v1.2.0

Fix

(#1183) Implement read-first memory behavior in Verilog
Implement read-first memories in VerilogMemDelays
Add read-under-write checks for memory emission
Improve read-under-write parameter support

(#1192) Restore ResolveGenders to its status as a Pass

Feature

(#1186) Absorb some instance analysis into InstanceGraph, use safer boxed Strings

(#1187) Bump sbt to 1.3.2

(#1188) [RFC] Define read-write collison for independently clocked mem ports

(#1189) Add explicit hline instead of phantom h1

(#1197) Add Block factory from argument list of Statements

(#1199) Make TopWiringTransform Idempotent
Add test for TopWiringTransform idempotency