Update tests that depend on source paths

chipsalliance · Jan 21, 2025 · aabc197 · aabc197
1 parent 86daa7f
commit aabc197
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Showing 7 changed files with 11 additions and 11 deletions.
diff --git a/src/test/scala-2/chiselTests/PortSpec.scala b/src/test/scala-2/chiselTests/PortSpec.scala
@@ -23,8 +23,8 @@ class PortSpec extends ChiselFreeSpec {
     chirrtl should include("input reset : UInt<1>")
     // other ports get source locators
     chirrtl should include(
-      "output in : { flip foo : UInt<1>, flip bar : UInt<8>} @[src/test/scala/chiselTests/PortSpec.scala"
+      "output in : { flip foo : UInt<1>, flip bar : UInt<8>} @[src/test/scala-2/chiselTests/PortSpec.scala"
     )
-    chirrtl should include("output out : UInt<1> @[src/test/scala/chiselTests/PortSpec.scala")
+    chirrtl should include("output out : UInt<1> @[src/test/scala-2/chiselTests/PortSpec.scala")
   }
 }
diff --git a/src/test/scala-2/chiselTests/SourceLocatorSpec.scala b/src/test/scala-2/chiselTests/SourceLocatorSpec.scala
@@ -9,7 +9,7 @@ import chisel3.experimental.hierarchy.Definition
 import firrtl.ir.FileInfo
 
 object SourceLocatorSpec {
-  val thisFile = "src/test/scala/chiselTests/SourceLocatorSpec.scala"
+  val thisFile = "src/test/scala-2/chiselTests/SourceLocatorSpec.scala"
 
   class RawModuleChild extends RawModule
   class ModuleChild extends Module
@@ -46,7 +46,7 @@ class SourceLocatorSpec extends ChiselFunSpec with Utils {
         val w = WireInit(UInt(1.W), 0.U)
       }
       val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Top)
-      chirrtl should include("@[src/test/scala/chiselTests/SourceLocatorSpec.scala")
+      chirrtl should include("@[src/test/scala-2/chiselTests/SourceLocatorSpec.scala")
     }
   }
 

diff --git a/src/test/scala-2/chiselTests/TypeAliasSpec.scala b/src/test/scala-2/chiselTests/TypeAliasSpec.scala
@@ -245,7 +245,7 @@ class TypeAliasSpec extends ChiselFlatSpec with Utils {
       "Attempted to redeclare an existing type alias 'DifferentBundle' with a new Record structure"
     )
     msg should include("The alias was previously defined as:")
-    msg should include("@[src/test/scala/chiselTests/TypeAliasSpec.scala")
+    msg should include("@[src/test/scala-2/chiselTests/TypeAliasSpec.scala")
   }
 
   "Bundles with unsanitary names" should "properly sanitize" in {

diff --git a/src/test/scala-2/chiselTests/properties/PropertySpec.scala b/src/test/scala-2/chiselTests/properties/PropertySpec.scala
@@ -787,7 +787,7 @@ class PropertySpec extends ChiselFlatSpec with FileCheck {
     }))
 
     e.getMessage should include(
-      "Property expressions are currently only supported in RawModules @[src/test/scala/chiselTests/properties/PropertySpec.scala"
+      "Property expressions are currently only supported in RawModules @[src/test/scala-2/chiselTests/properties/PropertySpec.scala"
     )
   }
 
@@ -876,7 +876,7 @@ class PropertySpec extends ChiselFlatSpec with FileCheck {
     }))
 
     e.getMessage should include(
-      "Property expressions are currently only supported in RawModules @[src/test/scala/chiselTests/properties/PropertySpec.scala"
+      "Property expressions are currently only supported in RawModules @[src/test/scala-2/chiselTests/properties/PropertySpec.scala"
     )
   }
 

diff --git a/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala b/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala
@@ -91,7 +91,7 @@ class SimulatorSpec extends AnyFunSpec with Matchers {
       }
       thrown.getMessage must include("Observed value '12' != 5.")
       (thrown.getMessage must include).regex(
-        """ @\[src/test/scala/chiselTests/simulator/SimulatorSpec\.scala:\d+:\d+\]"""
+        """ @\[src/test/scala-2/chiselTests/simulator/SimulatorSpec\.scala:\d+:\d+\]"""
       )
       thrown.getMessage must include("gcd.io.result.expect(5)")
       thrown.getMessage must include("                    ^")

diff --git a/src/test/scala-2/chiselTests/stage/WarningConfigurationSpec.scala b/src/test/scala-2/chiselTests/stage/WarningConfigurationSpec.scala
@@ -163,7 +163,7 @@ class WarningConfigurationSpec extends AnyFunSpec with Matchers with chiselTests
 
       info("including when rooted")
       val args3 =
-        Array("--warn-conf", "src=src/test/scala/**/WarningConfigurationSpec.scala:s,any:e", "--throw-on-first-error")
+        Array("--warn-conf", "src=src/test/scala-2/**/WarningConfigurationSpec.scala:s,any:e", "--throw-on-first-error")
       ChiselStage.emitCHIRRTL(new ModuleWithWarning, args3)
     }
 

diff --git a/src/test/scala-2/circtTests/stage/ChiselStageSpec.scala b/src/test/scala-2/circtTests/stage/ChiselStageSpec.scala
@@ -593,7 +593,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.Utils {
       val lines = stdout.split("\n")
       // Fuzzy includes aren't ideal but there is ANSI color in these strings that is hard to match
       lines(0) should include(
-        "src/test/scala/circtTests/stage/ChiselStageSpec.scala 97:9: Negative shift amounts are illegal (got -1)"
+        "src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 97:9: Negative shift amounts are illegal (got -1)"
       )
       lines(1) should include("    3.U >> -1")
       lines(2) should include("        ^")
@@ -614,7 +614,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.Utils {
       // Fuzzy includes aren't ideal but there is ANSI color in these strings that is hard to match
       lines.size should equal(2)
       lines(0) should include(
-        "src/test/scala/circtTests/stage/ChiselStageSpec.scala 97:9: Negative shift amounts are illegal (got -1)"
+        "src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 97:9: Negative shift amounts are illegal (got -1)"
       )
       (lines(1) should not).include("3.U >> -1")
     }