arch/esp32s3_wdt: ESP32-S3 WDT1 clock init

[nuttxs]

Summary

arch/esp32s3_wdt: ESP32-S3 WDT & TIMER adds clock enable and reset operations in the initial section

Impact

Only esp32s3 TIMERGROUP0 & 1

Testing

Enable esp32s3 wdt & timer

[tmedicci]

Hi @nuttxs , we have been testing watchdog operation on our internal CI without any issues. Can you please describe what problem you are trying to solve?

@eren-terzioglu , can you follow this discussion, please?

[nuttxs]

Hi @nuttxs , we have been testing watchdog operation on our internal CI without any issues. Can you please describe what problem you are trying to solve?

@eren-terzioglu , can you follow this discussion, please?
Hi @tmedicci
This commit refers to PR#5616, “Enable Timer Groups clocks on timer initialization.” In our internal test cases, when using WDT1, we occasionally encounter a crash similar to the following:

The refined PR has been updated; please help review. Thank you.

[eren-terzioglu]

Hi @nuttxs , we have been testing watchdog operation on our internal CI without any issues. Can you please describe what problem you are trying to solve?
@eren-terzioglu , can you follow this discussion, please?
Hi @tmedicci
This commit refers to PR#5616, “Enable Timer Groups clocks on timer initialization.” In our internal test cases, when using WDT1, we occasionally encounter a crash similar to the following:

The refined PR has been updated; please help review. Thank you.

Hi,

Could you give some information about your tests to reproduce the issue? We can test it for other chips to have better support about WDTs.

[nuttxs]

Could you give some information about your tests to reproduce the issue? We can test it for other chips to have better support about WDTs.

Hi @eren-terzioglu
We internally tested a part by referring to the timer implementation, enabling both wdt0 & wdt1 and setting them to bind to different CPUs. One is set to trigger at a slightly earlier time point to generate an interrupt, and the other is set to trigger at a more delayed time point to produce a WDT reset. The issue can be reproduced with the esp32s3-devkit:timer, and the attachment (
timer.log
)contains the complete log.

[eren-terzioglu]

Could you give some information about your tests to reproduce the issue? We can test it for other chips to have better support about WDTs.

Hi @eren-terzioglu We internally tested a part by referring to the timer implementation, enabling both wdt0 & wdt1 and setting them to bind to different CPUs. One is set to trigger at a slightly earlier time point to generate an interrupt, and the other is set to trigger at a more delayed time point to produce a WDT reset. The issue can be reproduced with the esp32s3-devkit:timer, and the attachment ( timer.log )contains the complete log.

I will test it as soon as possible, thanks for informing.

[eren-terzioglu]

Hello,

I tested but couldn't reproduce it properly. I used esp32s3-devkit:timer configuration with enabling ESP32S3_MWDT0 and ESP32S3_MWDT1 and then run timer -d /dev/timer1 for multiple times but seems it is working fine.
Also you are trying to enable TIMER_GROUP1 peripheral which should be enabled for CONFIG_ESP32S3_TIMER2 and CONFIG_ESP32S3_TIMER3 according to technical reference manual

Last but not least, seems the code you are doing was already implemented there. The code in esp32s3_tim.c is enabling TIMER_GROUP1 in TIMER_GROUP0 peripheral timer which should not make sense in action (in theory).