Merge pull request #150 from mithro/4mcmaster

Produce valid bitstreams for iCE40 architecture
antmicro · Jul 3, 2018 · dd77600 · dd77600
2 parents 8c8204c + e5eccf0
commit dd77600
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Showing 138 changed files with 6,820 additions and 4,424 deletions.
diff --git a/.gitignore b/.gitignore
@@ -23,3 +23,11 @@ env
 
 # Unused stuff
 *unused*
+
+# VPR output
+*.rpt
+*.echo
+*.net
+*.place
+*.route
+*.hlc
diff --git a/.gitmodules b/.gitmodules
@@ -4,3 +4,6 @@
 [submodule "third_party/prjxray-db"]
 	path = third_party/prjxray-db
 	url = https://github.com/SymbiFlow/prjxray-db.git
+[submodule "third_party/icestorm"]
+	path = third_party/icestorm
+	url = https://github.com/cliffordwolf/icestorm.git
diff --git a/tests/wire.eblif → common/wire.eblif b/tests/wire.eblif → common/wire.eblif
diff --git a/ice40/cells/ff/ff.interconnect.xml b/ice40/cells/ff/ff.interconnect.xml
diff --git a/ice40/cells/ff/ff.ports.xml b/ice40/cells/ff/ff.ports.xml
diff --git a/ice40/cells/ff_array/ff_array.interconnect.xml b/ice40/cells/ff_array/ff_array.interconnect.xml
diff --git a/ice40/cells/ff_array/ff_array.pb_type.xml b/ice40/cells/ff_array/ff_array.pb_type.xml
diff --git a/ice40/cells/io_local/io_local.pb_type.xml b/ice40/cells/io_local/io_local.pb_type.xml
@@ -1,40 +1,44 @@
 <!-- set: ai sw=1 ts=1 sta et -->
 <pb_type name="BLK_IG-IO_LOCAL" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
  <!-- SB_IO inputs -->
- <output name="io_0_D_IN" num_pins="2" equivalent="false"/>
- <output name="io_1_D_IN" num_pins="2" equivalent="false"/>
+ <output name="io_0_D_IN"       num_pins="2"/>
+ <output name="io_1_D_IN"       num_pins="2"/>
 
  <!-- SB_IO outputs -->
- <input name="io_0_D_OUT" num_pins="2" equivalent="false"/>
- <input name="io_1_D_OUT" num_pins="2" equivalent="false"/>
+ <input name="io_0_D_OUT"       num_pins="2"/>
+ <input name="io_1_D_OUT"       num_pins="2"/>
 
  <!-- Control signals -->
- <input name="io_0_OUT_ENB" num_pins="1" equivalent="false"/>
- <input name="io_1_OUT_ENB" num_pins="1" equivalent="false"/>
-
- <input name="io_global_cen"    num_pins="1" equivalent="false"/>
- <clock name="io_global_inclk"  num_pins="1" equivalent="false"/>
- <clock name="io_global_outclk" num_pins="1" equivalent="false"/>
- <input name="io_global_latch"  num_pins="1" equivalent="false"/>
- 
+ <input name="io_0_OUT_ENB"     num_pins="1"/>
+ <input name="io_1_OUT_ENB"     num_pins="1"/>
+
+ <input name="io_global_cen"    num_pins="1"/>
+ <clock name="io_global_inclk"  num_pins="1"/>
+ <clock name="io_global_outclk" num_pins="1"/>
+ <input name="io_global_latch"  num_pins="1"/>
+
  <pb_type name="BLK_IG-IO" num_pb="2">
   <xi:include href="../../primitives/sb_io/sb_io.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/>
  </pb_type>
 
  <interconnect>
-  <direct name="io_0_D_IN" input="BLK_IG-IO[0].D_IN" output="BLK_IG-IO_LOCAL.io_0_D_IN"/>
-  <direct name="io_1_D_IN" input="BLK_IG-IO[1].D_IN" output="BLK_IG-IO_LOCAL.io_1_D_IN"/>
+  <direct name="io_0_D_IN"         input="BLK_IG-IO[0].D_IN"                output="BLK_IG-IO_LOCAL.io_0_D_IN" />
+  <direct name="io_1_D_IN"         input="BLK_IG-IO[1].D_IN"                output="BLK_IG-IO_LOCAL.io_1_D_IN" />
 
-  <direct name="io_0_D_OUT" input="BLK_IG-IO_LOCAL.io_0_D_OUT" output="BLK_IG-IO[0].D_OUT"/>
-  <direct name="io_1_D_OUT" input="BLK_IG-IO_LOCAL.io_1_D_OUT" output="BLK_IG-IO[1].D_OUT"/>
+  <direct name="io_0_D_OUT"        input="BLK_IG-IO_LOCAL.io_0_D_OUT"       output="BLK_IG-IO[0].D_OUT"        />
+  <direct name="io_1_D_OUT"        input="BLK_IG-IO_LOCAL.io_1_D_OUT"       output="BLK_IG-IO[1].D_OUT"        />
 
-  <direct name="io_0_OUT_ENB" input="BLK_IG-IO_LOCAL.io_0_OUT_ENB" output="BLK_IG-IO[0].OUT_ENB"/>
-  <direct name="io_1_OUT_ENB" input="BLK_IG-IO_LOCAL.io_1_OUT_ENB" output="BLK_IG-IO[1].OUT_ENB"/>
+  <direct name="io_0_OUT_ENB"      input="BLK_IG-IO_LOCAL.io_0_OUT_ENB"     output="BLK_IG-IO[0].OUT_ENB"      />
+  <direct name="io_1_OUT_ENB"      input="BLK_IG-IO_LOCAL.io_1_OUT_ENB"     output="BLK_IG-IO[1].OUT_ENB"      />
 
-  <complete name="io_global_cen"    input="BLK_IG-IO_LOCAL.io_global_cen"    output="BLK_IG-IO.io_global_cen"/>
-  <complete name="io_global_inclk"  input="BLK_IG-IO_LOCAL.io_global_inclk"  output="BLK_IG-IO.io_global_inclk"/>
-  <complete name="io_global_outclk" input="BLK_IG-IO_LOCAL.io_global_outclk" output="BLK_IG-IO.io_global_outclk"/>
-  <complete name="io_global_latch"  input="BLK_IG-IO_LOCAL.io_global_latch"  output="BLK_IG-IO.io_global_latch"/>
+  <direct name="io_global_cen0"    input="BLK_IG-IO_LOCAL.io_global_cen"    output="BLK_IG-IO[0].CEN"          />
+  <direct name="io_global_cen1"    input="BLK_IG-IO_LOCAL.io_global_cen"    output="BLK_IG-IO[1].CEN"          />
+  <direct name="io_global_inclk0"  input="BLK_IG-IO_LOCAL.io_global_inclk"  output="BLK_IG-IO[0].INCLK"        />
+  <direct name="io_global_inclk1"  input="BLK_IG-IO_LOCAL.io_global_inclk"  output="BLK_IG-IO[1].INCLK"        />
+  <direct name="io_global_outclk0" input="BLK_IG-IO_LOCAL.io_global_outclk" output="BLK_IG-IO[0].OUTCLK"       />
+  <direct name="io_global_outclk1" input="BLK_IG-IO_LOCAL.io_global_outclk" output="BLK_IG-IO[1].OUTCLK"       />
+  <direct name="io_global_latch0"  input="BLK_IG-IO_LOCAL.io_global_latch"  output="BLK_IG-IO[0].LATCH"        />
+  <direct name="io_global_latch1"  input="BLK_IG-IO_LOCAL.io_global_latch"  output="BLK_IG-IO[1].LATCH"        />
  </interconnect>
- 
+
 </pb_type>
diff --git a/ice40/cells/lut_carry/lut_carry.pb_type.xml b/ice40/cells/lut_carry/lut_carry.pb_type.xml
diff --git a/ice40/cells/lutff/lutff.pb_type.xml b/ice40/cells/lutff/lutff.pb_type.xml
@@ -0,0 +1,95 @@
+<!-- set: ai sw=1 ts=1 sta et -->
+<pb_type name="BLK_IG-LUTFF" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
+ <!-- LUT -->
+ <input  name="I"     num_pins="4"/>
+
+ <input  name="LCIN"  num_pins="1"/>
+ <output name="LCOUT" num_pins="1"/>
+
+ <!-- FF -->
+ <clock  name="PCLK"  num_pins="1"/>
+ <clock  name="NCLK"  num_pins="1"/>
+ <input  name="EN"    num_pins="1"/>
+ <input  name="SR"    num_pins="1"/>
+ <output name="O"     num_pins="1"/>
+
+ <!-- CARRY -->
+ <input  name="FCIN"  num_pins="1"/>
+ <output name="FCOUT" num_pins="1"/>
+
+ <xi:include href="../../primitives/sb_lut/sb_lut.pb_type.xml"/>
+ <xi:include href="../../primitives/sb_carry/sb_carry.pb_type.xml"/>
+ <xi:include href="../../primitives/sb_ff/sb_ff.pb_type.xml"/>
+
+ <pb_type name="BLK_IG-ENABLE_FF" num_pb="1">
+  <input  name="I" num_pins="1"/>
+  <output name="O" num_pins="1"/>
+  <interconnect>
+   <direct name="I" input="BLK_IG-ENABLE_FF.I" output="BLK_IG-ENABLE_FF.O" />
+  </interconnect>
+  <metadata>
+   <meta name="hlc_property">enable_dff</meta>
+  </metadata>
+ </pb_type>
+ <pb_type name="BLK_IG-DISABLE_FF" num_pb="1">
+  <input  name="I" num_pins="1"/>
+  <output name="O" num_pins="1"/>
+  <interconnect>
+   <direct name="I" input="BLK_IG-DISABLE_FF.I" output="BLK_IG-DISABLE_FF.O" />
+  </interconnect>
+  <metadata>
+   <meta name="hlc_property"># disable_dff</meta>
+  </metadata>
+ </pb_type>
+
+ <interconnect>
+  <!-- LUT -->
+  <direct name="LUT.I[0]" input="BLK_IG-LUTFF.I[0]"                      output="BEL_LT-LUT.in[0]" />
+  <direct name="LUT.I[1]" input="BLK_IG-LUTFF.I[1]"                      output="BEL_LT-LUT.in[1]" />
+  <mux    name="LUT.I[2]" input="BLK_IG-LUTFF.LCIN[0] BLK_IG-LUTFF.I[2]" output="BEL_LT-LUT.in[2]" />
+  <!-- Disable FCIN->I3 mux until https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325 is fixed.
+  <mux    name="LUT.I[3]" input="BLK_IG-LUTFF.I[3] BLK_IG-LUTFF.FCIN" output="BEL_LT-LUT.in[3]" /> -->
+  <direct name="LUT.I[3]" input="BLK_IG-LUTFF.I[3]"                      output="BEL_LT-LUT.in[3]" />
+  <direct name="LCOUT"    input="BEL_LT-LUT.out"                         output="BLK_IG-LUTFF.LCOUT" />
+
+  <!-- LUT -->
+  <direct name="FF.C[0]"  input="BLK_IG-LUTFF.PCLK" output="BEL_FF-SB_FF.C" />
+  <direct name="FF.N[0]"  input="BLK_IG-LUTFF.NCLK" output="BEL_FF-SB_FF.N" />
+  <direct name="FF.E[0]"  input="BLK_IG-LUTFF.EN"   output="BEL_FF-SB_FF.E" />
+  <direct name="FF.R[0]"  input="BLK_IG-LUTFF.SR"   output="BEL_FF-SB_FF.R" />
+  <direct name="FF.S[0]"  input="BLK_IG-LUTFF.SR"   output="BEL_FF-SB_FF.S" />
+  <direct name="FF.D[0]"  input="BEL_LT-LUT.out"    output="BEL_FF-SB_FF.D"  >
+   <pack_pattern name="LUT+FF" in_port="BEL_LT-LUT.out" out_port="BEL_FF-SB_FF.D" />
+  </direct>
+
+  <direct name="DISABLE_FF" input="BEL_LT-LUT.out" output="BLK_IG-DISABLE_FF.I" />
+  <direct name="ENABLE_FF"  input="BEL_FF-SB_FF.Q" output="BLK_IG-ENABLE_FF.I"  />
+  <!-- Output -->
+  <mux name="O" input="BLK_IG-DISABLE_FF.O BLK_IG-ENABLE_FF.O" output="BLK_IG-LUTFF.O" />
+
+  <!--
+  <direct name="OMUX.LT" input="BLK_IG-ENABLE_FF.O"  output="BEL_RX-RMUX2.LT" />
+  <direct name="OMUX.FF" input="BLK_IG-DISABLE_FF.O" output="BEL_RX-RMUX2.FF" />
+  <direct name="OMUX.O"  input="BEL_RX-RMUX2.O"      output="BLK_IG-LUTFF.O" />
+       -->
+
+  <!-- CARRY -->
+  <direct name="SB_CARRY.I0" input="BLK_IG-LUTFF.I[1]" output="SB_CARRY.I0" />
+  <direct name="SB_CARRY.I1" input="BLK_IG-LUTFF.I[2]" output="SB_CARRY.I1" />
+
+  <direct name="BLK_IG-LUTFF.FCIN" input="BLK_IG-LUTFF.FCIN" output="SB_CARRY.CI">
+   <pack_pattern name="CARRYCHAIN" in_port="BLK_IG-LUTFF.FCIN" out_port="SB_CARRY.CI" />
+  </direct>
+  <direct name="BLK_IG-LUTFF.FCOUT" input="SB_CARRY.CO" output="BLK_IG-LUTFF.FCOUT">
+   <pack_pattern name="CARRYCHAIN" in_port="SB_CARRY.CO" out_port="BLK_IG-LUTFF.FCOUT" />
+  </direct>
+  <!--
+  <direct name="BLK_IG-LUTFF.FCIN" input="BLK_IG-LUTFF.FCIN" output="SB_CARRY.CI" />
+  <direct name="BLK_IG-LUTFF.FCOUT" input="SB_CARRY.CO" output="BLK_IG-LUTFF.FCOUT" />
+  -->
+
+ </interconnect>
+ <metadata>
+  <meta name="hlc_cell">lutff</meta>
+ </metadata>
+</pb_type>