Add HDL RegMap writer and HDL Generator CLI #6
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Write the register maps into SystemVerilog, to be used in testbenches. Add CLI hdl-gen to call the writer and execute on all hdl/docs/regmap files. Signed-off-by: Jorge Marques <[email protected]>
Better organization. Some methods could be wrapped in classes, however. Signed-off-by: Jorge Marques <[email protected]>
Try to parse default field value as int. In the writer/hdl.py, if the value is a string, set it as 'hXX. Signed-off-by: Jorge Marques <[email protected]>
Default to None when unset, or error parsing. Signed-off-by: Jorge Marques <[email protected]>
Test HDL regmap parser, resolve, expansion and writer. Add tests CI with pytest Signed-off-by: Jorge Marques <[email protected]>
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