SV files generation (#31)

SV files generation: Added test files creation

- Creates a testbench that includes all generated regmap files
- Creates bash script to run simulation
- Moved from parameterized classes to parameterization at creation
- Added missing reset value locking mechanism
- Added parameter definiton header file creation together with the regmaps
- Created arrays of repeating registers with calculated addressing

Signed-off-by: Istvan-Zsolt Szekely <[email protected]>

adi_doctools/cli/hdl_gen.py

@@ -17,6 +17,7 @@
 from ..parser.hdl import resolve_hdl_project
 from ..parser.hdl import parse_hdl_interfaces
 from ..writer.hdl import write_hdl_regmap
+from ..writer.hdl import write_hdl_regmap_test
 from ..writer.hdl import write_hdl_library_makefile
 from ..writer.hdl import write_hdl_project_makefile
 
@@ -204,6 +205,7 @@ def regmap_pre() -> Dict:
 
 
 def regmap_post(rm: Dict) -> None:
-    f_ = path.join('testbenches', 'common', 'sv')
+    f_ = path.join('testbenches', 'library', 'regmaps')
     for m in rm:
         write_hdl_regmap(f_, rm[m]['subregmap'], m)
+    write_hdl_regmap_test(f_, rm)