Set M 2023b and V 2023.2

analogdevicesinc · Jan 27, 2025 · 8aa7222 · 8aa7222
1 parent a9d5395
commit 8aa7222
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Showing 9 changed files with 14 additions and 13 deletions.
diff --git a/+adi/Version.m b/+adi/Version.m
@@ -2,8 +2,8 @@
     % Version
     %   BSP Version information
     properties (Constant)
-        Vivado = '2022.2'
-        MATLAB = 'R2022a'
+        Vivado = getenv('req_vivado_v')
+        MATLAB = getenv('req_matlab_v') 
         Release = '21.2.1'
         AppName = 'Analog Devices, Inc. Precision Toolbox'
         ToolboxName = 'PrecisionToolbox'

diff --git a/CI/scripts_hdl/matlab_processors.tcl b/CI/scripts_hdl/matlab_processors.tcl
@@ -47,9 +47,9 @@ proc preprocess_bd {project carrier rxtx} {
 	    }
 	  switch $carrier {
           zed {
-                set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
-                connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK]    [get_bd_pins axi_clkgen/clk_0]
-                connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
+                set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_gp0_interconnect]
+                connect_bd_net [get_bd_pins axi_gp0_interconnect/M20_ACLK]    [get_bd_pins axi_clkgen/clk_0]
+                connect_bd_net [get_bd_pins axi_gp0_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
               }
           }
         }

diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m b/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m
@@ -5,7 +5,7 @@
    case 'cn0585'
         switch fpga
             case{'ZED'}
-                InterfaceConnection = 'axi_cpu_interconnect/M20_AXI';
+                InterfaceConnection = 'axi_gp0_interconnect/M20_AXI';
                 BaseAddress = '0x43C00000';
                 MasterAddressSpace = 'sys_ps7/Data';
             otherwise

diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m
@@ -20,7 +20,7 @@
 hRD.BoardName = sprintf('AnalogDevices %s %s', pname, upper(board));
 
 % Tool information
-hRD.SupportedToolVersion = {'2022.2'};
+hRD.SupportedToolVersion = {'2023.2'};
 
 % Get the root directory
 rootDir = fileparts(strtok(mfilename('fullpath'), '+'));

diff --git a/.../targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m b/.../targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m
@@ -21,7 +21,7 @@
 hRD.BoardName = sprintf('AnalogDevices CN0585 GPIO Control');
 
 % Tool information
-hRD.SupportedToolVersion = {'2023.2'};
+hRD.SupportedToolVersion = {getenv('req_vivado_v')};
 
 % Get the root directories
 rootDirExample = fileparts(strtok(mfilename('fullpath'), '+'));

diff --git a/...targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m b/...targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m
@@ -2,7 +2,7 @@ function add_tx_io(hRD)
 
 % add AXI4 and AXI4-Lite slave interfaces
 hRD.addAXI4SlaveInterface( ...
-    'InterfaceConnection', 'axi_cpu_interconnect/M20_AXI', ...
+    'InterfaceConnection', 'axi_gp0_interconnect/M20_AXI', ...
     'BaseAddress',         '0x43C00000', ...
     'MasterAddressSpace',  'sys_ps7/Data');
 

diff --git a/pcx_examples/targeting/cn0585/cn0585_hdl/build_bsp.sh b/pcx_examples/targeting/cn0585/cn0585_hdl/build_bsp.sh
@@ -44,8 +44,7 @@ fi
 VIVADO=${VER}
 
 # Setup
-#source /opt/Xilinx/Vivado/$VIVADO/settings64.sh
-source /emea/mediadata/opt/Xilinx/Vivado/$VIVADO/settings64.sh
+source "$vivado_settings_path"
 
 # Rename .prj files since MATLAB ignores then during packaging
 FILES=$(grep -lrn hdl/projects/common -e '.prj' | grep -v Makefile | grep -v .git)

diff --git a/test/BSPTestsBase.m b/test/BSPTestsBase.m
@@ -161,6 +161,8 @@ function setVivadoPath(~,vivado)
                     pathname = ['C:\Xilinx\Vivado\',vivado,'\bin\vivado.bat'];
                 elseif isunix
                     pathname = ['/emea/mediadata/opt/Xilinx/Vivado/',vivado,'/bin/vivado'];
+                    %pathname = ['/opt/Xilinx/Vivado/',vivado,'/bin/vivado'];
+		    %pathname = getenv('vivado_settings_path');
                 end
             end
             assert(exist(pathname,'file')>0,'Correct version of Vivado is unavailable or in a non-standard location');
@@ -203,4 +205,4 @@ function testMain(testCase, configs, SynthesizeDesign)
             end
         end
     end
-end
+end
diff --git a/test/build_design.m b/test/build_design.m
@@ -29,7 +29,7 @@
 
 % Specify the top level project directory
 hWC.ProjectFolder = folder;
-hWC.ReferenceDesignToolVersion = '2023.2';
+hWC.ReferenceDesignToolVersion = getenv('req_vivado_v');
 hWC.IgnoreToolVersionMismatch = true;
 hWC.AllowUnsupportedToolVersion = true;