ci: markdownlint

TheMightyDuckOfDoom · May 8, 2024 · f9286ce · f9286ce
1 parent 7886bd1
commit f9286ce
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Showing 3 changed files with 18 additions and 2 deletions.
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -50,6 +50,14 @@ jobs:
       - name: Run veriloglint
         run: make veriloglint
 
+  markdownlint:
+    runs-on: self-hosted
+    needs: setup
+    steps:
+      - uses: actions/checkout@v4
+      - name: Run markdownlint
+        run: make markdownlint
+
   basic_tests:
     runs-on: self-hosted
     needs: setup

diff --git a/Makefile b/Makefile
@@ -20,6 +20,7 @@ YAML_FILES := $(shell find ./ -name '*.yml')
 JSON_FILES := $(shell find ./ -name '*.json')
 VERILOG_FILES := $(shell find ./ -name '*.v')
 SVERILOG_FILES := $(shell find ./ -name '*.sv')
+MARKDOWN_FILES := $(shell find ./ -name '*.md')
 
 # Get File Names
 TCL_FILE_NAME := $(basename $(TCL_FILES))
@@ -28,8 +29,9 @@ YAML_FILE_NAME := $(basename $(YAML_FILES))
 JSON_FILE_NAME := $(basename $(JSON_FILES))
 VERILOG_FILE_NAME := $(basename $(VERILOG_FILES))
 SVERILOG_FILE_NAME := $(basename $(SVERILOG_FILES))
+MARKDOWN_FILE_NAME := $(basename $(MARKDOWN_FILES))
 
-.PHONY: all clean lint yamllint tclint pylint jsonlint veriloglint
+.PHONY: all clean lint yamllint tclint pylint jsonlint veriloglint markdownlint
 
 all: gen_pdk
 
@@ -96,13 +98,14 @@ pcb: gen_pdk
 open_pcb:
 	pcbnew out/${PROJECT}.final.kicad_pcb
 
-lint: yamllint tclint jsonlint veriloglint pylint
+lint: yamllint tclint jsonlint veriloglint pylint markdownlint
 
 yamllint: $(YAML_FILE_NAME)
 tclint: $(TCL_FILE_NAME)
 pylint: $(PY_FILE_NAME)
 jsonlint: $(JSON_FILE_NAME)
 veriloglint: $(VERILOG_FILE_NAME) $(SVERILOG_FILE_NAME)
+markdownlint: $(MARKDOWN_FILE_NAME)
 
 $(YAML_FILE_NAME): $(YAML_FILES)
 	yamllint --no-warnings $@.yml
@@ -122,6 +125,9 @@ $(VERILOG_FILE_NAME): $(VERILOG_FILES)
 $(SVERILOG_FILE_NAME): $(SVERILOG_FILES)
 	verible-verilog-lint $(VERIBLE_FLAGS) $@.sv
 
+$(MARKDOWN_FILE_NAME): $(MARKDOWN_FILES)
+	mdl $@.md
+
 clean:
 	rm -rf .setup
 	rm -rf out

diff --git a/Readme.md b/Readme.md
@@ -3,3 +3,5 @@
 [![CI status](https://github.com/TheMightyDuckOfDoom/liberty74/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/TheMightyDuckOfDoom/liberty74/actions)
 
 Liberty74 is a fully open-source Verilog-to-PCB Flow.
+
+TODO: Documentation
Original file line number	Diff line number	Diff line change
Expand Up		@@ -3,3 +3,5 @@
		[![CI status](https://github.com/TheMightyDuckOfDoom/liberty74/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/TheMightyDuckOfDoom/liberty74/actions)

		Liberty74 is a fully open-source Verilog-to-PCB Flow.

		TODO: Documentation