Handle Illegal RVC Instructions and Mask Upper Bits in mtval for RVC Traps #120
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…its for RVC traps mtval
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Thanks ^^ I will port is to VexiiRiscv aswell :D |
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Dolu1990
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Aug 5, 2024
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Implemented handling of masking upper bits in mtval for RVC traps and added non-zero checks for RD/RS registers and immediate values in compressed instructions. Here is the list of instructions with the associated checks: