Updating the memory mapping for SocDemo

SpinalHDL · Jul 16, 2024 · a0bd8ed · a0bd8ed
1 parent ba63ee6
commit a0bd8ed
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala b/src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala
@@ -75,7 +75,7 @@ class SocDemo(cpuCount : Int, withL2 : Boolean = true, asic : Boolean = false, x
         )
       )
     )
-    emulated.node at(0, 0x1000) of bus
+    emulated.node at(0, 0x10000000) of bus
 
     val custom = Fiber build new Area{
       val mei,sei = in Bool()