Got icarus verilator to run asic config dhrystone simulation

SpinalHDL · Jan 16, 2024 · 9fb1618 · 9fb1618
1 parent 942825a
commit 9fb1618
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Showing 4 changed files with 21 additions and 18 deletions.
diff --git a/ext/riscv-isa-sim b/ext/riscv-isa-sim
diff --git a/ext/rvls b/ext/rvls
diff --git a/src/main/scala/naxriscv/misc/RegFilePlugin.scala b/src/main/scala/naxriscv/misc/RegFilePlugin.scala
@@ -157,35 +157,37 @@ class RegFileLatch(addressWidth    : Int,
       val mask = B(io.writes.map(port => port.valid && port.address === i))
       val maskReg = LatchWhen(mask, writeFrontend.clock)
       val validReg = LatchWhen(mask.orR, writeFrontend.clock)
-//      val maskReg = RegNext(mask)
-//      val validReg = RegNext(mask.orR)
       val data = OhMux.or(maskReg, writeFrontend.buffers)
+      val sample = !writeFrontend.clock && validReg
     }
 
-//    val storages = Array.fill(dataWidth)(new sky130_fd_sc_hd__dlxtp_1)
-//    val GATE = !writeFrontend.clock && write.validReg
-//    for((s, i) <- storages.zipWithIndex){
-//      s.D := write.data(i)
-//      s.GATE := GATE
-//    }
-//    val storage = storages.map(_.Q).toSeq.asBits
-
-    val storage = LatchWhen(write.data, !writeFrontend.clock && write.validReg)
+    // Infered latch implementation
+    val storage = LatchWhen(write.data, write.sample)
+
+    // sky130_fd_sc_hd__dlxtp_1 latch implementation
+    //    val storages = Array.fill(dataWidth)(new sky130_fd_sc_hd__dlxtp_1)
+    //    val GATE = !writeFrontend.clock && write.validReg
+    //    for((s, i) <- storages.zipWithIndex){
+    //      s.D := write.data(i)
+    //      s.GATE := GATE
+    //    }
+    //    val storage = storages.map(_.Q).toSeq.asBits
   }
 
 
   val readLogic = for ((r, i) <- io.reads.zipWithIndex) yield new Area {
     var mem = latches.map(_.storage).toList
     if(headZero) mem = B(0, dataWidth bits) :: mem
 
+    // Tristate based mux implementation
     val oh = UIntToOh(r.address)
     val tri = Analog(Bits(dataWidth bits))
     mem.onMask(oh){ value =>
       tri := value
     }
     r.data := tri
 
-
+    // Regular mux implementation
 //    r.data := mem.read(r.address)
   }
 }

diff --git a/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala b/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala
@@ -73,9 +73,10 @@ object SocSim extends App {
 
 
   val sc = SimConfig
-  sc.normalOptimisation
-//  sc.withIVerilog
-//  sc.withFstWave
+//  sc.normalOptimisation
+  sc.withIVerilog
+//  sc.withWave
+  sc.withFstWave
   sc.withConfig(SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = ASYNC)).includeSimulation)
 //  sc.addSimulatorFlag("--threads 1")
 //  sc.addSimulatorFlag("--prof-exec")
@@ -140,7 +141,7 @@ object SocSim extends App {
   def testIt(dut : SocDemoSim, onTrace : (=> Unit) => Unit = cb => {}): Unit = {
     val cd = dut.clockDomain
     cd.forkStimulus(10)
-    // cd.forkSimSpeedPrinter(1.0)
+     cd.forkSimSpeedPrinter(1.0)
 
     // Connect the few peripherals
     val ma = new MemoryAgent(dut.mem.node.bus, cd, seed = 0, randomProberFactor = 0.2f)(null) {
+2 −1		README.md
+4 −0		bindings/jni/rvls/jni/Frontend.java
+203 −0		bindings/spinal/rvls/spinal/Tracer.scala
+20 −0		src/jni_frontend.cpp