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SpinalHDL · Dec 19, 2023 · 6af1a20 · 6af1a20
1 parent 6461e9f
commit 6af1a20
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Showing 3 changed files with 12 additions and 2 deletions.
diff --git a/src/main/scala/naxriscv/execute/BranchPlugin.scala b/src/main/scala/naxriscv/execute/BranchPlugin.scala
@@ -128,7 +128,7 @@ class BranchPlugin(val euId : String,
     val branch = new ExecuteArea(branchAt){
       import stage._
 
-      val badEarlyTaken  = if(setup.withBranchContext) BRANCH_EARLY.taken =/= COND              else CombInit(stage(COND))
+      val badEarlyTaken  = if(setup.withBranchContext) BRANCH_EARLY.taken =/= COND else CombInit(stage(COND))
       MISSPREDICTED := badEarlyTaken || COND && BAD_EARLY_TARGET
 
       def target = if(setup.withBranchContext)  stage(PC, "TARGET") else stage(PC, "TRUE")

diff --git a/src/main/scala/naxriscv/platform/PeripheralEmulator.scala b/src/main/scala/naxriscv/platform/PeripheralEmulator.scala
@@ -54,7 +54,7 @@ class PeripheralEmulator(bus : tilelink.Bus, mei : Bool, sei : Bool, cd : ClockD
         a.address.toInt match {
           case IO_FAULT_ADDRESS => {
             d.denied = true
-            Random.nextBytes(d.data)
+            simRandom.nextBytes(d.data)
           }
           case GETC => {
             if(System.in.available() != 0) {

diff --git a/src/test/scala/naxriscv/Rvls.scala b/src/test/scala/naxriscv/Rvls.scala
@@ -0,0 +1,10 @@
+package naxriscv
+
+object Rvls extends App{
+  import rvls.jni.Frontend
+
+  val handle = Frontend.newDisassemble(32)
+  println(Frontend.disassemble(handle, 0x03410793))
+  println(Frontend.disassemble(handle, 0x13))
+  Frontend.deleteDisassemble(handle)
+}