Merge pull request #205 from RapidRoger18/RV-project

[MINOR UPDATE]: Adds styling changes for ApexCore Project
SRA-VJTI · May 16, 2024 · 530262b · 530262b
2 parents 2e0a42c + b1fda91
commit 530262b
Show file tree

Hide file tree

Showing 2 changed files with 23 additions and 21 deletions.
diff --git a/_projects/ApexCore.md b/_projects/ApexCore.md
@@ -1,13 +1,14 @@
 ---
 layout: page
-title: ApexCore a Risc-V based CPU
-description: Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards.  
+title: ApexCore a RISC-V based CPU
+description: Developing a RISC-V based soft processor IP compatible with AMD's Xilinx Boards.  
 importance: 1
 ---
 
 | Project Domains                              | Mentors                         | Project Difficulty |
 |----------------------------------------------|---------------------------------|--------------------|
 | Computer Architecture, FPGA, Digital Design  | Atharva Kashalkar, Saish Karole | Hard               |
+
 <br>
 
 ### Project Description

diff --git a/_site/projects/ApexCore/index.html b/_site/projects/ApexCore/index.html
@@ -10,9 +10,9 @@
     <meta charset="utf-8">
     <meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no">
     <meta http-equiv="X-UA-Compatible" content="IE=edge">
-    <title>ApexCore a Risc-V based CPU | Eklavya 2024  </title>
+    <title>ApexCore a RISC-V based CPU | Eklavya 2024  </title>
     <meta name="author" content="Eklavya 2024  ">
-    <meta name="description" content="Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards.">
+    <meta name="description" content="Developing a RISC-V based soft processor IP compatible with AMD's Xilinx Boards.">
     <meta name="keywords" content="jekyll, jekyll-theme, academic-website, portfolio-website">
 
 
@@ -114,27 +114,28 @@
         <div class="post table-borderless">
 
           <header class="post-header">
-            <h1 class="post-title">ApexCore a Risc-V based CPU</h1>
-            <p class="post-description">Developing a Risc-V based soft processor IP compatible with AMD's Xilinx Boards.</p>
+            <h1 class="post-title">ApexCore a RISC-V based CPU</h1>
+            <p class="post-description">Developing a RISC-V based soft processor IP compatible with AMD's Xilinx Boards.</p>
           </header>
 
           <article>
             <table>
-              <thead>
-                <tr>
-                  <th>Project Domains</th>
-                  <th>Mentors</th>
-                  <th>Project Difficulty</th>
-                </tr>
-              </thead>
-              <tbody>
-                <tr>
-                  <td>Computer Architecture, FPGA, Digital Design</td>
-                  <td>Atharva Kashalkar, Saish Karole </td>
-                  <td>Hard</td>
-                </tr>
-              </tbody>
-            </table>            
+  <thead>
+    <tr>
+      <th>Project Domains</th>
+      <th>Mentors</th>
+      <th>Project Difficulty</th>
+    </tr>
+  </thead>
+  <tbody>
+    <tr>
+      <td>Computer Architecture, FPGA, Digital Design</td>
+      <td>Atharva Kashalkar, Saish Karole</td>
+      <td>Hard</td>
+    </tr>
+  </tbody>
+</table>
+
 <p><br></p>
 
 <h3 id="project-description">Project Description</h3>