Fix store whole register (#2479)

* UopQueue: fix nfields calculation overflow * VSUopQueue: fix isLastelem of store whole register
OpenXiangShan · Nov 20, 2023 · 8921891 · 8921891
1 parent 4956915
commit 8921891
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala b/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala
@@ -224,7 +224,7 @@ class VlUopQueue(implicit p: Parameters) extends VLSUModule
       x.stride := io.loadRegIn.bits.src_stride
       x.flow_counter := flows
       x.flowNum := flows
-      x.nfields := nf + 1.U
+      x.nfields := nf +& 1.U
       x.vm := vm
       x.usWholeReg := isUnitStride(mop) && us_whole_reg(fuOpType)
       x.usMaskReg := isUnitStride(mop) && us_mask(fuOpType)

diff --git a/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala b/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala
@@ -189,7 +189,7 @@ class VsUopQueue(implicit p: Parameters) extends VLSUModule {
       x.stride := io.storeIn.bits.src_stride
       x.flow_counter := flows
       x.flowNum := flows
-      x.nfields := nf + 1.U
+      x.nfields := nf +& 1.U
       x.vm := vm
       x.usWholeReg := isUnitStride(mop) && us_whole_reg(fuOpType)
       x.usMaskReg := isUnitStride(mop) && us_mask(fuOpType)
@@ -320,7 +320,7 @@ class VsUopQueue(implicit p: Parameters) extends VLSUModule {
         alignedType = issueAlignedType
       )
       x.uopQueuePtr := flowSplitPtr
-      x.isLastElem := (elemIdx +& 1.U) === (issueNFIELDS << issueVLMAXLog2)
+      x.isLastElem := (elemIdx +& 1.U) === Mux(issueEntry.usWholeReg, (issueNFIELDS << log2Up(VLENB)),(issueNFIELDS << issueVLMAXLog2))
     }
   }