feat: implement OR, AND, XOR

Kelvinyu1117 · Jun 8, 2024 · eaa9053 · eaa9053
1 parent fa14e3d
commit eaa9053
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diff --git a/arabica/cpu/cpu.cpp b/arabica/cpu/cpu.cpp
@@ -22,6 +22,9 @@ void CPU::run(const Memory& memory) {
     case 0x8000: {
       switch (instruction & 0x000F) {
         case 0x0: opcode = OP_CODE::LD_Vx_Vy; break;
+        case 0x1: opcode = OP_CODE::OR_Vx_Vy; break;
+        case 0x2: opcode = OP_CODE::AND_Vx_Vy; break;
+        case 0x3: opcode = OP_CODE::XOR_Vx_Vy; break;
         case 0x4: opcode = OP_CODE::ADD_Vx_Vy; break;
         default: break;
       }
@@ -67,6 +70,27 @@ void CPU::run(const Memory& memory) {
 
       advance_pc(pc);
     } break;
+    case OP_CODE::OR_Vx_Vy: {
+      uint8_t x = (instruction & 0x0F00) >> 8;
+      uint8_t y = (instruction & 0x00F0) >> 4;
+      registers[x] |= registers[y];
+
+      advance_pc(pc);
+    } break;
+    case OP_CODE::AND_Vx_Vy: {
+      uint8_t x = (instruction & 0x0F00) >> 8;
+      uint8_t y = (instruction & 0x00F0) >> 4;
+      registers[x] &= registers[y];
+
+      advance_pc(pc);
+    } break;
+    case OP_CODE::XOR_Vx_Vy: {
+      uint8_t x = (instruction & 0x0F00) >> 8;
+      uint8_t y = (instruction & 0x00F0) >> 4;
+      registers[x] ^= registers[y];
+
+      advance_pc(pc);
+    } break;
     case OP_CODE::ADD_Vx_Vy: {
       uint8_t x      = (instruction & 0x0F00) >> 8;
       uint8_t y      = (instruction & 0x00F0) >> 4;

diff --git a/test/cpu/cpu_test_suite.hpp b/test/cpu/cpu_test_suite.hpp
@@ -107,6 +107,81 @@ arabica_cpu_test(test_ld_vx_vy,
   }
 )
 
+arabica_cpu_test(test_or_vx_vy,
+   // LD V[0], 0x12
+  memory.write(0x200, 0x60);
+  memory.write(0x201, 0x12);
+  cpu.run(memory);
+  ASSERT_EQ(cpu.pc, 0x202);
+  ASSERT_EQ(cpu.registers[0], 0x12);
+
+
+  // LD V[1], 0x34
+  memory.write(0x202, 0x61);
+  memory.write(0x203, 0x34);
+  cpu.run(memory);
+  ASSERT_EQ(cpu.pc, 0x204);
+  ASSERT_EQ(cpu.registers[1], 0x34);
+
+
+  // OR V[0], V[1]
+  memory.write(0x204, 0x80);
+  memory.write(0x205, 0x11);
+  cpu.run(memory);
+  ASSERT_EQ(cpu.pc, 0x206);
+  ASSERT_EQ(cpu.registers[0], 0x36);
+)
+
+arabica_cpu_test(test_and_vx_vy,
+  // LD V[0], 0x12
+  memory.write(0x200, 0x60);
+  memory.write(0x201, 0x12);
+  cpu.run(memory);
+  ASSERT_EQ(cpu.pc, 0x202);
+  ASSERT_EQ(cpu.registers[0], 0x12);
+
+
+  // LD V[1], 0x34
+  memory.write(0x202, 0x61);
+  memory.write(0x203, 0x34);
+  cpu.run(memory);
+  ASSERT_EQ(cpu.pc, 0x204);
+  ASSERT_EQ(cpu.registers[1], 0x34);
+
+
+  // AND V[0], V[1]
+  memory.write(0x204, 0x80);
+  memory.write(0x205, 0x12);
+  cpu.run(memory);
+  ASSERT_EQ(cpu.pc, 0x206);
+  ASSERT_EQ(cpu.registers[0], 0x10);
+)
+
+arabica_cpu_test(test_xor_vx_vy,
+   // LD V[0], 0x12
+  memory.write(0x200, 0x60);
+  memory.write(0x201, 0x12);
+  cpu.run(memory);
+  ASSERT_EQ(cpu.pc, 0x202);
+  ASSERT_EQ(cpu.registers[0], 0x12);
+
+
+  // LD V[1], 0x34
+  memory.write(0x202, 0x61);
+  memory.write(0x203, 0x34);
+  cpu.run(memory);
+  ASSERT_EQ(cpu.pc, 0x204);
+  ASSERT_EQ(cpu.registers[1], 0x34);
+
+
+  // XOR V[0], V[1]
+  memory.write(0x204, 0x80);
+  memory.write(0x205, 0x13);
+  cpu.run(memory);
+  ASSERT_EQ(cpu.pc, 0x206);
+  ASSERT_EQ(cpu.registers[0], 0x26);
+)
+
 arabica_cpu_test(test_add_vx_vy,
   // LD V[0], 0x1 
   memory.write(0x200, 0x60);