adding 93rd day of RTL

ItzzInfinity · Dec 25, 2024 · ff67d0b · ff67d0b
1 parent 18f8362
commit ff67d0b
Show file tree

Hide file tree

Showing 52 changed files with 885 additions and 0 deletions.
diff --git a/day_093/image/1.png b/day_093/image/1.png
diff --git a/day_093/image/2.png b/day_093/image/2.png
diff --git a/day_093/image/3.png b/day_093/image/3.png
diff --git a/day_093/image/4.png b/day_093/image/4.png
diff --git a/day_093/image/5.png b/day_093/image/5.png
diff --git a/day_093/project_1/project_1.cache/sim/ssm.db b/day_093/project_1/project_1.cache/sim/ssm.db
@@ -0,0 +1,10 @@
+################################################################################
+#                            DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Thu Dec 19 18:56:03 2024)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+#                            DONOT REMOVE THIS FILE
+################################################################################
diff --git a/day_093/project_1/project_1.cache/wt/project.wpc b/day_093/project_1/project_1.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
diff --git a/day_093/project_1/project_1.cache/wt/synthesis.wdf b/day_093/project_1/project_1.cache/wt/synthesis.wdf
@@ -0,0 +1,49 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:72746c5f31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7668646c5f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:5b7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66696c65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f77:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f775f73657474696e6773:64656661756c743a3a6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c75745f63617363616465:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d676c6f62616c5f726574696d696e67:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+eof:71835473
diff --git a/day_093/project_1/project_1.cache/wt/xsim.wdf b/day_093/project_1/project_1.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:241934075
diff --git a/day_093/project_1/project_1.hw/project_1.lpr b/day_093/project_1/project_1.hw/project_1.lpr
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit)                                     -->
+<!--                                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                        -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
diff --git a/day_093/project_1/project_1.ip_user_files/README.txt b/day_093/project_1/project_1.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/compile.log b/day_093/project_1/project_1.sim/sim_1/behav/xsim/compile.log
@@ -0,0 +1,4 @@
+INFO: [VRFC 10-2263] Analyzing Verilog file "/home/itzzinfinity/Cozy Drive/100daysofRTL/day_093/project_1/project_1.srcs/sources_1/new/pwm_generator.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module pwm_generator
+INFO: [VRFC 10-2263] Analyzing Verilog file "/home/itzzinfinity/Cozy Drive/100daysofRTL/day_093/project_1/project_1.srcs/sim_1/new/pwm_generator_tb.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module pwm_generator_tb
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/compile.sh b/day_093/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename    : compile.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Thu Dec 19 19:24:50 IST 2024
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj pwm_generator_tb_vlog.prj"
+xvlog --incr --relax -prj pwm_generator_tb_vlog.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log b/day_093/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,15 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /home/itzzinfinity/Xilinx/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot pwm_generator_tb_behav xil_defaultlib.pwm_generator_tb xil_defaultlib.glbl -log elaborate.log 
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling module xil_defaultlib.pwm_generator
+Compiling module xil_defaultlib.pwm_generator_tb
+Compiling module xil_defaultlib.glbl
+Built simulation snapshot pwm_generator_tb_behav
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh b/day_093/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename    : elaborate.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Thu Dec 19 19:24:51 IST 2024
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot pwm_generator_tb_behav xil_defaultlib.pwm_generator_tb xil_defaultlib.glbl -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot pwm_generator_tb_behav xil_defaultlib.pwm_generator_tb xil_defaultlib.glbl -log elaborate.log
+
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/glbl.v b/day_093/project_1/project_1.sim/sim_1/behav/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/pwm_generator_tb.tcl b/day_093/project_1/project_1.sim/sim_1/behav/xsim/pwm_generator_tb.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/pwm_generator_tb_behav.wdb b/day_093/project_1/project_1.sim/sim_1/behav/xsim/pwm_generator_tb_behav.wdb
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/pwm_generator_tb_vlog.prj b/day_093/project_1/project_1.sim/sim_1/behav/xsim/pwm_generator_tb_vlog.prj
@@ -0,0 +1,10 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib  \
+"../../../../project_1.srcs/sources_1/new/pwm_generator.v" \
+"../../../../project_1.srcs/sim_1/new/pwm_generator_tb.v" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/simulate.log b/day_093/project_1/project_1.sim/sim_1/behav/xsim/simulate.log
@@ -0,0 +1,30 @@
+Time resolution is 1 ps
+Time=0, Duty_Cycle=         0, PWM_Out=0
+Time=10, Duty_Cycle=        25, PWM_Out=1
+Time=266, Duty_Cycle=        25, PWM_Out=0
+Time=1034, Duty_Cycle=        25, PWM_Out=1
+Time=1290, Duty_Cycle=        25, PWM_Out=0
+Time=2058, Duty_Cycle=        25, PWM_Out=1
+Time=2314, Duty_Cycle=        25, PWM_Out=0
+Time=3010, Duty_Cycle=        50, PWM_Out=0
+Time=3082, Duty_Cycle=        50, PWM_Out=1
+Time=3594, Duty_Cycle=        50, PWM_Out=0
+Time=4106, Duty_Cycle=        50, PWM_Out=1
+Time=4618, Duty_Cycle=        50, PWM_Out=0
+Time=5130, Duty_Cycle=        50, PWM_Out=1
+Time=5642, Duty_Cycle=        50, PWM_Out=0
+Time=6010, Duty_Cycle=        75, PWM_Out=0
+Time=6154, Duty_Cycle=        75, PWM_Out=1
+Time=6922, Duty_Cycle=        75, PWM_Out=0
+Time=7178, Duty_Cycle=        75, PWM_Out=1
+Time=7946, Duty_Cycle=        75, PWM_Out=0
+Time=8202, Duty_Cycle=        75, PWM_Out=1
+Time=8970, Duty_Cycle=        75, PWM_Out=0
+Time=9010, Duty_Cycle=        99, PWM_Out=1
+Time=9222, Duty_Cycle=        99, PWM_Out=0
+Time=9226, Duty_Cycle=        99, PWM_Out=1
+Time=10246, Duty_Cycle=        99, PWM_Out=0
+Time=10250, Duty_Cycle=        99, PWM_Out=1
+Time=11270, Duty_Cycle=        99, PWM_Out=0
+Time=11274, Duty_Cycle=        99, PWM_Out=1
+$finish called at time : 12010 ns : File "/home/itzzinfinity/Cozy Drive/100daysofRTL/day_093/project_1/project_1.srcs/sim_1/new/pwm_generator_tb.v" Line 44
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh b/day_093/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename    : simulate.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Thu Dec 19 19:24:53 IST 2024
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim pwm_generator_tb_behav -key {Behavioral:sim_1:Functional:pwm_generator_tb} -tclbatch pwm_generator_tb.tcl -log simulate.log"
+xsim pwm_generator_tb_behav -key {Behavioral:sim_1:Functional:pwm_generator_tb} -tclbatch pwm_generator_tb.tcl -log simulate.log
+
diff --git a/day_093/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb b/day_093/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb
diff --git a/...ject_1/project_1.sim/sim_1/behav/xsim/xsim.dir/pwm_generator_tb_behav/Compile_Options.txt b/...ject_1/project_1.sim/sim_1/behav/xsim/xsim.dir/pwm_generator_tb_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "pwm_generator_tb_behav" "xil_defaultlib.pwm_generator_tb" "xil_defaultlib.glbl" -log "elaborate.log" 
diff --git a/...t_1/project_1.sim/sim_1/behav/xsim/xsim.dir/pwm_generator_tb_behav/TempBreakPointFile.txt b/...t_1/project_1.sim/sim_1/behav/xsim/xsim.dir/pwm_generator_tb_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/...oject_1/project_1.sim/sim_1/behav/xsim/xsim.dir/pwm_generator_tb_behav/obj/xsim_0.lnx64.o b/...oject_1/project_1.sim/sim_1/behav/xsim/xsim.dir/pwm_generator_tb_behav/obj/xsim_0.lnx64.o
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "pwm_generator_tb_behav" "xil_defaultlib.pwm_generator_tb" "xil_defaultlib.glbl" -log "elaborate.log"