adding 37th Day of RTL

day_037/project_1/project_1.cache/sim/ssm.db

@@ -0,0 +1,10 @@
+################################################################################
+#                            DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Sun Oct 13 17:22:46 2024)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+#                            DONOT REMOVE THIS FILE
+################################################################################

day_037/project_1/project_1.cache/wt/project.wpc

@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:

day_037/project_1/project_1.cache/wt/synthesis.wdf

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day_037/project_1/project_1.cache/wt/xsim.wdf

@@ -0,0 +1,4 @@
+version:1
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+eof:241934075

day_037/project_1/project_1.hw/project_1.lpr

@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit)                                     -->
+<!--                                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                        -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

day_037/project_1/project_1.ip_user_files/README.txt

@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

day_037/project_1/project_1.sim/sim_1/behav/xsim/compile.log

@@ -0,0 +1,6 @@
+INFO: [VRFC 10-2263] Analyzing Verilog file "/home/itzzinfinity/Cozy Drive/100daysofRTL/day_037/project_1/project_1.srcs/sources_1/new/decoder_5_to_32.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module decoder_5_to_32
+INFO: [VRFC 10-2263] Analyzing Verilog file "/home/itzzinfinity/Cozy Drive/100daysofRTL/day_037/project_1/project_1.srcs/sim_1/new/decoder_tb.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module decoder_tb
+INFO: [VRFC 10-2263] Analyzing Verilog file "/home/itzzinfinity/Cozy Drive/100daysofRTL/day_037/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module glbl

day_037/project_1/project_1.sim/sim_1/behav/xsim/compile.sh

@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename    : compile.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Sun Oct 13 17:22:46 IST 2024
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj decoder_tb_vlog.prj"
+xvlog --incr --relax -prj decoder_tb_vlog.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."

day_037/project_1/project_1.sim/sim_1/behav/xsim/decoder_tb.tcl

@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns

day_037/project_1/project_1.sim/sim_1/behav/xsim/decoder_tb_vlog.prj

@@ -0,0 +1,10 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib  \
+"../../../../project_1.srcs/sources_1/new/decoder_5_to_32.v" \
+"../../../../project_1.srcs/sim_1/new/decoder_tb.v" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort