adding 83rd day of RTL

day_083/project_1/project_1.cache/sim/ssm.db

@@ -0,0 +1,10 @@
+################################################################################
+#                            DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Thu Dec 12 21:33:16 2024)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+#                            DONOT REMOVE THIS FILE
+################################################################################

day_083/project_1/project_1.cache/wt/project.wpc

@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:

day_083/project_1/project_1.cache/wt/synthesis.wdf

@@ -0,0 +1,49 @@
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+eof:71835473

day_083/project_1/project_1.cache/wt/xsim.wdf

@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
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+eof:241934075

day_083/project_1/project_1.hw/project_1.lpr

@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit)                                     -->
+<!--                                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                        -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

day_083/project_1/project_1.ip_user_files/README.txt

@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

day_083/project_1/project_1.sim/sim_1/behav/xsim/compile.log

@@ -0,0 +1,4 @@
+INFO: [VRFC 10-2263] Analyzing Verilog file "/home/itzzinfinity/Cozy Drive/100daysofRTL/day_083/project_1/project_1.srcs/sources_1/new/stopwatch.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module stopwatch
+INFO: [VRFC 10-2263] Analyzing Verilog file "/home/itzzinfinity/Cozy Drive/100daysofRTL/day_083/project_1/project_1.srcs/sim_1/new/stopwatch_tb.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module stopwatch_tb

day_083/project_1/project_1.sim/sim_1/behav/xsim/compile.sh

@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename    : compile.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Thu Dec 12 22:33:25 IST 2024
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj stopwatch_tb_vlog.prj"
+xvlog --incr --relax -prj stopwatch_tb_vlog.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."

day_083/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log

@@ -0,0 +1,15 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /home/itzzinfinity/Xilinx/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot stopwatch_tb_behav xil_defaultlib.stopwatch_tb xil_defaultlib.glbl -log elaborate.log 
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling module xil_defaultlib.stopwatch
+Compiling module xil_defaultlib.stopwatch_tb
+Compiling module xil_defaultlib.glbl
+Built simulation snapshot stopwatch_tb_behav

day_083/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh

@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename    : elaborate.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Thu Dec 12 22:33:27 IST 2024
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot stopwatch_tb_behav xil_defaultlib.stopwatch_tb xil_defaultlib.glbl -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot stopwatch_tb_behav xil_defaultlib.stopwatch_tb xil_defaultlib.glbl -log elaborate.log
+

day_083/project_1/project_1.sim/sim_1/behav/xsim/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

day_083/project_1/project_1.sim/sim_1/behav/xsim/simulate.log

@@ -0,0 +1,2 @@
+Time resolution is 1 ps
+$stop called at time : 8012 ms : File "/home/itzzinfinity/Cozy Drive/100daysofRTL/day_083/project_1/project_1.srcs/sim_1/new/stopwatch_tb.v" Line 106

day_083/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh

@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename    : simulate.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Thu Dec 12 22:33:29 IST 2024
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim stopwatch_tb_behav -key {Behavioral:sim_1:Functional:stopwatch_tb} -tclbatch stopwatch_tb.tcl -log simulate.log"
+xsim stopwatch_tb_behav -key {Behavioral:sim_1:Functional:stopwatch_tb} -tclbatch stopwatch_tb.tcl -log simulate.log
+

day_083/project_1/project_1.sim/sim_1/behav/xsim/stopwatch_tb.tcl

@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns

day_083/project_1/project_1.sim/sim_1/behav/xsim/stopwatch_tb_vlog.prj

@@ -0,0 +1,10 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib  \
+"../../../../project_1.srcs/sources_1/new/stopwatch.v" \
+"../../../../project_1.srcs/sim_1/new/stopwatch_tb.v" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort

day_083/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/stopwatch_tb_behav/Compile_Options.txt

@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "stopwatch_tb_behav" "xil_defaultlib.stopwatch_tb" "xil_defaultlib.glbl" -log "elaborate.log" 

day_083/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/stopwatch_tb_behav/TempBreakPointFile.txt

@@ -0,0 +1 @@
+Breakpoint File Version 1.0