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RED-V_SiFive_RISC-V_FE310_SoC

Merge pull request #27 from Embedded-System-Lovers/update_ci #85

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Merge pull request #27 from Embedded-System-Lovers/update_ci

Merge pull request #27 from Embedded-System-Lovers/update_ci #85

Triggered via push May 31, 2024 07:56
@ckormanyosckormanyos
pushed a4e6e1e
master
Status Success
Total duration 1m 57s
Artifacts –

RED-V_SiFive_RISC-V_FE310_SoC.yml

on: push
target-gcc-riscv32-unknown-elf
1m 49s
target-gcc-riscv32-unknown-elf
target-gcc-riscv32-unknown-elf-cmake
1m 36s
target-gcc-riscv32-unknown-elf-cmake
target-gcc-riscv32-unknown-elf-macos
1m 19s
target-gcc-riscv32-unknown-elf-macos
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