RED-V_SiFive_RISC-V_FE310_SoC

Merge pull request #26 from Embedded-System-Lovers/the_unlicense #78

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Re-run triggered May 30, 2024 11:27

ckormanyos

master

Status Success

Total duration 1m 36s

Artifacts –

RED-V_SiFive_RISC-V_FE310_SoC.yml

on: push

target-gcc-riscv32-unknown-elf

target-gcc-riscv32-unknown-elf-cmake

target-gcc-riscv32-unknown-elf-macos