Generate primitives with multiple aspect ratios and then use the placer to decide which to choose. #671

stevenmburns · 2021-04-27T18:49:18Z

~~- [x] Set up a simple test framework where we hack in extra primitives and make the placer work~~

Hack generation of multiple primitives with equal total 'nfin'
Modify verilog json and placement verilog json to use "abstract_template_name" and "concrete_template_name"
Create C++ data structure to represent the abstract to concrete map. Should be a string to vector[string] map. (Replaces string to string map.)
Use the new map with the placer.

stevenmburns · 2021-04-27T19:21:40Z

@kkunal1408 @parijatm @soneryaldiz @arvuce22 @854768750 @Lastdayends
How do we decide the current aspect ratio of the primitives?
Currently only one the last of these below is chosen for a nfin240.
Is there any reason we can't generate all four and let the placer choose the best one?
The product of n, X, Y should be 240 in each case.

  "Switch_PMOS_nfin240_n10_X4_Y6_ST2_RVT": {
    "primitive": "Switch_PMOS",
    "value": 10,
    "x_cells": 4,
    "y_cells": 6,
    "parameters": {
      "w": 2.7e-08,
      "l": 2e-08,
      "nfin": 240.0,
      "stack": 2,
      "real_inst_type": "pmos_rvt"
    },
    "stack": 2,
    "vt_type": "RVT"
  },
  "Switch_PMOS_nfin240_n10_X6_Y4_ST2_RVT": {
    "primitive": "Switch_PMOS",
    "value": 10,
    "x_cells": 6,
    "y_cells": 4,
    "parameters": {
      "w": 2.7e-08,
      "l": 2e-08,
      "nfin": 240.0,
      "stack": 2,
      "real_inst_type": "pmos_rvt"
    },
    "stack": 2,
    "vt_type": "RVT"
  },
  "Switch_PMOS_nfin240_n12_X4_Y5_ST2_RVT": {
    "primitive": "Switch_PMOS",
    "value": 12,
    "x_cells": 4,
    "y_cells": 5,
    "parameters": {
      "w": 2.7e-08,
      "l": 2e-08,
      "nfin": 240.0,
      "stack": 2,
      "real_inst_type": "pmos_rvt"
    },
    "stack": 2,
    "vt_type": "RVT"
  },
  "Switch_PMOS_nfin240_n12_X5_Y4_ST2_RVT": {
    "primitive": "Switch_PMOS",
    "value": 12,
    "x_cells": 5,
    "y_cells": 4,
    "parameters": {
      "w": 2.7e-08,
      "l": 2e-08,
      "nfin": 240.0,
      "stack": 2,
      "real_inst_type": "pmos_rvt"
    },
    "stack": 2,
    "vt_type": "RVT"
  },

If this is okay, I'm going to change the interface data structure a little bit (at the align.main level, creating both a mapping file and a primitive file) and then ask various of you to move the adapters into the appropriate modules.

soneryaldiz · 2021-04-27T20:36:32Z

@stevenmburns , let's chat about this in our 1:1. The interface between the core and pdk has to change anyway to accommodate the generate constraint. Except few corner cases, what transistor array generator really needs is the number of rows to place the active array on. Given w/lnfin/nf/m from the netlist, no other parameters are needed.

We should really retire or move any custom hacks to netlist preprocessing. It might be good to allow a PDK to register a netlist preprocessor.

854768750 · 2021-04-28T02:27:41Z

I can add something in PnR when multiple aspect ratio is generated.

… model

854768750 · 2021-04-28T13:57:44Z

For PnR, multiple aspect ratio needs the modification of input files:
map file:

primitive1 primitive1_x1_y2.gds
primitive1 primitive1_x2_y1.gds

lef file:

MACRO primitive1_x1_y2
MACRO primitive1_x2_y1

verilog file:

"template_name":"primitive1"
"instance_name": "m1"

stevenmburns · 2021-04-28T20:54:25Z

@parijatm I'm now proposing that we modify the master name fields in the placement.verilog.json after placement and we have choose concrete layouts for each of the leaf cells. This PR is doing that now for capacitors.
Whether or not two instance of the same (abstract) template name have the same layout is upto whatever constraints are provided to the system and it will need to be verified using the checker system.

Since this is different semantics than usual, we might want to replace the template_name field with two new fields: abstract_template_name and concrete_template_name. For each abstract_template_name we have a list of possible concrete_template_name strings, which the placer can chose to use (based on area, meeting constraints, etc.)

This is what the current map file is meant to do, but that functionality has slowly died (not it is always a one-to-one mapping.)

Also, we don't current write out the placement_verilog_json anywhere

…_name (for leaves)

parijatm · 2021-04-28T22:15:57Z

@parijatm I'm now proposing that we modify the master name fields in the placement.verilog.json after placement and we have choose concrete layouts for each of the leaf cells. This PR is doing that now for capacitors.
Whether or not two instance of the same (abstract) template name have the same layout is upto whatever constraints are provided to the system and it will need to be verified using the checker system.

Since this is different semantics than usual, we might want to replace the template_name field with two new fields: abstract_template_name and concrete_template_name. For each abstract_template_name we have a list of possible concrete_template_name strings, which the placer can chose to use (based on area, meeting constraints, etc.)

This is what the current map file is meant to do, but that functionality has slowly died (not it is always a one-to-one mapping.)

Also, we don't current write out the placement_verilog_json anywhere

All the proposed changes sound good to me. Note that we haven't yet formalized any constraints that force two primitive instances of the same (abstract) template name to have the same layout. SymmetricBlocks comes to mind but I am yet to review exactly what PnR does for these.

I am not quite clear where the list of possible concrete_template_name strings are specified though. Are we fixing the map file, looking at the primitive key in primitive.json? I would rather keep it together with the heirarchy information (.verilog.json) somehow so that we can eventually eliminate the file based transfer of information we are doing now.

stevenmburns · 2021-04-28T22:46:40Z

Right now I'm generate more options by modifying the entries in the original primitives.json (from the topology generator), for example by switching the X and Y values (for values that are different) and running that through the primitive generation flow. This should be the job of the topology generator (or at least it is generating the one size now) or a new flow stage that decides what different aspect ratio might make sense.

stevenmburns · 2021-04-28T22:48:53Z

It seems that we could add the information in primitives.json to our verilog_json file for communication between stages.

…ithin PnR engine; currently fails

stevenmburns · 2021-04-29T03:37:24Z

@854768750 This is ready to rewrote the PnR code for the new map file.
Currently it looks like this (for current_mirror_ota) [I've added some more primitives]

DCL_PMOS_nfin60_RVT DCL_PMOS_nfin60_n12_X5_Y1_RVT.gds
Switch_PMOS_nfin240_ST2_RVT Switch_PMOS_nfin240_n12_X5_Y4_ST2_RVT.gds
SCM_NMOS_nfin10_RVT SCM_NMOS_nfin10_n12_X1_Y1_RVT.gds
SCM_NMOS_nfin24_RVT SCM_NMOS_nfin24_n12_X2_Y1_RVT.gds
DP_NMOS_B_nfin28_RVT DP_NMOS_B_nfin28_n12_X3_Y1_RVT.gds
DCL_PMOS_nfin60_RVT DCL_PMOS_nfin60_n12_X1_Y5_RVT.gds
Switch_PMOS_nfin240_ST2_RVT Switch_PMOS_nfin240_n12_X4_Y5_ST2_RVT.gds
SCM_NMOS_nfin24_RVT SCM_NMOS_nfin24_n12_X1_Y2_RVT.gds
DP_NMOS_B_nfin28_RVT DP_NMOS_B_nfin28_n12_X1_Y3_RVT.gds

It is crashing with some LEF fetching errors --- I think this is to be expected until we use the information in the map file correctly.

nR.PnRDB.PnRdatabase._ReadLEF INFO : PnRDB-Info: reading LEF file <string>
align.pnr.build_pnr_model INFO : Finished reading contraint json file current_mirror_ota.pnr.const.json
PnR.PnRDB.PnRdatabase.MergeLEFMapData INFO : merge LEF/map data on node current_mirror_ota
PnR.PnRDB.PnRdatabase.MergeLEFMapData ERROR : The key does not exist in map: DCL_PMOS_nfin60_RVT
PnR.PnRDB.PnRdatabase.MergeLEFMapData ERROR : The key does not exist in map: Switch_PMOS_nfin240_ST2_RVT
PnR.PnRDB.PnRdatabase.MergeLEFMapData ERROR : The key does not exist in map: DCL_PMOS_nfin60_RVT
PnR.PnRDB.PnRdatabase.MergeLEFMapData ERROR : The key does not exist in map: Switch_PMOS_nfin240_ST2_RVT
PnR.PnRDB.PnRdatabase.MergeLEFMapData ERROR : The key does not exist in map: SCM_NMOS_nfin10_RVT
PnR.PnRDB.PnRdatabase.MergeLEFMapData ERROR : The key does not exist in map: SCM_NMOS_nfin24_RVT
PnR.PnRDB.PnRdatabase.MergeLEFMapData ERROR : The key does not exist in map: DP_NMOS_B_nfin28_RVT
align.pnr.toplevel INFO : Starting bottom-up placement on current_mirror_ota 0
PnR.cap_placer.Placer_Router_Cap.Common_centroid_capacitor_aspect_ratio INFO : CC Capacitor Placement and Router : current_mirror_ota m21
PnR.cap_placer.Placer_Router_Cap.Common_centroid_capacitor_aspect_ratio INFO : CC Capacitor Placement and Router : current_mirror_ota m20s
PnR.cap_placer.Placer_Router_Cap.Common_centroid_capacitor_aspect_ratio INFO : CC Capacitor Placement and Router : current_mirror_ota m19
PnR.cap_placer.Placer_Router_Cap.Common_centroid_capacitor_aspect_ratio INFO : CC Capacitor Placement and Router : current_mirror_ota m18s
PnR.cap_placer.Placer_Router_Cap.Common_centroid_capacitor_aspect_ratio INFO : CC Capacitor Placement and Router : current_mirror_ota m14_m16
PnR.cap_placer.Placer_Router_Cap.Common_centroid_capacitor_aspect_ratio INFO : CC Capacitor Placement and Router : current_mirror_ota m11_m10
PnR.cap_placer.Placer_Router_Cap.Common_centroid_capacitor_aspect_ratio INFO : CC Capacitor Placement and Router : current_mirror_ota m17_m15
Segmentation fault

854768750 · 2021-04-29T03:42:26Z

I see. I will do some changes to the PnR code.

…w mapping; still broken

stevenmburns · 2021-04-29T06:51:30Z

PlaceRouteHierFlow/PnRDB/PnRdatabase.h

@@ -82,7 +82,8 @@ class PnRdatabase
    int unitScale;
    map<string, vector<PnRDB::lefMacro> > lefData;  //map from Macro name to Macro Instance
  public:
-    map<string, string> gdsData; //map from gds name to gds file
+    map<string, string> gdsData; //map from gds name to gds file (won't need this one after being replaced by gdsData2)
+    map<string, vector<string> > gdsData2; //map from gds name to multiple gds file (abstract to multiple concrete)


@854768750 I added this as the C++ data structure of the new mapping.

stevenmburns · 2021-04-29T06:53:53Z

align/pnr/build_pnr_model.py

    with (d / mapname).open( "rt") as fp:
        for line in fp:
            line = line.rstrip('\n')
            m = p.match(line)
            assert m
            k, v = m.groups()
            tbl[k] = str(d / v)
-    return tbl
+            tbl2[k].append( str(d / v))


@854768750 Here tbl2 is the python version of the map from abstract name to list of concrete names.

stevenmburns · 2021-04-29T06:53:55Z

align/pnr/build_pnr_model.py

@@ -189,7 +143,11 @@ def PnRdatabase( path, topcell, vname, lefname, mapname, drname):
    DB.ReadPDKJSON( path + '/' + drname)

    _ReadLEF( DB, path, lefname)
-    DB.gdsData = _ReadMap( path, mapname)
+    DB.gdsData, DB.gdsData2 = _ReadMap( path, mapname)


@854768750 Here is were the Python map get copied to the C++ map. (and the printed out so we can see it is doing the right thing.)

stevenmburns · 2021-04-29T20:08:02Z

@854768750 I added some more stuff that you should feel free to ignore. It might be helpful if you haven't started, but probably will not be helpful if you have.

854768750 · 2021-04-29T20:31:33Z

ok, I am solving the merge conflicts.

854768750 · 2021-04-30T15:52:16Z

ok, then capacitors are like other primitives, multiple aspect ratio of capacitor is before PnR

stevenmburns · 2021-04-30T15:54:11Z

That is what we want eventually. I wasn't going to move the capacitors to the primitive stage in this PR, but soon.

854768750 · 2021-04-30T15:56:07Z

ok, I will do some changes of name mapping in capplacer

stevenmburns · 2021-04-30T16:10:25Z

I did something simple. Ignore this check in if you have something better.

stevenmburns · 2021-04-30T16:36:21Z

@854768750 That seemed to fix things up well. Maybe we can wait on more fixes until another PR.

stevenmburns · 2021-04-30T16:38:36Z

PlaceRouteHierFlow/PnRDB/PnRdatabase.cpp

+    const string abstract_template_name = node.Blocks[i].instance.front().master;
+
+    if (gdsData2.find(abstract_template_name) == gdsData2.end()) {
+      if (abstract_template_name.find("Cap") != std::string::npos || abstract_template_name.find("cap") != std::string::npos || !node.Blocks[i].instance.back().isLeaf) continue;


@854768750 I just fir checked if the abstract_template_name was in gdsData2. If not, I'll skip the whole process if cap is in the name.

Currently this does not cause error on capacitor because capplacer is not functioning.

This is fine because, seems in BUFFER_VREFP1, Dcap is just like other ordinary primitives.

stevenmburns · 2021-04-30T16:50:01Z

I ran the regression through and there are some other corner cases to deal with. There are three that used to work that don't anymore: powertrain_binary, test_vga, and Gm1_v5_Practice

I'm looking to see if they have anything in common.

parijatm · 2021-04-30T17:06:39Z

I ran the regression through and there are some other corner cases to deal with. There are three that used to work that don't anymore: powertrain_binary, test_vga, and Gm1_v5_Practice

I'm looking to see if they have anything in common.

Some of these broke with the last PR merge. @kkunal1408 is looking into it now.

This is the current list:

FAILED tests/integration/test_all.py::test_A[20-FinFET14nm_Mock_PDK-SW_Cres_v3_5]
FAILED tests/integration/test_all.py::test_A[20-FinFET14nm_Mock_PDK-Sanitized_Coarse_Comp_CK]
FAILED tests/integration/test_all.py::test_A[20-FinFET14nm_Mock_PDK-COMP_GM_STAGE_0415]
FAILED tests/integration/test_all.py::test_A[20-FinFET14nm_Mock_PDK-powertrain_binary]
FAILED tests/integration/test_all.py::test_A[20-FinFET14nm_Mock_PDK-telescopic_ota_guard_ring]
FAILED tests/integration/test_all.py::test_A[20-FinFET14nm_Mock_PDK-vco_dtype_12_hierarchical]
FAILED tests/integration/test_all.py::test_A[20-FinFET14nm_Mock_PDK-test_vga]
FAILED tests/integration/test_all.py::test_A[20-FinFET14nm_Mock_PDK-vco_dtype_12_hierarchical_res]

stevenmburns · 2021-04-30T17:10:23Z

I guess I'll keep looking into: Gm1_v5_Practice
This seems to be the only one that is failing in addition to what is failing on master now.

stevenmburns · 2021-04-30T18:47:14Z

@parijatm @854768750 This is ready to check in.
There is some cleanup that should be done. Right now there are some warts in align/main.py that generate more primitives. We need to generate them in some better way. Also verilog file modification are being done there instead of at the source (the topology flow.) We can either address them now or in a subsequent PR.

stevenmburns · 2021-04-30T18:54:21Z

Here are two placement from current_mirror_ota where the leaf blocks have different aspect ratios

stevenmburns · 2021-04-30T18:59:50Z

align/main.py

@@ -33,6 +36,59 @@ def build_steps( flow_start, flow_stop):
    return steps_to_run


+def gen_more_primitives( primitives, topology_dir, subckt):


@kkunal1408 @arvuce22 This is the code that needs to be moved upstream in the flow, either topology, or primitives or both.

stevenmburns · 2021-04-30T20:35:48Z

@parijatm Ready for review.

parijatm

Lots of great changes in this PR.

Looks good to go !

Set up test to work on multi-aspect primitives

00271d9

stevenmburns requested review from soneryaldiz and removed request for soneryaldiz April 27, 2021 19:38

Experiments to determine placeholder hierarchy to maintain the folded…

879165b

… model

stevenmburns added 2 commits April 28, 2021 13:16

Renaming templates to their concrete name

20e4fc2

Use gdsFile (cleaned up a bit) as the concrete template name

26982b0

Renamed template_name to abstract_template_name and concrete_template…

6efc6c2

…_name (for leaves)

Generate some more primitives

2776f1c

[skip CI] Ready for integration of an abstract to concrete map file w…

dd78c8f

…ithin PnR engine; currently fails

stevenmburns added 2 commits April 28, 2021 23:29

Merge branch 'master' into feature/one_to_many_map_file

b2f8221

[skip CI] Added map from string to vector<string> to represent the ne…

ce9ec32

…w mapping; still broken

stevenmburns commented Apr 29, 2021

View reviewed changes

stevenmburns changed the title ~~Generate primitives with multiple aspect ratios and then use the placer to decide which to choose.~~ WIP: Generate primitives with multiple aspect ratios and then use the placer to decide which to choose. Apr 29, 2021

[skip CI] More changes

9f01d19

read multiple aspect ratio into gdsdata2 and block instances

e95a4e7

merge

20ec0c0

Better pattern matching; better handling of Dcaps

8480ad1

stevenmburns commented Apr 30, 2021

View reviewed changes

stevenmburns added 3 commits April 30, 2021 10:18

Better error messages

b749441

Fixed case of unused primitives

a61f323

Removed a redundant data structure

599a5d3

stevenmburns changed the title ~~WIP: Generate primitives with multiple aspect ratios and then use the placer to decide which to choose.~~ Generate primitives with multiple aspect ratios and then use the placer to decide which to choose. Apr 30, 2021

Make -rp work again.

da60b3b

stevenmburns mentioned this pull request Apr 30, 2021

Extract Capacitor Arrary Generation to Earlier in the Flow #661

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stevenmburns added 3 commits April 30, 2021 12:02

Remove unneeded test

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Add a rendering test

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Remove telescopic_ota_guard_ring from CI

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stevenmburns mentioned this pull request Apr 30, 2021

CI Failure: telescopic_ota_guard_ring has 57 DRC errors #679

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stevenmburns requested review from parijatm, 854768750 and soneryaldiz April 30, 2021 20:45

parijatm approved these changes Apr 30, 2021

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stevenmburns merged commit 9947659 into master Apr 30, 2021

stevenmburns deleted the feature/one_to_many_map_file branch April 30, 2021 20:50

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Generate primitives with multiple aspect ratios and then use the placer to decide which to choose. #671

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		@@ -33,6 +36,59 @@ def build_steps( flow_start, flow_stop):
		return steps_to_run


		def gen_more_primitives( primitives, topology_dir, subckt):

Generate primitives with multiple aspect ratios and then use the placer to decide which to choose. #671

Generate primitives with multiple aspect ratios and then use the placer to decide which to choose. #671

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