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Circuits database update
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...tabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/README.md
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| ## Gate driver circuit for a DLDO | ||
| ## Single-ended OTA testbench | ||
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| ### Circuit Description | ||
| The table below contains all the important OTA performance metrics and the corresponding simulation used to evaluate. | ||
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| This circuit is a part of the gate driver circuitry in a digital low voltage dropout regulator [1]. This circuit drives PMOS power transistors that supply a load current to the output at a given voltage. | ||
| <p align="center"> | ||
| <img width=60%" src="table.PNG"> | ||
| </p> | ||
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| The block diagram of the system is shown in the figure below. | ||
| The figure below contains a brief summary of the setup used for each of the testbenches listed above. | ||
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| The diagram of the circuit is as follows. | ||
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| ### Pin description | ||
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| * Din - input pulse waveform | ||
| * Dout - inverted output pulse waveform | ||
| * Vb - gate voltage of transistor in triode that changes the on resistance | ||
| * SS - steady state detection signal switch | ||
| * SS bar - inverted steady state detection signal switch | ||
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| The operation of the circuit is highlighted below. | ||
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| When the steady state detection is low, gate driver is a combination of an inverter with a voltage divider. Dout is at a voltage (eg. 250 mV) depending on the ratio of the resistors. When the steady state detection signal is high, the input is maintained constant, the voltage divider also incorporates the resistance contributed by the switch controlled by Vb. As Vb changes, Dout changes. | ||
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| ### Netlist description | ||
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| * Din - input | ||
| * Dout - output | ||
| * Vb - control (similar to diagram) | ||
| * ss - steady state detection signal | ||
| * ss_bar_nmos - nmos switch controlled by ss_bar | ||
| * ss_bar_pmos - pmos switch controlled by ss_bar | ||
| * Lres_nmos - on voltage of large nmos resistor | ||
| * Lres_pmos - on voltage of large pmos resistor | ||
| * Sres_nmos - on voltage of small nmos resistor | ||
| * Sres_pmos - on voltage of small pmos resistor | ||
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| ### Initial setup + Testbench | ||
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| To test this circuit, give a clock waveform at Din and observe Dout in steady state and not in steady state. In steady state, Vb can be changed to observe a change in Dout. | ||
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| ### Constraints | ||
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| * In steady state there is power dissipation through the voltage divider and any added parasitic routing | ||
| * The capacitance at the output will lower the speed of switching when not in steady state | ||
| <p align="center"> | ||
| <img width=60%" src="summary.PNG"> | ||
| </p> |
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... frequency analog/Single_ended_OTA_Testbench/single_ended_OTA_testbench_documentation.pdf
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CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Bandpass_filter/README.md
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| ## Bandpass filter circuit | ||
| A bandpass filter circuit is used for filtering band of signal frequencies at a center frequency (fc). | ||
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| ### Circuit description | ||
| The circuit requires inductors and capacitors for tuning the center frequency. As inductors are huge in size as compared to capacitors, | ||
| capacitors are used for tuning the center frequencies. To remove the parallel resistance in the LC circuit, a cross-coupled transistors | ||
| are used which add negative resistance. | ||
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| ### Testbench/Simulations | ||
| An AC and transient simulation is required to measure the perfomance of bandpass filter. An AC simulation will measure the quality factor | ||
| (Q) of the filter. | ||
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| ### Performance metrics | ||
| * Quality Factor (Q) | ||
| * Center frequency (fc) | ||
| * Bandwidth | ||
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| ### Constraints | ||
| The parasitics around output node must be minimized to reduce variations of center frequency. |
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CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/LNA/README.md
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| ## LNA | ||
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| ### Circuit description | ||
| LNA are used at RF front end of receiver to set Noise floor of the system. | ||
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| ### Testbench/Simulations | ||
| AC simulation is used to check the gain. A noise simulation is required to check noise figure (NF) of LNA. | ||
| Transient simulation is used for checking IIP3 of LNA. | ||
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| ### Performance metrics | ||
| * Gain | ||
| * Noise figure | ||
| * IIP3 | ||
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| ### Constraints | ||
| A guard ring must be covering all transistors in LNA. Wide metal lines to reduce resistance over lines. |
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CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Mixer/README.md
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| ## Mixer | ||
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| ### Circuit description | ||
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| Mixers are used for translating RF signals to IF signals or IF signals to RF signals using local oscillator frequency. | ||
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| ### Testbench/Simulations | ||
| Transient simulation is used for checking the output spectrum. PSP simulation is used to calculate the conversion gain. | ||
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| ### Performance metrics | ||
| * IIP3 | ||
| * Conversion Gain | ||
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| ### Constraints | ||
| Symmetric routing is critical for correct IF/RF output generation. Shielding the nets is recommended. |
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CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Oscillator/README.md
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| ## Oscillator | ||
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| ### Circuit description | ||
| For a oscillator circuit, a LC tank circuit is required. To cancel the parallel resistance in LC circuit, a cross coupled transistor pair | ||
| cancels the positive resistance by adding a negative resistance. | ||
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| ### Testbench/Simulations | ||
| Transient simulation is required to check lock range. | ||
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| ### Performance metrics | ||
| * Lock Range | ||
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| ### Constraints | ||
| Symmetric routes are required for differential output nets. Minimum parasitic for each net is critical for performance. |
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| **Wireline** | ||
| ## **Wireline** | ||
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| Circuit | Technology | Netlist | Schematic | Layout | Testbench | Constraints | ALIGN | | ||
| :------ | :--------- | :---- | :------ | :-------- | :----- | :-------- | :---------- | | ||
| Single to differential converter | 12 nm | :heavy_check_mark: | | | | | | | ||
| Adder | 12 nm | :heavy_check_mark: | | | | | | | ||
| Variable gain amplifier | 12 nm | :heavy_check_mark: | | | | | | | ||
| Variable gain amplifier (VGA) | 12 nm | :heavy_check_mark: | | | | | | | ||
| Adder unit | 12 nm | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | ||
| Double tail sense amplifier | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | | ||
| Linear Equalizer 2 level| 12 nm | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | | ||
| Linear Equalizer 4 level | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | :heavy_check_mark: | | ||
| Transimpedance amplifier | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | | ||
| Variable gain amplifier | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | :heavy_check_mark: | | ||
| Variable gain amplifier 3 stage | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | |
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CircuitsDatabase/Sized netlists/Wireline/adder_unit/Adder_schematic_top.sp
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| // Generated for: spectre | ||
| // Generated on: Jan 1 23:12:07 2020 | ||
| // Design library name: EQ_01012020 | ||
| // Design cell name: Adder_top | ||
| // Design view name: schematic | ||
| simulator lang=spectre global 0 vdd! | ||
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| // Library name: EQ_01012020 | ||
| // Cell name: Adder_top | ||
| // View name: schematic | ||
| R2 (vout vdd!) metalres w=32n l=19.944u metLayer=15 | ||
| R1 (vb1 net2) metalres w=32n l=684.384u metLayer=15 | ||
| R0 (net3 vb2) metalres w=32n l=684.384u metLayer=15 | ||
| N0 (vout net2 net010 0) nfet m=1 l=14n nfin=12 nf=3 | ||
| N2 (net010 net2 0 0) nfet m=1 l=14n nfin=12 nf=3 | ||
| C2 (vout 0) capacitor c=cload_adder | ||
| C1 (vin net2) apmom1v2 m=1 w=1.724u l=8.6u | ||
| C0 (vin net3) apmom1v2 m=1 w=1.724u l=8.6u | ||
| V3 (vdd! 0) vsource dc=vps type=dc | ||
| V1 (vb2 0) vsource dc=vbias_pfet_adder type=dc | ||
| V0 (vb1 0) vsource dc=vbias_nfet_adder type=dc | ||
| V2 (vin 0) vsource mag=1 type=sine ampl=100m freq=1G | ||
| P0 (vout net3 net011 vdd!) pfet m=1 l=14n nfin=12 nf=3 | ||
| P1 (net011 net3 vdd! vdd!) pfet m=1 l=14n nfin=12 nf=3 | ||
| simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ | ||
| tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ | ||
| digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ | ||
| checklimitdest=psf | ||
| dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status | ||
| dcOpInfo info what=oppoint where=rawfile | ||
| ac ac start=10000 stop=100G dec=10 annotate=status | ||
| tran tran stop=10n errpreset=conservative write="spectre.ic" \ | ||
| writefinal="spectre.fc" annotate=status maxiters=5 | ||
| finalTimeOP info what=oppoint where=rawfile | ||
| modelParameter info what=models where=rawfile | ||
| element info what=inst where=rawfile | ||
| outputParameter info what=output where=rawfile | ||
| designParamVals info what=parameters where=rawfile | ||
| primitives info what=primitives where=rawfile | ||
| subckts info what=subckts where=rawfile | ||
| saveOptions options save=allpub | ||
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CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_layout.tiff
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CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_schematic.tiff
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CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_unit.sp
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| .subckt adder_align vb1 vb2 vin vout vps vgnd | ||
| MN0 vout n1 vgnd vgnd nfet l=0.014u nfin=36 | ||
| MP0 vout n2 vps vps pfet l=0.014u nfin=36 | ||
| R0 n1 vb1 resistor r=15000 | ||
| Rph0 n1 vin resistor r=15000 | ||
| R1 n2 vb2 resistor r=15000 | ||
| Rph1 n2 vin resistor r=15000 | ||
| R2 vps vout resistor r=500 | ||
| .ends adder_align |
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...ized netlists/Wireline/double_tail_sense_amplifier/.double_tail_sense_amplifier.const.swp
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CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/DTSA_layout.tiff
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...tabase/Sized netlists/Wireline/double_tail_sense_amplifier/double_tail_sense_amplifier.sp
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| .subckt common_centroid_n d1 d2 s | ||
| MN1 d1 d2 s s nfet l=14e-9 nfin=12 | ||
| MN0 d2 d1 s s nfet l=14e-9 nfin=12 | ||
| .ends common_centroid_n | ||
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| .subckt common_centroid_p d1 d2 s | ||
| MP1 d1 d2 s s pfet l=14e-9 nfin=12 | ||
| MP0 d2 d1 s s pfet l=14e-9 nfin=12 | ||
| .ends common_centroid_p | ||
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| .subckt common_centroid_np d1 d2 vps vgnd | ||
| xI0 d1 d2 vgnd common_centroid_n | ||
| xI1 d1 d2 vps common_centroid_p | ||
| .ends | ||
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| .subckt double_tail_sense_amplifier clk clkb in1 in2 out1 out2 vps vgnd | ||
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| MN1 out1 n1 vgnd vgnd nfet l=14e-9 nfin=12 | ||
| MN2 out2 n2 vgnd vgnd nfet l=14e-9 nfin=12 | ||
| MP1 net8 clkb vps vps pfet l=14e-9 nfin=12 | ||
| xI2 out1 out2 net8 vgnd common_centroid_np | ||
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| MN3 n1 in1 net6 net6 nfet l=14e-9 nfin=12 | ||
| MN4 n2 in2 net6 net6 nfet l=14e-9 nfin=12 | ||
| MN5 net6 clk vgnd vgnd nfet l=14e-9 nfin=12 | ||
| MP2 n1 clk vps vps pfet l=14e-9 nfin=12 | ||
| MP3 n2 clk vps vps pfet l=14e-9 nfin=12 | ||
| .ends | ||
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CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/LE_layout.tiff
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CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/linear_equalizer.sp
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| .subckt linear_equalizer_or vmirror vin1 vin2 vout1 vout2 vps vgnd | ||
| MN0 vmirror vmirror vgnd vgnd nfet l=14e-9 nfin=12 | ||
| MN1 n1 vmirror vgnd vgnd nfet l=14e-9 nfin=12 | ||
| MN2 n2 vmirror vgnd vgnd nfet l=14e-9 nfin=12 | ||
| MN3 vout1 vin1 n1 vgnd nfet l=14e-9 nfin=12 | ||
| MN4 vout2 vin2 n2 vgnd nfet l=14e-9 nfin=12 | ||
| R0 vps vout1 resistor r=100 | ||
| R1 vps vout2 resistor r=100 | ||
| R2 n1 n2 resistor r=100 | ||
| R3 n1 n2 resistor r=2000 | ||
| .ends linear_equalizer_or | ||
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