Merge pull request #293 from ALIGN-analoglayout/design_database_reorg

Design database reorg

CircuitsDatabase/README.md

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+# Circuits Database
+
+<p align="center">
+  <img width=60%" src="circuit_database_structure.png">
+</p>
+
+* Sized netlists - Contains sized netlists in different technology nodes
+* Unsized netlists - Contains unsized netlists generated for training GCN based netlist annotation
+
+## Sized netlists
+
+Designs from four classes of circuits:
+
+* Low frequency analog
+* Power Management
+* Wireless/Radio frequency
+* Wireline
+
+### Testbenches
+
+Generic testbenches enabling plug and play of common modules with different internal topologies
+
+## Unsized netlists
+
+Currently contains designs from two classes of circuits:
+
+* Low frequency analog
+* Wireless/Radio frequency

CircuitsDatabase/Sized netlists/Low frequency analog/Cascode_current_mirror_OTA/README.md

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+## Cascode Current Mirror OTA - single ended
+
+### Circuit Description
+
+This OTA (Operational Transconductance Amplifier) circuit is used to achieve high gain and comparably higher output swing.
+
+The diagram of the circuit is as follows.
+
+![Circuit diagram](schematic.jpg)
+
+### Pin description
+
+* Vin - input common mode DC + input AC
+* Voutp - output of the amplifier
+* Vbiasn - bias current input
+* Vbiasp - bias current input
+* Vdd - supply voltage
+
+### Initial setup + Testbench
+
+The initial setup, for the voltages and currents to these input pins, and the testbench is present in the spice file.
+
+Simulations
+* DC - operating point information
+* AC - gain, three dB frequency, unity gain frequency, phase margin
+
+The AC response plot is shown below
+
+![AC response](AC_response.png)
+
+### Performance Metrics
+
+* Gain - 41 dB
+* Three dB frequency - 10.66 MHz
+* Unity gain frequency - 1.22 GHz
+* Phase margin ~ 80 degrees
+
+### Constraints
+
+* The input differential pair in the schematic needs to be matched
+* The current mirrors shown in the schematic need to be matched

CircuitsDatabase/Sized netlists/Low frequency analog/Cascode_current_mirror_OTA/cascode_current_mirror_ota.sp

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+** Generated for: hspiceD
+** Generated on: Nov 16 15:51:50 2018
+** Design library name: DC_converter
+** Design cell name: 2018_11_09_ASAP7_current_mirror_ota
+** Design view name: schematic
+.GLOBAL vdd!
+
+.OP
+
+.AC DEC 100 1.0 1e11
+
+.DC v1 600e-3 700e-3 100e-3
+
+.TEMP 25.0
+
+.OPTION INGOLD=2 ARTIST=2 PSF=2 MEASOUT=1 PARHIER=LOCAL PROBE=0 MARCH=2 ACCURACY=1 POST
+
+.INCLUDE /project/design-kits/OpenSource_PDKs/ASAP_7nm/asap7PDK_r1p3/models/hspice/7nm_TT_160803.pm
+
+
+** Library name: DC_converter
+** Cell name: 2018_11_09_ASAP7_current_mirror_ota
+** View name: schematic
+i4 vdd! net17 DC=200e-6
+c2 voutp 0 357e-15
+m25 voutp vbiasn net034 0 nmos_rvt w=27e-9 l=20e-9 nfin=24
+m24 vbiasnd vbiasn net033 0 nmos_rvt w=27e-9 l=20e-9 nfin=24
+m17 net16 vinn net24 0 nmos_rvt w=27e-9 l=20e-9 nfin=30
+m16 net24 net17 0 0 nmos_rvt w=27e-9 l=20e-9 nfin=15
+m15 net27 vinp net24 0 nmos_rvt w=27e-9 l=20e-9 nfin=30
+m14 net17 net17 0 0 nmos_rvt w=27e-9 l=20e-9 nfin=15
+m11 net033 vbiasnd 0 0 nmos_rvt w=27e-9 l=20e-9 nfin=30
+m10 net034 vbiasnd 0 0 nmos_rvt w=27e-9 l=20e-9 nfin=30
+**v1 vbiasp 0 DC=300e-3
+v0 vdd! 0 DC=1000e-3
+**v2 vbiasn 0 DC=700e-3
+
+i1 vdd! vbiasn DC=10e-6
+m1nup vbiasn vbiasn net9b 0 nmos_rvt w=270e-9 l=20e-9 nfin=3
+m1ndown net9b net9b 0 0 nmos_rvt w=270e-9 l=20e-9 nfin=5
+
+i2 vbiasp 0 DC=10e-6
+m1pup net8b net8b vdd! vdd! pmos_rvt w=270e-9 l=20e-9 nfin=5
+m1pdown vbiasp vbiasp net8b net8b pmos_rvt w=270e-9 l=20e-9 nfin=5
+
+
+v3 vinn 0 DC=0.55 AC 500e-3 180
+v4 vinp 0 DC=0.55 AC 500e-3 
+m27 net27 vbiasp net021 net021 pmos_rvt w=27e-9 l=20e-9 nfin=60
+m26 net16 vbiasp net015 net015 pmos_rvt w=27e-9 l=20e-9 nfin=60
+m23 voutp vbiasp net024 net024 pmos_rvt w=27e-9 l=20e-9 nfin=120
+m22 vbiasnd vbiasp net06 net06 pmos_rvt w=27e-9 l=20e-9 nfin=120
+m21 net015 net16 vdd! vdd! pmos_rvt w=27e-9 l=20e-9 nfin=5
+m20 net06 net16 vdd! vdd! pmos_rvt w=27e-9 l=20e-9 nfin=10
+m19 net021 net27 vdd! vdd! pmos_rvt w=27e-9 l=20e-9 nfin=5
+m18 net024 net27 vdd! vdd! pmos_rvt w=27e-9 l=20e-9 nfin=10
+.END

CircuitsDatabase/Sized netlists/Low frequency analog/Cascode_current_mirror_OTA/scope.log

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+ScopeSigMgr:loadpffile /scratch/ALIGN_shared/DESIGN_DATABASE/Cascode_current_mirror_ota/cascode_current_mirror_ota.ac0 1 openonly
+# PF:1
+wm geometry .sigmgr._PF:1 232x342+650+350
+pf:read PF:1 v(voutp)
+# WF:1:1
+Graph addsignal {WF:1:1 WF:1:1} -region {new new} -yview {cphasedeg(y) db(y)} -xview {real(x) real(x)} -tracehi {2 2}
+# Signal0 Signal1
+Graph:Select Graph0
+Graph:DSel
+Graph itemselect Signal1 add
+# Signal1
+GrMeas:AtX Graph0 Signal1 {} xyrangeVisible
+# M:0
+Graph:DSel
+GrMeas:Select Graph0 M:0 0 1
+GrMeas:MovePoint Graph0 M:0 0 1.0 41.107192992597
+GrMeas:MoveText Graph0 M:0 0 38 -41
+Graph:DSel
+pf:read PF:1 v(vbiasn)
+# WF:1:2
+Graph addsignal {WF:1:2 WF:1:2} -region {new new} -yview {cphasedeg(y) db(y)} -xview {real(x) real(x)} -tracehi {2 2}
+# Signal2 Signal3
+pf:read PF:1 v(vbiasnd)
+# WF:1:3
+Graph addsignal {WF:1:3 WF:1:3} -region {new new} -yview {cphasedeg(y) db(y)} -xview {real(x) real(x)} -tracehi {2 2}
+# Signal4 Signal5
+Graph:Select Graph0
+Graph:DSel
+Graph itemselect Signal5 add
+# Signal5
+Graph delsignal selected
+Graph:DSel
+Graph itemselect Signal4 add
+# Signal4
+Graph delsignal selected
+Graph:DSel
+Graph itemselect Signal3 add
+# Signal3
+Graph delsignal selected
+Graph:DSel
+Graph itemselect Signal2 add
+# Signal2
+Graph delsignal selected
+Graph:DSel
+Graph itemselect Signal1 add
+# Signal1
+GrMeas:AtX Graph0 Signal1 {} xyrangeVisible
+# M:1
+Graph:DSel
+GrMeas:Select Graph0 M:1 0 1
+GrMeas:MovePoint Graph0 M:1 0 15.908353741528meg 36.072183678407
+GrMeas:MoveText Graph0 M:1 0 29 -38
+GrMeas:MovePoint Graph0 M:1 0 10.759137076061meg 38.093298804738
+Graph:DSel
+Graph axisconfig {AxisY(1,0) AxisX(0)} -range {{55.100621188638 16.289115507289} {820000.0 210meg}}
+Graph:DSel
+Graph axisconfig {AxisY(1,0) AxisX(0)} -range {{51.839661086044 33.045801352959} {2.9meg 18meg}}
+Graph:DSel
+GrMeas:Select Graph0 M:1 0 1
+Graph:DSel
+Graph:DSel
+Graph axisconfig {AxisY(1,0) AxisX(0)} -range {{44.089720715028 27.306366906877} {5.819meg 23.98meg}}
+Graph:DSel
+GrMeas:Select Graph0 M:1 0 1
+GrMeas:MovePoint Graph0 M:1 0 10.512291512583meg 38.194867948802
+GrMeas:MovePoint Graph0 M:1 0 10.664143155914meg 38.1335295172
+Graph:DSel
+Graph axisconfig {AxisX(0) AxisY(0,0) AxisY(1,0)} -range {all all all} -zoomed {0 0 0}
+Graph:DSel
+Graph:DSel
+Graph itemselect Signal1 add
+# Signal1
+GrMeas:AtX Graph0 Signal1 {} xyrangeVisible
+# M:2
+Graph:DSel
+GrMeas:Select Graph0 M:2 0 1
+GrMeas:MovePoint Graph0 M:2 0 809.58035411885meg 3.5726825380104
+GrMeas:MoveText Graph0 M:2 0 -68 28
+Graph:DSel
+Graph axisconfig {AxisY(1,0) AxisX(0)} -range {{24.680792411365 -23.571349787069} {67meg 13g}}
+Graph:DSel
+GrMeas:Select Graph0 M:2 0 1
+GrMeas:MovePoint Graph0 M:2 0 1.2178533404354g 0.025102513378729
+Graph:DSel
+GrMeas:Select Graph0 M:2 0 2
+GrMeas:MoveText Graph0 M:2 0 44 -28
+Graph:DSel
+Graph axisconfig {AxisX(0) AxisY(0,0) AxisY(1,0)} -range {all all all} -zoomed {0 0 0}
+Graph:DSel
+GrMeas:Select Graph0 M:2 0 1
+GrMeas:MoveText Graph0 M:2 0 -71 32
+Graph:DSel
+Graph:DSel
+GrMeas:Select Graph0 M:1 0 2
+GrMeas:MoveText Graph0 M:1 0 34 -31
+Graph:DSel
+Graph:DSel
+GrMeas:Select Graph0 M:0 0 2
+GrMeas:MoveText Graph0 M:0 0 41 -30
+Graph:DSel

CircuitsDatabase/Sized netlists/Low frequency analog/Comparator_clocked/Netlist_comparator

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+// Generated for: spectre
+// Generated on: Nov  8 14:55:46 2018
+// Design library name: EnergyHarvesting
+// Design cell name: Comp
+// Design view name: schematic
+simulator lang=spectre
+global 0
+
+// Library name: DC_converter
+// Cell name: NOR
+// View name: schematic
+subckt NOR GND VDD VIN1 VIN2 VOUT
+    M0 (VOUT VIN1 GND GND) nch l=60n w=150.0n m=1 nf=1 
+    M1 (VOUT VIN2 GND GND) nch l=60n w=150.0n m=1 nf=1 
+    M3 (VOUT VIN1 net14 VDD) pch l=60n w=600n m=1 nf=1 
+    M2 (net14 VIN2 VDD VDD) pch l=60n w=600n m=1 nf=1 
+ends NOR
+// End of subcircuit definition.
+
+// Library name: EnergyHarvesting
+// Cell name: Comp
+// View name: schematic
+M2 (OUT OUTP net021 VDD) pch l=60n w=3u m=1 nf=1 
+M4 (OUTP OUT net020 VDD) pch l=60n w=3u m=1 nf=1 
+M3 (net023 CLK VDD VDD) pch l=60n w=300n m=1 nf=1 
+I1 (GND VDD OUT Q QB) NOR
+I0 (GND VDD OUTP QB Q) NOR
+M0 (net020 VINP net023 VDD) pch_25 l=20u w=400n m=1 nf=1 
+M1 (net021 VINN net023 VDD) pch_25 l=20u w=400n m=1 nf=1 
+M12 (net021 CLK GND GND) nch l=60n w=120.0n m=1 nf=1 
+M11 (net020 CLK GND GND) nch l=60n w=120.0n m=1 nf=1 
+M10 (net020 CLK net021 GND) nch l=60n w=120.0n m=1 nf=1 
+M9 (OUT CLK GND GND) nch l=60n w=200n m=1 nf=1 
+M6 (OUT OUTP GND GND) nch l=60n w=200n m=1 nf=1 
+M7 (OUTP OUT GND GND) nch l=60n w=200n m=1 nf=1 
+M8 (OUTP CLK GND GND) nch l=60n w=200n m=1 nf=1 
+

CircuitsDatabase/Sized netlists/Low frequency analog/Comparator_clocked/README.md

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+## Gate driver circuit for a DLDO
+
+### Circuit Description
+
+This circuit is a part of the gate driver circuitry in a digital low voltage dropout regulator [1]. This circuit drives PMOS power transistors that supply a load current to the output at a given voltage. 
+
+The block diagram of the system is shown in the figure below.
+
+![Block diagram](Block_diagram_DLDO.PNG)
+
+The diagram of the circuit is as follows.
+
+![Circuit diagram](Circuit_diagram_gate_driver.PNG)
+
+### Pin description
+
+* Din - input pulse waveform
+* Dout - inverted output pulse waveform
+* Vb - gate voltage of transistor in triode that changes the on resistance
+* SS - steady state detection signal switch
+* SS bar - inverted steady state detection signal switch
+
+The operation of the circuit is highlighted below.
+
+![Working](Concept_gate_driver_DLDO.PNG)
+
+When the steady state detection is low, gate driver is a combination of an inverter with a voltage divider. Dout is at a voltage (eg. 250 mV) depending on the ratio of the resistors. When the steady state detection signal is high, the input is maintained constant, the voltage divider also incorporates the resistance contributed by the switch controlled by Vb. As Vb changes, Dout changes.
+
+### Netlist description
+
+* Din - input
+* Dout - output
+* Vb - control (similar to diagram)
+* ss - steady state detection signal 
+* ss_bar_nmos - nmos switch controlled by ss_bar
+* ss_bar_pmos - pmos switch controlled by ss_bar
+* Lres_nmos - on voltage of large nmos resistor
+* Lres_pmos - on voltage of large pmos resistor
+* Sres_nmos - on voltage of small nmos resistor
+* Sres_pmos - on voltage of small pmos resistor
+
+### Initial setup + Testbench
+
+To test this circuit, give a clock waveform at Din and observe Dout in steady state and not in steady state. In steady state, Vb can be changed to observe a change in Dout.
+
+### Constraints
+
+* In steady state there is power dissipation through the voltage divider and any added parasitic routing
+* The capacitance at the output will lower the speed of switching when not in steady state

CircuitsDatabase/Sized netlists/Low frequency analog/Comparator_not_clocked/Constraints.txt

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+Constraints for the comparator circuit
+
+Initial pre-amplifier stage
+- matching between the differential pair and current mirror
+- symmetry
+
+Decision making stage
+- symmetry
+
+Output buffer
+- None

CircuitsDatabase/Sized netlists/Low frequency analog/Comparator_not_clocked/Netlist

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+// Generated for: spectre
+// Generated on: Nov  2 10:37:45 2018
+// Design library name: DC_converter
+// Design cell name: 23Dec_2017_comparator_symbol
+// Design view name: schematic
+simulator lang=spectre
+global 0
+
+// Library name: DC_converter
+// Cell name: 23Dec_2017_comparator_symbol
+// View name: schematic
+M21 (net44 cgnd Vdd Vdd) pch l=1.32u w=120.0n m=1 nf=1 
+M5 (net10 Vn net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M0 (net5 Vp net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M11 (net7 net44 cgnd cgnd) nmos_rf lr=120.0n wr=1.2u nr=1 
+M9 (net44 net44 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M10 (Vop Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M8 (Von Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M7 (Von Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M6 (Vop Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M20 (net18 net18 cgnd cgnd) nmos_rf lr=120.0n wr=6u nr=1 
+M18 (net17 net13 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M16 (Vout net23 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M14 (net23 Vop net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M12 (net13 Von net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 
+M3 (Vop net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 
+M2 (net5 net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 
+M4 (Von net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 
+M1 (net10 net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 
+M19 (net14 net13 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 
+M17 (Vout net23 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 
+M15 (net23 Vop net14 net14) pmos_rf lr=120.0n wr=900n nr=1 
+M13 (net13 Von net14 net14) pmos_rf lr=120.0n wr=900n nr=1 
+