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class A...
... new SimpleDevice(...)
... TLRegisterNode(...)
... new AImp()
class AImp...
val test1 = RegInit(666.U(32.W))
outer.node.regmap(0x00 -> Seq(RegField.r(32, test1)),)
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Hi!
I add a register to my hardware with
and test it succesfully with verilator:
Output:
However, when trying to do an FPGA-Simulation with a custom Linux kernel, the register is always zero:
What am I missing?
Thank you,
g
P.S.: I also asked here: https://groups.google.com/g/chipyard/c/t5H38HkG50U
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