From ebce8b6d1f75242d1654228ec479d8575a80a3ad Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 20 Mar 2024 09:34:21 -0700 Subject: [PATCH 01/11] Add Ara --- .gitmodules | 3 +++ build.sbt | 7 +++++- generators/ara | 1 + .../src/main/scala/config/AraConfigs.scala | 25 +++++++++++++++++++ 4 files changed, 35 insertions(+), 1 deletion(-) create mode 160000 generators/ara create mode 100644 generators/chipyard/src/main/scala/config/AraConfigs.scala diff --git a/.gitmodules b/.gitmodules index 1fd75921f6..75643ec7f9 100644 --- a/.gitmodules +++ b/.gitmodules @@ -154,3 +154,6 @@ [submodule "software/firesim-paper-workloads"] path = software/firesim-paper-workloads url = https://github.com/firesim/firesim-paper-workloads.git +[submodule "generators/ara"] + path = generators/ara + url = https://github.com/ucb-bar/ara-wrapper.git diff --git a/build.sbt b/build.sbt index db68f56a95..ff69763563 100644 --- a/build.sbt +++ b/build.sbt @@ -176,7 +176,7 @@ lazy val chipyard = (project in file("generators/chipyard")) dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, constellation, mempress, barf, shuttle, caliptra_aes, rerocc, - compressacc, saturn) + compressacc, saturn, ara) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -241,6 +241,11 @@ lazy val cva6 = (project in file("generators/cva6")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) +lazy val ara = (project in file("generators/ara")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val ibex = (project in file("generators/ibex")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/generators/ara b/generators/ara new file mode 160000 index 0000000000..3784618480 --- /dev/null +++ b/generators/ara @@ -0,0 +1 @@ +Subproject commit 3784618480eef0c622e5077690182cd8cfd1dded diff --git a/generators/chipyard/src/main/scala/config/AraConfigs.scala b/generators/chipyard/src/main/scala/config/AraConfigs.scala new file mode 100644 index 0000000000..5c564bd1a1 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/AraConfigs.scala @@ -0,0 +1,25 @@ +package chipyard + +import org.chipsalliance.cde.config.{Config} +import saturn.common.{VectorParams} + +// Rocket-integrated configs +class Ara2LaneRocketConfig extends Config( + new ara.WithAraRocketVectorUnit(2) ++ + new chipyard.harness.WithCospike ++ + new chipyard.config.WithTraceIO ++ + new freechips.rocketchip.subsystem.WithRocketCease(false) ++ + new freechips.rocketchip.subsystem.WithRocketDebugROB ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + + +class Ara4LaneRocketConfig extends Config( + new ara.WithAraRocketVectorUnit(4) ++ + new chipyard.harness.WithCospike ++ + new chipyard.config.WithTraceIO ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new freechips.rocketchip.subsystem.WithRocketCease(false) ++ + new freechips.rocketchip.subsystem.WithRocketDebugROB ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) From 807dc1ed27fcddf08add946bfc0e9eb68b8c15d2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 20 Mar 2024 09:36:39 -0700 Subject: [PATCH 02/11] special case ara for verilator --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index d7b1f14879..5df4315978 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -129,7 +129,7 @@ CHIPYARD_VERILATOR_FLAGS := \ # options dependent on whether external IP (cva6/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! PLATFORM_OPTS = $(shell \ - if grep -qiP "module\s+(CVA6|NVDLA)" $(GEN_COLLATERAL_DIR)/*.*v; \ + if grep -qiP "module\s+(CVA6|NVDLA|Ara)" $(GEN_COLLATERAL_DIR)/*.*v; \ then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) From 5fb0ce15e7a4c0290f3afee4ac3c8cb584bd77a9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 20 Mar 2024 16:39:33 -0700 Subject: [PATCH 03/11] Bump ara --- common.mk | 1 + generators/ara | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 759852c6a9..7c3d159ae2 100644 --- a/common.mk +++ b/common.mk @@ -64,6 +64,7 @@ HELP_COMMANDS += \ ######################################################################################### include $(base_dir)/generators/cva6/cva6.mk include $(base_dir)/generators/ibex/ibex.mk +include $(base_dir)/generators/ara/ara.mk include $(base_dir)/generators/tracegen/tracegen.mk include $(base_dir)/generators/nvdla/nvdla.mk include $(base_dir)/tools/torture.mk diff --git a/generators/ara b/generators/ara index 3784618480..409f00d5c7 160000 --- a/generators/ara +++ b/generators/ara @@ -1 +1 @@ -Subproject commit 3784618480eef0c622e5077690182cd8cfd1dded +Subproject commit 409f00d5c78563ccd310e2be5ed2db089f600197 From 15884bd9b0784c2814817734b815996105a8d08a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 22 Mar 2024 16:18:41 -0700 Subject: [PATCH 04/11] Update init-submods for ara --- scripts/init-submodules-no-riscv-tools-nolog.sh | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index dec397c34f..4e2ed43eca 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -70,6 +70,7 @@ cd "$RDIR" for name in \ toolchains/*-tools/* \ generators/cva6 \ + generators/ara \ generators/nvdla \ toolchains/libgloss \ generators/gemmini \ @@ -115,6 +116,10 @@ cd "$RDIR" git submodule update --init generators/nvdla git -C generators/nvdla submodule update --init src/main/resources/hw + # Non-recursive clone to exclude ara submods + git submodule update --init generators/ara + git -C generators/ara submodule update --init ara + # Non-recursive clone to exclude gemmini-software git submodule update --init generators/gemmini git -C generators/gemmini/ submodule update --init --recursive software/gemmini-rocc-tests From 52d1c4816898878835335e806578519f1bf39cc8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 6 Aug 2024 18:12:29 -0700 Subject: [PATCH 05/11] Update Ara submodule --- generators/ara | 2 +- .../chipyard/src/main/scala/config/AraConfigs.scala | 12 ++---------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/generators/ara b/generators/ara index 409f00d5c7..662990076a 160000 --- a/generators/ara +++ b/generators/ara @@ -1 +1 @@ -Subproject commit 409f00d5c78563ccd310e2be5ed2db089f600197 +Subproject commit 662990076aeb985ed99865527e9d7fe578a35e40 diff --git a/generators/chipyard/src/main/scala/config/AraConfigs.scala b/generators/chipyard/src/main/scala/config/AraConfigs.scala index 5c564bd1a1..b797dcc2e9 100644 --- a/generators/chipyard/src/main/scala/config/AraConfigs.scala +++ b/generators/chipyard/src/main/scala/config/AraConfigs.scala @@ -6,20 +6,12 @@ import saturn.common.{VectorParams} // Rocket-integrated configs class Ara2LaneRocketConfig extends Config( new ara.WithAraRocketVectorUnit(2) ++ - new chipyard.harness.WithCospike ++ - new chipyard.config.WithTraceIO ++ - new freechips.rocketchip.subsystem.WithRocketCease(false) ++ - new freechips.rocketchip.subsystem.WithRocketDebugROB ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class Ara4LaneRocketConfig extends Config( new ara.WithAraRocketVectorUnit(4) ++ - new chipyard.harness.WithCospike ++ - new chipyard.config.WithTraceIO ++ new chipyard.config.WithSystemBusWidth(128) ++ - new freechips.rocketchip.subsystem.WithRocketCease(false) ++ - new freechips.rocketchip.subsystem.WithRocketDebugROB ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.rocket.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) From 6e67d33518044ad37b6c4aadcc49d84d9ff3f361 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 6 Aug 2024 18:16:51 -0700 Subject: [PATCH 06/11] Add ara dependency on shuttle --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index ff69763563..28d912c492 100644 --- a/build.sbt +++ b/build.sbt @@ -242,7 +242,7 @@ lazy val cva6 = (project in file("generators/cva6")) .settings(commonSettings) lazy val ara = (project in file("generators/ara")) - .dependsOn(rocketchip) + .dependsOn(rocketchip, shuttle) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) From 7a9972f9bde35a5298e91e81fc426d6b7ec98b3d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 7 Aug 2024 15:13:43 -0700 Subject: [PATCH 07/11] Update Ara and add CI --- .github/scripts/defaults.sh | 3 ++- .github/scripts/run-tests.sh | 7 ++++++ .github/workflows/chipyard-run-tests.yml | 24 +++++++++++++++++++ generators/ara | 2 +- .../src/main/scala/config/AraConfigs.scala | 23 ++++++++++++++---- 5 files changed, 53 insertions(+), 6 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 74ce82772f..e6f6d9ebc9 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -27,7 +27,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" -grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector" +grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector chipyard-shuttleara" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4" grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters" @@ -75,6 +75,7 @@ mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig" mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig" mapping["chipyard-rocketvector"]=" CONFIG=MINV128D64RocketConfig" mapping["chipyard-shuttlevector"]=" CONFIG=GENV256D128ShuttleConfig" +mapping["chipyard-shuttleara"]=" CONFIG=V4096Ara2LaneShuttleConfig USE_ARA=1" mapping["constellation"]=" SUB_PROJECT=constellation" mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 19cf50cd36..68e8687830 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -144,6 +144,13 @@ case $1 in run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1 run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1 ;; + chipyard-shuttleara) + run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1 + # Ara cannot run strcmp + # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-strcmp.riscv LOADMEM=1 + run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1 + run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1 + ;; tracegen) run_tracegen ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 6de3f9e66c..bd3bda1467 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -844,6 +844,29 @@ jobs: group-key: "group-accels" project-key: "chipyard-shuttlevector" + chipyard-shuttleara-run-tests: + name: chipyard-shuttleara-run-tests + needs: prepare-chipyard-accels + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-accels" + project-key: "chipyard-shuttleara" + chipyard-gemmini-run-tests: name: chipyard-gemmini-run-tests needs: prepare-chipyard-accels @@ -1236,6 +1259,7 @@ jobs: chipyard-rerocc-run-tests, chipyard-rocketvector-run-tests, chipyard-shuttlevector-run-tests, + chipyard-shuttleara-run-tests, chipyard-gemmini-run-tests, chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, chipyard-prefetchers-run-tests, diff --git a/generators/ara b/generators/ara index 662990076a..a229662890 160000 --- a/generators/ara +++ b/generators/ara @@ -1 +1 @@ -Subproject commit 662990076aeb985ed99865527e9d7fe578a35e40 +Subproject commit a22966289070f1c87fddde57adddf55057b39868 diff --git a/generators/chipyard/src/main/scala/config/AraConfigs.scala b/generators/chipyard/src/main/scala/config/AraConfigs.scala index b797dcc2e9..803ff6212e 100644 --- a/generators/chipyard/src/main/scala/config/AraConfigs.scala +++ b/generators/chipyard/src/main/scala/config/AraConfigs.scala @@ -4,14 +4,29 @@ import org.chipsalliance.cde.config.{Config} import saturn.common.{VectorParams} // Rocket-integrated configs -class Ara2LaneRocketConfig extends Config( - new ara.WithAraRocketVectorUnit(2) ++ +class V4096Ara2LaneRocketConfig extends Config( + new ara.WithAraRocketVectorUnit(4096, 2) ++ new freechips.rocketchip.rocket.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -class Ara4LaneRocketConfig extends Config( - new ara.WithAraRocketVectorUnit(4) ++ +class V8192Ara4LaneRocketConfig extends Config( + new ara.WithAraRocketVectorUnit(8192, 4) ++ new chipyard.config.WithSystemBusWidth(128) ++ new freechips.rocketchip.rocket.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) + + +// Shuttle-integrated configs +class V4096Ara2LaneShuttleConfig extends Config( + new ara.WithAraShuttleVectorUnit(4096, 2) ++ + new shuttle.common.WithNShuttleCores(1) ++ + new chipyard.config.AbstractConfig) + + +class V8192Ara4LaneShuttleConfig extends Config( + new ara.WithAraShuttleVectorUnit(8192, 4) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new shuttle.common.WithShuttleTileBeatBytes(16) ++ + new shuttle.common.WithNShuttleCores(1) ++ + new chipyard.config.AbstractConfig) From aafb557a848fe0d408af86a58abed27e9bdbb44a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 7 Aug 2024 15:21:18 -0700 Subject: [PATCH 08/11] Update docs on Ara and Saturn --- docs/Generators/Ara.rst | 14 ++++++++++++++ docs/Generators/Saturn.rst | 1 + docs/Generators/index.rst | 1 + 3 files changed, 16 insertions(+) create mode 100644 docs/Generators/Ara.rst diff --git a/docs/Generators/Ara.rst b/docs/Generators/Ara.rst new file mode 100644 index 0000000000..41c35dd121 --- /dev/null +++ b/docs/Generators/Ara.rst @@ -0,0 +1,14 @@ +Ara +=== + +`Ara `__ is a RISC-V vector unit developed by the PULP project. +The Ara vector unit supports integration with either the Rocket or Shuttle in-order cores, following a similar methodology as used in the original Ara+CVA6 system. +Example Ara configurations are listed in ``generators/chipyard/src/main/scala/config/AraConfigs.scala``. + +.. Warning:: Ara only supports a partial subset of the full V-extension. Notably, we do not support virtual memory or precise traps with Ara. + +To compile simulators using Ara, you must pass an additional ``USE_ARA`` flag to the makefile. + +.. code-block:: shell + + make CONFIG=V4096Ara2LaneRocketConfig USE_ARA=1 diff --git a/docs/Generators/Saturn.rst b/docs/Generators/Saturn.rst index bbf2988f12..b0021fcfdf 100644 --- a/docs/Generators/Saturn.rst +++ b/docs/Generators/Saturn.rst @@ -5,6 +5,7 @@ Saturn is a parameterized RISC-V Vector Unit generator currently supporting inte Saturn implements a compact short-vector-length vector microarchitecture suitable for deployment in a DSP-optimized core or area-efficient general-purpose core. More documentation on Saturn will be released in the future. +A partial listing of supported Saturn configurations is in ``generators/chipyard/src/main/scala/config/SaturnConfigs.scala``. * Full support for `V` application-profile RVV 1.0 * Precise traps with virtual memory diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 25d4d24430..53a8895f42 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -36,3 +36,4 @@ so changes to the generators themselves will automatically be used when building Mempress CompressAcc Prefetchers + Ara From ddebdc61988fff180c9bff45c0ba27256dd5b233 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 7 Aug 2024 15:41:02 -0700 Subject: [PATCH 09/11] Bump ara pointer --- generators/ara | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/ara b/generators/ara index a229662890..ae77c7985e 160000 --- a/generators/ara +++ b/generators/ara @@ -1 +1 @@ -Subproject commit a22966289070f1c87fddde57adddf55057b39868 +Subproject commit ae77c7985e60afefc1c2bcbe3617ff9f5d3960ad From c1a79f526ec8f06e1226d43f97905dc85197a79d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 7 Aug 2024 16:49:54 -0700 Subject: [PATCH 10/11] Disable verilator builds of Ara --- .github/scripts/defaults.sh | 2 +- .github/scripts/run-tests.sh | 7 ++++--- .github/workflows/chipyard-run-tests.yml | 24 ------------------------ docs/Generators/Ara.rst | 2 ++ 4 files changed, 7 insertions(+), 28 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index e6f6d9ebc9..8d39785260 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -75,7 +75,7 @@ mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig" mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig" mapping["chipyard-rocketvector"]=" CONFIG=MINV128D64RocketConfig" mapping["chipyard-shuttlevector"]=" CONFIG=GENV256D128ShuttleConfig" -mapping["chipyard-shuttleara"]=" CONFIG=V4096Ara2LaneShuttleConfig USE_ARA=1" +mapping["chipyard-shuttleara"]=" CONFIG=V4096Ara2LaneShuttleConfig USE_ARA=1 verilog" mapping["constellation"]=" SUB_PROJECT=constellation" mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 68e8687830..f15b66663b 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -145,11 +145,12 @@ case $1 in run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1 ;; chipyard-shuttleara) - run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1 + # Ara does not work with verilator + # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1 # Ara cannot run strcmp # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-strcmp.riscv LOADMEM=1 - run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1 - run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1 + # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1 + # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1 ;; tracegen) run_tracegen diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index bd3bda1467..6de3f9e66c 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -844,29 +844,6 @@ jobs: group-key: "group-accels" project-key: "chipyard-shuttlevector" - chipyard-shuttleara-run-tests: - name: chipyard-shuttleara-run-tests - needs: prepare-chipyard-accels - runs-on: as4 - steps: - - name: Delete old checkout - run: | - ls -alh . - rm -rf ${{ github.workspace }}/* || true - rm -rf ${{ github.workspace }}/.* || true - ls -alh . - - name: Checkout - uses: actions/checkout@v3 - - name: Git workaround - uses: ./.github/actions/git-workaround - - name: Create conda env - uses: ./.github/actions/create-conda-env - - name: Run tests - uses: ./.github/actions/run-tests - with: - group-key: "group-accels" - project-key: "chipyard-shuttleara" - chipyard-gemmini-run-tests: name: chipyard-gemmini-run-tests needs: prepare-chipyard-accels @@ -1259,7 +1236,6 @@ jobs: chipyard-rerocc-run-tests, chipyard-rocketvector-run-tests, chipyard-shuttlevector-run-tests, - chipyard-shuttleara-run-tests, chipyard-gemmini-run-tests, chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, chipyard-prefetchers-run-tests, diff --git a/docs/Generators/Ara.rst b/docs/Generators/Ara.rst index 41c35dd121..08c17c5d0a 100644 --- a/docs/Generators/Ara.rst +++ b/docs/Generators/Ara.rst @@ -9,6 +9,8 @@ Example Ara configurations are listed in ``generators/chipyard/src/main/scala/co To compile simulators using Ara, you must pass an additional ``USE_ARA`` flag to the makefile. +.. Note:: Ara only supports VCS for simulation + .. code-block:: shell make CONFIG=V4096Ara2LaneRocketConfig USE_ARA=1 From 7a833f2accae75fd65a42a4662a162e370e7d3cf Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 7 Aug 2024 18:50:41 -0700 Subject: [PATCH 11/11] Add ara to check-commit --- .github/scripts/check-commit.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index c92d10a173..b2a0d1ec0f 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -46,7 +46,7 @@ search () { } -submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn") +submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara") dir="generators" branches=("master" "main" "dev") search