From d3165812acd1e8fdbd642b9b68205445340726cd Mon Sep 17 00:00:00 2001 From: "Tadashi G. Takaoka" Date: Tue, 28 Jan 2025 01:03:31 +0900 Subject: [PATCH] [TMS32010] Add TMS3202x variants --- README.md | 16 +- README_.adoc | 16 +- src/Makefile.arch | 4 +- src/asm_tms32010.cpp | 137 ++-- src/asm_tms32010.h | 3 + src/config_tms32010.h | 39 +- src/dis_tms32010.cpp | 125 ++- src/dis_tms32010.h | 14 + src/entry_tms32010.h | 11 + src/table_tms32010.cpp | 379 ++++++++- src/text_common.cpp | 6 + src/text_common.h | 6 + src/text_f3850.cpp | 4 +- src/text_f3850.h | 4 +- src/text_i8080.cpp | 2 +- src/text_i8080.h | 2 +- src/text_mc6809.cpp | 2 +- src/text_mc6809.h | 2 +- src/text_tms32010.cpp | 86 ++- src/text_tms32010.h | 84 +- src/text_tms9900.cpp | 2 +- src/text_tms9900.h | 2 +- src/text_z8000.cpp | 2 +- src/text_z8000.h | 2 +- test/autogen/gen_tms32010.asm | 28 +- test/autogen/gen_tms320c25.asm | 1195 +++++++++++++++++++++++++++++ test/autogen/gen_tms320c26.asm | 1194 ++++++++++++++++++++++++++++ test/gen_tms32010.cpp | 1 + test/reference/test_tms3202x.inc | 137 ++++ test/reference/test_tms320c25.asm | 25 + test/reference/test_tms320c25.hex | 24 + test/reference/test_tms320c26.asm | 25 + test/reference/test_tms320c26.hex | 24 + test/reference/test_tms320c2x.inc | 47 ++ test/test_asm_tms32010.cpp | 875 ++++++++++++++++++++- test/test_dis_tms32010.cpp | 1071 +++++++++++++++++++++++++- 36 files changed, 5413 insertions(+), 183 deletions(-) create mode 100644 test/autogen/gen_tms320c25.asm create mode 100644 test/autogen/gen_tms320c26.asm create mode 100644 test/reference/test_tms3202x.inc create mode 100644 test/reference/test_tms320c25.asm create mode 100644 test/reference/test_tms320c25.hex create mode 100644 test/reference/test_tms320c26.asm create mode 100644 test/reference/test_tms320c26.hex create mode 100644 test/reference/test_tms320c2x.inc diff --git a/README.md b/README.md index 65ad346a7..689514aae 100644 --- a/README.md +++ b/README.md @@ -79,9 +79,10 @@ It can generate Intel HEX or Motorola S-Record output. MC68HC08 MC6809 HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039 i8048 i80C39 i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88 TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 - F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 - MC68000 MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 - NS32032 MN1610 MN1613 MN1613A J11 T11 + F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 TMS32020 TMS320C25 + TMS320C26 i8086 i80186 V30 i8096 MC68000 MC68010 TMS9900 TMS9980 + TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032 MN1610 MN1613 MN1613A + J11 T11 -o : output file -l : list file -S[] : output Motorola S-Record format @@ -116,9 +117,10 @@ It can read Intel HEX or Motorola S-Record input. MC68HC08 MC6809 HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039 i8048 i80C39 i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88 TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 - F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 - MC68000 MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 - NS32032 MN1610 MN1613 MN1613A J11 T11 + F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 TMS32020 TMS320C25 + TMS320C26 i8086 i80186 V30 i8096 MC68000 MC68010 TMS9900 TMS9980 + TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032 MN1610 MN1613 MN1613A + J11 T11 -o : output file -l : list file : file can be Motorola S-Record or Intel HEX format @@ -146,6 +148,8 @@ It can read Intel HEX or Motorola S-Record input. --short-direct : use |addr| for short direct notation (bool: Z8001) --string-insn : string instruction as repeat operand (bool: 8086) --use-absolute : zero register indexing as absolute addressing (bool: 8096) + --use-aux-name : use aux register name ARn (bool: 32010) + --use-port-name : use port name PAn (bool: 32010) --use-register : use register name Rn (bool: 1802) --use-sharp : use # (default =) for immediate (bool: 8070) --work-register : prefer work register name than alias address (bool: Z8) diff --git a/README_.adoc b/README_.adoc index d779a6e8b..e4da15888 100644 --- a/README_.adoc +++ b/README_.adoc @@ -83,9 +83,10 @@ usage: asm [-o ] [-l ] MC68HC08 MC6809 HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039 i8048 i80C39 i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88 TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 - F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 - MC68000 MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 - NS32032 MN1610 MN1613 MN1613A J11 T11 + F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 TMS32020 TMS320C25 + TMS320C26 i8086 i80186 V30 i8096 MC68000 MC68010 TMS9900 TMS9980 + TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032 MN1610 MN1613 MN1613A + J11 T11 -o : output file -l : list file -S[] : output Motorola S-Record format @@ -122,9 +123,10 @@ usage: dis -C [-o ] [-l ] MC68HC08 MC6809 HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039 i8048 i80C39 i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88 TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 - F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 - MC68000 MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 - NS32032 MN1610 MN1613 MN1613A J11 T11 + F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 TMS32020 TMS320C25 + TMS320C26 i8086 i80186 V30 i8096 MC68000 MC68010 TMS9900 TMS9980 + TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032 MN1610 MN1613 MN1613A + J11 T11 -o : output file -l : list file : file can be Motorola S-Record or Intel HEX format @@ -152,6 +154,8 @@ usage: dis -C [-o ] [-l ] --short-direct : use |addr| for short direct notation (bool: Z8001) --string-insn : string instruction as repeat operand (bool: 8086) --use-absolute : zero register indexing as absolute addressing (bool: 8096) + --use-aux-name : use aux register name ARn (bool: 32010) + --use-port-name : use port name PAn (bool: 32010) --use-register : use register name Rn (bool: 1802) --use-sharp : use # (default =) for immediate (bool: 8070) --work-register : prefer work register name than alias address (bool: Z8) diff --git a/src/Makefile.arch b/src/Makefile.arch index 7f7691831..88f282aba 100644 --- a/src/Makefile.arch +++ b/src/Makefile.arch @@ -69,7 +69,7 @@ TGT_pdp11 = j11 t11 TGT_pdp8 = im6100 hd6120 TGT_scn2650 = scn2650 TGT_tlcs90 = tlcs90 -TGT_tms32010 = tms32010 +TGT_tms32010 = tms32010 tms320c25 tms320c26 TGT_tms7000 = tms7000 TGT_tms9900 = tms9900 tms9980 tms9995 tms99105 tms99110 TGT_z8000 = z8001 z8002 z8k1 z8k2 @@ -124,6 +124,8 @@ CPU_scn2650 = 2650 CPU_t11 = T11 CPU_tlcs90 = TLCS90 CPU_tms32010 = 32010 +CPU_tms320c25 = 320C25 +CPU_tms320c26 = 320C26 CPU_tms7000 = TMS7000 CPU_tms9900 = TMS9900 CPU_tms99105 = TMS99105 diff --git a/src/asm_tms32010.cpp b/src/asm_tms32010.cpp index ca3c60bf5..4bf80a248 100644 --- a/src/asm_tms32010.cpp +++ b/src/asm_tms32010.cpp @@ -57,34 +57,67 @@ AsmTms32010::AsmTms32010(const ValueParser::Plugins &plugins) reset(); } +void AsmTms32010::encodeIndirect(AsmInsn &insn, const Operand &op) const { + static constexpr uint8_t MAR[] PROGMEM = { + 0x80, // M_ARP: * + 0xA0, // M_INC: *+ + 0x90, // M_DEC: *- + 0xE0, // M_INC0: *0+ + 0xD0, // M_DEC0: *0- + 0xF0, // M_IBR0: *BR0+ + 0xC0, // M_DBR0: *BR0- + }; + if (op.mode >= M_ARP) + insn.embed(pgm_read_byte(&MAR[op.mode - M_ARP])); +} + +void AsmTms32010::encodeDirect(AsmInsn &insn, const Operand &op) const { + const auto dma = op.val.getUnsigned(); + if (op.val.isNegative() || !validDmAddr(insn.opCode(), dma)) + insn.setErrorIf(op, OVERFLOW_RANGE); + insn.embed(dma & 0x7F); +} + +void AsmTms32010::encodeNextAR(AsmInsn &insn, const Operand &op) const { + if ((insn.opCode() & 0x80) == 0) + return; + if (op.mode == M_NONE) { + if (is3201x()) + insn.embed(8); + return; + } + auto val = op.val.getUnsigned(); + if (!isAR(decodeAR(val))) { + val &= maxAR(); + insn.setErrorIf(op, UNKNOWN_REGISTER); + } + if (is3202x()) + insn.embed(8); + insn.embed(val); +} + void AsmTms32010::encodeOperand(AsmInsn &insn, const Operand &op, AddrMode mode) const { insn.setErrorIf(op); auto val = op.val.getUnsigned(); + auto max = UINT16_MAX; switch (mode) { case M_MAM: - switch (op.mode) { - case M_ARP: - insn.embed(0x88); - break; - case M_INC: - insn.embed(0xA8); - break; - case M_DEC: - insn.embed(0x98); - break; - default: - if (!validDmAddr(insn.opCode(), val)) - insn.setErrorIf(op, OVERFLOW_RANGE); - insn.embed(val & 0x7F); - break; + if (op.mode == M_CNST) { + encodeDirect(insn, op); + } else { + encodeIndirect(insn, op); } break; + case M_IND: + case M_MAR: + encodeIndirect(insn, op); + break; case M_LS0: if (val) insn.setErrorIf(op, ILLEGAL_CONSTANT); break; case M_LS3: - if (!(val == 0 || val == 1 || val == 4)) + if (!is320C2x() && !(val == 0 || val == 1 || val == 4)) insn.setErrorIf(op, ILLEGAL_CONSTANT); // Fall-through case M_PA: @@ -98,55 +131,62 @@ void AsmTms32010::encodeOperand(AsmInsn &insn, const Operand &op, AddrMode mode) val &= 15; insn.setErrorIf(op, OVERFLOW_RANGE); } + embed_hi8: insn.embed(val << 8); break; case M_NARP: - if (op.mode != M_NONE) { - if (!isAR(decodeAR(val))) { - val &= maxAR(); - insn.setErrorIf(op, UNKNOWN_REGISTER); - } - insn.setOpCode(insn.opCode() & ~8); - insn.embed(val); - } + encodeNextAR(insn, op); break; case M_AR: - if (!isAR(decodeAR(val))) { - val &= maxAR(); - insn.setErrorIf(op, UNKNOWN_REGISTER); - } - insn.embed(val << 8); - break; case M_ARK: if (!isAR(decodeAR(val))) { val &= maxAR(); insn.setErrorIf(op, UNKNOWN_REGISTER); } - insn.embed(val); - break; + if (mode == M_AR) + goto embed_hi8; + goto embed_const; case M_IM1: - if (op.val.overflow(1)) { - val &= 1; + max = 1; + check_const: + if (op.val.overflow(max)) { + val &= max; insn.setErrorIf(op, OVERFLOW_RANGE); } + embed_const: insn.embed(val); break; + case M_IM2: + max = 3; + goto check_const; + case M_BIT: + max = 15; + goto embed_hi8; case M_IM8: - if (op.val.overflow(UINT8_MAX)) { - val &= UINT8_MAX; - insn.setErrorIf(op, OVERFLOW_RANGE); - } - insn.embed(val); - break; + max = UINT8_MAX; + goto check_const; + case M_IM9: + max = 0x1FF; + goto check_const; case M_IM13: if (op.val.overflow(0x0FFF, -0x1000)) insn.setErrorIf(op, OVERFLOW_RANGE); insn.embed(val & 0x1FFF); break; case M_PM12: - if (op.val.overflow(0x0FFF)) + if (op.val.overflow(0x0FFF)) { + val &= 0x0FFF; + insn.setErrorIf(op, OVERFLOW_RANGE); + } + // Fall-through + case M_PM16: + if (op.val.overflow(UINT16_MAX)) + insn.setErrorIf(op, OVERFLOW_RANGE); + // Fall-through + case M_IM16: + if (op.val.overflowUint16()) insn.setErrorIf(op, OVERFLOW_RANGE); - insn.emitOperand16(val & 0x0FFF); + insn.emitOperand16(val); break; default: break; @@ -160,11 +200,20 @@ Error AsmTms32010::parseOperand(StrScanner &scan, Operand &op) const { return OK; if (p.expect('*')) { + auto s = p; + const auto br = p.iexpect('B') && p.iexpect('R'); + if (!br) + p = s; + const auto ar0 = p.expect('0'); + if (br && !ar0) + return op.setErrorIf(UNKNOWN_OPERAND); if (p.expect('+')) { - op.mode = M_INC; + op.mode = ar0 ? (br ? M_IBR0 : M_INC0) : M_INC; } else if (p.expect('-')) { - op.mode = M_DEC; + op.mode = ar0 ? (br ? M_DBR0 : M_DEC0) : M_DEC; } else { + if (br || ar0) + return op.setErrorIf(UNKNOWN_OPERAND); op.mode = M_ARP; } scan = p; diff --git a/src/asm_tms32010.h b/src/asm_tms32010.h index 8c42bb609..557d4510c 100644 --- a/src/asm_tms32010.h +++ b/src/asm_tms32010.h @@ -30,6 +30,9 @@ struct AsmTms32010 final : Assembler, Config { private: Error parseOperand(StrScanner &scan, Operand &op) const; + void encodeIndirect(AsmInsn &insn, const Operand &op) const; + void encodeDirect(AsmInsn &insn, const Operand &op) const; + void encodeNextAR(AsmInsn &insn, const Operand &op) const; void encodeOperand(AsmInsn &insn, const Operand &op, AddrMode mode) const; Error encodeImpl(StrScanner &scan, Insn &insn) const override; diff --git a/src/config_tms32010.h b/src/config_tms32010.h index da35b9187..382c8c7ff 100644 --- a/src/config_tms32010.h +++ b/src/config_tms32010.h @@ -26,17 +26,32 @@ namespace tms32010 { enum CpuType : uint8_t { TMS32010, TMS32015, + TMS32020, + TMS320C25, + TMS320C26, }; struct Config : ConfigImpl { Config(const InsnTable &table) : ConfigImpl(table, TMS32010) {} + AddressWidth addressWidth() const override { return is3201x() ? ADDRESS_12BIT : ADDRESS_16BIT; } + protected: - uint16_t dataMemoryMax() const { return cpuType() == TMS32010 ? UINT16_C(0x8F) : PAGE1_MAX; } + bool is3201x() const { return cpuType() == TMS32010 || cpuType() == TMS32015; } + bool is3202x() const { return !is3201x(); } + bool is320C2x() const { return cpuType() == TMS320C25 || cpuType() == TMS320C26; } - uint_fast8_t maxAR() const { return 1; } - uint_fast8_t maxPA() const { return 7; } + uint16_t dataMemoryMax() const { + if (is3201x()) { + return cpuType() == TMS32010 ? UINT16_C(0x8F) : PAGE1_MAX; + } else { + return cpuType() == TMS320C26 ? 0x7FF : 0x3FF; + } + } + + uint_fast8_t maxAR() const { return is3201x() ? 1 : 7; } + uint_fast8_t maxPA() const { return is3201x() ? 7 : 15; } bool isAR(RegName name) const { return name >= REG_AR0 && name <= REG_AR0 + maxAR(); } bool isPA(RegName name) const { return name >= REG_PA0 && name <= REG_PA0 + maxPA(); } RegName decodeAR(uint32_t r) const { return r <= maxAR() ? RegName(r + REG_AR0) : REG_UNDEF; } @@ -44,15 +59,22 @@ struct Config bool isSST(opcode_t opc) const { opc >>= 8; - return opc == 0x7C; // SST + return is3201x() ? opc == 0x7C // SST + : (opc & 0xFE) == 0x78; // SST and SST1 } bool validDmAddr(opcode_t opc, uint32_t dma) const { uint16_t min = UINT16_C(0); uint16_t max = dataMemoryMax(); if (isSST(opc)) { - // TMS3201x: SST destination must be in page 1. - min = PAGE1_MIN; + if (is3201x()) { + // TMS3201x: SST destination must be in page 1. + min = PAGE1_MIN; + } else { + // TMS3202x: SST/SST1 destination must be in page 0. + min = PAGE0_MIN; + max = PAGE0_MAX; + } } return dma >= min && dma <= max; } @@ -61,11 +83,14 @@ struct Config auto dma = opc & 0x7F; if (isSST(opc)) { // TMS3201x: SST destination must be in page 1. - return PAGE1_MIN + dma; + // TMS3202x: SST/SST1 destination must be in page 0. + return (is3201x() ? PAGE1_MIN : PAGE0_MIN) + dma; } return dma; } + static constexpr auto PAGE0_MIN = UINT16_C(0x0000); + static constexpr auto PAGE0_MAX = UINT16_C(0x007F); static constexpr auto PAGE1_MIN = UINT16_C(0x0080); static constexpr auto PAGE1_MAX = UINT16_C(0x00FF); }; diff --git a/src/dis_tms32010.cpp b/src/dis_tms32010.cpp index 283c22c15..ef7a2be6c 100644 --- a/src/dis_tms32010.cpp +++ b/src/dis_tms32010.cpp @@ -25,6 +25,15 @@ namespace tms32010 { using namespace reg; using namespace text::common; +namespace { + +const char OPT_BOOL_USE_REG_NAME[] PROGMEM = "use-aux-name"; +const char OPT_DESC_USE_REG_NAME[] PROGMEM = "use aux register name ARn"; +const char OPT_BOOL_USE_PORT_NAME[] PROGMEM = "use-port-name"; +const char OPT_DESC_USE_PORT_NAME[] PROGMEM = "use port name PAn"; + +} // namespace + const ValueFormatter::Plugins &DisTms32010::defaultPlugins() { static const struct final : ValueFormatter::Plugins { const HexFormatter &hex() const override { return _hex; } @@ -36,10 +45,31 @@ const ValueFormatter::Plugins &DisTms32010::defaultPlugins() { } DisTms32010::DisTms32010(const ValueFormatter::Plugins &plugins) - : Disassembler(plugins), Config(TABLE) { + : Disassembler(plugins, &_opt_useAuxName), + Config(TABLE), + _opt_useAuxName(this, &DisTms32010::setUseAuxName, OPT_BOOL_USE_REG_NAME, + OPT_DESC_USE_REG_NAME, &_opt_usePortName), + _opt_usePortName( + this, &DisTms32010::setUsePortName, OPT_BOOL_USE_PORT_NAME, OPT_DESC_USE_PORT_NAME) { reset(); } +void DisTms32010::reset() { + Disassembler::reset(); + setUseAuxName(true); + setUsePortName(true); +} + +Error DisTms32010::setUseAuxName(bool enable) { + _useAuxName = enable; + return OK; +} + +Error DisTms32010::setUsePortName(bool enable) { + _usePortName = enable; + return OK; +} + StrBuffer &DisTms32010::outDirect(StrBuffer &out, DisInsn &insn) const { const auto dma = toDmAddr(insn.opCode()); if (!validDmAddr(insn.opCode(), dma)) @@ -62,33 +92,19 @@ StrBuffer &DisTms32010::outIndirect(StrBuffer &out, uint8_t mam) const { return out; } -StrBuffer &DisTms32010::outModifyAR(StrBuffer &out, uint8_t mam) const { - const auto modify = (mam >> 4) & 7; - if (modify) - out.comma(); - return modify == 0 ? out : outIndirect(out, mam); -} - -namespace { -bool hasNarp(uint_fast8_t mam) { - if ((mam & 0x80) == 0) - return false; - const auto narp = mam & 8; - return narp == 0; -} -} // namespace - -StrBuffer &DisTms32010::outNextArp(StrBuffer &out, uint8_t mam) const { - if (hasNarp(mam)) - outRegName(out.comma(), decodeAR(mam & maxAR())); - return out; +StrBuffer &DisTms32010::outAuxiliary(StrBuffer &out, uint_fast8_t no) const { + no &= maxAR(); + if (_useAuxName) + return outRegName(out, decodeAR(no)); + return outDec(out, no, 3); } -StrBuffer &DisTms32010::outShiftCount(StrBuffer &out, uint8_t count, uint8_t mam) const { - if (count || hasNarp(mam)) - outDec(out.comma(), count, 4); - return out; -} +StrBuffer &DisTms32010::outPort(StrBuffer &out, uint_fast8_t no) const { + no &= maxPA(); + if (_usePortName) + return outRegName(out, decodePA(no)); + return outDec(out, no, 4); +}; StrBuffer &DisTms32010::outProgramAddress(StrBuffer &out, DisInsn &insn) const { const auto pma = insn.readUint16(); @@ -97,6 +113,22 @@ StrBuffer &DisTms32010::outProgramAddress(StrBuffer &out, DisInsn &insn) const { return out; } +bool DisTms32010::hasValue(DisInsn &insn, AddrMode mode) const { + const auto opc = insn.opCode(); + if (mode == M_NARP) { + return is3201x() ? (opc & 0x88) == 0x80 : (opc & 0x88) == 0x88; + } else if (mode == M_LS3) { + return ((opc >> 8) & 7) != 0; + } else if (mode == M_LS4) { + return ((opc >> 8) & 0xF) != 0; + } else if (mode == M_MAR) { + return (opc & 0xF0) != 0x80; + } else if (mode == M_LS0) { + return false; + } + return mode != M_NONE; +} + void DisTms32010::decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode) const { const auto opc = insn.opCode(); switch (mode) { @@ -107,31 +139,40 @@ void DisTms32010::decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode) co outDirect(out, insn); } break; + case M_IND: + case M_MAR: + outIndirect(out, opc); + break; case M_NARP: - outNextArp(out, opc); + case M_ARK: + outAuxiliary(out, opc); break; case M_LS4: - outShiftCount(out, (opc >> 8) & 0xF, opc); + case M_BIT: + outDec(out, opc >> 8, 4); break; case M_LS3: case M_LS0: - outShiftCount(out, (opc >> 8) & 7, opc); + outDec(out, opc >> 8, 3); break; case M_AR: - outRegName(out, decodeAR((opc >> 8) & maxAR())); + outAuxiliary(out, opc >> 8); break; case M_PA: - outRegName(out, decodePA((opc >> 8) & maxPA())); - break; - case M_ARK: - outRegName(out, decodeAR(opc & maxAR())); + outPort(out, opc >> 8); break; case M_IM1: out.letter((opc & 1) == 0 ? '0' : '1'); break; + case M_IM2: + outHex(out, opc & 3, 2); + break; case M_IM8: outDec(out, static_cast(opc), 8); break; + case M_IM9: + outHex(out, opc & 0x1FF, 9, false); + break; case M_IM13: // Sign extends 13-bit number as 0x1000 is a sign bit. outDec(out, signExtend(opc, 13), -13); @@ -139,6 +180,12 @@ void DisTms32010::decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode) co case M_PM12: outProgramAddress(out, insn); break; + case M_IM16: + outHex(out, insn.readUint16(), 16); + break; + case M_PM16: + outAbsAddr(out, insn.readUint16()); + break; default: break; } @@ -153,12 +200,12 @@ Error DisTms32010::decodeImpl(DisMemory &memory, Insn &_insn, StrBuffer &out) co decodeOperand(insn, out, insn.mode1()); const auto mode2 = insn.mode2(); if (mode2 != M_NONE) { - if (!(mode2 == M_LS4 || mode2 == M_LS3 || mode2 == M_LS0 || mode2 == M_NARP)) - out.comma(); - decodeOperand(insn, out, mode2); const auto mode3 = insn.mode3(); - if (mode3 != M_NONE) - decodeOperand(insn, out, mode3); + if (hasValue(insn, mode2) || hasValue(insn, mode3)) { + decodeOperand(insn, out.comma(), mode2); + if (mode3 != M_NONE && hasValue(insn, mode3)) + decodeOperand(insn, out.comma(), mode3); + } } return _insn.setError(insn); } diff --git a/src/dis_tms32010.h b/src/dis_tms32010.h index da0df6962..14d65b652 100644 --- a/src/dis_tms32010.h +++ b/src/dis_tms32010.h @@ -27,7 +27,20 @@ namespace tms32010 { struct DisTms32010 final : Disassembler, Config { DisTms32010(const ValueFormatter::Plugins &plugins = defaultPlugins()); + void reset() override; + + Error setUseAuxName(bool enable); + Error setUsePortName(bool enable); + private: + const BoolOption _opt_useAuxName; + const BoolOption _opt_usePortName; + + bool _useAuxName; + bool _usePortName; + + StrBuffer &outAuxiliary(StrBuffer &out, uint_fast8_t no) const; + StrBuffer &outPort(StrBuffer &out, uint_fast8_t no) const; StrBuffer &outDirect(StrBuffer &out, DisInsn &insn) const; StrBuffer &outIndirect(StrBuffer &out, uint8_t mam) const; StrBuffer &outModifyAR(StrBuffer &out, uint8_t mam) const; @@ -35,6 +48,7 @@ struct DisTms32010 final : Disassembler, Config { StrBuffer &outShiftCount(StrBuffer &out, uint8_t count, uint8_t mam) const; StrBuffer &outProgramAddress(StrBuffer &out, DisInsn &insn) const; void decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode) const; + bool hasValue(DisInsn &insn, AddrMode mode) const; Error decodeImpl(DisMemory &memory, Insn &insn, StrBuffer &out) const override; const ConfigBase &config() const override { return *this; } diff --git a/src/entry_tms32010.h b/src/entry_tms32010.h index 3df4b375a..5a44e5c14 100644 --- a/src/entry_tms32010.h +++ b/src/entry_tms32010.h @@ -29,8 +29,11 @@ enum AddrMode : uint8_t { // T=table, P=parser. M_IM1~M_CNST must be a constant. M_NONE = 0, // TP: No operand M_IM1 = 1, // T_: 1-bit unsigned immediate ---- ---- ---- ---k + M_IM2 = 2, // T_: 2-bit unsigned immediate ---- ---- ---- --kk M_IM8 = 3, // T_: 8-bit unsigned immediate ---- ---- kkkk kkkk + M_IM9 = 4, // T_: 9-bit unsigned immediate ---- ---k kkkk kkkk M_IM13 = 5, // T_: 13-bit signed immediate ---k kkkk kkkk kkkk + M_IM16 = 6, // T_: 16-bit unsigned immediate M_NARP = 7, // T_: Next ARP ---- ---- ---- xyyy M_ARK = 8, // T_: 3-bit AR register ---- ---- ---- -rrr M_AR = 9, // TP: AR[0-7] Auxiliary register ---- -rrr ---- ---- @@ -38,12 +41,20 @@ enum AddrMode : uint8_t { M_LS0 = 11, // T_: 0 constant for SACL ---- -000 ---- ---- M_LS3 = 12, // T_: 3-bit left shift ---- -xxx ---- ---- M_LS4 = 13, // T_: 4-bit left shift ---- ssss ---- ---- + M_BIT = 14, // T_: 4-bit bit position ---- bbbb ---- ---- M_PM12 = 15, // T_: 12-bit program address ---- pppp pppp pppp + M_PM16 = 16, // T_: 16-bit program address M_CNST = 17, // _P: constant M_MAM = 18, // T_: Direct address or M_IND ---- ---- ixxx xxxx + M_IND = 19, // T_: Indirect addressing ---- ---- 1vpm ---- + M_MAR = 20, // T_: Modify AR ---- ---- 1vpm ---- M_ARP = 21, // _P: "*" Indirect addressing M_INC = 22, // _P: "*+" Indirect then auto increment addressing M_DEC = 23, // _P: "*-" Indirect then auto decrement addressing + M_INC0 = 24, // _P: "*0+" Indirect then auto increment by AR0 addressing + M_DEC0 = 25, // _P: "*0-" Indirect then auto decrement by AR0 addressing + M_IBR0 = 26, // _P: "*BR+" Indirect then auto increment by bit-reverse AR0 addressing + M_DBR0 = 27, // _P: "*BR-" Indirect then auto decrement by bit-reverse AR0 addressing }; struct Entry final : entry::Base { diff --git a/src/table_tms32010.cpp b/src/table_tms32010.cpp index f7cced205..f1030f909 100644 --- a/src/table_tms32010.cpp +++ b/src/table_tms32010.cpp @@ -157,6 +157,305 @@ constexpr uint8_t INDEX_TMS32010[] PROGMEM = { 15, // TEXT_ZALS }; +const Entry TABLE_TMS3202X[] PROGMEM = { + E3(0x0000, TEXT_ADD, M_MAM, M_LS4, M_NARP), + E3(0x1000, TEXT_SUB, M_MAM, M_LS4, M_NARP), + E3(0x2000, TEXT_LAC, M_MAM, M_LS4, M_NARP), + E3(0x3000, TEXT_LAR, M_AR, M_MAM, M_NARP), + E2(0x3800, TEXT_MPY, M_MAM, M_NARP), + E2(0x3900, TEXT_SQRA, M_MAM, M_NARP), + E2(0x3C00, TEXT_LT, M_MAM, M_NARP), + E2(0x3D00, TEXT_LTA, M_MAM, M_NARP), + E2(0x3E00, TEXT_LTP, M_MAM, M_NARP), + E2(0x3F00, TEXT_LTD, M_MAM, M_NARP), + E2(0x4000, TEXT_ZALH, M_MAM, M_NARP), + E2(0x4100, TEXT_ZALS, M_MAM, M_NARP), + E2(0x4200, TEXT_LACT, M_MAM, M_NARP), + E2(0x4400, TEXT_SUBH, M_MAM, M_NARP), + E2(0x4500, TEXT_SUBS, M_MAM, M_NARP), + E2(0x4600, TEXT_SUBT, M_MAM, M_NARP), + E2(0x4700, TEXT_SUBC, M_MAM, M_NARP), + E2(0x4800, TEXT_ADDH, M_MAM, M_NARP), + E2(0x4900, TEXT_ADDS, M_MAM, M_NARP), + E2(0x4A00, TEXT_ADDT, M_MAM, M_NARP), + E2(0x4B00, TEXT_RPT, M_MAM, M_NARP), + E2(0x4C00, TEXT_XOR, M_MAM, M_NARP), + E2(0x4D00, TEXT_OR, M_MAM, M_NARP), + E2(0x4E00, TEXT_AND, M_MAM, M_NARP), + E2(0x5000, TEXT_LST, M_MAM, M_NARP), + E2(0x5100, TEXT_LST1, M_MAM, M_NARP), + E2(0x5200, TEXT_LDP, M_MAM, M_NARP), + E2(0x5300, TEXT_LPH, M_MAM, M_NARP), + E2(0x5400, TEXT_PSHD, M_MAM, M_NARP), + E0(0x5500, TEXT_NOP), + E1(0x5588, TEXT_LARP, M_ARK), + E2(0x5500, TEXT_MAR, M_MAM, M_NARP), + E2(0x5600, TEXT_DMOV, M_MAM, M_NARP), + E2(0x5700, TEXT_BITT, M_MAM, M_NARP), + E2(0x5800, TEXT_TBLR, M_MAM, M_NARP), + E2(0x5900, TEXT_TBLW, M_MAM, M_NARP), + E2(0x5A00, TEXT_SQRS, M_MAM, M_NARP), + E2(0x5B00, TEXT_LTS, M_MAM, M_NARP), + E3(0x5C00, TEXT_MACD, M_PM16, M_MAM, M_NARP), + E3(0x5D00, TEXT_MAC, M_PM16, M_MAM, M_NARP), + E3(0x6000, TEXT_SACL, M_MAM, M_LS3, M_NARP), + E3(0x6800, TEXT_SACH, M_MAM, M_LS3, M_NARP), + E3(0x7000, TEXT_SAR, M_AR, M_MAM, M_NARP), + E2(0x7800, TEXT_SST, M_MAM, M_NARP), + E2(0x7900, TEXT_SST1, M_MAM, M_NARP), + E2(0x7A00, TEXT_POPD, M_MAM, M_NARP), + E3(0x8000, TEXT_IN, M_MAM, M_PA, M_NARP), + E3(0x9000, TEXT_BIT, M_MAM, M_BIT, M_NARP), + E1(0xA000, TEXT_MPYK, M_IM13), + E2(0xC000, TEXT_LARK, M_AR, M_IM8), + E1(0xC800, TEXT_LDPK, M_IM9), + E0(0xCA00, TEXT_ZAC), + E1(0xCA00, TEXT_LACK, M_IM8), + E1(0xCB00, TEXT_RPTK, M_IM8), + E0(0xCE00, TEXT_EINT), + E0(0xCE01, TEXT_DINT), + E0(0xCE02, TEXT_ROVM), + E0(0xCE03, TEXT_SOVM), + E0(0xCE06, TEXT_RSXM), + E0(0xCE07, TEXT_SSXM), + E1(0xCE08, TEXT_SPM, M_IM2), + E0(0xCE0C, TEXT_RXF), + E0(0xCE0D, TEXT_SXF), + E1(0xCE0E, TEXT_FORT, M_IM1), + E0(0xCE14, TEXT_PAC), + E0(0xCE15, TEXT_APAC), + E0(0xCE16, TEXT_SPAC), + E0(0xCE18, TEXT_SFL), + E0(0xCE19, TEXT_SFR), + E0(0xCE1B, TEXT_ABS), + E0(0xCE1C, TEXT_PUSH), + E0(0xCE1D, TEXT_POP), + E0(0xCE1E, TEXT_TRAP), + E0(0xCE1F, TEXT_IDLE), + E0(0xCE20, TEXT_RTXM), + E0(0xCE21, TEXT_STXM), + E0(0xCE23, TEXT_NEG), + E0(0xCE24, TEXT_CALA), + E0(0xCE25, TEXT_BACC), + E0(0xCE26, TEXT_RET), + E0(0xCE27, TEXT_CMPL), + E1(0xCE50, TEXT_CMPR, M_IM2), + E2(0xD000, TEXT_LRLK, M_AR, M_PM16), + E2(0xD001, TEXT_LALK, M_IM16, M_LS4), + E2(0xD002, TEXT_ADLK, M_IM16, M_LS4), + E2(0xD003, TEXT_SBLK, M_IM16, M_LS4), + E2(0xD004, TEXT_ANDK, M_IM16, M_LS4), + E2(0xD005, TEXT_ORK, M_IM16, M_LS4), + E2(0xD006, TEXT_XORK, M_IM16, M_LS4), + E3(0xE000, TEXT_OUT, M_MAM, M_PA, M_NARP), + E3(0xF080, TEXT_BV, M_PM16, M_MAR, M_NARP), + E3(0xF180, TEXT_BGZ, M_PM16, M_MAR, M_NARP), + E3(0xF280, TEXT_BLEZ, M_PM16, M_MAR, M_NARP), + E3(0xF380, TEXT_BLZ, M_PM16, M_MAR, M_NARP), + E3(0xF480, TEXT_BGEZ, M_PM16, M_MAR, M_NARP), + E3(0xF580, TEXT_BNZ, M_PM16, M_MAR, M_NARP), + E3(0xF680, TEXT_BZ, M_PM16, M_MAR, M_NARP), + E3(0xF780, TEXT_BNV, M_PM16, M_MAR, M_NARP), + E3(0xF880, TEXT_BBZ, M_PM16, M_MAR, M_NARP), + E3(0xF980, TEXT_BBNZ, M_PM16, M_MAR, M_NARP), + E3(0xFA80, TEXT_BIOZ, M_PM16, M_MAR, M_NARP), + E3(0xFB80, TEXT_BANZ, M_PM16, M_MAR, M_NARP), + E3(0xFC00, TEXT_BLKP, M_PM16, M_MAM, M_NARP), + E3(0xFD00, TEXT_BLKD, M_PM16, M_MAM, M_NARP), + E3(0xFE80, TEXT_CALL, M_PM16, M_MAR, M_NARP), + E3(0xFF80, TEXT_B, M_PM16, M_MAR, M_NARP), +}; + +constexpr uint8_t INDEX_TMS3202X[] PROGMEM = { + 69, // TEXT_ABS + 0, // TEXT_ADD + 17, // TEXT_ADDH + 18, // TEXT_ADDS + 19, // TEXT_ADDT + 84, // TEXT_ADLK + 23, // TEXT_AND + 86, // TEXT_ANDK + 65, // TEXT_APAC + 105, // TEXT_B + 78, // TEXT_BACC + 101, // TEXT_BANZ + 99, // TEXT_BBNZ + 98, // TEXT_BBZ + 94, // TEXT_BGEZ + 91, // TEXT_BGZ + 100, // TEXT_BIOZ + 47, // TEXT_BIT + 33, // TEXT_BITT + 92, // TEXT_BLEZ + 103, // TEXT_BLKD + 102, // TEXT_BLKP + 93, // TEXT_BLZ + 97, // TEXT_BNV + 95, // TEXT_BNZ + 90, // TEXT_BV + 96, // TEXT_BZ + 77, // TEXT_CALA + 104, // TEXT_CALL + 80, // TEXT_CMPL + 81, // TEXT_CMPR + 55, // TEXT_DINT + 32, // TEXT_DMOV + 54, // TEXT_EINT + 63, // TEXT_FORT + 73, // TEXT_IDLE + 46, // TEXT_IN + 2, // TEXT_LAC + 52, // TEXT_LACK + 12, // TEXT_LACT + 83, // TEXT_LALK + 3, // TEXT_LAR + 49, // TEXT_LARK + 30, // TEXT_LARP + 26, // TEXT_LDP + 50, // TEXT_LDPK + 27, // TEXT_LPH + 82, // TEXT_LRLK + 24, // TEXT_LST + 25, // TEXT_LST1 + 6, // TEXT_LT + 7, // TEXT_LTA + 9, // TEXT_LTD + 8, // TEXT_LTP + 37, // TEXT_LTS + 39, // TEXT_MAC + 38, // TEXT_MACD + 31, // TEXT_MAR + 4, // TEXT_MPY + 48, // TEXT_MPYK + 76, // TEXT_NEG + 29, // TEXT_NOP + 22, // TEXT_OR + 87, // TEXT_ORK + 89, // TEXT_OUT + 64, // TEXT_PAC + 71, // TEXT_POP + 45, // TEXT_POPD + 28, // TEXT_PSHD + 70, // TEXT_PUSH + 79, // TEXT_RET + 56, // TEXT_ROVM + 20, // TEXT_RPT + 53, // TEXT_RPTK + 58, // TEXT_RSXM + 74, // TEXT_RTXM + 61, // TEXT_RXF + 41, // TEXT_SACH + 40, // TEXT_SACL + 42, // TEXT_SAR + 85, // TEXT_SBLK + 67, // TEXT_SFL + 68, // TEXT_SFR + 57, // TEXT_SOVM + 66, // TEXT_SPAC + 60, // TEXT_SPM + 5, // TEXT_SQRA + 36, // TEXT_SQRS + 43, // TEXT_SST + 44, // TEXT_SST1 + 59, // TEXT_SSXM + 75, // TEXT_STXM + 1, // TEXT_SUB + 16, // TEXT_SUBC + 13, // TEXT_SUBH + 14, // TEXT_SUBS + 15, // TEXT_SUBT + 62, // TEXT_SXF + 34, // TEXT_TBLR + 35, // TEXT_TBLW + 72, // TEXT_TRAP + 21, // TEXT_XOR + 88, // TEXT_XORK + 51, // TEXT_ZAC + 10, // TEXT_ZALH + 11, // TEXT_ZALS +}; + +constexpr Entry TABLE_TMS320C2X[] PROGMEM = { + E2(0x3A00, TEXT_MPYA, M_MAM, M_NARP), + E2(0x3B00, TEXT_MPYS, M_MAM, M_NARP), + E2(0x4300, TEXT_ADDC, M_MAM, M_NARP), + E2(0x4F00, TEXT_SUBB, M_MAM, M_NARP), + E3(0x5E80, TEXT_BC, M_PM16, M_MAR, M_NARP), + E3(0x5F80, TEXT_BNC, M_PM16, M_MAR, M_NARP), + E2(0x7B00, TEXT_ZALR, M_MAM, M_NARP), + E2(0x7C00, TEXT_SPL, M_MAM, M_NARP), + E2(0x7D00, TEXT_SPH, M_MAM, M_NARP), + E1(0x7E00, TEXT_ADRK, M_IM8), + E1(0x7F00, TEXT_SBRK, M_IM8), + E1(0xCC00, TEXT_ADDK, M_IM8), + E1(0xCD00, TEXT_SUBK, M_IM8), + E0(0xCE30, TEXT_RC), + E0(0xCE31, TEXT_SC), + E0(0xCE32, TEXT_RTC), + E0(0xCE33, TEXT_STC), + E0(0xCE34, TEXT_ROL), + E0(0xCE35, TEXT_ROR), + E0(0xCE36, TEXT_RFSM), + E0(0xCE37, TEXT_SFSM), + E0(0xCE38, TEXT_RHM), + E0(0xCE39, TEXT_SHM), + E1(0xCE82, TEXT_NORM, M_IND), + E2(0xCF00, TEXT_MPYU, M_MAM, M_NARP), +}; + +constexpr uint8_t INDEX_TMS320C2X[] = { + 2, // TEXT_ADDC + 11, // TEXT_ADDK + 9, // TEXT_ADRK + 4, // TEXT_BC + 5, // TEXT_BNC + 0, // TEXT_MPYA + 1, // TEXT_MPYS + 24, // TEXT_MPYU + 23, // TEXT_NORM + 13, // TEXT_RC + 19, // TEXT_RFSM + 21, // TEXT_RHM + 17, // TEXT_ROL + 18, // TEXT_ROR + 15, // TEXT_RTC + 10, // TEXT_SBRK + 14, // TEXT_SC + 20, // TEXT_SFSM + 22, // TEXT_SHM + 8, // TEXT_SPH + 7, // TEXT_SPL + 16, // TEXT_STC + 3, // TEXT_SUBB + 12, // TEXT_SUBK + 6, // TEXT_ZALR +}; + +constexpr Entry TABLE_TMS32020[] = { + E0(0xCE82, TEXT_NORM), +}; + +constexpr uint8_t INDEX_TMS32020[] = { + 0, // TEXT_NORM +}; + +constexpr Entry TABLE_TMS320CNFx[] PROGMEM = { + E0(0xCE04, TEXT_CNFD), + E0(0xCE05, TEXT_CNFP), +}; + +constexpr uint8_t INDEX_TMS320CNFx[] = { + 0, // TEXT_CNFD + 1, // TEXT_CNFP +}; + +constexpr Entry TABLE_TMS320CONF[] PROGMEM = { + E1(0xCE3C, TEXT_CONF, M_IM2), +}; + +constexpr uint8_t INDEX_TMS320CONF[] = { + 0, // TEXT_CONF +}; // clang-format on using EntryPage = entry::TableBase; @@ -167,9 +466,30 @@ constexpr EntryPage TMS32010_PAGES[] PROGMEM = { using Cpu = entry::CpuBase; +constexpr EntryPage TMS32020_PAGES[] PROGMEM = { + {ARRAY_RANGE(TABLE_TMS3202X), ARRAY_RANGE(INDEX_TMS3202X)}, + {ARRAY_RANGE(TABLE_TMS32020), ARRAY_RANGE(INDEX_TMS32020)}, + {ARRAY_RANGE(TABLE_TMS320CNFx), ARRAY_RANGE(INDEX_TMS320CNFx)}, +}; + +constexpr EntryPage TMS320C25_PAGES[] PROGMEM = { + {ARRAY_RANGE(TABLE_TMS320C2X), ARRAY_RANGE(INDEX_TMS320C2X)}, + {ARRAY_RANGE(TABLE_TMS3202X), ARRAY_RANGE(INDEX_TMS3202X)}, + {ARRAY_RANGE(TABLE_TMS320CNFx), ARRAY_RANGE(INDEX_TMS320CNFx)}, +}; + +constexpr EntryPage TMS320C26_PAGES[] PROGMEM = { + {ARRAY_RANGE(TABLE_TMS320C2X), ARRAY_RANGE(INDEX_TMS320C2X)}, + {ARRAY_RANGE(TABLE_TMS3202X), ARRAY_RANGE(INDEX_TMS3202X)}, + {ARRAY_RANGE(TABLE_TMS320CONF), ARRAY_RANGE(INDEX_TMS320CONF)}, +}; + constexpr Cpu CPU_TABLE[] PROGMEM = { {TMS32010, TEXT_CPU_32010, ARRAY_RANGE(TMS32010_PAGES)}, {TMS32015, TEXT_CPU_32015, ARRAY_RANGE(TMS32010_PAGES)}, + {TMS32020, TEXT_CPU_32020, ARRAY_RANGE(TMS32020_PAGES)}, + {TMS320C25, TEXT_CPU_320C25, ARRAY_RANGE(TMS320C25_PAGES)}, + {TMS320C26, TEXT_CPU_320C26, ARRAY_RANGE(TMS320C26_PAGES)}, }; const Cpu *cpu(CpuType cpuType) { @@ -180,11 +500,13 @@ bool acceptMode(AddrMode opr, AddrMode table) { if (opr == table) return true; if (opr == M_NONE) // These can be ommitted. - return table == M_LS0 || table == M_LS3 || table == M_LS4 || table == M_NARP; + return table == M_LS0 || table == M_LS3 || table == M_LS4 || table == M_MAR || + table == M_NARP; if (opr == M_AR) return table == M_ARK || table == M_NARP; - if (opr == M_ARP || opr == M_INC || opr == M_DEC) - return table == M_MAM; + if (opr == M_ARP || opr == M_INC || opr == M_DEC || opr == M_INC0 || opr == M_DEC0 || + opr == M_IBR0 || opr == M_DBR0) + return table == M_MAM || table == M_IND || table == M_MAR; if (opr == M_CNST) return table == M_MAM || (table >= M_IM1 && table < M_CNST); return false; @@ -201,7 +523,7 @@ Error searchName(CpuType cpuType, AsmInsn &insn) { return insn.getError(); } -bool matchOpCode(DisInsn &insn, const Entry *entry, const EntryPage *) { +bool matchOpCode(DisInsn &insn, const Entry *entry, CpuType cpuType) { auto opc = insn.opCode(); const auto flags = entry->readFlags(); const auto mode1 = flags.mode1(); @@ -210,14 +532,20 @@ bool matchOpCode(DisInsn &insn, const Entry *entry, const EntryPage *) { if ((opc & 0x80) != 0 && (mode2 == M_NARP || mode3 == M_NARP)) { const auto narp = (opc & 8); const auto ar = (opc & 7); - if (opc & 0x46) - return false; // check reserved bits - if (narp && ar) - return false; // check no next ARP + if (cpuType == TMS32010) { + if (opc & 0x46) + return false; // check reserved bits + if (narp && ar) + return false; // check no next ARP + } else { + if (narp == 0 && ar) + return false; // check no next ARP + } opc &= ~0xF; } - if ((opc & 0x80) != 0 && (mode1 == M_MAM || mode2 == M_MAM)) { + if ((opc & 0x80) != 0 && (mode1 == M_MAM || mode2 == M_MAM || mode1 == M_MAR || + mode2 == M_MAR || mode1 == M_IND)) { const auto modify = (opc >> 4) & 7; if (modify == 3) return false; // Don't allow both increment and decrement. @@ -230,24 +558,28 @@ bool matchOpCode(DisInsn &insn, const Entry *entry, const EntryPage *) { opc &= ~0xFF; } else if (mode1 == M_IM1) { opc &= ~1; + } else if (mode1 == M_IM2) { + opc &= ~3; + } else if (mode1 == M_IM9) { + opc &= ~0x1FF; } else if (mode1 == M_IM13) { opc &= ~0x1FFF; } - const auto maxAR = 1; + const auto maxAR = (cpuType == TMS32010) ? 1 : 7; if (mode1 == M_AR) opc &= ~(maxAR << 8); if (mode1 == M_ARK) opc &= ~(maxAR << 0); if (mode2 == M_PA) { - const auto maxPA = 7; + const auto maxPA = (cpuType == TMS32010) ? 7 : 15; opc &= ~(maxPA << 8); } - if (mode2 == M_LS4) + if (mode2 == M_LS4 || mode2 == M_BIT) opc &= ~(0xF << 8); if (mode2 == M_LS3) { const auto shift = (opc >> 8) & 7; - if (shift == 0 || shift == 1 || shift == 4) { + if (cpuType == TMS320C25 || shift == 0 || shift == 1 || shift == 4) { opc &= ~(7 << 8); } else { return false; @@ -256,8 +588,27 @@ bool matchOpCode(DisInsn &insn, const Entry *entry, const EntryPage *) { return opc == entry->readOpCode(); } +bool matchOpCode1x(DisInsn &insn, const Entry *entry, const EntryPage *) { + return matchOpCode(insn, entry, TMS32010); +} + +bool matchOpCode20(DisInsn &insn, const Entry *entry, const EntryPage *) { + return matchOpCode(insn, entry, TMS32020); +} + +bool matchOpCode2x(DisInsn &insn, const Entry *entry, const EntryPage *) { + return matchOpCode(insn, entry, TMS320C25); +} + Error searchOpCode(CpuType cpuType, DisInsn &insn, StrBuffer &out) { - cpu(cpuType)->searchOpCode(insn, out, matchOpCode); + const auto c = cpu(cpuType); + if (cpuType == TMS32010 || cpuType == TMS32015) { + c->searchOpCode(insn, out, matchOpCode1x); + } else if (cpuType == TMS32020) { + c->searchOpCode(insn, out, matchOpCode20); + } else { + c->searchOpCode(insn, out, matchOpCode2x); + } return insn.getError(); } diff --git a/src/text_common.cpp b/src/text_common.cpp index d611ca0aa..7df7d2932 100644 --- a/src/text_common.cpp +++ b/src/text_common.cpp @@ -66,6 +66,7 @@ constexpr char TEXT_ASRA[] PROGMEM = "ASRA"; constexpr char TEXT_ASRB[] PROGMEM = "ASRB"; constexpr char TEXT_ASR[] PROGMEM = "ASR"; constexpr char TEXT_BAND[] PROGMEM = "BAND"; +constexpr char TEXT_BC[] PROGMEM = "BC"; constexpr char TEXT_BCC[] PROGMEM = "BCC"; constexpr char TEXT_BCLR[] PROGMEM = "BCLR"; constexpr char TEXT_BCS[] PROGMEM = "BCS"; @@ -85,6 +86,7 @@ constexpr char TEXT_BLS[] PROGMEM = "BLS"; constexpr char TEXT_BLT[] PROGMEM = "BLT"; constexpr char TEXT_BMI[] PROGMEM = "BMI"; constexpr char TEXT_BM[] PROGMEM = "BM"; +constexpr char TEXT_BNC[] PROGMEM = "BNC"; constexpr char TEXT_BNE[] PROGMEM = "BNE"; constexpr char TEXT_BNZ[] PROGMEM = "BNZ"; constexpr char TEXT_BOR[] PROGMEM = "BOR"; @@ -127,6 +129,7 @@ constexpr char TEXT_CMPB[] PROGMEM = "CMPB"; constexpr char TEXT_CMPD[] PROGMEM = "CMPD"; constexpr char TEXT_CMPF[] PROGMEM = "CMPF"; constexpr char TEXT_CMPL[] PROGMEM = "CMPL"; +constexpr char TEXT_CMPR[] PROGMEM = "CMPR"; constexpr char TEXT_CMP[] PROGMEM = "CMP"; constexpr char TEXT_CM[] PROGMEM = "CM"; constexpr char TEXT_CMPSB[] PROGMEM = "CMPSB"; @@ -288,6 +291,7 @@ constexpr char TEXT_MOVSB[] PROGMEM = "MOVSB"; constexpr char TEXT_MOVSW[] PROGMEM = "MOVSW"; constexpr char TEXT_MOVX[] PROGMEM = "MOVX"; constexpr char TEXT_MPY[] PROGMEM = "MPY"; +constexpr char TEXT_MPYS[] PROGMEM = "MPYS"; constexpr char TEXT_MULB[] PROGMEM = "MULB"; constexpr char TEXT_MULD[] PROGMEM = "MULD"; constexpr char TEXT_MULF[] PROGMEM = "MULF"; @@ -330,6 +334,7 @@ constexpr char TEXT_PUSHF[] PROGMEM = "PUSHF"; constexpr char TEXT_PUSH[] PROGMEM = "PUSH"; constexpr char TEXT_RAL[] PROGMEM = "RAL"; constexpr char TEXT_RAR[] PROGMEM = "RAR"; +constexpr char TEXT_RC[] PROGMEM = "RC"; constexpr char TEXT_RCF[] PROGMEM = "RCF"; constexpr char TEXT_REP[] PROGMEM = "REP"; constexpr char TEXT_RESET[] PROGMEM = "RESET"; @@ -365,6 +370,7 @@ constexpr char TEXT_SBCA[] PROGMEM = "SBCA"; constexpr char TEXT_SBCB[] PROGMEM = "SBCB"; constexpr char TEXT_SBCD[] PROGMEM = "SBCD"; constexpr char TEXT_SBC[] PROGMEM = "SBC"; +constexpr char TEXT_SC[] PROGMEM = "SC"; constexpr char TEXT_SCC[] PROGMEM = "SCC"; constexpr char TEXT_SCF[] PROGMEM = "SCF"; constexpr char TEXT_SD[] PROGMEM = "SD"; diff --git a/src/text_common.h b/src/text_common.h index 938e2424f..27078d6ef 100644 --- a/src/text_common.h +++ b/src/text_common.h @@ -69,6 +69,7 @@ extern const char TEXT_ASRA[] PROGMEM; extern const char TEXT_ASRB[] PROGMEM; extern const char TEXT_ASR[] PROGMEM; extern const char TEXT_BAND[] PROGMEM; +extern const char TEXT_BC[] PROGMEM; extern const char TEXT_BCC[] PROGMEM; extern const char TEXT_BCLR[] PROGMEM; extern const char TEXT_BCS[] PROGMEM; @@ -88,6 +89,7 @@ extern const char TEXT_BLS[] PROGMEM; extern const char TEXT_BLT[] PROGMEM; extern const char TEXT_BMI[] PROGMEM; extern const char TEXT_BM[] PROGMEM; +extern const char TEXT_BNC[] PROGMEM; extern const char TEXT_BNE[] PROGMEM; extern const char TEXT_BNZ[] PROGMEM; extern const char TEXT_BOR[] PROGMEM; @@ -132,6 +134,7 @@ extern const char TEXT_CMPF[] PROGMEM; extern const char TEXT_CMPL[] PROGMEM; extern const char TEXT_CMP[] PROGMEM; extern const char TEXT_CM[] PROGMEM; +extern const char TEXT_CMPR[] PROGMEM; extern const char TEXT_CMPSB[] PROGMEM; extern const char TEXT_CMPS[] PROGMEM; extern const char TEXT_CMPSW[] PROGMEM; @@ -291,6 +294,7 @@ extern const char TEXT_MOVSB[] PROGMEM; extern const char TEXT_MOVSW[] PROGMEM; extern const char TEXT_MOVX[] PROGMEM; extern const char TEXT_MPY[] PROGMEM; +extern const char TEXT_MPYS[] PROGMEM; extern const char TEXT_MULB[] PROGMEM; extern const char TEXT_MULD[] PROGMEM; extern const char TEXT_MULF[] PROGMEM; @@ -333,6 +337,7 @@ extern const char TEXT_PUSHF[] PROGMEM; extern const char TEXT_PUSH[] PROGMEM; extern const char TEXT_RAL[] PROGMEM; extern const char TEXT_RAR[] PROGMEM; +extern const char TEXT_RC[] PROGMEM; extern const char TEXT_RCF[] PROGMEM; extern const char TEXT_REP[] PROGMEM; extern const char TEXT_RESET[] PROGMEM; @@ -368,6 +373,7 @@ extern const char TEXT_SBCA[] PROGMEM; extern const char TEXT_SBCB[] PROGMEM; extern const char TEXT_SBCD[] PROGMEM; extern const char TEXT_SBC[] PROGMEM; +extern const char TEXT_SC[] PROGMEM; extern const char TEXT_SCC[] PROGMEM; extern const char TEXT_SCF[] PROGMEM; extern const char TEXT_SD[] PROGMEM; diff --git a/src/text_f3850.cpp b/src/text_f3850.cpp index 00da1a342..51c7d6dbc 100644 --- a/src/text_f3850.cpp +++ b/src/text_f3850.cpp @@ -33,10 +33,10 @@ constexpr char TEXT_CPU_3850[] PROGMEM = "3850"; constexpr char TEXT_AMD[] PROGMEM = "AMD"; constexpr char TEXT_AS[] PROGMEM = "AS"; constexpr char TEXT_ASD[] PROGMEM = "ASD"; -constexpr char TEXT_BC[] PROGMEM = "BC"; +// constexpr char TEXT_BC[] PROGMEM = "BC"; constexpr char TEXT_BF[] PROGMEM = "BF"; // constexpr char TEXT_BM[] PROGMEM = "BM"; -constexpr char TEXT_BNC[] PROGMEM = "BNC"; +// constexpr char TEXT_BNC[] PROGMEM = "BNC"; constexpr char TEXT_BNO[] PROGMEM = "BNO"; // constexpr char TEXT_BNZ[] PROGMEM = "BNZ"; // constexpr char TEXT_BP[] PROGMEM = "BP"; diff --git a/src/text_f3850.h b/src/text_f3850.h index 3e24f8d3d..958472b44 100644 --- a/src/text_f3850.h +++ b/src/text_f3850.h @@ -36,10 +36,10 @@ using common::TEXT_AM; extern const char TEXT_AMD[] PROGMEM; extern const char TEXT_AS[] PROGMEM; extern const char TEXT_ASD[] PROGMEM; -extern const char TEXT_BC[] PROGMEM; +using common::TEXT_BC; extern const char TEXT_BF[] PROGMEM; using common::TEXT_BM; -extern const char TEXT_BNC[] PROGMEM; +using common::TEXT_BNC; extern const char TEXT_BNO[] PROGMEM; using common::TEXT_BNZ; using common::TEXT_BP; diff --git a/src/text_i8080.cpp b/src/text_i8080.cpp index cda58d6cb..9d5e90247 100644 --- a/src/text_i8080.cpp +++ b/src/text_i8080.cpp @@ -79,7 +79,7 @@ constexpr char TEXT_PCHL[] PROGMEM = "PCHL"; // constexpr char TEXT_PUSH[] PROGMEM = "PUSH"; // constexpr char TEXT_RAL[] PROGMEM = "RAL"; // constexpr char TEXT_RAR[] PROGMEM = "RAR"; -constexpr char TEXT_RC[] PROGMEM = "RC"; +// constexpr char TEXT_RC[] PROGMEM = "RC"; // constexpr char TEXT_RET[] PROGMEM = "RET"; // constexpr char TEXT_RLC[] PROGMEM = "RLC"; constexpr char TEXT_RM[] PROGMEM = "RM"; diff --git a/src/text_i8080.h b/src/text_i8080.h index 24f465e02..5dab75754 100644 --- a/src/text_i8080.h +++ b/src/text_i8080.h @@ -82,7 +82,7 @@ using common::TEXT_POP; using common::TEXT_PUSH; using common::TEXT_RAL; using common::TEXT_RAR; -extern const char TEXT_RC[] PROGMEM; +using common::TEXT_RC; using common::TEXT_RET; using common::TEXT_RLC; extern const char TEXT_RM[] PROGMEM; diff --git a/src/text_mc6809.cpp b/src/text_mc6809.cpp index 8f80097b2..ba0e25ad1 100644 --- a/src/text_mc6809.cpp +++ b/src/text_mc6809.cpp @@ -194,7 +194,7 @@ constexpr char TEXT_CLRE[] PROGMEM = "CLRE"; constexpr char TEXT_CLRW[] PROGMEM = "CLRW"; constexpr char TEXT_CMPE[] PROGMEM = "CMPE"; // constexpr char TEXT_CMPF[] PROGMEM = "CMPF"; -constexpr char TEXT_CMPR[] PROGMEM = "CMPR"; +// constexpr char TEXT_CMPR[] PROGMEM = "CMPR"; // constexpr char TEXT_CMPW[] PROGMEM = "CMPW"; // constexpr char TEXT_COMD[] PROGMEM = "COMD"; constexpr char TEXT_COME[] PROGMEM = "COME"; diff --git a/src/text_mc6809.h b/src/text_mc6809.h index 61c92932d..aa0a66a8e 100644 --- a/src/text_mc6809.h +++ b/src/text_mc6809.h @@ -197,7 +197,7 @@ using common::TEXT_CLRF; extern const char TEXT_CLRW[] PROGMEM; extern const char TEXT_CMPE[] PROGMEM; using common::TEXT_CMPF; -extern const char TEXT_CMPR[] PROGMEM; +using common::TEXT_CMPR; using common::TEXT_CMPW; using common::TEXT_COMD; extern const char TEXT_COME[] PROGMEM; diff --git a/src/text_tms32010.cpp b/src/text_tms32010.cpp index f2506063e..6c88de363 100644 --- a/src/text_tms32010.cpp +++ b/src/text_tms32010.cpp @@ -21,9 +21,12 @@ namespace text { namespace tms32010 { // clang-format off -constexpr char TEXT_TMS32010_LIST[] PROGMEM = "TMS32010, TMS32015"; +constexpr char TEXT_TMS32010_LIST[] PROGMEM = "TMS32010, TMS32015, TMS32020, TMS320C25, TMS320C26"; constexpr char TEXT_CPU_32010[] PROGMEM = "32010"; constexpr char TEXT_CPU_32015[] PROGMEM = "32015"; +constexpr char TEXT_CPU_32020[] PROGMEM = "32020"; +constexpr char TEXT_CPU_320C25[] PROGMEM = "320C25"; +constexpr char TEXT_CPU_320C26[] PROGMEM = "320C26"; // TMS32010 // constexpr char TEXT_ABS[] PROGMEM = "ABS"; @@ -87,8 +90,89 @@ constexpr char TEXT_ZAC[] PROGMEM = "ZAC"; constexpr char TEXT_ZALH[] PROGMEM = "ZALH"; constexpr char TEXT_ZALS[] PROGMEM = "ZALS"; +// TMS32020 +constexpr char TEXT_ADDT[] PROGMEM = "ADDT"; +constexpr char TEXT_ADLK[] PROGMEM = "ADLK"; +constexpr char TEXT_ANDK[] PROGMEM = "ANDK"; +constexpr char TEXT_BACC[] PROGMEM = "BACC"; +constexpr char TEXT_BBNZ[] PROGMEM = "BBNZ"; +constexpr char TEXT_BBZ[] PROGMEM = "BBZ"; +// constexpr char TEXT_BIT[] PROGMEM = "BIT"; +constexpr char TEXT_BITT[] PROGMEM = "BITT"; +constexpr char TEXT_BLKD[] PROGMEM = "BLKD"; +constexpr char TEXT_BLKP[] PROGMEM = "BLKP"; +constexpr char TEXT_BNV[] PROGMEM = "BNV"; +// constexpr char TEXT_CMPL[] PROGMEM = "CMPL"; +// constexpr char TEXT_CMPR[] PROGMEM = "CMPR"; +constexpr char TEXT_CNFD[] PROGMEM = "CNFD"; +constexpr char TEXT_CNFP[] PROGMEM = "CNFP"; +constexpr char TEXT_FORT[] PROGMEM = "FORT"; +// constexpr char TEXT_IDLE[] PROGMEM = "IDLE"; +constexpr char TEXT_LACT[] PROGMEM = "LACT"; +constexpr char TEXT_LALK[] PROGMEM = "LALK"; +constexpr char TEXT_LPH[] PROGMEM = "LPH"; +constexpr char TEXT_LRLK[] PROGMEM = "LRLK"; +constexpr char TEXT_LST1[] PROGMEM = "LST1"; +constexpr char TEXT_LTP[] PROGMEM = "LTP"; +constexpr char TEXT_LTS[] PROGMEM = "LTS"; +constexpr char TEXT_MAC[] PROGMEM = "MAC"; +constexpr char TEXT_MACD[] PROGMEM = "MACD"; +// constexpr char TEXT_NEG[] PROGMEM = "NEG"; +constexpr char TEXT_NORM[] PROGMEM = "NORM"; +constexpr char TEXT_ORK[] PROGMEM = "ORK"; +constexpr char TEXT_POPD[] PROGMEM = "POPD"; +constexpr char TEXT_PSHD[] PROGMEM = "PSHD"; +constexpr char TEXT_RPT[] PROGMEM = "RPT"; +constexpr char TEXT_RPTK[] PROGMEM = "RPTK"; +constexpr char TEXT_RSXM[] PROGMEM = "RSXM"; +constexpr char TEXT_RTXM[] PROGMEM = "RTXM"; +constexpr char TEXT_RXF[] PROGMEM = "RXF"; +constexpr char TEXT_SBLK[] PROGMEM = "SBLK"; +constexpr char TEXT_SFL[] PROGMEM = "SFL"; +constexpr char TEXT_SFR[] PROGMEM = "SFR"; +constexpr char TEXT_SPM[] PROGMEM = "SPM"; +constexpr char TEXT_SQRA[] PROGMEM = "SQRA"; +constexpr char TEXT_SQRS[] PROGMEM = "SQRS"; +constexpr char TEXT_SST1[] PROGMEM = "SST1"; +constexpr char TEXT_SSXM[] PROGMEM = "SSXM"; +constexpr char TEXT_SUBT[] PROGMEM = "SUBT"; +constexpr char TEXT_STXM[] PROGMEM = "STXM"; +constexpr char TEXT_SXF[] PROGMEM = "SXF"; +// constexpr char TEXT_TRAP[] PROGMEM = "TRAP"; +constexpr char TEXT_XORK[] PROGMEM = "XORK"; + +// TMS320C25 +// constexpr char TEXT_ADDC[] PROGMEM = "ADDC"; +constexpr char TEXT_ADDK[] PROGMEM = "ADDK"; +constexpr char TEXT_ADRK[] PROGMEM = "ADRK"; +// constexpr char TEXT_BC[] PROGMEM = "BC"; +// constexpr char TEXT_BNC[] PROGMEM = "BNC"; +constexpr char TEXT_MPYA[] PROGMEM = "MPYA"; +// constexpr char TEXT_MPYS[] PROGMEM = "MPYS"; +constexpr char TEXT_MPYU[] PROGMEM = "MPYU"; +// constexpr char TEXT_RC[] PROGMEM = "RC"; +constexpr char TEXT_RFSM[] PROGMEM = "RFSM"; +constexpr char TEXT_RHM[] PROGMEM = "RHM"; +// constexpr char TEXT_ROL[] PROGMEM = "ROL"; +// constexpr char TEXT_ROR[] PROGMEM = "ROR"; +constexpr char TEXT_RTC[] PROGMEM = "RTC"; +constexpr char TEXT_SBRK[] PROGMEM = "SBRK"; +// constexpr char TEXT_SC[] PROGMEM = "SC"; +constexpr char TEXT_SFSM[] PROGMEM = "SFSM"; +constexpr char TEXT_SHM[] PROGMEM = "SHM"; +constexpr char TEXT_SPH[] PROGMEM = "SPH"; +// constexpr char TEXT_SPL[] PROGMEM = "SPL"; +constexpr char TEXT_STC[] PROGMEM = "STC"; +// constexpr char TEXT_SUBB[] PROGMEM = "SUBB"; +constexpr char TEXT_SUBK[] PROGMEM = "SUBK"; +constexpr char TEXT_ZALR[] PROGMEM = "ZALR"; + +// TMS320C26 +constexpr char TEXT_CONF[] = "CONF"; + constexpr char TEXT_REG_AR[] PROGMEM = "AR"; constexpr char TEXT_REG_PA[] PROGMEM = "PA"; + // clang-format on } // namespace tms32010 diff --git a/src/text_tms32010.h b/src/text_tms32010.h index 72f4af1e6..47237ed0d 100644 --- a/src/text_tms32010.h +++ b/src/text_tms32010.h @@ -27,6 +27,9 @@ namespace tms32010 { extern const char TEXT_TMS32010_LIST[] PROGMEM; extern const char TEXT_CPU_32010[] PROGMEM; extern const char TEXT_CPU_32015[] PROGMEM; +extern const char TEXT_CPU_32020[] PROGMEM; +extern const char TEXT_CPU_320C25[] PROGMEM; +extern const char TEXT_CPU_320C26[] PROGMEM; // TMS32010 using common::TEXT_ABS; @@ -90,6 +93,86 @@ extern const char TEXT_ZAC[] PROGMEM; extern const char TEXT_ZALH[] PROGMEM; extern const char TEXT_ZALS[] PROGMEM; +// TMS32020 +extern const char TEXT_ADDT[] PROGMEM; +extern const char TEXT_ADLK[] PROGMEM; +extern const char TEXT_ANDK[] PROGMEM; +extern const char TEXT_BACC[] PROGMEM; +extern const char TEXT_BBNZ[] PROGMEM; +extern const char TEXT_BBZ[] PROGMEM; +using common::TEXT_BIT; +extern const char TEXT_BITT[] PROGMEM; +extern const char TEXT_BLKD[] PROGMEM; +extern const char TEXT_BLKP[] PROGMEM; +extern const char TEXT_BNV[] PROGMEM; +using common::TEXT_CMPL; +using common::TEXT_CMPR; +extern const char TEXT_CNFD[] PROGMEM; +extern const char TEXT_CNFP[] PROGMEM; +extern const char TEXT_FORT[] PROGMEM; +using common::TEXT_IDLE; +extern const char TEXT_LACT[] PROGMEM; +extern const char TEXT_LALK[] PROGMEM; +extern const char TEXT_LPH[] PROGMEM; +extern const char TEXT_LRLK[] PROGMEM; +extern const char TEXT_LST1[] PROGMEM; +extern const char TEXT_LTP[] PROGMEM; +extern const char TEXT_LTS[] PROGMEM; +extern const char TEXT_MAC[] PROGMEM; +extern const char TEXT_MACD[] PROGMEM; +using common::TEXT_NEG; +extern const char TEXT_NORM[] PROGMEM; +extern const char TEXT_ORK[] PROGMEM; +extern const char TEXT_POPD[] PROGMEM; +extern const char TEXT_PSHD[] PROGMEM; +extern const char TEXT_RPT[] PROGMEM; +extern const char TEXT_RPTK[] PROGMEM; +extern const char TEXT_RSXM[] PROGMEM; +extern const char TEXT_RTXM[] PROGMEM; +extern const char TEXT_RXF[] PROGMEM; +extern const char TEXT_SBLK[] PROGMEM; +extern const char TEXT_SFL[] PROGMEM; +extern const char TEXT_SFR[] PROGMEM; +extern const char TEXT_SPM[] PROGMEM; +extern const char TEXT_SQRA[] PROGMEM; +extern const char TEXT_SQRS[] PROGMEM; +extern const char TEXT_SST1[] PROGMEM; +extern const char TEXT_SSXM[] PROGMEM; +extern const char TEXT_SUBT[] PROGMEM; +extern const char TEXT_STXM[] PROGMEM; +extern const char TEXT_SXF[] PROGMEM; +using common::TEXT_TRAP; +extern const char TEXT_XORK[] PROGMEM; + +// TMS320C25 +using common::TEXT_ADDC; +extern const char TEXT_ADDK[] PROGMEM; +extern const char TEXT_ADRK[] PROGMEM; +using common::TEXT_BC; +using common::TEXT_BNC; +extern const char TEXT_MPYA[] PROGMEM; +using common::TEXT_MPYS; +extern const char TEXT_MPYU[] PROGMEM; +using common::TEXT_RC; +extern const char TEXT_RFSM[] PROGMEM; +extern const char TEXT_RHM[] PROGMEM; +using common::TEXT_ROL; +using common::TEXT_ROR; +extern const char TEXT_RTC[] PROGMEM; +extern const char TEXT_SBRK[] PROGMEM; +using common::TEXT_SC; +extern const char TEXT_SFSM[] PROGMEM; +extern const char TEXT_SHM[] PROGMEM; +extern const char TEXT_SPH[] PROGMEM; +using common::TEXT_SPL; +extern const char TEXT_STC[] PROGMEM; +using common::TEXT_SUBB; +extern const char TEXT_SUBK[] PROGMEM; +extern const char TEXT_ZALR[] PROGMEM; + +// TMS320C26 +extern const char TEXT_CONF[] PROGMEM; + extern const char TEXT_REG_AR[] PROGMEM; extern const char TEXT_REG_PA[] PROGMEM; @@ -100,7 +183,6 @@ extern const char TEXT_REG_PA[] PROGMEM; } // namespace libasm #endif // __LIBASM_TEXT_TMS32010__ - // Local Variables: // mode: c++ // c-basic-offset: 4 diff --git a/src/text_tms9900.cpp b/src/text_tms9900.cpp index 1dd0f3e50..c8dd185ca 100644 --- a/src/text_tms9900.cpp +++ b/src/text_tms9900.cpp @@ -101,7 +101,7 @@ constexpr char TEXT_XOP[] PROGMEM = "XOP"; // constexpr char TEXT_XOR[] PROGMEM = "XOR"; // TMS9995 -constexpr char TEXT_MPYS[] PROGMEM = "MPYS"; +// constexpr char TEXT_MPYS[] PROGMEM = "MPYS"; // constexpr char TEXT_DIVS[] PROGMEM = "DIVS"; // constexpr char TEXT_LST[] PROGMEM = "LST"; constexpr char TEXT_LWP[] PROGMEM = "LWP"; diff --git a/src/text_tms9900.h b/src/text_tms9900.h index 8cb431b02..0a175452e 100644 --- a/src/text_tms9900.h +++ b/src/text_tms9900.h @@ -105,7 +105,7 @@ extern const char TEXT_XOP[] PROGMEM; using common::TEXT_XOR; // TMS9995 -extern const char TEXT_MPYS[] PROGMEM; +using common::TEXT_MPYS; using common::TEXT_DIVS; using common::TEXT_LST; extern const char TEXT_LWP[] PROGMEM; diff --git a/src/text_z8000.cpp b/src/text_z8000.cpp index 906e1f242..4d5403415 100644 --- a/src/text_z8000.cpp +++ b/src/text_z8000.cpp @@ -152,7 +152,7 @@ constexpr char TEXT_RRCB[] PROGMEM = "RRCB"; constexpr char TEXT_RRDB[] PROGMEM = "RRDB"; // constexpr char TEXT_SBC[] PROGMEM = "SBC"; // constexpr char TEXT_SBCB[] PROGMEM = "SBCB"; -constexpr char TEXT_SC[] PROGMEM = "SC"; +// constexpr char TEXT_SC[] PROGMEM = "SC"; constexpr char TEXT_SDA[] PROGMEM = "SDA"; constexpr char TEXT_SDAB[] PROGMEM = "SDAB"; constexpr char TEXT_SDAL[] PROGMEM = "SDAL"; diff --git a/src/text_z8000.h b/src/text_z8000.h index 5d55adeea..2f2123c5d 100644 --- a/src/text_z8000.h +++ b/src/text_z8000.h @@ -155,7 +155,7 @@ extern const char TEXT_RRCB[] PROGMEM; extern const char TEXT_RRDB[] PROGMEM; using common::TEXT_SBC; using common::TEXT_SBCB; -extern const char TEXT_SC[] PROGMEM; +using common::TEXT_SC; extern const char TEXT_SDA[] PROGMEM; extern const char TEXT_SDAB[] PROGMEM; extern const char TEXT_SDAL[] PROGMEM; diff --git a/test/autogen/gen_tms32010.asm b/test/autogen/gen_tms32010.asm index a5aea5566..bb670e226 100644 --- a/test/autogen/gen_tms32010.asm +++ b/test/autogen/gen_tms32010.asm @@ -49,20 +49,20 @@ LAR AR0, *- LAR AR0, *+, AR0 LAR AR0, *+ - IN 00H, PA0 - IN *, PA0, AR0 - IN *, PA0 - IN *-, PA0, AR0 - IN *-, PA0 - IN *+, PA0, AR0 - IN *+, PA0 - OUT 00H, PA0 - OUT *, PA0, AR0 - OUT *, PA0 - OUT *-, PA0, AR0 - OUT *-, PA0 - OUT *+, PA0, AR0 - OUT *+, PA0 + IN 00H, 0 + IN *, 0, AR0 + IN *, 0 + IN *-, 0, AR0 + IN *-, 0 + IN *+, 0, AR0 + IN *+, 0 + OUT 00H, 0 + OUT *, 0, AR0 + OUT *, 0 + OUT *-, 0, AR0 + OUT *-, 0 + OUT *+, 0, AR0 + OUT *+, 0 SACL 00H SACL *, 0, AR0 SACL * diff --git a/test/autogen/gen_tms320c25.asm b/test/autogen/gen_tms320c25.asm new file mode 100644 index 000000000..8f4cb526b --- /dev/null +++ b/test/autogen/gen_tms320c25.asm @@ -0,0 +1,1195 @@ +;;; AUTO GENERATED FILE +;;; generated by: gen_tms32010 -u -C 320C25 -o gen_tms320c25.asm -l gen_tms320c25.lst + CPU 320C25 + ORG 0100H + ADD 00H + ADD * + ADD *, 0, AR0 + ADD *- + ADD *-, 0, AR0 + ADD *+ + ADD *+, 0, AR0 + ADD *BR0- + ADD *BR0-, 0, AR0 + ADD *0- + ADD *0-, 0, AR0 + ADD *0+ + ADD *0+, 0, AR0 + ADD *BR0+ + ADD *BR0+, 0, AR0 + ADD 00H, 1 + ADD *, 1 + ADD *-, 1 + ADD *+, 1 + ADD *BR0-, 1 + ADD *0-, 1 + ADD *0+, 1 + ADD *BR0+, 1 + SUB 00H + SUB * + SUB *, 0, AR0 + SUB *- + SUB *-, 0, AR0 + SUB *+ + SUB *+, 0, AR0 + SUB *BR0- + SUB *BR0-, 0, AR0 + SUB *0- + SUB *0-, 0, AR0 + SUB *0+ + SUB *0+, 0, AR0 + SUB *BR0+ + SUB *BR0+, 0, AR0 + SUB 00H, 1 + SUB *, 1 + SUB *-, 1 + SUB *+, 1 + SUB *BR0-, 1 + SUB *0-, 1 + SUB *0+, 1 + SUB *BR0+, 1 + LAC 00H + LAC * + LAC *, 0, AR0 + LAC *- + LAC *-, 0, AR0 + LAC *+ + LAC *+, 0, AR0 + LAC *BR0- + LAC *BR0-, 0, AR0 + LAC *0- + LAC *0-, 0, AR0 + LAC *0+ + LAC *0+, 0, AR0 + LAC *BR0+ + LAC *BR0+, 0, AR0 + LAC 00H, 1 + LAC *, 1 + LAC *-, 1 + LAC *+, 1 + LAC *BR0-, 1 + LAC *0-, 1 + LAC *0+, 1 + LAC *BR0+, 1 + LAR AR0, 00H + LAR AR0, * + LAR AR0, *, AR0 + LAR AR0, *- + LAR AR0, *-, AR0 + LAR AR0, *+ + LAR AR0, *+, AR0 + LAR AR0, *BR0- + LAR AR0, *BR0-, AR0 + LAR AR0, *0- + LAR AR0, *0-, AR0 + LAR AR0, *0+ + LAR AR0, *0+, AR0 + LAR AR0, *BR0+ + LAR AR0, *BR0+, AR0 + MPY 00H + MPY * + MPY *, AR0 + MPY *- + MPY *-, AR0 + MPY *+ + MPY *+, AR0 + MPY *BR0- + MPY *BR0-, AR0 + MPY *0- + MPY *0-, AR0 + MPY *0+ + MPY *0+, AR0 + MPY *BR0+ + MPY *BR0+, AR0 + SQRA 00H + SQRA * + SQRA *, AR0 + SQRA *- + SQRA *-, AR0 + SQRA *+ + SQRA *+, AR0 + SQRA *BR0- + SQRA *BR0-, AR0 + SQRA *0- + SQRA *0-, AR0 + SQRA *0+ + SQRA *0+, AR0 + SQRA *BR0+ + SQRA *BR0+, AR0 + MPYA 00H + MPYA * + MPYA *, AR0 + MPYA *- + MPYA *-, AR0 + MPYA *+ + MPYA *+, AR0 + MPYA *BR0- + MPYA *BR0-, AR0 + MPYA *0- + MPYA *0-, AR0 + MPYA *0+ + MPYA *0+, AR0 + MPYA *BR0+ + MPYA *BR0+, AR0 + MPYS 00H + MPYS * + MPYS *, AR0 + MPYS *- + MPYS *-, AR0 + MPYS *+ + MPYS *+, AR0 + MPYS *BR0- + MPYS *BR0-, AR0 + MPYS *0- + MPYS *0-, AR0 + MPYS *0+ + MPYS *0+, AR0 + MPYS *BR0+ + MPYS *BR0+, AR0 + LT 00H + LT * + LT *, AR0 + LT *- + LT *-, AR0 + LT *+ + LT *+, AR0 + LT *BR0- + LT *BR0-, AR0 + LT *0- + LT *0-, AR0 + LT *0+ + LT *0+, AR0 + LT *BR0+ + LT *BR0+, AR0 + LTA 00H + LTA * + LTA *, AR0 + LTA *- + LTA *-, AR0 + LTA *+ + LTA *+, AR0 + LTA *BR0- + LTA *BR0-, AR0 + LTA *0- + LTA *0-, AR0 + LTA *0+ + LTA *0+, AR0 + LTA *BR0+ + LTA *BR0+, AR0 + LTP 00H + LTP * + LTP *, AR0 + LTP *- + LTP *-, AR0 + LTP *+ + LTP *+, AR0 + LTP *BR0- + LTP *BR0-, AR0 + LTP *0- + LTP *0-, AR0 + LTP *0+ + LTP *0+, AR0 + LTP *BR0+ + LTP *BR0+, AR0 + LTD 00H + LTD * + LTD *, AR0 + LTD *- + LTD *-, AR0 + LTD *+ + LTD *+, AR0 + LTD *BR0- + LTD *BR0-, AR0 + LTD *0- + LTD *0-, AR0 + LTD *0+ + LTD *0+, AR0 + LTD *BR0+ + LTD *BR0+, AR0 + ZALH 00H + ZALH * + ZALH *, AR0 + ZALH *- + ZALH *-, AR0 + ZALH *+ + ZALH *+, AR0 + ZALH *BR0- + ZALH *BR0-, AR0 + ZALH *0- + ZALH *0-, AR0 + ZALH *0+ + ZALH *0+, AR0 + ZALH *BR0+ + ZALH *BR0+, AR0 + ZALS 00H + ZALS * + ZALS *, AR0 + ZALS *- + ZALS *-, AR0 + ZALS *+ + ZALS *+, AR0 + ZALS *BR0- + ZALS *BR0-, AR0 + ZALS *0- + ZALS *0-, AR0 + ZALS *0+ + ZALS *0+, AR0 + ZALS *BR0+ + ZALS *BR0+, AR0 + LACT 00H + LACT * + LACT *, AR0 + LACT *- + LACT *-, AR0 + LACT *+ + LACT *+, AR0 + LACT *BR0- + LACT *BR0-, AR0 + LACT *0- + LACT *0-, AR0 + LACT *0+ + LACT *0+, AR0 + LACT *BR0+ + LACT *BR0+, AR0 + ADDC 00H + ADDC * + ADDC *, AR0 + ADDC *- + ADDC *-, AR0 + ADDC *+ + ADDC *+, AR0 + ADDC *BR0- + ADDC *BR0-, AR0 + ADDC *0- + ADDC *0-, AR0 + ADDC *0+ + ADDC *0+, AR0 + ADDC *BR0+ + ADDC *BR0+, AR0 + SUBH 00H + SUBH * + SUBH *, AR0 + SUBH *- + SUBH *-, AR0 + SUBH *+ + SUBH *+, AR0 + SUBH *BR0- + SUBH *BR0-, AR0 + SUBH *0- + SUBH *0-, AR0 + SUBH *0+ + SUBH *0+, AR0 + SUBH *BR0+ + SUBH *BR0+, AR0 + SUBS 00H + SUBS * + SUBS *, AR0 + SUBS *- + SUBS *-, AR0 + SUBS *+ + SUBS *+, AR0 + SUBS *BR0- + SUBS *BR0-, AR0 + SUBS *0- + SUBS *0-, AR0 + SUBS *0+ + SUBS *0+, AR0 + SUBS *BR0+ + SUBS *BR0+, AR0 + SUBT 00H + SUBT * + SUBT *, AR0 + SUBT *- + SUBT *-, AR0 + SUBT *+ + SUBT *+, AR0 + SUBT *BR0- + SUBT *BR0-, AR0 + SUBT *0- + SUBT *0-, AR0 + SUBT *0+ + SUBT *0+, AR0 + SUBT *BR0+ + SUBT *BR0+, AR0 + SUBC 00H + SUBC * + SUBC *, AR0 + SUBC *- + SUBC *-, AR0 + SUBC *+ + SUBC *+, AR0 + SUBC *BR0- + SUBC *BR0-, AR0 + SUBC *0- + SUBC *0-, AR0 + SUBC *0+ + SUBC *0+, AR0 + SUBC *BR0+ + SUBC *BR0+, AR0 + ADDH 00H + ADDH * + ADDH *, AR0 + ADDH *- + ADDH *-, AR0 + ADDH *+ + ADDH *+, AR0 + ADDH *BR0- + ADDH *BR0-, AR0 + ADDH *0- + ADDH *0-, AR0 + ADDH *0+ + ADDH *0+, AR0 + ADDH *BR0+ + ADDH *BR0+, AR0 + ADDS 00H + ADDS * + ADDS *, AR0 + ADDS *- + ADDS *-, AR0 + ADDS *+ + ADDS *+, AR0 + ADDS *BR0- + ADDS *BR0-, AR0 + ADDS *0- + ADDS *0-, AR0 + ADDS *0+ + ADDS *0+, AR0 + ADDS *BR0+ + ADDS *BR0+, AR0 + ADDT 00H + ADDT * + ADDT *, AR0 + ADDT *- + ADDT *-, AR0 + ADDT *+ + ADDT *+, AR0 + ADDT *BR0- + ADDT *BR0-, AR0 + ADDT *0- + ADDT *0-, AR0 + ADDT *0+ + ADDT *0+, AR0 + ADDT *BR0+ + ADDT *BR0+, AR0 + RPT 00H + RPT * + RPT *, AR0 + RPT *- + RPT *-, AR0 + RPT *+ + RPT *+, AR0 + RPT *BR0- + RPT *BR0-, AR0 + RPT *0- + RPT *0-, AR0 + RPT *0+ + RPT *0+, AR0 + RPT *BR0+ + RPT *BR0+, AR0 + XOR 00H + XOR * + XOR *, AR0 + XOR *- + XOR *-, AR0 + XOR *+ + XOR *+, AR0 + XOR *BR0- + XOR *BR0-, AR0 + XOR *0- + XOR *0-, AR0 + XOR *0+ + XOR *0+, AR0 + XOR *BR0+ + XOR *BR0+, AR0 + OR 00H + OR * + OR *, AR0 + OR *- + OR *-, AR0 + OR *+ + OR *+, AR0 + OR *BR0- + OR *BR0-, AR0 + OR *0- + OR *0-, AR0 + OR *0+ + OR *0+, AR0 + OR *BR0+ + OR *BR0+, AR0 + AND 00H + AND * + AND *, AR0 + AND *- + AND *-, AR0 + AND *+ + AND *+, AR0 + AND *BR0- + AND *BR0-, AR0 + AND *0- + AND *0-, AR0 + AND *0+ + AND *0+, AR0 + AND *BR0+ + AND *BR0+, AR0 + SUBB 00H + SUBB * + SUBB *, AR0 + SUBB *- + SUBB *-, AR0 + SUBB *+ + SUBB *+, AR0 + SUBB *BR0- + SUBB *BR0-, AR0 + SUBB *0- + SUBB *0-, AR0 + SUBB *0+ + SUBB *0+, AR0 + SUBB *BR0+ + SUBB *BR0+, AR0 + LST 00H + LST * + LST *, AR0 + LST *- + LST *-, AR0 + LST *+ + LST *+, AR0 + LST *BR0- + LST *BR0-, AR0 + LST *0- + LST *0-, AR0 + LST *0+ + LST *0+, AR0 + LST *BR0+ + LST *BR0+, AR0 + LST1 00H + LST1 * + LST1 *, AR0 + LST1 *- + LST1 *-, AR0 + LST1 *+ + LST1 *+, AR0 + LST1 *BR0- + LST1 *BR0-, AR0 + LST1 *0- + LST1 *0-, AR0 + LST1 *0+ + LST1 *0+, AR0 + LST1 *BR0+ + LST1 *BR0+, AR0 + LDP 00H + LDP * + LDP *, AR0 + LDP *- + LDP *-, AR0 + LDP *+ + LDP *+, AR0 + LDP *BR0- + LDP *BR0-, AR0 + LDP *0- + LDP *0-, AR0 + LDP *0+ + LDP *0+, AR0 + LDP *BR0+ + LDP *BR0+, AR0 + LPH 00H + LPH * + LPH *, AR0 + LPH *- + LPH *-, AR0 + LPH *+ + LPH *+, AR0 + LPH *BR0- + LPH *BR0-, AR0 + LPH *0- + LPH *0-, AR0 + LPH *0+ + LPH *0+, AR0 + LPH *BR0+ + LPH *BR0+, AR0 + PSHD 00H + PSHD * + PSHD *, AR0 + PSHD *- + PSHD *-, AR0 + PSHD *+ + PSHD *+, AR0 + PSHD *BR0- + PSHD *BR0-, AR0 + PSHD *0- + PSHD *0-, AR0 + PSHD *0+ + PSHD *0+, AR0 + PSHD *BR0+ + PSHD *BR0+, AR0 + NOP + MAR 01H + MAR * + LARP AR0 + MAR *- + MAR *-, AR0 + MAR *+ + MAR *+, AR0 + MAR *BR0- + MAR *BR0-, AR0 + MAR *0- + MAR *0-, AR0 + MAR *0+ + MAR *0+, AR0 + MAR *BR0+ + MAR *BR0+, AR0 + DMOV 00H + DMOV * + DMOV *, AR0 + DMOV *- + DMOV *-, AR0 + DMOV *+ + DMOV *+, AR0 + DMOV *BR0- + DMOV *BR0-, AR0 + DMOV *0- + DMOV *0-, AR0 + DMOV *0+ + DMOV *0+, AR0 + DMOV *BR0+ + DMOV *BR0+, AR0 + BITT 00H + BITT * + BITT *, AR0 + BITT *- + BITT *-, AR0 + BITT *+ + BITT *+, AR0 + BITT *BR0- + BITT *BR0-, AR0 + BITT *0- + BITT *0-, AR0 + BITT *0+ + BITT *0+, AR0 + BITT *BR0+ + BITT *BR0+, AR0 + TBLR 00H + TBLR * + TBLR *, AR0 + TBLR *- + TBLR *-, AR0 + TBLR *+ + TBLR *+, AR0 + TBLR *BR0- + TBLR *BR0-, AR0 + TBLR *0- + TBLR *0-, AR0 + TBLR *0+ + TBLR *0+, AR0 + TBLR *BR0+ + TBLR *BR0+, AR0 + TBLW 00H + TBLW * + TBLW *, AR0 + TBLW *- + TBLW *-, AR0 + TBLW *+ + TBLW *+, AR0 + TBLW *BR0- + TBLW *BR0-, AR0 + TBLW *0- + TBLW *0-, AR0 + TBLW *0+ + TBLW *0+, AR0 + TBLW *BR0+ + TBLW *BR0+, AR0 + SQRS 00H + SQRS * + SQRS *, AR0 + SQRS *- + SQRS *-, AR0 + SQRS *+ + SQRS *+, AR0 + SQRS *BR0- + SQRS *BR0-, AR0 + SQRS *0- + SQRS *0-, AR0 + SQRS *0+ + SQRS *0+, AR0 + SQRS *BR0+ + SQRS *BR0+, AR0 + LTS 00H + LTS * + LTS *, AR0 + LTS *- + LTS *-, AR0 + LTS *+ + LTS *+, AR0 + LTS *BR0- + LTS *BR0-, AR0 + LTS *0- + LTS *0-, AR0 + LTS *0+ + LTS *0+, AR0 + LTS *BR0+ + LTS *BR0+, AR0 + MACD 5D01H, 00H + MACD 5D81H, * + MACD 5D89H, *, AR0 + MACD 5D91H, *- + MACD 5D99H, *-, AR0 + MACD 5DA1H, *+ + MACD 5DA9H, *+, AR0 + MACD 5DC1H, *BR0- + MACD 5DC9H, *BR0-, AR0 + MACD 5DD1H, *0- + MACD 5DD9H, *0-, AR0 + MACD 5DE1H, *0+ + MACD 5DE9H, *0+, AR0 + MACD 5DF1H, *BR0+ + MACD 5DF9H, *BR0+, AR0 + MAC 5E01H, 00H + MAC 5E81H, * + MAC 5E89H, *, AR0 + MAC 5E91H, *- + MAC 5E99H, *-, AR0 + MAC 5EA1H, *+ + MAC 5EA9H, *+, AR0 + MAC 5EC1H, *BR0- + MAC 5EC9H, *BR0-, AR0 + MAC 5ED1H, *0- + MAC 5ED9H, *0-, AR0 + MAC 5EE1H, *0+ + MAC 5EE9H, *0+, AR0 + MAC 5EF1H, *BR0+ + MAC 5EF9H, *BR0+, AR0 + BC 5F81H + BC 5F89H, *, AR0 + BC 5F91H, *- + BC 5F99H, *-, AR0 + BC 5FA1H, *+ + BC 5FA9H, *+, AR0 + BC 5FC1H, *BR0- + BC 5FC9H, *BR0-, AR0 + BC 5FD1H, *0- + BC 5FD9H, *0-, AR0 + BC 5FE1H, *0+ + BC 5FE9H, *0+, AR0 + BC 5FF1H, *BR0+ + BC 5FF9H, *BR0+, AR0 + BNC 6081H + BNC 6089H, *, AR0 + BNC 6091H, *- + BNC 6099H, *-, AR0 + BNC 60A1H, *+ + BNC 60A9H, *+, AR0 + BNC 60C1H, *BR0- + BNC 60C9H, *BR0-, AR0 + BNC 60D1H, *0- + BNC 60D9H, *0-, AR0 + BNC 60E1H, *0+ + BNC 60E9H, *0+, AR0 + BNC 60F1H, *BR0+ + BNC 60F9H, *BR0+, AR0 + SACL 00H + SACL * + SACL *, 0, AR0 + SACL *- + SACL *-, 0, AR0 + SACL *+ + SACL *+, 0, AR0 + SACL *BR0- + SACL *BR0-, 0, AR0 + SACL *0- + SACL *0-, 0, AR0 + SACL *0+ + SACL *0+, 0, AR0 + SACL *BR0+ + SACL *BR0+, 0, AR0 + SACL 00H, 1 + SACL *, 1 + SACL *-, 1 + SACL *+, 1 + SACL *BR0-, 1 + SACL *0-, 1 + SACL *0+, 1 + SACL *BR0+, 1 + SACH 00H + SACH * + SACH *, 0, AR0 + SACH *- + SACH *-, 0, AR0 + SACH *+ + SACH *+, 0, AR0 + SACH *BR0- + SACH *BR0-, 0, AR0 + SACH *0- + SACH *0-, 0, AR0 + SACH *0+ + SACH *0+, 0, AR0 + SACH *BR0+ + SACH *BR0+, 0, AR0 + SACH 00H, 1 + SACH *, 1 + SACH *-, 1 + SACH *+, 1 + SACH *BR0-, 1 + SACH *0-, 1 + SACH *0+, 1 + SACH *BR0+, 1 + SAR AR0, 00H + SAR AR0, * + SAR AR0, *, AR0 + SAR AR0, *- + SAR AR0, *-, AR0 + SAR AR0, *+ + SAR AR0, *+, AR0 + SAR AR0, *BR0- + SAR AR0, *BR0-, AR0 + SAR AR0, *0- + SAR AR0, *0-, AR0 + SAR AR0, *0+ + SAR AR0, *0+, AR0 + SAR AR0, *BR0+ + SAR AR0, *BR0+, AR0 + SST 00H + SST * + SST *, AR0 + SST *- + SST *-, AR0 + SST *+ + SST *+, AR0 + SST *BR0- + SST *BR0-, AR0 + SST *0- + SST *0-, AR0 + SST *0+ + SST *0+, AR0 + SST *BR0+ + SST *BR0+, AR0 + SST1 00H + SST1 * + SST1 *, AR0 + SST1 *- + SST1 *-, AR0 + SST1 *+ + SST1 *+, AR0 + SST1 *BR0- + SST1 *BR0-, AR0 + SST1 *0- + SST1 *0-, AR0 + SST1 *0+ + SST1 *0+, AR0 + SST1 *BR0+ + SST1 *BR0+, AR0 + POPD 00H + POPD * + POPD *, AR0 + POPD *- + POPD *-, AR0 + POPD *+ + POPD *+, AR0 + POPD *BR0- + POPD *BR0-, AR0 + POPD *0- + POPD *0-, AR0 + POPD *0+ + POPD *0+, AR0 + POPD *BR0+ + POPD *BR0+, AR0 + ZALR 00H + ZALR * + ZALR *, AR0 + ZALR *- + ZALR *-, AR0 + ZALR *+ + ZALR *+, AR0 + ZALR *BR0- + ZALR *BR0-, AR0 + ZALR *0- + ZALR *0-, AR0 + ZALR *0+ + ZALR *0+, AR0 + ZALR *BR0+ + ZALR *BR0+, AR0 + SPL 00H + SPL * + SPL *, AR0 + SPL *- + SPL *-, AR0 + SPL *+ + SPL *+, AR0 + SPL *BR0- + SPL *BR0-, AR0 + SPL *0- + SPL *0-, AR0 + SPL *0+ + SPL *0+, AR0 + SPL *BR0+ + SPL *BR0+, AR0 + SPH 00H + SPH * + SPH *, AR0 + SPH *- + SPH *-, AR0 + SPH *+ + SPH *+, AR0 + SPH *BR0- + SPH *BR0-, AR0 + SPH *0- + SPH *0-, AR0 + SPH *0+ + SPH *0+, AR0 + SPH *BR0+ + SPH *BR0+, AR0 + ADRK 0 + SBRK 0 + IN 00H, 0 + IN *, 0 + IN *, 0, AR0 + IN *-, 0 + IN *-, 0, AR0 + IN *+, 0 + IN *+, 0, AR0 + IN *BR0-, 0 + IN *BR0-, 0, AR0 + IN *0-, 0 + IN *0-, 0, AR0 + IN *0+, 0 + IN *0+, 0, AR0 + IN *BR0+, 0 + IN *BR0+, 0, AR0 + BIT 00H, 0 + BIT *, 0 + BIT *, 0, AR0 + BIT *-, 0 + BIT *-, 0, AR0 + BIT *+, 0 + BIT *+, 0, AR0 + BIT *BR0-, 0 + BIT *BR0-, 0, AR0 + BIT *0-, 0 + BIT *0-, 0, AR0 + BIT *0+, 0 + BIT *0+, 0, AR0 + BIT *BR0+, 0 + BIT *BR0+, 0, AR0 + MPYK 0 + MPYK -4096 + LARK AR0, 0 + LDPK 000H + ZAC + LACK 1 + RPTK 0 + ADDK 0 + SUBK 0 + EINT + DINT + ROVM + SOVM + CNFD + CNFP + RSXM + SSXM + SPM 0 + RXF + SXF + FORT 0 + PAC + APAC + SPAC + SFL + SFR + ABS + PUSH + POP + TRAP + IDLE + RTXM + STXM + NEG + CALA + BACC + RET + CMPL + RC + SC + RTC + STC + ROL + ROR + RFSM + SFSM + RHM + SHM + CMPR 0 + NORM * + NORM *- + NORM *+ + NORM *BR0- + NORM *0- + NORM *0+ + NORM *BR0+ + MPYU 00H + MPYU * + MPYU *, AR0 + MPYU *- + MPYU *-, AR0 + MPYU *+ + MPYU *+, AR0 + MPYU *BR0- + MPYU *BR0-, AR0 + MPYU *0- + MPYU *0-, AR0 + MPYU *0+ + MPYU *0+, AR0 + MPYU *BR0+ + MPYU *BR0+, AR0 + LRLK AR0, 0D101H + LALK 0D102H + ADLK 0D103H + SBLK 0D104H + ANDK 0D105H + ORK 0D106H + XORK 0D107H + LALK 0D202H, 1 + ADLK 0D203H, 1 + SBLK 0D204H, 1 + ANDK 0D205H, 1 + ORK 0D206H, 1 + XORK 0D207H, 1 + OUT 00H, 0 + OUT *, 0 + OUT *, 0, AR0 + OUT *-, 0 + OUT *-, 0, AR0 + OUT *+, 0 + OUT *+, 0, AR0 + OUT *BR0-, 0 + OUT *BR0-, 0, AR0 + OUT *0-, 0 + OUT *0-, 0, AR0 + OUT *0+, 0 + OUT *0+, 0, AR0 + OUT *BR0+, 0 + OUT *BR0+, 0, AR0 + BV 0F181H + BV 0F189H, *, AR0 + BV 0F191H, *- + BV 0F199H, *-, AR0 + BV 0F1A1H, *+ + BV 0F1A9H, *+, AR0 + BV 0F1C1H, *BR0- + BV 0F1C9H, *BR0-, AR0 + BV 0F1D1H, *0- + BV 0F1D9H, *0-, AR0 + BV 0F1E1H, *0+ + BV 0F1E9H, *0+, AR0 + BV 0F1F1H, *BR0+ + BV 0F1F9H, *BR0+, AR0 + BGZ 0F281H + BGZ 0F289H, *, AR0 + BGZ 0F291H, *- + BGZ 0F299H, *-, AR0 + BGZ 0F2A1H, *+ + BGZ 0F2A9H, *+, AR0 + BGZ 0F2C1H, *BR0- + BGZ 0F2C9H, *BR0-, AR0 + BGZ 0F2D1H, *0- + BGZ 0F2D9H, *0-, AR0 + BGZ 0F2E1H, *0+ + BGZ 0F2E9H, *0+, AR0 + BGZ 0F2F1H, *BR0+ + BGZ 0F2F9H, *BR0+, AR0 + BLEZ 0F381H + BLEZ 0F389H, *, AR0 + BLEZ 0F391H, *- + BLEZ 0F399H, *-, AR0 + BLEZ 0F3A1H, *+ + BLEZ 0F3A9H, *+, AR0 + BLEZ 0F3C1H, *BR0- + BLEZ 0F3C9H, *BR0-, AR0 + BLEZ 0F3D1H, *0- + BLEZ 0F3D9H, *0-, AR0 + BLEZ 0F3E1H, *0+ + BLEZ 0F3E9H, *0+, AR0 + BLEZ 0F3F1H, *BR0+ + BLEZ 0F3F9H, *BR0+, AR0 + BLZ 0F481H + BLZ 0F489H, *, AR0 + BLZ 0F491H, *- + BLZ 0F499H, *-, AR0 + BLZ 0F4A1H, *+ + BLZ 0F4A9H, *+, AR0 + BLZ 0F4C1H, *BR0- + BLZ 0F4C9H, *BR0-, AR0 + BLZ 0F4D1H, *0- + BLZ 0F4D9H, *0-, AR0 + BLZ 0F4E1H, *0+ + BLZ 0F4E9H, *0+, AR0 + BLZ 0F4F1H, *BR0+ + BLZ 0F4F9H, *BR0+, AR0 + BGEZ 0F581H + BGEZ 0F589H, *, AR0 + BGEZ 0F591H, *- + BGEZ 0F599H, *-, AR0 + BGEZ 0F5A1H, *+ + BGEZ 0F5A9H, *+, AR0 + BGEZ 0F5C1H, *BR0- + BGEZ 0F5C9H, *BR0-, AR0 + BGEZ 0F5D1H, *0- + BGEZ 0F5D9H, *0-, AR0 + BGEZ 0F5E1H, *0+ + BGEZ 0F5E9H, *0+, AR0 + BGEZ 0F5F1H, *BR0+ + BGEZ 0F5F9H, *BR0+, AR0 + BNZ 0F681H + BNZ 0F689H, *, AR0 + BNZ 0F691H, *- + BNZ 0F699H, *-, AR0 + BNZ 0F6A1H, *+ + BNZ 0F6A9H, *+, AR0 + BNZ 0F6C1H, *BR0- + BNZ 0F6C9H, *BR0-, AR0 + BNZ 0F6D1H, *0- + BNZ 0F6D9H, *0-, AR0 + BNZ 0F6E1H, *0+ + BNZ 0F6E9H, *0+, AR0 + BNZ 0F6F1H, *BR0+ + BNZ 0F6F9H, *BR0+, AR0 + BZ 0F781H + BZ 0F789H, *, AR0 + BZ 0F791H, *- + BZ 0F799H, *-, AR0 + BZ 0F7A1H, *+ + BZ 0F7A9H, *+, AR0 + BZ 0F7C1H, *BR0- + BZ 0F7C9H, *BR0-, AR0 + BZ 0F7D1H, *0- + BZ 0F7D9H, *0-, AR0 + BZ 0F7E1H, *0+ + BZ 0F7E9H, *0+, AR0 + BZ 0F7F1H, *BR0+ + BZ 0F7F9H, *BR0+, AR0 + BNV 0F881H + BNV 0F889H, *, AR0 + BNV 0F891H, *- + BNV 0F899H, *-, AR0 + BNV 0F8A1H, *+ + BNV 0F8A9H, *+, AR0 + BNV 0F8C1H, *BR0- + BNV 0F8C9H, *BR0-, AR0 + BNV 0F8D1H, *0- + BNV 0F8D9H, *0-, AR0 + BNV 0F8E1H, *0+ + BNV 0F8E9H, *0+, AR0 + BNV 0F8F1H, *BR0+ + BNV 0F8F9H, *BR0+, AR0 + BBZ 0F981H + BBZ 0F989H, *, AR0 + BBZ 0F991H, *- + BBZ 0F999H, *-, AR0 + BBZ 0F9A1H, *+ + BBZ 0F9A9H, *+, AR0 + BBZ 0F9C1H, *BR0- + BBZ 0F9C9H, *BR0-, AR0 + BBZ 0F9D1H, *0- + BBZ 0F9D9H, *0-, AR0 + BBZ 0F9E1H, *0+ + BBZ 0F9E9H, *0+, AR0 + BBZ 0F9F1H, *BR0+ + BBZ 0F9F9H, *BR0+, AR0 + BBNZ 0FA81H + BBNZ 0FA89H, *, AR0 + BBNZ 0FA91H, *- + BBNZ 0FA99H, *-, AR0 + BBNZ 0FAA1H, *+ + BBNZ 0FAA9H, *+, AR0 + BBNZ 0FAC1H, *BR0- + BBNZ 0FAC9H, *BR0-, AR0 + BBNZ 0FAD1H, *0- + BBNZ 0FAD9H, *0-, AR0 + BBNZ 0FAE1H, *0+ + BBNZ 0FAE9H, *0+, AR0 + BBNZ 0FAF1H, *BR0+ + BBNZ 0FAF9H, *BR0+, AR0 + BIOZ 0FB81H + BIOZ 0FB89H, *, AR0 + BIOZ 0FB91H, *- + BIOZ 0FB99H, *-, AR0 + BIOZ 0FBA1H, *+ + BIOZ 0FBA9H, *+, AR0 + BIOZ 0FBC1H, *BR0- + BIOZ 0FBC9H, *BR0-, AR0 + BIOZ 0FBD1H, *0- + BIOZ 0FBD9H, *0-, AR0 + BIOZ 0FBE1H, *0+ + BIOZ 0FBE9H, *0+, AR0 + BIOZ 0FBF1H, *BR0+ + BIOZ 0FBF9H, *BR0+, AR0 + BANZ 0FC81H + BANZ 0FC89H, *, AR0 + BANZ 0FC91H, *- + BANZ 0FC99H, *-, AR0 + BANZ 0FCA1H, *+ + BANZ 0FCA9H, *+, AR0 + BANZ 0FCC1H, *BR0- + BANZ 0FCC9H, *BR0-, AR0 + BANZ 0FCD1H, *0- + BANZ 0FCD9H, *0-, AR0 + BANZ 0FCE1H, *0+ + BANZ 0FCE9H, *0+, AR0 + BANZ 0FCF1H, *BR0+ + BANZ 0FCF9H, *BR0+, AR0 + BLKP 0FD01H, 00H + BLKP 0FD81H, * + BLKP 0FD89H, *, AR0 + BLKP 0FD91H, *- + BLKP 0FD99H, *-, AR0 + BLKP 0FDA1H, *+ + BLKP 0FDA9H, *+, AR0 + BLKP 0FDC1H, *BR0- + BLKP 0FDC9H, *BR0-, AR0 + BLKP 0FDD1H, *0- + BLKP 0FDD9H, *0-, AR0 + BLKP 0FDE1H, *0+ + BLKP 0FDE9H, *0+, AR0 + BLKP 0FDF1H, *BR0+ + BLKP 0FDF9H, *BR0+, AR0 + BLKD 0FE01H, 00H + BLKD 0FE81H, * + BLKD 0FE89H, *, AR0 + BLKD 0FE91H, *- + BLKD 0FE99H, *-, AR0 + BLKD 0FEA1H, *+ + BLKD 0FEA9H, *+, AR0 + BLKD 0FEC1H, *BR0- + BLKD 0FEC9H, *BR0-, AR0 + BLKD 0FED1H, *0- + BLKD 0FED9H, *0-, AR0 + BLKD 0FEE1H, *0+ + BLKD 0FEE9H, *0+, AR0 + BLKD 0FEF1H, *BR0+ + BLKD 0FEF9H, *BR0+, AR0 + CALL 0FF81H + CALL 0FF89H, *, AR0 + CALL 0FF91H, *- + CALL 0FF99H, *-, AR0 + CALL 0FFA1H, *+ + CALL 0FFA9H, *+, AR0 + CALL 0FFC1H, *BR0- + CALL 0FFC9H, *BR0-, AR0 + CALL 0FFD1H, *0- + CALL 0FFD9H, *0-, AR0 + CALL 0FFE1H, *0+ + CALL 0FFE9H, *0+, AR0 + CALL 0FFF1H, *BR0+ + CALL 0FFF9H, *BR0+, AR0 + B 0081H + B 0089H, *, AR0 + B 0091H, *- + B 0099H, *-, AR0 + B 00A1H, *+ + B 00A9H, *+, AR0 + B 00C1H, *BR0- + B 00C9H, *BR0-, AR0 + B 00D1H, *0- + B 00D9H, *0-, AR0 + B 00E1H, *0+ + B 00E9H, *0+, AR0 + B 00F1H, *BR0+ + B 00F9H, *BR0+, AR0 diff --git a/test/autogen/gen_tms320c26.asm b/test/autogen/gen_tms320c26.asm new file mode 100644 index 000000000..9b8102b05 --- /dev/null +++ b/test/autogen/gen_tms320c26.asm @@ -0,0 +1,1194 @@ +;;; AUTO GENERATED FILE +;;; generated by: gen_tms32010 -u -C 320C26 -o gen_tms320c26.asm -l gen_tms320c26.lst + CPU 320C26 + ORG 0100H + ADD 00H + ADD * + ADD *, 0, AR0 + ADD *- + ADD *-, 0, AR0 + ADD *+ + ADD *+, 0, AR0 + ADD *BR0- + ADD *BR0-, 0, AR0 + ADD *0- + ADD *0-, 0, AR0 + ADD *0+ + ADD *0+, 0, AR0 + ADD *BR0+ + ADD *BR0+, 0, AR0 + ADD 00H, 1 + ADD *, 1 + ADD *-, 1 + ADD *+, 1 + ADD *BR0-, 1 + ADD *0-, 1 + ADD *0+, 1 + ADD *BR0+, 1 + SUB 00H + SUB * + SUB *, 0, AR0 + SUB *- + SUB *-, 0, AR0 + SUB *+ + SUB *+, 0, AR0 + SUB *BR0- + SUB *BR0-, 0, AR0 + SUB *0- + SUB *0-, 0, AR0 + SUB *0+ + SUB *0+, 0, AR0 + SUB *BR0+ + SUB *BR0+, 0, AR0 + SUB 00H, 1 + SUB *, 1 + SUB *-, 1 + SUB *+, 1 + SUB *BR0-, 1 + SUB *0-, 1 + SUB *0+, 1 + SUB *BR0+, 1 + LAC 00H + LAC * + LAC *, 0, AR0 + LAC *- + LAC *-, 0, AR0 + LAC *+ + LAC *+, 0, AR0 + LAC *BR0- + LAC *BR0-, 0, AR0 + LAC *0- + LAC *0-, 0, AR0 + LAC *0+ + LAC *0+, 0, AR0 + LAC *BR0+ + LAC *BR0+, 0, AR0 + LAC 00H, 1 + LAC *, 1 + LAC *-, 1 + LAC *+, 1 + LAC *BR0-, 1 + LAC *0-, 1 + LAC *0+, 1 + LAC *BR0+, 1 + LAR AR0, 00H + LAR AR0, * + LAR AR0, *, AR0 + LAR AR0, *- + LAR AR0, *-, AR0 + LAR AR0, *+ + LAR AR0, *+, AR0 + LAR AR0, *BR0- + LAR AR0, *BR0-, AR0 + LAR AR0, *0- + LAR AR0, *0-, AR0 + LAR AR0, *0+ + LAR AR0, *0+, AR0 + LAR AR0, *BR0+ + LAR AR0, *BR0+, AR0 + MPY 00H + MPY * + MPY *, AR0 + MPY *- + MPY *-, AR0 + MPY *+ + MPY *+, AR0 + MPY *BR0- + MPY *BR0-, AR0 + MPY *0- + MPY *0-, AR0 + MPY *0+ + MPY *0+, AR0 + MPY *BR0+ + MPY *BR0+, AR0 + SQRA 00H + SQRA * + SQRA *, AR0 + SQRA *- + SQRA *-, AR0 + SQRA *+ + SQRA *+, AR0 + SQRA *BR0- + SQRA *BR0-, AR0 + SQRA *0- + SQRA *0-, AR0 + SQRA *0+ + SQRA *0+, AR0 + SQRA *BR0+ + SQRA *BR0+, AR0 + MPYA 00H + MPYA * + MPYA *, AR0 + MPYA *- + MPYA *-, AR0 + MPYA *+ + MPYA *+, AR0 + MPYA *BR0- + MPYA *BR0-, AR0 + MPYA *0- + MPYA *0-, AR0 + MPYA *0+ + MPYA *0+, AR0 + MPYA *BR0+ + MPYA *BR0+, AR0 + MPYS 00H + MPYS * + MPYS *, AR0 + MPYS *- + MPYS *-, AR0 + MPYS *+ + MPYS *+, AR0 + MPYS *BR0- + MPYS *BR0-, AR0 + MPYS *0- + MPYS *0-, AR0 + MPYS *0+ + MPYS *0+, AR0 + MPYS *BR0+ + MPYS *BR0+, AR0 + LT 00H + LT * + LT *, AR0 + LT *- + LT *-, AR0 + LT *+ + LT *+, AR0 + LT *BR0- + LT *BR0-, AR0 + LT *0- + LT *0-, AR0 + LT *0+ + LT *0+, AR0 + LT *BR0+ + LT *BR0+, AR0 + LTA 00H + LTA * + LTA *, AR0 + LTA *- + LTA *-, AR0 + LTA *+ + LTA *+, AR0 + LTA *BR0- + LTA *BR0-, AR0 + LTA *0- + LTA *0-, AR0 + LTA *0+ + LTA *0+, AR0 + LTA *BR0+ + LTA *BR0+, AR0 + LTP 00H + LTP * + LTP *, AR0 + LTP *- + LTP *-, AR0 + LTP *+ + LTP *+, AR0 + LTP *BR0- + LTP *BR0-, AR0 + LTP *0- + LTP *0-, AR0 + LTP *0+ + LTP *0+, AR0 + LTP *BR0+ + LTP *BR0+, AR0 + LTD 00H + LTD * + LTD *, AR0 + LTD *- + LTD *-, AR0 + LTD *+ + LTD *+, AR0 + LTD *BR0- + LTD *BR0-, AR0 + LTD *0- + LTD *0-, AR0 + LTD *0+ + LTD *0+, AR0 + LTD *BR0+ + LTD *BR0+, AR0 + ZALH 00H + ZALH * + ZALH *, AR0 + ZALH *- + ZALH *-, AR0 + ZALH *+ + ZALH *+, AR0 + ZALH *BR0- + ZALH *BR0-, AR0 + ZALH *0- + ZALH *0-, AR0 + ZALH *0+ + ZALH *0+, AR0 + ZALH *BR0+ + ZALH *BR0+, AR0 + ZALS 00H + ZALS * + ZALS *, AR0 + ZALS *- + ZALS *-, AR0 + ZALS *+ + ZALS *+, AR0 + ZALS *BR0- + ZALS *BR0-, AR0 + ZALS *0- + ZALS *0-, AR0 + ZALS *0+ + ZALS *0+, AR0 + ZALS *BR0+ + ZALS *BR0+, AR0 + LACT 00H + LACT * + LACT *, AR0 + LACT *- + LACT *-, AR0 + LACT *+ + LACT *+, AR0 + LACT *BR0- + LACT *BR0-, AR0 + LACT *0- + LACT *0-, AR0 + LACT *0+ + LACT *0+, AR0 + LACT *BR0+ + LACT *BR0+, AR0 + ADDC 00H + ADDC * + ADDC *, AR0 + ADDC *- + ADDC *-, AR0 + ADDC *+ + ADDC *+, AR0 + ADDC *BR0- + ADDC *BR0-, AR0 + ADDC *0- + ADDC *0-, AR0 + ADDC *0+ + ADDC *0+, AR0 + ADDC *BR0+ + ADDC *BR0+, AR0 + SUBH 00H + SUBH * + SUBH *, AR0 + SUBH *- + SUBH *-, AR0 + SUBH *+ + SUBH *+, AR0 + SUBH *BR0- + SUBH *BR0-, AR0 + SUBH *0- + SUBH *0-, AR0 + SUBH *0+ + SUBH *0+, AR0 + SUBH *BR0+ + SUBH *BR0+, AR0 + SUBS 00H + SUBS * + SUBS *, AR0 + SUBS *- + SUBS *-, AR0 + SUBS *+ + SUBS *+, AR0 + SUBS *BR0- + SUBS *BR0-, AR0 + SUBS *0- + SUBS *0-, AR0 + SUBS *0+ + SUBS *0+, AR0 + SUBS *BR0+ + SUBS *BR0+, AR0 + SUBT 00H + SUBT * + SUBT *, AR0 + SUBT *- + SUBT *-, AR0 + SUBT *+ + SUBT *+, AR0 + SUBT *BR0- + SUBT *BR0-, AR0 + SUBT *0- + SUBT *0-, AR0 + SUBT *0+ + SUBT *0+, AR0 + SUBT *BR0+ + SUBT *BR0+, AR0 + SUBC 00H + SUBC * + SUBC *, AR0 + SUBC *- + SUBC *-, AR0 + SUBC *+ + SUBC *+, AR0 + SUBC *BR0- + SUBC *BR0-, AR0 + SUBC *0- + SUBC *0-, AR0 + SUBC *0+ + SUBC *0+, AR0 + SUBC *BR0+ + SUBC *BR0+, AR0 + ADDH 00H + ADDH * + ADDH *, AR0 + ADDH *- + ADDH *-, AR0 + ADDH *+ + ADDH *+, AR0 + ADDH *BR0- + ADDH *BR0-, AR0 + ADDH *0- + ADDH *0-, AR0 + ADDH *0+ + ADDH *0+, AR0 + ADDH *BR0+ + ADDH *BR0+, AR0 + ADDS 00H + ADDS * + ADDS *, AR0 + ADDS *- + ADDS *-, AR0 + ADDS *+ + ADDS *+, AR0 + ADDS *BR0- + ADDS *BR0-, AR0 + ADDS *0- + ADDS *0-, AR0 + ADDS *0+ + ADDS *0+, AR0 + ADDS *BR0+ + ADDS *BR0+, AR0 + ADDT 00H + ADDT * + ADDT *, AR0 + ADDT *- + ADDT *-, AR0 + ADDT *+ + ADDT *+, AR0 + ADDT *BR0- + ADDT *BR0-, AR0 + ADDT *0- + ADDT *0-, AR0 + ADDT *0+ + ADDT *0+, AR0 + ADDT *BR0+ + ADDT *BR0+, AR0 + RPT 00H + RPT * + RPT *, AR0 + RPT *- + RPT *-, AR0 + RPT *+ + RPT *+, AR0 + RPT *BR0- + RPT *BR0-, AR0 + RPT *0- + RPT *0-, AR0 + RPT *0+ + RPT *0+, AR0 + RPT *BR0+ + RPT *BR0+, AR0 + XOR 00H + XOR * + XOR *, AR0 + XOR *- + XOR *-, AR0 + XOR *+ + XOR *+, AR0 + XOR *BR0- + XOR *BR0-, AR0 + XOR *0- + XOR *0-, AR0 + XOR *0+ + XOR *0+, AR0 + XOR *BR0+ + XOR *BR0+, AR0 + OR 00H + OR * + OR *, AR0 + OR *- + OR *-, AR0 + OR *+ + OR *+, AR0 + OR *BR0- + OR *BR0-, AR0 + OR *0- + OR *0-, AR0 + OR *0+ + OR *0+, AR0 + OR *BR0+ + OR *BR0+, AR0 + AND 00H + AND * + AND *, AR0 + AND *- + AND *-, AR0 + AND *+ + AND *+, AR0 + AND *BR0- + AND *BR0-, AR0 + AND *0- + AND *0-, AR0 + AND *0+ + AND *0+, AR0 + AND *BR0+ + AND *BR0+, AR0 + SUBB 00H + SUBB * + SUBB *, AR0 + SUBB *- + SUBB *-, AR0 + SUBB *+ + SUBB *+, AR0 + SUBB *BR0- + SUBB *BR0-, AR0 + SUBB *0- + SUBB *0-, AR0 + SUBB *0+ + SUBB *0+, AR0 + SUBB *BR0+ + SUBB *BR0+, AR0 + LST 00H + LST * + LST *, AR0 + LST *- + LST *-, AR0 + LST *+ + LST *+, AR0 + LST *BR0- + LST *BR0-, AR0 + LST *0- + LST *0-, AR0 + LST *0+ + LST *0+, AR0 + LST *BR0+ + LST *BR0+, AR0 + LST1 00H + LST1 * + LST1 *, AR0 + LST1 *- + LST1 *-, AR0 + LST1 *+ + LST1 *+, AR0 + LST1 *BR0- + LST1 *BR0-, AR0 + LST1 *0- + LST1 *0-, AR0 + LST1 *0+ + LST1 *0+, AR0 + LST1 *BR0+ + LST1 *BR0+, AR0 + LDP 00H + LDP * + LDP *, AR0 + LDP *- + LDP *-, AR0 + LDP *+ + LDP *+, AR0 + LDP *BR0- + LDP *BR0-, AR0 + LDP *0- + LDP *0-, AR0 + LDP *0+ + LDP *0+, AR0 + LDP *BR0+ + LDP *BR0+, AR0 + LPH 00H + LPH * + LPH *, AR0 + LPH *- + LPH *-, AR0 + LPH *+ + LPH *+, AR0 + LPH *BR0- + LPH *BR0-, AR0 + LPH *0- + LPH *0-, AR0 + LPH *0+ + LPH *0+, AR0 + LPH *BR0+ + LPH *BR0+, AR0 + PSHD 00H + PSHD * + PSHD *, AR0 + PSHD *- + PSHD *-, AR0 + PSHD *+ + PSHD *+, AR0 + PSHD *BR0- + PSHD *BR0-, AR0 + PSHD *0- + PSHD *0-, AR0 + PSHD *0+ + PSHD *0+, AR0 + PSHD *BR0+ + PSHD *BR0+, AR0 + NOP + MAR 01H + MAR * + LARP AR0 + MAR *- + MAR *-, AR0 + MAR *+ + MAR *+, AR0 + MAR *BR0- + MAR *BR0-, AR0 + MAR *0- + MAR *0-, AR0 + MAR *0+ + MAR *0+, AR0 + MAR *BR0+ + MAR *BR0+, AR0 + DMOV 00H + DMOV * + DMOV *, AR0 + DMOV *- + DMOV *-, AR0 + DMOV *+ + DMOV *+, AR0 + DMOV *BR0- + DMOV *BR0-, AR0 + DMOV *0- + DMOV *0-, AR0 + DMOV *0+ + DMOV *0+, AR0 + DMOV *BR0+ + DMOV *BR0+, AR0 + BITT 00H + BITT * + BITT *, AR0 + BITT *- + BITT *-, AR0 + BITT *+ + BITT *+, AR0 + BITT *BR0- + BITT *BR0-, AR0 + BITT *0- + BITT *0-, AR0 + BITT *0+ + BITT *0+, AR0 + BITT *BR0+ + BITT *BR0+, AR0 + TBLR 00H + TBLR * + TBLR *, AR0 + TBLR *- + TBLR *-, AR0 + TBLR *+ + TBLR *+, AR0 + TBLR *BR0- + TBLR *BR0-, AR0 + TBLR *0- + TBLR *0-, AR0 + TBLR *0+ + TBLR *0+, AR0 + TBLR *BR0+ + TBLR *BR0+, AR0 + TBLW 00H + TBLW * + TBLW *, AR0 + TBLW *- + TBLW *-, AR0 + TBLW *+ + TBLW *+, AR0 + TBLW *BR0- + TBLW *BR0-, AR0 + TBLW *0- + TBLW *0-, AR0 + TBLW *0+ + TBLW *0+, AR0 + TBLW *BR0+ + TBLW *BR0+, AR0 + SQRS 00H + SQRS * + SQRS *, AR0 + SQRS *- + SQRS *-, AR0 + SQRS *+ + SQRS *+, AR0 + SQRS *BR0- + SQRS *BR0-, AR0 + SQRS *0- + SQRS *0-, AR0 + SQRS *0+ + SQRS *0+, AR0 + SQRS *BR0+ + SQRS *BR0+, AR0 + LTS 00H + LTS * + LTS *, AR0 + LTS *- + LTS *-, AR0 + LTS *+ + LTS *+, AR0 + LTS *BR0- + LTS *BR0-, AR0 + LTS *0- + LTS *0-, AR0 + LTS *0+ + LTS *0+, AR0 + LTS *BR0+ + LTS *BR0+, AR0 + MACD 5D01H, 00H + MACD 5D81H, * + MACD 5D89H, *, AR0 + MACD 5D91H, *- + MACD 5D99H, *-, AR0 + MACD 5DA1H, *+ + MACD 5DA9H, *+, AR0 + MACD 5DC1H, *BR0- + MACD 5DC9H, *BR0-, AR0 + MACD 5DD1H, *0- + MACD 5DD9H, *0-, AR0 + MACD 5DE1H, *0+ + MACD 5DE9H, *0+, AR0 + MACD 5DF1H, *BR0+ + MACD 5DF9H, *BR0+, AR0 + MAC 5E01H, 00H + MAC 5E81H, * + MAC 5E89H, *, AR0 + MAC 5E91H, *- + MAC 5E99H, *-, AR0 + MAC 5EA1H, *+ + MAC 5EA9H, *+, AR0 + MAC 5EC1H, *BR0- + MAC 5EC9H, *BR0-, AR0 + MAC 5ED1H, *0- + MAC 5ED9H, *0-, AR0 + MAC 5EE1H, *0+ + MAC 5EE9H, *0+, AR0 + MAC 5EF1H, *BR0+ + MAC 5EF9H, *BR0+, AR0 + BC 5F81H + BC 5F89H, *, AR0 + BC 5F91H, *- + BC 5F99H, *-, AR0 + BC 5FA1H, *+ + BC 5FA9H, *+, AR0 + BC 5FC1H, *BR0- + BC 5FC9H, *BR0-, AR0 + BC 5FD1H, *0- + BC 5FD9H, *0-, AR0 + BC 5FE1H, *0+ + BC 5FE9H, *0+, AR0 + BC 5FF1H, *BR0+ + BC 5FF9H, *BR0+, AR0 + BNC 6081H + BNC 6089H, *, AR0 + BNC 6091H, *- + BNC 6099H, *-, AR0 + BNC 60A1H, *+ + BNC 60A9H, *+, AR0 + BNC 60C1H, *BR0- + BNC 60C9H, *BR0-, AR0 + BNC 60D1H, *0- + BNC 60D9H, *0-, AR0 + BNC 60E1H, *0+ + BNC 60E9H, *0+, AR0 + BNC 60F1H, *BR0+ + BNC 60F9H, *BR0+, AR0 + SACL 00H + SACL * + SACL *, 0, AR0 + SACL *- + SACL *-, 0, AR0 + SACL *+ + SACL *+, 0, AR0 + SACL *BR0- + SACL *BR0-, 0, AR0 + SACL *0- + SACL *0-, 0, AR0 + SACL *0+ + SACL *0+, 0, AR0 + SACL *BR0+ + SACL *BR0+, 0, AR0 + SACL 00H, 1 + SACL *, 1 + SACL *-, 1 + SACL *+, 1 + SACL *BR0-, 1 + SACL *0-, 1 + SACL *0+, 1 + SACL *BR0+, 1 + SACH 00H + SACH * + SACH *, 0, AR0 + SACH *- + SACH *-, 0, AR0 + SACH *+ + SACH *+, 0, AR0 + SACH *BR0- + SACH *BR0-, 0, AR0 + SACH *0- + SACH *0-, 0, AR0 + SACH *0+ + SACH *0+, 0, AR0 + SACH *BR0+ + SACH *BR0+, 0, AR0 + SACH 00H, 1 + SACH *, 1 + SACH *-, 1 + SACH *+, 1 + SACH *BR0-, 1 + SACH *0-, 1 + SACH *0+, 1 + SACH *BR0+, 1 + SAR AR0, 00H + SAR AR0, * + SAR AR0, *, AR0 + SAR AR0, *- + SAR AR0, *-, AR0 + SAR AR0, *+ + SAR AR0, *+, AR0 + SAR AR0, *BR0- + SAR AR0, *BR0-, AR0 + SAR AR0, *0- + SAR AR0, *0-, AR0 + SAR AR0, *0+ + SAR AR0, *0+, AR0 + SAR AR0, *BR0+ + SAR AR0, *BR0+, AR0 + SST 00H + SST * + SST *, AR0 + SST *- + SST *-, AR0 + SST *+ + SST *+, AR0 + SST *BR0- + SST *BR0-, AR0 + SST *0- + SST *0-, AR0 + SST *0+ + SST *0+, AR0 + SST *BR0+ + SST *BR0+, AR0 + SST1 00H + SST1 * + SST1 *, AR0 + SST1 *- + SST1 *-, AR0 + SST1 *+ + SST1 *+, AR0 + SST1 *BR0- + SST1 *BR0-, AR0 + SST1 *0- + SST1 *0-, AR0 + SST1 *0+ + SST1 *0+, AR0 + SST1 *BR0+ + SST1 *BR0+, AR0 + POPD 00H + POPD * + POPD *, AR0 + POPD *- + POPD *-, AR0 + POPD *+ + POPD *+, AR0 + POPD *BR0- + POPD *BR0-, AR0 + POPD *0- + POPD *0-, AR0 + POPD *0+ + POPD *0+, AR0 + POPD *BR0+ + POPD *BR0+, AR0 + ZALR 00H + ZALR * + ZALR *, AR0 + ZALR *- + ZALR *-, AR0 + ZALR *+ + ZALR *+, AR0 + ZALR *BR0- + ZALR *BR0-, AR0 + ZALR *0- + ZALR *0-, AR0 + ZALR *0+ + ZALR *0+, AR0 + ZALR *BR0+ + ZALR *BR0+, AR0 + SPL 00H + SPL * + SPL *, AR0 + SPL *- + SPL *-, AR0 + SPL *+ + SPL *+, AR0 + SPL *BR0- + SPL *BR0-, AR0 + SPL *0- + SPL *0-, AR0 + SPL *0+ + SPL *0+, AR0 + SPL *BR0+ + SPL *BR0+, AR0 + SPH 00H + SPH * + SPH *, AR0 + SPH *- + SPH *-, AR0 + SPH *+ + SPH *+, AR0 + SPH *BR0- + SPH *BR0-, AR0 + SPH *0- + SPH *0-, AR0 + SPH *0+ + SPH *0+, AR0 + SPH *BR0+ + SPH *BR0+, AR0 + ADRK 0 + SBRK 0 + IN 00H, 0 + IN *, 0 + IN *, 0, AR0 + IN *-, 0 + IN *-, 0, AR0 + IN *+, 0 + IN *+, 0, AR0 + IN *BR0-, 0 + IN *BR0-, 0, AR0 + IN *0-, 0 + IN *0-, 0, AR0 + IN *0+, 0 + IN *0+, 0, AR0 + IN *BR0+, 0 + IN *BR0+, 0, AR0 + BIT 00H, 0 + BIT *, 0 + BIT *, 0, AR0 + BIT *-, 0 + BIT *-, 0, AR0 + BIT *+, 0 + BIT *+, 0, AR0 + BIT *BR0-, 0 + BIT *BR0-, 0, AR0 + BIT *0-, 0 + BIT *0-, 0, AR0 + BIT *0+, 0 + BIT *0+, 0, AR0 + BIT *BR0+, 0 + BIT *BR0+, 0, AR0 + MPYK 0 + MPYK -4096 + LARK AR0, 0 + LDPK 000H + ZAC + LACK 1 + RPTK 0 + ADDK 0 + SUBK 0 + EINT + DINT + ROVM + SOVM + RSXM + SSXM + SPM 0 + RXF + SXF + FORT 0 + PAC + APAC + SPAC + SFL + SFR + ABS + PUSH + POP + TRAP + IDLE + RTXM + STXM + NEG + CALA + BACC + RET + CMPL + RC + SC + RTC + STC + ROL + ROR + RFSM + SFSM + RHM + SHM + CONF 0 + CMPR 0 + NORM * + NORM *- + NORM *+ + NORM *BR0- + NORM *0- + NORM *0+ + NORM *BR0+ + MPYU 00H + MPYU * + MPYU *, AR0 + MPYU *- + MPYU *-, AR0 + MPYU *+ + MPYU *+, AR0 + MPYU *BR0- + MPYU *BR0-, AR0 + MPYU *0- + MPYU *0-, AR0 + MPYU *0+ + MPYU *0+, AR0 + MPYU *BR0+ + MPYU *BR0+, AR0 + LRLK AR0, 0D101H + LALK 0D102H + ADLK 0D103H + SBLK 0D104H + ANDK 0D105H + ORK 0D106H + XORK 0D107H + LALK 0D202H, 1 + ADLK 0D203H, 1 + SBLK 0D204H, 1 + ANDK 0D205H, 1 + ORK 0D206H, 1 + XORK 0D207H, 1 + OUT 00H, 0 + OUT *, 0 + OUT *, 0, AR0 + OUT *-, 0 + OUT *-, 0, AR0 + OUT *+, 0 + OUT *+, 0, AR0 + OUT *BR0-, 0 + OUT *BR0-, 0, AR0 + OUT *0-, 0 + OUT *0-, 0, AR0 + OUT *0+, 0 + OUT *0+, 0, AR0 + OUT *BR0+, 0 + OUT *BR0+, 0, AR0 + BV 0F181H + BV 0F189H, *, AR0 + BV 0F191H, *- + BV 0F199H, *-, AR0 + BV 0F1A1H, *+ + BV 0F1A9H, *+, AR0 + BV 0F1C1H, *BR0- + BV 0F1C9H, *BR0-, AR0 + BV 0F1D1H, *0- + BV 0F1D9H, *0-, AR0 + BV 0F1E1H, *0+ + BV 0F1E9H, *0+, AR0 + BV 0F1F1H, *BR0+ + BV 0F1F9H, *BR0+, AR0 + BGZ 0F281H + BGZ 0F289H, *, AR0 + BGZ 0F291H, *- + BGZ 0F299H, *-, AR0 + BGZ 0F2A1H, *+ + BGZ 0F2A9H, *+, AR0 + BGZ 0F2C1H, *BR0- + BGZ 0F2C9H, *BR0-, AR0 + BGZ 0F2D1H, *0- + BGZ 0F2D9H, *0-, AR0 + BGZ 0F2E1H, *0+ + BGZ 0F2E9H, *0+, AR0 + BGZ 0F2F1H, *BR0+ + BGZ 0F2F9H, *BR0+, AR0 + BLEZ 0F381H + BLEZ 0F389H, *, AR0 + BLEZ 0F391H, *- + BLEZ 0F399H, *-, AR0 + BLEZ 0F3A1H, *+ + BLEZ 0F3A9H, *+, AR0 + BLEZ 0F3C1H, *BR0- + BLEZ 0F3C9H, *BR0-, AR0 + BLEZ 0F3D1H, *0- + BLEZ 0F3D9H, *0-, AR0 + BLEZ 0F3E1H, *0+ + BLEZ 0F3E9H, *0+, AR0 + BLEZ 0F3F1H, *BR0+ + BLEZ 0F3F9H, *BR0+, AR0 + BLZ 0F481H + BLZ 0F489H, *, AR0 + BLZ 0F491H, *- + BLZ 0F499H, *-, AR0 + BLZ 0F4A1H, *+ + BLZ 0F4A9H, *+, AR0 + BLZ 0F4C1H, *BR0- + BLZ 0F4C9H, *BR0-, AR0 + BLZ 0F4D1H, *0- + BLZ 0F4D9H, *0-, AR0 + BLZ 0F4E1H, *0+ + BLZ 0F4E9H, *0+, AR0 + BLZ 0F4F1H, *BR0+ + BLZ 0F4F9H, *BR0+, AR0 + BGEZ 0F581H + BGEZ 0F589H, *, AR0 + BGEZ 0F591H, *- + BGEZ 0F599H, *-, AR0 + BGEZ 0F5A1H, *+ + BGEZ 0F5A9H, *+, AR0 + BGEZ 0F5C1H, *BR0- + BGEZ 0F5C9H, *BR0-, AR0 + BGEZ 0F5D1H, *0- + BGEZ 0F5D9H, *0-, AR0 + BGEZ 0F5E1H, *0+ + BGEZ 0F5E9H, *0+, AR0 + BGEZ 0F5F1H, *BR0+ + BGEZ 0F5F9H, *BR0+, AR0 + BNZ 0F681H + BNZ 0F689H, *, AR0 + BNZ 0F691H, *- + BNZ 0F699H, *-, AR0 + BNZ 0F6A1H, *+ + BNZ 0F6A9H, *+, AR0 + BNZ 0F6C1H, *BR0- + BNZ 0F6C9H, *BR0-, AR0 + BNZ 0F6D1H, *0- + BNZ 0F6D9H, *0-, AR0 + BNZ 0F6E1H, *0+ + BNZ 0F6E9H, *0+, AR0 + BNZ 0F6F1H, *BR0+ + BNZ 0F6F9H, *BR0+, AR0 + BZ 0F781H + BZ 0F789H, *, AR0 + BZ 0F791H, *- + BZ 0F799H, *-, AR0 + BZ 0F7A1H, *+ + BZ 0F7A9H, *+, AR0 + BZ 0F7C1H, *BR0- + BZ 0F7C9H, *BR0-, AR0 + BZ 0F7D1H, *0- + BZ 0F7D9H, *0-, AR0 + BZ 0F7E1H, *0+ + BZ 0F7E9H, *0+, AR0 + BZ 0F7F1H, *BR0+ + BZ 0F7F9H, *BR0+, AR0 + BNV 0F881H + BNV 0F889H, *, AR0 + BNV 0F891H, *- + BNV 0F899H, *-, AR0 + BNV 0F8A1H, *+ + BNV 0F8A9H, *+, AR0 + BNV 0F8C1H, *BR0- + BNV 0F8C9H, *BR0-, AR0 + BNV 0F8D1H, *0- + BNV 0F8D9H, *0-, AR0 + BNV 0F8E1H, *0+ + BNV 0F8E9H, *0+, AR0 + BNV 0F8F1H, *BR0+ + BNV 0F8F9H, *BR0+, AR0 + BBZ 0F981H + BBZ 0F989H, *, AR0 + BBZ 0F991H, *- + BBZ 0F999H, *-, AR0 + BBZ 0F9A1H, *+ + BBZ 0F9A9H, *+, AR0 + BBZ 0F9C1H, *BR0- + BBZ 0F9C9H, *BR0-, AR0 + BBZ 0F9D1H, *0- + BBZ 0F9D9H, *0-, AR0 + BBZ 0F9E1H, *0+ + BBZ 0F9E9H, *0+, AR0 + BBZ 0F9F1H, *BR0+ + BBZ 0F9F9H, *BR0+, AR0 + BBNZ 0FA81H + BBNZ 0FA89H, *, AR0 + BBNZ 0FA91H, *- + BBNZ 0FA99H, *-, AR0 + BBNZ 0FAA1H, *+ + BBNZ 0FAA9H, *+, AR0 + BBNZ 0FAC1H, *BR0- + BBNZ 0FAC9H, *BR0-, AR0 + BBNZ 0FAD1H, *0- + BBNZ 0FAD9H, *0-, AR0 + BBNZ 0FAE1H, *0+ + BBNZ 0FAE9H, *0+, AR0 + BBNZ 0FAF1H, *BR0+ + BBNZ 0FAF9H, *BR0+, AR0 + BIOZ 0FB81H + BIOZ 0FB89H, *, AR0 + BIOZ 0FB91H, *- + BIOZ 0FB99H, *-, AR0 + BIOZ 0FBA1H, *+ + BIOZ 0FBA9H, *+, AR0 + BIOZ 0FBC1H, *BR0- + BIOZ 0FBC9H, *BR0-, AR0 + BIOZ 0FBD1H, *0- + BIOZ 0FBD9H, *0-, AR0 + BIOZ 0FBE1H, *0+ + BIOZ 0FBE9H, *0+, AR0 + BIOZ 0FBF1H, *BR0+ + BIOZ 0FBF9H, *BR0+, AR0 + BANZ 0FC81H + BANZ 0FC89H, *, AR0 + BANZ 0FC91H, *- + BANZ 0FC99H, *-, AR0 + BANZ 0FCA1H, *+ + BANZ 0FCA9H, *+, AR0 + BANZ 0FCC1H, *BR0- + BANZ 0FCC9H, *BR0-, AR0 + BANZ 0FCD1H, *0- + BANZ 0FCD9H, *0-, AR0 + BANZ 0FCE1H, *0+ + BANZ 0FCE9H, *0+, AR0 + BANZ 0FCF1H, *BR0+ + BANZ 0FCF9H, *BR0+, AR0 + BLKP 0FD01H, 00H + BLKP 0FD81H, * + BLKP 0FD89H, *, AR0 + BLKP 0FD91H, *- + BLKP 0FD99H, *-, AR0 + BLKP 0FDA1H, *+ + BLKP 0FDA9H, *+, AR0 + BLKP 0FDC1H, *BR0- + BLKP 0FDC9H, *BR0-, AR0 + BLKP 0FDD1H, *0- + BLKP 0FDD9H, *0-, AR0 + BLKP 0FDE1H, *0+ + BLKP 0FDE9H, *0+, AR0 + BLKP 0FDF1H, *BR0+ + BLKP 0FDF9H, *BR0+, AR0 + BLKD 0FE01H, 00H + BLKD 0FE81H, * + BLKD 0FE89H, *, AR0 + BLKD 0FE91H, *- + BLKD 0FE99H, *-, AR0 + BLKD 0FEA1H, *+ + BLKD 0FEA9H, *+, AR0 + BLKD 0FEC1H, *BR0- + BLKD 0FEC9H, *BR0-, AR0 + BLKD 0FED1H, *0- + BLKD 0FED9H, *0-, AR0 + BLKD 0FEE1H, *0+ + BLKD 0FEE9H, *0+, AR0 + BLKD 0FEF1H, *BR0+ + BLKD 0FEF9H, *BR0+, AR0 + CALL 0FF81H + CALL 0FF89H, *, AR0 + CALL 0FF91H, *- + CALL 0FF99H, *-, AR0 + CALL 0FFA1H, *+ + CALL 0FFA9H, *+, AR0 + CALL 0FFC1H, *BR0- + CALL 0FFC9H, *BR0-, AR0 + CALL 0FFD1H, *0- + CALL 0FFD9H, *0-, AR0 + CALL 0FFE1H, *0+ + CALL 0FFE9H, *0+, AR0 + CALL 0FFF1H, *BR0+ + CALL 0FFF9H, *BR0+, AR0 + B 0081H + B 0089H, *, AR0 + B 0091H, *- + B 0099H, *-, AR0 + B 00A1H, *+ + B 00A9H, *+, AR0 + B 00C1H, *BR0- + B 00C9H, *BR0-, AR0 + B 00D1H, *0- + B 00D9H, *0-, AR0 + B 00E1H, *0+ + B 00E9H, *0+, AR0 + B 00F1H, *BR0+ + B 00F9H, *BR0+, AR0 diff --git a/test/gen_tms32010.cpp b/test/gen_tms32010.cpp index a9216e79a..e09ceec63 100644 --- a/test/gen_tms32010.cpp +++ b/test/gen_tms32010.cpp @@ -26,6 +26,7 @@ int main(int argc, const char **argv) { if (driver.main(argc, argv)) return 1; + dis32010.setOption("use-port-name", "off"); TestGenerator generator(driver, dis32010, 0x0100); generator.generate(); diff --git a/test/reference/test_tms3202x.inc b/test/reference/test_tms3202x.inc new file mode 100644 index 000000000..8d6c2c404 --- /dev/null +++ b/test/reference/test_tms3202x.inc @@ -0,0 +1,137 @@ +;;; Copyright 2025 Tadashi G. Takaoka +;;; +;;; Licensed under the Apache License, Version 2.0 (the "License"); +;;; you may not use this file except in compliance with the License. +;;; You may obtain a copy of the License at +;;; +;;; http://www.apache.org/licenses/LICENSE-2.0 +;;; +;;; Unless required by applicable law or agreed to in writing, software +;;; distributed under the License is distributed on an "AS IS" BASIS, +;;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;;; See the License for the specific language governing permissions and +;;; limitations under the License. + + add 23H, 1 + sub 34H, 2 + lac 45H, 3 + lar AR4, 56H + mpy *-, AR2 + sqra *+, 3 + lt *0-, AR6 + lta *0+, 7 + ltp *BR0+ + ltd 01H + zalh 12H + zals 23H + lact 34H + subh 56H + subs 67H + subt 78H + subc *, 1 + addh *-, AR2 + adds *+, 3 + addt 4BH + rpt *BR0-, AR5 + xor *0-, 6 + or *0+, AR7 + and *BR0+ + lst 12H + lst1 23H + ldp 34H + lph 45H + pshd 56H + nop + mar 67H + larp AR0 + larp 7 + dmov 78H + bitt *, 1 + tblr *-, AR2 + tblw *+, 3 + sqrs 5BH + lts *BR0-, AR5 + macd 0F012H, *0-, 6 + mac 0123H, *0+, AR7 + sacl *, 7, AR1 + sach *+, 0, AR4 + sar AR1, 23H + sst *-, 2 + sst1 *+, AR3 + popd 7BH + in *+, 9, 3 + bit 76H, 8 + mpyk 0BCDH + lark AR7, 0C8H + ldpk 1CAH + zac + lack 0CBH + rptk 0CCH + eint + dint + rovm + sovm + rsxm + ssxm + spm 0 + spm 3 + rxf + sxf + fort 0 + fort 1 + pac + apac + spac + sfl + sfr + abs + push + pop + trap + idle + rtxm + stxm + neg + cala + bacc + ret + cmpl + cmpr 0 + cmpr 3 + norm * + lrlk 0, 0D1D2H + lrlk AR7, 0D8D9H + lalk 2345H + lalk 2345H, 14 + adlk 3456H + adlk 3456H, 14 + sblk 4567H + sblk 4567H, 14 + andk 5678H + andk 5678H, 14 + ork 6789H + ork 6789H, 14 + xork 789AH + xork 789AH, 14 + out *BR0-, 13, AR3 + bv 0ABCDH, *, 1 + bgz 0BCDEH, *-, AR2 + blez 0CDEFH, *+, 3 + blz 0EF01H, *BR0-, AR5 + bgez 0F012H, *0-, 6 + bnz 00123H, *0+, AR7 + bz 01234H, *BR0+ + bnv 0ABCDH, *, 1 + bbz 0BCDEH, *-, AR2 + bbnz 0CDEFH, *+, 3 + bioz 0FCFDH, *BR0+, AR3 + banz 0EF01H, *BR0-, 5 + blkp 0F012H, *0-, AR6 + blkd 00123H, *0+, 7 + call 0BA98H, *0-, AR4 + b 0ABCDH, *, 1 + +;;; Local Variables: +;;; mode: asm +;;; End: +;;; vim: set ft=asm: diff --git a/test/reference/test_tms320c25.asm b/test/reference/test_tms320c25.asm new file mode 100644 index 000000000..18d761f1f --- /dev/null +++ b/test/reference/test_tms320c25.asm @@ -0,0 +1,25 @@ +;;; Copyright 2025 Tadashi G. Takaoka +;;; +;;; Licensed under the Apache License, Version 2.0 (the "License"); +;;; you may not use this file except in compliance with the License. +;;; You may obtain a copy of the License at +;;; +;;; http://www.apache.org/licenses/LICENSE-2.0 +;;; +;;; Unless required by applicable law or agreed to in writing, software +;;; distributed under the License is distributed on an "AS IS" BASIS, +;;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;;; See the License for the specific language governing permissions and +;;; limitations under the License. + + cpu 320C25 + org 0100H + include "test_tms3202x.inc" + include "test_tms320c2x.inc" + cnfd + cnfp + end +;;; Local Variables: +;;; mode: asm +;;; End: +;;; vim: set ft=asm: diff --git a/test/reference/test_tms320c25.hex b/test/reference/test_tms320c25.hex new file mode 100644 index 000000000..2121dacbd --- /dev/null +++ b/test/reference/test_tms320c25.hex @@ -0,0 +1,24 @@ +:1002000023013412452356349A38AB39DE3CEF3D96 +:10021000F03E013F12402341344256446745784640 +:1002200089479A48AB494B4ACD4BDE4CEF4DF04ED7 +:100230001250235134524553565400556755885532 +:100240008F55785689579A58AB595B5ACD5BDE5C0F +:1002500012F0EF5D23018967AC6823719A78AB795E +:100260007B7AAB897698CDABC8C7CAC900CACBCA5E +:10027000CCCB00CE01CE02CE03CE06CE07CE08CE2A +:100280000BCE0CCE0DCE0ECE0FCE14CE15CE16CE7E +:1002900018CE19CE1BCE1CCE1DCE1ECE1FCE20CE0C +:1002A00021CE23CE24CE25CE26CE27CE50CE53CE61 +:1002B00082CE00D0D2D100D7D9D801D0452301DEDB +:1002C000452302D0563402DE563403D0674503DEA0 +:1002D000674504D0785604DE785605D0896705DE78 +:1002E000896706D09A7806DE9A78CBED89F0CDAB97 +:1002F0009AF1DEBCABF2EFCDCDF301EFDEF412F0FC +:10030000EFF52301F0F6341289F7CDAB9AF8DEBC95 +:10031000ABF9EFCDFBFAFDFCCDFB01EFDEFC12F0FB +:10032000EFFD2301DCFE98BA89FFCDAB3B3ACD3B14 +:100330002143ED4FDC5E98BAED5FA9CBCD7BDE7C2F +:10034000EF7D7F7E807FCDCCCECD30CE31CE32CE14 +:1003500033CE34CE35CE36CE37CE38CE39CE92CE21 +:0C036000A2CEE2CEC2CEEDCF04CE05CE80 +:00000001FF diff --git a/test/reference/test_tms320c26.asm b/test/reference/test_tms320c26.asm new file mode 100644 index 000000000..8275dda46 --- /dev/null +++ b/test/reference/test_tms320c26.asm @@ -0,0 +1,25 @@ +;;; Copyright 2025 Tadashi G. Takaoka +;;; +;;; Licensed under the Apache License, Version 2.0 (the "License"); +;;; you may not use this file except in compliance with the License. +;;; You may obtain a copy of the License at +;;; +;;; http://www.apache.org/licenses/LICENSE-2.0 +;;; +;;; Unless required by applicable law or agreed to in writing, software +;;; distributed under the License is distributed on an "AS IS" BASIS, +;;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;;; See the License for the specific language governing permissions and +;;; limitations under the License. + + cpu 320C26 + org 0100H + include "test_tms3202x.inc" + include "test_tms320c2x.inc" + conf 0 + conf 3 + end +;;; Local Variables: +;;; mode: asm +;;; End: +;;; vim: set ft=asm: diff --git a/test/reference/test_tms320c26.hex b/test/reference/test_tms320c26.hex new file mode 100644 index 000000000..7c9daec8d --- /dev/null +++ b/test/reference/test_tms320c26.hex @@ -0,0 +1,24 @@ +:1002000023013412452356349A38AB39DE3CEF3D96 +:10021000F03E013F12402341344256446745784640 +:1002200089479A48AB494B4ACD4BDE4CEF4DF04ED7 +:100230001250235134524553565400556755885532 +:100240008F55785689579A58AB595B5ACD5BDE5C0F +:1002500012F0EF5D23018967AC6823719A78AB795E +:100260007B7AAB897698CDABC8C7CAC900CACBCA5E +:10027000CCCB00CE01CE02CE03CE06CE07CE08CE2A +:100280000BCE0CCE0DCE0ECE0FCE14CE15CE16CE7E +:1002900018CE19CE1BCE1CCE1DCE1ECE1FCE20CE0C +:1002A00021CE23CE24CE25CE26CE27CE50CE53CE61 +:1002B00082CE00D0D2D100D7D9D801D0452301DEDB +:1002C000452302D0563402DE563403D0674503DEA0 +:1002D000674504D0785604DE785605D0896705DE78 +:1002E000896706D09A7806DE9A78CBED89F0CDAB97 +:1002F0009AF1DEBCABF2EFCDCDF301EFDEF412F0FC +:10030000EFF52301F0F6341289F7CDAB9AF8DEBC95 +:10031000ABF9EFCDFBFAFDFCCDFB01EFDEFC12F0FB +:10032000EFFD2301DCFE98BA89FFCDAB3B3ACD3B14 +:100330002143ED4FDC5E98BAED5FA9CBCD7BDE7C2F +:10034000EF7D7F7E807FCDCCCECD30CE31CE32CE14 +:1003500033CE34CE35CE36CE37CE38CE39CE92CE21 +:0C036000A2CEE2CEC2CEEDCF3CCE3FCE0E +:00000001FF diff --git a/test/reference/test_tms320c2x.inc b/test/reference/test_tms320c2x.inc new file mode 100644 index 000000000..52b25fedb --- /dev/null +++ b/test/reference/test_tms320c2x.inc @@ -0,0 +1,47 @@ +;;; Copyright 2025 Tadashi G. Takaoka +;;; +;;; Licensed under the Apache License, Version 2.0 (the "License"); +;;; you may not use this file except in compliance with the License. +;;; You may obtain a copy of the License at +;;; +;;; http://www.apache.org/licenses/LICENSE-2.0 +;;; +;;; Unless required by applicable law or agreed to in writing, software +;;; distributed under the License is distributed on an "AS IS" BASIS, +;;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;;; See the License for the specific language governing permissions and +;;; limitations under the License. + + mpya 3BH + mpys *BR0-, AR5 + addc 21H + subb *0+, 5 + bc 0BA98H, *0-, AR4 + bnc 0CBA9H, *0+, 5 + zalr *BR0-, AR5 + spl *0-, 6 + sph *0+, AR7 + adrk 7FH + sbrk 80H + addk 0CDH + subk 0CEH + rc + sc + rtc + stc + rol + ror + rfsm + sfsm + rhm + shm + norm *- + norm *+ + norm *0+ + norm *BR0- + mpyu *0+, AR5 + +;;; Local Variables: +;;; mode: asm +;;; End: +;;; vim: set ft=asm: diff --git a/test/test_asm_tms32010.cpp b/test/test_asm_tms32010.cpp index 304d80d0e..2500d111f 100644 --- a/test/test_asm_tms32010.cpp +++ b/test/test_asm_tms32010.cpp @@ -32,6 +32,30 @@ bool is32015() { return strcmp_P("32015", assembler.config().cpu_P()) == 0; } +bool is3201x() { + return is32010() || is32015(); +} + +bool is32020() { + return strcmp_P("32020", assembler.config().cpu_P()) == 0; +} + +bool is320C25() { + return strcmp_P("320C25", assembler.config().cpu_P()) == 0; +} + +bool is320C26() { + return strcmp_P("320C26", assembler.config().cpu_P()) == 0; +} + +bool is3202x() { + return is32020() || is320C25() || is320C26(); +} + +bool is320C2x() { + return is320C25() || is320C26(); +} + void set_up() { assembler.reset(); } @@ -48,14 +72,32 @@ void test_cpu() { EQUALS("cpu 32015", true, assembler.setCpu("32015")); EQUALS_P("cpu 32015", "32015", assembler.config().cpu_P()); + EQUALS("cpu 32020", true, assembler.setCpu("32020")); + EQUALS_P("cpu 32020", "32020", assembler.config().cpu_P()); + + EQUALS("cpu 320C25", true, assembler.setCpu("320C25")); + EQUALS_P("cpu 320C25", "320C25", assembler.config().cpu_P()); + + EQUALS("cpu 320C26", true, assembler.setCpu("320C26")); + EQUALS_P("cpu 320C26", "320C26", assembler.config().cpu_P()); + EQUALS("cpu TMS32010", true, assembler.setCpu("TMS32010")); EQUALS_P("cpu TMS32010", "32010", assembler.config().cpu_P()); EQUALS("cpu TMS32015", true, assembler.setCpu("TMS32015")); EQUALS_P("cpu TMS32015", "32015", assembler.config().cpu_P()); + + EQUALS("cpu TMS32020", true, assembler.setCpu("TMS32020")); + EQUALS_P("cpu TMS32020", "32020", assembler.config().cpu_P()); + + EQUALS("cpu TMS320C25", true, assembler.setCpu("TMS320C25")); + EQUALS_P("cpu TMS320C25", "320C25", assembler.config().cpu_P()); + + EQUALS("cpu TMS320C26", true, assembler.setCpu("TMS320C26")); + EQUALS_P("cpu TMS320C26", "320C26", assembler.config().cpu_P()); } -void test_accumrator() { +void test_accumrator_1x() { TEST("ABS", 0x7F88); TEST("ADD 70H", 0x0070); @@ -253,7 +295,345 @@ void test_accumrator() { TEST("ZALS *+, AR0", 0x66A0); } -void test_auxiliary() { +void test_accumrator_2x() { + TEST("ABS", 0xCE1B); + + TEST("ADD 70H", 0x0070); + TEST("ADD 70H, 15", 0x0F70); + ERRT("ADD 70H, 16", OVERFLOW_RANGE, "16", 0x0070); + TEST("ADD *", 0x0080); + TEST("ADD *, 0, AR0", 0x0088); + TEST("ADD *, 0, AR7", 0x008F); + TEST("ADD *-", 0x0090); + TEST("ADD *+", 0x00A0); + TEST("ADD *BR0-", 0x00C0); + TEST("ADD *0-", 0x00D0); + TEST("ADD *0+", 0x00E0); + TEST("ADD *BR0+", 0x00F0); + TEST("ADD *, 1", 0x0180); + TEST("ADD *-, 2", 0x0290); + TEST("ADD *+, 3", 0x03A0); + TEST("ADD *, 0, AR0", 0x0088); + TEST("ADD *, 4, AR1", 0x0489); + TEST("ADD *-, 4, AR0", 0x0498); + TEST("ADD *-, 0, AR1", 0x0099); + TEST("ADD *+, 15, AR0", 0x0FA8); + TEST("ADD *BR0+, 15, AR7", 0x0FFF); + + TEST("ADDH 70H", 0x4870); + TEST("ADDH *", 0x4880); + TEST("ADDH *-", 0x4890); + TEST("ADDH *+", 0x48A0); + TEST("ADDH *, AR0", 0x4888); + TEST("ADDH *-, AR1", 0x4899); + TEST("ADDH *+, AR0", 0x48A8); + + TEST("ADDS 70H", 0x4970); + TEST("ADDS *", 0x4980); + TEST("ADDS *-", 0x4990); + TEST("ADDS *+", 0x49A0); + TEST("ADDS *, AR0", 0x4988); + TEST("ADDS *-, AR1", 0x4999); + TEST("ADDS *+, AR0", 0x49A8); + + TEST("ADDT 70H", 0x4A70); + TEST("ADDT *", 0x4A80); + TEST("ADDT *-", 0x4A90); + TEST("ADDT *+", 0x4AA0); + TEST("ADDT *, AR0", 0x4A88); + TEST("ADDT *-, AR1", 0x4A99); + TEST("ADDT *+, AR0", 0x4AA8); + + TEST("ADLK 0", 0xD002, 0x0000); + TEST("ADLK 0FFFFH", 0xD002, 0xFFFF); + TEST("ADLK 18, 4", 0xD402, 0x0012); + TEST("ADLK 00FFH, 10", 0xDA02, 0x00FF); + TEST("ADLK 0FFFFH, 15", 0xDF02, 0xFFFF); + + if (is320C2x()) { + TEST("ADDC 70H", 0x4370); + TEST("ADDC *", 0x4380); + TEST("ADDC *-", 0x4390); + TEST("ADDC *+", 0x43A0); + TEST("ADDC *, AR0", 0x4388); + TEST("ADDC *-, AR1", 0x4399); + TEST("ADDC *+, AR0", 0x43A8); + + TEST("ADDK 0", 0xCC00); + TEST("ADDK 255", 0xCCFF); + } + + TEST("AND 70H", 0x4E70); + TEST("AND *", 0x4E80); + TEST("AND *-", 0x4E90); + TEST("AND *+", 0x4EA0); + TEST("AND *, AR0", 0x4E88); + TEST("AND *-, AR1", 0x4E99); + TEST("AND *+, AR0", 0x4EA8); + + TEST("ANDK 0", 0xD004, 0x0000); + TEST("ANDK 0FFFFH", 0xD004, 0xFFFF); + TEST("ANDK 18, 4", 0xD404, 0x0012); + TEST("ANDK 00FFH, 10", 0xDA04, 0x00FF); + TEST("ANDK 0FFFFH, 15", 0xDF04, 0xFFFF); + + TEST("CMPL", 0xCE27); + + TEST("LAC 70H", 0x2070); + TEST("LAC 70H, 15", 0x2F70); + TEST("LAC *", 0x2080); + TEST("LAC *, 0, AR0", 0x2088); + TEST("LAC *, 0, AR7", 0x208F); + TEST("LAC *-", 0x2090); + TEST("LAC *+", 0x20A0); + TEST("LAC *BR0-", 0x20C0); + TEST("LAC *0-", 0x20D0); + TEST("LAC *0+", 0x20E0); + TEST("LAC *BR0+", 0x20F0); + TEST("LAC *, 1", 0x2180); + TEST("LAC *-, 2", 0x2290); + TEST("LAC *+, 3", 0x23A0); + TEST("LAC *, 0, AR0", 0x2088); + TEST("LAC *, 4, AR1", 0x2489); + TEST("LAC *-, 4, AR0", 0x2498); + TEST("LAC *-, 0, AR1", 0x2099); + TEST("LAC *+, 15, AR0", 0x2FA8); + TEST("LAC *BR0+, 15, AR7", 0x2FFF); + + TEST("ZAC", 0xCA00); + TEST("LACK 1", 0xCA01); + TEST("LACK 255", 0xCAFF); + + TEST("LACT 70H", 0x4270); + TEST("LACT *", 0x4280); + TEST("LACT *-", 0x4290); + TEST("LACT *+", 0x42A0); + TEST("LACT *, AR0", 0x4288); + TEST("LACT *-, AR1", 0x4299); + TEST("LACT *+, AR0", 0x42A8); + + TEST("LALK 0", 0xD001, 0x0000); + TEST("LALK 0FFFFH", 0xD001, 0xFFFF); + TEST("LALK 18, 4", 0xD401, 0x0012); + TEST("LALK 00FFH, 10", 0xDA01, 0x00FF); + TEST("LALK 0FFFFH, 15", 0xDF01, 0xFFFF); + + TEST("NEG", 0xCE23); + + if (is32020()) { + TEST("NORM", 0xCE82); + } + if (is320C2x()) { + TEST("NORM *", 0xCE82); + TEST("NORM *-", 0xCE92); + TEST("NORM *+", 0xCEA2); + TEST("NORM *BR0-", 0xCEC2); + TEST("NORM *0-", 0xCED2); + TEST("NORM *0+", 0xCEE2); + TEST("NORM *BR0+", 0xCEF2); + } + + TEST("OR 70H", 0x4D70); + TEST("OR *", 0x4D80); + TEST("OR *-", 0x4D90); + TEST("OR *+", 0x4DA0); + TEST("OR *, AR0", 0x4D88); + TEST("OR *-, AR1", 0x4D99); + TEST("OR *+, AR0", 0x4DA8); + + TEST("ORK 0", 0xD005, 0x0000); + TEST("ORK 0FFFFH", 0xD005, 0xFFFF); + TEST("ORK 18, 4", 0xD405, 0x0012); + TEST("ORK 00FFH, 10", 0xDA05, 0x00FF); + TEST("ORK 0FFFFH, 15", 0xDF05, 0xFFFF); + + TEST("SACH 70H", 0x6870); + if (is32020()) { + TEST("SACH 70H, 1", 0x6970); + TEST("SACH 70H, 4", 0x6C70); + } else { + TEST("SACH 70H, 1", 0x6970); + TEST("SACH 70H, 2", 0x6A70); + TEST("SACH 70H, 3", 0x6B70); + TEST("SACH 70H, 4", 0x6C70); + TEST("SACH 70H, 5", 0x6D70); + TEST("SACH 70H, 6", 0x6E70); + TEST("SACH 70H, 7", 0x6F70); + } + TEST("SACH *", 0x6880); + + TEST("SACH *, 0, AR0", 0x6888); + TEST("SACH *, 0, AR7", 0x688F); + TEST("SACH *-", 0x6890); + TEST("SACH *+", 0x68A0); + TEST("SACH *BR0-", 0x68C0); + TEST("SACH *0-", 0x68D0); + TEST("SACH *0+", 0x68E0); + TEST("SACH *BR0+", 0x68F0); + TEST("SACH *, 1", 0x6980); + TEST("SACH *-, 1", 0x6990); + TEST("SACH *+, 4", 0x6CA0); + TEST("SACH *, 0, AR0", 0x6888); + TEST("SACH *, 4, AR1", 0x6C89); + TEST("SACH *-, 4, AR0", 0x6C98); + TEST("SACH *-, 0, AR1", 0x6899); + TEST("SACH *+, 4, AR0", 0x6CA8); + if (is32020()) { + TEST("SACH *BR0+, 4, AR7", 0x6CFF); + } else { + TEST("SACH *BR0+, 7, AR7", 0x6FFF); + } + + TEST("SACL 70H", 0x6070); + if (is32020()) { + TEST("SACL 70H, 1", 0x6170); + TEST("SACL 70H, 4", 0x6470); + } else { + TEST("SACL 70H, 1", 0x6170); + TEST("SACL 70H, 2", 0x6270); + TEST("SACL 70H, 3", 0x6370); + TEST("SACL 70H, 4", 0x6470); + TEST("SACL 70H, 5", 0x6570); + TEST("SACL 70H, 6", 0x6670); + TEST("SACL 70H, 7", 0x6770); + } + TEST("SACL *", 0x6080); + TEST("SACL *, 0, AR0", 0x6088); + TEST("SACL *, 0, AR7", 0x608F); + TEST("SACL *-", 0x6090); + TEST("SACL *+", 0x60A0); + TEST("SACL *BR0-", 0x60C0); + TEST("SACL *0-", 0x60D0); + TEST("SACL *0+", 0x60E0); + TEST("SACL *BR0+", 0x60F0); + TEST("SACL *, 1", 0x6180); + TEST("SACL *-, 1", 0x6190); + TEST("SACL *+, 4", 0x64A0); + TEST("SACL *, 0, AR0", 0x6088); + TEST("SACL *, 4, AR1", 0x6489); + TEST("SACL *-, 4, AR0", 0x6498); + TEST("SACL *-, 0, AR1", 0x6099); + TEST("SACL *+, 4, AR0", 0x64A8); + if (is32020()) { + TEST("SACL *BR0+, 4, AR7", 0x64FF); + } else { + TEST("SACL *BR0+, 7, AR7", 0x67FF); + } + + TEST("SUB 70H", 0x1070); + TEST("SUB 70H, 15", 0x1F70); + TEST("SUB *", 0x1080); + TEST("SUB *, 0, AR0", 0x1088); + TEST("SUB *, 0, AR7", 0x108F); + TEST("SUB *-", 0x1090); + TEST("SUB *+", 0x10A0); + TEST("SUB *BR0-", 0x10C0); + TEST("SUB *0-", 0x10D0); + TEST("SUB *0+", 0x10E0); + TEST("SUB *BR0+", 0x10F0); + TEST("SUB *, 1", 0x1180); + TEST("SUB *-, 2", 0x1290); + TEST("SUB *+, 3", 0x13A0); + TEST("SUB *, 0, AR0", 0x1088); + TEST("SUB *, 4, AR1", 0x1489); + TEST("SUB *-, 4, AR0", 0x1498); + TEST("SUB *-, 0, AR1", 0x1099); + TEST("SUB *+, 15, AR0", 0x1FA8); + TEST("SUB *BR0+, 15, AR7", 0x1FFF); + + TEST("SUBC 70H", 0x4770); + TEST("SUBC *", 0x4780); + TEST("SUBC *-", 0x4790); + TEST("SUBC *+", 0x47A0); + TEST("SUBC *, AR0", 0x4788); + TEST("SUBC *-, AR1", 0x4799); + TEST("SUBC *+, AR0", 0x47A8); + + TEST("SUBH 70H", 0x4470); + TEST("SUBH *", 0x4480); + TEST("SUBH *-", 0x4490); + TEST("SUBH *+", 0x44A0); + TEST("SUBH *, AR0", 0x4488); + TEST("SUBH *-, AR1", 0x4499); + TEST("SUBH *+, AR0", 0x44A8); + + TEST("SUBS 70H", 0x4570); + TEST("SUBS *", 0x4580); + TEST("SUBS *-", 0x4590); + TEST("SUBS *+", 0x45A0); + TEST("SUBS *, AR0", 0x4588); + TEST("SUBS *-, AR1", 0x4599); + TEST("SUBS *+, AR0", 0x45A8); + + TEST("SUBT 70H", 0x4670); + TEST("SUBT *", 0x4680); + TEST("SUBT *-", 0x4690); + TEST("SUBT *+", 0x46A0); + TEST("SUBT *, AR0", 0x4688); + TEST("SUBT *-, AR1", 0x4699); + TEST("SUBT *+, AR0", 0x46A8); + + TEST("SBLK 0", 0xD003, 0x0000); + TEST("SBLK 0FFFFH", 0xD003, 0xFFFF); + TEST("SBLK 18, 4", 0xD403, 0x0012); + TEST("SBLK 00FFH, 10", 0xDA03, 0x00FF); + TEST("SBLK 0FFFFH, 15", 0xDF03, 0xFFFF); + + if (is320C2x()) { + TEST("SUBB 70H", 0x4F70); + TEST("SUBB *", 0x4F80); + TEST("SUBB *-", 0x4F90); + TEST("SUBB *+", 0x4FA0); + TEST("SUBB *, AR0", 0x4F88); + TEST("SUBB *-, AR1", 0x4F99); + TEST("SUBB *+, AR0", 0x4FA8); + + TEST("SUBK 0", 0xCD00); + TEST("SUBK 255", 0xCDFF); + } + + TEST("XOR 70H", 0x4C70); + TEST("XOR *", 0x4C80); + TEST("XOR *-", 0x4C90); + TEST("XOR *+", 0x4CA0); + TEST("XOR *, AR0", 0x4C88); + TEST("XOR *-, AR1", 0x4C99); + TEST("XOR *+, AR0", 0x4CA8); + + TEST("XORK 0", 0xD006, 0x0000); + TEST("XORK 0FFFFH", 0xD006, 0xFFFF); + TEST("XORK 18, 4", 0xD406, 0x0012); + TEST("XORK 00FFH, 10", 0xDA06, 0x00FF); + TEST("XORK 0FFFFH, 15", 0xDF06, 0xFFFF); + + TEST("ZALH 70H", 0x4070); + TEST("ZALH *", 0x4080); + TEST("ZALH *-", 0x4090); + TEST("ZALH *+", 0x40A0); + TEST("ZALH *, AR0", 0x4088); + TEST("ZALH *-, AR1", 0x4099); + TEST("ZALH *+, AR0", 0x40A8); + + TEST("ZALS 70H", 0x4170); + TEST("ZALS *", 0x4180); + TEST("ZALS *-", 0x4190); + TEST("ZALS *+", 0x41A0); + TEST("ZALS *, AR0", 0x4188); + TEST("ZALS *-, AR1", 0x4199); + TEST("ZALS *+, AR0", 0x41A8); + + if (is320C2x()) { + TEST("ZALR 70H", 0x7B70); + TEST("ZALR *", 0x7B80); + TEST("ZALR *-", 0x7B90); + TEST("ZALR *+", 0x7BA0); + TEST("ZALR *, AR0", 0x7B88); + TEST("ZALR *-, AR1", 0x7B99); + TEST("ZALR *+, AR0", 0x7BA8); + } +} + +void test_auxiliary_1x() { TEST("LAR AR0, 70H", 0x3870); TEST("LAR 0, 70H", 0x3870); ERRT("LAR 2, 70H", UNKNOWN_REGISTER, "2, 70H", 0x3870); @@ -320,7 +700,75 @@ void test_auxiliary() { TEST("SAR AR1, *+, AR0", 0x31A0); } -void test_multiply() { +void test_auxiliary_2x() { + TEST("LAR AR0, 70H", 0x3070); + TEST("LAR AR1, *", 0x3180); + TEST("LAR AR2, *-", 0x3290); + TEST("LAR AR3, *+", 0x33A0); + TEST("LAR AR4, *, AR0", 0x3488); + TEST("LAR AR5, *-, AR1", 0x3599); + TEST("LAR AR6, *+, AR0", 0x36A8); + TEST("LAR AR7, 70H", 0x3770); + TEST("LAR AR0, *", 0x3080); + TEST("LAR AR1, *-", 0x3190); + TEST("LAR AR2, *+", 0x32A0); + TEST("LAR AR3, *, AR0", 0x3388); + TEST("LAR AR4, *-, AR1", 0x3499); + TEST("LAR AR5, *+, AR0", 0x35A8); + + TEST("LARK AR0, 255", 0xC0FF); + TEST("LARK AR7, 128", 0xC780); + + TEST("LARP AR0", 0x5588); + TEST("LARP AR7", 0x558F); + + TEST("LDP 70H", 0x5270); + TEST("LDP *", 0x5280); + TEST("LDP *-", 0x5290); + TEST("LDP *+", 0x52A0); + TEST("LDP *, AR0", 0x5288); + TEST("LDP *-, AR1", 0x5299); + TEST("LDP *+, AR0", 0x52A8); + + TEST("LDPK 000H", 0xC800); + TEST("LDPK 1FFH", 0xC9FF); + + TEST("LRLK AR0, 0000H", 0xD000, 0x0000); + TEST("LRLK AR7, 0FFFFH", 0xD700, 0xFFFF); + + if (is320C2x()) { + TEST("ADRK 0", 0x7E00); + TEST("ADRK 255", 0x7EFF); + + TEST("SBRK 0", 0x7F00); + TEST("SBRK 255", 0x7FFF); + } + + TEST("MAR 70H", 0x5570); + TEST("MAR *", 0x5580); + TEST("MAR *-", 0x5590); + TEST("MAR *+", 0x55A0); + TEST("LARP AR0", 0x5588); + TEST("MAR *-, AR1", 0x5599); + TEST("MAR *+, AR0", 0x55A8); + + TEST("SAR AR0, 70H", 0x7070); + TEST("SAR AR0, *", 0x7080); + TEST("SAR AR0, *-", 0x7090); + TEST("SAR AR0, *+", 0x70A0); + TEST("SAR AR0, *, AR0", 0x7088); + TEST("SAR AR0, *-, AR1", 0x7099); + TEST("SAR AR0, *+, AR0", 0x70A8); + TEST("SAR AR1, 70H", 0x7170); + TEST("SAR AR1, *", 0x7180); + TEST("SAR AR1, *-", 0x7190); + TEST("SAR AR1, *+", 0x71A0); + TEST("SAR AR1, *, AR0", 0x7188); + TEST("SAR AR1, *-, AR1", 0x7199); + TEST("SAR AR1, *+, AR0", 0x71A8); +} + +void test_multiply_1x() { TEST("APAC", 0x7F8F); TEST("LT 70H", 0x6A70); @@ -368,7 +816,158 @@ void test_multiply() { TEST("SPAC", 0x7F90); } -void test_branch() { +void test_multiply_2x() { + TEST("APAC", 0xCE15); + + TEST("LPH 70H", 0x5370); + TEST("LPH *", 0x5380); + TEST("LPH *-", 0x5390); + TEST("LPH *+", 0x53A0); + TEST("LPH *, AR0", 0x5388); + TEST("LPH *-, AR1", 0x5399); + TEST("LPH *+, AR0", 0x53A8); + + TEST("LT 70H", 0x3C70); + TEST("LT *", 0x3C80); + TEST("LT *-", 0x3C90); + TEST("LT *+", 0x3CA0); + TEST("LT *, AR0", 0x3C88); + TEST("LT *-, AR1", 0x3C99); + TEST("LT *+, AR0", 0x3CA8); + + TEST("LTA 70H", 0x3D70); + TEST("LTA *", 0x3D80); + TEST("LTA *-", 0x3D90); + TEST("LTA *+", 0x3DA0); + TEST("LTA *, AR0", 0x3D88); + TEST("LTA *-, AR1", 0x3D99); + TEST("LTA *+, AR0", 0x3DA8); + + TEST("LTD 70H", 0x3F70); + TEST("LTD *", 0x3F80); + TEST("LTD *-", 0x3F90); + TEST("LTD *+", 0x3FA0); + TEST("LTD *, AR0", 0x3F88); + TEST("LTD *-, AR1", 0x3F99); + TEST("LTD *+, AR0", 0x3FA8); + + TEST("LTP 70H", 0x3E70); + TEST("LTP *", 0x3E80); + TEST("LTP *-", 0x3E90); + TEST("LTP *+", 0x3EA0); + TEST("LTP *, AR0", 0x3E88); + TEST("LTP *-, AR1", 0x3E99); + TEST("LTP *+, AR0", 0x3EA8); + + TEST("LTS 70H", 0x5B70); + TEST("LTS *", 0x5B80); + TEST("LTS *-", 0x5B90); + TEST("LTS *+", 0x5BA0); + TEST("LTS *, AR0", 0x5B88); + TEST("LTS *-, AR1", 0x5B99); + TEST("LTS *+, AR0", 0x5BA8); + + TEST("MAC 1000H, 70H", 0x5D70, 0x1000); + TEST("MAC 2000H, *", 0x5D80, 0x2000); + TEST("MAC 4000H, *-", 0x5D90, 0x4000); + TEST("MAC 8000H, *+", 0x5DA0, 0x8000); + TEST("MAC 1234H, *, AR0", 0x5D88, 0x1234); + TEST("MAC 5678H, *-, AR1", 0x5D99, 0x5678); + TEST("MAC 9ABCH, *+, AR0", 0x5DA8, 0x9ABC); + + TEST("MACD 1000H, 70H", 0x5C70, 0x1000); + TEST("MACD 2000H, *", 0x5C80, 0x2000); + TEST("MACD 4000H, *-", 0x5C90, 0x4000); + TEST("MACD 8000H, *+", 0x5CA0, 0x8000); + TEST("MACD 1234H, *, AR0", 0x5C88, 0x1234); + TEST("MACD 5678H, *-, AR1", 0x5C99, 0x5678); + TEST("MACD 9ABCH, *+, AR0", 0x5CA8, 0x9ABC); + + TEST("MPY 70H", 0x3870); + TEST("MPY *", 0x3880); + TEST("MPY *-", 0x3890); + TEST("MPY *+", 0x38A0); + TEST("MPY *, AR0", 0x3888); + TEST("MPY *-, AR1", 0x3899); + TEST("MPY *+, AR0", 0x38A8); + + TEST("MPYK 0", 0xA000); + TEST("MPYK 2", 0xA002); + TEST("MPYK 4095", 0xAFFF); + TEST("MPYK -1", 0xBFFF); + TEST("MPYK -2", 0xBFFE); + TEST("MPYK -4096", 0xB000); + + if (is320C2x()) { + TEST("MPYA 70H", 0x3A70); + TEST("MPYA *", 0x3A80); + TEST("MPYA *-", 0x3A90); + TEST("MPYA *+", 0x3AA0); + TEST("MPYA *, AR0", 0x3A88); + TEST("MPYA *-, AR1", 0x3A99); + TEST("MPYA *+, AR0", 0x3AA8); + + TEST("MPYS 70H", 0x3B70); + TEST("MPYS *", 0x3B80); + TEST("MPYS *-", 0x3B90); + TEST("MPYS *+", 0x3BA0); + TEST("MPYS *, AR0", 0x3B88); + TEST("MPYS *-, AR1", 0x3B99); + TEST("MPYS *+, AR0", 0x3BA8); + + TEST("MPYU 70H", 0xCF70); + TEST("MPYU *", 0xCF80); + TEST("MPYU *-", 0xCF90); + TEST("MPYU *+", 0xCFA0); + TEST("MPYU *, AR0", 0xCF88); + TEST("MPYU *-, AR1", 0xCF99); + TEST("MPYU *+, AR0", 0xCFA8); + } + + TEST("PAC ", 0xCE14); + TEST("SPAC", 0xCE16); + + if (is320C2x()) { + TEST("SPH 70H", 0x7D70); + TEST("SPH *", 0x7D80); + TEST("SPH *-", 0x7D90); + TEST("SPH *+", 0x7DA0); + TEST("SPH *, AR0", 0x7D88); + TEST("SPH *-, AR1", 0x7D99); + TEST("SPH *+, AR0", 0x7DA8); + + TEST("SPL 70H", 0x7C70); + TEST("SPL *", 0x7C80); + TEST("SPL *-", 0x7C90); + TEST("SPL *+", 0x7CA0); + TEST("SPL *, AR0", 0x7C88); + TEST("SPL *-, AR1", 0x7C99); + TEST("SPL *+, AR0", 0x7CA8); + } + + TEST("SPM 0", 0xCE08); + TEST("SPM 1", 0xCE09); + TEST("SPM 2", 0xCE0A); + TEST("SPM 3", 0xCE0B); + + TEST("SQRA 70H", 0x3970); + TEST("SQRA *", 0x3980); + TEST("SQRA *-", 0x3990); + TEST("SQRA *+", 0x39A0); + TEST("SQRA *, AR0", 0x3988); + TEST("SQRA *-, AR1", 0x3999); + TEST("SQRA *+, AR0", 0x39A8); + + TEST("SQRS 70H", 0x5A70); + TEST("SQRS *", 0x5A80); + TEST("SQRS *-", 0x5A90); + TEST("SQRS *+", 0x5AA0); + TEST("SQRS *, AR0", 0x5A88); + TEST("SQRS *-, AR1", 0x5A99); + TEST("SQRS *+, AR0", 0x5AA8); +} + +void test_branch_1x() { TEST("B 000H", 0xF900, 0x0000); TEST("B 001H", 0xF900, 0x0001); TEST("B 002H", 0xF900, 0x0002); @@ -406,7 +1005,58 @@ void test_branch() { TEST("RET", 0x7F8D); } -void test_control() { +void test_branch_2x() { + TEST("B 1000H", 0xFF80, 0x1000); + TEST("B 2000H", 0xFF80, 0x2000); + TEST("B 4000H", 0xFF80, 0x4000); + TEST("B 8000H", 0xFF80, 0x8000); + TEST("B 0FFFFH", 0xFF80, 0xFFFF); + TEST("B 8000H, *-", 0xFF90, 0x8000); + TEST("B 8000H, *+", 0xFFA0, 0x8000); + TEST("B 8000H, *BR0-", 0xFFC0, 0x8000); + TEST("B 8000H, *0-", 0xFFD0, 0x8000); + TEST("B 8000H, *0+", 0xFFE0, 0x8000); + TEST("B 8000H, *BR0+", 0xFFF0, 0x8000); + + TEST("BANZ 9000H", 0xFB80, 0x9000); + TEST("BANZ 9000H, *+", 0xFBA0, 0x9000); + TEST("BBNZ 9000H", 0xF980, 0x9000); + TEST("BBNZ 9000H, *+", 0xF9A0, 0x9000); + TEST("BBZ 9000H", 0xF880, 0x9000); + TEST("BBZ 9000H, *+", 0xF8A0, 0x9000); + TEST("BGEZ 9000H", 0xF480, 0x9000); + TEST("BGEZ 9000H, *+", 0xF4A0, 0x9000); + TEST("BGZ 9000H", 0xF180, 0x9000); + TEST("BGZ 9000H, *+", 0xF1A0, 0x9000); + TEST("BIOZ 9000H", 0xFA80, 0x9000); + TEST("BIOZ 9000H, *+", 0xFAA0, 0x9000); + TEST("BLEZ 9000H", 0xF280, 0x9000); + TEST("BLEZ 9000H, *+", 0xF2A0, 0x9000); + TEST("BLZ 9000H", 0xF380, 0x9000); + TEST("BLZ 9000H, *+", 0xF3A0, 0x9000); + TEST("BNV 9000H", 0xF780, 0x9000); + TEST("BNV 9000H, *+", 0xF7A0, 0x9000); + TEST("BNZ 9000H", 0xF580, 0x9000); + TEST("BNZ 9000H, *+", 0xF5A0, 0x9000); + TEST("BV 9000H", 0xF080, 0x9000); + TEST("BV 9000H, *+", 0xF0A0, 0x9000); + TEST("BZ 9000H", 0xF680, 0x9000); + TEST("BZ 9000H, *+", 0xF6A0, 0x9000); + TEST("CALL 9000H", 0xFE80, 0x9000); + TEST("CALL 9000H, *+", 0xFEA0, 0x9000); + if (is320C2x()) { + TEST("BC 9000H", 0x5E80, 0x9000); + TEST("BC 9000H, *+", 0x5EA0, 0x9000); + TEST("BNC 9000H", 0x5F80, 0x9000); + TEST("BNC 9000H, *+", 0x5fA0, 0x9000); + } + + TEST("BACC", 0xCE25); + TEST("CALA", 0xCE24); + TEST("RET ", 0xCE26); +} + +void test_control_1x() { TEST("DINT", 0x7F81); TEST("EINT", 0x7F82); TEST("NOP", 0x7F80); @@ -442,7 +1092,86 @@ void test_control() { TEST("SST *+, AR0", 0x7CA0); } -void test_dataio() { +void test_control_2x() { + TEST("BIT 70H, 0", 0x9070); + if (is320C26()) { + TEST("CONF 0", 0xCE3C); + TEST("CONF 1", 0xCE3D); + TEST("CONF 2", 0xCE3E); + TEST("CONF 3", 0xCE3F); + } else { + TEST("CNFD", 0xCE04); + TEST("CNFP", 0xCE05); + } + + TEST("DINT", 0xCE01); + TEST("EINT", 0xCE00); + TEST("NOP ", 0x5500); + TEST("POP ", 0xCE1D); + TEST("PUSH", 0xCE1C); + TEST("POPD *", 0x7A80); + TEST("PSHD *+", 0x54A0); + TEST("ROVM", 0xCE02); + TEST("SOVM", 0xCE03); + TEST("RSXM", 0xCE06); + TEST("SSXM", 0xCE07); + if (is320C2x()) { + TEST("RC ", 0xCE30); + TEST("SC ", 0xCE31); + TEST("RHM ", 0xCE38); + TEST("SHM ", 0xCE39); + TEST("RTC ", 0xCE32); + TEST("STC ", 0xCE33); + } + + TEST("RPT 00H", 0x4B00); + TEST("RPT 70H", 0x4B70); + TEST("RPT *", 0x4B80); + TEST("RPT *-", 0x4B90); + TEST("RPT *+", 0x4BA0); + TEST("RPT *, AR0", 0x4B88); + TEST("RPT *-, AR7", 0x4B9F); + TEST("RPT *+, AR4", 0x4BAC); + TEST("RPTK 100", 0xCB64); + + TEST("LST 00H", 0x5000); + TEST("LST 70H", 0x5070); + TEST("LST *", 0x5080); + TEST("LST *-", 0x5090); + TEST("LST *+", 0x50A0); + TEST("LST *, AR0", 0x5088); + TEST("LST *-, AR7", 0x509F); + TEST("LST *+, AR4", 0x50AC); + TEST("LST1 00H", 0x5100); + TEST("LST1 70H", 0x5170); + TEST("LST1 *", 0x5180); + TEST("LST1 *-", 0x5190); + TEST("LST1 *+", 0x51A0); + TEST("LST1 *, AR0", 0x5188); + TEST("LST1 *-, AR7", 0x519F); + TEST("LST1 *+, AR4", 0x51AC); + + TEST("SST 10H", 0x7810); + TEST("SST 1FH", 0x781F); + TEST("SST 7FH", 0x787F); + TEST("SST *", 0x7880); + TEST("SST *-", 0x7890); + TEST("SST *+", 0x78A0); + TEST("SST *, AR0", 0x7888); + TEST("SST *-, AR7", 0x789F); + TEST("SST *+, AR0", 0x78A8); + TEST("SST1 10H", 0x7910); + TEST("SST1 1FH", 0x791F); + TEST("SST1 7FH", 0x797F); + TEST("SST1 *", 0x7980); + TEST("SST1 *-", 0x7990); + TEST("SST1 *+", 0x79A0); + TEST("SST1 *, AR0", 0x7988); + TEST("SST1 *-, AR7", 0x799F); + TEST("SST1 *+, AR0", 0x79A8); +} + +void test_dataio_1x() { TEST("DMOV 00H", 0x6900); TEST("DMOV 70H", 0x6970); TEST("DMOV *", 0x6988); @@ -515,7 +1244,101 @@ void test_dataio() { ERRT("OUT *+, PA7, UNDEF", UNDEFINED_SYMBOL, "UNDEF", 0x4FA0); } -void test_comment() { +void test_dataio_2x() { + TEST("BLKD 1234H, 00H", 0xFD00, 0x1234); + TEST("BLKD 1234H, 70H", 0xFD70, 0x1234); + TEST("BLKD 1234H, *", 0xFD80, 0x1234); + TEST("BLKD 1234H, *-", 0xFD90, 0x1234); + TEST("BLKD 1234H, *+", 0xFDA0, 0x1234); + TEST("BLKD 1234H, *, AR0", 0xFD88, 0x1234); + TEST("BLKD 1234H, *-, AR1", 0xFD99, 0x1234); + TEST("BLKD 1234H, *+, AR0", 0xFDA8, 0x1234); + + TEST("BLKP 1234H, 00H", 0xFC00, 0x1234); + TEST("BLKP 1234H, 70H", 0xFC70, 0x1234); + TEST("BLKP 1234H, *", 0xFC80, 0x1234); + TEST("BLKP 1234H, *-", 0xFC90, 0x1234); + TEST("BLKP 1234H, *+", 0xFCA0, 0x1234); + TEST("BLKP 1234H, *, AR0", 0xFC88, 0x1234); + TEST("BLKP 1234H, *-, AR1", 0xFC99, 0x1234); + TEST("BLKP 1234H, *+, AR0", 0xFCA8, 0x1234); + + TEST("DMOV 00H", 0x5600); + TEST("DMOV 70H", 0x5670); + TEST("DMOV *", 0x5680); + TEST("DMOV *-", 0x5690); + TEST("DMOV *+", 0x56A0); + TEST("DMOV *, AR0", 0x5688); + TEST("DMOV *-, AR1", 0x5699); + TEST("DMOV *+, AR0", 0x56A8); + + TEST("FORT 0", 0xCE0E); + TEST("FORT 1", 0xCE0F); + + if (is320C2x()) { + TEST("RFSM", 0xCE36); + TEST("SFSM", 0xCE37); + } + TEST("RTXM", 0xCE20); + TEST("STXM", 0xCE21); + TEST("RXF ", 0xCE0C); + TEST("SXF ", 0xCE0D); + + TEST("TBLR 00H", 0x5800); + TEST("TBLR 70H", 0x5870); + TEST("TBLR *", 0x5880); + TEST("TBLR *-", 0x5890); + TEST("TBLR *+", 0x58A0); + TEST("TBLR *, AR0", 0x5888); + TEST("TBLR *-, AR1", 0x5899); + TEST("TBLR *+, AR0", 0x58A8); + + TEST("TBLW 00H", 0x5900); + TEST("TBLW 70H", 0x5970); + TEST("TBLW *", 0x5980); + TEST("TBLW *-", 0x5990); + TEST("TBLW *+", 0x59A0); + TEST("TBLW *, AR0", 0x5988); + TEST("TBLW *-, AR1", 0x5999); + TEST("TBLW *+, AR0", 0x59A8); + + TEST("IN 70H, PA0", 0x8070); + TEST("IN 70H, PA15", 0x8F70); + TEST("IN *, PA0, AR0", 0x8088); + TEST("IN *, PA15, AR7", 0x8F8F); + TEST("IN *, PA0", 0x8080); + TEST("IN *-, PA1", 0x8190); + TEST("IN *+, PA2", 0x82A0); + TEST("IN *BR0-, PA0, AR7", 0x80CF); + TEST("IN *, PA1", 0x8180); + TEST("IN *-, PA2", 0x8290); + TEST("IN *+, PA3", 0x83A0); + TEST("IN *, PA0, AR0", 0x8088); + TEST("IN *, PA4, AR1", 0x8489); + TEST("IN *-, PA4, AR0", 0x8498); + TEST("IN *-, PA0, AR1", 0x8099); + TEST("IN *+, PA7, AR0", 0x87A8); + TEST("IN *+, PA7, AR1", 0x87A9); + + TEST("OUT 70H, PA8", 0xE870); + TEST("OUT 70H, PA15", 0xEF70); + TEST("OUT *, PA8, AR0", 0xE888); + TEST("OUT *, PA15, AR1", 0xEF89); + TEST("OUT *, PA8", 0xE880); + TEST("OUT *-, PA9", 0xE990); + TEST("OUT *+, PA10", 0xEAA0); + TEST("OUT *, PA9", 0xE980); + TEST("OUT *-, PA10", 0xEA90); + TEST("OUT *+, PA11", 0xEBA0); + TEST("OUT *, PA8, AR0", 0xE888); + TEST("OUT *, PA12, AR1", 0xEC89); + TEST("OUT *-, PA12, AR0", 0xEC98); + TEST("OUT *-, PA8, AR1", 0xE899); + TEST("OUT *+, PA15, AR0", 0xEFA8); + TEST("OUT *+, PA15, AR1", 0xEFA9); +} + +void test_comment_1x() { COMM("ADDH 70H ; comment", "; comment", 0x6070); COMM("ADDH * ; comment", "; comment", 0x6088); COMM("ADDH *- ; comment", "; comment", 0x6098); @@ -531,7 +1354,7 @@ void test_comment() { COMM(R"(.string "TEXT" ; comment)", "; comment", 0x4554, 0x5458); } -void test_undef() { +void test_undef_1x() { ERRT("ADDH *+, UNDEF", UNDEFINED_SYMBOL, "UNDEF", 0x60A0); ERRT("LAC UNDEF", UNDEFINED_SYMBOL, "UNDEF", 0x2000); ERRT("LAC UNDEF, 15", UNDEFINED_SYMBOL, "UNDEF, 15", 0x2F00); @@ -540,6 +1363,15 @@ void test_undef() { ERRT("LAC *, UNDEF, AR1", UNDEFINED_SYMBOL, "UNDEF, AR1", 0x2081); } +void test_undef_2x() { + ERRT("ADDH *+, UNDEF", UNDEFINED_SYMBOL, "UNDEF", 0x48A8); + ERRT("LAC UNDEF", UNDEFINED_SYMBOL, "UNDEF", 0x2000); + ERRT("LAC UNDEF, 15", UNDEFINED_SYMBOL, "UNDEF, 15", 0x2F00); + ERRT("LAC 70H, UNDEF", UNDEFINED_SYMBOL, "UNDEF", 0x2070); + ERRT("LAC UNDEF, UNDEF", UNDEFINED_SYMBOL, "UNDEF, UNDEF", 0x2000); + ERRT("LAC *, UNDEF, AR7", UNDEFINED_SYMBOL, "UNDEF, AR7", 0x208F); +} + void test_data_constant() { TEST(".byte -128, 255", 0x0080, 0x00FF); TEST(".byte 1234H", 0x0034); @@ -588,14 +1420,25 @@ void test_data_constant() { void run_tests(const char *cpu) { assembler.setCpu(cpu); - RUN_TEST(test_accumrator); - RUN_TEST(test_auxiliary); - RUN_TEST(test_multiply); - RUN_TEST(test_branch); - RUN_TEST(test_control); - RUN_TEST(test_dataio); - RUN_TEST(test_comment); - RUN_TEST(test_undef); + if (is3201x()) { + RUN_TEST(test_accumrator_1x); + RUN_TEST(test_auxiliary_1x); + RUN_TEST(test_multiply_1x); + RUN_TEST(test_branch_1x); + RUN_TEST(test_control_1x); + RUN_TEST(test_dataio_1x); + RUN_TEST(test_comment_1x); + RUN_TEST(test_undef_1x); + } + if (is3202x()) { + RUN_TEST(test_auxiliary_2x); + RUN_TEST(test_multiply_2x); + RUN_TEST(test_branch_2x); + RUN_TEST(test_control_2x); + RUN_TEST(test_dataio_2x); + RUN_TEST(test_accumrator_2x); + RUN_TEST(test_undef_2x); + } RUN_TEST(test_data_constant); } diff --git a/test/test_dis_tms32010.cpp b/test/test_dis_tms32010.cpp index 5d04b8689..98ce818d9 100644 --- a/test/test_dis_tms32010.cpp +++ b/test/test_dis_tms32010.cpp @@ -33,6 +33,30 @@ bool is32015() { return strcmp_P("32015", disassembler.config().cpu_P()) == 0; } +bool is3201x() { + return is32010() || is32015(); +} + +bool is32020() { + return strcmp_P("32020", disassembler.config().cpu_P()) == 0; +} + +bool is320C25() { + return strcmp_P("320C25", disassembler.config().cpu_P()) == 0; +} + +bool is320C26() { + return strcmp_P("320C26", disassembler.config().cpu_P()) == 0; +} + +bool is3202x() { + return is32020() || is320C25() || is320C26(); +} + +bool is320C2x() { + return is320C25() || is320C26(); +} + void set_up() { disassembler.reset(); } @@ -48,15 +72,33 @@ void test_cpu() { EQUALS("cpu 32015", true, disassembler.setCpu("32015")); EQUALS_P("cpu 32015", "32015", disassembler.config().cpu_P()); + EQUALS("cpu 32020", true, disassembler.setCpu("32020")); + EQUALS_P("cpu 32020", "32020", disassembler.config().cpu_P()); + + EQUALS("cpu 320C25", true, disassembler.setCpu("320C25")); + EQUALS_P("cpu 320C25", "320C25", disassembler.config().cpu_P()); + + EQUALS("cpu 320C26", true, disassembler.setCpu("320C26")); + EQUALS_P("cpu 320C26", "320C26", disassembler.config().cpu_P()); + EQUALS("cpu TMS32010", true, disassembler.setCpu("TMS32010")); EQUALS_P("cpu TMS32010", "32010", disassembler.config().cpu_P()); EQUALS("cpu TMS32015", true, disassembler.setCpu("TMS32015")); EQUALS_P("cpu TMS32015", "32015", disassembler.config().cpu_P()); + + EQUALS("cpu TMS32020", true, disassembler.setCpu("TMS32020")); + EQUALS_P("cpu TMS32020", "32020", disassembler.config().cpu_P()); + + EQUALS("cpu TMS320C25", true, disassembler.setCpu("TMS320C25")); + EQUALS_P("cpu TMS320C25", "320C25", disassembler.config().cpu_P()); + + EQUALS("cpu TMS320C26", true, disassembler.setCpu("TMS320C26")); + EQUALS_P("cpu TMS320C26", "320C26", disassembler.config().cpu_P()); } // clang-format off -void test_accumrator() { +void test_accumrator_1x() { TEST("ABS", "", 0x7F88); TEST("ADD", "70H", 0x0070); @@ -273,7 +315,401 @@ void test_accumrator() { TEST("ZALS", "*+, AR0", 0x66A0); } -void test_auxiliary() { +void test_accumrator_2x() { + TEST("ABS", "", 0xCE1B); + + TEST("ADD", "70H", 0x0070); + TEST("ADD", "70H, 15", 0x0F70); + TEST("ADD", "*", 0x0080); + UNKN( 0x0081); + UNKN( 0x0082); + UNKN( 0x0083); + UNKN( 0x0084); + UNKN( 0x0085); + UNKN( 0x0086); + UNKN( 0x0087); + TEST("ADD", "*, 0, AR0", 0x0088); + TEST("ADD", "*, 0, AR7", 0x008F); + TEST("ADD", "*-", 0x0090); + TEST("ADD", "*+", 0x00A0); + UNKN( 0x00B0); + TEST("ADD", "*BR0-", 0x00C0); + TEST("ADD", "*0-", 0x00D0); + TEST("ADD", "*0+", 0x00E0); + TEST("ADD", "*BR0+", 0x00F0); + TEST("ADD", "*, 1", 0x0180); + TEST("ADD", "*-, 2", 0x0290); + TEST("ADD", "*+, 3", 0x03A0); + TEST("ADD", "*, 0, AR0", 0x0088); + TEST("ADD", "*, 4, AR1", 0x0489); + TEST("ADD", "*-, 4, AR0", 0x0498); + TEST("ADD", "*-, 0, AR1", 0x0099); + TEST("ADD", "*+, 15, AR0", 0x0FA8); + TEST("ADD", "*BR0+, 15, AR7", 0x0FFF); + + TEST("ADDH", "70H", 0x4870); + TEST("ADDH", "*", 0x4880); + TEST("ADDH", "*-", 0x4890); + TEST("ADDH", "*+", 0x48A0); + TEST("ADDH", "*, AR0", 0x4888); + TEST("ADDH", "*-, AR1", 0x4899); + TEST("ADDH", "*+, AR0", 0x48A8); + + TEST("ADDS", "70H", 0x4970); + TEST("ADDS", "*", 0x4980); + TEST("ADDS", "*-", 0x4990); + TEST("ADDS", "*+", 0x49A0); + TEST("ADDS", "*, AR0", 0x4988); + TEST("ADDS", "*-, AR1", 0x4999); + TEST("ADDS", "*+, AR0", 0x49A8); + + TEST("ADDT", "70H", 0x4A70); + TEST("ADDT", "*", 0x4A80); + TEST("ADDT", "*-", 0x4A90); + TEST("ADDT", "*+", 0x4AA0); + TEST("ADDT", "*, AR0", 0x4A88); + TEST("ADDT", "*-, AR1", 0x4A99); + TEST("ADDT", "*+, AR0", 0x4AA8); + + TEST("ADLK", "0", 0xD002, 0x0000); + TEST("ADLK", "0FFFFH", 0xD002, 0xFFFF); + TEST("ADLK", "18, 4", 0xD402, 0x0012); + TEST("ADLK", "00FFH, 10", 0xDA02, 0x00FF); + TEST("ADLK", "0FFFFH, 15", 0xDF02, 0xFFFF); + + if (is320C2x()) { + TEST("ADDC", "70H", 0x4370); + TEST("ADDC", "*", 0x4380); + TEST("ADDC", "*-", 0x4390); + TEST("ADDC", "*+", 0x43A0); + TEST("ADDC", "*, AR0", 0x4388); + TEST("ADDC", "*-, AR1", 0x4399); + TEST("ADDC", "*+, AR0", 0x43A8); + + TEST("ADDK", "0", 0xCC00); + TEST("ADDK", "255", 0xCCFF); + } + + TEST("AND", "70H", 0x4E70); + TEST("AND", "*", 0x4E80); + TEST("AND", "*-", 0x4E90); + TEST("AND", "*+", 0x4EA0); + TEST("AND", "*, AR0", 0x4E88); + TEST("AND", "*-, AR1", 0x4E99); + TEST("AND", "*+, AR0", 0x4EA8); + + TEST("ANDK", "0", 0xD004, 0x0000); + TEST("ANDK", "0FFFFH", 0xD004, 0xFFFF); + TEST("ANDK", "18, 4", 0xD404, 0x0012); + TEST("ANDK", "00FFH, 10", 0xDA04, 0x00FF); + TEST("ANDK", "0FFFFH, 15", 0xDF04, 0xFFFF); + + TEST("CMPL", "", 0xCE27); + + TEST("LAC", "70H", 0x2070); + TEST("LAC", "70H, 15", 0x2F70); + TEST("LAC", "*", 0x2080); + UNKN( 0x2081); + UNKN( 0x2082); + UNKN( 0x2083); + UNKN( 0x2084); + UNKN( 0x2085); + UNKN( 0x2086); + UNKN( 0x2087); + TEST("LAC", "*, 0, AR0", 0x2088); + TEST("LAC", "*, 0, AR7", 0x208F); + TEST("LAC", "*-", 0x2090); + TEST("LAC", "*+", 0x20A0); + UNKN( 0x20B0); + TEST("LAC", "*BR0-", 0x20C0); + TEST("LAC", "*0-", 0x20D0); + TEST("LAC", "*0+", 0x20E0); + TEST("LAC", "*BR0+", 0x20F0); + TEST("LAC", "*, 1", 0x2180); + TEST("LAC", "*-, 2", 0x2290); + TEST("LAC", "*+, 3", 0x23A0); + TEST("LAC", "*, 0, AR0", 0x2088); + TEST("LAC", "*, 4, AR1", 0x2489); + TEST("LAC", "*-, 4, AR0", 0x2498); + TEST("LAC", "*-, 0, AR1", 0x2099); + TEST("LAC", "*+, 15, AR0", 0x2FA8); + TEST("LAC", "*BR0+, 15, AR7", 0x2FFF); + + TEST("ZAC", "", 0xCA00); + TEST("LACK", "1", 0xCA01); + TEST("LACK", "255", 0xCAFF); + + TEST("LACT", "70H", 0x4270); + TEST("LACT", "*", 0x4280); + TEST("LACT", "*-", 0x4290); + TEST("LACT", "*+", 0x42A0); + TEST("LACT", "*, AR0", 0x4288); + TEST("LACT", "*-, AR1", 0x4299); + TEST("LACT", "*+, AR0", 0x42A8); + + TEST("LALK", "0", 0xD001, 0x0000); + TEST("LALK", "0FFFFH", 0xD001, 0xFFFF); + TEST("LALK", "18, 4", 0xD401, 0x0012); + TEST("LALK", "00FFH, 10", 0xDA01, 0x00FF); + TEST("LALK", "0FFFFH, 15", 0xDF01, 0xFFFF); + + TEST("NEG", "", 0xCE23); + + if (is32020()) { + TEST("NORM", "", 0xCE82); + UNKN(0xCE92); + UNKN(0xCEA2); + UNKN(0xCEB2); + UNKN(0xCEC2); + UNKN(0xCED2); + UNKN(0xCEE2); + UNKN(0xCEF2); + } + if (is320C2x()) { + TEST("NORM", "*", 0xCE82); + TEST("NORM", "*-", 0xCE92); + TEST("NORM", "*+", 0xCEA2); + UNKN( 0xCEB2); + TEST("NORM", "*BR0-", 0xCEC2); + TEST("NORM", "*0-", 0xCED2); + TEST("NORM", "*0+", 0xCEE2); + TEST("NORM", "*BR0+", 0xCEF2); + } + + TEST("OR", "70H", 0x4D70); + TEST("OR", "*", 0x4D80); + TEST("OR", "*-", 0x4D90); + TEST("OR", "*+", 0x4DA0); + TEST("OR", "*, AR0", 0x4D88); + TEST("OR", "*-, AR1", 0x4D99); + TEST("OR", "*+, AR0", 0x4DA8); + + TEST("ORK", "0", 0xD005, 0x0000); + TEST("ORK", "0FFFFH", 0xD005, 0xFFFF); + TEST("ORK", "18, 4", 0xD405, 0x0012); + TEST("ORK", "00FFH, 10", 0xDA05, 0x00FF); + TEST("ORK", "0FFFFH, 15", 0xDF05, 0xFFFF); + + TEST("SACH", "70H", 0x6870); + if (is32020()) { + TEST("SACH", "70H, 1", 0x6970); + UNKN( 0x6A70); + UNKN( 0x6B70); + TEST("SACH", "70H, 4", 0x6C70); + UNKN( 0x6D70); + UNKN( 0x6E70); + UNKN( 0x6F70); + } else { + TEST("SACH", "70H, 1", 0x6970); + TEST("SACH", "70H, 2", 0x6A70); + TEST("SACH", "70H, 3", 0x6B70); + TEST("SACH", "70H, 4", 0x6C70); + TEST("SACH", "70H, 5", 0x6D70); + TEST("SACH", "70H, 6", 0x6E70); + TEST("SACH", "70H, 7", 0x6F70); + } + TEST("SACH", "*", 0x6880); + UNKN( 0x6881); + UNKN( 0x6882); + UNKN( 0x6883); + UNKN( 0x6884); + UNKN( 0x6885); + UNKN( 0x6886); + UNKN( 0x6887); + TEST("SACH", "*, 0, AR0", 0x6888); + TEST("SACH", "*, 0, AR7", 0x688F); + TEST("SACH", "*-", 0x6890); + TEST("SACH", "*+", 0x68A0); + UNKN( 0x68B0); + TEST("SACH", "*BR0-", 0x68C0); + TEST("SACH", "*0-", 0x68D0); + TEST("SACH", "*0+", 0x68E0); + TEST("SACH", "*BR0+", 0x68F0); + TEST("SACH", "*, 1", 0x6980); + TEST("SACH", "*-, 1", 0x6990); + TEST("SACH", "*+, 4", 0x6CA0); + TEST("SACH", "*, 0, AR0", 0x6888); + TEST("SACH", "*, 4, AR1", 0x6C89); + TEST("SACH", "*-, 4, AR0", 0x6C98); + TEST("SACH", "*-, 0, AR1", 0x6899); + TEST("SACH", "*+, 4, AR0", 0x6CA8); + if (is32020()) { + TEST("SACH", "*BR0+, 4, AR7", 0x6CFF); + } else { + TEST("SACH", "*BR0+, 7, AR7", 0x6FFF); + } + + TEST("SACL", "70H", 0x6070); + if (is32020()) { + TEST("SACL", "70H, 1", 0x6170); + UNKN( 0x6270); + UNKN( 0x6370); + TEST("SACL", "70H, 4", 0x6470); + UNKN( 0x6570); + UNKN( 0x6670); + UNKN( 0x6770); + } else { + TEST("SACL", "70H, 1", 0x6170); + TEST("SACL", "70H, 2", 0x6270); + TEST("SACL", "70H, 3", 0x6370); + TEST("SACL", "70H, 4", 0x6470); + TEST("SACL", "70H, 5", 0x6570); + TEST("SACL", "70H, 6", 0x6670); + TEST("SACL", "70H, 7", 0x6770); + } + TEST("SACL", "*", 0x6080); + UNKN( 0x6081); + UNKN( 0x6082); + UNKN( 0x6083); + UNKN( 0x6084); + UNKN( 0x6085); + UNKN( 0x6086); + UNKN( 0x6087); + TEST("SACL", "*, 0, AR0", 0x6088); + TEST("SACL", "*, 0, AR7", 0x608F); + TEST("SACL", "*-", 0x6090); + TEST("SACL", "*+", 0x60A0); + UNKN( 0x60B0); + TEST("SACL", "*BR0-", 0x60C0); + TEST("SACL", "*0-", 0x60D0); + TEST("SACL", "*0+", 0x60E0); + TEST("SACL", "*BR0+", 0x60F0); + TEST("SACL", "*, 1", 0x6180); + TEST("SACL", "*-, 1", 0x6190); + TEST("SACL", "*+, 4", 0x64A0); + TEST("SACL", "*, 0, AR0", 0x6088); + TEST("SACL", "*, 4, AR1", 0x6489); + TEST("SACL", "*-, 4, AR0", 0x6498); + TEST("SACL", "*-, 0, AR1", 0x6099); + TEST("SACL", "*+, 4, AR0", 0x64A8); + if (is32020()) { + TEST("SACL", "*BR0+, 4, AR7", 0x64FF); + } else { + TEST("SACL", "*BR0+, 7, AR7", 0x67FF); + } + + TEST("SUB", "70H", 0x1070); + TEST("SUB", "70H, 15", 0x1F70); + TEST("SUB", "*", 0x1080); + UNKN( 0x1081); + UNKN( 0x1082); + UNKN( 0x1083); + UNKN( 0x1084); + UNKN( 0x1085); + UNKN( 0x1086); + UNKN( 0x1087); + TEST("SUB", "*, 0, AR0", 0x1088); + TEST("SUB", "*, 0, AR7", 0x108F); + TEST("SUB", "*-", 0x1090); + TEST("SUB", "*+", 0x10A0); + UNKN( 0x10B0); + TEST("SUB", "*BR0-", 0x10C0); + TEST("SUB", "*0-", 0x10D0); + TEST("SUB", "*0+", 0x10E0); + TEST("SUB", "*BR0+", 0x10F0); + TEST("SUB", "*, 1", 0x1180); + TEST("SUB", "*-, 2", 0x1290); + TEST("SUB", "*+, 3", 0x13A0); + TEST("SUB", "*, 0, AR0", 0x1088); + TEST("SUB", "*, 4, AR1", 0x1489); + TEST("SUB", "*-, 4, AR0", 0x1498); + TEST("SUB", "*-, 0, AR1", 0x1099); + TEST("SUB", "*+, 15, AR0", 0x1FA8); + TEST("SUB", "*BR0+, 15, AR7", 0x1FFF); + + TEST("SUBC", "70H", 0x4770); + TEST("SUBC", "*", 0x4780); + TEST("SUBC", "*-", 0x4790); + TEST("SUBC", "*+", 0x47A0); + TEST("SUBC", "*, AR0", 0x4788); + TEST("SUBC", "*-, AR1", 0x4799); + TEST("SUBC", "*+, AR0", 0x47A8); + + TEST("SUBH", "70H", 0x4470); + TEST("SUBH", "*", 0x4480); + TEST("SUBH", "*-", 0x4490); + TEST("SUBH", "*+", 0x44A0); + TEST("SUBH", "*, AR0", 0x4488); + TEST("SUBH", "*-, AR1", 0x4499); + TEST("SUBH", "*+, AR0", 0x44A8); + + TEST("SUBS", "70H", 0x4570); + TEST("SUBS", "*", 0x4580); + TEST("SUBS", "*-", 0x4590); + TEST("SUBS", "*+", 0x45A0); + TEST("SUBS", "*, AR0", 0x4588); + TEST("SUBS", "*-, AR1", 0x4599); + TEST("SUBS", "*+, AR0", 0x45A8); + + TEST("SUBT", "70H", 0x4670); + TEST("SUBT", "*", 0x4680); + TEST("SUBT", "*-", 0x4690); + TEST("SUBT", "*+", 0x46A0); + TEST("SUBT", "*, AR0", 0x4688); + TEST("SUBT", "*-, AR1", 0x4699); + TEST("SUBT", "*+, AR0", 0x46A8); + + TEST("SBLK", "0", 0xD003, 0x0000); + TEST("SBLK", "0FFFFH", 0xD003, 0xFFFF); + TEST("SBLK", "18, 4", 0xD403, 0x0012); + TEST("SBLK", "00FFH, 10", 0xDA03, 0x00FF); + TEST("SBLK", "0FFFFH, 15", 0xDF03, 0xFFFF); + + if (is320C2x()) { + TEST("SUBB", "70H", 0x4F70); + TEST("SUBB", "*", 0x4F80); + TEST("SUBB", "*-", 0x4F90); + TEST("SUBB", "*+", 0x4FA0); + TEST("SUBB", "*, AR0", 0x4F88); + TEST("SUBB", "*-, AR1", 0x4F99); + TEST("SUBB", "*+, AR0", 0x4FA8); + + TEST("SUBK", "0", 0xCD00); + TEST("SUBK", "255", 0xCDFF); + } + + TEST("XOR", "70H", 0x4C70); + TEST("XOR", "*", 0x4C80); + TEST("XOR", "*-", 0x4C90); + TEST("XOR", "*+", 0x4CA0); + TEST("XOR", "*, AR0", 0x4C88); + TEST("XOR", "*-, AR1", 0x4C99); + TEST("XOR", "*+, AR0", 0x4CA8); + + TEST("XORK", "0", 0xD006, 0x0000); + TEST("XORK", "0FFFFH", 0xD006, 0xFFFF); + TEST("XORK", "18, 4", 0xD406, 0x0012); + TEST("XORK", "00FFH, 10", 0xDA06, 0x00FF); + TEST("XORK", "0FFFFH, 15", 0xDF06, 0xFFFF); + + TEST("ZALH", "70H", 0x4070); + TEST("ZALH", "*", 0x4080); + TEST("ZALH", "*-", 0x4090); + TEST("ZALH", "*+", 0x40A0); + TEST("ZALH", "*, AR0", 0x4088); + TEST("ZALH", "*-, AR1", 0x4099); + TEST("ZALH", "*+, AR0", 0x40A8); + + TEST("ZALS", "70H", 0x4170); + TEST("ZALS", "*", 0x4180); + TEST("ZALS", "*-", 0x4190); + TEST("ZALS", "*+", 0x41A0); + TEST("ZALS", "*, AR0", 0x4188); + TEST("ZALS", "*-, AR1", 0x4199); + TEST("ZALS", "*+, AR0", 0x41A8); + + if (is320C2x()) { + TEST("ZALR", "70H", 0x7B70); + TEST("ZALR", "*", 0x7B80); + TEST("ZALR", "*-", 0x7B90); + TEST("ZALR", "*+", 0x7BA0); + TEST("ZALR", "*, AR0", 0x7B88); + TEST("ZALR", "*-, AR1", 0x7B99); + TEST("ZALR", "*+, AR0", 0x7BA8); + } +} + +void test_auxiliary_1x() { TEST("LAR", "AR0, 70H", 0x3870); TEST("LAR", "AR0, *", 0x3888); TEST("LAR", "AR0, *-", 0x3898); @@ -330,7 +766,75 @@ void test_auxiliary() { TEST("SAR", "AR1, *+, AR0", 0x31A0); } -void test_multiply() { +void test_auxiliary_2x() { + TEST("LAR", "AR0, 70H", 0x3070); + TEST("LAR", "AR1, *", 0x3180); + TEST("LAR", "AR2, *-", 0x3290); + TEST("LAR", "AR3, *+", 0x33A0); + TEST("LAR", "AR4, *, AR0", 0x3488); + TEST("LAR", "AR5, *-, AR1", 0x3599); + TEST("LAR", "AR6, *+, AR0", 0x36A8); + TEST("LAR", "AR7, 70H", 0x3770); + TEST("LAR", "AR0, *", 0x3080); + TEST("LAR", "AR1, *-", 0x3190); + TEST("LAR", "AR2, *+", 0x32A0); + TEST("LAR", "AR3, *, AR0", 0x3388); + TEST("LAR", "AR4, *-, AR1", 0x3499); + TEST("LAR", "AR5, *+, AR0", 0x35A8); + + TEST("LARK", "AR0, 255", 0xC0FF); + TEST("LARK", "AR7, 128", 0xC780); + + TEST("LARP", "AR0", 0x5588); + TEST("LARP", "AR7", 0x558F); + + TEST("LDP", "70H", 0x5270); + TEST("LDP", "*", 0x5280); + TEST("LDP", "*-", 0x5290); + TEST("LDP", "*+", 0x52A0); + TEST("LDP", "*, AR0", 0x5288); + TEST("LDP", "*-, AR1", 0x5299); + TEST("LDP", "*+, AR0", 0x52A8); + + TEST("LDPK", "000H", 0xC800); + TEST("LDPK", "1FFH", 0xC9FF); + + TEST("LRLK", "AR0, 0000H", 0xD000, 0x0000); + TEST("LRLK", "AR7, 0FFFFH", 0xD700, 0xFFFF); + + if (is320C2x()) { + TEST("ADRK", "0", 0x7E00); + TEST("ADRK", "255", 0x7EFF); + + TEST("SBRK", "0", 0x7F00); + TEST("SBRK", "255", 0x7FFF); + } + + TEST("MAR", "70H", 0x5570); + TEST("MAR", "*", 0x5580); + TEST("MAR", "*-", 0x5590); + TEST("MAR", "*+", 0x55A0); + TEST("LARP", "AR0", 0x5588); + TEST("MAR", "*-, AR1", 0x5599); + TEST("MAR", "*+, AR0", 0x55A8); + + TEST("SAR", "AR0, 70H", 0x7070); + TEST("SAR", "AR0, *", 0x7080); + TEST("SAR", "AR0, *-", 0x7090); + TEST("SAR", "AR0, *+", 0x70A0); + TEST("SAR", "AR0, *, AR0", 0x7088); + TEST("SAR", "AR0, *-, AR1", 0x7099); + TEST("SAR", "AR0, *+, AR0", 0x70A8); + TEST("SAR", "AR1, 70H", 0x7170); + TEST("SAR", "AR1, *", 0x7180); + TEST("SAR", "AR1, *-", 0x7190); + TEST("SAR", "AR1, *+", 0x71A0); + TEST("SAR", "AR1, *, AR0", 0x7188); + TEST("SAR", "AR1, *-, AR1", 0x7199); + TEST("SAR", "AR1, *+, AR0", 0x71A8); +} + +void test_multiply_1x() { TEST("APAC", "", 0x7F8F); TEST("LT", "70H", 0x6A70); @@ -376,7 +880,158 @@ void test_multiply() { TEST("SPAC", "", 0x7F90); } -void test_branch() { +void test_multiply_2x() { + TEST("APAC", "", 0xCE15); + + TEST("LPH", "70H", 0x5370); + TEST("LPH", "*", 0x5380); + TEST("LPH", "*-", 0x5390); + TEST("LPH", "*+", 0x53A0); + TEST("LPH", "*, AR0", 0x5388); + TEST("LPH", "*-, AR1", 0x5399); + TEST("LPH", "*+, AR0", 0x53A8); + + TEST("LT", "70H", 0x3C70); + TEST("LT", "*", 0x3C80); + TEST("LT", "*-", 0x3C90); + TEST("LT", "*+", 0x3CA0); + TEST("LT", "*, AR0", 0x3C88); + TEST("LT", "*-, AR1", 0x3C99); + TEST("LT", "*+, AR0", 0x3CA8); + + TEST("LTA", "70H", 0x3D70); + TEST("LTA", "*", 0x3D80); + TEST("LTA", "*-", 0x3D90); + TEST("LTA", "*+", 0x3DA0); + TEST("LTA", "*, AR0", 0x3D88); + TEST("LTA", "*-, AR1", 0x3D99); + TEST("LTA", "*+, AR0", 0x3DA8); + + TEST("LTD", "70H", 0x3F70); + TEST("LTD", "*", 0x3F80); + TEST("LTD", "*-", 0x3F90); + TEST("LTD", "*+", 0x3FA0); + TEST("LTD", "*, AR0", 0x3F88); + TEST("LTD", "*-, AR1", 0x3F99); + TEST("LTD", "*+, AR0", 0x3FA8); + + TEST("LTP", "70H", 0x3E70); + TEST("LTP", "*", 0x3E80); + TEST("LTP", "*-", 0x3E90); + TEST("LTP", "*+", 0x3EA0); + TEST("LTP", "*, AR0", 0x3E88); + TEST("LTP", "*-, AR1", 0x3E99); + TEST("LTP", "*+, AR0", 0x3EA8); + + TEST("LTS", "70H", 0x5B70); + TEST("LTS", "*", 0x5B80); + TEST("LTS", "*-", 0x5B90); + TEST("LTS", "*+", 0x5BA0); + TEST("LTS", "*, AR0", 0x5B88); + TEST("LTS", "*-, AR1", 0x5B99); + TEST("LTS", "*+, AR0", 0x5BA8); + + TEST("MAC", "1000H, 70H", 0x5D70, 0x1000); + TEST("MAC", "2000H, *", 0x5D80, 0x2000); + TEST("MAC", "4000H, *-", 0x5D90, 0x4000); + TEST("MAC", "8000H, *+", 0x5DA0, 0x8000); + TEST("MAC", "1234H, *, AR0", 0x5D88, 0x1234); + TEST("MAC", "5678H, *-, AR1", 0x5D99, 0x5678); + TEST("MAC", "9ABCH, *+, AR0", 0x5DA8, 0x9ABC); + + TEST("MACD", "1000H, 70H", 0x5C70, 0x1000); + TEST("MACD", "2000H, *", 0x5C80, 0x2000); + TEST("MACD", "4000H, *-", 0x5C90, 0x4000); + TEST("MACD", "8000H, *+", 0x5CA0, 0x8000); + TEST("MACD", "1234H, *, AR0", 0x5C88, 0x1234); + TEST("MACD", "5678H, *-, AR1", 0x5C99, 0x5678); + TEST("MACD", "9ABCH, *+, AR0", 0x5CA8, 0x9ABC); + + TEST("MPY", "70H", 0x3870); + TEST("MPY", "*", 0x3880); + TEST("MPY", "*-", 0x3890); + TEST("MPY", "*+", 0x38A0); + TEST("MPY", "*, AR0", 0x3888); + TEST("MPY", "*-, AR1", 0x3899); + TEST("MPY", "*+, AR0", 0x38A8); + + TEST("MPYK", "0", 0xA000); + TEST("MPYK", "2", 0xA002); + TEST("MPYK", "4095", 0xAFFF); + TEST("MPYK", "-1", 0xBFFF); + TEST("MPYK", "-2", 0xBFFE); + TEST("MPYK", "-4096", 0xB000); + + if (is320C2x()) { + TEST("MPYA", "70H", 0x3A70); + TEST("MPYA", "*", 0x3A80); + TEST("MPYA", "*-", 0x3A90); + TEST("MPYA", "*+", 0x3AA0); + TEST("MPYA", "*, AR0", 0x3A88); + TEST("MPYA", "*-, AR1", 0x3A99); + TEST("MPYA", "*+, AR0", 0x3AA8); + + TEST("MPYS", "70H", 0x3B70); + TEST("MPYS", "*", 0x3B80); + TEST("MPYS", "*-", 0x3B90); + TEST("MPYS", "*+", 0x3BA0); + TEST("MPYS", "*, AR0", 0x3B88); + TEST("MPYS", "*-, AR1", 0x3B99); + TEST("MPYS", "*+, AR0", 0x3BA8); + + TEST("MPYU", "70H", 0xCF70); + TEST("MPYU", "*", 0xCF80); + TEST("MPYU", "*-", 0xCF90); + TEST("MPYU", "*+", 0xCFA0); + TEST("MPYU", "*, AR0", 0xCF88); + TEST("MPYU", "*-, AR1", 0xCF99); + TEST("MPYU", "*+, AR0", 0xCFA8); + } + + TEST("PAC", "", 0xCE14); + TEST("SPAC", "", 0xCE16); + + if (is320C2x()) { + TEST("SPH", "70H", 0x7D70); + TEST("SPH", "*", 0x7D80); + TEST("SPH", "*-", 0x7D90); + TEST("SPH", "*+", 0x7DA0); + TEST("SPH", "*, AR0", 0x7D88); + TEST("SPH", "*-, AR1", 0x7D99); + TEST("SPH", "*+, AR0", 0x7DA8); + + TEST("SPL", "70H", 0x7C70); + TEST("SPL", "*", 0x7C80); + TEST("SPL", "*-", 0x7C90); + TEST("SPL", "*+", 0x7CA0); + TEST("SPL", "*, AR0", 0x7C88); + TEST("SPL", "*-, AR1", 0x7C99); + TEST("SPL", "*+, AR0", 0x7CA8); + } + + TEST("SPM", "0", 0xCE08); + TEST("SPM", "1", 0xCE09); + TEST("SPM", "2", 0xCE0A); + TEST("SPM", "3", 0xCE0B); + + TEST("SQRA", "70H", 0x3970); + TEST("SQRA", "*", 0x3980); + TEST("SQRA", "*-", 0x3990); + TEST("SQRA", "*+", 0x39A0); + TEST("SQRA", "*, AR0", 0x3988); + TEST("SQRA", "*-, AR1", 0x3999); + TEST("SQRA", "*+, AR0", 0x39A8); + + TEST("SQRS", "70H", 0x5A70); + TEST("SQRS", "*", 0x5A80); + TEST("SQRS", "*-", 0x5A90); + TEST("SQRS", "*+", 0x5AA0); + TEST("SQRS", "*, AR0", 0x5A88); + TEST("SQRS", "*-, AR1", 0x5A99); + TEST("SQRS", "*+, AR0", 0x5AA8); +} + +void test_branch_1x() { TEST("B", "800H", 0xF900, 0x0800); TEST("B", "0FFFH", 0xF900, 0x0FFF); ERRT("B", "1000H", OVERFLOW_RANGE, "1000H", 0xF900, 0x1000); @@ -399,7 +1054,59 @@ void test_branch() { TEST("RET", "", 0x7F8D); } -void test_control() { +void test_branch_2x() { + TEST("B", "1000H", 0xFF80, 0x1000); + TEST("B", "2000H", 0xFF80, 0x2000); + TEST("B", "4000H", 0xFF80, 0x4000); + TEST("B", "8000H", 0xFF80, 0x8000); + TEST("B", "0FFFFH", 0xFF80, 0xFFFF); + TEST("B", "8000H, *-", 0xFF90, 0x8000); + TEST("B", "8000H, *+", 0xFFA0, 0x8000); + UNKN( 0xFFB0); + TEST("B", "8000H, *BR0-", 0xFFC0, 0x8000); + TEST("B", "8000H, *0-", 0xFFD0, 0x8000); + TEST("B", "8000H, *0+", 0xFFE0, 0x8000); + TEST("B", "8000H, *BR0+", 0xFFF0, 0x8000); + + TEST("BANZ", "9000H", 0xFB80, 0x9000); + TEST("BANZ", "9000H, *+", 0xFBA0, 0x9000); + TEST("BBNZ", "9000H", 0xF980, 0x9000); + TEST("BBNZ", "9000H, *+", 0xF9A0, 0x9000); + TEST("BBZ", "9000H", 0xF880, 0x9000); + TEST("BBZ", "9000H, *+", 0xF8A0, 0x9000); + TEST("BGEZ", "9000H", 0xF480, 0x9000); + TEST("BGEZ", "9000H, *+", 0xF4A0, 0x9000); + TEST("BGZ", "9000H", 0xF180, 0x9000); + TEST("BGZ", "9000H, *+", 0xF1A0, 0x9000); + TEST("BIOZ", "9000H", 0xFA80, 0x9000); + TEST("BIOZ", "9000H, *+", 0xFAA0, 0x9000); + TEST("BLEZ", "9000H", 0xF280, 0x9000); + TEST("BLEZ", "9000H, *+", 0xF2A0, 0x9000); + TEST("BLZ", "9000H", 0xF380, 0x9000); + TEST("BLZ", "9000H, *+", 0xF3A0, 0x9000); + TEST("BNV", "9000H", 0xF780, 0x9000); + TEST("BNV", "9000H, *+", 0xF7A0, 0x9000); + TEST("BNZ", "9000H", 0xF580, 0x9000); + TEST("BNZ", "9000H, *+", 0xF5A0, 0x9000); + TEST("BV", "9000H", 0xF080, 0x9000); + TEST("BV", "9000H, *+", 0xF0A0, 0x9000); + TEST("BZ", "9000H", 0xF680, 0x9000); + TEST("BZ", "9000H, *+", 0xF6A0, 0x9000); + TEST("CALL", "9000H", 0xFE80, 0x9000); + TEST("CALL", "9000H, *+", 0xFEA0, 0x9000); + if (is320C2x()) { + TEST("BC", "9000H", 0x5E80, 0x9000); + TEST("BC", "9000H, *+", 0x5EA0, 0x9000); + TEST("BNC", "9000H", 0x5F80, 0x9000); + TEST("BNC", "9000H, *+", 0x5fA0, 0x9000); + } + + TEST("BACC", "", 0xCE25); + TEST("CALA", "", 0xCE24); + TEST("RET", "", 0xCE26); +} + +void test_control_1x() { TEST("DINT", "", 0x7F81); TEST("EINT", "", 0x7F82); TEST("NOP", "", 0x7F80); @@ -433,7 +1140,92 @@ void test_control() { TEST("SST", "*+, AR0", 0x7CA0); } -void test_dataio() { +void test_control_2x() { + TEST("BIT", "70H, 0", 0x9070); + if (is320C26()) { + UNKN(0xCE04); + UNKN(0xCE05); + TEST("CONF", "0", 0xCE3C); + TEST("CONF", "1", 0xCE3D); + TEST("CONF", "2", 0xCE3E); + TEST("CONF", "3", 0xCE3F); + } else { + TEST("CNFD", "", 0xCE04); + TEST("CNFP", "", 0xCE05); + UNKN(0xCE3C); + UNKN(0xCE3D); + UNKN(0xCE3E); + UNKN(0xCE3F); + } + + TEST("DINT", "", 0xCE01); + TEST("EINT", "", 0xCE00); + TEST("NOP", "", 0x5500); + TEST("POP", "", 0xCE1D); + TEST("PUSH", "", 0xCE1C); + TEST("POPD", "*", 0x7A80); + TEST("PSHD", "*+", 0x54A0); + TEST("ROVM", "", 0xCE02); + TEST("SOVM", "", 0xCE03); + TEST("RSXM", "", 0xCE06); + TEST("SSXM", "", 0xCE07); + if (is320C2x()) { + TEST("RC", "", 0xCE30); + TEST("SC", "", 0xCE31); + TEST("RHM", "", 0xCE38); + TEST("SHM", "", 0xCE39); + TEST("RTC", "", 0xCE32); + TEST("STC", "", 0xCE33); + } + + TEST("RPT", "00H", 0x4B00); + TEST("RPT", "70H", 0x4B70); + TEST("RPT", "*", 0x4B80); + TEST("RPT", "*-", 0x4B90); + TEST("RPT", "*+", 0x4BA0); + TEST("RPT", "*, AR0", 0x4B88); + TEST("RPT", "*-, AR7", 0x4B9F); + TEST("RPT", "*+, AR4", 0x4BAC); + TEST("RPTK", "100", 0xCB64); + + TEST("LST", "00H", 0x5000); + TEST("LST", "70H", 0x5070); + TEST("LST", "*", 0x5080); + TEST("LST", "*-", 0x5090); + TEST("LST", "*+", 0x50A0); + TEST("LST", "*, AR0", 0x5088); + TEST("LST", "*-, AR7", 0x509F); + TEST("LST", "*+, AR4", 0x50AC); + TEST("LST1", "00H", 0x5100); + TEST("LST1", "70H", 0x5170); + TEST("LST1", "*", 0x5180); + TEST("LST1", "*-", 0x5190); + TEST("LST1", "*+", 0x51A0); + TEST("LST1", "*, AR0", 0x5188); + TEST("LST1", "*-, AR7", 0x519F); + TEST("LST1", "*+, AR4", 0x51AC); + + TEST("SST", "10H", 0x7810); + TEST("SST", "1FH", 0x781F); + TEST("SST", "7FH", 0x787F); + TEST("SST", "*", 0x7880); + TEST("SST", "*-", 0x7890); + TEST("SST", "*+", 0x78A0); + TEST("SST", "*, AR0", 0x7888); + TEST("SST", "*-, AR7", 0x789F); + TEST("SST", "*+, AR0", 0x78A8); + TEST("SST1", "10H", 0x7910); + TEST("SST1", "1FH", 0x791F); + TEST("SST1", "7FH", 0x797F); + TEST("SST1", "*", 0x7980); + TEST("SST1", "*-", 0x7990); + TEST("SST1", "*+", 0x79A0); + TEST("SST1", "*, AR0", 0x7988); + TEST("SST1", "*-, AR7", 0x799F); + TEST("SST1", "*+, AR0", 0x79A8); +} + +void test_dataio_1x() { TEST("DMOV", "00H", 0x6900); TEST("DMOV", "70H", 0x6970); TEST("DMOV", "*", 0x6988); @@ -512,6 +1304,100 @@ void test_dataio() { TEST("OUT", "*+, PA7, AR1", 0x4FA1); } +void test_dataio_2x() { + TEST("BLKD", "1234H, 00H", 0xFD00, 0x1234); + TEST("BLKD", "1234H, 70H", 0xFD70, 0x1234); + TEST("BLKD", "1234H, *", 0xFD80, 0x1234); + TEST("BLKD", "1234H, *-", 0xFD90, 0x1234); + TEST("BLKD", "1234H, *+", 0xFDA0, 0x1234); + TEST("BLKD", "1234H, *, AR0", 0xFD88, 0x1234); + TEST("BLKD", "1234H, *-, AR1", 0xFD99, 0x1234); + TEST("BLKD", "1234H, *+, AR0", 0xFDA8, 0x1234); + + TEST("BLKP", "1234H, 00H", 0xFC00, 0x1234); + TEST("BLKP", "1234H, 70H", 0xFC70, 0x1234); + TEST("BLKP", "1234H, *", 0xFC80, 0x1234); + TEST("BLKP", "1234H, *-", 0xFC90, 0x1234); + TEST("BLKP", "1234H, *+", 0xFCA0, 0x1234); + TEST("BLKP", "1234H, *, AR0", 0xFC88, 0x1234); + TEST("BLKP", "1234H, *-, AR1", 0xFC99, 0x1234); + TEST("BLKP", "1234H, *+, AR0", 0xFCA8, 0x1234); + + TEST("DMOV", "00H", 0x5600); + TEST("DMOV", "70H", 0x5670); + TEST("DMOV", "*", 0x5680); + TEST("DMOV", "*-", 0x5690); + TEST("DMOV", "*+", 0x56A0); + TEST("DMOV", "*, AR0", 0x5688); + TEST("DMOV", "*-, AR1", 0x5699); + TEST("DMOV", "*+, AR0", 0x56A8); + + TEST("FORT", "0", 0xCE0E); + TEST("FORT", "1", 0xCE0F); + + if (is320C2x()) { + TEST("RFSM", "", 0xCE36); + TEST("SFSM", "", 0xCE37); + } + TEST("RTXM", "", 0xCE20); + TEST("STXM", "", 0xCE21); + TEST("RXF", "", 0xCE0C); + TEST("SXF", "", 0xCE0D); + + TEST("TBLR", "00H", 0x5800); + TEST("TBLR", "70H", 0x5870); + TEST("TBLR", "*", 0x5880); + TEST("TBLR", "*-", 0x5890); + TEST("TBLR", "*+", 0x58A0); + TEST("TBLR", "*, AR0", 0x5888); + TEST("TBLR", "*-, AR1", 0x5899); + TEST("TBLR", "*+, AR0", 0x58A8); + + TEST("TBLW", "00H", 0x5900); + TEST("TBLW", "70H", 0x5970); + TEST("TBLW", "*", 0x5980); + TEST("TBLW", "*-", 0x5990); + TEST("TBLW", "*+", 0x59A0); + TEST("TBLW", "*, AR0", 0x5988); + TEST("TBLW", "*-, AR1", 0x5999); + TEST("TBLW", "*+, AR0", 0x59A8); + + TEST("IN", "70H, PA0", 0x8070); + TEST("IN", "70H, PA15", 0x8F70); + TEST("IN", "*, PA0, AR0", 0x8088); + TEST("IN", "*, PA15, AR7", 0x8F8F); + TEST("IN", "*, PA0", 0x8080); + TEST("IN", "*-, PA1", 0x8190); + TEST("IN", "*+, PA2", 0x82A0); + TEST("IN", "*BR0-, PA0, AR7", 0x80CF); + TEST("IN", "*, PA1", 0x8180); + TEST("IN", "*-, PA2", 0x8290); + TEST("IN", "*+, PA3", 0x83A0); + TEST("IN", "*, PA0, AR0", 0x8088); + TEST("IN", "*, PA4, AR1", 0x8489); + TEST("IN", "*-, PA4, AR0", 0x8498); + TEST("IN", "*-, PA0, AR1", 0x8099); + TEST("IN", "*+, PA7, AR0", 0x87A8); + TEST("IN", "*+, PA7, AR1", 0x87A9); + + TEST("OUT", "70H, PA8", 0xE870); + TEST("OUT", "70H, PA15", 0xEF70); + TEST("OUT", "*, PA8, AR0", 0xE888); + TEST("OUT", "*, PA15, AR1", 0xEF89); + TEST("OUT", "*, PA8", 0xE880); + TEST("OUT", "*-, PA9", 0xE990); + TEST("OUT", "*+, PA10", 0xEAA0); + TEST("OUT", "*, PA9", 0xE980); + TEST("OUT", "*-, PA10", 0xEA90); + TEST("OUT", "*+, PA11", 0xEBA0); + TEST("OUT", "*, PA8, AR0", 0xE888); + TEST("OUT", "*, PA12, AR1", 0xEC89); + TEST("OUT", "*-, PA12, AR0", 0xEC98); + TEST("OUT", "*-, PA8, AR1", 0xE899); + TEST("OUT", "*+, PA15, AR0", 0xEFA8); + TEST("OUT", "*+, PA15, AR1", 0xEFA9); +} + void assert_low8s(Config::opcode_t base) { for (auto low8 = 0x00; low8 < 0x100; low8++) { const Config::opcode_t opc = base | low8; @@ -519,7 +1405,7 @@ void assert_low8s(Config::opcode_t base) { } } -void assert_indirect(Config::opcode_t base) { +void assert_indirect_1x(Config::opcode_t base) { static constexpr uint8_t valids[] = { 0x80, // *, AR0 0x81, // *, AR1 @@ -543,12 +1429,12 @@ void assert_indirect(Config::opcode_t base) { } } -void test_illegal() { +void test_illegal_1x() { // ADD, SUB, LAC static constexpr Config::opcode_t mam_ls4[] = { 0x0000, 0x1000, 0x2000, }; for (const auto base : mam_ls4) { for (auto ls4 = 0; ls4 < 16; ls4++) { - assert_indirect(base | (ls4 << 8)); + assert_indirect_1x(base | (ls4 << 8)); } } @@ -556,7 +1442,7 @@ void test_illegal() { static constexpr Config::opcode_t ar_mam[] = { 0x3000, 0x3800 }; for (const auto base : ar_mam) { for (auto ar = 0; ar < 2; ar++) { - assert_indirect(base | (ar << 8)); + assert_indirect_1x(base | (ar << 8)); } for (auto ar = 2; ar < 8; ar++) { assert_low8s(base | (ar << 8)); @@ -565,14 +1451,14 @@ void test_illegal() { // IN, OUT for (auto pa = 0; pa < 8; pa++) { - assert_indirect(0x4000 | (pa << 8)); - assert_indirect(0x4800 | (pa << 8)); + assert_indirect_1x(0x4000 | (pa << 8)); + assert_indirect_1x(0x4800 | (pa << 8)); } // SACL for (auto ls0 = 0; ls0 < 8; ls0++) { if (ls0 == 0) { - assert_indirect(0x5000 | (ls0 << 8)); + assert_indirect_1x(0x5000 | (ls0 << 8)); } else { assert_low8s(0x5000 | (ls0 << 8)); } @@ -581,7 +1467,7 @@ void test_illegal() { // SACH for (auto ls3 = 0; ls3 < 8; ls3++) { if (ls3 == 0 || ls3 == 1 || ls3 == 4) { - assert_indirect(0x5800 | (ls3 << 8)); + assert_indirect_1x(0x5800 | (ls3 << 8)); } else { assert_low8s(0x5800 | (ls3 << 8)); } @@ -596,7 +1482,7 @@ void test_illegal() { 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, }; for (size_t idx = 0; idx < sizeof(mam_hi8s); idx++) { - assert_indirect(mam_hi8s[idx] << 8); + assert_indirect_1x(mam_hi8s[idx] << 8); } // LDPK @@ -647,17 +1533,158 @@ void test_illegal() { } } +void assert_indirect_2x(Config::opcode_t base) { + for (auto indir = 0x80; indir < 0x100; indir++) { + const Config::opcode_t opc = base | indir; + const auto modify = (opc >> 4) & 7; + const auto narp = opc & 0xF; + if (modify == 3 || ((narp & 8) == 0 && (narp & 7))) { + UNKN(opc); + } + } +} + +void test_illegal_2x() { + // ADD, SUB, LAC + for (auto ls4 = 0; ls4 < 16; ls4++) { + assert_indirect_2x(0x0000 | (ls4 << 8)); + assert_indirect_2x(0x1000 | (ls4 << 8)); + assert_indirect_2x(0x2000 | (ls4 << 8)); + } + + // LAR, SAR + for (auto ar = 0; ar < 8; ar++) { + assert_indirect_2x(0x3000 | (ar << 8)); + assert_indirect_2x(0x7000 | (ar << 8)); + } + + // MPYA, MPYS, ADDC, SUBB, MPYU + static constexpr uint8_t mam_320C2X_1[] = { 0x3A, 0x3B, 0x43, 0x4F, 0xCF }; + for (auto idx = 0, hi8 = 0x38; hi8 <= 0x5B; hi8++) { + const Config::opcode_t base = hi8 << 8; + if (is32020() && hi8 == mam_320C2X_1[idx]) { + idx++; + assert_low8s(base); + continue; + } + assert_indirect_2x(base); + } + + // SACL, SACH + constexpr auto SACL = 0x6000; + constexpr auto SACH = 0x6800; + for (auto ls3 = 0; ls3 < 8; ls3++) { + if (!is32020() || ls3 == 0 || ls3 == 1 || ls3 == 4) { + assert_indirect_2x(SACL | (ls3 << 8)); + assert_indirect_2x(SACH | (ls3 << 8)); + } else { + assert_low8s(SACL | (ls3 << 8)); + assert_low8s(SACH | (ls3 << 8)); + } + } + + // SST, SST1, POPD, + for (auto hi8 = 0x78; hi8 <= 0x7D; hi8++) { + const Config::opcode_t base = hi8 << 8; + if (hi8 >= 0x7B && is32020()) { + assert_low8s(base); + continue; + } + assert_indirect_2x(base); + } + + // MACD, MAC + assert_indirect_2x(0x5C00); + assert_indirect_2x(0x5D00); + + // BC, BNC, branches + static constexpr uint8_t branches[] = { + 0x5E, 0x5F, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, + 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, + }; + for (size_t idx = 0; idx < sizeof(idx); idx++) { + const Config::opcode_t base = branches[idx] << 8; + for (auto lo8 = 0x00; lo8 < 0x80; lo8++) { + const Config::opcode_t opc = base | lo8; + UNKN(opc); + } + assert_indirect_2x(base); + } + + // IN, OUT, BIT + for (auto pa = 0; pa < 16; pa++) { + assert_indirect_2x(0x8000 | (pa << 8)); + assert_indirect_2x(0x9000 | (pa << 8)); + assert_indirect_2x(0xE000 | (pa << 8)); + } + + // controls etc. + static constexpr uint8_t illegal_low8s[] = { + 0x10, 0x11, 0x12, 0x13, 0x17, 0x1A, + 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + }; + for (auto idx = 0, lo8 = 0; lo8 < 0x100; lo8++) { + const Config::opcode_t opc = 0xCE00 | lo8; + if (lo8 < 0x30) { + if (lo8 == illegal_low8s[idx]) { + UNKN(opc); + idx++; + } + } else if (lo8 <= 0x39) { + if (is32020()) + UNKN(opc); + } else if (lo8 >= 0x3C && lo8 < 0x40) { + if (!is320C26()) + UNKN(opc); + } else if (lo8 >= 0x50 && lo8 < 0x54) { + continue; + } else if ((lo8 & ~0x70) == 0x82) { + const auto ind = (lo8 >> 4) & 7; + if (ind == 0) + continue; + if (is32020()) + UNKN(opc); + } else { + UNKN(opc); + } + } + + // LRLK, LALK, etc + for (auto hi8 = 0xD0; hi8 < 0xE0; hi8++) { + if (hi8 >= 0xD8) { + const Config::opcode_t lrlk = (hi8 << 8) | 0; + UNKN(lrlk); + } + for (auto lo8 = 0x07; lo8 < 0x100; lo8++) { + const Config::opcode_t opc = (hi8 << 8) | lo8; + UNKN(opc); + } + } +} + // clang-format on void run_tests(const char *cpu) { disassembler.setCpu(cpu); - RUN_TEST(test_accumrator); - RUN_TEST(test_auxiliary); - RUN_TEST(test_multiply); - RUN_TEST(test_branch); - RUN_TEST(test_control); - RUN_TEST(test_dataio); - RUN_TEST(test_illegal); + if (is3201x()) { + RUN_TEST(test_accumrator_1x); + RUN_TEST(test_auxiliary_1x); + RUN_TEST(test_multiply_1x); + RUN_TEST(test_branch_1x); + RUN_TEST(test_control_1x); + RUN_TEST(test_dataio_1x); + RUN_TEST(test_illegal_1x); + } + if (is3202x()) { + RUN_TEST(test_accumrator_2x); + RUN_TEST(test_auxiliary_2x); + RUN_TEST(test_multiply_2x); + RUN_TEST(test_branch_2x); + RUN_TEST(test_control_2x); + RUN_TEST(test_dataio_2x); + RUN_TEST(test_illegal_2x); + } } // Local Variables: