A simple 5 stage pipeline in conformance with RISC V Standards.
A single core capable of handling every RV32I Instruction. Minimal verification has been conducted thusfar, however the framework to run simulations and view waveforms are in place.
This project was started to gain experience in digital design and brush up on chip architecture while becoming equipped with RISC V ISA. RTL is described in Verilog 2012 and EDA tools consist of Icarus Verilog & Yosys. I also found the open source risc v assembler python package provided by _ very useful when testing in my Test Bench.
The RV32 Pipeline is architected as a single core standard 5 stage pipeline. Only Fetch and Decode stages will stall in two cases: Failed Branch Prediction and sequential data conflict when the first instruction must write from data memory.
These instructions will get you a copy of the project up and running on your local machine for development and testing purposes. See deployment for notes on how to deploy the project on a live system.
- Verilog 2012 - Language
- Icarus Verilog - Compiler
- GTKWave - Waveform Simulator
- [Risc V Manual] (https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf)) - Instruction Set Architecture
- @sprsr - Idea & Initial work
- Open Source EDA Tools
- Risc V Org
- Onur Mutlu (Computer Architecture lectures on Youtube)