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msrs.h
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MSR_FUNCS(0x6, IA32_MONITOR_FILTER_SIZE)
MSR_FUNCS(0x10, IA32_TIME_STAMP_COUNTER)
MSR_FUNCS(0x17, IA32_PLATFORM_ID)
MSR_FUNCS(0x1B, IA32_APIC_BASE)
MSR_FUNCS(0x3A, IA32_FEATURE_CONTROL)
MSR_FUNCS(0x3B, IA32_TSC_ADJUST)
MSR_FUNCS(0x48, IA32_SPEC_CTRL)
MSR_FUNCS(0x49, IA32_PRED_CMD)
MSR_FUNCS(0x79, IA32_BIOS_UPDT_TRIG)
MSR_FUNCS(0x8B, IA32_BIOS_SIGN_ID)
MSR_FUNCS(0x8C, IA32_SGXLEPUBKEYHASH0)
MSR_FUNCS(0x8D, IA32_SGXLEPUBKEYHASH1)
MSR_FUNCS(0x8E, IA32_SGXLEPUBKEYHASH2)
MSR_FUNCS(0x8F, IA32_SGXLEPUBKEYHASH3)
MSR_FUNCS(0x9B, IA32_SMM_MONITOR_CTL)
MSR_FUNCS(0x9E, IA32_SMBASE)
MSR_FUNCS(0xC1, IA32_PMC0)
MSR_FUNCS(0xC2, IA32_PMC1)
MSR_FUNCS(0xC3, IA32_PMC2)
MSR_FUNCS(0xC4, IA32_PMC3)
MSR_FUNCS(0xC5, IA32_PMC4)
MSR_FUNCS(0xC6, IA32_PMC5)
MSR_FUNCS(0xC7, IA32_PMC6)
MSR_FUNCS(0xC8, IA32_PMC7)
MSR_FUNCS(0xE1, IA32_UMWAIT_CONTROL)
MSR_FUNCS(0xE7, IA32_MPERF)
MSR_FUNCS(0xE8, IA32_APERF)
MSR_FUNCS(0xFE, IA32_MTRRCAP)
MSR_FUNCS(0x10A, IA32_ARCH_CAPABILITIES)
MSR_FUNCS(0x10B, IA32_FLUSH_CMD)
MSR_FUNCS(0x17A, IA32_SYSENTER_CS)
MSR_FUNCS(0x175, IA32_SYSENTER_ESP)
MSR_FUNCS(0x176, IA32_SYSENTER_EIP)
MSR_FUNCS(0x179, IA32_MCG_CAP)
MSR_FUNCS(0x17A, IA32_MCG_STATUS)
MSR_FUNCS(0x17B, IA32_MCG_CTL)
MSR_FUNCS(0x186, IA32_PERFEVTSEL0)
MSR_FUNCS(0x187, IA32_PERFEVTSEL1)
MSR_FUNCS(0x188, IA32_PERFEVTSEL2)
MSR_FUNCS(0x189, IA32_PERFEVTSEL3)
MSR_FUNCS(0x198, IA32_PERF_STATUS)
MSR_FUNCS(0x199, IA32_PERF_CTL)
MSR_FUNCS(0x19A, IA32_CLOCK_MODULATION)
MSR_FUNCS(0x19B, IA32_THERM_INTERRUPT)
MSR_FUNCS(0x19C, IA32_THERM_STATUS)
MSR_FUNCS(0x1A0, IA32_MISC_ENABLE)
MSR_FUNCS(0x1B0, IA32_ENERGY_PERF_BIAS)
MSR_FUNCS(0x1B1, IA32_PACKAGE_THERM_STATUS)
MSR_FUNCS(0x1B2, IA32_PACKAGE_THERM_INTERRUPT)
MSR_FUNCS(0x1D9, IA32_DEBUGCTL)
MSR_FUNCS(0x1F2, IA32_SMRR_PHYSBASE)
MSR_FUNCS(0x1F3, IA32_SMRR_PHYSMASK)
MSR_FUNCS(0x1F8, IA32_PLATFORM_DCA_CAP)
MSR_FUNCS(0x1F9, IA32_CPU_DCA_CAP)
MSR_FUNCS(0x1FA, IA32_DCA_0_CAP)
MSR_FUNCS(0x200, IA32_MTRR_PHYSBASE0)
MSR_FUNCS(0x201, IA32_MTRR_PHYSMASK0)
MSR_FUNCS(0x202, IA32_MTRR_PHYSBASE1)
MSR_FUNCS(0x203, IA32_MTRR_PHYSMASK1)
MSR_FUNCS(0x204, IA32_MTRR_PHYSBASE2)
MSR_FUNCS(0x205, IA32_MTRR_PHYSMASK2)
MSR_FUNCS(0x206, IA32_MTRR_PHYSBASE3)
MSR_FUNCS(0x207, IA32_MTRR_PHYSMASK3)
MSR_FUNCS(0x208, IA32_MTRR_PHYSBASE4)
MSR_FUNCS(0x209, IA32_MTRR_PHYSMASK4)
MSR_FUNCS(0x20A, IA32_MTRR_PHYSBASE5)
MSR_FUNCS(0x20B, IA32_MTRR_PHYSMASK5)
MSR_FUNCS(0x20C, IA32_MTRR_PHYSBASE6)
MSR_FUNCS(0x20D, IA32_MTRR_PHYSMASK6)
MSR_FUNCS(0x20E, IA32_MTRR_PHYSBASE7)
MSR_FUNCS(0x20F, IA32_MTRR_PHYSMASK7)
MSR_FUNCS(0x210, IA32_MTRR_PHYSBASE8)
MSR_FUNCS(0x211, IA32_MTRR_PHYSMASK8)
MSR_FUNCS(0x212, IA32_MTRR_PHYSBASE9)
MSR_FUNCS(0x213, IA32_MTRR_PHYSMASK9)
MSR_FUNCS(0x250, IA32_MTRR_FIX64K_00000)
MSR_FUNCS(0x258, IA32_MTRR_FIX16K_80000)
MSR_FUNCS(0x259, IA32_MTRR_FIX16K_A0000)
MSR_FUNCS(0x268, IA32_MTRR_FIX4K_C0000)
MSR_FUNCS(0x269, IA32_MTRR_FIX4K_C8000)
MSR_FUNCS(0x26A, IA32_MTRR_FIX4K_D0000)
MSR_FUNCS(0x26B, IA32_MTRR_FIX4K_D8000)
MSR_FUNCS(0x26C, IA32_MTRR_FIX4K_E0000)
MSR_FUNCS(0x26D, IA32_MTRR_FIX4K_E8000)
MSR_FUNCS(0x26E, IA32_MTRR_FIX4K_F0000)
MSR_FUNCS(0x26F, IA32_MTRR_FIX4K_F8000)
MSR_FUNCS(0x277, IA32_PAT)
MSR_FUNCS(0x280, IA32_MC0_CTL2)
MSR_FUNCS(0x281, IA32_MC1_CTL2)
MSR_FUNCS(0x282, IA32_MC2_CTL2)
MSR_FUNCS(0x283, IA32_MC3_CTL2)
MSR_FUNCS(0x284, IA32_MC4_CTL2)
MSR_FUNCS(0x285, IA32_MC5_CTL2)
MSR_FUNCS(0x286, IA32_MC6_CTL2)
MSR_FUNCS(0x287, IA32_MC7_CTL2)
MSR_FUNCS(0x288, IA32_MC8_CTL2)
MSR_FUNCS(0x289, IA32_MC9_CTL2)
MSR_FUNCS(0x28A, IA32_MC10_CTL2)
MSR_FUNCS(0x28B, IA32_MC11_CTL2)
MSR_FUNCS(0x28C, IA32_MC12_CTL2)
MSR_FUNCS(0x28D, IA32_MC13_CTL2)
MSR_FUNCS(0x28E, IA32_MC14_CTL2)
MSR_FUNCS(0x28F, IA32_MC15_CTL2)
MSR_FUNCS(0x290, IA32_MC16_CTL2)
MSR_FUNCS(0x291, IA32_MC17_CTL2)
MSR_FUNCS(0x292, IA32_MC18_CTL2)
MSR_FUNCS(0x293, IA32_MC19_CTL2)
MSR_FUNCS(0x294, IA32_MC20_CTL2)
MSR_FUNCS(0x295, IA32_MC21_CTL2)
MSR_FUNCS(0x296, IA32_MC22_CTL2)
MSR_FUNCS(0x297, IA32_MC23_CTL2)
MSR_FUNCS(0x298, IA32_MC24_CTL2)
MSR_FUNCS(0x299, IA32_MC25_CTL2)
MSR_FUNCS(0x29A, IA32_MC26_CTL2)
MSR_FUNCS(0x29B, IA32_MC27_CTL2)
MSR_FUNCS(0x29C, IA32_MC28_CTL2)
MSR_FUNCS(0x29D, IA32_MC29_CTL2)
MSR_FUNCS(0x29E, IA32_MC30_CTL2)
MSR_FUNCS(0x29F, IA32_MC31_CTL2)
MSR_FUNCS(0x2FF, IA32_MTRR_DEF_TYPE)
MSR_FUNCS(0x309, IA32_FIXED_CTR0)
MSR_FUNCS(0x30A, IA32_FIXED_CTR1)
MSR_FUNCS(0x30B, IA32_FIXED_CTR2)
MSR_FUNCS(0x345, IA32_PERF_CAPABILITIES)
MSR_FUNCS(0x38D, IA32_FIXED_CTR_CTRL)
MSR_FUNCS(0x38E, IA32_PERF_GLOBAL_STATUS)
MSR_FUNCS(0x38F, IA32_PERF_GLOBAL_CTRL)
MSR_FUNCS(0x390, IA32_PERF_GLOBAL_STATUS_RESET)
MSR_FUNCS(0x391, IA32_PERF_GLOBAL_STATUS_SET)
MSR_FUNCS(0x392, IA32_PERF_GLOBAL_INUSE)
MSR_FUNCS(0x3F1, IA32_PEBS_ENABLE)
MSR_FUNCS(0x400, IA32_MC0_CTL)
MSR_FUNCS(0x401, IA32_MC0_STATUS)
MSR_FUNCS(0x402, IA32_MC0_ADDR)
MSR_FUNCS(0x403, IA32_MC0_MISC)
MSR_FUNCS(0x404, IA32_MC1_CTL)
MSR_FUNCS(0x405, IA32_MC1_STATUS)
MSR_FUNCS(0x406, IA32_MC1_ADDR)
MSR_FUNCS(0x407, IA32_MC1_MISC)
MSR_FUNCS(0x408, IA32_MC2_CTL)
MSR_FUNCS(0x409, IA32_MC2_STATUS)
MSR_FUNCS(0x40A, IA32_MC2_ADDR)
MSR_FUNCS(0x40B, IA32_MC2_MISC)
MSR_FUNCS(0x40C, IA32_MC3_CTL)
MSR_FUNCS(0x40D, IA32_MC3_STATUS)
MSR_FUNCS(0x40E, IA32_MC3_ADDR)
MSR_FUNCS(0x40F, IA32_MC3_MISC)
MSR_FUNCS(0x410, IA32_MC4_CTL)
MSR_FUNCS(0x411, IA32_MC4_STATUS)
MSR_FUNCS(0x412, IA32_MC4_ADDR)
MSR_FUNCS(0x413, IA32_MC4_MISC)
MSR_FUNCS(0x414, IA32_MC5_CTL)
MSR_FUNCS(0x415, IA32_MC5_STATUS)
MSR_FUNCS(0x416, IA32_MC5_ADDR)
MSR_FUNCS(0x417, IA32_MC5_MISC)
MSR_FUNCS(0x418, IA32_MC6_CTL)
MSR_FUNCS(0x419, IA32_MC6_STATUS)
MSR_FUNCS(0x41A, IA32_MC6_ADDR)
MSR_FUNCS(0x41B, IA32_MC6_MISC)
MSR_FUNCS(0x41C, IA32_MC7_CTL)
MSR_FUNCS(0x41D, IA32_MC7_STATUS)
MSR_FUNCS(0x41E, IA32_MC7_ADDR)
MSR_FUNCS(0x41F, IA32_MC7_MISC)
MSR_FUNCS(0x420, IA32_MC8_CTL)
MSR_FUNCS(0x421, IA32_MC8_STATUS)
MSR_FUNCS(0x422, IA32_MC8_ADDR)
MSR_FUNCS(0x423, IA32_MC8_MISC)
MSR_FUNCS(0x424, IA32_MC9_CTL)
MSR_FUNCS(0x425, IA32_MC9_STATUS)
MSR_FUNCS(0x426, IA32_MC9_ADDR)
MSR_FUNCS(0x427, IA32_MC9_MISC)
MSR_FUNCS(0x428, IA32_MC10_CTL)
MSR_FUNCS(0x429, IA32_MC10_STATUS)
MSR_FUNCS(0x42A, IA32_MC10_ADDR)
MSR_FUNCS(0x42B, IA32_MC10_MISC)
MSR_FUNCS(0x42C, IA32_MC11_CTL)
MSR_FUNCS(0x42D, IA32_MC11_STATUS)
MSR_FUNCS(0x42E, IA32_MC11_ADDR)
MSR_FUNCS(0x42F, IA32_MC11_MISC)
MSR_FUNCS(0x430, IA32_MC12_CTL)
MSR_FUNCS(0x431, IA32_MC12_STATUS)
MSR_FUNCS(0x432, IA32_MC12_ADDR)
MSR_FUNCS(0x433, IA32_MC12_MISC)
MSR_FUNCS(0x434, IA32_MC13_CTL)
MSR_FUNCS(0x435, IA32_MC13_STATUS)
MSR_FUNCS(0x436, IA32_MC13_ADDR)
MSR_FUNCS(0x437, IA32_MC13_MISC)
MSR_FUNCS(0x438, IA32_MC14_CTL)
MSR_FUNCS(0x439, IA32_MC14_STATUS)
MSR_FUNCS(0x43A, IA32_MC14_ADDR)
MSR_FUNCS(0x43B, IA32_MC14_MISC)
MSR_FUNCS(0x43C, IA32_MC15_CTL)
MSR_FUNCS(0x43D, IA32_MC15_STATUS)
MSR_FUNCS(0x43E, IA32_MC15_ADDR)
MSR_FUNCS(0x43F, IA32_MC15_MISC)
MSR_FUNCS(0x440, IA32_MC16_CTL)
MSR_FUNCS(0x441, IA32_MC16_STATUS)
MSR_FUNCS(0x442, IA32_MC16_ADDR)
MSR_FUNCS(0x443, IA32_MC16_MISC)
MSR_FUNCS(0x444, IA32_MC17_CTL)
MSR_FUNCS(0x445, IA32_MC17_STATUS)
MSR_FUNCS(0x446, IA32_MC17_ADDR)
MSR_FUNCS(0x447, IA32_MC17_MISC)
MSR_FUNCS(0x448, IA32_MC18_CTL)
MSR_FUNCS(0x449, IA32_MC18_STATUS)
MSR_FUNCS(0x44A, IA32_MC18_ADDR)
MSR_FUNCS(0x44B, IA32_MC18_MISC)
MSR_FUNCS(0x44C, IA32_MC19_CTL)
MSR_FUNCS(0x44D, IA32_MC19_STATUS)
MSR_FUNCS(0x44E, IA32_MC19_ADDR)
MSR_FUNCS(0x44F, IA32_MC19_MISC)
MSR_FUNCS(0x450, IA32_MC20_CTL)
MSR_FUNCS(0x451, IA32_MC20_STATUS)
MSR_FUNCS(0x452, IA32_MC20_ADDR)
MSR_FUNCS(0x453, IA32_MC20_MISC)
MSR_FUNCS(0x454, IA32_MC21_CTL)
MSR_FUNCS(0x455, IA32_MC21_STATUS)
MSR_FUNCS(0x456, IA32_MC21_ADDR)
MSR_FUNCS(0x457, IA32_MC21_MISC)
MSR_FUNCS(0x458, IA32_MC22_CTL)
MSR_FUNCS(0x459, IA32_MC22_STATUS)
MSR_FUNCS(0x45A, IA32_MC22_ADDR)
MSR_FUNCS(0x45B, IA32_MC22_MISC)
MSR_FUNCS(0x45C, IA32_MC23_CTL)
MSR_FUNCS(0x45D, IA32_MC23_STATUS)
MSR_FUNCS(0x45E, IA32_MC23_ADDR)
MSR_FUNCS(0x45F, IA32_MC23_MISC)
MSR_FUNCS(0x460, IA32_MC24_CTL)
MSR_FUNCS(0x461, IA32_MC24_STATUS)
MSR_FUNCS(0x462, IA32_MC24_ADDR)
MSR_FUNCS(0x463, IA32_MC24_MISC)
MSR_FUNCS(0x464, IA32_MC25_CTL)
MSR_FUNCS(0x465, IA32_MC25_STATUS)
MSR_FUNCS(0x466, IA32_MC25_ADDR)
MSR_FUNCS(0x467, IA32_MC25_MISC)
MSR_FUNCS(0x468, IA32_MC26_CTL)
MSR_FUNCS(0x469, IA32_MC26_STATUS)
MSR_FUNCS(0x46A, IA32_MC26_ADDR)
MSR_FUNCS(0x46B, IA32_MC26_MISC)
MSR_FUNCS(0x46C, IA32_MC27_CTL)
MSR_FUNCS(0x46D, IA32_MC27_STATUS)
MSR_FUNCS(0x46E, IA32_MC27_ADDR)
MSR_FUNCS(0x46F, IA32_MC27_MISC)
MSR_FUNCS(0x470, IA32_MC28_CTL)
MSR_FUNCS(0x471, IA32_MC28_STATUS)
MSR_FUNCS(0x472, IA32_MC28_ADDR)
MSR_FUNCS(0x473, IA32_MC28_MISC)
MSR_FUNCS(0x480, IA32_VMX_BASIC)
MSR_FUNCS(0x481, IA32_VMX_PINBASED_CTLS)
MSR_FUNCS(0x482, IA32_VMX_PROCBASED_CTLS)
MSR_FUNCS(0x483, IA32_VMX_EXIT_CTLS)
MSR_FUNCS(0x484, IA32_VMX_ENTRY_CTLS)
MSR_FUNCS(0x485, IA32_VMX_MISC)
MSR_FUNCS(0x486, IA32_VMX_CR0_FIXED0)
MSR_FUNCS(0x487, IA32_VMX_CR0_FIXED1)
MSR_FUNCS(0x488, IA32_VMX_CR4_FIXED0)
MSR_FUNCS(0x489, IA32_VMX_CR4_FIXED1)
MSR_FUNCS(0x48A, IA32_VMX_VMCS_ENUM)
MSR_FUNCS(0x48B, IA32_VMX_PROCBASED_CTLS2)
MSR_FUNCS(0x48C, IA32_VMX_EPT_VPID_CAP)
MSR_FUNCS(0x48D, IA32_VMX_TRUE_PINBASED_CTLS)
MSR_FUNCS(0x48E, IA32_VMX_TRUE_PROCBASED_CTLS)
MSR_FUNCS(0x48F, IA32_VMX_TRUE_EXIT_CTLS)
MSR_FUNCS(0x490, IA32_VMX_TRUE_ENTRY_CTLS)
MSR_FUNCS(0x491, IA32_VMX_VMFUNC)
MSR_FUNCS(0x4C1, IA32_A_PMC0)
MSR_FUNCS(0x4C2, IA32_A_PMC1)
MSR_FUNCS(0x4C3, IA32_A_PMC2)
MSR_FUNCS(0x4C4, IA32_A_PMC3)
MSR_FUNCS(0x4C5, IA32_A_PMC4)
MSR_FUNCS(0x4C6, IA32_A_PMC5)
MSR_FUNCS(0x4C7, IA32_A_PMC6)
MSR_FUNCS(0x4C8, IA32_A_PMC7)
MSR_FUNCS(0x4D0, IA32_MCG_EXT_CTL)
MSR_FUNCS(0x500, IA32_SGX_SVN_STATUS)
MSR_FUNCS(0x560, IA32_RTIT_OUTPUT_BASE)
MSR_FUNCS(0x561, IA32_RTIT_OUTPUT_MASK_PTRS)
MSR_FUNCS(0x570, IA32_RTIT_CTL)
MSR_FUNCS(0x571, IA32_RTIT_STATUS)
MSR_FUNCS(0x572, IA32_RTIT_CR3_MATCH)
MSR_FUNCS(0x580, IA32_RTIT_ADDR0_A)
MSR_FUNCS(0x581, IA32_RTIT_ADDR0_B)
MSR_FUNCS(0x582, IA32_RTIT_ADDR1_A)
MSR_FUNCS(0x583, IA32_RTIT_ADDR1_B)
MSR_FUNCS(0x584, IA32_RTIT_ADDR2_A)
MSR_FUNCS(0x585, IA32_RTIT_ADDR2_B)
MSR_FUNCS(0x586, IA32_RTIT_ADDR3_A)
MSR_FUNCS(0x587, IA32_RTIT_ADDR3_B)
MSR_FUNCS(0x600, IA32_DS_AREA)
MSR_FUNCS(0x6E0, IA32_TSC_DEADLINE)
MSR_FUNCS(0x770, IA32_PM_ENABLE)
MSR_FUNCS(0x771, IA32_HWP_CAPABILITIES)
MSR_FUNCS(0x772, IA32_HWP_REQUEST_PKG)
MSR_FUNCS(0x773, IA32_HWP_INTERRUPT)
MSR_FUNCS(0x774, IA32_HWP_REQUEST)
MSR_FUNCS(0x777, IA32_HWP_STATUS)
MSR_FUNCS(0x802, IA32_X2APIC_APICID)
MSR_FUNCS(0x803, IA32_X2APIC_VERSION)
MSR_FUNCS(0x808, IA32_X2APIC_TPR)
MSR_FUNCS(0x80A, IA32_X2APIC_PPR)
MSR_FUNCS(0x80B, IA32_X2APIC_EOI)
MSR_FUNCS(0x80D, IA32_X2APIC_LDR)
MSR_FUNCS(0x80F, IA32_X2APIC_SIVR)
MSR_FUNCS(0x810, IA32_X2APIC_ISR0)
MSR_FUNCS(0x811, IA32_X2APIC_ISR1)
MSR_FUNCS(0x812, IA32_X2APIC_ISR2)
MSR_FUNCS(0x813, IA32_X2APIC_ISR3)
MSR_FUNCS(0x814, IA32_X2APIC_ISR4)
MSR_FUNCS(0x815, IA32_X2APIC_ISR5)
MSR_FUNCS(0x816, IA32_X2APIC_ISR6)
MSR_FUNCS(0x817, IA32_X2APIC_ISR7)
MSR_FUNCS(0x818, IA32_X2APIC_TMR0)
MSR_FUNCS(0x819, IA32_X2APIC_TMR1)
MSR_FUNCS(0x81A, IA32_X2APIC_TMR2)
MSR_FUNCS(0x81B, IA32_X2APIC_TMR3)
MSR_FUNCS(0x81C, IA32_X2APIC_TMR4)
MSR_FUNCS(0x81D, IA32_X2APIC_TMR5)
MSR_FUNCS(0x81E, IA32_X2APIC_TMR6)
MSR_FUNCS(0x81F, IA32_X2APIC_TMR7)
MSR_FUNCS(0x820, IA32_X2APIC_IRR0)
MSR_FUNCS(0x821, IA32_X2APIC_IRR1)
MSR_FUNCS(0x822, IA32_X2APIC_IRR2)
MSR_FUNCS(0x823, IA32_X2APIC_IRR3)
MSR_FUNCS(0x824, IA32_X2APIC_IRR4)
MSR_FUNCS(0x825, IA32_X2APIC_IRR5)
MSR_FUNCS(0x826, IA32_X2APIC_IRR6)
MSR_FUNCS(0x827, IA32_X2APIC_IRR7)
MSR_FUNCS(0x828, IA32_X2APIC_ESR)
MSR_FUNCS(0x82F, IA32_X2APIC_LVT_CMCI)
MSR_FUNCS(0x830, IA32_X2APIC_ICR)
MSR_FUNCS(0x832, IA32_X2APIC_LVT_TIMER)
MSR_FUNCS(0x833, IA32_X2APIC_LVT_THERMAL)
MSR_FUNCS(0x834, IA32_X2APIC_LVT_PMI)
MSR_FUNCS(0x835, IA32_X2APIC_LVT_LINT0)
MSR_FUNCS(0x836, IA32_X2APIC_LVT_LINT1)
MSR_FUNCS(0x837, IA32_X2APIC_LVT_ERROR)
MSR_FUNCS(0x838, IA32_X2APIC_INIT_COUNT)
MSR_FUNCS(0x839, IA32_X2APIC_CUR_COUNT)
MSR_FUNCS(0x83E, IA32_X2APIC_DIV_CONF)
MSR_FUNCS(0x83F, IA32_X2APIC_SELF_IPI)
MSR_FUNCS(0xC80, IA32_DEBUG_INTERFACE)
MSR_FUNCS(0xC81, IA32_L3_QOS_CFG)
MSR_FUNCS(0xC82, IA32_L2_QOS_CFG)
MSR_FUNCS(0xC8D, IA32_QM_EVTSEL)
MSR_FUNCS(0xC8E, IA32_QM_CTR)
MSR_FUNCS(0xC8F, IA32_PQR_ASSOC)
MSR_FUNCS(0xC90, IA32_L3_MASK_0)
MSR_FUNCS(0xD10, IA32_L2_MASK_0)
MSR_FUNCS(0xD90, IA32_BNDCFGS)
MSR_FUNCS(0xDA0, IA32_XSS)
MSR_FUNCS(0xDB0, IA32_PKG_HDC_CTL)
MSR_FUNCS(0xDB1, IA32_PM_CTL1)
MSR_FUNCS(0xDB2, IA32_THREAD_STALL)
MSR_FUNCS(0xC0000080, IA32_EFER)
MSR_FUNCS(0xC0000081, IA32_STAR)
MSR_FUNCS(0xC0000082, IA32_LSTAR)
MSR_FUNCS(0xC0000083, IA32_CSTAR)
MSR_FUNCS(0xC0000084, IA32_FMASK)
MSR_FUNCS(0xC0000100, IA32_FS_BASE)
MSR_FUNCS(0xC0000101, IA32_GS_BASE)
MSR_FUNCS(0xC0000102, IA32_KERNEL_GS_BASE)
MSR_FUNCS(0xC0000103, IA32_TSC_AUX)
#define MSR(_addr, _name) { \
.addr = _addr, \
.name = #_name, \
.attr = __ATTR(_name, 0660, show_msr_##_name, store_msr_##_name) \
},
#define END_MSRS { .addr = 0x0 }
static struct msr_def msrs[] = {
MSR(0x6, IA32_MONITOR_FILTER_SIZE)
MSR(0x10, IA32_TIME_STAMP_COUNTER)
MSR(0x17, IA32_PLATFORM_ID)
MSR(0x1B, IA32_APIC_BASE)
MSR(0x3A, IA32_FEATURE_CONTROL)
MSR(0x3B, IA32_TSC_ADJUST)
MSR(0x48, IA32_SPEC_CTRL)
MSR(0x49, IA32_PRED_CMD)
MSR(0x79, IA32_BIOS_UPDT_TRIG)
MSR(0x8B, IA32_BIOS_SIGN_ID)
MSR(0x8C, IA32_SGXLEPUBKEYHASH0)
MSR(0x8D, IA32_SGXLEPUBKEYHASH1)
MSR(0x8E, IA32_SGXLEPUBKEYHASH2)
MSR(0x8F, IA32_SGXLEPUBKEYHASH3)
MSR(0x9B, IA32_SMM_MONITOR_CTL)
MSR(0x9E, IA32_SMBASE)
MSR(0xC1, IA32_PMC0)
MSR(0xC2, IA32_PMC1)
MSR(0xC3, IA32_PMC2)
MSR(0xC4, IA32_PMC3)
MSR(0xC5, IA32_PMC4)
MSR(0xC6, IA32_PMC5)
MSR(0xC7, IA32_PMC6)
MSR(0xC8, IA32_PMC7)
MSR(0xE1, IA32_UMWAIT_CONTROL)
MSR(0xE7, IA32_MPERF)
MSR(0xE8, IA32_APERF)
MSR(0xFE, IA32_MTRRCAP)
MSR(0x10A, IA32_ARCH_CAPABILITIES)
MSR(0x10B, IA32_FLUSH_CMD)
MSR(0x17A, IA32_SYSENTER_CS)
MSR(0x175, IA32_SYSENTER_ESP)
MSR(0x176, IA32_SYSENTER_EIP)
MSR(0x179, IA32_MCG_CAP)
MSR(0x17A, IA32_MCG_STATUS)
MSR(0x17B, IA32_MCG_CTL)
MSR(0x186, IA32_PERFEVTSEL0)
MSR(0x187, IA32_PERFEVTSEL1)
MSR(0x188, IA32_PERFEVTSEL2)
MSR(0x189, IA32_PERFEVTSEL3)
MSR(0x198, IA32_PERF_STATUS)
MSR(0x199, IA32_PERF_CTL)
MSR(0x19A, IA32_CLOCK_MODULATION)
MSR(0x19B, IA32_THERM_INTERRUPT)
MSR(0x19C, IA32_THERM_STATUS)
MSR(0x1A0, IA32_MISC_ENABLE)
MSR(0x1B0, IA32_ENERGY_PERF_BIAS)
MSR(0x1B1, IA32_PACKAGE_THERM_STATUS)
MSR(0x1B2, IA32_PACKAGE_THERM_INTERRUPT)
MSR(0x1D9, IA32_DEBUGCTL)
MSR(0x1F2, IA32_SMRR_PHYSBASE)
MSR(0x1F3, IA32_SMRR_PHYSMASK)
MSR(0x1F8, IA32_PLATFORM_DCA_CAP)
MSR(0x1F9, IA32_CPU_DCA_CAP)
MSR(0x1FA, IA32_DCA_0_CAP)
MSR(0x200, IA32_MTRR_PHYSBASE0)
MSR(0x201, IA32_MTRR_PHYSMASK0)
MSR(0x202, IA32_MTRR_PHYSBASE1)
MSR(0x203, IA32_MTRR_PHYSMASK1)
MSR(0x204, IA32_MTRR_PHYSBASE2)
MSR(0x205, IA32_MTRR_PHYSMASK2)
MSR(0x206, IA32_MTRR_PHYSBASE3)
MSR(0x207, IA32_MTRR_PHYSMASK3)
MSR(0x208, IA32_MTRR_PHYSBASE4)
MSR(0x209, IA32_MTRR_PHYSMASK4)
MSR(0x20A, IA32_MTRR_PHYSBASE5)
MSR(0x20B, IA32_MTRR_PHYSMASK5)
MSR(0x20C, IA32_MTRR_PHYSBASE6)
MSR(0x20D, IA32_MTRR_PHYSMASK6)
MSR(0x20E, IA32_MTRR_PHYSBASE7)
MSR(0x20F, IA32_MTRR_PHYSMASK7)
MSR(0x210, IA32_MTRR_PHYSBASE8)
MSR(0x211, IA32_MTRR_PHYSMASK8)
MSR(0x212, IA32_MTRR_PHYSBASE9)
MSR(0x213, IA32_MTRR_PHYSMASK9)
MSR(0x250, IA32_MTRR_FIX64K_00000)
MSR(0x258, IA32_MTRR_FIX16K_80000)
MSR(0x259, IA32_MTRR_FIX16K_A0000)
MSR(0x268, IA32_MTRR_FIX4K_C0000)
MSR(0x269, IA32_MTRR_FIX4K_C8000)
MSR(0x26A, IA32_MTRR_FIX4K_D0000)
MSR(0x26B, IA32_MTRR_FIX4K_D8000)
MSR(0x26C, IA32_MTRR_FIX4K_E0000)
MSR(0x26D, IA32_MTRR_FIX4K_E8000)
MSR(0x26E, IA32_MTRR_FIX4K_F0000)
MSR(0x26F, IA32_MTRR_FIX4K_F8000)
MSR(0x277, IA32_PAT)
MSR(0x280, IA32_MC0_CTL2)
MSR(0x281, IA32_MC1_CTL2)
MSR(0x282, IA32_MC2_CTL2)
MSR(0x283, IA32_MC3_CTL2)
MSR(0x284, IA32_MC4_CTL2)
MSR(0x285, IA32_MC5_CTL2)
MSR(0x286, IA32_MC6_CTL2)
MSR(0x287, IA32_MC7_CTL2)
MSR(0x288, IA32_MC8_CTL2)
MSR(0x289, IA32_MC9_CTL2)
MSR(0x28A, IA32_MC10_CTL2)
MSR(0x28B, IA32_MC11_CTL2)
MSR(0x28C, IA32_MC12_CTL2)
MSR(0x28D, IA32_MC13_CTL2)
MSR(0x28E, IA32_MC14_CTL2)
MSR(0x28F, IA32_MC15_CTL2)
MSR(0x290, IA32_MC16_CTL2)
MSR(0x291, IA32_MC17_CTL2)
MSR(0x292, IA32_MC18_CTL2)
MSR(0x293, IA32_MC19_CTL2)
MSR(0x294, IA32_MC20_CTL2)
MSR(0x295, IA32_MC21_CTL2)
MSR(0x296, IA32_MC22_CTL2)
MSR(0x297, IA32_MC23_CTL2)
MSR(0x298, IA32_MC24_CTL2)
MSR(0x299, IA32_MC25_CTL2)
MSR(0x29A, IA32_MC26_CTL2)
MSR(0x29B, IA32_MC27_CTL2)
MSR(0x29C, IA32_MC28_CTL2)
MSR(0x29D, IA32_MC29_CTL2)
MSR(0x29E, IA32_MC30_CTL2)
MSR(0x29F, IA32_MC31_CTL2)
MSR(0x2FF, IA32_MTRR_DEF_TYPE)
MSR(0x309, IA32_FIXED_CTR0)
MSR(0x30A, IA32_FIXED_CTR1)
MSR(0x30B, IA32_FIXED_CTR2)
MSR(0x345, IA32_PERF_CAPABILITIES)
MSR(0x38D, IA32_FIXED_CTR_CTRL)
MSR(0x38E, IA32_PERF_GLOBAL_STATUS)
MSR(0x38F, IA32_PERF_GLOBAL_CTRL)
MSR(0x390, IA32_PERF_GLOBAL_STATUS_RESET)
MSR(0x391, IA32_PERF_GLOBAL_STATUS_SET)
MSR(0x392, IA32_PERF_GLOBAL_INUSE)
MSR(0x3F1, IA32_PEBS_ENABLE)
MSR(0x400, IA32_MC0_CTL)
MSR(0x401, IA32_MC0_STATUS)
MSR(0x402, IA32_MC0_ADDR)
MSR(0x403, IA32_MC0_MISC)
MSR(0x404, IA32_MC1_CTL)
MSR(0x405, IA32_MC1_STATUS)
MSR(0x406, IA32_MC1_ADDR)
MSR(0x407, IA32_MC1_MISC)
MSR(0x408, IA32_MC2_CTL)
MSR(0x409, IA32_MC2_STATUS)
MSR(0x40A, IA32_MC2_ADDR)
MSR(0x40B, IA32_MC2_MISC)
MSR(0x40C, IA32_MC3_CTL)
MSR(0x40D, IA32_MC3_STATUS)
MSR(0x40E, IA32_MC3_ADDR)
MSR(0x40F, IA32_MC3_MISC)
MSR(0x410, IA32_MC4_CTL)
MSR(0x411, IA32_MC4_STATUS)
MSR(0x412, IA32_MC4_ADDR)
MSR(0x413, IA32_MC4_MISC)
MSR(0x414, IA32_MC5_CTL)
MSR(0x415, IA32_MC5_STATUS)
MSR(0x416, IA32_MC5_ADDR)
MSR(0x417, IA32_MC5_MISC)
MSR(0x418, IA32_MC6_CTL)
MSR(0x419, IA32_MC6_STATUS)
MSR(0x41A, IA32_MC6_ADDR)
MSR(0x41B, IA32_MC6_MISC)
MSR(0x41C, IA32_MC7_CTL)
MSR(0x41D, IA32_MC7_STATUS)
MSR(0x41E, IA32_MC7_ADDR)
MSR(0x41F, IA32_MC7_MISC)
MSR(0x420, IA32_MC8_CTL)
MSR(0x421, IA32_MC8_STATUS)
MSR(0x422, IA32_MC8_ADDR)
MSR(0x423, IA32_MC8_MISC)
MSR(0x424, IA32_MC9_CTL)
MSR(0x425, IA32_MC9_STATUS)
MSR(0x426, IA32_MC9_ADDR)
MSR(0x427, IA32_MC9_MISC)
MSR(0x428, IA32_MC10_CTL)
MSR(0x429, IA32_MC10_STATUS)
MSR(0x42A, IA32_MC10_ADDR)
MSR(0x42B, IA32_MC10_MISC)
MSR(0x42C, IA32_MC11_CTL)
MSR(0x42D, IA32_MC11_STATUS)
MSR(0x42E, IA32_MC11_ADDR)
MSR(0x42F, IA32_MC11_MISC)
MSR(0x430, IA32_MC12_CTL)
MSR(0x431, IA32_MC12_STATUS)
MSR(0x432, IA32_MC12_ADDR)
MSR(0x433, IA32_MC12_MISC)
MSR(0x434, IA32_MC13_CTL)
MSR(0x435, IA32_MC13_STATUS)
MSR(0x436, IA32_MC13_ADDR)
MSR(0x437, IA32_MC13_MISC)
MSR(0x438, IA32_MC14_CTL)
MSR(0x439, IA32_MC14_STATUS)
MSR(0x43A, IA32_MC14_ADDR)
MSR(0x43B, IA32_MC14_MISC)
MSR(0x43C, IA32_MC15_CTL)
MSR(0x43D, IA32_MC15_STATUS)
MSR(0x43E, IA32_MC15_ADDR)
MSR(0x43F, IA32_MC15_MISC)
MSR(0x440, IA32_MC16_CTL)
MSR(0x441, IA32_MC16_STATUS)
MSR(0x442, IA32_MC16_ADDR)
MSR(0x443, IA32_MC16_MISC)
MSR(0x444, IA32_MC17_CTL)
MSR(0x445, IA32_MC17_STATUS)
MSR(0x446, IA32_MC17_ADDR)
MSR(0x447, IA32_MC17_MISC)
MSR(0x448, IA32_MC18_CTL)
MSR(0x449, IA32_MC18_STATUS)
MSR(0x44A, IA32_MC18_ADDR)
MSR(0x44B, IA32_MC18_MISC)
MSR(0x44C, IA32_MC19_CTL)
MSR(0x44D, IA32_MC19_STATUS)
MSR(0x44E, IA32_MC19_ADDR)
MSR(0x44F, IA32_MC19_MISC)
MSR(0x450, IA32_MC20_CTL)
MSR(0x451, IA32_MC20_STATUS)
MSR(0x452, IA32_MC20_ADDR)
MSR(0x453, IA32_MC20_MISC)
MSR(0x454, IA32_MC21_CTL)
MSR(0x455, IA32_MC21_STATUS)
MSR(0x456, IA32_MC21_ADDR)
MSR(0x457, IA32_MC21_MISC)
MSR(0x458, IA32_MC22_CTL)
MSR(0x459, IA32_MC22_STATUS)
MSR(0x45A, IA32_MC22_ADDR)
MSR(0x45B, IA32_MC22_MISC)
MSR(0x45C, IA32_MC23_CTL)
MSR(0x45D, IA32_MC23_STATUS)
MSR(0x45E, IA32_MC23_ADDR)
MSR(0x45F, IA32_MC23_MISC)
MSR(0x460, IA32_MC24_CTL)
MSR(0x461, IA32_MC24_STATUS)
MSR(0x462, IA32_MC24_ADDR)
MSR(0x463, IA32_MC24_MISC)
MSR(0x464, IA32_MC25_CTL)
MSR(0x465, IA32_MC25_STATUS)
MSR(0x466, IA32_MC25_ADDR)
MSR(0x467, IA32_MC25_MISC)
MSR(0x468, IA32_MC26_CTL)
MSR(0x469, IA32_MC26_STATUS)
MSR(0x46A, IA32_MC26_ADDR)
MSR(0x46B, IA32_MC26_MISC)
MSR(0x46C, IA32_MC27_CTL)
MSR(0x46D, IA32_MC27_STATUS)
MSR(0x46E, IA32_MC27_ADDR)
MSR(0x46F, IA32_MC27_MISC)
MSR(0x470, IA32_MC28_CTL)
MSR(0x471, IA32_MC28_STATUS)
MSR(0x472, IA32_MC28_ADDR)
MSR(0x473, IA32_MC28_MISC)
MSR(0x480, IA32_VMX_BASIC)
MSR(0x481, IA32_VMX_PINBASED_CTLS)
MSR(0x482, IA32_VMX_PROCBASED_CTLS)
MSR(0x483, IA32_VMX_EXIT_CTLS)
MSR(0x484, IA32_VMX_ENTRY_CTLS)
MSR(0x485, IA32_VMX_MISC)
MSR(0x486, IA32_VMX_CR0_FIXED0)
MSR(0x487, IA32_VMX_CR0_FIXED1)
MSR(0x488, IA32_VMX_CR4_FIXED0)
MSR(0x489, IA32_VMX_CR4_FIXED1)
MSR(0x48A, IA32_VMX_VMCS_ENUM)
MSR(0x48B, IA32_VMX_PROCBASED_CTLS2)
MSR(0x48C, IA32_VMX_EPT_VPID_CAP)
MSR(0x48D, IA32_VMX_TRUE_PINBASED_CTLS)
MSR(0x48E, IA32_VMX_TRUE_PROCBASED_CTLS)
MSR(0x48F, IA32_VMX_TRUE_EXIT_CTLS)
MSR(0x490, IA32_VMX_TRUE_ENTRY_CTLS)
MSR(0x491, IA32_VMX_VMFUNC)
MSR(0x4C1, IA32_A_PMC0)
MSR(0x4C2, IA32_A_PMC1)
MSR(0x4C3, IA32_A_PMC2)
MSR(0x4C4, IA32_A_PMC3)
MSR(0x4C5, IA32_A_PMC4)
MSR(0x4C6, IA32_A_PMC5)
MSR(0x4C7, IA32_A_PMC6)
MSR(0x4C8, IA32_A_PMC7)
MSR(0x4D0, IA32_MCG_EXT_CTL)
MSR(0x500, IA32_SGX_SVN_STATUS)
MSR(0x560, IA32_RTIT_OUTPUT_BASE)
MSR(0x561, IA32_RTIT_OUTPUT_MASK_PTRS)
MSR(0x570, IA32_RTIT_CTL)
MSR(0x571, IA32_RTIT_STATUS)
MSR(0x572, IA32_RTIT_CR3_MATCH)
MSR(0x580, IA32_RTIT_ADDR0_A)
MSR(0x581, IA32_RTIT_ADDR0_B)
MSR(0x582, IA32_RTIT_ADDR1_A)
MSR(0x583, IA32_RTIT_ADDR1_B)
MSR(0x584, IA32_RTIT_ADDR2_A)
MSR(0x585, IA32_RTIT_ADDR2_B)
MSR(0x586, IA32_RTIT_ADDR3_A)
MSR(0x587, IA32_RTIT_ADDR3_B)
MSR(0x600, IA32_DS_AREA)
MSR(0x6E0, IA32_TSC_DEADLINE)
MSR(0x770, IA32_PM_ENABLE)
MSR(0x771, IA32_HWP_CAPABILITIES)
MSR(0x772, IA32_HWP_REQUEST_PKG)
MSR(0x773, IA32_HWP_INTERRUPT)
MSR(0x774, IA32_HWP_REQUEST)
MSR(0x777, IA32_HWP_STATUS)
MSR(0x802, IA32_X2APIC_APICID)
MSR(0x803, IA32_X2APIC_VERSION)
MSR(0x808, IA32_X2APIC_TPR)
MSR(0x80A, IA32_X2APIC_PPR)
MSR(0x80B, IA32_X2APIC_EOI)
MSR(0x80D, IA32_X2APIC_LDR)
MSR(0x80F, IA32_X2APIC_SIVR)
MSR(0x810, IA32_X2APIC_ISR0)
MSR(0x811, IA32_X2APIC_ISR1)
MSR(0x812, IA32_X2APIC_ISR2)
MSR(0x813, IA32_X2APIC_ISR3)
MSR(0x814, IA32_X2APIC_ISR4)
MSR(0x815, IA32_X2APIC_ISR5)
MSR(0x816, IA32_X2APIC_ISR6)
MSR(0x817, IA32_X2APIC_ISR7)
MSR(0x818, IA32_X2APIC_TMR0)
MSR(0x819, IA32_X2APIC_TMR1)
MSR(0x81A, IA32_X2APIC_TMR2)
MSR(0x81B, IA32_X2APIC_TMR3)
MSR(0x81C, IA32_X2APIC_TMR4)
MSR(0x81D, IA32_X2APIC_TMR5)
MSR(0x81E, IA32_X2APIC_TMR6)
MSR(0x81F, IA32_X2APIC_TMR7)
MSR(0x820, IA32_X2APIC_IRR0)
MSR(0x821, IA32_X2APIC_IRR1)
MSR(0x822, IA32_X2APIC_IRR2)
MSR(0x823, IA32_X2APIC_IRR3)
MSR(0x824, IA32_X2APIC_IRR4)
MSR(0x825, IA32_X2APIC_IRR5)
MSR(0x826, IA32_X2APIC_IRR6)
MSR(0x827, IA32_X2APIC_IRR7)
MSR(0x828, IA32_X2APIC_ESR)
MSR(0x82F, IA32_X2APIC_LVT_CMCI)
MSR(0x830, IA32_X2APIC_ICR)
MSR(0x832, IA32_X2APIC_LVT_TIMER)
MSR(0x833, IA32_X2APIC_LVT_THERMAL)
MSR(0x834, IA32_X2APIC_LVT_PMI)
MSR(0x835, IA32_X2APIC_LVT_LINT0)
MSR(0x836, IA32_X2APIC_LVT_LINT1)
MSR(0x837, IA32_X2APIC_LVT_ERROR)
MSR(0x838, IA32_X2APIC_INIT_COUNT)
MSR(0x839, IA32_X2APIC_CUR_COUNT)
MSR(0x83E, IA32_X2APIC_DIV_CONF)
MSR(0x83F, IA32_X2APIC_SELF_IPI)
MSR(0xC80, IA32_DEBUG_INTERFACE)
MSR(0xC81, IA32_L3_QOS_CFG)
MSR(0xC82, IA32_L2_QOS_CFG)
MSR(0xC8D, IA32_QM_EVTSEL)
MSR(0xC8E, IA32_QM_CTR)
MSR(0xC8F, IA32_PQR_ASSOC)
MSR(0xC90, IA32_L3_MASK_0)
MSR(0xD10, IA32_L2_MASK_0)
MSR(0xD90, IA32_BNDCFGS)
MSR(0xDA0, IA32_XSS)
MSR(0xDB0, IA32_PKG_HDC_CTL)
MSR(0xDB1, IA32_PM_CTL1)
MSR(0xDB2, IA32_THREAD_STALL)
MSR(0xC0000080, IA32_EFER)
MSR(0xC0000081, IA32_STAR)
MSR(0xC0000082, IA32_LSTAR)
MSR(0xC0000083, IA32_CSTAR)
MSR(0xC0000084, IA32_FMASK)
MSR(0xC0000100, IA32_FS_BASE)
MSR(0xC0000101, IA32_GS_BASE)
MSR(0xC0000102, IA32_KERNEL_GS_BASE)
MSR(0xC0000103, IA32_TSC_AUX)
END_MSRS
};