Skip to content

@efabless Efabless

Change the repository type filter

All

    Repositories list

    228 repositories

    • sky130_ef_ip__rdac3v_8bit

      Public
      8-bit resistor ladder DAC with 3.3V output range
      MATLAB
      •
      Apache License 2.0
      •2•0•0•0•Updated Feb 25, 2025Feb 25, 2025

    • frigate_analog

      Public
      The analog signal processing and timing frontend subsystems for the Frigate harness chip
      Verilog
      •
      Apache License 2.0
      •0•0•1•1•Updated Feb 25, 2025Feb 25, 2025

    • openlane-metrics

      Public
      Repository to store metric results for OpenLane 2.0.0+
      0•0•0•0•Updated Feb 25, 2025Feb 25, 2025

    • Caravel_on_FPGA

      Public
      Verilog
      •0•4•1•0•Updated Feb 25, 2025Feb 25, 2025

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      flowasicedaverilogvlsipnrsiliconlvsflowssta
      Python
      •
      Apache License 2.0
      •46•269•85•11•Updated Feb 25, 2025Feb 25, 2025

    • IHP-Open-PDK

      Public
      130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
      HTML
      •
      Apache License 2.0
      •73•0•1•0•Updated Feb 25, 2025Feb 25, 2025

    • frigate-os

      Public
      Verilog
      •0•0•0•0•Updated Feb 25, 2025Feb 25, 2025

    • openlane2-step-unit-tests

      Public
      Step-specific Unit Tests for OpenLane 2.0.0+
      Verilog
      •
      Apache License 2.0
      •0•0•0•2•Updated Feb 25, 2025Feb 25, 2025

    • mpw_precheck

      Public
      Python
      •
      Apache License 2.0
      •24•36•40•7•Updated Feb 25, 2025Feb 25, 2025

    • caravel_user_project

      Public template
      https://caravel-user-project.readthedocs.io
      Verilog
      •
      Apache License 2.0
      •338•192•85•22•Updated Feb 25, 2025Feb 25, 2025

    • sky130_ef_ip__samplehold

      Public
      Analog 3.3V sample and hold circuit, with buffered output
      Tcl
      •
      Apache License 2.0
      •2•0•0•0•Updated Feb 25, 2025Feb 25, 2025

    • ipm

      Public
      Open-source IPs Package Manager (IPM)
      Python
      •
      Apache License 2.0
      •2•14•7•0•Updated Feb 24, 2025Feb 24, 2025

    • nix-eda

      Public
      Nix derivations for EDA tools
      nixedaelectronic-design-automationnix-flake
      Nix
      •
      Apache License 2.0
      •3•9•2•0•Updated Feb 24, 2025Feb 24, 2025

    • caravel_user_sram

      Public
      Verilog
      •
      Apache License 2.0
      •0•4•7•1•Updated Feb 24, 2025Feb 24, 2025

    • sky130_ef_ip__template

      Public template
      A template repository for analog designs to ensure consistency and interoperability between IP blocks.
      Apache License 2.0
      •0•0•0•0•Updated Feb 24, 2025Feb 24, 2025

    • EF_SRAM_1024x32

      Public
      Verilog
      •0•3•7•0•Updated Feb 23, 2025Feb 23, 2025

    • EF_SHA256

      Public
      Verilog
      •0•0•2•1•Updated Feb 23, 2025Feb 23, 2025

    • caravel_SI_testing

      Public
      C
      •1•2•3•5•Updated Feb 23, 2025Feb 23, 2025

    • openlane2-ci-designs

      Public
      Continuous Integration Designs for OpenLane 2.0.0 or higher
      Verilog
      •1•0•0•0•Updated Feb 23, 2025Feb 23, 2025

    • central_CI

      Public
      0•0•1•5•Updated Feb 22, 2025Feb 22, 2025

    • openframe_timer_example

      Public
      Example digital project for the Efabless Caravel "openframe" harness
      Verilog
      •
      Apache License 2.0
      •13•4•3•0•Updated Feb 21, 2025Feb 21, 2025

    • sky130_ef_ip__adc3v_12bit

      Public
      12-bit ADC using other analog component repositories for the sample & hold, DAC, and comparator.
      Verilog
      •
      Apache License 2.0
      •2•0•0•0•Updated Feb 20, 2025Feb 20, 2025

    • panamax

      Public
      The Panamax 130-pin padframe for SkyWater sky130
      Verilog
      •
      Apache License 2.0
      •0•5•1•1•Updated Feb 20, 2025Feb 20, 2025

    • EF_GPIO8

      Public
      A generic 8-bit General Purpose I/O (GPIO) Peripheral
      Verilog
      •
      Apache License 2.0
      •1•1•1•1•Updated Feb 20, 2025Feb 20, 2025

    • EF_I2C

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•6•1•Updated Feb 20, 2025Feb 20, 2025

    • EF_QSPI_FLASH_WRITER

      Public
      Verilog
      •0•0•0•1•Updated Feb 20, 2025Feb 20, 2025

    • EF_PSRAM_CTRL

      Public
      Verilog
      •
      Apache License 2.0
      •0•1•3•2•Updated Feb 20, 2025Feb 20, 2025

    • EF_QSPI_XIP_CTRL

      Public
      A QSPI XiP Flash Controller with a Direct Mapped Cache
      Verilog
      •
      Apache License 2.0
      •0•1•3•1•Updated Feb 20, 2025Feb 20, 2025

    • EF_TMR32

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•2•1•Updated Feb 20, 2025Feb 20, 2025

    • BusWrap

      Public
      Python
      •0•5•6•0•Updated Feb 20, 2025Feb 20, 2025