From 9877af5eb6e28700adc32dc7229622e2afa618f1 Mon Sep 17 00:00:00 2001 From: AngelaGonzalezMarino <135128652+AngelaGonzalezMarino@users.noreply.github.com> Date: Tue, 3 Dec 2024 07:14:29 +0100 Subject: [PATCH 1/2] fix size of vectors when AxiNumWords=1 (#2639) in wt_axi_adapter, axi_rd_blen and axi_wr_blen are defined like this: logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen; However, if AxiNumWords=1, this gives a synthesis error. This happens if the cache line is set to 64 bits (same as AXI width). It can be fixed by changing to: logic [AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords-1:0] axi_rd_blen, axi_wr_blen; --- core/cache_subsystem/wt_axi_adapter.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 6c5fe585f8..9408fb8802 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -64,6 +64,7 @@ module wt_axi_adapter localparam MaxNumWords = $clog2(CVA6Cfg.AxiDataWidth / 8); localparam AxiRdBlenIcache = CVA6Cfg.ICACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1; localparam AxiRdBlenDcache = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1; + localparam AxiBlenWidth = AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords; /////////////////////////////////////////////////////// // request path @@ -82,7 +83,7 @@ module wt_axi_adapter logic axi_wr_valid, axi_rd_valid, axi_rd_rdy, axi_wr_rdy; logic axi_rd_lock, axi_wr_lock, axi_rd_exokay, axi_wr_exokay, wr_exokay; logic [CVA6Cfg.AxiAddrWidth-1:0] axi_rd_addr, axi_wr_addr; - logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen; + logic [AxiBlenWidth-1:0] axi_rd_blen, axi_wr_blen; logic [2:0] axi_rd_size, axi_wr_size; logic [CVA6Cfg.AxiIdWidth-1:0] axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out; @@ -170,14 +171,14 @@ module wt_axi_adapter // If dcache_data.size MSB is set, we want to read as much as possible axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size; if (dcache_data.size[2]) begin - axi_rd_blen = AxiRdBlenDcache[$clog2(AxiNumWords)-1:0]; + axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0]; end end else begin // Cast to AXI address width axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, icache_data.paddr}; axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill if (!icache_data.nc) begin - axi_rd_blen = AxiRdBlenIcache[$clog2(AxiNumWords)-1:0]; + axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0]; end end From b5b316ad1209ab7f8977429063481e181f007f65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= <61976467+ASintzoff@users.noreply.github.com> Date: Tue, 3 Dec 2024 07:43:05 +0100 Subject: [PATCH 2/2] doc: fix build (cva6_frontend.adoc) (#2644) use defined adoc variable --- .../design/design-manual/source/cva6_frontend.adoc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/design/design-manual/source/cva6_frontend.adoc b/docs/design/design-manual/source/cva6_frontend.adoc index dc6cb6bb36..ced4d04ffc 100644 --- a/docs/design/design-manual/source/cva6_frontend.adoc +++ b/docs/design/design-manual/source/cva6_frontend.adoc @@ -256,7 +256,7 @@ DECODE pops them when decode stage is ready and indicates to the FRONTEND the in The instruction queue contains two FIFOs: one for instructions and one for addresses, which stores addresses in case of a prediction. -The instruction FIFO can hold up to 4×{INSTR_PER_FETCH} instructions, while the address FIFO can hold up to 2 addresses. +The instruction FIFO can hold up to 4×{instr-per-fetch} instructions, while the address FIFO can hold up to 2 addresses. If the instruction FIFO is full, a replay request is sent to inform the fetch mechanism to replay the fetch. If the address FIFO is full and there is a prediction, a replay request is sent to inform the fetch mechanism to replay the fetch, even if the instruction FIFO is not full. @@ -285,23 +285,23 @@ BHT (Branch History Table) submodule The BHT is implemented as a memory which is composed of {BHTEntries} entries. The BHT is a two-dimensional table: -* The first dimension represents the access address, with a length equal to `{BHTEntries} / {INSTR_PER_FETCH}`. -* The second dimension represents the row index, with a length equal to `INSTR_PER_FETCH`. +* The first dimension represents the access address, with a length equal to `{BHTEntries} / {instr-per-fetch}`. +* The second dimension represents the row index, with a length equal to `{instr-per-fetch}`. In the case of branch prediction, the BHT uses only part of the virtual address to get the value of the saturation counter. In the case of a valid misprediction, the BHT uses only part of the misprediction address to access the BHT table and update the saturation counter. -'UPPER_ADDRESS_INDEX = $clog2(BHTDepth) + ((RVC == 1) ? 1 : 2)' +`UPPER_ADDRESS_INDEX = $clog2(BHTDepth) + ((RVC == 1) ? 1 : 2)` -'LOWER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 + $clog2(INSTR_PER_FETCH)' +`LOWER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 + $clog2(INSTR_PER_FETCH)` `ACCESS_ADDRESS = PC/MISPREDICT_ADDRESS [ UPPER_ADDRESS_INDEX : LOWER_ADDRESS_INDEX ]` The lower address bits of the virtual address point to the memory entry. -'UPPER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 + $clog2(INSTR_PER_FETCH)' +`UPPER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 + $clog2(INSTR_PER_FETCH)` -'LOWER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 + $clog2(INSTR_PER_FETCH)' +`LOWER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 + $clog2(INSTR_PER_FETCH)` `ACCESS_INDEX = PC/MISPREDICT_ADDRESS [ UPPER_ADDRESS_INDEX : LOWER_ADDRESS_INDEX]`