From ea8ed2d7a771d8f77575660665f94bd6caf6768d Mon Sep 17 00:00:00 2001 From: AFC Date: Mon, 11 Sep 2023 16:28:51 -0500 Subject: [PATCH 1/3] version updated --- voice_core/system.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/voice_core/system.v b/voice_core/system.v index 7e367e3..08f492d 100644 --- a/voice_core/system.v +++ b/voice_core/system.v @@ -29,7 +29,7 @@ module system #( parameter SYS_FREQ_HZ = 150_000_000 , parameter CLKFX_DIVIDE = 1 , parameter CLKFX_MULTIPLY = 3 , - parameter [ 63:0] VERSION = 64'hBAD2_6032_000A_0001 , + parameter [ 63:0] VERSION = 64'hBAD3_6032_000A_0001 , //Microphone Configuration parameter OUT_FREQ_HZ = 16_000 , parameter PDM_FREQ_HZ = 3_000_000 , /* this frequency must be multiple of 16000, 22000, 44000, 48000 Hz */ From d9e094639d2ff4517a3db5c00e0c5c5331060bac Mon Sep 17 00:00:00 2001 From: AFC Date: Mon, 11 Sep 2023 16:47:13 -0500 Subject: [PATCH 2/3] new pinout --- voice_core/rtl/wb_mic_array/cic.v | 2 +- voice_core/voice.ucf | 36 +++++++++++++++---------------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/voice_core/rtl/wb_mic_array/cic.v b/voice_core/rtl/wb_mic_array/cic.v index 882fe01..b61b6ef 100644 --- a/voice_core/rtl/wb_mic_array/cic.v +++ b/voice_core/rtl/wb_mic_array/cic.v @@ -54,7 +54,7 @@ always @(posedge clk or posedge resetn) begin pdm_data_reg <= {CHANNELS{1'b0}}; else begin if (pdm_read_enable) - pdm_data_reg <= pdm_data; + pdm_data_reg <= ~pdm_data; else pdm_data_reg <= pdm_data_reg; end diff --git a/voice_core/voice.ucf b/voice_core/voice.ucf index ab606f3..7774ffb 100644 --- a/voice_core/voice.ucf +++ b/voice_core/voice.ucf @@ -76,15 +76,15 @@ NET "dac_hp_nspk" LOC = "D1" | IOSTANDARD = LVCMOS33; ####################### # MIC ARRAY # ####################### -NET "pdm_clk" LOC = "B5" | IOSTANDARD = LVCMOS33; -NET "pdm_data<0>" LOC = "E6" | IOSTANDARD = LVCMOS33; -NET "pdm_data<1>" LOC = "B8" | IOSTANDARD = LVCMOS33; -NET "pdm_data<2>" LOC = "A8" | IOSTANDARD = LVCMOS33; -NET "pdm_data<3>" LOC = "C7" | IOSTANDARD = LVCMOS33; -NET "pdm_data<4>" LOC = "A7" | IOSTANDARD = LVCMOS33; -NET "pdm_data<5>" LOC = "A6" | IOSTANDARD = LVCMOS33; -NET "pdm_data<6>" LOC = "B6" | IOSTANDARD = LVCMOS33; -NET "pdm_data<7>" LOC = "A5" | IOSTANDARD = LVCMOS33; +NET "pdm_clk" LOC = "G1" | IOSTANDARD = LVCMOS33; +NET "pdm_data<0>" LOC = "G3" | IOSTANDARD = LVCMOS33; +NET "pdm_data<1>" LOC = "H1" | IOSTANDARD = LVCMOS33; +NET "pdm_data<2>" LOC = "H2" | IOSTANDARD = LVCMOS33; +NET "pdm_data<3>" LOC = "J1" | IOSTANDARD = LVCMOS33; +NET "pdm_data<4>" LOC = "J3" | IOSTANDARD = LVCMOS33; +NET "pdm_data<5>" LOC = "K1" | IOSTANDARD = LVCMOS33; +NET "pdm_data<6>" LOC = "K2" | IOSTANDARD = LVCMOS33; +NET "pdm_data<7>" LOC = "L1" | IOSTANDARD = LVCMOS33; NET "mic_irq<0>" LOC = "R7" | IOSTANDARD = LVCMOS33; #RPI_GPIO6 NET "mic_irq<1>" LOC = "H4" | IOSTANDARD = LVCMOS33; #ESP_IO5 @@ -99,12 +99,12 @@ NET "gpio_io<12>" LOC="P1" | IOSTANDARD = LVCMOS33; NET "gpio_io<11>" LOC="N1" | IOSTANDARD = LVCMOS33; NET "gpio_io<10>" LOC="M2" | IOSTANDARD = LVCMOS33; NET "gpio_io<9>" LOC="M1" | IOSTANDARD = LVCMOS33; -NET "gpio_io<8>" LOC="L1" | IOSTANDARD = LVCMOS33; -NET "gpio_io<7>" LOC="K2" | IOSTANDARD = LVCMOS33; -NET "gpio_io<6>" LOC="K1" | IOSTANDARD = LVCMOS33; -NET "gpio_io<5>" LOC="J3" | IOSTANDARD = LVCMOS33; -NET "gpio_io<4>" LOC="J1" | IOSTANDARD = LVCMOS33; -NET "gpio_io<3>" LOC="H2" | IOSTANDARD = LVCMOS33; -NET "gpio_io<2>" LOC="H1" | IOSTANDARD = LVCMOS33; -NET "gpio_io<1>" LOC="G3" | IOSTANDARD = LVCMOS33; -NET "gpio_io<0>" LOC="G1" | IOSTANDARD = LVCMOS33; \ No newline at end of file +NET "gpio_io<8>" LOC="A5" | IOSTANDARD = LVCMOS33; +NET "gpio_io<7>" LOC="B6" | IOSTANDARD = LVCMOS33; +NET "gpio_io<6>" LOC="A6" | IOSTANDARD = LVCMOS33; +NET "gpio_io<5>" LOC="A7" | IOSTANDARD = LVCMOS33; +NET "gpio_io<4>" LOC="C7" | IOSTANDARD = LVCMOS33; +NET "gpio_io<3>" LOC="A8" | IOSTANDARD = LVCMOS33; +NET "gpio_io<2>" LOC="B8" | IOSTANDARD = LVCMOS33; +NET "gpio_io<1>" LOC="E6" | IOSTANDARD = LVCMOS33; +NET "gpio_io<0>" LOC="B5" | IOSTANDARD = LVCMOS33; \ No newline at end of file From 4fc829f26eaa883347c7fe729d9421443fef9f44 Mon Sep 17 00:00:00 2001 From: AFC Date: Mon, 11 Sep 2023 20:34:50 -0500 Subject: [PATCH 3/3] neg clk --- voice_core/rtl/wb_mic_array/cic.v | 2 +- voice_core/rtl/wb_mic_array/cic_sync.v | 12 ++++++++---- voice_core/system.v | 2 +- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/voice_core/rtl/wb_mic_array/cic.v b/voice_core/rtl/wb_mic_array/cic.v index b61b6ef..882fe01 100644 --- a/voice_core/rtl/wb_mic_array/cic.v +++ b/voice_core/rtl/wb_mic_array/cic.v @@ -54,7 +54,7 @@ always @(posedge clk or posedge resetn) begin pdm_data_reg <= {CHANNELS{1'b0}}; else begin if (pdm_read_enable) - pdm_data_reg <= ~pdm_data; + pdm_data_reg <= pdm_data; else pdm_data_reg <= pdm_data_reg; end diff --git a/voice_core/rtl/wb_mic_array/cic_sync.v b/voice_core/rtl/wb_mic_array/cic_sync.v index 0da1854..387e658 100644 --- a/voice_core/rtl/wb_mic_array/cic_sync.v +++ b/voice_core/rtl/wb_mic_array/cic_sync.v @@ -38,7 +38,7 @@ module cic_sync #( input [$clog2(CHANNELS)-1:0] channel, input cic_finish, - output reg pdm_clk, + output pdm_clk, output reg read_enable, output reg integrator_enable, output comb_enable @@ -62,6 +62,10 @@ module cic_sync #( reg [2:0] state; + reg pdm_clk_reg; + + assign pdm_clk = ~pdm_clk_reg; + always @(state) begin case(state) S_IDLE : @@ -122,12 +126,12 @@ module cic_sync #( always @(posedge clk or posedge resetn) begin if (resetn | pdm_conndition) - pdm_clk <= 1'b1; + pdm_clk_reg <= 1'b1; else begin if (sys_count == pdm_half_ratio) - pdm_clk <= 1'b0; + pdm_clk_reg <= 1'b0; else - pdm_clk <= pdm_clk; + pdm_clk_reg <= pdm_clk_reg; end end diff --git a/voice_core/system.v b/voice_core/system.v index 08f492d..c521a74 100644 --- a/voice_core/system.v +++ b/voice_core/system.v @@ -29,7 +29,7 @@ module system #( parameter SYS_FREQ_HZ = 150_000_000 , parameter CLKFX_DIVIDE = 1 , parameter CLKFX_MULTIPLY = 3 , - parameter [ 63:0] VERSION = 64'hBAD3_6032_000A_0001 , + parameter [ 63:0] VERSION = 64'hBAD4_6032_000A_0001 , //Microphone Configuration parameter OUT_FREQ_HZ = 16_000 , parameter PDM_FREQ_HZ = 3_000_000 , /* this frequency must be multiple of 16000, 22000, 44000, 48000 Hz */