diff --git a/voice_core/rtl/wb_mic_array/cic_sync.v b/voice_core/rtl/wb_mic_array/cic_sync.v
index 0da1854..387e658 100644
--- a/voice_core/rtl/wb_mic_array/cic_sync.v
+++ b/voice_core/rtl/wb_mic_array/cic_sync.v
@@ -38,7 +38,7 @@ module cic_sync #(
   input [$clog2(CHANNELS)-1:0] channel,
 
   input cic_finish,
-  output reg pdm_clk,
+  output pdm_clk,
   output reg read_enable,
   output reg integrator_enable,
   output comb_enable
@@ -62,6 +62,10 @@ module cic_sync #(
 
   reg [2:0] state;
 
+  reg pdm_clk_reg;
+
+  assign pdm_clk = ~pdm_clk_reg;
+
   always @(state) begin
     case(state)
       S_IDLE :
@@ -122,12 +126,12 @@ module cic_sync #(
 
   always @(posedge clk or posedge resetn) begin
     if (resetn | pdm_conndition)
-      pdm_clk <= 1'b1;
+      pdm_clk_reg <= 1'b1;
     else begin
       if (sys_count == pdm_half_ratio)
-        pdm_clk <= 1'b0;
+        pdm_clk_reg <= 1'b0;
       else
-        pdm_clk <= pdm_clk;
+        pdm_clk_reg <= pdm_clk_reg;
     end
   end
 
diff --git a/voice_core/system.v b/voice_core/system.v
index 7e367e3..c521a74 100644
--- a/voice_core/system.v
+++ b/voice_core/system.v
@@ -29,7 +29,7 @@ module system #(
   parameter                  SYS_FREQ_HZ       = 150_000_000                     ,
   parameter                  CLKFX_DIVIDE      = 1                               ,
   parameter                  CLKFX_MULTIPLY    = 3                               ,
-  parameter [          63:0] VERSION           = 64'hBAD2_6032_000A_0001         ,
+  parameter [          63:0] VERSION           = 64'hBAD4_6032_000A_0001         ,
   //Microphone Configuration
   parameter                  OUT_FREQ_HZ       = 16_000                          ,
   parameter                  PDM_FREQ_HZ       = 3_000_000                       , /* this frequency must be multiple of 16000, 22000, 44000, 48000 Hz */
diff --git a/voice_core/voice.ucf b/voice_core/voice.ucf
index ab606f3..7774ffb 100644
--- a/voice_core/voice.ucf
+++ b/voice_core/voice.ucf
@@ -76,15 +76,15 @@ NET "dac_hp_nspk"       LOC = "D1"  | IOSTANDARD = LVCMOS33;
 #######################
 # MIC ARRAY           #
 #######################
-NET "pdm_clk"      LOC = "B5"  | IOSTANDARD = LVCMOS33;
-NET "pdm_data<0>"  LOC = "E6"  | IOSTANDARD = LVCMOS33;
-NET "pdm_data<1>"  LOC = "B8"  | IOSTANDARD = LVCMOS33;
-NET "pdm_data<2>"  LOC = "A8"  | IOSTANDARD = LVCMOS33;
-NET "pdm_data<3>"  LOC = "C7"  | IOSTANDARD = LVCMOS33;
-NET "pdm_data<4>"  LOC = "A7"  | IOSTANDARD = LVCMOS33;
-NET "pdm_data<5>"  LOC = "A6"  | IOSTANDARD = LVCMOS33;
-NET "pdm_data<6>"  LOC = "B6"  | IOSTANDARD = LVCMOS33;
-NET "pdm_data<7>"  LOC = "A5"  | IOSTANDARD = LVCMOS33;
+NET "pdm_clk"      LOC = "G1"  | IOSTANDARD = LVCMOS33;
+NET "pdm_data<0>"  LOC = "G3"  | IOSTANDARD = LVCMOS33;
+NET "pdm_data<1>"  LOC = "H1"  | IOSTANDARD = LVCMOS33;
+NET "pdm_data<2>"  LOC = "H2"  | IOSTANDARD = LVCMOS33;
+NET "pdm_data<3>"  LOC = "J1"  | IOSTANDARD = LVCMOS33;
+NET "pdm_data<4>"  LOC = "J3"  | IOSTANDARD = LVCMOS33;
+NET "pdm_data<5>"  LOC = "K1"  | IOSTANDARD = LVCMOS33;
+NET "pdm_data<6>"  LOC = "K2"  | IOSTANDARD = LVCMOS33;
+NET "pdm_data<7>"  LOC = "L1"  | IOSTANDARD = LVCMOS33;
 NET "mic_irq<0>"   LOC = "R7"  | IOSTANDARD = LVCMOS33; #RPI_GPIO6
 NET "mic_irq<1>"   LOC = "H4"  | IOSTANDARD = LVCMOS33; #ESP_IO5
 
@@ -99,12 +99,12 @@ NET "gpio_io<12>" LOC="P1" | IOSTANDARD = LVCMOS33;
 NET "gpio_io<11>" LOC="N1" | IOSTANDARD = LVCMOS33;
 NET "gpio_io<10>" LOC="M2" | IOSTANDARD = LVCMOS33;
 NET "gpio_io<9>"  LOC="M1" | IOSTANDARD = LVCMOS33;
-NET "gpio_io<8>"  LOC="L1" | IOSTANDARD = LVCMOS33;
-NET "gpio_io<7>"  LOC="K2" | IOSTANDARD = LVCMOS33;
-NET "gpio_io<6>"  LOC="K1" | IOSTANDARD = LVCMOS33;
-NET "gpio_io<5>"  LOC="J3" | IOSTANDARD = LVCMOS33;
-NET "gpio_io<4>"  LOC="J1" | IOSTANDARD = LVCMOS33;
-NET "gpio_io<3>"  LOC="H2" | IOSTANDARD = LVCMOS33;
-NET "gpio_io<2>"  LOC="H1" | IOSTANDARD = LVCMOS33;
-NET "gpio_io<1>"  LOC="G3" | IOSTANDARD = LVCMOS33;
-NET "gpio_io<0>"  LOC="G1" | IOSTANDARD = LVCMOS33;
\ No newline at end of file
+NET "gpio_io<8>"  LOC="A5" | IOSTANDARD = LVCMOS33;
+NET "gpio_io<7>"  LOC="B6" | IOSTANDARD = LVCMOS33;
+NET "gpio_io<6>"  LOC="A6" | IOSTANDARD = LVCMOS33;
+NET "gpio_io<5>"  LOC="A7" | IOSTANDARD = LVCMOS33;
+NET "gpio_io<4>"  LOC="C7" | IOSTANDARD = LVCMOS33;
+NET "gpio_io<3>"  LOC="A8" | IOSTANDARD = LVCMOS33;
+NET "gpio_io<2>"  LOC="B8" | IOSTANDARD = LVCMOS33;
+NET "gpio_io<1>"  LOC="E6" | IOSTANDARD = LVCMOS33;
+NET "gpio_io<0>"  LOC="B5" | IOSTANDARD = LVCMOS33;
\ No newline at end of file