diff --git a/.github/workflows/Openwrt-AutoBuild.yml b/.github/workflows/Openwrt-AutoBuild.yml index d0d176fc4a80..d91515bf8240 100644 --- a/.github/workflows/Openwrt-AutoBuild.yml +++ b/.github/workflows/Openwrt-AutoBuild.yml @@ -147,12 +147,13 @@ jobs: - name: Clone source code run: | + set -x TAG_INFO="$(curl -gs -H 'Content-Type: application/json' \ -H "Authorization: Bearer ${{ secrets.TOKEN_KIDDIN9 }}" \ -X POST -d '{ "query": "query {repository(owner: \"openwrt\", name: \"openwrt\") {refs(refPrefix: \"refs/tags/\", first: 4, orderBy: {field: TAG_COMMIT_DATE, direction: DESC}) {nodes {name target { ... on Tag {tagger {date}}}}}}}"}' https://api.github.com/graphql)" - TAG_DATE="$( echo ${TAG_INFO} | jq -r '.data.repository.refs.nodes[] | select(.name | startswith("v23")) | .target.tagger.date' | head -n 1)" + TAG_DATE="$( echo ${TAG_INFO} | jq -r '.data.repository.refs.nodes[] | select(.name | startswith("v24")) | .target.tagger.date' | head -n 1)" if [[ $(( ($(date +%s) - $(date -d "$TAG_DATE" +%s)) / 86400 )) -lt 30 ]]; then - REPO_BRANCH="$( echo ${TAG_INFO} | jq -r '.data.repository.refs.nodes[].name' | grep v23 | head -n 1)" + REPO_BRANCH="$( echo ${TAG_INFO} | jq -r '.data.repository.refs.nodes[].name' | grep v24 | head -n 1)" else REPO_BRANCH="openwrt-24.10" fi diff --git a/devices/amlogic_meson8b/patches/BRCMFMAC_SDIO.patch b/devices/amlogic_meson8b/patches/BRCMFMAC_SDIO.patch index a4fc04f67e3b..79be18f5ee9a 100644 --- a/devices/amlogic_meson8b/patches/BRCMFMAC_SDIO.patch +++ b/devices/amlogic_meson8b/patches/BRCMFMAC_SDIO.patch @@ -1,10 +1,10 @@ --- a/package/kernel/mac80211/broadcom.mk +++ b/package/kernel/mac80211/broadcom.mk -@@ -437,6 +437,7 @@ define KernelPackage/brcmfmac/config - default y if TARGET_starfive - default y if TARGET_rockchip - default y if TARGET_sunxi +@@ -432,6 +432,7 @@ define KernelPackage/brcmfmac/config + + config BRCMFMAC_SDIO + bool "Enable SDIO bus interface support" + default y if TARGET_amlogic - default n - help - Enable support for cards attached to an SDIO bus. \ No newline at end of file + default y if TARGET_bcm27xx + default y if TARGET_imx_cortexa7 + default y if TARGET_starfive diff --git a/devices/common/.config b/devices/common/.config index 00b3c739db72..5e851d0461cd 100644 --- a/devices/common/.config +++ b/devices/common/.config @@ -8,6 +8,9 @@ CONFIG_LUCI_CSSTIDY=n CONFIG_SIGNED_PACKAGES=n CONFIG_SIGNATURE_CHECK=n +CONFIG_TARGET_MULTI_PROFILE=y +CONFIG_TARGET_ALL_PROFILES=y + # 设置固件大小: CONFIG_TARGET_ROOTFS_PARTSIZE=1004 @@ -15,6 +18,8 @@ CONFIG_ALL_NONSHARED=y CONFIG_USE_APK=n +CONFIG_BUILD_PATENTED=y + CONFIG_IB=y CONFIG_IB_STANDALONE=y CONFIG_JSON_OVERVIEW_IMAGE_INFO=y @@ -33,6 +38,7 @@ CONFIG_IPV6=y CONFIG_PACKAGE_luci-theme-bootstrap=y +CONFIG_PACKAGE_procd-seccomp=n # 其他需要安装的软件包: diff --git a/devices/common/diy.sh b/devices/common/diy.sh index 7bed143830e5..0810cd9f523a 100644 --- a/devices/common/diy.sh +++ b/devices/common/diy.sh @@ -13,17 +13,29 @@ sed -i '/ refresh_config();/d' scripts/feeds ./scripts/feeds install -a -p kiddin9 -f ./scripts/feeds install -a -rm -rf package/base-files -mv -f feeds/kiddin9/base-files package/ +sed -i "/DISTRIB_DESCRIPTION/c\DISTRIB_DESCRIPTION=\"%D %C by Kiddin'\"" package/base-files/files/etc/openwrt_release +sed -i -e '$a /etc/bench.log' \ + -e '/\/etc\/profile/d' \ + -e '/\/etc\/shinit/d' \ + package/base-files/files/lib/upgrade/keep.d/base-files-essential +sed -i -e '/^\/etc\/profile/d' \ + -e '/^\/etc\/shinit/d' \ + package/base-files/Makefile +sed -i "s/192.168.1/10.0.0/" package/base-files/files/bin/config_generate + +wget -N https://github.com/immortalwrt/immortalwrt/raw/refs/heads/openwrt-24.10/package/network/utils/nftables/patches/002-nftables-add-fullcone-expression-support.patch -P package/network/utils/nftables/patches/ +wget -N https://github.com/immortalwrt/immortalwrt/raw/refs/heads/openwrt-24.10/package/network/utils/nftables/patches/001-drop-useless-file.patch -P package/network/utils/nftables/patches/ +wget -N https://github.com/immortalwrt/immortalwrt/raw/refs/heads/openwrt-24.10/package/system/fstools/patches/100-fstools-support-extroot-for-non-MTD-rootfs_data.patch -P package/system/fstools/patches/ +wget -N https://github.com/immortalwrt/immortalwrt/raw/refs/heads/openwrt-24.10/package/libs/libnftnl/patches/001-libnftnl-add-fullcone-expression-support.patch -P package/libs/libnftnl/patches/ +wget -N https://github.com/immortalwrt/immortalwrt/raw/refs/heads/openwrt-24.10/package/firmware/wireless-regdb/patches/600-custom-change-txpower-and-dfs.patch -P package/firmware/wireless-regdb/patches/ echo "$(date +"%s")" >version.date sed -i '/$(curdir)\/compile:/c\$(curdir)/compile: package/opkg/host/compile' package/Makefile sed -i "s/DEFAULT_PACKAGES:=/DEFAULT_PACKAGES:=luci-app-advancedplus luci-app-firewall luci-app-package-manager luci-app-upnp luci-app-syscontrol \ luci-app-wizard luci-base luci-compat luci-lib-ipkg luci-lib-fs \ -coremark wget-ssl curl autocore htop nano zram-swap kmod-lib-zstd kmod-tcp-bbr bash openssh-sftp-server block-mount resolveip ds-lite swconfig luci-app-fan luci-app-fileassistant /" include/target.mk +coremark wget-ssl curl autocore htop nano zram-swap kmod-lib-zstd kmod-tcp-bbr bash openssh-sftp-server block-mount resolveip ds-lite swconfig luci-app-fan luci-app-filemanager /" include/target.mk sed -i "s/procd-ujail//" include/target.mk -sed -i "s/procd-seccomp//" include/target.mk sed -i "s/^.*vermagic$/\techo '1' > \$(LINUX_DIR)\/.vermagic/" include/kernel-defaults.mk @@ -39,18 +51,15 @@ mv -f feeds/kiddin9/r81* tmp/ wget -N https://raw.githubusercontent.com/openwrt/packages/master/lang/golang/golang/Makefile -P feeds/packages/lang/golang/golang/ -sed -i "s/192.168.1/10.0.0/" package/base-files/files/bin/config_generate - #sed -i "/call Build\/check-size,\$\$(KERNEL_SIZE)/d" include/image.mk -wget -N https://github.com/openwrt/openwrt/raw/refs/heads/main/package/kernel/linux/modules/video.mk -P package/kernel/linux/modules/ - git_clone_path master https://github.com/coolsnowwolf/lede mv target/linux/generic/hack-6.6 rm -rf target/linux/generic/hack-6.6/929-Revert-genetlink* wget -N https://raw.githubusercontent.com/coolsnowwolf/lede/master/target/linux/generic/pending-6.6/613-netfilter_optional_tcp_window_check.patch -P target/linux/generic/pending-6.6/ +wget -N https://patch-diff.githubusercontent.com/raw/openwrt/openwrt/pull/16414.patch -P devices/common/patches/ + sed -i "/mediaurlbase/d" package/feeds/*/luci-theme*/root/etc/uci-defaults/* -sed -i 's/=bbr/=cubic/' package/kernel/linux/files/sysctl-tcp-bbr.conf # find target/linux/x86 -name "config*" -exec bash -c 'cat kernel.conf >> "{}"' \; sed -i 's/max_requests 3/max_requests 20/g' package/network/services/uhttpd/files/uhttpd.config diff --git a/devices/common/diy/package/base-files/files/etc/banner b/devices/common/diy/package/base-files/files/etc/banner new file mode 100644 index 000000000000..88a28a6288b3 --- /dev/null +++ b/devices/common/diy/package/base-files/files/etc/banner @@ -0,0 +1,6 @@ + + |\__/,| (`\ + _.|o o |_ ) ) + -------------(((---(((------------------- + %D %C by Kiddin' + ----------------------------------------- diff --git a/devices/common/diy/package/network/config/firewall/files/firewall.exwan b/devices/common/diy/package/network/config/firewall/files/firewall.exwan new file mode 100644 index 000000000000..e087ff4840c0 --- /dev/null +++ b/devices/common/diy/package/network/config/firewall/files/firewall.exwan @@ -0,0 +1,183 @@ +#!/bin/sh + +# UCI 配置操作函数 +config_get() { uci -q get "$1"; } +config_set() { uci set "$1=$2"; } +config_add_list() { uci add_list "$1=$2"; } +config_delete() { uci -q delete "$1"; } +config_commit() { uci commit "$1"; } + +# 检查列表是否包含元素 +list_contains() { + local value="$1"; shift + echo "$@" | grep -q -w "$value" +} + +# 从列表中移除元素 +list_remove() { + local value="$1" + local list="$2" + echo "$list" | sed "s/\<$value\>//g" | xargs +} + +# 更新 SSH 和 TTYD 配置 +update_ssh_ttyd() { + if [ "$(config_get "firewall.@defaults[0].ex_ssh")" = "1" ]; then + if [ -n "$(config_get "dropbear.@dropbear[0].GatewayPorts")" ]; then + config_set "dropbear.@dropbear[0].GatewayPorts" "on" + config_commit "dropbear" + service dropbear reload & + fi + if command -v ttyd >/dev/null 2>&1; then + [ "$(config_get "ttyd.@ttyd[0].interface")" != "@lan" ] && config_set "ttyd.@ttyd[0].interface" "@lan" + if [ "$(config_get "firewall.@defaults[0].family")" = "ipv4" ]; then + config_set "ttyd.@ttyd[0].ipv6" "0" + else + config_set "ttyd.@ttyd[0].ipv6" "1" + fi + config_commit "ttyd" + service ttyd reload & + fi + fi +} + +# 更新防火墙规则 +update_firewall_rule() { + local port="$1" + local is_backend_port="$2" + local rule="firewall.ex_$port" + local family=$(config_get "firewall.@defaults[0].family") + local proto=$(config_get "firewall.@defaults[0].proto") + + config_set "$rule" "rule" + config_set "$rule.name" "ex_$port" + config_set "$rule.src" "wan" + config_set "$rule.dest_port" "$port" + config_set "$rule.target" "ACCEPT" + + [ "$family" = "ipv4" ] && config_set "$rule.family" "ipv4" || config_set "$rule.family" "ipv6" + + if [ "$is_backend_port" = "1" ]; then + config_add_list "$rule.proto" "tcp" + else + case "$proto" in + udp) config_add_list "$rule.proto" "udp" ;; + tudp) + config_add_list "$rule.proto" "tcp" + config_add_list "$rule.proto" "udp" + ;; + *) config_add_list "$rule.proto" "tcp" ;; + esac + fi +} + +# 删除所有以前生成的 config rule +remove_all_ex_rules() { + local rules=$(uci show firewall | grep "\.name='ex_" | cut -d. -f2) + for rule in $rules; do + config_delete "firewall.$rule" + done +} + +# 更新 export 配置 +update_export() { + local export=$(config_get "firewall.@defaults[0].export") + local ex_ssh=$(config_get "firewall.@defaults[0].ex_ssh") + local sshport=$(config_get "dropbear.@dropbear[0].Port") + + # 处理 SSH 端口 + if [ "$ex_ssh" = "1" ]; then + if ! list_contains "$sshport" $export; then + export="$export $sshport" + fi + else + export=$(list_remove "$sshport" "$export") + fi + + config_set "firewall.@defaults[0].export" "$export" + + remove_all_ex_rules + + # 添加新的规则 + for port in $export; do + update_firewall_rule "$port" "0" + done +} + +# 更新 uhttpd 配置 +update_uhttpd() { + local backend_port="$1" + local old_backend_port="$2" + local use_https=$(config_get "uhttpd.main.redirect_https") + + uci -q del_list uhttpd.main.listen_http="0.0.0.0:$old_backend_port" + uci -q del_list uhttpd.main.listen_http="[::]:$old_backend_port" + uci -q del_list uhttpd.main.listen_https="0.0.0.0:$old_backend_port" + uci -q del_list uhttpd.main.listen_https="[::]:$old_backend_port" + + if [ -n "$backend_port" ]; then + if [ "$use_https" = "1" ]; then + config_add_list "uhttpd.main.listen_https" "0.0.0.0:$backend_port" + config_add_list "uhttpd.main.listen_https" "[::]:$backend_port" + else + config_add_list "uhttpd.main.listen_http" "0.0.0.0:$backend_port" + config_add_list "uhttpd.main.listen_http" "[::]:$backend_port" + fi + fi + config_commit "uhttpd" +} + +# 更新 nginx 配置 +update_nginx() { + local backend_port="$1" + local old_backend_port="$2" + local use_https=$(uci show nginx | grep -q "_redirect2ssl" && echo "1" || echo "0") + + config_delete "nginx.ex_$old_backend_port" + + if [ -n "$backend_port" ]; then + config_set "nginx.ex_$backend_port" "server" + config_set "nginx.ex_$backend_port.server_name" "ex_$backend_port" + config_add_list "nginx.ex_$backend_port.include" "conf.d/*.locations" + config_set "nginx.ex_$backend_port.access_log" "off" + if [ "$use_https" = "1" ]; then + config_add_list "nginx.ex_$backend_port.listen" "$backend_port ssl" + config_add_list "nginx.ex_$backend_port.listen" "[::]:$backend_port ssl" + if [ ! "$(config_get "nginx.ex_$backend_port.ssl_certificate")" ]; then + config_set "nginx.ex_$backend_port.ssl_certificate" "/etc/nginx/conf.d/_lan.crt" + config_set "nginx.ex_$backend_port.ssl_certificate_key" "/etc/nginx/conf.d/_lan.key" + fi + else + config_add_list "nginx.ex_$backend_port.listen" "$backend_port" + config_add_list "nginx.ex_$backend_port.listen" "[::]:$backend_port" + fi + fi + + config_commit "nginx" +} + +# 主逻辑 +main() { + local backend_port=$(config_get "firewall.@defaults[0].backend_port") + local old_backend_port=$(config_get "firewall.@defaults[0].old_backend_port") + + update_ssh_ttyd + update_export + + if [ "$backend_port" != "$old_backend_port" ]; then + if pgrep nginx >/dev/null; then + update_nginx "$backend_port" "$old_backend_port" + /etc/init.d/nginx reload & + elif pgrep uhttpd >/dev/null; then + update_uhttpd "$backend_port" "$old_backend_port" + /etc/init.d/uhttpd reload & + fi + config_set "firewall.@defaults[0].old_backend_port" "$backend_port" + fi + + [ -n "$backend_port" ] && update_firewall_rule "$backend_port" "1" + + config_commit "firewall" +} + +main diff --git a/devices/common/diy/package/network/config/firewall/patches/fullconenat.patch b/devices/common/diy/package/network/config/firewall/patches/fullconenat.patch new file mode 100644 index 000000000000..d69e7129ec7e --- /dev/null +++ b/devices/common/diy/package/network/config/firewall/patches/fullconenat.patch @@ -0,0 +1,63 @@ +index 85a3750..9fac9b1 100644 +--- a/defaults.c ++++ b/defaults.c +@@ -46,7 +46,9 @@ const struct fw3_option fw3_flag_opts[] = { + FW3_OPT("synflood_protect", bool, defaults, syn_flood), + FW3_OPT("synflood_rate", limit, defaults, syn_flood_rate), + FW3_OPT("synflood_burst", int, defaults, syn_flood_rate.burst), +- ++ ++ FW3_OPT("fullcone", bool, defaults, fullcone), ++ + FW3_OPT("tcp_syncookies", bool, defaults, tcp_syncookies), + FW3_OPT("tcp_ecn", int, defaults, tcp_ecn), + FW3_OPT("tcp_window_scaling", bool, defaults, tcp_window_scaling), +diff --git a/options.h b/options.h +index 6edd174..c02eb97 100644 +--- a/options.h ++++ b/options.h +@@ -267,6 +267,7 @@ struct fw3_defaults + bool drop_invalid; + + bool syn_flood; ++ bool fullcone; + struct fw3_limit syn_flood_rate; + + bool tcp_syncookies; +diff --git a/zones.c b/zones.c +index 2aa7473..57eead0 100644 +--- a/zones.c ++++ b/zones.c +@@ -627,6 +627,7 @@ print_zone_rule(struct fw3_ipt_handle *h + struct fw3_address *msrc; + struct fw3_address *mdest; + struct fw3_ipt_rule *r; ++ struct fw3_defaults *defs = &state->defaults; + + if (!fw3_is_family(zone, handle->family)) + return; +@@ -712,8 +713,22 @@ print_zone_rule(struct fw3_ipt_handle *h + { + r = fw3_ipt_rule_new(handle); + fw3_ipt_rule_src_dest(r, msrc, mdest); +- fw3_ipt_rule_target(r, "MASQUERADE"); +- fw3_ipt_rule_append(r, "zone_%s_postrouting", zone->name); ++ /*FIXME: Workaround for FULLCONE-NAT*/ ++ if(defs->fullcone) ++ { ++ warn("%s will enable FULLCONE-NAT", zone->name); ++ fw3_ipt_rule_target(r, "FULLCONENAT"); ++ fw3_ipt_rule_append(r, "zone_%s_postrouting", zone->name); ++ r = fw3_ipt_rule_new(handle); ++ fw3_ipt_rule_src_dest(r, msrc, mdest); ++ fw3_ipt_rule_target(r, "FULLCONENAT"); ++ fw3_ipt_rule_append(r, "zone_%s_prerouting", zone->name); ++ } ++ else ++ { ++ fw3_ipt_rule_target(r, "MASQUERADE"); ++ fw3_ipt_rule_append(r, "zone_%s_postrouting", zone->name); ++ } + } + } + } diff --git a/devices/common/diy/package/network/config/firewall4/files/firewall.exwan b/devices/common/diy/package/network/config/firewall4/files/firewall.exwan new file mode 100644 index 000000000000..e087ff4840c0 --- /dev/null +++ b/devices/common/diy/package/network/config/firewall4/files/firewall.exwan @@ -0,0 +1,183 @@ +#!/bin/sh + +# UCI 配置操作函数 +config_get() { uci -q get "$1"; } +config_set() { uci set "$1=$2"; } +config_add_list() { uci add_list "$1=$2"; } +config_delete() { uci -q delete "$1"; } +config_commit() { uci commit "$1"; } + +# 检查列表是否包含元素 +list_contains() { + local value="$1"; shift + echo "$@" | grep -q -w "$value" +} + +# 从列表中移除元素 +list_remove() { + local value="$1" + local list="$2" + echo "$list" | sed "s/\<$value\>//g" | xargs +} + +# 更新 SSH 和 TTYD 配置 +update_ssh_ttyd() { + if [ "$(config_get "firewall.@defaults[0].ex_ssh")" = "1" ]; then + if [ -n "$(config_get "dropbear.@dropbear[0].GatewayPorts")" ]; then + config_set "dropbear.@dropbear[0].GatewayPorts" "on" + config_commit "dropbear" + service dropbear reload & + fi + if command -v ttyd >/dev/null 2>&1; then + [ "$(config_get "ttyd.@ttyd[0].interface")" != "@lan" ] && config_set "ttyd.@ttyd[0].interface" "@lan" + if [ "$(config_get "firewall.@defaults[0].family")" = "ipv4" ]; then + config_set "ttyd.@ttyd[0].ipv6" "0" + else + config_set "ttyd.@ttyd[0].ipv6" "1" + fi + config_commit "ttyd" + service ttyd reload & + fi + fi +} + +# 更新防火墙规则 +update_firewall_rule() { + local port="$1" + local is_backend_port="$2" + local rule="firewall.ex_$port" + local family=$(config_get "firewall.@defaults[0].family") + local proto=$(config_get "firewall.@defaults[0].proto") + + config_set "$rule" "rule" + config_set "$rule.name" "ex_$port" + config_set "$rule.src" "wan" + config_set "$rule.dest_port" "$port" + config_set "$rule.target" "ACCEPT" + + [ "$family" = "ipv4" ] && config_set "$rule.family" "ipv4" || config_set "$rule.family" "ipv6" + + if [ "$is_backend_port" = "1" ]; then + config_add_list "$rule.proto" "tcp" + else + case "$proto" in + udp) config_add_list "$rule.proto" "udp" ;; + tudp) + config_add_list "$rule.proto" "tcp" + config_add_list "$rule.proto" "udp" + ;; + *) config_add_list "$rule.proto" "tcp" ;; + esac + fi +} + +# 删除所有以前生成的 config rule +remove_all_ex_rules() { + local rules=$(uci show firewall | grep "\.name='ex_" | cut -d. -f2) + for rule in $rules; do + config_delete "firewall.$rule" + done +} + +# 更新 export 配置 +update_export() { + local export=$(config_get "firewall.@defaults[0].export") + local ex_ssh=$(config_get "firewall.@defaults[0].ex_ssh") + local sshport=$(config_get "dropbear.@dropbear[0].Port") + + # 处理 SSH 端口 + if [ "$ex_ssh" = "1" ]; then + if ! list_contains "$sshport" $export; then + export="$export $sshport" + fi + else + export=$(list_remove "$sshport" "$export") + fi + + config_set "firewall.@defaults[0].export" "$export" + + remove_all_ex_rules + + # 添加新的规则 + for port in $export; do + update_firewall_rule "$port" "0" + done +} + +# 更新 uhttpd 配置 +update_uhttpd() { + local backend_port="$1" + local old_backend_port="$2" + local use_https=$(config_get "uhttpd.main.redirect_https") + + uci -q del_list uhttpd.main.listen_http="0.0.0.0:$old_backend_port" + uci -q del_list uhttpd.main.listen_http="[::]:$old_backend_port" + uci -q del_list uhttpd.main.listen_https="0.0.0.0:$old_backend_port" + uci -q del_list uhttpd.main.listen_https="[::]:$old_backend_port" + + if [ -n "$backend_port" ]; then + if [ "$use_https" = "1" ]; then + config_add_list "uhttpd.main.listen_https" "0.0.0.0:$backend_port" + config_add_list "uhttpd.main.listen_https" "[::]:$backend_port" + else + config_add_list "uhttpd.main.listen_http" "0.0.0.0:$backend_port" + config_add_list "uhttpd.main.listen_http" "[::]:$backend_port" + fi + fi + config_commit "uhttpd" +} + +# 更新 nginx 配置 +update_nginx() { + local backend_port="$1" + local old_backend_port="$2" + local use_https=$(uci show nginx | grep -q "_redirect2ssl" && echo "1" || echo "0") + + config_delete "nginx.ex_$old_backend_port" + + if [ -n "$backend_port" ]; then + config_set "nginx.ex_$backend_port" "server" + config_set "nginx.ex_$backend_port.server_name" "ex_$backend_port" + config_add_list "nginx.ex_$backend_port.include" "conf.d/*.locations" + config_set "nginx.ex_$backend_port.access_log" "off" + if [ "$use_https" = "1" ]; then + config_add_list "nginx.ex_$backend_port.listen" "$backend_port ssl" + config_add_list "nginx.ex_$backend_port.listen" "[::]:$backend_port ssl" + if [ ! "$(config_get "nginx.ex_$backend_port.ssl_certificate")" ]; then + config_set "nginx.ex_$backend_port.ssl_certificate" "/etc/nginx/conf.d/_lan.crt" + config_set "nginx.ex_$backend_port.ssl_certificate_key" "/etc/nginx/conf.d/_lan.key" + fi + else + config_add_list "nginx.ex_$backend_port.listen" "$backend_port" + config_add_list "nginx.ex_$backend_port.listen" "[::]:$backend_port" + fi + fi + + config_commit "nginx" +} + +# 主逻辑 +main() { + local backend_port=$(config_get "firewall.@defaults[0].backend_port") + local old_backend_port=$(config_get "firewall.@defaults[0].old_backend_port") + + update_ssh_ttyd + update_export + + if [ "$backend_port" != "$old_backend_port" ]; then + if pgrep nginx >/dev/null; then + update_nginx "$backend_port" "$old_backend_port" + /etc/init.d/nginx reload & + elif pgrep uhttpd >/dev/null; then + update_uhttpd "$backend_port" "$old_backend_port" + /etc/init.d/uhttpd reload & + fi + config_set "firewall.@defaults[0].old_backend_port" "$backend_port" + fi + + [ -n "$backend_port" ] && update_firewall_rule "$backend_port" "1" + + config_commit "firewall" +} + +main diff --git a/devices/common/diy/package/network/config/firewall4/files/firewall.include b/devices/common/diy/package/network/config/firewall4/files/firewall.include new file mode 100644 index 000000000000..8b137891791f --- /dev/null +++ b/devices/common/diy/package/network/config/firewall4/files/firewall.include @@ -0,0 +1 @@ + diff --git a/devices/common/diy/package/network/config/firewall4/patches/001-firewall4-add-support-for-fullcone-nat.patch b/devices/common/diy/package/network/config/firewall4/patches/001-firewall4-add-support-for-fullcone-nat.patch new file mode 100644 index 000000000000..9f34b1eefd25 --- /dev/null +++ b/devices/common/diy/package/network/config/firewall4/patches/001-firewall4-add-support-for-fullcone-nat.patch @@ -0,0 +1,216 @@ +From aa3b56e289fba7425e649a608c333622ffd9c367 Mon Sep 17 00:00:00 2001 +From: Syrone Wong +Date: Sat, 9 Apr 2022 13:24:19 +0800 +Subject: [PATCH] firewall4: add fullcone support + +fullcone is drop-in replacement of masq for non-udp traffic + +add runtime fullcone rule check, disable it globally if fullcone expr is +invalid + +defaults.fullcone and defaults.fullcone6 are switches for IPv4 and IPv6 +respectively, most IPv6 traffic do NOT need this FullCone NAT functionality. + +Renew: ZiMing Mo +--- + root/etc/config/firewall | 2 ++ + root/usr/share/firewall4/templates/ruleset.uc | 16 ++++++++++++++-- + .../firewall4/templates/zone-fullcone.uc | 4 ++++ + root/usr/share/ucode/fw4.uc | 69 ++++++++++++++++++- + 4 files changed, 89 insertions(+), 4 deletions(-) + create mode 100644 root/usr/share/firewall4/templates/zone-fullcone.uc + +--- a/root/etc/config/firewall ++++ b/root/etc/config/firewall +@@ -5,6 +5,10 @@ config defaults + option forward REJECT + # Uncomment this line to disable ipv6 rules + # option disable_ipv6 1 ++ option flow_offloading 1 ++ option flow_offloading_hw 1 ++ option fullcone 1 ++ option fullcone6 0 + + config zone + option name lan +--- a/root/usr/share/firewall4/templates/ruleset.uc ++++ b/root/usr/share/firewall4/templates/ruleset.uc +@@ -327,6 +327,12 @@ table inet fw4 { + {% for (let redirect in fw4.redirects(`dstnat_${zone.name}`)): %} + {%+ include("redirect.uc", { fw4, zone, redirect }) %} + {% endfor %} ++{% if (zone.masq && fw4.default_option("fullcone")): %} ++ {%+ include("zone-fullcone.uc", { fw4, zone, family: 4, direction: "dstnat" }) %} ++{% endif %} ++{% if (zone.masq6 && fw4.default_option("fullcone6")): %} ++ {%+ include("zone-fullcone.uc", { fw4, zone, family: 6, direction: "dstnat" }) %} ++{% endif %} + {% fw4.includes('chain-append', `dstnat_${zone.name}`) %} + } + +@@ -337,20 +343,26 @@ table inet fw4 { + {% for (let redirect in fw4.redirects(`srcnat_${zone.name}`)): %} + {%+ include("redirect.uc", { fw4, zone, redirect }) %} + {% endfor %} +-{% if (zone.masq): %} ++{% if (zone.masq && !fw4.default_option("fullcone")): %} + {% for (let saddrs in zone.masq4_src_subnets): %} + {% for (let daddrs in zone.masq4_dest_subnets): %} + {%+ include("zone-masq.uc", { fw4, zone, family: 4, saddrs, daddrs }) %} + {% endfor %} + {% endfor %} + {% endif %} +-{% if (zone.masq6): %} ++{% if (zone.masq6 && !fw4.default_option("fullcone6")): %} + {% for (let saddrs in zone.masq6_src_subnets): %} + {% for (let daddrs in zone.masq6_dest_subnets): %} + {%+ include("zone-masq.uc", { fw4, zone, family: 6, saddrs, daddrs }) %} + {% endfor %} + {% endfor %} + {% endif %} ++{% if (zone.masq && fw4.default_option("fullcone")): %} ++ {%+ include("zone-fullcone.uc", { fw4, zone, family: 4, direction: "srcnat" }) %} ++{% endif %} ++{% if (zone.masq6 && fw4.default_option("fullcone6")): %} ++ {%+ include("zone-fullcone.uc", { fw4, zone, family: 6, direction: "srcnat" }) %} ++{% endif %} + {% fw4.includes('chain-append', `srcnat_${zone.name}`) %} + } + +--- /dev/null ++++ b/root/usr/share/firewall4/templates/zone-fullcone.uc +@@ -0,0 +1,4 @@ ++{# /usr/share/firewall4/templates/zone-fullcone.uc #} ++ meta nfproto {{ fw4.nfproto(family) }} fullcone comment "!fw4: Handle {{ ++ zone.name ++}} {{ fw4.nfproto(family, true) }} fullcone NAT {{ direction }} traffic" +--- a/root/usr/share/ucode/fw4.uc ++++ b/root/usr/share/ucode/fw4.uc +@@ -1,3 +1,5 @@ ++// /usr/share/ucode/fw4.uc ++ + const fs = require("fs"); + const uci = require("uci"); + const ubus = require("ubus"); +@@ -489,6 +491,25 @@ function nft_try_hw_offload(devices) { + return (rc == 0); + } + ++function nft_try_fullcone() { ++ let nft_test = ++ 'add table inet fw4-fullcone-test; ' + ++ 'add chain inet fw4-fullcone-test dstnat { ' + ++ 'type nat hook prerouting priority -100; policy accept; ' + ++ 'fullcone; ' + ++ '}; ' + ++ 'add chain inet fw4-fullcone-test srcnat { ' + ++ 'type nat hook postrouting priority -100; policy accept; ' + ++ 'fullcone; ' + ++ '}; '; ++ let cmd = sprintf("/usr/sbin/nft -c '%s' 2>/dev/null", replace(nft_test, "'", "'\\''")); ++ let ok = system(cmd) == 0; ++ if (!ok) { ++ warn("nft_try_fullcone: cmd "+ cmd + "\n"); ++ } ++ return ok; ++} ++ + + return { + read_kernel_version: function() { +@@ -855,6 +876,18 @@ return { + warn(`[!] ${msg}\n`); + }, + ++ myinfo: function(fmt, ...args) { ++ if (getenv("QUIET")) ++ return; ++ ++ let msg = sprintf(fmt, ...args); ++ ++ if (getenv("TTY")) ++ warn(`\033[32m${msg}\033[m\n`); ++ else ++ warn(`[I] ${msg}\n`); ++ }, ++ + get: function(sid, opt) { + return this.cursor.get("firewall", sid, opt); + }, +@@ -1036,6 +1069,21 @@ return { + } + }, + ++ myinfo_section: function(s, msg) { ++ if (s[".name"]) { ++ if (s.name) ++ this.myinfo("Section %s (%s) %s", this.section_id(s[".name"]), s.name, msg); ++ else ++ this.myinfo("Section %s %s", this.section_id(s[".name"]), msg); ++ } ++ else { ++ if (s.name) ++ this.myinfo("ubus %s (%s) %s", s.type || "rule", s.name, msg); ++ else ++ this.myinfo("ubus %s %s", s.type || "rule", msg); ++ } ++ }, ++ + parse_policy: function(val) { + return this.parse_enum(val, [ + "accept", +@@ -1475,6 +1523,7 @@ return { + "dnat", + "snat", + "masquerade", ++ "fullcone", + "accept", + "reject", + "drop" +@@ -1946,6 +1995,8 @@ return { + } + + let defs = this.parse_options(data, { ++ fullcone: [ "bool", "0" ], ++ fullcone6: [ "bool", "0" ], + input: [ "policy", "drop" ], + output: [ "policy", "drop" ], + forward: [ "policy", "drop" ], +@@ -1980,6 +2031,11 @@ return { + + delete defs.syn_flood; + ++ if (!nft_try_fullcone()) { ++ delete defs.fullcone; ++ warn("nft_try_fullcone failed, disable fullcone globally\n"); ++ } ++ + this.state.defaults = defs; + }, + +@@ -2205,10 +2261,23 @@ return { + zone.related_subnets = related_subnets; + zone.related_physdevs = related_physdevs; + +- if (zone.masq || zone.masq6) ++ if (zone.masq) { + zone.dflags.snat = true; ++ if (this.state.defaults.fullcone) { ++ zone.dflags.dnat = true; ++ this.myinfo_section(data, "IPv4 fullcone enabled for zone '" + zone.name + "'"); ++ } ++ } ++ ++ if (zone.masq6) { ++ zone.dflags.snat = true; ++ if (this.state.defaults.fullcone6) { ++ zone.dflags.dnat = true; ++ this.myinfo_section(data, "IPv6 fullcone enabled for zone '" + zone.name + "'"); ++ } ++ } + +- if ((zone.auto_helper && !(zone.masq || zone.masq6)) || length(zone.helper)) { ++ if ((zone.auto_helper && !(zone.masq || zone.masq6 || this.state.defaults.fullcone || this.state.defaults.fullcone6)) || length(zone.helper)) { + zone.dflags.helper = true; + + for (let helper in (length(zone.helper) ? zone.helper : this.state.helpers)) { diff --git a/devices/common/diy/package/network/config/firewall4/patches/100-fw4-support-script.patch b/devices/common/diy/package/network/config/firewall4/patches/100-fw4-support-script.patch new file mode 100644 index 000000000000..984ecbebdb98 --- /dev/null +++ b/devices/common/diy/package/network/config/firewall4/patches/100-fw4-support-script.patch @@ -0,0 +1,20 @@ +diff --git a/root/sbin/fw4 b/root/sbin/fw4 +index c3e95c2..8fa6c6e 100755 +--- a/root/sbin/fw4 ++++ b/root/sbin/fw4 +@@ -20,6 +20,7 @@ start() { + { + flock -x 1000 + ++ test -f /etc/firewall.exwan && sh /etc/firewall.exwan + case "$1" in + start) + [ -f $STATE ] && die "The fw4 firewall appears to be already loaded." +@@ -38,6 +39,7 @@ start() { + ACTION=includes \ + utpl -S $MAIN + } 1000>$LOCK ++ test -f /etc/firewall.include && sh /etc/firewall.include + } + + print() { diff --git a/devices/common/diy/package/network/config/firewall4/patches/200-fw4-hotplug-fork.patch b/devices/common/diy/package/network/config/firewall4/patches/200-fw4-hotplug-fork.patch new file mode 100644 index 000000000000..7594291ce16c --- /dev/null +++ b/devices/common/diy/package/network/config/firewall4/patches/200-fw4-hotplug-fork.patch @@ -0,0 +1,10 @@ +diff --git a/root/etc/hotplug.d/iface/20-firewall b/root/etc/hotplug.d/iface/20-firewall +index d0f030b..9a8132c 100644 +--- a/root/etc/hotplug.d/iface/20-firewall ++++ b/root/etc/hotplug.d/iface/20-firewall +@@ -14,4 +14,4 @@ has_zone() { + has_zone || exit 0 + + logger -t firewall "Reloading firewall due to $ACTION of $INTERFACE ($DEVICE)" +-fw4 -q reload ++fw4 -q reload & diff --git a/devices/common/diy/package/network/services/ppp/patches/512-syncppp.patch b/devices/common/diy/package/network/services/ppp/patches/512-syncppp.patch new file mode 100644 index 000000000000..00de134a0721 --- /dev/null +++ b/devices/common/diy/package/network/services/ppp/patches/512-syncppp.patch @@ -0,0 +1,203 @@ +--- a/pppd/chap.c ++++ b/pppd/chap.c +@@ -42,6 +42,9 @@ + #include "chap.h" + #include "chap-md5.h" + ++#include ++#include "syncppp.h" ++ + #ifdef PPP_WITH_CHAPMS + #include "chap_ms.h" + #define MDTYPE_ALL (MDTYPE_MICROSOFT_V2 | MDTYPE_MICROSOFT | MDTYPE_MD5) +@@ -520,6 +523,18 @@ chap_respond(struct chap_client_state *c + p[2] = len >> 8; + p[3] = len; + ++ if (npppd > 1) { ++ if (syncppp(npppd) < 0) { ++ error("syncppp sync fail"); ++ sem_unlink(SEM_COUNT_NAME); ++ sem_unlink(SEM_BLOCK_NAME); ++ } else { ++ info("syncppp sync succeeded"); ++ } ++ } else { ++ info("syncppp not active"); ++ } ++ + output(0, response, PPP_HDRLEN + len); + } + +--- a/pppd/Makefile.am ++++ b/pppd/Makefile.am +@@ -67,6 +67,7 @@ noinst_HEADERS = \ + peap.h \ + pppd-private.h \ + spinlock.h \ ++ syncppp.h \ + tls.h \ + tdb.h + +@@ -85,6 +86,7 @@ pppd_SOURCES = \ + main.c \ + options.c \ + session.c \ ++ syncppp.c \ + tty.c \ + upap.c \ + utils.c +@@ -95,7 +97,7 @@ BUILT_SOURCE = \ + + pppd_CPPFLAGS = -DSYSCONFDIR=\"${sysconfdir}\" -DPPPD_RUNTIME_DIR='"@PPPD_RUNTIME_DIR@"' -DPPPD_LOGFILE_DIR='"@PPPD_LOGFILE_DIR@"' + pppd_LDFLAGS = +-pppd_LIBS = ++pppd_LIBS = -lpthread + + if PPP_WITH_SYSTEM_CA_PATH + pppd_CPPFLAGS += -DSYSTEM_CA_PATH='"@SYSTEM_CA_PATH@"' +--- a/pppd/options.c ++++ b/pppd/options.c +@@ -136,6 +136,7 @@ bool show_options; /* print all support + bool dryrun; /* print out option values and exit */ + char *domain; /* domain name set by domain option */ + int child_wait = 5; /* # seconds to wait for children at exit */ ++int npppd = 0; /* synchronize between multiple pppd */ + struct userenv *userenv_list; /* user environment variables */ + int dfl_route_metric = -1; /* metric of the default route to set over the PPP link */ + +@@ -339,6 +340,9 @@ struct option general_options[] = { + "Unset user environment variable", + OPT_A2PRINTER | OPT_NOPRINT, (void *)user_unsetprint }, + ++ { "syncppp", o_int, &npppd, ++ "sync among multiple pppd when sending chap/pap respond", OPT_PRIO }, ++ + { "defaultroute-metric", o_int, &dfl_route_metric, + "Metric to use for the default route (Linux only; -1 for default behavior)", + OPT_PRIV|OPT_LLIMIT|OPT_INITONLY, NULL, 0, -1 }, +--- a/pppd/pppd-private.h ++++ b/pppd/pppd-private.h +@@ -207,6 +207,7 @@ extern bool dump_options; /* print out o + extern bool show_options; /* show all option names and descriptions */ + extern bool dryrun; /* check everything, print options, exit */ + extern int child_wait; /* # seconds to wait for children at end */ ++extern int npppd; /* synchronize between multiple pppd */ + extern char *current_option; /* the name of the option being parsed */ + extern int privileged_option; /* set iff the current option came from root */ + extern char *option_source; /* string saying where the option came from */ +--- /dev/null ++++ b/pppd/syncppp.c +@@ -0,0 +1,75 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "pppd-private.h" ++#include "syncppp.h" ++ ++int syncppp(int nproc) ++{ ++ int flags; ++ int value; ++ sem_t *block; ++ sem_t *count; ++ struct timespec ts; ++ ++ if (nproc <= 1) { ++ error("syncppp: number of pppd should be larger than 1"); ++ return -1; ++ } ++ ++ if (clock_gettime(CLOCK_REALTIME, &ts) == -1) { ++ error("clock_gettime error"); ++ return -1; ++ } ++ ts.tv_sec += SYNCPPP_TIMEOUT; ++ ++ ++ flags = O_RDWR | O_CREAT; ++ block = sem_open(SEM_BLOCK_NAME, flags, 0644, 0); ++ count = sem_open(SEM_COUNT_NAME, flags, 0644, 0); ++ if (block == SEM_FAILED || count == SEM_FAILED) { ++ error("syncppp: sem_open failed"); ++ return -1; ++ } ++ ++ if (sem_post(count) < 0) { ++ error("syncppp: sem_post failed"); ++ return -1; ++ } ++ if (sem_getvalue(count, &value) < 0) { ++ error("syncppp: sem_getvalue failed"); ++ return -1; ++ } ++ info("%d pppd have arrived, waiting for the left %d", value, nproc-value); ++ if (value >= nproc) { ++ while (nproc-1 > 0) { ++ if (sem_post(block) < 0) { ++ error("syncppp: sem_post failed"); ++ return -1; ++ } ++ nproc--; ++ } ++ } else { ++ if (sem_timedwait(block, &ts) < 0) { ++ if (errno == ETIMEDOUT) { ++ error("syncppp: sem_timewait time out"); ++ } else { ++ error("syncppp: sem_timewait error"); ++ } ++ return -1; ++ } ++ ++ } ++ ++ sem_close(count); ++ sem_close(block); ++ ++ sem_unlink(SEM_COUNT_NAME); ++ sem_unlink(SEM_BLOCK_NAME); ++ ++ return 0; ++} ++ +--- /dev/null ++++ b/pppd/syncppp.h +@@ -0,0 +1,4 @@ ++#define SEM_BLOCK_NAME "block" ++#define SEM_COUNT_NAME "count" ++#define SYNCPPP_TIMEOUT 5 ++extern int syncppp(int nproc); +--- a/pppd/upap.c ++++ b/pppd/upap.c +@@ -55,6 +55,8 @@ + #include "options.h" + #include "upap.h" + ++#include ++#include "syncppp.h" + + static bool hide_password = 1; + +@@ -545,6 +547,18 @@ upap_sauthreq(upap_state *u) + PUTCHAR(u->us_passwdlen, outp); + BCOPY(u->us_passwd, outp, u->us_passwdlen); + ++ if (npppd > 1) { ++ if (syncppp(npppd) < 0) { ++ error("syncppp sync fail"); ++ sem_unlink(SEM_COUNT_NAME); ++ sem_unlink(SEM_BLOCK_NAME); ++ } else { ++ info("syncppp sync succeeded"); ++ } ++ } else { ++ info("syncppp not active"); ++ } ++ + output(u->us_unit, outpacket_buf, outlen + PPP_HDRLEN); + + TIMEOUT(upap_timeout, u, u->us_timeouttime); diff --git a/devices/common/diy/package/system/opkg/patches/010-opkg-force-depends.patch b/devices/common/diy/package/system/opkg/patches/010-opkg-force-depends.patch new file mode 100644 index 000000000000..1b4ac393dcbf --- /dev/null +++ b/devices/common/diy/package/system/opkg/patches/010-opkg-force-depends.patch @@ -0,0 +1,13 @@ +--- a/src/opkg-cl.c ++++ b/src/opkg-cl.c +@@ -255,6 +255,10 @@ static int args_parse(int argc, char *argv[]) + } + } + ++ conf->force_depends = 1; ++ conf->force_checksum = 1; ++ conf->force_overwrite = 1; ++ + if (!conf->conf_file && !conf->offline_root) + conf->conf_file = xstrdup("/etc/opkg.conf"); + diff --git a/devices/common/diy/package/system/opkg/patches/ignore_error.patch b/devices/common/diy/package/system/opkg/patches/ignore_error.patch new file mode 100644 index 000000000000..41f7005e4b13 --- /dev/null +++ b/devices/common/diy/package/system/opkg/patches/ignore_error.patch @@ -0,0 +1,8 @@ +--- a/libopkg/pkg.c ++++ b/libopkg/pkg.c +@@ -1422,5 +1422,4 @@ + "package \"%s\" %s script returned status %d.\n", + pkg->name, script, err); +- return err; + } + diff --git a/devices/common/diy/package/system/opkg/patches/pkg_hash.patch b/devices/common/diy/package/system/opkg/patches/pkg_hash.patch new file mode 100644 index 000000000000..e7cc7c66eda1 --- /dev/null +++ b/devices/common/diy/package/system/opkg/patches/pkg_hash.patch @@ -0,0 +1,9 @@ +--- a/libopkg/pkg_hash.c ++++ b/libopkg/pkg_hash.c +@@ -263,5 +263,5 @@ + + if (unresolved) { +- res = 1; ++ // res = 1; + tmp = unresolved; + while (*tmp) { diff --git a/devices/common/diy/package/system/opkg/patches/zh-cn.patch b/devices/common/diy/package/system/opkg/patches/zh-cn.patch new file mode 100644 index 000000000000..94aa1a1d4f9c --- /dev/null +++ b/devices/common/diy/package/system/opkg/patches/zh-cn.patch @@ -0,0 +1,75 @@ +--- a/libopkg/opkg_download.c ++++ b/libopkg/opkg_download.c +@@ -174,9 +174,9 @@ + if (res) { + opkg_msg(ERROR, +- "Failed to download %s, wget returned %d.\n", ++ "下载失败 %s, wget returned %d.\n", + src, res); + if (res == 4) + opkg_msg(ERROR, +- "Check your network settings and connectivity.\n\n"); ++ "请检查网络设置, 确保本设备网络可用.\n\n"); + free(tmp_file_location); + return -1; + +--- a/libopkg/opkg.c ++++ b/libopkg/opkg.c +@@ -225,5 +225,5 @@ + new = pkg_hash_fetch_best_installation_candidate_by_name(package_name); + if (!new) { +- opkg_msg(ERROR, "Couldn't find package %s\n", package_name); ++ opkg_msg(ERROR, "找不到软件包 %s\n", package_name); + return -1; + } +@@ -242,5 +242,5 @@ + if (unresolved) { + char **tmp = unresolved; +- opkg_msg(ERROR, "Couldn't satisfy the following dependencies" ++ opkg_msg(ERROR, "无法满足以下依赖" + " for %s:\n", package_name); + while (*tmp) { +@@ -271,5 +271,5 @@ + + if (pkg->src == NULL) { +- opkg_msg(ERROR, "Package %s not available from any " ++ opkg_msg(ERROR, "在以下仓库未找到可用的 %s 软件包" + "configured src\n", package_name); + return -1; + +--- a/libopkg/opkg_install.c ++++ b/libopkg/opkg_install.c +@@ -222,6 +222,6 @@ + + if (pkg_size_kbs >= kbs_available) { +- opkg_msg(ERROR, "Only have %ldkb available on filesystem %s, " +- "pkg %s needs %ld\n", ++ opkg_msg(ERROR, "剩余可用容量不足, 文件系统 %s 当前剩余 %ldkb 可用," ++ "软件包 %s 需要 %ld\n", + kbs_available, root_dir, pkg->name, pkg_size_kbs); + return -1; +@@ -1319,6 +1319,6 @@ + } + if (err) { +- opkg_msg(ERROR, "Failed to download %s. " +- "Perhaps you need to run 'opkg update'?\n", ++ opkg_msg(ERROR, "下载 %s 失败. " ++ "请更新列表后重试\n", + pkg->name); + return -1; + +--- a/libopkg/opkg_conf.c ++++ b/libopkg/opkg_conf.c +@@ -497,10 +497,10 @@ + lock_fd = creat(lock_file, S_IRUSR | S_IWUSR | S_IRGRP); + if (lock_fd == -1) { +- opkg_perror(ERROR, "Could not create lock file %s", lock_file); ++ opkg_perror(ERROR, "有任务在执行中, 请稍后再试.", lock_file); + goto err2; + } + + if (lockf(lock_fd, F_TLOCK, (off_t) 0) == -1) { +- opkg_perror(ERROR, "Could not lock %s", lock_file); ++ opkg_perror(ERROR, "有任务在执行中, 请稍后再试.", lock_file); + if (close(lock_fd) == -1) + opkg_perror(ERROR, "Couldn't close descriptor %d (%s)", diff --git a/devices/common/kernel_6.1.sh b/devices/common/kernel_6.1.sh deleted file mode 100644 index 834d93bdc7f6..000000000000 --- a/devices/common/kernel_6.1.sh +++ /dev/null @@ -1,48 +0,0 @@ -#!/bin/bash - -shopt -s extglob - -rm -rf target/linux package/kernel package/boot package/firmware - -mkdir new; cp -rf .git new/.git -cd new -git reset --hard origin/master - -cp -rf --parents target/linux package/kernel package/boot package/firmware include/kernel* config/Config-images.in config/Config-kernel.in include/image*.mk include/trusted-firmware-a.mk include/bpf.mk scripts/ubinize-image.sh scripts/target-metadata.pl package/utils/bcm27xx-utils package/devel/perf package/network/config/qosify ../ -cd - - -sed -i "s/^.*vermagic$/\techo '1' > \$(LINUX_DIR)\/.vermagic/" include/kernel-defaults.mk - -#sed -i "s/\$(PKG_VERSION)-\$(PKG_RELEASE)/\$(PKG_VERSION)-r\$(PKG_RELEASE)/" include/package-defaults.mk - -cp -rf devices/common/patches/rootfstargz.patch.main devices/common/patches/rootfstargz.patch -cp -rf devices/common/patches/qca-ssdk.patch.main devices/common/patches/qca-ssdk.patch -cp -rf devices/common/patches/ebpf.patch.main devices/common/patches/ebpf.patch -cp -rf devices/common/patches/nonshared.patch.main devices/common/patches/nonshared.patch - -git_clone_path master https://github.com/coolsnowwolf/lede target/linux/generic/hack-6.1 - -wget -N https://raw.githubusercontent.com/coolsnowwolf/lede/master/target/linux/generic/pending-6.1/613-netfilter_optional_tcp_window_check.patch -P target/linux/generic/pending-6.1/ - -wget -N https://raw.githubusercontent.com/coolsnowwolf/lede/master/package/kernel/linux/modules/video.mk -P package/kernel/linux/modules/ - -rm -rf target/linux/generic/hack-6.1/{410-block-fit-partition-parser.patch,724-net-phy-aquantia*,720-net-phy-add-aqr-phys.patch} - -wget -N https://raw.githubusercontent.com/openwrt/openwrt/main/include/u-boot.mk -P include/ - -wget -N https://raw.githubusercontent.com/immortalwrt/immortalwrt/master/package/kernel/mt76/patches/0001-mt76-allow-VHT-rate-on-2.4GHz.patch -P package/kernel/mt76/patches/ - -cd feeds/packages -rm -rf kernel libs/xr_usb_serial_common net/xtables-addons -git_clone_path master https://github.com/openwrt/packages kernel libs/xr_usb_serial_common net/xtables-addons -cd ../../ - -wget -N https://raw.githubusercontent.com/openwrt/packages/master/net/coova-chilli/patches/011-kernel517.patch -P package/feeds/packages/coova-chilli/patches/ - -sed -i 's/=bbr/=cubic/' package/kernel/linux/files/sysctl-tcp-bbr.conf - -sed -i "s/tty\(0\|1\)::askfirst/tty\1::respawn/g" target/linux/*/base-files/etc/inittab - -sed -i "s/no-lto,/no-lto no-mold,/" include/package.mk - -sed -i "s/OpenWrt/Kwrt/g" package/base-files/files/bin/config_generate package/base-files/image-config.in config/Config-images.in Config.in include/u-boot.mk include/version.mk package/network/config/wifi-scripts/files/lib/wifi/mac80211.sh || true \ No newline at end of file diff --git a/devices/common/kernel_6.6.sh b/devices/common/kernel_6.6.sh deleted file mode 100644 index b0c137904661..000000000000 --- a/devices/common/kernel_6.6.sh +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/bash - -shopt -s extglob -SHELL_FOLDER=$(dirname $(readlink -f "$0")) - -#bash $SHELL_FOLDER/../common/kernel_6.1.sh - -git_clone_path master https://github.com/coolsnowwolf/lede target/linux/generic/hack-6.6 -rm -rf target/linux/generic/hack-6.6/767-net-phy-realtek* - -wget -N https://raw.githubusercontent.com/coolsnowwolf/lede/master/target/linux/generic/pending-6.6/613-netfilter_optional_tcp_window_check.patch -P target/linux/generic/pending-6.6/ - -wget -N https://raw.githubusercontent.com/openwrt/packages/master/libs/dmx_usb_module/patches/101-fix-kernel-6.6-builds.patch -P package/feeds/packages/dmx_usb_module/patches/ - -cd feeds/packages -rm -rf libs/libpfring -git_clone_path master https://github.com/openwrt/packages libs/libpfring -cd ../../ - -wget -N https://raw.githubusercontent.com/openwrt/openwrt/main/package/devel/kselftests-bpf/Makefile -P package/devel/kselftests-bpf/ - -rm -rf target/linux/generic/hack-6.6/{410-block-fit-partition-parser.patch,724-net-phy-aquantia*,720-net-phy-add-aqr-phys.patch} diff --git a/devices/common/patches/base-files.patch b/devices/common/patches/base-files.patch new file mode 100644 index 000000000000..91eaf0697e5d --- /dev/null +++ b/devices/common/patches/base-files.patch @@ -0,0 +1,64 @@ +--- a/package/base-files/files/etc/shinit ++++ b/package/base-files/files/etc/shinit +@@ -2,6 +2,8 @@ + [ -x /usr/bin/vim ] && alias vi=vim || alias vim=vi + + alias ll='ls -alF --color=auto' ++alias reboot='(/bin/busybox reboot &);sleep 3;/bin/busybox reboot -f' ++PS1='\[\e[32m\][\[\e[m\]\[\e[31m\]\u\[\e[m\]\[\e[33m\]@\[\e[m\]\[\e[32m\]\h\[\e[m\]:\[\e[m\]\[\e[32m\]\[\e[1;32m\]\@\[\e[36m\] \w\[\e[m\]\[\e[32m\]]\[\e[0m\] \$\[\e[m\] ' + + [ -z "$KSH_VERSION" -o \! -s /etc/mkshrc ] || . /etc/mkshrc + +--- a/package/base-files/files/sbin/sysupgrade ++++ b/package/base-files/files/sbin/sysupgrade +@@ -277,13 +277,15 @@ create_backup_archive() { + # Part of archive with installed packages info + if [ $ret -eq 0 ]; then + if [ "$SAVE_INSTALLED_PKGS" -eq 1 ]; then +- # Format: pkg-name{rom,overlay,unknown} +- # rom is used for pkgs in /rom, even if updated later +- tar_print_member "$INSTALLED_PACKAGES" "$(find /usr/lib/opkg/info -name "*.control" \( \ +- \( -exec test -f /rom/{} \; -exec echo {} rom \; \) -o \ +- \( -exec test -f /overlay/upper/{} \; -exec echo {} overlay \; \) -o \ +- \( -exec echo {} unknown \; \) \ +- \) | sed -e 's,.*/,,;s/\.control /\t/')" || ret=1 ++ . /etc/profile.d/opkg.sh && opkg save ++ [ -f /rom/etc/uci-defaults/zz-asu-defaults ] && { ++ cp -f /rom/etc/uci-defaults/zz-asu-defaults /etc/uci-defaults/zz-asu-defaults ++ echo "/etc/uci-defaults/zz-asu-defaults" >> $CONFFILES ++ } ++ else ++ uci -q del opkg.auto ++ uci -q del opkg.custom ++ uci commit opkg + fi + fi + + +--- a/package/base-files/files/etc/profile ++++ b/package/base-files/files/etc/profile +@@ -22,7 +23,11 @@ esac + + [ -n "$FAILSAFE" ] || { + for FILE in /etc/profile.d/*.sh; do +- [ -e "$FILE" ] && . "$FILE" ++ if [ "$FILE" == "/etc/profile.d/30-sysinfo.sh" ]; then ++ [ "$(which bash)" ] && env -i bash "$FILE" ++ else ++ [ -e "$FILE" ] && . "$FILE" ++ fi + done + unset FILE + } + +--- a/package/base-files/files/lib/preinit/02_sysinfo ++++ b/package/base-files/files/lib/preinit/02_sysinfo +@@ -5,6 +5,7 @@ do_sysinfo_generic() { + echo "$(strings /proc/device-tree/compatible | head -1)" > /tmp/sysinfo/board_name + [ ! -e /tmp/sysinfo/model -a -e /proc/device-tree/model ] && \ + echo "$(cat /proc/device-tree/model)" > /tmp/sysinfo/model ++ sed -i "s/friendlyelec/friendlyarm/" /tmp/sysinfo/board_name + } + + boot_hook_add preinit_main do_sysinfo_generic + diff --git a/devices/common/patches/curl.patch b/devices/common/patches/curl.patch new file mode 100644 index 000000000000..b8d088545dd4 --- /dev/null +++ b/devices/common/patches/curl.patch @@ -0,0 +1,11 @@ +--- a/package/feeds/packages/curl/Config.in ++++ b/package/feeds/packages/curl/Config.in +@@ -4,7 +4,7 @@ comment "SSL support" + + choice + prompt "Selected SSL library" +- default LIBCURL_MBEDTLS ++ default LIBCURL_OPENSSL + + config LIBCURL_MBEDTLS + bool "mbed TLS" diff --git a/devices/common/patches/dnsmasq.patch b/devices/common/patches/dnsmasq.patch new file mode 100644 index 000000000000..b1c533aee0b3 --- /dev/null +++ b/devices/common/patches/dnsmasq.patch @@ -0,0 +1,102 @@ +--- a/package/network/services/dnsmasq/Makefile ++++ b/package/network/services/dnsmasq/Makefile +@@ -22,6 +22,8 @@ PKG_CPE_ID:=cpe:/a:thekelleys:dnsmasq + + PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_UPSTREAM_VERSION) + ++PKG_BUILD_DEPENDS:=nftables ++ + PKG_INSTALL:=1 + PKG_BUILD_PARALLEL:=1 + PKG_BUILD_FLAGS:=lto +@@ -66,8 +68,7 @@ $(call Package/dnsmasq/Default) + TITLE += (with DNSSEC, DHCPv6, Auth DNS, IPset, Nftset, Conntrack, NO_ID enabled by default) + DEPENDS+=+PACKAGE_dnsmasq_full_dnssec:libnettle \ + +PACKAGE_dnsmasq_full_ipset:kmod-ipt-ipset \ +- +PACKAGE_dnsmasq_full_conntrack:libnetfilter-conntrack \ +- +PACKAGE_dnsmasq_full_nftset:nftables-json ++ +PACKAGE_dnsmasq_full_conntrack:libnetfilter-conntrack + VARIANT:=full + PROVIDES:=dnsmasq + endef +@@ -187,6 +188,11 @@ define Package/dnsmasq/install + $(INSTALL_DIR) $(1)/etc/uci-defaults + $(INSTALL_BIN) ./files/50-dnsmasq-migrate-resolv-conf-auto.sh $(1)/etc/uci-defaults + $(INSTALL_BIN) ./files/50-dnsmasq-migrate-ipset.sh $(1)/etc/uci-defaults ++ $(INSTALL_DIR) $(1)/usr/lib ++ $(INSTALL_BIN) $(STAGING_DIR)/usr/lib/libnftables.so.1 $(1)/usr/lib/libnftables.so.1 ++ $(INSTALL_BIN) $(STAGING_DIR)/usr/lib/libjansson.so.4 $(1)/usr/lib/libjansson.so.4 ++ $(INSTALL_BIN) $(STAGING_DIR)/usr/lib/libnftnl.so.11 $(1)/usr/lib/libnftnl.so.11 ++ $(INSTALL_BIN) $(STAGING_DIR)/usr/lib/libmnl.so.0 $(1)/usr/lib/libmnl.so.0 + endef + + Package/dnsmasq-dhcpv6/install = $(Package/dnsmasq/install) + + +--- a/package/network/services/dnsmasq/files/dnsmasq.init ++++ b/package/network/services/dnsmasq/files/dnsmasq.init +@@ -1204,7 +1204,6 @@ dnsmasq_start() + [ -n "$instance_ifc" ] && network_get_device instance_netdev "$instance_ifc" && + [ -n "$instance_netdev" ] && procd_set_param netdev $instance_netdev + +- procd_add_jail dnsmasq ubus log + procd_add_jail_mount $CONFIGFILE $DHCPBOGUSHOSTNAMEFILE $DHCPSCRIPT $DHCPSCRIPT_DEPENDS + procd_add_jail_mount $EXTRA_MOUNT $RFC6761FILE $TRUSTANCHORSFILE + procd_add_jail_mount $dnsmasqconffile $dnsmasqconfdir $resolvdir $user_dhcpscript +@@ -1217,6 +1216,20 @@ dnsmasq_start() + [ -e "$hostsfile" ] && procd_add_jail_mount $hostsfile + + procd_close_instance ++ config_get_bool dns_redirect "$cfg" dns_redirect 0 ++ config_get dns_port "$cfg" port 53 ++ if [ "$dns_redirect" = 1 ]; then ++ if [ -n "$(command -v nft)" ]; then ++ nft add table inet dnsmasq ++ nft add chain inet dnsmasq prerouting "{ type nat hook prerouting priority -105; policy accept; }" ++ nft add rule inet dnsmasq prerouting "meta nfproto { ipv4, ipv6 } udp dport 53 counter redirect to :$dns_port comment \"DNSMASQ HIJACK\"" ++ else ++ iptables -t nat -A PREROUTING -m comment --comment "DNSMASQ" -p udp --dport 53 -j REDIRECT --to-ports $dns_port ++ iptables -t nat -A PREROUTING -m comment --comment "DNSMASQ" -p tcp --dport 53 -j REDIRECT --to-ports $dns_port ++ [ -n "$(command -v ip6tables)" ] && ip6tables -t nat -A PREROUTING -m comment --comment "DNSMASQ" -p udp --dport 53 -j REDIRECT --to-ports $dns_port ++ [ -n "$(command -v ip6tables)" ] && ip6tables -t nat -A PREROUTING -m comment --comment "DNSMASQ" -p tcp --dport 53 -j REDIRECT --to-ports $dns_port ++ fi ++ fi + } + + dnsmasq_stop() +@@ -1234,6 +1247,21 @@ dnsmasq_stop() + rm -f ${BASEDHCPSTAMPFILE}.${cfg}.*.dhcp + } + ++iptables_clear() ++{ ++ config_get dns_port "$cfg" port 53 ++ iptables -t nat -D PREROUTING -m comment --comment "DNSMASQ" -p udp --dport 53 -j REDIRECT --to-ports $dns_port 2>"/dev/null" ++ iptables -t nat -D PREROUTING -m comment --comment "DNSMASQ" -p tcp --dport 53 -j REDIRECT --to-ports $dns_port 2>"/dev/null" ++ [ -n "$(command -v ip6tables)" ] && ip6tables -t nat -D PREROUTING -m comment --comment "DNSMASQ" -p udp --dport 53 -j REDIRECT --to-ports $dns_port 2>"/dev/null" ++ [ -n "$(command -v ip6tables)" ] && ip6tables -t nat -D PREROUTING -m comment --comment "DNSMASQ" -p tcp --dport 53 -j REDIRECT --to-ports $dns_port 2>"/dev/null" ++} ++ ++nftables_clear() ++{ ++ ! nft --check list table inet dnsmasq > "/dev/null" 2>&1 || \ ++ nft delete table inet dnsmasq ++} ++ + add_interface_trigger() + { + local interface ignore +@@ -1304,6 +1332,7 @@ start_service() { + } + + reload_service() { ++ [ -n "$(command -v nft)" ] && nftables_clear || iptables_clear + rc_procd start_service "$@" + procd_send_signal dnsmasq "$@" + } +@@ -1330,4 +1359,5 @@ stop_service() { + else + config_foreach dnsmasq_stop dnsmasq + fi ++ [ -n "$(command -v nft)" ] && nftables_clear || iptables_clear + } diff --git a/devices/common/patches/firewall.patch b/devices/common/patches/firewall.patch new file mode 100644 index 000000000000..8a583bc6bd08 --- /dev/null +++ b/devices/common/patches/firewall.patch @@ -0,0 +1,124 @@ +--- a/package/network/config/firewall4/Makefile ++++ b/package/network/config/firewall4/Makefile +@@ -25,7 +25,8 @@ define Package/firewall4 + +kmod-nft-core +kmod-nft-fib +kmod-nft-offload \ + +kmod-nft-nat \ + +nftables-json \ +- +ucode +ucode-mod-fs +ucode-mod-ubus +ucode-mod-uci ++ +ucode +ucode-mod-fs +ucode-mod-ubus +ucode-mod-uci \ ++ +iptables +ip6tables +kmod-nft-fullcone +kmod-nft-socket +kmod-nft-tproxy + EXTRA_DEPENDS:=ucode (>=2022.03.22) + PROVIDES:=uci-firewall + endef +@@ -38,10 +39,14 @@ endef + define Package/firewall4/conffiles + /etc/config/firewall + /etc/nftables.d/ ++/etc/firewall.user + endef + + define Package/firewall4/install + $(CP) -a $(PKG_BUILD_DIR)/root/* $(1)/ ++ $(INSTALL_DIR) $(1)/etc/ ++ $(INSTALL_CONF) ./files/firewall.include $(1)/etc/firewall.user ++ $(INSTALL_CONF) ./files/firewall.exwan $(1)/etc/firewall.exwan + endef + + define Build/Compile + +--- a/package/network/config/firewall/Makefile ++++ b/package/network/config/firewall/Makefile +@@ -30,9 +30,10 @@ define Package/firewall + SECTION:=net + CATEGORY:=Base system + TITLE:=OpenWrt C Firewall +- DEPENDS:=+libubox +libubus +libuci +libip4tc +IPV6:libip6tc +libiptext +IPV6:libiptext6 +libxtables +kmod-ipt-core +kmod-ipt-conntrack +IPV6:kmod-nf-conntrack6 +kmod-ipt-nat ++ DEPENDS:=+libubox +libubus +libuci +libip4tc +IPV6:libip6tc +libiptext +IPV6:libiptext6 +libxtables +kmod-ipt-core +kmod-ipt-conntrack +IPV6:kmod-nf-conntrack6 +kmod-ipt-nat \ ++ +iptables-mod-fullconenat +ip6tables-mod-fullconenat +iptables-legacy +ip6tables-legacy +kmod-ipt-nat6 +kmod-ipt-offload \ ++ +ipset +iptables-mod-conntrack-extra +iptables-mod-iprange +iptables-mod-socket +iptables-mod-tproxy + PROVIDES:=uci-firewall +- CONFLICTS:=firewall4 + endef + + define Package/firewall/description + + + define Package/package/network/config/firewall/description +@@ -59,6 +59,7 @@ define Package/package/network/config/firewall/install + $(INSTALL_CONF) ./files/firewall.config $(1)/etc/config/firewall + $(INSTALL_DIR) $(1)/etc/ + $(INSTALL_CONF) ./files/firewall.user $(1)/etc/firewall.user ++ $(INSTALL_CONF) ./files/firewall.exwan $(1)/etc/firewall.exwan + $(INSTALL_DIR) $(1)/usr/share/fw3 + $(INSTALL_CONF) $(PKG_BUILD_DIR)/helpers.conf $(1)/usr/share/fw3 + endef + +--- a/package/feeds/luci/luci-app-firewall/htdocs/luci-static/resources/view/firewall/zones.js ++++ b/package/feeds/luci/luci-app-firewall/htdocs/luci-static/resources/view/firewall/zones.js +@@ -63,6 +63,43 @@ return view.extend({ + o = s.option(form.Flag, 'fullcone6', _('Enable FullCone NAT6')); + } + ++ o = s.option(form.Flag, 'expose_wan', _('Expose WAN'), _('Danger! Proceed at your own risk.')); ++ ++ o = s.option(form.Value, 'export', _('Ports to Expose'), _('Multiple ports can be, separated by spaces, format: 80 81 82')); ++ o.depends('expose_wan', '1'); ++ o.validate = function(section_id, value) { ++ if (value.match(/^(\d+\s*)+$/)) { ++ return true; ++ } ++ return _('Please enter valid format.'); ++ }; ++ ++ o = s.option(form.ListValue, 'family', _('Restrict to address family')); ++ o.modalonly = true; ++ o.rmempty = true; ++ o.depends('expose_wan', '1'); ++ o.value('', _('IPv4 and IPv6')); ++ o.value('ipv4', _('IPv4 only')); ++ o.value('ipv6', _('IPv6 only')); ++ ++ o = s.option(form.ListValue, 'proto', _('Protocol')); ++ o.modalonly = true; ++ o.rmempty = true; ++ o.default = 'tcp'; ++ o.depends('expose_wan', '1'); ++ o.value('tcp', _('TCP')); ++ o.value('udp', _('UDP')); ++ o.value('tudp', _('TCP+UDP')); ++ ++ o = s.option(form.Flag, 'ex_ssh', _('Expose SSH')); ++ o.depends('expose_wan', '1'); ++ o = s.option(form.Flag, 'ex_backend', _('Expose Backend')); ++ o.depends('expose_wan', '1'); ++ o = s.option(form.Value, 'backend_port', _('Backend Port'), _('国内请使用除80,443外的端口')); ++ o.depends('ex_backend', '1'); ++ o.rmempty = false; ++ o.datatype = 'integer'; ++ + var p = [ + s.option(form.ListValue, 'input', _('Input')), + s.option(form.ListValue, 'output', _('Output')), + +--- a/package/network/config/firewall/files/firewall.init ++++ b/package/network/config/firewall/files/firewall.init +@@ -38,10 +38,12 @@ service_triggers() { + } + + restart() { ++ test -f /etc/firewall.exwan && sh /etc/firewall.exwan + fw3 restart + } + + start_service() { ++ test -f /etc/firewall.exwan && sh /etc/firewall.exwan + fw3 ${QUIET} start + } + +@@ -50,6 +52,7 @@ stop_service() { + } + + reload_service() { ++ test -f /etc/firewall.exwan && sh /etc/firewall.exwan + fw3 reload + } diff --git a/devices/common/patches/fstools.patch b/devices/common/patches/fstools.patch new file mode 100644 index 000000000000..f411b8fe3127 --- /dev/null +++ b/devices/common/patches/fstools.patch @@ -0,0 +1,19 @@ +--- a/package/system/fstools/Makefile ++++ b/package/system/fstools/Makefile +@@ -82,14 +82,14 @@ define Package/block-mount + SECTION:=base + CATEGORY:=Base system + TITLE:=Block device mounting and checking +- DEPENDS:=+ubox +libubox +libuci +libblobmsg-json +libjson-c ++ DEPENDS:=+ubox +libubox +libuci +libblobmsg-json +libjson-c +fstools + endef + + define Package/blockd + SECTION:=base + CATEGORY:=Base system + TITLE:=Block device automounting +- DEPENDS:=+block-mount +fstools +libubus +kmod-fs-autofs4 +libblobmsg-json +libjson-c ++ DEPENDS:=+block-mount +libubus +kmod-fs-autofs4 +libblobmsg-json +libjson-c + endef + + define Package/fstools/install diff --git a/devices/common/patches/imagebuilder.patch b/devices/common/patches/imagebuilder.patch index 2149a326634c..c00040bf0d26 100644 --- a/devices/common/patches/imagebuilder.patch +++ b/devices/common/patches/imagebuilder.patch @@ -1,21 +1,5 @@ --- a/include/image.mk +++ b/include/image.mk -@@ -504,7 +504,6 @@ define Device/Check - endif - endef - --ifndef IB - define Device/Build/initramfs - $(call Device/Export,$(KDIR)/tmp/$$(KERNEL_INITRAMFS_IMAGE),$(1)) - $$(_TARGET): $$(if $$(KERNEL_INITRAMFS),$(BIN_DIR)/$$(KERNEL_INITRAMFS_IMAGE) \ -@@ -557,7 +556,6 @@ define Device/Build/initramfs - SUPPORTED_DEVICES="$$(SUPPORTED_DEVICES)" \ - $(TOPDIR)/scripts/json_add_image_info.py $$@ - endef --endif - - define Device/Build/compile - $$(_COMPILE_TARGET): $(KDIR)/$(1) @@ -623,7 +621,7 @@ define Device/Build/kernel endef @@ -29,7 +13,7 @@ Target-Profile: DEVICE_$(1) Target-Profile-Name: $(DEVICE_DISPLAY) Target-Profile-Packages: $(DEVICE_PACKAGES) -+Target-Profile-ImageSize: $(IMAGE_SIZE) ++Target-Profile-ImageSize: $(shell echo $$(( $(call exp_units,$(IMAGE_SIZE)) / 1024 ))) Target-Profile-hasImageMetadata: $(if $(foreach image,$(IMAGES),$(findstring append-metadata,$(IMAGE/$(image)))),1,0) Target-Profile-SupportedDevices: $(SUPPORTED_DEVICES) $(if $(BROKEN),Target-Profile-Broken: $(BROKEN)) @@ -87,26 +71,36 @@ --- a/target/imagebuilder/files/Makefile +++ b/target/imagebuilder/files/Makefile -@@ -142,6 +142,26 @@ BUILD_PACKAGES:=$(sort $(DEFAULT_PACKAGES) $($(USER_PROFILE)_PACKAGES) kernel) +@@ -142,6 +142,36 @@ BUILD_PACKAGES:=$(sort $(DEFAULT_PACKAGES) $($(USER_PROFILE)_PACKAGES) kernel) # "-pkgname" in the package list means remove "pkgname" from the package list BUILD_PACKAGES:=$(filter-out $(filter -%,$(BUILD_PACKAGES)) $(patsubst -%,%,$(filter -%,$(BUILD_PACKAGES))),$(BUILD_PACKAGES)) BUILD_PACKAGES:=$(USER_PACKAGES) $(BUILD_PACKAGES) -+IMAGE_SIZE_VALUE := $(shell echo $($(USER_PROFILE)_IMAGE_SIZE) | sed 's/k$$//') ++IMAGE_SIZE_VALUE := $($(USER_PROFILE)_IMAGE_SIZE) +ifdef IMAGE_SIZE_VALUE -+ ifeq ($(shell test $(IMAGE_SIZE_VALUE) -lt 20480 && echo true),true) -+ SMALL_FLASH := true -+ endif ++ ifeq ($(shell test $(IMAGE_SIZE_VALUE) -le 35840 && echo true),true) ++ SMALL_FLASH := true ++ endif ++ ifeq ($(shell test $(IMAGE_SIZE_VALUE) -le 20480 && echo true),true) ++ XSMALL_FLASH := true ++ endif +endif +ifneq ($(findstring usb,$(BUILD_PACKAGES)),) -+ BUILD_PACKAGES += automount luci-app-diskman ++ ifneq ($(XSMALL_FLASH),true) ++ BUILD_PACKAGES += automount luci-app-diskman ++ endif +endif +ifeq ($(SMALL_FLASH),true) -+ BUILD_PACKAGES += -coremark -htop -bash -openssh-sftp-server -luci-app-diskman ++ ifeq ($(XSMALL_FLASH),true) ++ BUILD_PACKAGES += -coremark -htop -bash -openssh-sftp-server ++ endif + ifeq ($(shell grep -q small_flash $(TOPDIR)/repositories.conf || echo "not_found"),not_found) + $(shell echo "`grep kwrt_kiddin9 $(TOPDIR)/repositories.conf | sed -e 's/kiddin9/small_flash/g'`" >>$(TOPDIR)/repositories.conf) -+ endif ++ endif ++ ifneq ($(findstring /data/bcache/,$(BIN_DIR)),) ++ BUILD_PACKAGES += -luci-app-homeproxy -luci-app-istorex -luci-theme-argon ++ endif +else -+ $(shell sed -i "/small_flash/d" $(TOPDIR)/repositories.conf) ++ $(shell sed -i "/small_flash/d" $(TOPDIR)/repositories.conf) +endif +define add_zh_cn_packages +$(eval BUILD_PACKAGES += $(foreach pkg,$(BUILD_PACKAGES),$(if $(and $(filter luci-app-%,$(pkg)),$(shell $(OPKG) list | grep -q "^luci-i18n-$(patsubst luci-app-%,%,$(pkg))-zh-cn" && echo 1)),luci-i18n-$(patsubst luci-app-%,%,$(pkg))-zh-cn))) @@ -114,7 +108,7 @@ BUILD_PACKAGES:=$(filter-out $(filter -%,$(BUILD_PACKAGES)) $(patsubst -%,%,$(filter -%,$(BUILD_PACKAGES))),$(BUILD_PACKAGES)) PACKAGES:= -@@ -157,6 +177,8 @@ _call_image: staging_dir/host/.prereq-build +@@ -157,6 +187,8 @@ _call_image: staging_dir/host/.prereq-build $(MAKE) -s build_image $(MAKE) -s json_overview_image_info $(MAKE) -s checksum @@ -123,7 +117,7 @@ _call_manifest: FORCE rm -rf $(TARGET_DIR) -@@ -224,9 +246,17 @@ package_install: FORCE +@@ -224,9 +256,17 @@ package_install: FORCE @echo @echo Installing packages... ifeq ($(CONFIG_USE_APK),) @@ -135,14 +129,14 @@ + $(if $(USER_FILES), \ + find $(USER_FILES) -name "*.ipk" -print0 | \ + while IFS= read -r -d '' ipk; do \ -+ $(OPKG) install "$$ipk" && rm -f "$$ipk" || true; \ ++ $(OPKG) install "$$ipk" && rm -f "$$ipk" || true; \ + done; \ + ) -+ $(OPKG) install --force-maintainer --force-reinstall my-default-settings ++ $(OPKG) install --force-maintainer --force-reinstall my-default-settings 2>/dev/null else $(APK) add --no-scripts $(firstword $(wildcard $(LINUX_DIR)/libc-*.apk $(PACKAGE_DIR)/libc-*.apk)) $(APK) add --no-scripts $(firstword $(wildcard $(LINUX_DIR)/kernel-*.apk $(PACKAGE_DIR)/kernel-*.apk)) -@@ -237,7 +267,7 @@ prepare_rootfs: FORCE +@@ -237,7 +277,7 @@ prepare_rootfs: FORCE @echo @echo Finalizing root filesystem... @@ -151,12 +145,12 @@ ifeq ($(CONFIG_USE_APK),) $(if $(CONFIG_SIGNATURE_CHECK), \ $(if $(ADD_LOCAL_KEY), \ -@@ -254,16 +284,19 @@ else +@@ -254,16 +294,19 @@ else ) endif $(call prepare_rootfs,$(TARGET_DIR),$(USER_FILES),$(DISABLED_SERVICES)) + $(if $(SMALL_FLASH), \ -+ $(shell echo "`grep kwrt_kiddin9 $(TOPDIR)/repositories.conf | sed -e 's/kiddin9/small_flash/g'`" >>$(BUILD_DIR)/root-*/etc/opkg/distfeeds.conf) \ ++ $(shell echo "`grep kwrt_kiddin9 $(TOPDIR)/repositories.conf | sed -e 's/kiddin9/small_flash/g'`" >>$(BUILD_DIR)/root-*/etc/opkg/distfeeds.conf) \ + ) build_image: FORCE diff --git a/devices/common/patches/kernel_version.patch b/devices/common/patches/kernel_version.patch deleted file mode 100644 index 46cbf02a7a38..000000000000 --- a/devices/common/patches/kernel_version.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/scripts/json_overview_image_info.py -+++ b/scripts/json_overview_image_info.py -@@ -47,7 +47,7 @@ def get_initial_output(image_info): - - - if output: -- default_packages, output["arch_packages"] = run( -+ default_packages, output["arch_packages"], output["kernel_version"] = run( - [ - "make", - "--no-print-directory", -@@ -55,6 +55,7 @@ def get_initial_output(image_info): - "target/linux/", - "val.DEFAULT_PACKAGES", - "val.ARCH_PACKAGES", -+ "val.LINUX_VERSION", - "V=s", - ], - stdout=PIPE, diff --git a/devices/common/patches/luci-base.patch b/devices/common/patches/luci-base.patch new file mode 100644 index 000000000000..9a3aec07a83c --- /dev/null +++ b/devices/common/patches/luci-base.patch @@ -0,0 +1,187 @@ +--- a/package/feeds/luci/luci-base/root/usr/share/rpcd/ucode/luci ++++ b/package/feeds/luci/luci-base/root/usr/share/rpcd/ucode/luci +@@ -192,6 +192,7 @@ const methods = { + + getFeatures: { + call: function() { ++ let kernel_version = popen('echo -n `uname -r`').read('all'); + let result = { + firewall: access('/sbin/fw3') == true, + firewall4: access('/sbin/fw4') == true, +@@ -199,6 +200,7 @@ const methods = { + bonding: access('/sys/module/bonding'), + mii_tool: access('/usr/sbin/mii-tool'), + offloading: access('/sys/module/xt_FLOWOFFLOAD/refcnt') == true || access('/sys/module/nft_flow_offload/refcnt') == true, ++ fullcone: access(`/lib/modules/${kernel_version}/xt_FULLCONENAT.ko`) == true || access(`/lib/modules/${kernel_version}/nft_fullcone.ko`) == true, + br2684ctl: access('/usr/sbin/br2684ctl') == true, + swconfig: access('/sbin/swconfig') == true, + odhcpd: access('/usr/sbin/odhcpd') == true, +@@ -538,6 +540,99 @@ const methods = { + call: function() { + return { result: process_list() }; + } ++ }, ++ ++ getCPUBench: { ++ call: function() { ++ return { cpubench: readfile('/etc/bench.log') || '' }; ++ } ++ }, ++ ++ getCPUInfo: { ++ call: function() { ++ if (!access('/sbin/cpuinfo')) ++ return {}; ++ ++ const fd = popen('/sbin/cpuinfo'); ++ if (fd) { ++ let cpuinfo = fd.read('all'); ++ fd.close(); ++ ++ return { cpuinfo: cpuinfo }; ++ } else { ++ return { cpuinfo: error() }; ++ } ++ } ++ }, ++ ++ getCPUUsage: { ++ call: function() { ++ const fd = popen('top -n1 | awk \'/^CPU/ {printf("%d%", 100 - $8)}\''); ++ if (fd) { ++ let cpuusage = fd.read('all'); ++ fd.close(); ++ ++ return { cpuusage: cpuusage }; ++ } else { ++ return { cpuusage: error() }; ++ } ++ } ++ }, ++ ++ getETHInfo: { ++ call: function() { ++ if (!access('/sbin/ethinfo')) ++ return {}; ++ ++ const fd = popen('/sbin/ethinfo'); ++ if (fd) { ++ let ethinfo = fd.read('all'); ++ if (!ethinfo) ++ ethinfo = '{}'; ++ ethinfo = json(ethinfo); ++ fd.close(); ++ ++ return { ethinfo: ethinfo }; ++ } else { ++ return { ethinfo: error() }; ++ } ++ } ++ }, ++ ++ getTempInfo: { ++ call: function() { ++ if (!access('/sbin/tempinfo')) ++ return {}; ++ ++ const fd = popen('/sbin/tempinfo'); ++ if (fd) { ++ let tempinfo = fd.read('all'); ++ fd.close(); ++ ++ return { tempinfo: tempinfo }; ++ } else { ++ return { tempinfo: error() }; ++ } ++ } ++ }, ++ ++ getOnlineUsers: { ++ call: function() { ++ const fd = open('/proc/net/arp', 'r'); ++ if (fd) { ++ let onlineusers = 0; ++ ++ for (let line = fd.read('line'); length(line); line = fd.read('line')) ++ if (match(trim(line), /^.*(0x2).*(br-lan)$/)) ++ onlineusers++; ++ ++ fd.close(); ++ ++ return { onlineusers: onlineusers }; ++ } else { ++ return { onlineusers: error() }; ++ } ++ } + } + }; + + +--- a/package/feeds/luci/luci-base/htdocs/luci-static/resources/network.js ++++ b/package/feeds/luci/luci-base/htdocs/luci-static/resources/network.js +@@ -4376,4 +4376,10 @@ WifiNetwork = baseclass.extend(/** @lends LuCI.network.WifiNetwork.prototype */ + } + }); + ++setTimeout(function(){ ++try{ ++ document.getElementsByClassName('cbi-button-apply')[0].children[3].children[0].value='1' ++}catch(err) { ++}},1000) ++ + return Network; + +--- a/package/feeds/luci/luci-base/ucode/dispatcher.uc ++++ b/package/feeds/luci/luci-base/ucode/dispatcher.uc +@@ -939,7 +939,12 @@ dispatch = function(_http, path) { + let cookie_name = (http.getenv('HTTPS') == 'on') ? 'sysauth_https' : 'sysauth_http', + cookie_secure = (http.getenv('HTTPS') == 'on') ? '; secure' : ''; + +- http.header('Set-Cookie', `${cookie_name}=${session.sid}; path=${build_url()}; SameSite=strict; HttpOnly${cookie_secure}`); ++ let cookie_p = uci.get('wizard', 'default', 'cookie_p'); ++ if (cookie_p == '0') { ++ http.header('Set-Cookie', `${cookie_name}=${session.sid}; path=${build_url()}; SameSite=strict; HttpOnly${cookie_secure}`); ++ } else { ++ http.header('Set-Cookie', `${cookie_name}=${session.sid}; Max-Age=2147483647; path=${build_url()}; SameSite=strict; HttpOnly${cookie_secure}`); ++ } + http.redirect(build_url(...resolved.ctx.request_path)); + + return; + +--- a/package/feeds/luci/luci-base/root/www/index.html ++++ b/package/feeds/luci/luci-base/root/www/index.html +@@ -15,6 +15,5 @@ + + + +- LuCI - Lua Configuration Interface + + + +--- a/package/feeds/luci/luci-base/htdocs/luci-static/resources/ui.js ++++ b/package/feeds/luci/luci-base/htdocs/luci-static/resources/ui.js +@@ -3129,12 +3129,6 @@ var UIMenu = baseclass.singleton(/** @lends LuCI.ui.menu.prototype */ { + + for (var i = 0; root != null && i < path.length; i++) + root = L.isObject(root.children) ? root.children[path[i]] : null; +- +- if (root) +- subnode = Object.assign({}, subnode, { +- children: root.children, +- action: root.action +- }); + } + + children.push(subnode); + +--- a/package/feeds/luci/luci-base/root/etc/init.d/ucitrack ++++ b/package/feeds/luci/luci-base/root/etc/init.d/ucitrack +@@ -8,7 +8,7 @@ register_init() { + local init="$2" + shift; shift + +- if [ -x "$init" ] && "$init" enabled && ! grep -sqE 'USE_PROCD=.' "$init"; then ++ if [ -x "$init" ] && "$init" enabled && ! grep -sq 'procd_add_reload_trigger' "$init"; then + logger -t "ucitrack" "Setting up /etc/config/$config reload trigger for non-procd $init" + procd_add_config_trigger "config.change" "$config" "$init" "$@" + fi diff --git a/devices/common/patches/luci-dhcp.patch b/devices/common/patches/luci-dhcp.patch new file mode 100644 index 000000000000..18253e38e81d --- /dev/null +++ b/devices/common/patches/luci-dhcp.patch @@ -0,0 +1,39 @@ +--- a/package/feeds/luci/luci-mod-network/htdocs/luci-static/resources/view/network/dhcp.js ++++ b/package/feeds/luci/luci-mod-network/htdocs/luci-static/resources/view/network/dhcp.js +@@ -337,6 +337,25 @@ return view.extend({ + s.tab('mxhosts', _('MX')); + s.tab('cnamehosts', _('CNAME')); + s.tab('pxe_tftp', _('PXE/TFTP')); ++ s.tab('custom_domain', _('Custom Redirect Domain')); ++ ++ o = s.taboption('custom_domain', form.SectionValue, 'domain', form.GridSection, 'domain', null, ++ _('Define a custom domain name and the corresponding PTR record')); ++ ++ ss = o.subsection; ++ ss.addremove = true; ++ ss.anonymous = true; ++ ++ so = ss.option(form.Value, 'name', _('Domain Name')); ++ so.datatype = 'hostname'; ++ so.rmempty = false; ++ ++ so = ss.option(form.Value, 'ip', _('IPv4-Address')); ++ so.datatype = 'or(ip4addr,"ignore")'; ++ so.rmempty = false; ++ ++ so = ss.option(form.Value, 'comments', _('Comments')); ++ so.rmempty = true; + + s.taboption('filteropts', form.Flag, 'domainneeded', + _('Domain required'), +@@ -347,6 +366,10 @@ return view.extend({ + _('Authoritative'), + _('This is the only DHCP server in the local network.')); + ++ s.taboption('general', form.Flag, 'dns_redirect', ++ _('DNS redirect'), ++ _('Force redirect all local DNS queries to DNSMasq, a.k.a. DNS Hijacking.')); ++ + o = s.taboption('general', form.Value, 'local', + _('Resolve these locally'), + _('Never forward these matching domains or subdomains; resolve from DHCP or hosts files only.')); diff --git a/devices/common/patches/luci-mod-system.patch b/devices/common/patches/luci-mod-system.patch new file mode 100644 index 000000000000..d5564f21084a --- /dev/null +++ b/devices/common/patches/luci-mod-system.patch @@ -0,0 +1,21 @@ +--- a/package/feeds/luci/luci-mod-system/htdocs/luci-static/resources/view/system/flash.js ++++ b/package/feeds/luci/luci-mod-system/htdocs/luci-static/resources/view/system/flash.js +@@ -261,6 +261,7 @@ return view.extend({ + body.push(E('p', {}, E('label', { 'class': 'btn' }, [ + opts.backup_pkgs[0], ' ', _('Include in backup a list of current installed packages at /etc/backup/installed_packages.txt') + ]))); ++ opts.backup_pkgs[0].checked = true; + }; + + var cntbtn = E('button', { +@@ -302,6 +303,10 @@ return view.extend({ + opts.keep[0].addEventListener('change', function(ev) { + opts.skip_orig[0].disabled = !ev.target.checked; + opts.backup_pkgs[0].disabled = !ev.target.checked; ++ if (ev.target.checked == false){ ++ opts.skip_orig[0].checked =false ++ opts.backup_pkgs[0].checked =false ++ } + + }); + diff --git a/devices/common/patches/nftables.patch b/devices/common/patches/nftables.patch new file mode 100644 index 000000000000..d647a361783f --- /dev/null +++ b/devices/common/patches/nftables.patch @@ -0,0 +1,10 @@ +--- a/package/network/utils/nftables/Makefile ++++ b/package/network/utils/nftables/Makefile +@@ -48,7 +48,6 @@ define Package/nftables-nojson + TITLE+= no JSON support + VARIANT:=nojson + DEFAULT_VARIANT:=1 +- CONFLICTS:=nftables-json + endef + + define Package/nftables-json diff --git a/devices/common/patches/status.patch b/devices/common/patches/status.patch new file mode 100644 index 000000000000..675b33787d0a --- /dev/null +++ b/devices/common/patches/status.patch @@ -0,0 +1,140 @@ +--- a/package/feeds/luci/luci-mod-status/htdocs/luci-static/resources/view/status/include/20_memory.js ++++ b/package/feeds/luci/luci-mod-status/htdocs/luci-static/resources/view/status/include/20_memory.js +@@ -32,8 +32,7 @@ return baseclass.extend({ + swap = L.isObject(systeminfo.swap) ? systeminfo.swap : {}; + + var fields = [ +- _('Total Available'), (mem.available) ? mem.available : (mem.total && mem.free && mem.buffered) ? mem.free + mem.buffered : null, mem.total, +- _('Used'), (mem.total && mem.free) ? (mem.total - mem.free) : null, mem.total, ++ _('Used'), (mem.total && mem.available) ? (mem.total - mem.free - mem.buffered - mem.cached) : null, mem.total, + ]; + + if (mem.buffered) +@@ -43,9 +42,9 @@ return baseclass.extend({ + fields.push(_('Cached'), mem.cached, mem.total); + + if (swap.total > 0) +- fields.push(_('Swap free'), swap.free, swap.total); ++ fields.push(_('Swap used'), swap.total - swap.free, swap.total); + +- var table = E('table', { 'class': 'table' }); ++ var table = E('table', { 'class': 'table memory' }); + + for (var i = 0; i < fields.length; i += 3) { + table.appendChild(E('tr', { 'class': 'tr' }, [ + +--- a/package/feeds/luci/luci-mod-status/root/usr/share/rpcd/acl.d/luci-mod-status.json ++++ b/package/feeds/luci/luci-mod-status/root/usr/share/rpcd/acl.d/luci-mod-status.json +@@ -3,7 +3,7 @@ + "description": "Grant access to realtime statistics", + "read": { + "ubus": { +- "luci": [ "getConntrackList", "getRealtimeStats" ], ++ "luci": [ "getConntrackList", "getRealtimeStats", "getCPUBench", "getCPUUsage", "getOnlineUsers" ], + "network.rrdns": [ "lookup" ] + } + } + +--- a/package/feeds/luci/luci-mod-status/htdocs/luci-static/resources/view/status/include/10_system.js ++++ b/package/feeds/luci/luci-mod-status/htdocs/luci-static/resources/view/status/include/10_system.js +@@ -18,6 +18,21 @@ var callSystemInfo = rpc.declare({ + method: 'info' + }); + ++var callCPUBench = rpc.declare({ ++ object: 'luci', ++ method: 'getCPUBench' ++}); ++ ++var callCPUInfo = rpc.declare({ ++ object: 'luci', ++ method: 'getCPUInfo' ++}); ++ ++var callTempInfo = rpc.declare({ ++ object: 'luci', ++ method: 'getTempInfo' ++}); ++ + return baseclass.extend({ + title: _('System'), + +@@ -25,6 +45,9 @@ return baseclass.extend({ + return Promise.all([ + L.resolveDefault(callSystemBoard(), {}), + L.resolveDefault(callSystemInfo(), {}), ++ L.resolveDefault(callCPUBench(), {}), ++ L.resolveDefault(callCPUInfo(), {}), ++ L.resolveDefault(callTempInfo(), {}), + L.resolveDefault(callLuciVersion(), { revision: _('unknown version'), branch: 'LuCI' }) + ]); + }, +@@ -32,7 +56,10 @@ return baseclass.extend({ + render: function(data) { + var boardinfo = data[0], + systeminfo = data[1], +- luciversion = data[2]; ++ cpubench = data[2], ++ cpuinfo = data[3], ++ tempinfo = data[4], ++ luciversion = data[5]; + + luciversion = luciversion.branch + ' ' + luciversion.revision; + +@@ -53,8 +81,6 @@ return baseclass.extend({ + + var fields = [ + _('Hostname'), boardinfo.hostname, +- _('Model'), boardinfo.model, +- _('Architecture'), boardinfo.system, + _('Target Platform'), (L.isObject(boardinfo.release) ? boardinfo.release.target : ''), + _('Firmware Version'), (L.isObject(boardinfo.release) ? boardinfo.release.description + ' / ' : '') + (luciversion || ''), + _('Kernel Version'), boardinfo.kernel, +@@ -67,6 +93,24 @@ return baseclass.extend({ + ) : null + ]; + ++ if (tempinfo.tempinfo) { ++ fields.splice(6, 0, _('Temperature')); ++ fields.splice(7, 0, tempinfo.tempinfo); ++ } ++ if (boardinfo.model == "Default string Default string") { ++ if (cpuinfo.cpuinfo) { ++ fields.splice(2, 0, _('Architecture')); ++ fields.splice(3, 0, cpuinfo.cpuinfo + cpubench.cpubench); ++ } ++ } else { ++ fields.splice(2, 0, _('Model')); ++ fields.splice(3, 0, boardinfo.model + cpubench.cpubench); ++ if (cpuinfo.cpuinfo) { ++ fields.splice(4, 0, _('Architecture')); ++ fields.splice(5, 0, cpuinfo.cpuinfo); ++ } ++ } ++ + var table = E('table', { 'class': 'table' }); + + for (var i = 0; i < fields.length; i += 2) { + +--- a/package/feeds/luci/luci-mod-status/htdocs/luci-static/resources/view/status/nftables.js ++++ b/package/feeds/luci/luci-mod-status/htdocs/luci-static/resources/view/status/nftables.js +@@ -675,7 +675,6 @@ return view.extend({ + checkLegacyRules: function(ipt4save, ipt6save) { + if (ipt4save.match(/\n-A /) || ipt6save.match(/\n-A /)) { + ui.addNotification(_('Legacy rules detected'), [ +- E('p', _('There are legacy iptables rules present on the system. Mixing iptables and nftables rules is discouraged and may lead to incomplete traffic filtering.')), + E('button', { + 'class': 'btn cbi-button', + 'click': function() { location.href = 'nftables/iptables' } + +--- a/package/feeds/luci/luci-mod-status/htdocs/luci-static/resources/view/status/include/29_ports.js ++++ b/package/feeds/luci/luci-mod-status/htdocs/luci-static/resources/view/status/include/29_ports.js +@@ -309,8 +309,6 @@ return baseclass.extend({ + }, + + render: function(data) { +- if (L.hasSystemFeature('swconfig')) +- return null; + + var board = JSON.parse(data[1]), + known_ports = [], diff --git a/devices/common/patches/syncdial.patch b/devices/common/patches/syncdial.patch new file mode 100644 index 000000000000..e717432b92eb --- /dev/null +++ b/devices/common/patches/syncdial.patch @@ -0,0 +1,30 @@ +--- a/package/network/services/ppp/Makefile ++++ b/package/network/services/ppp/Makefile +@@ -39,7 +39,7 @@ endef + + define Package/ppp + $(call Package/ppp/Default) +- DEPENDS:=+kmod-ppp ++ DEPENDS:=+kmod-ppp +libpthread +shellsync +kmod-mppe + TITLE:=PPP daemon + VARIANT:=default + endef + +--- a/package/network/services/ppp/files/ppp.sh ++++ b/package/network/services/ppp/files/ppp.sh +@@ -233,7 +233,15 @@ proto_pppoe_setup() { + json_get_var padi_attempts padi_attempts + json_get_var padi_timeout padi_timeout + ++ syncppp_option="" ++ [ "$(uci get syncdial.config.enabled)" -eq "1" ] && { ++ ppp_if_cnt=$(uci show network | grep -c "\.proto=\'pppoe\'$") ++ syncppp_option="syncppp $ppp_if_cnt" ++ shellsync $ppp_if_cnt 10 ++ } ++ + ppp_generic_setup "$config" \ ++ $syncppp_option \ + plugin pppoe.so \ + ${ac:+rp_pppoe_ac "$ac"} \ + ${service:+rp_pppoe_service "$service"} \ diff --git a/devices/common/patches/usb-audio.patch b/devices/common/patches/usb-audio.patch deleted file mode 100644 index 488918495e4f..000000000000 --- a/devices/common/patches/usb-audio.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/package/kernel/linux/modules/usb.mk -+++ b/package/kernel/linux/modules/usb.mk -@@ -576,6 +576,7 @@ define KernelPackage/usb-audio - CONFIG_SND_USB_AUDIO - $(call AddDepends/usb) - $(call AddDepends/sound) -+ DEPENDS+=+kmod-media-controller - FILES:= \ - $(LINUX_DIR)/sound/usb/snd-usbmidi-lib.ko \ - $(LINUX_DIR)/sound/usb/snd-usb-audio.ko diff --git a/devices/common/patches/wifi-scripts.patch b/devices/common/patches/wifi-scripts.patch new file mode 100644 index 000000000000..4094b64d1ede --- /dev/null +++ b/devices/common/patches/wifi-scripts.patch @@ -0,0 +1,18 @@ +--- a/package/network/config/wifi-scripts/files/lib/wifi/mac80211.uc ++++ b/package/network/config/wifi-scripts/files/lib/wifi/mac80211.uc +@@ -98,13 +98,13 @@ set ${s}.channel='${channel}' + set ${s}.htmode='${htmode}' + set ${s}.country='${country || ''}' + set ${s}.num_global_macaddr='${num_global_macaddr || ''}' +-set ${s}.disabled='${defaults ? 0 : 1}' ++set ${s}.disabled='0' + + set ${si}=wifi-iface + set ${si}.device='${name}' + set ${si}.network='lan' + set ${si}.mode='ap' +-set ${si}.ssid='${defaults?.ssid || "OpenWrt"}' ++set ${si}.ssid='${defaults?.ssid || "Kwrt"}' + set ${si}.encryption='${defaults?.encryption || "none"}' + set ${si}.key='${defaults?.key || ""}' + diff --git a/devices/common/patches/wireless.patch b/devices/common/patches/wireless.patch new file mode 100644 index 000000000000..e21341734f48 --- /dev/null +++ b/devices/common/patches/wireless.patch @@ -0,0 +1,101 @@ +--- a/package/feeds/luci/luci-mod-network/htdocs/luci-static/resources/view/network/wireless.js ++++ b/package/feeds/luci/luci-mod-network/htdocs/luci-static/resources/view/network/wireless.js +@@ -944,6 +944,10 @@ return view.extend({ + o = ss.taboption('general', form.Flag, 'legacy_rates', _('Allow legacy 802.11b rates'), _('Legacy or badly behaving devices may require legacy 802.11b rates to interoperate. Airtime efficiency may be significantly reduced where these are used. It is recommended to not allow 802.11b rates where possible.')); + o.depends({'_freq': '2g', '!contains': true}); + ++ o = ss.taboption("advanced", form.Flag, 'mu_beamformer', _('MU-MIMO')); ++ o.rmempty = false; ++ o.default = '0'; ++ + o = ss.taboption('general', CBIWifiTxPowerValue, 'txpower', _('Maximum transmit power'), _('Specifies the maximum transmit power the wireless radio may use. Depending on regulatory requirements and wireless usage, the actual transmit power may be reduced by the driver.')); + o.wifiNetwork = radioNet; + +@@ -975,6 +979,9 @@ return view.extend({ + o.datatype = 'range(15,65535)'; + o.placeholder = 100; + o.rmempty = true; ++ ++ o = ss.taboption('advanced', form.Flag, 'vendor_vht', _('Enable 256-QAM'), _('802.11n 2.4Ghz Only')); ++ o.default = o.disabled; + } + + +@@ -1069,6 +1076,68 @@ return view.extend({ + }; + + if (hwtype == 'mac80211') { ++ // Probe 802.11k support ++ o = ss.taboption('encryption', form.Flag, 'ieee80211k', _('802.11k'), _('Enables The 802.11k standard provides information to discover the best available access point')); ++ o.depends({ mode : 'ap', encryption : 'wpa' }); ++ o.depends({ mode : 'ap', encryption : 'wpa2' }); ++ o.depends({ mode : 'ap-wds', encryption : 'wpa' }); ++ o.depends({ mode : 'ap-wds', encryption : 'wpa2' }); ++ o.depends({ mode : 'ap', encryption : 'psk' }); ++ o.depends({ mode : 'ap', encryption : 'psk2' }); ++ o.depends({ mode : 'ap', encryption : 'psk-mixed' }); ++ o.depends({ mode : 'ap-wds', encryption : 'psk' }); ++ o.depends({ mode : 'ap-wds', encryption : 'psk2' }); ++ o.depends({ mode : 'ap-wds', encryption : 'psk-mixed' }); ++ o.rmempty = true; ++ ++ o = ss.taboption('encryption', form.Flag, 'rrm_neighbor_report', _('Enable neighbor report via radio measurements')); ++ o.default = o.enabled; ++ o.depends({ ieee80211k : '1' }); ++ o.rmempty = true; ++ ++ o = ss.taboption('encryption', form.Flag, 'rrm_beacon_report', _('Enable beacon report via radio measurements')); ++ o.default = o.enabled; ++ o.depends({ ieee80211k : '1' }); ++ o.rmempty = true; ++ // End of 802.11k options ++ ++ // Probe 802.11v support ++ o = ss.taboption('encryption', form.Flag, 'ieee80211v', _('802.11v'), _('Enables 802.11v allows client devices to exchange information about the network topology,tating overall improvement of the wireless network.')); ++ o.depends({ mode : 'ap', encryption : 'wpa' }); ++ o.depends({ mode : 'ap', encryption : 'wpa2' }); ++ o.depends({ mode : 'ap-wds', encryption : 'wpa' }); ++ o.depends({ mode : 'ap-wds', encryption : 'wpa2' }); ++ o.depends({ mode : 'ap', encryption : 'psk' }); ++ o.depends({ mode : 'ap', encryption : 'psk2' }); ++ o.depends({ mode : 'ap', encryption : 'psk-mixed' }); ++ o.depends({ mode : 'ap-wds', encryption : 'psk' }); ++ o.depends({ mode : 'ap-wds', encryption : 'psk2' }); ++ o.depends({ mode : 'ap-wds', encryption : 'psk-mixed' }); ++ o.rmempty = true; ++ ++ ++ o = ss.taboption('encryption', form.Flag, 'wnm_sleep_mode', _('extended sleep mode for stations')); ++ o.default = o.disabled; ++ o.depends({ ieee80211v : '1' }); ++ o.rmempty = true; ++ ++ o = ss.taboption('encryption', form.Flag, 'bss_transition', _('BSS Transition Management')); ++ o.default = o.disabled; ++ o.depends({ ieee80211v : '1' }); ++ o.rmempty = true; ++ ++ o = ss.taboption('encryption', form.ListValue, 'time_advertisement', _('Time advertisement')); ++ o.depends({ ieee80211v : '1' }); ++ o.value('0', _('disabled')); ++ o.value('2', _('UTC time at which the TSF timer is 0')); ++ o.rmempty = true; ++ ++ o = ss.taboption('encryption', form.Value, 'time_zone', _('time zone'), _('Local time zone as specified in 8.3 of IEEE Std 1003.1-2004')); ++ o.depends({ time_advertisement : '2' }); ++ o.placeholder = 'UTC8'; ++ o.rmempty = true; ++ // End of 802.11v options ++ + var mode = ss.children[0], + bssid = ss.children[5], + encr; +@@ -1254,7 +1323,7 @@ return view.extend({ + + var crypto_modes = []; + +- if (hwtype == 'mac80211') { ++ if (hwtype != 'broadcom') { + var has_supplicant = L.hasSystemFeature('wpasupplicant'), + has_hostapd = L.hasSystemFeature('hostapd'); + diff --git a/devices/ipq40xx_generic/.config b/devices/ipq40xx_generic/.config index abe29db41d33..b1d71a683187 100644 --- a/devices/ipq40xx_generic/.config +++ b/devices/ipq40xx_generic/.config @@ -2,20 +2,15 @@ CONFIG_TARGET_ipq40xx=y CONFIG_TARGET_ipq40xx_generic=y CONFIG_TARGET_MULTI_PROFILE=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_asus_rt-ac42u=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_asus_rt-ac58u=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_p2w_r619ac-128m=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_p2w_r619ac-64m=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_zte_mf286d=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_glinet_gl-b1300=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_glinet_gl-a1300=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_glinet_gl-s1300-emmc=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_linksys_ea6350v3=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_glinet_gl-ap1300=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_linksys_ea8300=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_linksys_mr8300=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_mobipromo_cm520-79f=y -CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_zte_mf289f=y +CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_dlink_dap-2610=n +CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_eagle-pro-ai-m32-a1=n +CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_eagle-pro-ai-r32-a1=n +CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_extreme-networks_ws-ap391x=n +CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_netgear_ex6100v2=n +CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_netgear_ex6150v2=n +CONFIG_TARGET_DEVICE_ipq40xx_generic_DEVICE_zyxel_nbg6617=n + + diff --git a/devices/ipq50xx_arm/.config b/devices/ipq50xx_arm/.config deleted file mode 100644 index f59e561c67ac..000000000000 --- a/devices/ipq50xx_arm/.config +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_TARGET_ipq50xx=y -CONFIG_TARGET_ipq50xx_arm=y -CONFIG_TARGET_MULTI_PROFILE=y -CONFIG_TARGET_ALL_PROFILES=y diff --git a/devices/ipq50xx_arm/diy.sh b/devices/ipq50xx_arm/diy.sh deleted file mode 100644 index 75949522f6d6..000000000000 --- a/devices/ipq50xx_arm/diy.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -shopt -s extglob - -SHELL_FOLDER=$(dirname $(readlink -f "$0")) - -rm -rf package/kernel/qca-* package/boot/uboot-envtools package/firmware/ipq-wifi package/firmware/ath11k-firmware - -git_clone_path ipq50xx-mainline-kernel-5.15-openwrt-23.05 https://github.com/hzyitc/openwrt-redmi-ax3000 target/linux/ipq50xx package/firmware/ipq-wifi package/firmware/ath11k-firmware package/boot/uboot-envtools - -sed -i "s/wpad-basic-wolfssl/wpad-basic-mbedtls/" target/linux/ipq50xx/Makefile \ No newline at end of file diff --git a/devices/ipq50xx_arm/patches/ipq50xx.patch b/devices/ipq50xx_arm/patches/ipq50xx.patch deleted file mode 100644 index 115df1d2004a..000000000000 --- a/devices/ipq50xx_arm/patches/ipq50xx.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/package/kernel/linux/modules/netsupport.mk -+++ b/package/kernel/linux/modules/netsupport.mk -@@ -1604,7 +1604,7 @@ $(eval $(call KernelPackage,qrtr-tun)) - define KernelPackage/qrtr-smd - SUBMENU:=$(NETWORK_SUPPORT_MENU) - TITLE:=SMD IPC Router channels -- DEPENDS:=+kmod-qrtr @TARGET_qualcommax -+ DEPENDS:=+kmod-qrtr @(TARGET_ipq50xx||TARGET_qualcommax) - KCONFIG:=CONFIG_QRTR_SMD - FILES:= $(LINUX_DIR)/net/qrtr/qrtr-smd.ko - AUTOLOAD:=$(call AutoProbe,qrtr-smd) - ---- a/target/linux/generic/files/include/linux/switch.h -+++ b/target/linux/generic/files/include/linux/switch.h -@@ -45,6 +45,9 @@ enum switch_port_speed { - SWITCH_PORT_SPEED_10 = 10, - SWITCH_PORT_SPEED_100 = 100, - SWITCH_PORT_SPEED_1000 = 1000, -+ SWITCH_PORT_SPEED_2500 = 2500, -+ SWITCH_PORT_SPEED_5000 = 5000, -+ SWITCH_PORT_SPEED_10000 = 10000 - }; - - struct switch_port_link { \ No newline at end of file diff --git a/devices/ipq806x_generic/.config b/devices/ipq806x_generic/.config index 44146f7f589e..7345bbc84d38 100644 --- a/devices/ipq806x_generic/.config +++ b/devices/ipq806x_generic/.config @@ -2,18 +2,9 @@ CONFIG_TARGET_ipq806x=y CONFIG_TARGET_ipq806x_generic=y CONFIG_TARGET_MULTI_PROFILE=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_linksys_ea7500-v1=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_linksys_ea8500=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_netgear_d7800=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_netgear_r7500=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_netgear_r7500v2=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_netgear_r7800=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_netgear_xr500=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_tplink_ad7200=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_tplink_c2600=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_tplink_vr2600v=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_buffalo_wxr-2533dhp=y -CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_xiaomi_r3d=y +CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_tplink_ad7200=n +CONFIG_TARGET_DEVICE_ipq806x_generic_DEVICE_tplink_c2600=n + CONFIG_PACKAGE_MAC80211_NSS_SUPPORT=y diff --git a/devices/mediatek_filogic/.config b/devices/mediatek_filogic/.config index 3e545266615a..df6d0825911c 100644 --- a/devices/mediatek_filogic/.config +++ b/devices/mediatek_filogic/.config @@ -3,6 +3,9 @@ CONFIG_TARGET_mediatek=y CONFIG_TARGET_mediatek_filogic=y CONFIG_TARGET_MULTI_PROFILE=y CONFIG_TARGET_ALL_PROFILES=y +CONFIG_TARGET_DEVICE_mediatek_filogic_DEVICE_cudy_re3000-v1=n +CONFIG_TARGET_DEVICE_mediatek_filogic_DEVICE_cudy_wr3000-v1=n +CONFIG_TARGET_DEVICE_mediatek_filogic_DEVICE_yuncore_ax835=n CONFIG_PACKAGE_kmod-pcie_mhi=m diff --git a/devices/mediatek_filogic/diy.sh b/devices/mediatek_filogic/diy.sh index 7ede84096dc5..83f503133f21 100644 --- a/devices/mediatek_filogic/diy.sh +++ b/devices/mediatek_filogic/diy.sh @@ -10,8 +10,6 @@ sed -i '/bootargs-.* = " root=\/dev\/fit0 rootwait";/d' target/linux/mediatek/dt sed -i "s/-stock//g" package/boot/uboot-envtools/files/mediatek_filogic sed -i "s/-stock//g" target/linux/mediatek/filogic/base-files/etc/board.d/01_leds sed -i "s/-stock//g" target/linux/mediatek/filogic/base-files/etc/board.d/02_network -sed -i "s/-stock//g" target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh sed -i "s/-stock//g" target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface sed -i "s/openwrt-mediatek-filogic/kwrt-mediatek-filogic/g" target/linux/mediatek/image/filogic.mk - diff --git a/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981-kst-wf3000a.dts b/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981-kst-wf3000a.dts new file mode 100644 index 000000000000..bb40cd6c7be1 --- /dev/null +++ b/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981-kst-wf3000a.dts @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023 Tianling Shen + */ + +/dts-v1/; +#include +#include + +#include "mt7981.dtsi" + +/ { + model = "KST-WF3000A"; + compatible = "kst,wf3000a", "mediatek,mt7981"; + + aliases { + led-boot = &status_red_led; + led-failsafe = &status_red_led; + led-running = &status_green_led; + led-upgrade = &status_blue_led; + }; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 earlycon=uart8250,mmio32,0x11002000"; + }; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_red_led: led-0 { + label = "red:status"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + status_green_led: led-1 { + label = "green:status"; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + status_blue_led: led-2 { + label = "blue:status"; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + }; + + + nmbm_spim_nand { + compatible = "generic,nmbm"; + + #address-cells = <1>; + #size-cells = <1>; + + lower-mtd-device = <&spi_nand>; + forced-create; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x100000>; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7200000>; + }; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <8>; + bias-pull-up = <103>; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <8>; + bias-pull-down = <103>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981-sl-3000-emmc.dts b/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981-sl-3000-emmc.dts new file mode 100644 index 000000000000..745818bb9896 --- /dev/null +++ b/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981-sl-3000-emmc.dts @@ -0,0 +1,185 @@ +/dts-v1/; +#include "mt7981.dtsi" + +/ { + model = "SL-3000 eMMC bootstrap version"; + compatible = "sl,3000-emmc", "mediatek,mt7981"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11002000 \ + root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; + }; + + aliases { + led-boot = &status_red_led; + led-failsafe = &status_red_led; + led-running = &status_green_led; + led-upgrade = &status_blue_led; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + status_red_led: led-0 { + label = "red:status"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + status_green_led: led-1 { + label = "green:status"; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + status_blue_led: led-2 { + label = "blue:status"; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + mesh { + label = "mesh"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&xhci { + mediatek,u3p-dis-msk = <0x0>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + status = "okay"; +}; + +&mmc0 { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <52000000>; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&pio { + mmc0_pins_default: mmc0-pins-default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_uhs: mmc0-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; +}; diff --git a/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981-sl-3000.dts b/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981-sl-3000.dts new file mode 100644 index 000000000000..2148872db48a --- /dev/null +++ b/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981-sl-3000.dts @@ -0,0 +1,269 @@ +/dts-v1/; +#include "mt7981.dtsi" + +/ { + model = "SL-3000"; + compatible = "sl,3000", "mediatek,mt7981"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11002000 \ + root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; + }; + + aliases { + led-boot = &status_red_led; + led-failsafe = &status_red_led; + led-running = &status_green_led; + led-upgrade = &status_blue_led; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + status_red_led: led-0 { + label = "red:status"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + status_green_led: led-1 { + label = "green:status"; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + status_blue_led: led-2 { + label = "blue:status"; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + mesh { + label = "mesh"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + spi_nor@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 < + 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ + spi-cal-addrlen = <1>; + spi-cal-addr = /bits/ 32 <0x0>; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partition@00000 { + label = "BL2"; + reg = <0x00000 0x0100000>; + }; + partition@100000 { + label = "Config"; + reg = <0x100000 0x080000>; + }; + partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + }; + partition@380000 { + label = "FIP"; + reg = <0x380000 0x0200000>; + }; + partition@580000 { + label = "firmware"; + reg = <0x580000 0x1900000>; + }; + partition@1E80000 { + label = "Product"; + reg = <0x1E80000 0x20000>; + }; + partition@1EA0000 { + label = "Custom"; + reg = <0x1EA0000 0x160000>; + }; + }; +}; + +&mmc0 { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <52000000>; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&pio { + spic_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1_1"; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + + mmc0_pins_default: mmc0-pins-default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_uhs: mmc0-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; +}; + +&wed { + dy_txbm_enable = "true"; + dy_txbm_budget = <8>; + txbm_init_sz = <8>; + txbm_max_sz = <32>; + status = "okay"; +}; diff --git a/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t-an8855.dts b/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t-an8855.dts new file mode 100644 index 000000000000..6131151e9513 --- /dev/null +++ b/devices/mediatek_filogic/diy/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t-an8855.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-ax3000t.dts" + +/ { + model = "Xiaomi Mi Router AX3000T with AN8855"; + compatible = "xiaomi,mi-router-ax3000t-an8855", "mediatek,mt7981"; + + gsw_an8855: gsw@1 { + compatible = "airoha,an8855"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; +}; + + diff --git a/devices/mediatek_filogic/patches/08-cmcc_rax3000m.patch b/devices/mediatek_filogic/patches/08-cmcc_rax3000m.patch index e81b87656db6..ced17d90cd0e 100644 --- a/devices/mediatek_filogic/patches/08-cmcc_rax3000m.patch +++ b/devices/mediatek_filogic/patches/08-cmcc_rax3000m.patch @@ -26,12 +26,13 @@ --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata -@@ -24,6 +24,8 @@ case "$FIRMWARE" in +@@ -24,6 +24,9 @@ case "$FIRMWARE" in ;; "mediatek/mt7981_eeprom_mt7976_dbdc.bin") case "$board" in + cmcc,rax3000m-emmc|\ + cmcc,xr30-emmc|\ ++ sl,3000-emmc |\ ubnt,unifi-6-plus) caldata_extract_mmc "factory" 0x0 0x1000 ;; @@ -107,18 +108,18 @@ --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh -@@ -114,6 +114,8 @@ platform_do_upgrade() { - yuncore,ax835) - default_do_upgrade "$1" - ;; -+ cmcc,rax3000m-emmc|\ +@@ -95,6 +95,8 @@ platform_do_upgrade() { + acer,predator-w6d|\ + acer,vero-w6m|\ + arcadyan,mozart|\ ++ cmcc,rax3000m-emmc|\ + cmcc,xr30-emmc|\ glinet,gl-mt2500|\ glinet,gl-mt6000|\ glinet,gl-x3000|\ -@@ -204,6 +206,8 @@ platform_copy_config() { - ;; - acer,predator-w6|\ +@@ -206,6 +208,8 @@ platform_copy_config() { + acer,predator-w6d|\ + acer,vero-w6m|\ arcadyan,mozart|\ + cmcc,rax3000m-emmc|\ + cmcc,xr30-emmc|\ diff --git a/devices/mediatek_filogic/patches/17-lc-hx3001.patch b/devices/mediatek_filogic/patches/17-lc-hx3001.patch index cdfa5723d770..64b1dda6622c 100644 --- a/devices/mediatek_filogic/patches/17-lc-hx3001.patch +++ b/devices/mediatek_filogic/patches/17-lc-hx3001.patch @@ -273,9 +273,9 @@ index 0a1f642c70924..fda3d4b98d875 100644 +konka,komi-a31) + ucidef_set_led_netdev "eth1" "eth1" "blue:status" "eth1" "link" + ;; - mercusys,mr90x-v1) - ucidef_set_led_netdev "lan-0" "lan-0" "green:lan-0" "lan0" "link tx rx" - ucidef_set_led_netdev "lan-1" "lan-1" "green:lan-1" "lan1" "link tx rx" + glinet,gl-x3000|\ + glinet,gl-xe3000) + ucidef_set_led_default "power" "POWER" "green:power" "1" diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 61637e09c7f0e..4048eddadb45a 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network diff --git a/devices/mediatek_filogic/patches/21-q3000.patch b/devices/mediatek_filogic/patches/21-q3000.patch index a8b04c41f5e8..9bc0c83ca37b 100644 --- a/devices/mediatek_filogic/patches/21-q3000.patch +++ b/devices/mediatek_filogic/patches/21-q3000.patch @@ -25,21 +25,20 @@ DEVICE_VENDOR := IMOU DEVICE_MODEL := LC-HX3001 - --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds -@@ -42,6 +42,11 @@ h3c,nx30pro) - ucidef_set_led_default "green" "GREEN" "nx30pro:green" "1" - ucidef_set_led_default "red" "RED" "nx30pro:red" "0" +@@ -49,6 +49,11 @@ glinet,gl-xe3000) + ucidef_set_led_netdev "wlan2g" "WLAN2G" "green:wifi2g" "phy0-ap0" + ucidef_set_led_netdev "wlan5g" "WLAN5G" "green:wifi5g" "phy1-ap0" ;; +ikuai,q3000) + ucidef_set_led_default "green" "GREEN" "q3000:green" "1" + ucidef_set_led_default "blue" "BLUE" "q3000:blue" "0" + ucidef_set_led_default "red" "RED" "q3000:red" "0" + ;; - konka,komi-a31) - ucidef_set_led_netdev "blue" "BLUE" "blue:status" "eth1" "link" - ;; + mercusys,mr90x-v1|\ + mercusys,mr90x-v1-ubi) + ucidef_set_led_netdev "lan-0" "lan-0" "green:lan-0" "lan0" "link tx rx" --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -59,6 +58,6 @@ + wan_mac=$(mtd_get_mac_binary $part_name 0x10048) + lan_mac=$(macaddr_add $wan_mac 1) + ;; - mercusys,mr90x-v1) + mercusys,mr90x-v1|\ + tplink,re6000xd) label_mac=$(get_mac_binary "/tmp/tp_data/default-mac" 0) - lan_mac=$label_mac \ No newline at end of file diff --git a/devices/mediatek_filogic/patches/22-netcore-n60.patch b/devices/mediatek_filogic/patches/22-netcore-n60.patch index 4d457e68a876..d8c77b9ef72a 100644 --- a/devices/mediatek_filogic/patches/22-netcore-n60.patch +++ b/devices/mediatek_filogic/patches/22-netcore-n60.patch @@ -22,7 +22,7 @@ --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk -@@ -942,18 +942,10 @@ define Device/netcore_n60 +@@ -1096,18 +1096,11 @@ define Device/netcore_n60 BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_IN_UBI := 1 @@ -38,6 +38,7 @@ - ARTIFACTS := preloader.bin bl31-uboot.fip - ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3 - ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot netcore_n60 ++ IMAGE_SIZE := 112640k + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata diff --git a/devices/mediatek_filogic/patches/25-platform.patch b/devices/mediatek_filogic/patches/25-platform.patch index e6c12d2b362b..9e7bd7636d57 100644 --- a/devices/mediatek_filogic/patches/25-platform.patch +++ b/devices/mediatek_filogic/patches/25-platform.patch @@ -1,6 +1,6 @@ --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh -@@ -64,28 +64,17 @@ platform_do_upgrade() { +@@ -64,28 +64,16 @@ platform_do_upgrade() { local board=$(board_name) case "$board" in @@ -10,22 +10,30 @@ bananapi,bpi-r4|\ bananapi,bpi-r4-poe|\ - cmcc,rax3000m|\ + gatonetworks,gdsp|\ - h3c,magic-nx30-pro|\ - jcg,q30-pro|\ - jdcloud,re-cp-03|\ mediatek,mt7981-rfb|\ mediatek,mt7988a-rfb|\ + mercusys,mr90x-v1-ubi|\ - nokia,ea0326gmp|\ openwrt,one|\ - netcore,n60|\ - qihoo,360t7|\ - tplink,tl-xdr4288|\ - tplink,tl-xdr6086|\ - tplink,tl-xdr6088|\ - tplink,tl-xtr8488|\ -- xiaomi,mi-router-ax3000t-ubootmod|\ -- xiaomi,redmi-router-ax6000-ubootmod|\ -- xiaomi,mi-router-wr30u-ubootmod|\ - zyxel,ex5601-t0-ubootmod) - fit_do_upgrade "$1" + routerich,ax3000-ubootmod|\ +- tplink,tl-xdr4288|\ +- tplink,tl-xdr6086|\ +- tplink,tl-xdr6088|\ +- tplink,tl-xtr8488|\ + xiaomi,mi-router-ax3000t-ubootmod|\ + xiaomi,redmi-router-ax6000-ubootmod|\ + xiaomi,mi-router-wr30u-ubootmod|\ +@@ -150,7 +138,6 @@ platform_do_upgrade() { + ;; + esac ;; +- xiaomi,mi-router-ax3000t|\ + xiaomi,mi-router-wr30u-stock|\ + xiaomi,redmi-router-ax6000-stock) + CI_KERN_UBIPART=ubi_kernel diff --git a/devices/mediatek_filogic/patches/27-tplink-tl-xdr.patch b/devices/mediatek_filogic/patches/27-tplink-tl-xdr.patch index 06e9fad3eeca..49d8cd751441 100644 --- a/devices/mediatek_filogic/patches/27-tplink-tl-xdr.patch +++ b/devices/mediatek_filogic/patches/27-tplink-tl-xdr.patch @@ -76,4 +76,4 @@ - ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot tplink_tl-xdr6088 $(call Device/tplink_tl-xdr-common) endef - TARGET_DEVICES += tplink_tl-xdr6088 \ No newline at end of file + TARGET_DEVICES += tplink_tl-xdr6088 diff --git a/devices/mediatek_filogic/patches/34-sl-3000.patch b/devices/mediatek_filogic/patches/34-sl-3000.patch new file mode 100644 index 000000000000..ee58cace8060 --- /dev/null +++ b/devices/mediatek_filogic/patches/34-sl-3000.patch @@ -0,0 +1,129 @@ +--- a/target/linux/mediatek/image/filogic.mk ++++ b/target/linux/mediatek/image/filogic.mk +@@ -1672,3 +1672,43 @@ define Device/zyxel_nwa50ax-pro + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + endef + TARGET_DEVICES += zyxel_nwa50ax-pro ++ ++define Device/sl_3000 ++ DEVICE_VENDOR := SL ++ DEVICE_MODEL := 3000 ++ DEVICE_DTS := mt7981-sl-3000 ++ DEVICE_DTS_DIR := ../dts ++ SUPPORTED_DEVICES := sl,3000 ++ DEVICE_PACKAGES := $(MT7981_USB_PKGS) f2fsck losetup mkf2fs kmod-fs-f2fs kmod-mmc ++ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata ++endef ++TARGET_DEVICES += sl_3000 ++ ++define Device/sl_3000-emmc ++ DEVICE_VENDOR := SL ++ DEVICE_MODEL := 3000 eMMC ++ DEVICE_DTS := mt7981-sl-3000-emmc ++ DEVICE_DTS_DIR := ../dts ++ SUPPORTED_DEVICES := sl,3000-emmc ++ DEVICE_PACKAGES := $(MT7981_USB_PKGS) f2fsck losetup mkf2fs kmod-fs-f2fs kmod-mmc ++ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata ++endef ++TARGET_DEVICES += sl_3000-emmc ++ ++define Device/kst_wf3000a ++ DEVICE_VENDOR := KST ++ DEVICE_MODEL := WF3000A ++ DEVICE_DTS := mt7981-kst-wf3000a ++ DEVICE_DTS_DIR := ../dts ++ SUPPORTED_DEVICES := kst,wf3000a ++ UBINIZE_OPTS := -E 5 ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ IMAGE_SIZE := 116736k ++ KERNEL_IN_UBI := 1 ++ IMAGES += factory.bin ++ IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) ++ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata ++endef ++TARGET_DEVICES += kst_wf3000a ++ + +--- a/package/boot/uboot-envtools/files/mediatek_filogic ++++ b/package/boot/uboot-envtools/files/mediatek_filogic +@@ -94,6 +94,11 @@ + ;; + esac + ;; ++cmcc,xr30-emmc|\ ++sl,3000|\ ++sl,3000-emmc) ++ ubootenv_add_uci_config "/dev/mmcblk0p1" "0x0" "0x80000" "0x80000" ++ ;; + comfast,cf-e393ax) + ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x80000" + ;; + +--- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh ++++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +@@ -86,6 +86,9 @@ + arcadyan,mozart|\ + cmcc,rax3000m-emmc|\ + cmcc,xr30-emmc|\ ++ cmcc,xr30-emmc |\ ++ *sl,3000* |\ ++ *sl,3000-emmc* |\ + glinet,gl-mt2500|\ + glinet,gl-mt6000|\ + glinet,gl-x3000|\ + +--- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network ++++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +@@ -40,6 +40,8 @@ + ikuai,q3000|\ + jcg,q30-pro|\ + qihoo,360t7|\ ++ kst,wf3000a|\ ++ sl,3000*|\ + routerich,ax3000|\ + routerich,ax3000-ubootmod) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan +@@ -198,6 +200,42 @@ + wan_mac=$label_mac + lan_mac=$(macaddr_add "$label_mac" 1) + ;; ++ sl,3000) ++ local wifi_mac="$(mtd_get_mac_binary Factory 0x04)" ++ wan_mac=$(macaddr_add $wifi_mac -2) ++ lan_mac=$(macaddr_add $wifi_mac -1) ++ local b0dat="$(l1dat if2dat ra0)" ++ local b1dat="$(l1dat if2dat rax0)" ++ if [ -f ${b0dat} ] && ! grep -q "MacAddress=" ${b0dat}; then ++ local b0mac="$(macaddr_add $wifi_mac)" ++ echo "MacAddress=$b0mac" >> ${b0dat} ++ fi ++ if [ -f ${b1dat} ] && ! grep -q "MacAddress=" ${b1dat}; then ++ local b1mac="$(macaddr_add $wifi_mac 1)" ++ echo "MacAddress=$b1mac" >> ${b1dat} ++ fi ++ ;; ++ sl,3000-emmc) ++ local wifi_mac="$(mmc_get_mac_binary factory 0x04)" ++ wan_mac=$(macaddr_add $wifi_mac -2) ++ lan_mac=$(macaddr_add $wifi_mac -1) ++ local b0dat="$(l1dat if2dat ra0)" ++ local b1dat="$(l1dat if2dat rax0)" ++ if [ -f ${b0dat} ] && ! grep -q "MacAddress=" ${b0dat}; then ++ local b0mac="$(macaddr_add $wifi_mac)" ++ echo "MacAddress=$b0mac" >> ${b0dat} ++ fi ++ if [ -f ${b1dat} ] && ! grep -q "MacAddress=" ${b1dat}; then ++ local b1mac="$(macaddr_add $wifi_mac 1)" ++ echo "MacAddress=$b1mac" >> ${b1dat} ++ fi ++ ;; ++ kst,wf3000a|\ ++ newland,nl-wr8103) ++ local wifi_mac=$(mtd_get_mac_binary Factory 0x4) ++ lan_mac=$(macaddr_add $wifi_mac -1) ++ wan_mac=$(macaddr_add $wifi_mac -2) ++ ;; + xiaomi,mi-router-ax3000t|\ + xiaomi,mi-router-ax3000t-ubootmod|\ + xiaomi,mi-router-wr30u|\ diff --git a/devices/mediatek_filogic/patches/AN8855-r241130.patch b/devices/mediatek_filogic/patches/AN8855-r241130.patch new file mode 100644 index 000000000000..805939a5b2e0 --- /dev/null +++ b/devices/mediatek_filogic/patches/AN8855-r241130.patch @@ -0,0 +1,4116 @@ +From 401c3c22aab4b09918b43d09c2e90fea2e4a5841 Mon Sep 17 00:00:00 2001 +From: Dim Fish +Date: Fri, 11 Oct 2024 19:25:29 +0300 +Subject: [PATCH] mediatek: add Airoha AN8855 gigabit switch driver + +New revisions of Xiaomi AX3000T with 1.0.84+ stock firmware contain new hardware. +This commit add support for Airoha AN8855 gigabit switch driver with 6.6 kernel patches + +Based on https://patchwork.kernel.org/project/netdevbpf/cover/20241108132511.18801-1-ansuelsmth@gmail.com/ + +Signed-off-by: Dim Fish +--- + .../dts/mt7981b-xiaomi-mi-router-common.dtsi | 171 ++ + .../files-6.6/drivers/net/dsa/an8855.c | 2585 +++++++++++++++++ + .../files-6.6/drivers/net/dsa/an8855.h | 753 +++++ + .../files-6.6/drivers/net/phy/air_an8855.c | 268 ++ + target/linux/mediatek/filogic/config-6.6 | 2 + + target/linux/mediatek/mt7622/config-6.6 | 2 + + target/linux/mediatek/mt7623/config-6.6 | 2 + + target/linux/mediatek/mt7629/config-6.6 | 2 + + .../737-net-dsa-add-Airoha-AN8855.patch | 197 ++ + 9 files changed, 3982 insertions(+) + create mode 100644 target/linux/mediatek/files-6.6/drivers/net/dsa/an8855.c + create mode 100644 target/linux/mediatek/files-6.6/drivers/net/dsa/an8855.h + create mode 100644 target/linux/mediatek/files-6.6/drivers/net/phy/air_an8855.c + create mode 100644 target/linux/mediatek/patches-6.6/737-net-dsa-add-Airoha-AN8855.patch + +diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi +index d6872395a9017a..8ddc4c20a07cbe 100644 +--- a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi ++++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi +@@ -83,6 +83,14 @@ + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; ++ ++ switch2: switch@1 { ++ compatible = "airoha,an8855"; ++ reg = <1>; ++ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; ++ airoha,ext-surge; ++ #nvmem-cell-cells = <0>; ++ }; + }; + + &switch { +@@ -124,6 +132,169 @@ + }; + }; + ++&switch2 { ++ nvmem-layout { ++ compatible = "fixed-layout"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ shift_sel_port0_tx_a: shift-sel-port0-tx-a@c { ++ reg = <0xc 0x4>; ++ }; ++ ++ shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 { ++ reg = <0x10 0x4>; ++ }; ++ ++ shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 { ++ reg = <0x14 0x4>; ++ }; ++ ++ shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 { ++ reg = <0x18 0x4>; ++ }; ++ ++ shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c { ++ reg = <0x1c 0x4>; ++ }; ++ ++ shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 { ++ reg = <0x20 0x4>; ++ }; ++ ++ shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 { ++ reg = <0x24 0x4>; ++ }; ++ ++ shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 { ++ reg = <0x28 0x4>; ++ }; ++ ++ shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c { ++ reg = <0x2c 0x4>; ++ }; ++ ++ shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 { ++ reg = <0x30 0x4>; ++ }; ++ ++ shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 { ++ reg = <0x34 0x4>; ++ }; ++ ++ shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 { ++ reg = <0x38 0x4>; ++ }; ++ ++ shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c { ++ reg = <0x4c 0x4>; ++ }; ++ ++ shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 { ++ reg = <0x50 0x4>; ++ }; ++ ++ shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 { ++ reg = <0x54 0x4>; ++ }; ++ ++ shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 { ++ reg = <0x58 0x4>; ++ }; ++ }; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ label = "wan"; ++ phy-mode = "internal"; ++ phy-handle = <&internal_phy1>; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ label = "lan2"; ++ phy-mode = "internal"; ++ phy-handle = <&internal_phy2>; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ label = "lan3"; ++ phy-mode = "internal"; ++ phy-handle = <&internal_phy3>; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ label = "lan4"; ++ phy-mode = "internal"; ++ phy-handle = <&internal_phy4>; ++ }; ++ ++ port@5 { ++ reg = <5>; ++ label = "cpu"; ++ ethernet = <&gmac0>; ++ phy-mode = "2500base-x"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ }; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ internal_phy1: phy@1 { ++ reg = <1>; ++ ++ nvmem-cells = <&shift_sel_port0_tx_a>, ++ <&shift_sel_port0_tx_b>, ++ <&shift_sel_port0_tx_c>, ++ <&shift_sel_port0_tx_d>; ++ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; ++ }; ++ ++ internal_phy2: phy@2 { ++ reg = <2>; ++ ++ nvmem-cells = <&shift_sel_port1_tx_a>, ++ <&shift_sel_port1_tx_b>, ++ <&shift_sel_port1_tx_c>, ++ <&shift_sel_port1_tx_d>; ++ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; ++ }; ++ ++ internal_phy3: phy@3 { ++ reg = <3>; ++ ++ nvmem-cells = <&shift_sel_port2_tx_a>, ++ <&shift_sel_port2_tx_b>, ++ <&shift_sel_port2_tx_c>, ++ <&shift_sel_port2_tx_d>; ++ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; ++ }; ++ ++ internal_phy4: phy@4 { ++ reg = <4>; ++ ++ nvmem-cells = <&shift_sel_port3_tx_a>, ++ <&shift_sel_port3_tx_b>, ++ <&shift_sel_port3_tx_c>, ++ <&shift_sel_port3_tx_d>; ++ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; ++ }; ++ }; ++}; ++ + &spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; +diff --git a/target/linux/mediatek/files-6.6/drivers/net/dsa/an8855.c b/target/linux/mediatek/files-6.6/drivers/net/dsa/an8855.c +new file mode 100644 +index 00000000000000..6ce7574255c32d +--- /dev/null ++++ b/target/linux/mediatek/files-6.6/drivers/net/dsa/an8855.c +@@ -0,0 +1,2585 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Airoha AN8855 DSA Switch driver ++ * Copyright (C) 2023 Min Yao ++ * Copyright (C) 2024 Christian Marangi ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "an8855.h" ++ ++static const struct an8855_mib_desc an8855_mib[] = { ++ MIB_DESC(1, AN8855_PORT_MIB_TX_DROP, "TxDrop"), ++ MIB_DESC(1, AN8855_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), ++ MIB_DESC(1, AN8855_PORT_MIB_TX_COLLISION, "TxCollision"), ++ MIB_DESC(1, AN8855_PORT_MIB_TX_OVERSIZE_DROP, "TxOversizeDrop"), ++ MIB_DESC(2, AN8855_PORT_MIB_TX_BAD_PKT_BYTES, "TxBadPktBytes"), ++ MIB_DESC(1, AN8855_PORT_MIB_RX_DROP, "RxDrop"), ++ MIB_DESC(1, AN8855_PORT_MIB_RX_FILTERING, "RxFiltering"), ++ MIB_DESC(1, AN8855_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), ++ MIB_DESC(1, AN8855_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), ++ MIB_DESC(1, AN8855_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), ++ MIB_DESC(1, AN8855_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), ++ MIB_DESC(1, AN8855_PORT_MIB_FLOW_CONTROL_DROP, "FlowControlDrop"), ++ MIB_DESC(1, AN8855_PORT_MIB_WRED_DROP, "WredDrop"), ++ MIB_DESC(1, AN8855_PORT_MIB_MIRROR_DROP, "MirrorDrop"), ++ MIB_DESC(2, AN8855_PORT_MIB_RX_BAD_PKT_BYTES, "RxBadPktBytes"), ++ MIB_DESC(1, AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP, "RxsFlowSamplingPktDrop"), ++ MIB_DESC(1, AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP, "RxsFlowTotalPktDrop"), ++ MIB_DESC(1, AN8855_PORT_MIB_PORT_CONTROL_DROP, "PortControlDrop"), ++}; ++ ++static int an8855_mii_set_page(struct mii_bus *bus, u8 phy_id, u8 page) ++{ ++ int ret; ++ ++ ret = __mdiobus_write(bus, phy_id, AN8855_PHY_SELECT_PAGE, page); ++ if (ret < 0) ++ dev_err_ratelimited(&bus->dev, ++ "failed to set an8855 mii page\n"); ++ ++ return ret; ++} ++ ++static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg, u32 *val) ++{ ++ int lo, hi, ret; ++ ++ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, ++ AN8855_PBUS_MODE_ADDR_FIXED); ++ if (ret < 0) ++ goto err; ++ ++ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH, ++ upper_16_bits(reg)); ++ if (ret < 0) ++ goto err; ++ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW, ++ lower_16_bits(reg)); ++ if (ret < 0) ++ goto err; ++ ++ hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH); ++ if (hi < 0) { ++ ret = hi; ++ goto err; ++ } ++ lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW); ++ if (lo < 0) { ++ ret = lo; ++ goto err; ++ } ++ ++ *val = ((u16)hi << 16) | ((u16)lo & 0xffff); ++ ++ return 0; ++err: ++ dev_err_ratelimited(&bus->dev, ++ "failed to read an8855 register\n"); ++ return ret; ++} ++ ++static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val) ++{ ++ struct an8855_priv *priv = ctx; ++ struct mii_bus *bus = priv->bus; ++ int ret; ++ ++ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ ret = an8855_mii_set_page(bus, priv->phy_base, AN8855_PHY_PAGE_EXTENDED_4); ++ if (ret < 0) ++ goto exit; ++ ++ ret = an8855_mii_read32(bus, priv->phy_base, ++ reg, val); ++ ++exit: ++ an8855_mii_set_page(bus, priv->phy_base, AN8855_PHY_PAGE_STANDARD); ++ mutex_unlock(&bus->mdio_lock); ++ ++ return ret < 0 ? ret : 0; ++} ++ ++static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg, u32 val) ++{ ++ int ret; ++ ++ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, ++ AN8855_PBUS_MODE_ADDR_FIXED); ++ if (ret < 0) ++ goto err; ++ ++ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH, ++ upper_16_bits(reg)); ++ if (ret < 0) ++ goto err; ++ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW, ++ lower_16_bits(reg)); ++ if (ret < 0) ++ goto err; ++ ++ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH, ++ upper_16_bits(val)); ++ if (ret < 0) ++ goto err; ++ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW, ++ lower_16_bits(val)); ++ if (ret < 0) ++ goto err; ++ ++ return 0; ++err: ++ dev_err_ratelimited(&bus->dev, ++ "failed to write an8855 register\n"); ++ return ret; ++} ++ ++static int ++an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val) ++{ ++ struct an8855_priv *priv = ctx; ++ struct mii_bus *bus = priv->bus; ++ int ret; ++ ++ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ ret = an8855_mii_set_page(bus, priv->phy_base, AN8855_PHY_PAGE_EXTENDED_4); ++ if (ret < 0) ++ goto exit; ++ ++ ret = an8855_mii_write32(priv->bus, priv->phy_base, ++ reg, val); ++ ++exit: ++ an8855_mii_set_page(bus, priv->phy_base, AN8855_PHY_PAGE_STANDARD); ++ mutex_unlock(&bus->mdio_lock); ++ ++ return ret < 0 ? ret : 0; ++} ++ ++static int ++an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val) ++{ ++ struct an8855_priv *priv = ctx; ++ struct mii_bus *bus = priv->bus; ++ u32 val; ++ int ret; ++ ++ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ ret = an8855_mii_set_page(bus, priv->phy_base, AN8855_PHY_PAGE_EXTENDED_4); ++ if (ret < 0) ++ goto exit; ++ ++ ret = an8855_mii_read32(bus, priv->phy_base, reg, &val); ++ if (ret < 0) ++ goto exit; ++ ++ val &= ~mask; ++ val |= write_val; ++ ret = an8855_mii_write32(bus, priv->phy_base, reg, val); ++ ++exit: ++ an8855_mii_set_page(bus, priv->phy_base, AN8855_PHY_PAGE_STANDARD); ++ mutex_unlock(&bus->mdio_lock); ++ ++ return ret < 0 ? ret : 0; ++} ++ ++static const struct regmap_range an8855_readable_ranges[] = { ++ regmap_reg_range(0x10000000, 0x10000fff), /* SCU */ ++ regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */ ++ regmap_reg_range(0x10002000, 0x10002fff), /* MCU */ ++ regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */ ++ regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */ ++ regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */ ++ regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */ ++ regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */ ++ regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */ ++ regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */ ++ regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */ ++ regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */ ++ regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */ ++ regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */ ++ regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */ ++ regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */ ++ regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */ ++ regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */ ++ regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */ ++ regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */ ++ regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */ ++ regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */ ++ regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */ ++ regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */ ++ regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */ ++ regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */ ++ regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */ ++}; ++ ++static const struct regmap_access_table an8855_readable_table = { ++ .yes_ranges = an8855_readable_ranges, ++ .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges), ++}; ++ ++static const struct regmap_config an8855_regmap_config = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = 0xbfffffff, ++ .reg_read = an8855_regmap_read, ++ .reg_write = an8855_regmap_write, ++ .reg_update_bits = an8855_regmap_update_bits, ++ .disable_locking = true, ++ .rd_table = &an8855_readable_table, ++}; ++ ++static int ++an8855_mib_init(struct an8855_priv *priv) ++{ ++ int ret; ++ ++ ret = regmap_write(priv->regmap, AN8855_MIB_CCR, ++ AN8855_CCR_MIB_ENABLE); ++ if (ret) ++ return ret; ++ ++ return regmap_write(priv->regmap, AN8855_MIB_CCR, ++ AN8855_CCR_MIB_ACTIVATE); ++} ++ ++static void an8855_fdb_write(struct an8855_priv *priv, u16 vid, ++ u8 port_mask, const u8 *mac, ++ bool add) __must_hold(&priv->reg_mutex) ++{ ++ u32 mac_reg[2] = { }; ++ u32 reg; ++ ++ mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC0, mac[0]); ++ mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC1, mac[1]); ++ mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC2, mac[2]); ++ mac_reg[0] |= FIELD_PREP(AN8855_ATA1_MAC3, mac[3]); ++ mac_reg[1] |= FIELD_PREP(AN8855_ATA2_MAC4, mac[4]); ++ mac_reg[1] |= FIELD_PREP(AN8855_ATA2_MAC5, mac[5]); ++ ++ regmap_bulk_write(priv->regmap, AN8855_ATA1, mac_reg, ++ ARRAY_SIZE(mac_reg)); ++ ++ reg = AN8855_ATWD_IVL; ++ if (add) ++ reg |= AN8855_ATWD_VLD; ++ reg |= FIELD_PREP(AN8855_ATWD_VID, vid); ++ reg |= FIELD_PREP(AN8855_ATWD_FID, AN8855_FID_BRIDGED); ++ regmap_write(priv->regmap, AN8855_ATWD, reg); ++ regmap_write(priv->regmap, AN8855_ATWD2, ++ FIELD_PREP(AN8855_ATWD2_PORT, port_mask)); ++} ++ ++static void an8855_fdb_read(struct an8855_priv *priv, struct an8855_fdb *fdb) ++{ ++ u32 reg[4]; ++ ++ regmap_bulk_read(priv->regmap, AN8855_ATRD0, reg, ++ ARRAY_SIZE(reg)); ++ ++ fdb->live = FIELD_GET(AN8855_ATRD0_LIVE, reg[0]); ++ fdb->type = FIELD_GET(AN8855_ATRD0_TYPE, reg[0]); ++ fdb->ivl = FIELD_GET(AN8855_ATRD0_IVL, reg[0]); ++ fdb->vid = FIELD_GET(AN8855_ATRD0_VID, reg[0]); ++ fdb->fid = FIELD_GET(AN8855_ATRD0_FID, reg[0]); ++ fdb->aging = FIELD_GET(AN8855_ATRD1_AGING, reg[1]); ++ fdb->port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, reg[3]); ++ fdb->mac[0] = FIELD_GET(AN8855_ATRD2_MAC0, reg[2]); ++ fdb->mac[1] = FIELD_GET(AN8855_ATRD2_MAC1, reg[2]); ++ fdb->mac[2] = FIELD_GET(AN8855_ATRD2_MAC2, reg[2]); ++ fdb->mac[3] = FIELD_GET(AN8855_ATRD2_MAC3, reg[2]); ++ fdb->mac[4] = FIELD_GET(AN8855_ATRD1_MAC4, reg[1]); ++ fdb->mac[5] = FIELD_GET(AN8855_ATRD1_MAC5, reg[1]); ++ fdb->noarp = !!FIELD_GET(AN8855_ATRD0_ARP, reg[0]); ++} ++ ++static int an8855_fdb_cmd(struct an8855_priv *priv, u32 cmd, ++ u32 *rsp) __must_hold(&priv->reg_mutex) ++{ ++ u32 val; ++ int ret; ++ ++ /* Set the command operating upon the MAC address entries */ ++ val = AN8855_ATC_BUSY | cmd; ++ ret = regmap_write(priv->regmap, AN8855_ATC, val); ++ if (ret) ++ return ret; ++ ++ ret = regmap_read_poll_timeout(priv->regmap, AN8855_ATC, val, ++ !(val & AN8855_ATC_BUSY), 20, 200000); ++ if (ret) ++ return ret; ++ ++ if (rsp) ++ *rsp = val; ++ ++ return 0; ++} ++ ++static void ++an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) ++{ ++ struct dsa_port *dp = dsa_to_port(ds, port); ++ struct an8855_priv *priv = ds->priv; ++ bool learning = false; ++ u32 stp_state; ++ ++ switch (state) { ++ case BR_STATE_DISABLED: ++ stp_state = AN8855_STP_DISABLED; ++ break; ++ case BR_STATE_BLOCKING: ++ stp_state = AN8855_STP_BLOCKING; ++ break; ++ case BR_STATE_LISTENING: ++ stp_state = AN8855_STP_LISTENING; ++ break; ++ case BR_STATE_LEARNING: ++ stp_state = AN8855_STP_LEARNING; ++ learning = dp->learning; ++ break; ++ case BR_STATE_FORWARDING: ++ learning = dp->learning; ++ fallthrough; ++ default: ++ stp_state = AN8855_STP_FORWARDING; ++ break; ++ } ++ ++ regmap_update_bits(priv->regmap, AN8855_SSP_P(port), ++ AN8855_FID_PST_MASK(AN8855_FID_BRIDGED), ++ AN8855_FID_PST_VAL(AN8855_FID_BRIDGED, stp_state)); ++ ++ regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS, ++ learning ? 0 : AN8855_SA_DIS); ++} ++ ++static void an8855_port_fast_age(struct dsa_switch *ds, int port) ++{ ++ struct an8855_priv *priv = ds->priv; ++ int ret; ++ ++ /* Set to clean Dynamic entry */ ++ ret = regmap_write(priv->regmap, AN8855_ATA2, AN8855_ATA2_TYPE); ++ if (ret) ++ return; ++ ++ /* Set Port */ ++ ret = regmap_write(priv->regmap, AN8855_ATWD2, ++ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port))); ++ if (ret) ++ return; ++ ++ /* Flush Dynamic entry at port */ ++ an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_TYPE_PORT) | ++ AN8855_FDB_FLUSH, NULL); ++} ++ ++static int an8855_update_port_member(struct dsa_switch *ds, int port, ++ const struct net_device *bridge_dev, ++ bool join) ++{ ++ struct an8855_priv *priv = ds->priv; ++ bool isolated, other_isolated; ++ struct dsa_port *dp; ++ u32 port_mask = 0; ++ int ret; ++ ++ isolated = !!(priv->port_isolated_map & BIT(port)); ++ ++ dsa_switch_for_each_user_port(dp, ds) { ++ if (dp->index == port) ++ continue; ++ ++ if (!dsa_port_offloads_bridge_dev(dp, bridge_dev)) ++ continue; ++ ++ other_isolated = !!(priv->port_isolated_map & BIT(dp->index)); ++ port_mask |= BIT(dp->index); ++ /* Add/remove this port to the portvlan mask of the other ++ * ports in the bridge ++ */ ++ if (join && !(isolated && other_isolated)) ++ ret = regmap_set_bits(priv->regmap, ++ AN8855_PORTMATRIX_P(dp->index), ++ FIELD_PREP(AN8855_USER_PORTMATRIX, ++ BIT(port))); ++ else ++ ret = regmap_clear_bits(priv->regmap, ++ AN8855_PORTMATRIX_P(dp->index), ++ FIELD_PREP(AN8855_USER_PORTMATRIX, ++ BIT(port))); ++ if (ret) ++ return ret; ++ } ++ ++ /* Add/remove all other ports to this port's portvlan mask */ ++ return regmap_update_bits(priv->regmap, AN8855_PORTMATRIX_P(port), ++ AN8855_USER_PORTMATRIX, ++ join ? port_mask : ~port_mask); ++} ++ ++static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port, ++ struct switchdev_brport_flags flags, ++ struct netlink_ext_ack *extack) ++{ ++ if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | ++ BR_BCAST_FLOOD | BR_ISOLATED)) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int an8855_port_bridge_flags(struct dsa_switch *ds, int port, ++ struct switchdev_brport_flags flags, ++ struct netlink_ext_ack *extack) ++{ ++ struct an8855_priv *priv = ds->priv; ++ int ret; ++ ++ if (flags.mask & BR_LEARNING) { ++ ret = regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS, ++ flags.val & BR_LEARNING ? 0 : AN8855_SA_DIS); ++ if (ret) ++ return ret; ++ } ++ ++ if (flags.mask & BR_FLOOD) { ++ ret = regmap_update_bits(priv->regmap, AN8855_UNUF, BIT(port), ++ flags.val & BR_FLOOD ? BIT(port) : 0); ++ if (ret) ++ return ret; ++ } ++ ++ if (flags.mask & BR_MCAST_FLOOD) { ++ ret = regmap_update_bits(priv->regmap, AN8855_UNMF, BIT(port), ++ flags.val & BR_MCAST_FLOOD ? BIT(port) : 0); ++ if (ret) ++ return ret; ++ } ++ ++ if (flags.mask & BR_BCAST_FLOOD) { ++ ret = regmap_update_bits(priv->regmap, AN8855_BCF, BIT(port), ++ flags.val & BR_BCAST_FLOOD ? BIT(port) : 0); ++ if (ret) ++ return ret; ++ } ++ ++ if (flags.mask & BR_ISOLATED) { ++ struct dsa_port *dp = dsa_to_port(ds, port); ++ struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); ++ ++ if (flags.val & BR_ISOLATED) ++ priv->port_isolated_map |= BIT(port); ++ else ++ priv->port_isolated_map &= ~BIT(port); ++ ++ ret = an8855_update_port_member(ds, port, bridge_dev, true); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) ++{ ++ struct an8855_priv *priv = ds->priv; ++ u32 age_count, age_unit, val; ++ ++ /* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */ ++ val = msecs / AN8855_L2_AGING_MS_CONSTANT; ++ /* Derive the count unit */ ++ age_unit = val / FIELD_MAX(AN8855_AGE_UNIT); ++ /* Get the count in unit, age_unit is always incremented by 1 internally */ ++ age_count = val / (age_unit + 1); ++ ++ return regmap_update_bits(priv->regmap, AN8855_AAC, ++ AN8855_AGE_CNT | AN8855_AGE_UNIT, ++ FIELD_PREP(AN8855_AGE_CNT, age_count) | ++ FIELD_PREP(AN8855_AGE_UNIT, age_unit)); ++} ++ ++static int an8855_port_bridge_join(struct dsa_switch *ds, int port, ++ struct dsa_bridge bridge, ++ bool *tx_fwd_offload, ++ struct netlink_ext_ack *extack) ++{ ++ struct an8855_priv *priv = ds->priv; ++ int ret; ++ ++ ret = an8855_update_port_member(ds, port, bridge.dev, true); ++ if (ret) ++ return ret; ++ ++ /* Set to fallback mode for independent VLAN learning if in a bridge */ ++ return regmap_update_bits(priv->regmap, AN8855_PCR_P(port), ++ AN8855_PORT_VLAN, ++ FIELD_PREP(AN8855_PORT_VLAN, ++ AN8855_PORT_FALLBACK_MODE)); ++} ++ ++static void an8855_port_bridge_leave(struct dsa_switch *ds, int port, ++ struct dsa_bridge bridge) ++{ ++ struct an8855_priv *priv = ds->priv; ++ ++ an8855_update_port_member(ds, port, bridge.dev, false); ++ ++ /* When a port is removed from the bridge, the port would be set up ++ * back to the default as is at initial boot which is a VLAN-unaware ++ * port. ++ */ ++ regmap_update_bits(priv->regmap, AN8855_PCR_P(port), ++ AN8855_PORT_VLAN, ++ FIELD_PREP(AN8855_PORT_VLAN, ++ AN8855_PORT_MATRIX_MODE)); ++} ++ ++static int an8855_port_fdb_add(struct dsa_switch *ds, int port, ++ const unsigned char *addr, u16 vid, ++ struct dsa_db db) ++{ ++ struct an8855_priv *priv = ds->priv; ++ u8 port_mask = BIT(port); ++ int ret; ++ ++ /* Set the vid to the port vlan id if no vid is set */ ++ if (!vid) ++ vid = AN8855_PORT_VID_DEFAULT; ++ ++ mutex_lock(&priv->reg_mutex); ++ an8855_fdb_write(priv, vid, port_mask, addr, true); ++ ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); ++ mutex_unlock(&priv->reg_mutex); ++ ++ return ret; ++} ++ ++static int an8855_port_fdb_del(struct dsa_switch *ds, int port, ++ const unsigned char *addr, u16 vid, ++ struct dsa_db db) ++{ ++ struct an8855_priv *priv = ds->priv; ++ u8 port_mask = BIT(port); ++ int ret; ++ ++ /* Set the vid to the port vlan id if no vid is set */ ++ if (!vid) ++ vid = AN8855_PORT_VID_DEFAULT; ++ ++ mutex_lock(&priv->reg_mutex); ++ an8855_fdb_write(priv, vid, port_mask, addr, false); ++ ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); ++ mutex_unlock(&priv->reg_mutex); ++ ++ return ret; ++} ++ ++static int an8855_port_fdb_dump(struct dsa_switch *ds, int port, ++ dsa_fdb_dump_cb_t *cb, void *data) ++{ ++ struct an8855_priv *priv = ds->priv; ++ int banks, count = 0; ++ u32 rsp; ++ int ret; ++ int i; ++ ++ mutex_lock(&priv->reg_mutex); ++ ++ /* Load search port */ ++ ret = regmap_write(priv->regmap, AN8855_ATWD2, ++ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port))); ++ if (ret) ++ goto exit; ++ ret = an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_PORT) | ++ AN8855_FDB_START, &rsp); ++ if (ret < 0) ++ goto exit; ++ ++ do { ++ /* From response get the number of banks to read, exit if 0 */ ++ banks = FIELD_GET(AN8855_ATC_HIT, rsp); ++ if (!banks) ++ break; ++ ++ /* Each banks have 4 entry */ ++ for (i = 0; i < 4; i++) { ++ struct an8855_fdb _fdb = { }; ++ ++ count++; ++ ++ /* Check if bank is present */ ++ if (!(banks & BIT(i))) ++ continue; ++ ++ /* Select bank entry index */ ++ ret = regmap_write(priv->regmap, AN8855_ATRDS, ++ FIELD_PREP(AN8855_ATRD_SEL, i)); ++ if (ret) ++ break; ++ /* wait 1ms for the bank entry to be filled */ ++ usleep_range(1000, 1500); ++ an8855_fdb_read(priv, &_fdb); ++ ++ if (!_fdb.live) ++ continue; ++ ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, data); ++ if (ret < 0) ++ break; ++ } ++ ++ /* Stop if reached max FDB number */ ++ if (count >= AN8855_NUM_FDB_RECORDS) ++ break; ++ ++ /* Read next bank */ ++ ret = an8855_fdb_cmd(priv, AN8855_ATC_MAT(AND8855_FDB_MAT_MAC_PORT) | ++ AN8855_FDB_NEXT, &rsp); ++ if (ret < 0) ++ break; ++ } while (true); ++ ++exit: ++ mutex_unlock(&priv->reg_mutex); ++ return ret; ++} ++ ++static int an8855_vlan_cmd(struct an8855_priv *priv, enum an8855_vlan_cmd cmd, ++ u16 vid) __must_hold(&priv->reg_mutex) ++{ ++ u32 val; ++ int ret; ++ ++ val = AN8855_VTCR_BUSY | FIELD_PREP(AN8855_VTCR_FUNC, cmd) | ++ FIELD_PREP(AN8855_VTCR_VID, vid); ++ ret = regmap_write(priv->regmap, AN8855_VTCR, val); ++ if (ret) ++ return ret; ++ ++ return regmap_read_poll_timeout(priv->regmap, AN8855_VTCR, val, ++ !(val & AN8855_VTCR_BUSY), 20, 200000); ++} ++ ++static int an8855_vlan_add(struct an8855_priv *priv, u8 port, u16 vid, ++ bool untagged) __must_hold(&priv->reg_mutex) ++{ ++ u32 port_mask; ++ u32 val; ++ int ret; ++ ++ /* Fetch entry */ ++ ret = an8855_vlan_cmd(priv, AN8855_VTCR_RD_VID, vid); ++ if (ret) ++ return ret; ++ ++ ret = regmap_read(priv->regmap, AN8855_VARD0, &val); ++ if (ret) ++ return ret; ++ port_mask = FIELD_GET(AN8855_VA0_PORT, val) | BIT(port); ++ ++ /* Validate the entry with independent learning, create egress tag per ++ * VLAN and joining the port as one of the port members. ++ */ ++ val = (val & AN8855_VA0_ETAG) | AN8855_VA0_IVL_MAC | ++ AN8855_VA0_VTAG_EN | AN8855_VA0_VLAN_VALID | ++ FIELD_PREP(AN8855_VA0_PORT, port_mask) | ++ FIELD_PREP(AN8855_VA0_FID, AN8855_FID_BRIDGED); ++ ret = regmap_write(priv->regmap, AN8855_VAWD0, val); ++ if (ret) ++ return ret; ++ ret = regmap_write(priv->regmap, AN8855_VAWD1, 0); ++ if (ret) ++ return ret; ++ ++ /* CPU port is always taken as a tagged port for serving more than one ++ * VLANs across and also being applied with egress type stack mode for ++ * that VLAN tags would be appended after hardware special tag used as ++ * DSA tag. ++ */ ++ if (port == AN8855_CPU_PORT) ++ val = AN8855_VLAN_EGRESS_STACK; ++ /* Decide whether adding tag or not for those outgoing packets from the ++ * port inside the VLAN. ++ */ ++ else ++ val = untagged ? AN8855_VLAN_EGRESS_UNTAG : AN8855_VLAN_EGRESS_TAG; ++ ret = regmap_update_bits(priv->regmap, AN8855_VAWD0, ++ AN8855_VA0_ETAG_PORT_MASK(port), ++ AN8855_VA0_ETAG_PORT_VAL(port, val)); ++ if (ret) ++ return ret; ++ ++ /* Flush result to hardware */ ++ return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, vid); ++} ++ ++static int an8855_vlan_del(struct an8855_priv *priv, u8 port, ++ u16 vid) __must_hold(&priv->reg_mutex) ++{ ++ u32 port_mask; ++ u32 val; ++ int ret; ++ ++ /* Fetch entry */ ++ ret = an8855_vlan_cmd(priv, AN8855_VTCR_RD_VID, vid); ++ if (ret) ++ return ret; ++ ++ ret = regmap_read(priv->regmap, AN8855_VARD0, &val); ++ if (ret) ++ return ret; ++ port_mask = FIELD_GET(AN8855_VA0_PORT, val) & ~BIT(port); ++ ++ if (!(val & AN8855_VA0_VLAN_VALID)) { ++ dev_err(priv->dev, "Cannot be deleted due to invalid entry\n"); ++ return -EINVAL; ++ } ++ ++ if (port_mask) { ++ val = (val & AN8855_VA0_ETAG) | AN8855_VA0_IVL_MAC | ++ AN8855_VA0_VTAG_EN | AN8855_VA0_VLAN_VALID | ++ FIELD_PREP(AN8855_VA0_PORT, port_mask); ++ ret = regmap_write(priv->regmap, AN8855_VAWD0, val); ++ if (ret) ++ return ret; ++ } else { ++ ret = regmap_write(priv->regmap, AN8855_VAWD0, 0); ++ if (ret) ++ return ret; ++ } ++ ret = regmap_write(priv->regmap, AN8855_VAWD1, 0); ++ if (ret) ++ return ret; ++ ++ /* Flush result to hardware */ ++ return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, vid); ++} ++ ++static int an8855_port_set_vlan_mode(struct an8855_priv *priv, int port, ++ enum an8855_port_mode port_mode, ++ enum an8855_vlan_port_eg_tag eg_tag, ++ enum an8855_vlan_port_attr vlan_attr, ++ enum an8855_vlan_port_acc_frm acc_frm) ++{ ++ int ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(port), ++ AN8855_PORT_VLAN, ++ FIELD_PREP(AN8855_PORT_VLAN, port_mode)); ++ if (ret) ++ return ret; ++ ++ return regmap_update_bits(priv->regmap, AN8855_PVC_P(port), ++ AN8855_PVC_EG_TAG | AN8855_VLAN_ATTR | AN8855_ACC_FRM, ++ FIELD_PREP(AN8855_PVC_EG_TAG, eg_tag) | ++ FIELD_PREP(AN8855_VLAN_ATTR, vlan_attr) | ++ FIELD_PREP(AN8855_ACC_FRM, acc_frm)); ++} ++ ++static int an8855_port_set_pid(struct an8855_priv *priv, int port, ++ u16 pid) ++{ ++ int ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_PPBV1_P(port), ++ AN8855_PPBV_G0_PORT_VID, ++ FIELD_PREP(AN8855_PPBV_G0_PORT_VID, pid)); ++ if (ret) ++ return ret; ++ ++ return regmap_update_bits(priv->regmap, AN8855_PVID_P(port), ++ AN8855_G0_PORT_VID, ++ FIELD_PREP(AN8855_G0_PORT_VID, pid)); ++} ++ ++static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port, ++ bool vlan_filtering, ++ struct netlink_ext_ack *extack) ++{ ++ struct an8855_priv *priv = ds->priv; ++ u32 val; ++ int ret; ++ ++ /* The port is being kept as VLAN-unaware port when bridge is ++ * set up with vlan_filtering not being set, Otherwise, the ++ * port and the corresponding CPU port is required the setup ++ * for becoming a VLAN-aware port. ++ */ ++ if (vlan_filtering) { ++ u32 acc_frm; ++ /* CPU port is set to fallback mode to let untagged ++ * frames pass through. ++ */ ++ ret = an8855_port_set_vlan_mode(priv, AN8855_CPU_PORT, ++ AN8855_PORT_FALLBACK_MODE, ++ AN8855_VLAN_EG_CONSISTENT, ++ AN8855_VLAN_USER, ++ AN8855_VLAN_ACC_ALL); ++ if (ret) ++ return ret; ++ ++ ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val); ++ if (ret) ++ return ret; ++ ++ /* Only accept tagged frames if PVID is not set */ ++ if (FIELD_GET(AN8855_G0_PORT_VID, val) != AN8855_PORT_VID_DEFAULT) ++ acc_frm = AN8855_VLAN_ACC_TAGGED; ++ else ++ acc_frm = AN8855_VLAN_ACC_ALL; ++ ++ /* Trapped into security mode allows packet forwarding through VLAN ++ * table lookup. ++ * Set the port as a user port which is to be able to recognize VID ++ * from incoming packets before fetching entry within the VLAN table. ++ */ ++ ret = an8855_port_set_vlan_mode(priv, port, ++ AN8855_PORT_SECURITY_MODE, ++ AN8855_VLAN_EG_DISABLED, ++ AN8855_VLAN_USER, ++ acc_frm); ++ if (ret) ++ return ret; ++ } else { ++ bool disable_cpu_vlan = true; ++ struct dsa_port *dp; ++ u32 port_mode; ++ ++ /* This is called after .port_bridge_leave when leaving a VLAN-aware ++ * bridge. Don't set standalone ports to fallback mode. ++ */ ++ if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) ++ port_mode = AN8855_PORT_FALLBACK_MODE; ++ else ++ port_mode = AN8855_PORT_MATRIX_MODE; ++ ++ /* When a port is removed from the bridge, the port would be set up ++ * back to the default as is at initial boot which is a VLAN-unaware ++ * port. ++ */ ++ ret = an8855_port_set_vlan_mode(priv, port, port_mode, ++ AN8855_VLAN_EG_CONSISTENT, ++ AN8855_VLAN_TRANSPARENT, ++ AN8855_VLAN_ACC_ALL); ++ if (ret) ++ return ret; ++ ++ /* Restore default PVID */ ++ ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT); ++ if (ret) ++ return ret; ++ ++ dsa_switch_for_each_user_port(dp, ds) { ++ if (dsa_port_is_vlan_filtering(dp)) { ++ disable_cpu_vlan = false; ++ break; ++ } ++ } ++ ++ if (disable_cpu_vlan) { ++ ret = an8855_port_set_vlan_mode(priv, AN8855_CPU_PORT, ++ AN8855_PORT_MATRIX_MODE, ++ AN8855_VLAN_EG_CONSISTENT, ++ AN8855_VLAN_USER, ++ AN8855_VLAN_ACC_ALL); ++ if (ret) ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int an8855_port_vlan_add(struct dsa_switch *ds, int port, ++ const struct switchdev_obj_port_vlan *vlan, ++ struct netlink_ext_ack *extack) ++{ ++ bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; ++ bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; ++ struct an8855_priv *priv = ds->priv; ++ u32 val; ++ int ret; ++ ++ mutex_lock(&priv->reg_mutex); ++ ret = an8855_vlan_add(priv, port, vlan->vid, untagged); ++ mutex_unlock(&priv->reg_mutex); ++ if (ret) ++ return ret; ++ ++ if (pvid) { ++ /* Accept all frames if PVID is set */ ++ regmap_update_bits(priv->regmap, AN8855_PVC_P(port), AN8855_ACC_FRM, ++ FIELD_PREP(AN8855_ACC_FRM, AN8855_VLAN_ACC_ALL)); ++ ++ /* Only configure PVID if VLAN filtering is enabled */ ++ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { ++ ret = an8855_port_set_pid(priv, port, vlan->vid); ++ if (ret) ++ return ret; ++ } ++ } else if (vlan->vid) { ++ ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val); ++ if (ret) ++ return ret; ++ ++ if (FIELD_GET(AN8855_G0_PORT_VID, val) != vlan->vid) ++ return 0; ++ ++ /* This VLAN is overwritten without PVID, so unset it */ ++ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { ++ ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(port), ++ AN8855_ACC_FRM, ++ FIELD_PREP(AN8855_ACC_FRM, ++ AN8855_VLAN_ACC_TAGGED)); ++ if (ret) ++ return ret; ++ } ++ ++ ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int an8855_port_vlan_del(struct dsa_switch *ds, int port, ++ const struct switchdev_obj_port_vlan *vlan) ++{ ++ struct an8855_priv *priv = ds->priv; ++ u32 val; ++ int ret; ++ ++ mutex_lock(&priv->reg_mutex); ++ ret = an8855_vlan_del(priv, port, vlan->vid); ++ mutex_unlock(&priv->reg_mutex); ++ if (ret) ++ return ret; ++ ++ ret = regmap_read(priv->regmap, AN8855_PVID_P(port), &val); ++ if (ret) ++ return ret; ++ ++ /* PVID is being restored to the default whenever the PVID port ++ * is being removed from the VLAN. ++ */ ++ if (FIELD_GET(AN8855_G0_PORT_VID, val) == vlan->vid) { ++ /* Only accept tagged frames if the port is VLAN-aware */ ++ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { ++ ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(port), ++ AN8855_ACC_FRM, ++ FIELD_PREP(AN8855_ACC_FRM, ++ AN8855_VLAN_ACC_TAGGED)); ++ if (ret) ++ return ret; ++ } ++ ++ ret = an8855_port_set_pid(priv, port, AN8855_PORT_VID_DEFAULT); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int ++an8855_port_mdb_add(struct dsa_switch *ds, int port, ++ const struct switchdev_obj_port_mdb *mdb, ++ struct dsa_db db) ++{ ++ struct an8855_priv *priv = ds->priv; ++ const u8 *addr = mdb->addr; ++ u16 vid = mdb->vid; ++ u8 port_mask = 0; ++ u32 val; ++ int ret; ++ ++ /* Set the vid to the port vlan id if no vid is set */ ++ if (!vid) ++ vid = AN8855_PORT_VID_DEFAULT; ++ ++ mutex_lock(&priv->reg_mutex); ++ ++ an8855_fdb_write(priv, vid, 0, addr, false); ++ if (!an8855_fdb_cmd(priv, AN8855_FDB_READ, NULL)) { ++ ret = regmap_read(priv->regmap, AN8855_ATRD3, &val); ++ if (ret) ++ goto exit; ++ ++ port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, val); ++ } ++ ++ port_mask |= BIT(port); ++ an8855_fdb_write(priv, vid, port_mask, addr, true); ++ ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); ++ ++exit: ++ mutex_unlock(&priv->reg_mutex); ++ ++ return ret; ++} ++ ++static int ++an8855_port_mdb_del(struct dsa_switch *ds, int port, ++ const struct switchdev_obj_port_mdb *mdb, ++ struct dsa_db db) ++{ ++ struct an8855_priv *priv = ds->priv; ++ const u8 *addr = mdb->addr; ++ u16 vid = mdb->vid; ++ u8 port_mask = 0; ++ u32 val; ++ int ret; ++ ++ /* Set the vid to the port vlan id if no vid is set */ ++ if (!vid) ++ vid = AN8855_PORT_VID_DEFAULT; ++ ++ mutex_lock(&priv->reg_mutex); ++ ++ an8855_fdb_write(priv, vid, 0, addr, 0); ++ if (!an8855_fdb_cmd(priv, AN8855_FDB_READ, NULL)) { ++ ret = regmap_read(priv->regmap, AN8855_ATRD3, &val); ++ if (ret) ++ goto exit; ++ ++ port_mask = FIELD_GET(AN8855_ATRD3_PORTMASK, val); ++ } ++ ++ port_mask &= ~BIT(port); ++ an8855_fdb_write(priv, vid, port_mask, addr, port_mask ? true : false); ++ ret = an8855_fdb_cmd(priv, AN8855_FDB_WRITE, NULL); ++ ++exit: ++ mutex_unlock(&priv->reg_mutex); ++ ++ return ret; ++} ++ ++static int ++an8855_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) ++{ ++ struct an8855_priv *priv = ds->priv; ++ int length; ++ u32 val; ++ ++ /* When a new MTU is set, DSA always set the CPU port's MTU to the ++ * largest MTU of the slave ports. Because the switch only has a global ++ * RX length register, only allowing CPU port here is enough. ++ */ ++ if (!dsa_is_cpu_port(ds, port)) ++ return 0; ++ ++ /* RX length also includes Ethernet header, MTK tag, and FCS length */ ++ length = new_mtu + ETH_HLEN + MTK_TAG_LEN + ETH_FCS_LEN; ++ if (length <= 1522) ++ val = AN8855_MAX_RX_PKT_1518_1522; ++ else if (length <= 1536) ++ val = AN8855_MAX_RX_PKT_1536; ++ else if (length <= 1552) ++ val = AN8855_MAX_RX_PKT_1552; ++ else if (length <= 3072) ++ val = AN8855_MAX_RX_JUMBO_3K; ++ else if (length <= 4096) ++ val = AN8855_MAX_RX_JUMBO_4K; ++ else if (length <= 5120) ++ val = AN8855_MAX_RX_JUMBO_5K; ++ else if (length <= 6144) ++ val = AN8855_MAX_RX_JUMBO_6K; ++ else if (length <= 7168) ++ val = AN8855_MAX_RX_JUMBO_7K; ++ else if (length <= 8192) ++ val = AN8855_MAX_RX_JUMBO_8K; ++ else if (length <= 9216) ++ val = AN8855_MAX_RX_JUMBO_9K; ++ else if (length <= 12288) ++ val = AN8855_MAX_RX_JUMBO_12K; ++ else if (length <= 15360) ++ val = AN8855_MAX_RX_JUMBO_15K; ++ else ++ val = AN8855_MAX_RX_JUMBO_16K; ++ ++ /* Enable JUMBO packet */ ++ if (length > 1552) ++ val |= AN8855_MAX_RX_PKT_JUMBO; ++ ++ return regmap_update_bits(priv->regmap, AN8855_GMACCR, ++ AN8855_MAX_RX_JUMBO | AN8855_MAX_RX_PKT_LEN, ++ val); ++} ++ ++static int ++an8855_port_max_mtu(struct dsa_switch *ds, int port) ++{ ++ return AN8855_MAX_MTU; ++} ++ ++static void ++an8855_get_strings(struct dsa_switch *ds, int port, u32 stringset, ++ uint8_t *data) ++{ ++ int i; ++ ++ if (stringset != ETH_SS_STATS) ++ return; ++ ++ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) ++ ethtool_puts(&data, an8855_mib[i].name); ++} ++ ++static void ++an8855_read_port_stats(struct an8855_priv *priv, int port, u32 offset, u8 size, ++ uint64_t *data) ++{ ++ u32 val, reg = AN8855_PORT_MIB_COUNTER(port) + offset; ++ ++ regmap_read(priv->regmap, reg, &val); ++ *data = val; ++ ++ if (size == 2) { ++ regmap_read(priv->regmap, reg + 4, &val); ++ *data |= (u64)val << 32; ++ } ++} ++ ++static void ++an8855_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) ++{ ++ struct an8855_priv *priv = ds->priv; ++ const struct an8855_mib_desc *mib; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) { ++ mib = &an8855_mib[i]; ++ ++ an8855_read_port_stats(priv, port, mib->offset, mib->size, ++ data + i); ++ } ++} ++ ++static int ++an8855_get_sset_count(struct dsa_switch *ds, int port, int sset) ++{ ++ if (sset != ETH_SS_STATS) ++ return 0; ++ ++ return ARRAY_SIZE(an8855_mib); ++} ++ ++static void ++an8855_get_eth_mac_stats(struct dsa_switch *ds, int port, ++ struct ethtool_eth_mac_stats *mac_stats) ++{ ++ struct an8855_priv *priv = ds->priv; ++ ++ /* MIB counter doesn't provide a FramesTransmittedOK but instead ++ * provide stats for Unicast, Broadcast and Multicast frames separately. ++ * To simulate a global frame counter, read Unicast and addition Multicast ++ * and Broadcast later ++ */ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_UNICAST, 1, ++ &mac_stats->FramesTransmittedOK); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_SINGLE_COLLISION, 1, ++ &mac_stats->SingleCollisionFrames); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_MULTIPLE_COLLISION, 1, ++ &mac_stats->MultipleCollisionFrames); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_UNICAST, 1, ++ &mac_stats->FramesReceivedOK); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_BYTES, 2, ++ &mac_stats->OctetsTransmittedOK); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_ALIGN_ERR, 1, ++ &mac_stats->AlignmentErrors); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_DEFERRED, 1, ++ &mac_stats->FramesWithDeferredXmissions); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_LATE_COLLISION, 1, ++ &mac_stats->LateCollisions); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, ++ &mac_stats->FramesAbortedDueToXSColls); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_BYTES, 2, ++ &mac_stats->OctetsReceivedOK); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_MULTICAST, 1, ++ &mac_stats->MulticastFramesXmittedOK); ++ mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_BROADCAST, 1, ++ &mac_stats->BroadcastFramesXmittedOK); ++ mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_MULTICAST, 1, ++ &mac_stats->MulticastFramesReceivedOK); ++ mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_BROADCAST, 1, ++ &mac_stats->BroadcastFramesReceivedOK); ++ mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; ++} ++ ++static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = { ++ { 0, 64 }, ++ { 65, 127 }, ++ { 128, 255 }, ++ { 256, 511 }, ++ { 512, 1023 }, ++ { 1024, 1518 }, ++ { 1519, AN8855_MAX_MTU }, ++ {} ++}; ++ ++static void an8855_get_rmon_stats(struct dsa_switch *ds, int port, ++ struct ethtool_rmon_stats *rmon_stats, ++ const struct ethtool_rmon_hist_range **ranges) ++{ ++ struct an8855_priv *priv = ds->priv; ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_UNDER_SIZE_ERR, 1, ++ &rmon_stats->undersize_pkts); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_OVER_SZ_ERR, 1, ++ &rmon_stats->oversize_pkts); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_FRAG_ERR, 1, ++ &rmon_stats->fragments); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_JABBER_ERR, 1, ++ &rmon_stats->jabbers); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_64, 1, ++ &rmon_stats->hist[0]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, ++ &rmon_stats->hist[1]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, ++ &rmon_stats->hist[2]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, ++ &rmon_stats->hist[3]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, ++ &rmon_stats->hist[4]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518, 1, ++ &rmon_stats->hist[5]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX, 1, ++ &rmon_stats->hist[6]); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_64, 1, ++ &rmon_stats->hist_tx[0]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, ++ &rmon_stats->hist_tx[1]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, ++ &rmon_stats->hist_tx[2]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, ++ &rmon_stats->hist_tx[3]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, ++ &rmon_stats->hist_tx[4]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518, 1, ++ &rmon_stats->hist_tx[5]); ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX, 1, ++ &rmon_stats->hist_tx[6]); ++ ++ *ranges = an8855_rmon_ranges; ++} ++ ++static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port, ++ struct ethtool_eth_ctrl_stats *ctrl_stats) ++{ ++ struct an8855_priv *priv = ds->priv; ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_TX_PAUSE, 1, ++ &ctrl_stats->MACControlFramesTransmitted); ++ ++ an8855_read_port_stats(priv, port, AN8855_PORT_MIB_RX_PAUSE, 1, ++ &ctrl_stats->MACControlFramesReceived); ++} ++ ++static int an8855_port_mirror_add(struct dsa_switch *ds, int port, ++ struct dsa_mall_mirror_tc_entry *mirror, ++ bool ingress, ++ struct netlink_ext_ack *extack) ++{ ++ struct an8855_priv *priv = ds->priv; ++ int monitor_port; ++ u32 val; ++ int ret; ++ ++ /* Check for existent entry */ ++ if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) ++ return -EEXIST; ++ ++ ret = regmap_read(priv->regmap, AN8855_MIR, &val); ++ if (ret) ++ return ret; ++ ++ /* AN8855 supports 4 monitor port, but only use first group */ ++ monitor_port = FIELD_GET(AN8855_MIRROR_PORT, val); ++ if (val & AN8855_MIRROR_EN && monitor_port != mirror->to_local_port) ++ return -EEXIST; ++ ++ val = AN8855_MIRROR_EN; ++ val |= FIELD_PREP(AN8855_MIRROR_PORT, mirror->to_local_port); ++ ret = regmap_update_bits(priv->regmap, AN8855_MIR, ++ AN8855_MIRROR_EN | AN8855_MIRROR_PORT, ++ val); ++ if (ret) ++ return ret; ++ ++ ret = regmap_set_bits(priv->regmap, AN8855_PCR_P(port), ++ ingress ? AN8855_PORT_RX_MIR : AN8855_PORT_TX_MIR); ++ if (ret) ++ return ret; ++ ++ if (ingress) ++ priv->mirror_rx |= BIT(port); ++ else ++ priv->mirror_tx |= BIT(port); ++ ++ return 0; ++} ++ ++static void an8855_port_mirror_del(struct dsa_switch *ds, int port, ++ struct dsa_mall_mirror_tc_entry *mirror) ++{ ++ struct an8855_priv *priv = ds->priv; ++ ++ if (mirror->ingress) ++ priv->mirror_rx &= ~BIT(port); ++ else ++ priv->mirror_tx &= ~BIT(port); ++ ++ regmap_clear_bits(priv->regmap, AN8855_PCR_P(port), ++ mirror->ingress ? AN8855_PORT_RX_MIR : ++ AN8855_PORT_TX_MIR); ++ ++ if (!priv->mirror_rx && !priv->mirror_tx) ++ regmap_clear_bits(priv->regmap, AN8855_MIR, AN8855_MIRROR_EN); ++} ++ ++static int an8855_port_set_status(struct an8855_priv *priv, int port, ++ bool enable) ++{ ++ if (enable) ++ return regmap_set_bits(priv->regmap, AN8855_PMCR_P(port), ++ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); ++ else ++ return regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port), ++ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); ++} ++ ++static int an8855_port_enable(struct dsa_switch *ds, int port, ++ struct phy_device *phy) ++{ ++ return an8855_port_set_status(ds->priv, port, true); ++} ++ ++static void an8855_port_disable(struct dsa_switch *ds, int port) ++{ ++ an8855_port_set_status(ds->priv, port, false); ++} ++ ++static int an8855_set_mac_eee(struct dsa_switch *ds, int port, ++ struct ethtool_eee *eee) ++{ ++ struct an8855_priv *priv = ds->priv; ++ u32 reg; ++ int ret; ++ ++ if (eee->eee_enabled) { ++ ret = regmap_read(priv->regmap, AN8855_PMCR_P(port), ®); ++ if (ret) ++ return ret; ++ /* Force enable EEE if force mode and LINK */ ++ if (reg & AN8855_PMCR_FORCE_MODE && ++ reg & AN8855_PMCR_FORCE_LNK) { ++ switch (reg & AN8855_PMCR_FORCE_SPEED) { ++ case AN8855_PMCR_FORCE_SPEED_1000: ++ reg |= AN8855_PMCR_FORCE_EEE1G; ++ break; ++ case AN8855_PMCR_FORCE_SPEED_100: ++ reg |= AN8855_PMCR_FORCE_EEE100; ++ break; ++ default: ++ break; ++ } ++ ret = regmap_write(priv->regmap, AN8855_PMCR_P(port), reg); ++ if (ret) ++ return ret; ++ } ++ ret = regmap_update_bits(priv->regmap, AN8855_PMEEECR_P(port), ++ AN8855_LPI_MODE_EN, ++ eee->tx_lpi_enabled ? AN8855_LPI_MODE_EN : 0); ++ if (ret) ++ return ret; ++ } else { ++ ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port), ++ AN8855_PMCR_FORCE_EEE1G | ++ AN8855_PMCR_FORCE_EEE100); ++ if (ret) ++ return ret; ++ ++ ret = regmap_clear_bits(priv->regmap, AN8855_PMEEECR_P(port), ++ AN8855_LPI_MODE_EN); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int an8855_get_mac_eee(struct dsa_switch *ds, int port, ++ struct ethtool_eee *eee) ++{ ++ struct an8855_priv *priv = ds->priv; ++ u32 reg; ++ int ret; ++ ++ ret = regmap_read(priv->regmap, AN8855_PMEEECR_P(port), ®); ++ if (ret) ++ return ret; ++ eee->tx_lpi_enabled = reg & AN8855_LPI_MODE_EN; ++ ++ ret = regmap_read(priv->regmap, AN8855_CKGCR, ®); ++ if (ret) ++ return ret; ++ /* Global LPI TXIDLE Threshold, default 60ms (unit 2us) */ ++ eee->tx_lpi_timer = FIELD_GET(AN8855_LPI_TXIDLE_THD_MASK, reg) / 500; ++ ++ ret = regmap_read(priv->regmap, AN8855_PMSR_P(port), ®); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static u32 en8855_get_phy_flags(struct dsa_switch *ds, int port) ++{ ++ struct an8855_priv *priv = ds->priv; ++ ++ /* PHY doesn't need calibration */ ++ if (!priv->phy_require_calib) ++ return 0; ++ ++ /* Use AN8855_PHY_FLAGS_EN_CALIBRATION to signal ++ * calibration needed. ++ */ ++ return AN8855_PHY_FLAGS_EN_CALIBRATION; ++} ++ ++static enum dsa_tag_protocol ++an8855_get_tag_protocol(struct dsa_switch *ds, int port, ++ enum dsa_tag_protocol mp) ++{ ++ return DSA_TAG_PROTO_MTK; ++} ++ ++static int an8855_phy_read(struct mii_bus *bus, int phy, int regnum) ++{ ++ struct an8855_priv *priv = bus->priv; ++ ++ return mdiobus_read_nested(priv->bus, phy, regnum); ++} ++ ++static int an8855_phy_write(struct mii_bus *bus, int phy, int regnum, u16 val) ++{ ++ struct an8855_priv *priv = bus->priv; ++ ++ return mdiobus_write_nested(priv->bus, phy, regnum, val); ++} ++ ++static int an8855_mdio_setup(struct an8855_priv *priv) ++{ ++ struct dsa_switch *ds = priv->ds; ++ struct device *dev = priv->dev; ++ struct device_node *np; ++ struct mii_bus *bus; ++ int ret = 0; ++ ++ np = of_get_child_by_name(priv->dev->of_node, "mdio"); ++ if (!np || !of_device_is_available(np)) ++ goto exit; ++ ++ bus = devm_mdiobus_alloc(priv->dev); ++ if (!bus) { ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ bus->priv = priv; ++ bus->name = KBUILD_MODNAME "-mii"; ++ snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d.%d", ++ ds->dst->index, ds->index); ++ bus->parent = dev; ++ bus->read = an8855_phy_read; ++ bus->write = an8855_phy_write; ++ ++ ret = devm_of_mdiobus_register(dev, bus, np); ++ if (ret) ++ dev_err(dev, "failed to register MDIO bus: %d", ret); ++ ++exit: ++ of_node_put(np); ++ return ret; ++} ++ ++static int ++an8855_setup_pvid_vlan(struct an8855_priv *priv) ++{ ++ u32 val; ++ int ret; ++ ++ /* Validate the entry with independent learning, keep the original ++ * ingress tag attribute. ++ */ ++ val = AN8855_VA0_IVL_MAC | AN8855_VA0_EG_CON | ++ FIELD_PREP(AN8855_VA0_FID, AN8855_FID_BRIDGED) | ++ AN8855_VA0_PORT | AN8855_VA0_VLAN_VALID; ++ ret = regmap_write(priv->regmap, AN8855_VAWD0, val); ++ if (ret) ++ return ret; ++ ++ return an8855_vlan_cmd(priv, AN8855_VTCR_WR_VID, ++ AN8855_PORT_VID_DEFAULT); ++} ++ ++static int an8855_setup(struct dsa_switch *ds) ++{ ++ struct an8855_priv *priv = ds->priv; ++ struct dsa_port *dp; ++ int ret; ++ ++ /* Setup mdio BUS for internal PHY */ ++ ret = an8855_mdio_setup(priv); ++ if (ret) ++ return ret; ++ ++ /* Enable and reset MIB counters */ ++ ret = an8855_mib_init(priv); ++ if (ret) ++ return ret; ++ ++ dsa_switch_for_each_user_port(dp, ds) { ++ /* Disable MAC by default on all user ports */ ++ ret = an8855_port_set_status(priv, dp->index, false); ++ if (ret) ++ return ret; ++ ++ /* Individual user ports get connected to CPU port only */ ++ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(dp->index), ++ FIELD_PREP(AN8855_PORTMATRIX, BIT(AN8855_CPU_PORT))); ++ if (ret) ++ return ret; ++ ++ /* Disable Learning on user ports */ ++ ret = regmap_set_bits(priv->regmap, AN8855_PSC_P(dp->index), ++ AN8855_SA_DIS); ++ if (ret) ++ return ret; ++ ++ /* Disable Broadcast Forward on user ports */ ++ ret = regmap_clear_bits(priv->regmap, AN8855_BCF, BIT(dp->index)); ++ if (ret) ++ return ret; ++ ++ /* Disable Unknown Unicast Forward on user ports */ ++ ret = regmap_clear_bits(priv->regmap, AN8855_UNUF, BIT(dp->index)); ++ if (ret) ++ return ret; ++ ++ /* Disable Unknown Multicast Forward on user ports */ ++ ret = regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index)); ++ if (ret) ++ return ret; ++ ++ /* Set default PVID to on all user ports */ ++ ret = an8855_port_set_pid(priv, dp->index, AN8855_PORT_VID_DEFAULT); ++ if (ret) ++ return ret; ++ } ++ ++ /* Enable Airoha header mode on the cpu port */ ++ ret = regmap_write(priv->regmap, AN8855_PVC_P(AN8855_CPU_PORT), ++ AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG); ++ if (ret) ++ return ret; ++ ++ /* Unknown multicast frame forwarding to the cpu port */ ++ ret = regmap_write(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT)); ++ if (ret) ++ return ret; ++ ++ /* Set CPU port number */ ++ ret = regmap_update_bits(priv->regmap, AN8855_MFC, ++ AN8855_CPU_EN | AN8855_CPU_PORT_IDX, ++ AN8855_CPU_EN | ++ FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT)); ++ if (ret) ++ return ret; ++ ++ /* CPU port gets connected to all user ports of ++ * the switch. ++ */ ++ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT), ++ FIELD_PREP(AN8855_PORTMATRIX, dsa_user_ports(ds))); ++ if (ret) ++ return ret; ++ ++ /* CPU port is set to fallback mode to let untagged ++ * frames pass through. ++ */ ++ ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(AN8855_CPU_PORT), ++ AN8855_PORT_VLAN, ++ FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE)); ++ if (ret) ++ return ret; ++ ++ /* Enable Learning on CPU port */ ++ ret = regmap_clear_bits(priv->regmap, AN8855_PSC_P(AN8855_CPU_PORT), AN8855_SA_DIS); ++ if (ret) ++ return ret; ++ ++ /* Enable Broadcast Forward on CPU port */ ++ ret = regmap_set_bits(priv->regmap, AN8855_BCF, BIT(AN8855_CPU_PORT)); ++ if (ret) ++ return ret; ++ ++ /* Enable Unknown Unicast Forward on CPU port */ ++ ret = regmap_set_bits(priv->regmap, AN8855_UNUF, BIT(AN8855_CPU_PORT)); ++ if (ret) ++ return ret; ++ ++ /* Enable Unknown Multicast Forward on CPU port */ ++ ret = regmap_set_bits(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT)); ++ if (ret) ++ return ret; ++ ++ /* BPDU to CPU port */ ++ ret = regmap_update_bits(priv->regmap, AN8855_BPC, AN8855_BPDU_PORT_FW, ++ FIELD_PREP(AN8855_BPDU_PORT_FW, AN8855_BPDU_CPU_ONLY)); ++ if (ret) ++ return ret; ++ ++ dsa_switch_for_each_port(dp, ds) { ++ /* Enable consistent egress tag (for VLAN unware VLAN-passtrough) */ ++ ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(dp->index), ++ AN8855_PVC_EG_TAG, ++ FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT)); ++ if (ret) ++ return ret; ++ } ++ ++ /* Setup VLAN for Default PVID */ ++ ret = an8855_setup_pvid_vlan(priv); ++ if (ret) ++ return ret; ++ ++ ret = regmap_clear_bits(priv->regmap, AN8855_CKGCR, ++ AN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP); ++ if (ret) ++ return ret; ++ ++ /* Release global PHY power down */ ++ ret = regmap_write(priv->regmap, AN8855_RG_GPHY_AFE_PWD, 0x0); ++ if (ret) ++ return ret; ++ ++ ds->configure_vlan_while_not_filtering = true; ++ ++ /* Flush the FDB table */ ++ ret = an8855_fdb_cmd(priv, AN8855_FDB_FLUSH, NULL); ++ if (ret < 0) ++ return ret; ++ ++ /* Set min a max ageing value supported */ ++ ds->ageing_time_min = AN8855_L2_AGING_MS_CONSTANT; ++ ds->ageing_time_max = FIELD_MAX(AN8855_AGE_CNT) * ++ FIELD_MAX(AN8855_AGE_UNIT) * ++ AN8855_L2_AGING_MS_CONSTANT; ++ ++ return 0; ++} ++ ++static struct phylink_pcs * ++an8855_phylink_mac_select_pcs(struct phylink_config *config, ++ phy_interface_t interface) ++{ ++ struct dsa_port *dp = dsa_phylink_to_port(config); ++ struct an8855_priv *priv = dp->ds->priv; ++ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_2500BASEX: ++ return &priv->pcs; ++ default: ++ return NULL; ++ } ++} ++ ++static void ++an8855_phylink_mac_config(struct phylink_config *config, unsigned int mode, ++ const struct phylink_link_state *state) ++{ ++ struct dsa_port *dp = dsa_phylink_to_port(config); ++ struct dsa_switch *ds = dp->ds; ++ struct an8855_priv *priv; ++ int port = dp->index; ++ ++ priv = ds->priv; ++ ++ if (port != 5) { ++ if (port > 5) ++ dev_err(ds->dev, "unsupported port: %d", port); ++ return; ++ } ++ ++ regmap_update_bits(priv->regmap, AN8855_PMCR_P(port), ++ AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE | ++ AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN, ++ FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) | ++ AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN | ++ AN8855_PMCR_BACKPR_EN); ++} ++ ++static void an8855_phylink_get_caps(struct dsa_switch *ds, int port, ++ struct phylink_config *config) ++{ ++ switch (port) { ++ case 0: ++ case 1: ++ case 2: ++ case 3: ++ case 4: ++ __set_bit(PHY_INTERFACE_MODE_GMII, ++ config->supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_INTERNAL, ++ config->supported_interfaces); ++ break; ++ case 5: ++ phy_interface_set_rgmii(config->supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_SGMII, ++ config->supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_2500BASEX, ++ config->supported_interfaces); ++ break; ++ } ++ ++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | ++ MAC_10 | MAC_100 | MAC_1000FD; ++} ++ ++static void ++an8855_phylink_mac_link_down(struct phylink_config *config, unsigned int mode, ++ phy_interface_t interface) ++{ ++ struct dsa_port *dp = dsa_phylink_to_port(config); ++ struct an8855_priv *priv = dp->ds->priv; ++ ++ /* With autoneg just disable TX/RX else also force link down */ ++ if (phylink_autoneg_inband(mode)) { ++ regmap_clear_bits(priv->regmap, AN8855_PMCR_P(dp->index), ++ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN); ++ } else { ++ regmap_update_bits(priv->regmap, AN8855_PMCR_P(dp->index), ++ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN | ++ AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK, ++ AN8855_PMCR_FORCE_MODE); ++ } ++} ++ ++static void ++an8855_phylink_mac_link_up(struct phylink_config *config, ++ struct phy_device *phydev, unsigned int mode, ++ phy_interface_t interface, int speed, int duplex, ++ bool tx_pause, bool rx_pause) ++{ ++ struct dsa_port *dp = dsa_phylink_to_port(config); ++ struct an8855_priv *priv = dp->ds->priv; ++ int port = dp->index; ++ u32 reg; ++ ++ reg = regmap_read(priv->regmap, AN8855_PMCR_P(port), ®); ++ if (phylink_autoneg_inband(mode)) { ++ reg &= ~AN8855_PMCR_FORCE_MODE; ++ } else { ++ reg |= AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK; ++ ++ reg &= ~AN8855_PMCR_FORCE_SPEED; ++ switch (speed) { ++ case SPEED_10: ++ reg |= AN8855_PMCR_FORCE_SPEED_10; ++ break; ++ case SPEED_100: ++ reg |= AN8855_PMCR_FORCE_SPEED_100; ++ break; ++ case SPEED_1000: ++ reg |= AN8855_PMCR_FORCE_SPEED_1000; ++ break; ++ case SPEED_2500: ++ reg |= AN8855_PMCR_FORCE_SPEED_2500; ++ break; ++ case SPEED_5000: ++ reg |= AN8855_PMCR_FORCE_SPEED_5000; ++ break; ++ } ++ ++ reg &= ~AN8855_PMCR_FORCE_FDX; ++ if (duplex == DUPLEX_FULL) ++ reg |= AN8855_PMCR_FORCE_FDX; ++ ++ reg &= ~AN8855_PMCR_RX_FC_EN; ++ if (rx_pause || dsa_port_is_cpu(dp)) ++ reg |= AN8855_PMCR_RX_FC_EN; ++ ++ reg &= ~AN8855_PMCR_TX_FC_EN; ++ if (rx_pause || dsa_port_is_cpu(dp)) ++ reg |= AN8855_PMCR_TX_FC_EN; ++ ++ /* Disable any EEE options */ ++ reg &= ~(AN8855_PMCR_FORCE_EEE5G | AN8855_PMCR_FORCE_EEE2P5G | ++ AN8855_PMCR_FORCE_EEE1G | AN8855_PMCR_FORCE_EEE100); ++ } ++ ++ reg |= AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN; ++ ++ regmap_write(priv->regmap, AN8855_PMCR_P(port), reg); ++} ++ ++static void an8855_pcs_get_state(struct phylink_pcs *pcs, ++ struct phylink_link_state *state) ++{ ++ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs); ++ u32 val; ++ int ret; ++ ++ ret = regmap_read(priv->regmap, AN8855_PMSR_P(AN8855_CPU_PORT), &val); ++ if (ret < 0) { ++ state->link = false; ++ return; ++ } ++ ++ state->link = !!(val & AN8855_PMSR_LNK); ++ state->an_complete = state->link; ++ state->duplex = (val & AN8855_PMSR_DPX) ? DUPLEX_FULL : ++ DUPLEX_HALF; ++ ++ switch (val & AN8855_PMSR_SPEED) { ++ case AN8855_PMSR_SPEED_10: ++ state->speed = SPEED_10; ++ break; ++ case AN8855_PMSR_SPEED_100: ++ state->speed = SPEED_100; ++ break; ++ case AN8855_PMSR_SPEED_1000: ++ state->speed = SPEED_1000; ++ break; ++ case AN8855_PMSR_SPEED_2500: ++ state->speed = SPEED_2500; ++ break; ++ case AN8855_PMSR_SPEED_5000: ++ state->speed = SPEED_5000; ++ break; ++ default: ++ state->speed = SPEED_UNKNOWN; ++ break; ++ } ++ ++ if (val & AN8855_PMSR_RX_FC) ++ state->pause |= MLO_PAUSE_RX; ++ if (val & AN8855_PMSR_TX_FC) ++ state->pause |= MLO_PAUSE_TX; ++} ++ ++static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, ++ phy_interface_t interface, ++ const unsigned long *advertising, ++ bool permit_pause_to_mac) ++{ ++ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs); ++ u32 val; ++ int ret; ++ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ break; ++ case PHY_INTERFACE_MODE_2500BASEX: ++ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { ++ dev_err(priv->dev, "in-band negotiation unsupported"); ++ return -EINVAL; ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* !!! WELCOME TO HELL !!! */ ++ ++ /* TX FIR - improve TX EYE */ ++ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_10, ++ AN8855_RG_DA_QP_TX_FIR_C2_SEL | ++ AN8855_RG_DA_QP_TX_FIR_C2_FORCE | ++ AN8855_RG_DA_QP_TX_FIR_C1_SEL | ++ AN8855_RG_DA_QP_TX_FIR_C1_FORCE, ++ AN8855_RG_DA_QP_TX_FIR_C2_SEL | ++ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) | ++ AN8855_RG_DA_QP_TX_FIR_C1_SEL | ++ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0)); ++ if (ret) ++ return ret; ++ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = 0x0; ++ else ++ val = 0xd; ++ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_11, ++ AN8855_RG_DA_QP_TX_FIR_C0B_SEL | ++ AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, ++ AN8855_RG_DA_QP_TX_FIR_C0B_SEL | ++ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val)); ++ if (ret) ++ return ret; ++ ++ /* RX CDR - improve RX Jitter Tolerance */ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = 0x5; ++ else ++ val = 0x6; ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_BOT_LIM, ++ AN8855_RG_QP_CDR_LPF_KP_GAIN | ++ AN8855_RG_QP_CDR_LPF_KI_GAIN, ++ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) | ++ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val)); ++ if (ret) ++ return ret; ++ ++ /* PLL */ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = 0x1; ++ else ++ val = 0x0; ++ ret = regmap_update_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_1, ++ AN8855_RG_TPHY_SPEED, ++ FIELD_PREP(AN8855_RG_TPHY_SPEED, val)); ++ if (ret) ++ return ret; ++ ++ /* PLL - LPF */ ++ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, ++ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF | ++ AN8855_RG_DA_QP_PLL_FBKSEL_INTF | ++ AN8855_RG_DA_QP_PLL_BR_INTF | ++ AN8855_RG_DA_QP_PLL_BPD_INTF | ++ AN8855_RG_DA_QP_PLL_BPA_INTF | ++ AN8855_RG_DA_QP_PLL_BC_INTF, ++ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF | ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) | ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) | ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) | ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) | ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1)); ++ if (ret) ++ return ret; ++ ++ /* PLL - ICO */ ++ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_4, ++ AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF); ++ if (ret) ++ return ret; ++ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2, ++ AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF); ++ if (ret) ++ return ret; ++ ++ /* PLL - CHP */ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = 0x6; ++ else ++ val = 0x4; ++ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, ++ AN8855_RG_DA_QP_PLL_IR_INTF, ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val)); ++ if (ret) ++ return ret; ++ ++ /* PLL - PFD */ ++ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, ++ AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF | ++ AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF | ++ AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) | ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1)); ++ if (ret) ++ return ret; ++ ++ /* PLL - POSTDIV */ ++ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, ++ AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF | ++ AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF | ++ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF, ++ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF); ++ if (ret) ++ return ret; ++ ++ /* PLL - SDM */ ++ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2, ++ AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0)); ++ if (ret) ++ return ret; ++ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2, ++ AN8855_RG_DA_QP_PLL_SDM_IFM_INTF); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_SS_LCPLL_PWCTL_SETTING_2, ++ AN8855_RG_NCPO_ANA_MSB, ++ FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1)); ++ if (ret) ++ return ret; ++ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = 0x7a000000; ++ else ++ val = 0x48000000; ++ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_2, ++ FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val)); ++ if (ret) ++ return ret; ++ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_PCW_1, ++ FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_clear_bits(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_5, ++ AN8855_RG_LCPLL_NCPO_CHG); ++ if (ret) ++ return ret; ++ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0, ++ AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF); ++ if (ret) ++ return ret; ++ ++ /* PLL - SS */ ++ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3, ++ AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0)); ++ if (ret) ++ return ret; ++ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_4, ++ AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0)); ++ if (ret) ++ return ret; ++ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3, ++ AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, ++ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0)); ++ if (ret) ++ return ret; ++ ++ /* PLL - TDC */ ++ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0, ++ AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF); ++ if (ret) ++ return ret; ++ ++ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD, ++ AN8855_RG_QP_PLL_SSC_TRI_EN); ++ if (ret) ++ return ret; ++ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD, ++ AN8855_RG_QP_PLL_SSC_PHASE_INI); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_RX_DAC_EN, ++ AN8855_RG_QP_SIGDET_HF, ++ FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2)); ++ if (ret) ++ return ret; ++ ++ /* TCL Disable (only for Co-SIM) */ ++ ret = regmap_clear_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_0, ++ AN8855_RG_QP_EQ_RX500M_CK_SEL); ++ if (ret) ++ return ret; ++ ++ /* TX Init */ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = 0x4; ++ else ++ val = 0x0; ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_TX_MODE, ++ AN8855_RG_QP_TX_RESERVE | ++ AN8855_RG_QP_TX_MODE_16B_EN, ++ FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val)); ++ if (ret) ++ return ret; ++ ++ /* RX Control/Init */ ++ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_RXAFE_RESERVE, ++ AN8855_RG_QP_CDR_PD_10B_EN); ++ if (ret) ++ return ret; ++ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = 0x1; ++ else ++ val = 0x2; ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_MJV_LIM, ++ AN8855_RG_QP_CDR_LPF_RATIO, ++ FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_SETVALUE, ++ AN8855_RG_QP_CDR_PR_BUF_IN_SR | ++ AN8855_RG_QP_CDR_PR_BETA_SEL, ++ FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) | ++ FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1)); ++ if (ret) ++ return ret; ++ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = 0xf; ++ else ++ val = 0xc; ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1, ++ AN8855_RG_QP_CDR_PR_DAC_BAND, ++ FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, ++ AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE | ++ AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, ++ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, ++ AN8855_RG_QP_CDR_PHYCK_SEL | ++ AN8855_RG_QP_CDR_PHYCK_RSTB | ++ AN8855_RG_QP_CDR_PHYCK_DIV, ++ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) | ++ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_clear_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, ++ AN8855_RG_QP_CDR_PR_XFICK_EN); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1, ++ AN8855_RG_QP_CDR_PR_KBAND_DIV, ++ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_26, ++ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN | ++ AN8855_RG_LINK_NE_EN | ++ AN8855_RG_LINK_ERRO_EN, ++ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN | ++ AN8855_RG_LINK_ERRO_EN); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RX_DLY_0, ++ AN8855_RG_QP_RX_SAOSC_EN_H_DLY | ++ AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, ++ FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) | ++ FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_42, ++ AN8855_RG_QP_EQ_EN_DLY, ++ FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_2, ++ AN8855_RG_QP_RX_EQ_EN_H_DLY, ++ FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_9, ++ AN8855_RG_QP_EQ_LEQOSC_DLYCNT, ++ FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_8, ++ AN8855_RG_DA_QP_SAOSC_DONE_TIME | ++ AN8855_RG_DA_QP_LEQOS_EN_TIME, ++ FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) | ++ FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff)); ++ if (ret) ++ return ret; ++ ++ /* Frequency meter */ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = 0x10; ++ else ++ val = 0x28; ++ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_5, ++ AN8855_RG_FREDET_CHK_CYCLE, ++ FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_6, ++ AN8855_RG_FREDET_GOLDEN_CYCLE, ++ FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_7, ++ AN8855_RG_FREDET_TOLERATE_CYCLE, ++ FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_0, ++ AN8855_RG_PHYA_AUTO_INIT); ++ if (ret) ++ return ret; ++ ++ /* PCS Init */ ++ if (interface == PHY_INTERFACE_MODE_SGMII && ++ neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) { ++ ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0, ++ AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN); ++ if (ret) ++ return ret; ++ } ++ ++ ret = regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1, ++ AN8855_RG_TBI_10B_MODE); ++ if (ret) ++ return ret; ++ ++ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { ++ /* Set AN Ability - Interrupt */ ++ ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37, ++ AN8855_RG_FORCE_AN_DONE); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN_13, ++ AN8855_SGMII_REMOTE_FAULT_DIS | ++ AN8855_SGMII_IF_MODE, ++ AN8855_SGMII_REMOTE_FAULT_DIS | ++ FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb)); ++ if (ret) ++ return ret; ++ } ++ ++ /* Rate Adaption - GMII path config. */ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) { ++ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, ++ AN8855_RG_P0_DIS_MII_MODE); ++ if (ret) ++ return ret; ++ } else { ++ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { ++ ret = regmap_set_bits(priv->regmap, AN8855_MII_RA_AN_ENABLE, ++ AN8855_RG_P0_RA_AN_EN); ++ if (ret) ++ return ret; ++ } else { ++ ret = regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE, ++ AN8855_RG_FORCE_CUR_SGMII_MODE | ++ AN8855_RG_FORCE_CUR_SGMII_SEL, ++ AN8855_RG_FORCE_CUR_SGMII_SEL); ++ if (ret) ++ return ret; ++ ++ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, ++ AN8855_RG_P0_MII_RA_RX_EN | ++ AN8855_RG_P0_MII_RA_TX_EN | ++ AN8855_RG_P0_MII_RA_RX_MODE | ++ AN8855_RG_P0_MII_RA_TX_MODE); ++ if (ret) ++ return ret; ++ } ++ ++ ret = regmap_set_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0, ++ AN8855_RG_P0_MII_MODE); ++ if (ret) ++ return ret; ++ } ++ ++ ret = regmap_set_bits(priv->regmap, AN8855_RG_RATE_ADAPT_CTRL_0, ++ AN8855_RG_RATE_ADAPT_RX_BYPASS | ++ AN8855_RG_RATE_ADAPT_TX_BYPASS | ++ AN8855_RG_RATE_ADAPT_RX_EN | ++ AN8855_RG_RATE_ADAPT_TX_EN); ++ if (ret) ++ return ret; ++ ++ /* Disable AN if not in autoneg */ ++ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANENABLE, ++ neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE : ++ 0); ++ if (ret) ++ return ret; ++ ++ if (interface == PHY_INTERFACE_MODE_SGMII && ++ neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) { ++ ret = regmap_set_bits(priv->regmap, AN8855_PHY_RX_FORCE_CTRL_0, ++ AN8855_RG_FORCE_TXC_SEL); ++ if (ret) ++ return ret; ++ } ++ ++ /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */ ++ if (interface == PHY_INTERFACE_MODE_2500BASEX || ++ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) { ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val = AN8855_RG_LINK_MODE_P0_SPEED_2500; ++ else ++ val = AN8855_RG_LINK_MODE_P0_SPEED_1000; ++ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_STS_CTRL_0, ++ AN8855_RG_LINK_MODE_P0 | ++ AN8855_RG_FORCE_SPD_MODE_P0, ++ val | AN8855_RG_FORCE_SPD_MODE_P0); ++ if (ret) ++ return ret; ++ } ++ ++ /* bypass flow control to MAC */ ++ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_0, ++ AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 | ++ AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 | ++ AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0); ++ if (ret) ++ return ret; ++ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_2, ++ AN8855_RG_RXFC_AN_BYPASS_P3 | ++ AN8855_RG_RXFC_AN_BYPASS_P2 | ++ AN8855_RG_RXFC_AN_BYPASS_P1 | ++ AN8855_RG_TXFC_AN_BYPASS_P3 | ++ AN8855_RG_TXFC_AN_BYPASS_P2 | ++ AN8855_RG_TXFC_AN_BYPASS_P1 | ++ AN8855_RG_DPX_AN_BYPASS_P3 | ++ AN8855_RG_DPX_AN_BYPASS_P2 | ++ AN8855_RG_DPX_AN_BYPASS_P1 | ++ AN8855_RG_DPX_AN_BYPASS_P0); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void an8855_pcs_an_restart(struct phylink_pcs *pcs) ++{ ++ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs); ++ ++ regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANRESTART); ++} ++ ++static const struct phylink_pcs_ops an8855_pcs_ops = { ++ .pcs_get_state = an8855_pcs_get_state, ++ .pcs_config = an8855_pcs_config, ++ .pcs_an_restart = an8855_pcs_an_restart, ++}; ++ ++static const struct phylink_mac_ops an8855_phylink_mac_ops = { ++ .mac_select_pcs = an8855_phylink_mac_select_pcs, ++ .mac_config = an8855_phylink_mac_config, ++ .mac_link_down = an8855_phylink_mac_link_down, ++ .mac_link_up = an8855_phylink_mac_link_up, ++}; ++ ++static const struct dsa_switch_ops an8855_switch_ops = { ++ .get_tag_protocol = an8855_get_tag_protocol, ++ .setup = an8855_setup, ++ .get_phy_flags = en8855_get_phy_flags, ++ .phylink_get_caps = an8855_phylink_get_caps, ++ .get_strings = an8855_get_strings, ++ .get_ethtool_stats = an8855_get_ethtool_stats, ++ .get_sset_count = an8855_get_sset_count, ++ .get_eth_mac_stats = an8855_get_eth_mac_stats, ++ .get_eth_ctrl_stats = an8855_get_eth_ctrl_stats, ++ .get_rmon_stats = an8855_get_rmon_stats, ++ .port_enable = an8855_port_enable, ++ .port_disable = an8855_port_disable, ++ .get_mac_eee = an8855_get_mac_eee, ++ .set_mac_eee = an8855_set_mac_eee, ++ .set_ageing_time = an8855_set_ageing_time, ++ .port_bridge_join = an8855_port_bridge_join, ++ .port_bridge_leave = an8855_port_bridge_leave, ++ .port_fast_age = an8855_port_fast_age, ++ .port_stp_state_set = an8855_port_stp_state_set, ++ .port_pre_bridge_flags = an8855_port_pre_bridge_flags, ++ .port_bridge_flags = an8855_port_bridge_flags, ++ .port_vlan_filtering = an8855_port_vlan_filtering, ++ .port_vlan_add = an8855_port_vlan_add, ++ .port_vlan_del = an8855_port_vlan_del, ++ .port_fdb_add = an8855_port_fdb_add, ++ .port_fdb_del = an8855_port_fdb_del, ++ .port_fdb_dump = an8855_port_fdb_dump, ++ .port_mdb_add = an8855_port_mdb_add, ++ .port_mdb_del = an8855_port_mdb_del, ++ .port_change_mtu = an8855_port_change_mtu, ++ .port_max_mtu = an8855_port_max_mtu, ++ .port_mirror_add = an8855_port_mirror_add, ++ .port_mirror_del = an8855_port_mirror_del, ++}; ++ ++static int an8855_read_switch_id(struct an8855_priv *priv) ++{ ++ u32 id; ++ int ret; ++ ++ ret = regmap_read(priv->regmap, AN8855_CREV, &id); ++ if (ret) ++ return ret; ++ ++ if (id != AN8855_ID) { ++ dev_err(priv->dev, ++ "Switch id detected %x but expected %x", ++ id, AN8855_ID); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static int an8855_efuse_read(void *context, unsigned int offset, ++ void *val, size_t bytes) ++{ ++ struct an8855_priv *priv = context; ++ ++ return regmap_bulk_read(priv->regmap, AN8855_EFUSE_DATA0 + offset, ++ val, bytes / sizeof(u32)); ++} ++ ++static struct nvmem_config an8855_nvmem_config = { ++ .name = "an8855-efuse", ++ .size = AN8855_EFUSE_CELL * sizeof(u32), ++ .stride = sizeof(u32), ++ .word_size = sizeof(u32), ++ .reg_read = an8855_efuse_read, ++}; ++ ++static int an8855_sw_register_nvmem(struct an8855_priv *priv) ++{ ++ struct nvmem_device *nvmem; ++ ++ an8855_nvmem_config.priv = priv; ++ an8855_nvmem_config.dev = priv->dev; ++ nvmem = devm_nvmem_register(priv->dev, &an8855_nvmem_config); ++ if (IS_ERR(nvmem)) ++ return PTR_ERR(nvmem); ++ ++ return 0; ++} ++ ++static int ++an8855_sw_probe(struct mdio_device *mdiodev) ++{ ++ struct an8855_priv *priv; ++ u32 val; ++ int ret; ++ ++ priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->bus = mdiodev->bus; ++ priv->dev = &mdiodev->dev; ++ priv->phy_base = mdiodev->addr; ++ priv->phy_require_calib = of_property_read_bool(priv->dev->of_node, ++ "airoha,ext-surge"); ++ ++ priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset", ++ GPIOD_OUT_LOW); ++ if (IS_ERR(priv->reset_gpio)) ++ return PTR_ERR(priv->reset_gpio); ++ ++ priv->regmap = devm_regmap_init(priv->dev, NULL, priv, ++ &an8855_regmap_config); ++ if (IS_ERR(priv->regmap)) { ++ dev_err(priv->dev, "regmap initialization failed"); ++ return PTR_ERR(priv->regmap); ++ } ++ ++ if (priv->reset_gpio) { ++ usleep_range(100000, 150000); ++ gpiod_set_value_cansleep(priv->reset_gpio, 0); ++ usleep_range(100000, 150000); ++ gpiod_set_value_cansleep(priv->reset_gpio, 1); ++ ++ /* Poll HWTRAP reg to wait for Switch to fully Init */ ++ ret = regmap_read_poll_timeout(priv->regmap, AN8855_HWTRAP, val, ++ val, 20, 200000); ++ if (ret) ++ return ret; ++ } ++ ++ ret = an8855_read_switch_id(priv); ++ if (ret) ++ return ret; ++ ++ priv->ds = devm_kzalloc(priv->dev, sizeof(*priv->ds), GFP_KERNEL); ++ if (!priv->ds) ++ return -ENOMEM; ++ ++ priv->ds->dev = priv->dev; ++ priv->ds->num_ports = AN8855_NUM_PORTS; ++ priv->ds->priv = priv; ++ priv->ds->ops = &an8855_switch_ops; ++ devm_mutex_init(priv->dev, &priv->reg_mutex); ++ priv->ds->phylink_mac_ops = &an8855_phylink_mac_ops; ++ ++ priv->pcs.ops = &an8855_pcs_ops; ++ priv->pcs.neg_mode = true; ++ priv->pcs.poll = true; ++ ++ ret = an8855_sw_register_nvmem(priv); ++ if (ret) ++ return ret; ++ ++ dev_set_drvdata(priv->dev, priv); ++ ++ return devm_dsa_register_switch(priv->dev, priv->ds); ++} ++ ++static const struct of_device_id an8855_of_match[] = { ++ { .compatible = "airoha,an8855" }, ++ { /* sentinel */ } ++}; ++ ++static struct mdio_driver an8855_mdio_driver = { ++ .probe = an8855_sw_probe, ++ .mdiodrv.driver = { ++ .name = "an8855", ++ .of_match_table = an8855_of_match, ++ }, ++}; ++ ++mdio_module_driver(an8855_mdio_driver); ++ ++MODULE_AUTHOR("Min Yao "); ++MODULE_AUTHOR("Christian Marangi "); ++MODULE_DESCRIPTION("Driver for Airoha AN8855 Switch"); ++MODULE_LICENSE("GPL"); +diff --git a/target/linux/mediatek/files-6.6/drivers/net/dsa/an8855.h b/target/linux/mediatek/files-6.6/drivers/net/dsa/an8855.h +new file mode 100644 +index 00000000000000..632c0e511bc374 +--- /dev/null ++++ b/target/linux/mediatek/files-6.6/drivers/net/dsa/an8855.h +@@ -0,0 +1,753 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2023 Min Yao ++ * Copyright (C) 2024 Christian Marangi ++ */ ++ ++#ifndef __AN8855_H ++#define __AN8855_H ++ ++#include ++ ++#define AN8855_NUM_PORTS 6 ++#define AN8855_CPU_PORT 5 ++#define AN8855_NUM_FDB_RECORDS 2048 ++#define AN8855_GPHY_SMI_ADDR_DEFAULT 1 ++#define AN8855_PORT_VID_DEFAULT 0 ++#define AN8855_EFUSE_CELL 50 ++ ++#define MTK_TAG_LEN 4 ++#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN) ++ ++#define AN8855_L2_AGING_MS_CONSTANT 1024 ++ ++#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0) ++ ++/* MII Registers */ ++#define AN8855_PHY_SELECT_PAGE 0x1f ++#define AN8855_PHY_PAGE GENMASK(2, 0) ++#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) ++#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1) ++#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4) ++ ++/* MII Registers Page 4 */ ++#define AN8855_PBUS_MODE 0x10 ++#define AN8855_PBUS_MODE_ADDR_FIXED 0x0 ++#define AN8855_PBUS_MODE_ADDR_INCR BIT(15) ++#define AN8855_PBUS_WR_ADDR_HIGH 0x11 ++#define AN8855_PBUS_WR_ADDR_LOW 0x12 ++#define AN8855_PBUS_WR_DATA_HIGH 0x13 ++#define AN8855_PBUS_WR_DATA_LOW 0x14 ++#define AN8855_PBUS_RD_ADDR_HIGH 0x15 ++#define AN8855_PBUS_RD_ADDR_LOW 0x16 ++#define AN8855_PBUS_RD_DATA_HIGH 0x17 ++#define AN8855_PBUS_RD_DATA_LOW 0x18 ++ ++/* AN8855_SCU 0x10000000 */ ++#define AN8855_RG_GPIO_LED_MODE 0x10000054 ++#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4))) ++#define AN8855_RG_INTB_MODE 0x10000080 ++#define AN8855_RG_RGMII_TXCK_C 0x100001d0 ++ ++#define AN8855_PKG_SEL 0x10000094 ++#define AN8855_PAG_SEL_AN8855H 0x2 ++ ++/* Register for hw trap status */ ++#define AN8855_HWTRAP 0x1000009c ++ ++#define AN8855_RG_GPIO_L_INV 0x10000010 ++#define AN8855_RG_GPIO_CTRL 0x1000a300 ++#define AN8855_RG_GPIO_DATA 0x1000a304 ++#define AN8855_RG_GPIO_OE 0x1000a314 ++ ++#define AN8855_EFUSE_DATA0 0x1000a500 ++#define AN8855_EFUSE_R50O GENMASK(30, 24) ++ ++#define AN8855_CREV 0x10005000 ++#define AN8855_ID 0x8855 ++ ++/* Register for system reset */ ++#define AN8855_RST_CTRL 0x100050c0 ++#define AN8855_SYS_CTRL_SYS_RST BIT(31) ++ ++#define AN8855_INT_MASK 0x100050f0 ++#define AN8855_INT_SYS BIT(15) ++ ++#define AN8855_RG_CLK_CPU_ICG 0x10005034 ++#define AN8855_MCU_ENABLE BIT(3) ++ ++#define AN8855_RG_TIMER_CTL 0x1000a100 ++#define AN8855_WDOG_ENABLE BIT(25) ++ ++#define AN8855_RG_GDMP_RAM 0x10010000 ++ ++/* Registers to mac forward control for unknown frames */ ++#define AN8855_MFC 0x10200010 ++#define AN8855_CPU_EN BIT(15) ++#define AN8855_CPU_PORT_IDX GENMASK(12, 8) ++ ++#define AN8855_AAC 0x102000a0 ++#define AN8855_MAC_AUTO_FLUSH BIT(28) ++/* Control Address Table Age time. ++ * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT ++ */ ++#define AN8855_AGE_CNT GENMASK(20, 12) ++/* Value in seconds. Value is always incremented of 1 */ ++#define AN8855_AGE_UNIT GENMASK(10, 0) ++ ++/* Registers for ARL Unknown Unicast Forward control */ ++#define AN8855_UNUF 0x102000b4 ++ ++/* Registers for ARL Unknown Multicast Forward control */ ++#define AN8855_UNMF 0x102000b8 ++ ++/* Registers for ARL Broadcast forward control */ ++#define AN8855_BCF 0x102000bc ++ ++/* Registers for port address age disable */ ++#define AN8855_AGDIS 0x102000c0 ++ ++/* Registers for mirror port control */ ++#define AN8855_MIR 0x102000cc ++#define AN8855_MIRROR_EN BIT(7) ++#define AN8855_MIRROR_PORT GENMASK(4, 0) ++ ++/* Registers for BPDU and PAE frame control*/ ++#define AN8855_BPC 0x102000D0 ++#define AN8855_BPDU_PORT_FW GENMASK(2, 0) ++ ++enum an8855_bpdu_port_fw { ++ AN8855_BPDU_FOLLOW_MFC = 0, ++ AN8855_BPDU_CPU_EXCLUDE = 4, ++ AN8855_BPDU_CPU_INCLUDE = 5, ++ AN8855_BPDU_CPU_ONLY = 6, ++ AN8855_BPDU_DROP = 7, ++}; ++ ++/* Register for address table control */ ++#define AN8855_ATC 0x10200300 ++#define AN8855_ATC_BUSY BIT(31) ++#define AN8855_ATC_HASH GENMASK(24, 16) ++#define AN8855_ATC_HIT GENMASK(15, 12) ++#define AN8855_ATC_MAT_MASK GENMASK(11, 7) ++#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x) ++#define AN8855_ATC_SAT GENMASK(5, 4) ++#define AN8855_ATC_CMD GENMASK(2, 0) ++ ++enum an8855_fdb_mat_cmds { ++ AND8855_FDB_MAT_ALL = 0, ++ AND8855_FDB_MAT_MAC, /* All MAC address */ ++ AND8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */ ++ AND8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */ ++ AND8855_FDB_MAT_DIP, /* All DIP/GA address */ ++ AND8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */ ++ AND8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */ ++ AND8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */ ++ AND8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */ ++ AND8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */ ++ AND8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */ ++ AND8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */ ++ AND8855_FDB_MAT_MAC_PORT, /* All MAC address with port */ ++ AND8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */ ++ AND8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */ ++ AND8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */ ++ AND8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */ ++ /* All MAC address with MAC type (dynamic or static) with CVID */ ++ AND8855_FDB_MAT_MAC_TYPE_CVID, ++ /* All MAC address with MAC type (dynamic or static) with Filter ID */ ++ AND8855_FDB_MAT_MAC_TYPE_FID, ++ /* All MAC address with MAC type (dynamic or static) with port */ ++ AND8855_FDB_MAT_MAC_TYPE_PORT, ++}; ++ ++enum an8855_fdb_cmds { ++ AN8855_FDB_READ = 0, ++ AN8855_FDB_WRITE = 1, ++ AN8855_FDB_FLUSH = 2, ++ AN8855_FDB_START = 4, ++ AN8855_FDB_NEXT = 5, ++}; ++ ++/* Registers for address table access */ ++#define AN8855_ATA1 0x10200304 ++#define AN8855_ATA1_MAC0 GENMASK(31, 24) ++#define AN8855_ATA1_MAC1 GENMASK(23, 16) ++#define AN8855_ATA1_MAC2 GENMASK(15, 8) ++#define AN8855_ATA1_MAC3 GENMASK(7, 0) ++#define AN8855_ATA2 0x10200308 ++#define AN8855_ATA2_MAC4 GENMASK(31, 24) ++#define AN8855_ATA2_MAC5 GENMASK(23, 16) ++#define AN8855_ATA2_UNAUTH BIT(10) ++#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */ ++#define AN8855_ATA2_AGE GENMASK(8, 0) ++ ++/* Register for address table write data */ ++#define AN8855_ATWD 0x10200324 ++#define AN8855_ATWD_FID GENMASK(31, 28) ++#define AN8855_ATWD_VID GENMASK(27, 16) ++#define AN8855_ATWD_IVL BIT(15) ++#define AN8855_ATWD_EG_TAG GENMASK(14, 12) ++#define AN8855_ATWD_SA_MIR GENMASK(9, 8) ++#define AN8855_ATWD_SA_FWD GENMASK(7, 5) ++#define AN8855_ATWD_UPRI GENMASK(4, 2) ++#define AN8855_ATWD_LEAKY BIT(1) ++#define AN8855_ATWD_VLD BIT(0) /* vid LOAD */ ++#define AN8855_ATWD2 0x10200328 ++#define AN8855_ATWD2_PORT GENMASK(7, 0) ++ ++/* Registers for table search read address */ ++#define AN8855_ATRDS 0x10200330 ++#define AN8855_ATRD_SEL GENMASK(1, 0) ++#define AN8855_ATRD0 0x10200334 ++#define AN8855_ATRD0_FID GENMASK(28, 25) ++#define AN8855_ATRD0_VID GENMASK(21, 10) ++#define AN8855_ATRD0_IVL BIT(9) ++#define AN8855_ATRD0_TYPE GENMASK(4, 3) ++#define AN8855_ATRD0_ARP GENMASK(2, 1) ++#define AN8855_ATRD0_LIVE BIT(0) ++#define AN8855_ATRD1 0x10200338 ++#define AN8855_ATRD1_MAC4 GENMASK(31, 24) ++#define AN8855_ATRD1_MAC5 GENMASK(23, 16) ++#define AN8855_ATRD1_AGING GENMASK(10, 3) ++#define AN8855_ATRD2 0x1020033c ++#define AN8855_ATRD2_MAC0 GENMASK(31, 24) ++#define AN8855_ATRD2_MAC1 GENMASK(23, 16) ++#define AN8855_ATRD2_MAC2 GENMASK(15, 8) ++#define AN8855_ATRD2_MAC3 GENMASK(7, 0) ++#define AN8855_ATRD3 0x10200340 ++#define AN8855_ATRD3_PORTMASK GENMASK(7, 0) ++ ++enum an8855_fdb_type { ++ AN8855_MAC_TB_TY_MAC = 0, ++ AN8855_MAC_TB_TY_DIP = 1, ++ AN8855_MAC_TB_TY_DIP_SIP = 2, ++}; ++ ++/* Register for vlan table control */ ++#define AN8855_VTCR 0x10200600 ++#define AN8855_VTCR_BUSY BIT(31) ++#define AN8855_VTCR_FUNC GENMASK(15, 12) ++#define AN8855_VTCR_VID GENMASK(11, 0) ++ ++enum an8855_vlan_cmd { ++ /* Read/Write the specified VID entry from VAWD register based ++ * on VID. ++ */ ++ AN8855_VTCR_RD_VID = 0, ++ AN8855_VTCR_WR_VID = 1, ++}; ++ ++/* Register for setup vlan write data */ ++#define AN8855_VAWD0 0x10200604 ++/* VLAN Member Control */ ++#define AN8855_VA0_PORT GENMASK(31, 26) ++/* Egress Tag Control */ ++#define AN8855_VA0_ETAG GENMASK(23, 12) ++#define AN8855_VA0_ETAG_PORT GENMASK(13, 12) ++#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2) ++#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \ ++ AN8855_VA0_ETAG_PORT_SHIFT(port)) ++#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \ ++ AN8855_VA0_ETAG_PORT_SHIFT(port)) ++#define AN8855_VA0_EG_CON BIT(11) ++#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */ ++#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */ ++#define AN8855_VA0_FID GENMASK(4, 1) ++#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */ ++#define AN8855_VAWD1 0x10200608 ++#define AN8855_VA1_PORT_STAG BIT(1) ++ ++enum an8855_fid { ++ AN8855_FID_STANDALONE = 0, ++ AN8855_FID_BRIDGED = 1, ++}; ++ ++/* Same register field of VAWD0 */ ++#define AN8855_VARD0 0x10200618 ++ ++enum an8855_vlan_egress_attr { ++ AN8855_VLAN_EGRESS_UNTAG = 0, ++ AN8855_VLAN_EGRESS_TAG = 2, ++ AN8855_VLAN_EGRESS_STACK = 3, ++}; ++ ++/* Register for port STP state control */ ++#define AN8855_SSP_P(x) (0x10208000 + ((x) * 0x200)) ++/* Up to 16 FID supported, each with the same mask */ ++#define AN8855_FID_PST GENMASK(1, 0) ++#define AN8855_FID_PST_SHIFT(fid) (2 * (fid)) ++#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \ ++ AN8855_FID_PST_SHIFT(fid)) ++#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) << \ ++ AN8855_FID_PST_SHIFT(fid)) ++ ++enum an8855_stp_state { ++ AN8855_STP_DISABLED = 0, ++ AN8855_STP_BLOCKING = 1, ++ AN8855_STP_LISTENING = AN8855_STP_BLOCKING, ++ AN8855_STP_LEARNING = 2, ++ AN8855_STP_FORWARDING = 3 ++}; ++ ++/* Register for port control */ ++#define AN8855_PCR_P(x) (0x10208004 + ((x) * 0x200)) ++#define AN8855_EG_TAG GENMASK(29, 28) ++#define AN8855_PORT_PRI GENMASK(26, 24) ++#define AN8855_PORT_TX_MIR BIT(20) ++#define AN8855_PORT_RX_MIR BIT(16) ++#define AN8855_PORT_VLAN GENMASK(1, 0) ++ ++enum an8855_port_mode { ++ /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ ++ AN8855_PORT_MATRIX_MODE = 0, ++ ++ /* Fallback Mode: Forward received frames with ingress ports that do ++ * not belong to the VLAN member. Frames whose VID is not listed on ++ * the VLAN table are forwarded by the PCR_MATRIX members. ++ */ ++ AN8855_PORT_FALLBACK_MODE = 1, ++ ++ /* Check Mode: Forward received frames whose ingress do not ++ * belong to the VLAN member. Discard frames if VID ismiddes on the ++ * VLAN table. ++ */ ++ AN8855_PORT_CHECK_MODE = 2, ++ ++ /* Security Mode: Discard any frame due to ingress membership ++ * violation or VID missed on the VLAN table. ++ */ ++ AN8855_PORT_SECURITY_MODE = 3, ++}; ++ ++/* Register for port security control */ ++#define AN8855_PSC_P(x) (0x1020800c + ((x) * 0x200)) ++#define AN8855_SA_DIS BIT(4) ++ ++/* Register for port vlan control */ ++#define AN8855_PVC_P(x) (0x10208010 + ((x) * 0x200)) ++#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11) ++#define AN8855_PVC_EG_TAG GENMASK(10, 8) ++#define AN8855_VLAN_ATTR GENMASK(7, 6) ++#define AN8855_PORT_SPEC_TAG BIT(5) ++#define AN8855_ACC_FRM GENMASK(1, 0) ++ ++enum an8855_vlan_port_eg_tag { ++ AN8855_VLAN_EG_DISABLED = 0, ++ AN8855_VLAN_EG_CONSISTENT = 1, ++ AN8855_VLAN_EG_UNTAGGED = 4, ++ AN8855_VLAN_EG_SWAP = 5, ++ AN8855_VLAN_EG_TAGGED = 6, ++ AN8855_VLAN_EG_STACK = 7, ++}; ++ ++enum an8855_vlan_port_attr { ++ AN8855_VLAN_USER = 0, ++ AN8855_VLAN_STACK = 1, ++ AN8855_VLAN_TRANSPARENT = 3, ++}; ++ ++enum an8855_vlan_port_acc_frm { ++ AN8855_VLAN_ACC_ALL = 0, ++ AN8855_VLAN_ACC_TAGGED = 1, ++ AN8855_VLAN_ACC_UNTAGGED = 2, ++}; ++ ++#define AN8855_PPBV1_P(x) (0x10208014 + ((x) * 0x200)) ++#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0) ++ ++#define AN8855_PORTMATRIX_P(x) (0x10208044 + ((x) * 0x200)) ++#define AN8855_PORTMATRIX GENMASK(5, 0) ++/* Port matrix without the CPU port that should never be removed */ ++#define AN8855_USER_PORTMATRIX GENMASK(4, 0) ++ ++/* Register for port PVID */ ++#define AN8855_PVID_P(x) (0x10208048 + ((x) * 0x200)) ++#define AN8855_G0_PORT_VID GENMASK(11, 0) ++ ++/* Register for port MAC control register */ ++#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200)) ++#define AN8855_PMCR_FORCE_MODE BIT(31) ++#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28) ++#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4) ++#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3) ++#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2) ++#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1) ++#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1) ++#define AN8855_PMCR_FORCE_FDX BIT(25) ++#define AN8855_PMCR_FORCE_LNK BIT(24) ++#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20) ++#define AN8855_PMCR_EXT_PHY BIT(19) ++#define AN8855_PMCR_MAC_MODE BIT(18) ++#define AN8855_PMCR_TX_EN BIT(16) ++#define AN8855_PMCR_RX_EN BIT(15) ++#define AN8855_PMCR_BACKOFF_EN BIT(12) ++#define AN8855_PMCR_BACKPR_EN BIT(11) ++#define AN8855_PMCR_FORCE_EEE5G BIT(9) ++#define AN8855_PMCR_FORCE_EEE2P5G BIT(8) ++#define AN8855_PMCR_FORCE_EEE1G BIT(7) ++#define AN8855_PMCR_FORCE_EEE100 BIT(6) ++#define AN8855_PMCR_TX_FC_EN BIT(5) ++#define AN8855_PMCR_RX_FC_EN BIT(4) ++ ++#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200) ++#define AN8855_PMSR_SPEED GENMASK(30, 28) ++#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4) ++#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3) ++#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2) ++#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1) ++#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0) ++#define AN8855_PMSR_DPX BIT(25) ++#define AN8855_PMSR_LNK BIT(24) ++#define AN8855_PMSR_EEE1G BIT(7) ++#define AN8855_PMSR_EEE100M BIT(6) ++#define AN8855_PMSR_RX_FC BIT(5) ++#define AN8855_PMSR_TX_FC BIT(4) ++ ++#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200) ++#define AN8855_LPI_MODE_EN BIT(31) ++#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16) ++#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8) ++#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0) ++#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200) ++#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0) ++ ++#define AN8855_GMACCR 0x10213e00 ++#define AN8855_MAX_RX_JUMBO GENMASK(7, 4) ++/* 2K for 0x0, 0x1, 0x2 */ ++#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0) ++#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3) ++#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4) ++#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5) ++#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6) ++#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7) ++#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8) ++#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9) ++#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa) ++#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb) ++#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc) ++#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0) ++#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0) ++#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1) ++#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2) ++#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3) ++ ++#define AN8855_CKGCR 0x10213e1c ++#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14) ++#define AN8855_CKG_LNKDN_PORT_STOP BIT(1) ++#define AN8855_CKG_LNKDN_GLB_STOP BIT(0) ++ ++/* Register for MIB */ ++#define AN8855_PORT_MIB_COUNTER(x) (0x10214000 + (x) * 0x200) ++/* Each define is an offset of AN8855_PORT_MIB_COUNTER */ ++#define AN8855_PORT_MIB_TX_DROP 0x00 ++#define AN8855_PORT_MIB_TX_CRC_ERR 0x04 ++#define AN8855_PORT_MIB_TX_UNICAST 0x08 ++#define AN8855_PORT_MIB_TX_MULTICAST 0x0c ++#define AN8855_PORT_MIB_TX_BROADCAST 0x10 ++#define AN8855_PORT_MIB_TX_COLLISION 0x14 ++#define AN8855_PORT_MIB_TX_SINGLE_COLLISION 0x18 ++#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c ++#define AN8855_PORT_MIB_TX_DEFERRED 0x20 ++#define AN8855_PORT_MIB_TX_LATE_COLLISION 0x24 ++#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28 ++#define AN8855_PORT_MIB_TX_PAUSE 0x2c ++#define AN8855_PORT_MIB_TX_PKT_SZ_64 0x30 ++#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34 ++#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38 ++#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3 ++#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40 ++#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 0x44 ++#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX 0x48 ++#define AN8855_PORT_MIB_TX_BYTES 0x4c /* 64 bytes */ ++#define AN8855_PORT_MIB_TX_OVERSIZE_DROP 0x54 ++#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES 0x58 /* 64 bytes */ ++#define AN8855_PORT_MIB_RX_DROP 0x80 ++#define AN8855_PORT_MIB_RX_FILTERING 0x84 ++#define AN8855_PORT_MIB_RX_UNICAST 0x88 ++#define AN8855_PORT_MIB_RX_MULTICAST 0x8c ++#define AN8855_PORT_MIB_RX_BROADCAST 0x90 ++#define AN8855_PORT_MIB_RX_ALIGN_ERR 0x94 ++#define AN8855_PORT_MIB_RX_CRC_ERR 0x98 ++#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR 0x9c ++#define AN8855_PORT_MIB_RX_FRAG_ERR 0xa0 ++#define AN8855_PORT_MIB_RX_OVER_SZ_ERR 0xa4 ++#define AN8855_PORT_MIB_RX_JABBER_ERR 0xa8 ++#define AN8855_PORT_MIB_RX_PAUSE 0xac ++#define AN8855_PORT_MIB_RX_PKT_SZ_64 0xb0 ++#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 0xb4 ++#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 0xb8 ++#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 0xbc ++#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xc0 ++#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 0xc4 ++#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX 0xc8 ++#define AN8855_PORT_MIB_RX_BYTES 0xcc /* 64 bytes */ ++#define AN8855_PORT_MIB_RX_CTRL_DROP 0xd4 ++#define AN8855_PORT_MIB_RX_INGRESS_DROP 0xd8 ++#define AN8855_PORT_MIB_RX_ARL_DROP 0xdc ++#define AN8855_PORT_MIB_FLOW_CONTROL_DROP 0xe0 ++#define AN8855_PORT_MIB_WRED_DROP 0xe4 ++#define AN8855_PORT_MIB_MIRROR_DROP 0xe8 ++#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES 0xec /* 64 bytes */ ++#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP 0xf4 ++#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP 0xf8 ++#define AN8855_PORT_MIB_PORT_CONTROL_DROP 0xfc ++#define AN8855_MIB_CCR 0x10213e30 ++#define AN8855_CCR_MIB_ENABLE BIT(31) ++#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7) ++#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6) ++#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5) ++#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4) ++#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3) ++#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2) ++#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1) ++#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0) ++#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \ ++ AN8855_CCR_RX_OCT_CNT_GOOD | \ ++ AN8855_CCR_RX_OCT_CNT_BAD | \ ++ AN8855_CCR_TX_OCT_CNT_GOOD | \ ++ AN8855_CCR_TX_OCT_CNT_BAD | \ ++ AN8855_CCR_RX_OCT_CNT_BAD_2 | \ ++ AN8855_CCR_TX_OCT_CNT_BAD_2) ++#define AN8855_MIB_CLR 0x10213e34 ++#define AN8855_MIB_PORT6_CLR BIT(6) ++#define AN8855_MIB_PORT5_CLR BIT(5) ++#define AN8855_MIB_PORT4_CLR BIT(4) ++#define AN8855_MIB_PORT3_CLR BIT(3) ++#define AN8855_MIB_PORT2_CLR BIT(2) ++#define AN8855_MIB_PORT1_CLR BIT(1) ++#define AN8855_MIB_PORT0_CLR BIT(0) ++ ++/* HSGMII/SGMII Configuration register */ ++/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */ ++#define AN8855_SGMII_REG_AN0 0x10220000 ++/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */ ++/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */ ++#define AN8855_SGMII_REG_AN_13 0x10220034 ++#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8) ++#define AN8855_SGMII_IF_MODE GENMASK(5, 0) ++#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060 ++#define AN8855_RG_FORCE_AN_DONE BIT(0) ++ ++/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */ ++#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00 ++#define AN8855_RG_TBI_10B_MODE BIT(30) ++#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24 ++#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4) ++#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0) ++ ++/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */ ++#define AN8855_SGMII_STS_CTRL_0 0x10224018 ++#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4) ++#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3) ++#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2) ++#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1) ++#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0) ++#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2) ++#define AN8855_MSG_RX_CTRL_0 0x10224100 ++#define AN8855_MSG_RX_LIK_STS_0 0x10224514 ++#define AN8855_RG_DPX_STS_P3 BIT(24) ++#define AN8855_RG_DPX_STS_P2 BIT(16) ++#define AN8855_RG_EEE1G_STS_P1 BIT(12) ++#define AN8855_RG_DPX_STS_P1 BIT(8) ++#define AN8855_RG_TXFC_STS_P0 BIT(2) ++#define AN8855_RG_RXFC_STS_P0 BIT(1) ++#define AN8855_RG_DPX_STS_P0 BIT(0) ++#define AN8855_MSG_RX_LIK_STS_2 0x1022451c ++#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11) ++#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10) ++#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9) ++#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7) ++#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6) ++#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5) ++#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3) ++#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2) ++#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1) ++#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0) ++#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520 ++#define AN8855_RG_FORCE_TXC_SEL BIT(4) ++ ++/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */ ++#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8 ++ ++/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */ ++#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000 ++#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27) ++#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26) ++#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4) ++#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0) ++#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100 ++#define AN8855_RG_P0_DIS_MII_MODE BIT(31) ++#define AN8855_RG_P0_MII_MODE BIT(28) ++#define AN8855_RG_P0_MII_RA_RX_EN BIT(3) ++#define AN8855_RG_P0_MII_RA_TX_EN BIT(2) ++#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1) ++#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0) ++#define AN8855_MII_RA_AN_ENABLE 0x10226300 ++#define AN8855_RG_P0_RA_AN_EN BIT(0) ++ ++/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */ ++#define AN8855_QP_CK_RST_CTRL_4 0x1022a310 ++#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324 ++#define AN8855_RG_SGMII_MODE GENMASK(5, 4) ++#define AN8855_RG_SGMII_AN_EN BIT(0) ++#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330 ++#define AN8855_RG_TPHY_SPEED GENMASK(3, 2) ++ ++/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */ ++#define AN8855_USGMII_CTRL_0 0x1022c000 ++ ++/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */ ++#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100 ++#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12) ++#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124 ++#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0) ++ ++#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208 ++#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16) ++#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230 ++#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0) ++#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c ++#define AN8855_RG_LCPLL_NCPO_CHG BIT(24) ++#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248 ++#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0) ++#define AN8855_INTF_CTRL_8 0x1022e320 ++#define AN8855_INTF_CTRL_9 0x1022e324 ++#define AN8855_INTF_CTRL_10 0x1022e328 ++#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29) ++#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24) ++#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21) ++#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16) ++#define AN8855_INTF_CTRL_11 0x1022e32c ++#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6) ++#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0) ++#define AN8855_PLL_CTRL_0 0x1022e400 ++#define AN8855_RG_PHYA_AUTO_INIT BIT(0) ++#define AN8855_PLL_CTRL_2 0x1022e408 ++#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30) ++#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29) ++#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28) ++#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27) ++#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26) ++#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24) ++#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22) ++#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20) ++#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16) ++#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14) ++#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12) ++#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8) ++#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6) ++#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2) ++#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0) ++#define AN8855_PLL_CTRL_3 0x1022e40c ++#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16) ++#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0) ++#define AN8855_PLL_CTRL_4 0x1022e410 ++#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3) ++#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2) ++#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0) ++#define AN8855_PLL_CK_CTRL_0 0x1022e414 ++#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9) ++#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8) ++#define AN8855_RX_DLY_0 0x1022e614 ++#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8) ++#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0) ++#define AN8855_RX_CTRL_2 0x1022e630 ++#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16) ++#define AN8855_RX_CTRL_5 0x1022e63c ++#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10) ++#define AN8855_RX_CTRL_6 0x1022e640 ++#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0) ++#define AN8855_RX_CTRL_7 0x1022e644 ++#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0) ++#define AN8855_RX_CTRL_8 0x1022e648 ++#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16) ++#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0) ++#define AN8855_RX_CTRL_26 0x1022e690 ++#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26) ++#define AN8855_RG_LINK_NE_EN BIT(24) ++#define AN8855_RG_LINK_ERRO_EN BIT(23) ++#define AN8855_RX_CTRL_42 0x1022e6d0 ++#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0) ++ ++/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */ ++#define AN8855_RG_QP_RX_DAC_EN 0x1022f000 ++#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16) ++#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004 ++#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11) ++#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008 ++#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24) ++#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20) ++#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c ++#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4) ++#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014 ++#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29) ++#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25) ++#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018 ++#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24) ++#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8) ++#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c ++#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30) ++#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6) ++#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0) ++#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020 ++#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16) ++#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13) ++#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6) ++#define AN8855_RG_QP_TX_MODE 0x1022f028 ++#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16) ++#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0) ++#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c ++#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040 ++#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4) ++#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3) ++ ++/* AN8855_ETHER_SYS_BASE 0x1028c800 */ ++#define AN8855_RG_GPHY_AFE_PWD 0x1028c840 ++#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848 ++ ++#define MIB_DESC(_s, _o, _n) \ ++ { \ ++ .size = (_s), \ ++ .offset = (_o), \ ++ .name = (_n), \ ++ } ++ ++struct an8855_mib_desc { ++ unsigned int size; ++ unsigned int offset; ++ const char *name; ++}; ++ ++struct an8855_fdb { ++ u16 vid; ++ u8 port_mask; ++ u8 aging; ++ u8 mac[6]; ++ bool noarp; ++ u8 live; ++ u8 type; ++ u8 fid; ++ u8 ivl; ++}; ++ ++struct an8855_priv { ++ struct device *dev; ++ struct dsa_switch *ds; ++ struct mii_bus *bus; ++ struct regmap *regmap; ++ struct gpio_desc *reset_gpio; ++ /* Protect ATU or VLAN table access */ ++ struct mutex reg_mutex; ++ ++ struct phylink_pcs pcs; ++ ++ unsigned int phy_base; ++ ++ u8 mirror_rx; ++ u8 mirror_tx; ++ u8 port_isolated_map; ++ ++ bool phy_require_calib; ++}; ++ ++#endif /* __AN8855_H */ +diff --git a/target/linux/mediatek/files-6.6/drivers/net/phy/air_an8855.c b/target/linux/mediatek/files-6.6/drivers/net/phy/air_an8855.c +new file mode 100644 +index 00000000000000..10627ea2be3873 +--- /dev/null ++++ b/target/linux/mediatek/files-6.6/drivers/net/phy/air_an8855.c +@@ -0,0 +1,268 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2024 Christian Marangi ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#define AN8855_PHY_SELECT_PAGE 0x1f ++/* Mask speculation based on page up to 0x4 */ ++#define AN8855_PHY_PAGE GENMASK(2, 0) ++#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) ++#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1) ++ ++/* MII Registers Page 1 */ ++#define AN8855_PHY_EXT_REG_14 0x14 ++#define AN8855_PHY_EN_DOWN_SHIFT BIT(4) ++ ++/* R50 Calibration regs in MDIO_MMD_VEND1 */ ++#define AN8855_PHY_R500HM_RSEL_TX_AB 0x174 ++#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15) ++#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8) ++#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7) ++#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0) ++#define AN8855_PHY_R500HM_RSEL_TX_CD 0x175 ++#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15) ++#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8) ++#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7) ++#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0) ++ ++#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24) ++ ++/* PHY TX PAIR DELAY SELECT Register */ ++#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013 ++#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE GENMASK(14, 12) ++#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_B_GBE GENMASK(10, 8) ++#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE GENMASK(6, 4) ++#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_D_GBE GENMASK(2, 0) ++/* PHY ADC Register */ ++#define AN8855_PHY_RXADC_CTRL 0x0d8 ++#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A BIT(12) ++#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_B BIT(8) ++#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C BIT(4) ++#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_D BIT(0) ++#define AN8855_PHY_RXADC_REV_0 0x0d9 ++#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8) ++#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0) ++#define AN8855_PHY_RXADC_REV_1 0x0da ++#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8) ++#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0) ++ ++#define AN8855_PHY_ID 0xc0ff0410 ++ ++#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0) ++ ++struct air_an8855_priv { ++ u8 calibration_data[4]; ++}; ++ ++static const u8 dsa_r50ohm_table[] = { ++ 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, ++ 127, 127, 127, 127, 127, 127, 127, 126, 122, 117, ++ 112, 109, 104, 101, 97, 94, 90, 88, 84, 80, ++ 78, 74, 72, 68, 66, 64, 61, 58, 56, 53, ++ 51, 48, 47, 44, 42, 40, 38, 36, 34, 32, ++ 31, 28, 27, 24, 24, 22, 20, 18, 16, 16, ++ 14, 12, 11, 9 ++}; ++ ++static int en8855_get_r50ohm_val(struct device *dev, const char *calib_name, ++ u8 *dest) ++{ ++ u32 shift_sel, val; ++ int ret; ++ int i; ++ ++ ret = nvmem_cell_read_u32(dev, calib_name, &val); ++ if (ret) ++ return ret; ++ ++ shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val); ++ for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++) ++ if (dsa_r50ohm_table[i] == shift_sel) ++ break; ++ ++ if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table)) ++ *dest = dsa_r50ohm_table[25]; ++ else ++ *dest = dsa_r50ohm_table[i - 8]; ++ ++ return 0; ++} ++ ++static int an8855_probe(struct phy_device *phydev) ++{ ++ struct device *dev = &phydev->mdio.dev; ++ struct device_node *node = dev->of_node; ++ struct air_an8855_priv *priv; ++ int ret; ++ ++ /* If we don't have a node, skip get calib */ ++ if (!node) ++ return 0; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ ret = en8855_get_r50ohm_val(dev, "tx_a", &priv->calibration_data[0]); ++ if (ret) ++ return ret; ++ ++ ret = en8855_get_r50ohm_val(dev, "tx_b", &priv->calibration_data[1]); ++ if (ret) ++ return ret; ++ ++ ret = en8855_get_r50ohm_val(dev, "tx_c", &priv->calibration_data[2]); ++ if (ret) ++ return ret; ++ ++ ret = en8855_get_r50ohm_val(dev, "tx_d", &priv->calibration_data[3]); ++ if (ret) ++ return ret; ++ ++ phydev->priv = priv; ++ ++ return 0; ++} ++ ++static int an8855_get_downshift(struct phy_device *phydev, u8 *data) ++{ ++ int val; ++ ++ val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14); ++ if (val < 0) ++ return val; ++ ++ *data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT : ++ DOWNSHIFT_DEV_DISABLE; ++ ++ return 0; ++} ++ ++static int an8855_set_downshift(struct phy_device *phydev, u8 cnt) ++{ ++ u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0; ++ ++ return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, ++ AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT, ++ ds); ++} ++ ++static int an8855_config_init(struct phy_device *phydev) ++{ ++ struct air_an8855_priv *priv = phydev->priv; ++ int ret; ++ ++ /* Enable HW auto downshift */ ++ ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT); ++ if (ret) ++ return ret; ++ ++ /* Apply calibration values, if needed. ++ * AN8855_PHY_FLAGS_EN_CALIBRATION signal this. ++ */ ++ if (priv && phydev->dev_flags & AN8855_PHY_FLAGS_EN_CALIBRATION) { ++ u8 *calibration_data = priv->calibration_data; ++ ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_AB, ++ AN8855_PHY_R50OHM_RSEL_TX_A | AN8855_PHY_R50OHM_RSEL_TX_B, ++ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A, calibration_data[0]) | ++ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B, calibration_data[1])); ++ if (ret) ++ return ret; ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_CD, ++ AN8855_PHY_R50OHM_RSEL_TX_C | AN8855_PHY_R50OHM_RSEL_TX_D, ++ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C, calibration_data[2]) | ++ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D, calibration_data[3])); ++ if (ret) ++ return ret; ++ } ++ ++ /* Apply values to reduce signal noise */ ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE, ++ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE, 0x4) | ++ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE, 0x4)); ++ if (ret) ++ return ret; ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL, ++ AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A | ++ AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C); ++ if (ret) ++ return ret; ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0, ++ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1)); ++ if (ret) ++ return ret; ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1, ++ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1)); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int an8855_get_tunable(struct phy_device *phydev, ++ struct ethtool_tunable *tuna, void *data) ++{ ++ switch (tuna->id) { ++ case ETHTOOL_PHY_DOWNSHIFT: ++ return an8855_get_downshift(phydev, data); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++static int an8855_set_tunable(struct phy_device *phydev, ++ struct ethtool_tunable *tuna, const void *data) ++{ ++ switch (tuna->id) { ++ case ETHTOOL_PHY_DOWNSHIFT: ++ return an8855_set_downshift(phydev, *(const u8 *)data); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++static int an8855_read_page(struct phy_device *phydev) ++{ ++ return __phy_read(phydev, AN8855_PHY_SELECT_PAGE); ++} ++ ++static int an8855_write_page(struct phy_device *phydev, int page) ++{ ++ return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page); ++} ++ ++static struct phy_driver an8855_driver[] = { ++{ ++ PHY_ID_MATCH_EXACT(AN8855_PHY_ID), ++ .name = "Airoha AN8855 internal PHY", ++ /* PHY_GBIT_FEATURES */ ++ .flags = PHY_IS_INTERNAL, ++ .probe = an8855_probe, ++ .config_init = an8855_config_init, ++ .soft_reset = genphy_soft_reset, ++ .get_tunable = an8855_get_tunable, ++ .set_tunable = an8855_set_tunable, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .read_page = an8855_read_page, ++ .write_page = an8855_write_page, ++}, }; ++ ++module_phy_driver(an8855_driver); ++ ++static struct mdio_device_id __maybe_unused an8855_tbl[] = { ++ { PHY_ID_MATCH_EXACT(AN8855_PHY_ID) }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, an8855_tbl); ++ ++MODULE_DESCRIPTION("Airoha AN8855 PHY driver"); ++MODULE_AUTHOR("Christian Marangi "); ++MODULE_LICENSE("GPL"); +diff --git a/target/linux/mediatek/filogic/config-6.6 b/target/linux/mediatek/filogic/config-6.6 +index 85e7367f41cfe5..aa2d74be4b4364 100644 +--- a/target/linux/mediatek/filogic/config-6.6 ++++ b/target/linux/mediatek/filogic/config-6.6 +@@ -1,5 +1,6 @@ + CONFIG_64BIT=y + # CONFIG_AHCI_MTK is not set ++CONFIG_AIR_AN8855_PHY=y + CONFIG_AIROHA_EN8801SC_PHY=y + CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y + CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +@@ -291,6 +292,7 @@ CONFIG_NEED_DMA_MAP_STATE=y + CONFIG_NEED_SG_DMA_LENGTH=y + CONFIG_NET_DEVLINK=y + CONFIG_NET_DSA=y ++CONFIG_NET_DSA_AN8855=y + CONFIG_NET_DSA_MT7530=y + CONFIG_NET_DSA_MT7530_MDIO=y + CONFIG_NET_DSA_MT7530_MMIO=y +diff --git a/target/linux/mediatek/mt7622/config-6.6 b/target/linux/mediatek/mt7622/config-6.6 +index ec3be8df9aa574..b18fc848a27fa3 100644 +--- a/target/linux/mediatek/mt7622/config-6.6 ++++ b/target/linux/mediatek/mt7622/config-6.6 +@@ -1,5 +1,6 @@ + CONFIG_64BIT=y + # CONFIG_AHCI_MTK is not set ++# CONFIG_AIR_AN8855_PHY is not set + # CONFIG_AIROHA_EN8801SC_PHY is not set + CONFIG_AQUANTIA_PHY=y + CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +@@ -294,6 +295,7 @@ CONFIG_NEED_DMA_MAP_STATE=y + CONFIG_NEED_SG_DMA_LENGTH=y + CONFIG_NET_DEVLINK=y + CONFIG_NET_DSA=y ++# CONFIG_NET_DSA_AN8855 is not set + CONFIG_NET_DSA_MT7530=y + CONFIG_NET_DSA_MT7530_MDIO=y + # CONFIG_NET_DSA_MT7530_MMIO is not set +diff --git a/target/linux/mediatek/mt7623/config-6.6 b/target/linux/mediatek/mt7623/config-6.6 +index 6bc92a09dce30e..ce9f817a62a353 100644 +--- a/target/linux/mediatek/mt7623/config-6.6 ++++ b/target/linux/mediatek/mt7623/config-6.6 +@@ -1,4 +1,5 @@ + # CONFIG_AIO is not set ++# CONFIG_AIR_AN8855_PHY is not set + # CONFIG_AIROHA_EN8801SC_PHY is not set + CONFIG_ALIGNMENT_TRAP=y + CONFIG_ARCH_32BIT_OFF_T=y +@@ -410,6 +411,7 @@ CONFIG_NEED_SRCU_NMI_SAFE=y + CONFIG_NEON=y + CONFIG_NET_DEVLINK=y + CONFIG_NET_DSA=y ++# CONFIG_NET_DSA_AN8855 is not set + CONFIG_NET_DSA_MT7530=y + CONFIG_NET_DSA_MT7530_MDIO=y + # CONFIG_NET_DSA_MT7530_MMIO is not set +diff --git a/target/linux/mediatek/mt7629/config-6.6 b/target/linux/mediatek/mt7629/config-6.6 +index 9f57bda3e9e7a7..21c1862e679a35 100644 +--- a/target/linux/mediatek/mt7629/config-6.6 ++++ b/target/linux/mediatek/mt7629/config-6.6 +@@ -1,3 +1,4 @@ ++# CONFIG_AIR_AN8855_PHY is not set + # CONFIG_AIROHA_EN8801SC_PHY is not set + CONFIG_ALIGNMENT_TRAP=y + CONFIG_ARCH_32BIT_OFF_T=y +@@ -216,6 +217,7 @@ CONFIG_NETFILTER=y + CONFIG_NETFILTER_BPF_LINK=y + CONFIG_NET_DEVLINK=y + CONFIG_NET_DSA=y ++# CONFIG_NET_DSA_AN8855 is not set + CONFIG_NET_DSA_MT7530=y + CONFIG_NET_DSA_MT7530_MDIO=y + # CONFIG_NET_DSA_MT7530_MMIO is not set +diff --git a/target/linux/mediatek/patches-6.6/737-net-dsa-add-Airoha-AN8855.patch b/target/linux/mediatek/patches-6.6/737-net-dsa-add-Airoha-AN8855.patch +new file mode 100644 +index 00000000000000..fcfe61997856cb +--- /dev/null ++++ b/target/linux/mediatek/patches-6.6/737-net-dsa-add-Airoha-AN8855.patch +@@ -0,0 +1,197 @@ ++From: Christian Marangi ++To: Christian Marangi , ++ Andrew Lunn , ++ Florian Fainelli , ++ Vladimir Oltean , ++ "David S. Miller" , ++ Eric Dumazet , ++ Jakub Kicinski , Paolo Abeni , ++ Rob Herring , ++ Krzysztof Kozlowski , ++ Conor Dooley , ++ Heiner Kallweit , ++ Russell King , ++ Matthias Brugger , ++ AngeloGioacchino Del Regno ++ , ++ linux-arm-kernel@lists.infradead.org, ++ linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, ++ devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ++ upstream@airoha.com ++Subject: [net-next PATCH v4 0/3] net: dsa: Add Airoha AN8855 support ++Date: Fri, 8 Nov 2024 14:24:13 +0100 [thread overview] ++Message-ID: <20241108132511.18801-1-ansuelsmth@gmail.com> (raw) ++ ++This small series add the initial support for the Airoha AN8855 Switch. ++ ++It's a 5 port Gigabit Switch with SGMII/HSGMII upstream port. ++ ++This is starting to get in the wild and there are already some router ++having this switch chip. ++ ++It's conceptually similar to mediatek switch but register and bits ++are different. And there is that massive Hell that is the PCS ++configuration. ++Saddly for that part we have absolutely NO documentation currently. ++ ++There is this special thing where PHY needs to be calibrated with values ++from the switch efuse. (the thing have a whole cpu timer and MCU) ++ ++Changes v4: ++- Set regmap readable_table static (mute compilation warning) ++- Add support for port_bridge flags (LEARNING, FLOOD) ++- Reset fdb struct in fdb_dump ++- Drop support_asym_pause in port_enable ++- Add define for get_phy_flags ++- Fix bug for port not inititially part of a bridge ++ (in an8855_setup the port matrix was always cleared but ++ the CPU port was never initially added) ++- Disable learning and flood for user port by default ++- Set CPU port to flood and learning by default ++- Correctly AND force duplex and flow control in an8855_phylink_mac_link_up ++- Drop RGMII from pcs_config ++- Check ret in "Disable AN if not in autoneg" ++- Use devm_mutex_init ++- Fix typo for AN8855_PORT_CHECK_MODE ++- Better define AN8855_STP_LISTENING = AN8855_STP_BLOCKING ++- Fix typo in AN8855_PHY_EN_DOWN_SHIFT ++- Use paged helper for PHY ++- Skip calibration in config_init if priv not defined ++Changes v3: ++- Out of RFC ++- Switch PHY code to select_page API ++- Better describe masks and bits in PHY driver for ADC register ++- Drop raw values and use define for mii read/write ++- Switch to absolute PHY address ++- Replace raw values with mask and bits for pcs_config ++- Fix typo for ext-surge property name ++- Drop support for relocating Switch base PHY address on the bus ++Changes v2: ++- Drop mutex guard patch ++- Drop guard usage in DSA driver ++- Use __mdiobus_write/read ++- Check return condition and return errors for mii read/write ++- Fix wrong logic for EEE ++- Fix link_down (don't force link down with autoneg) ++- Fix forcing speed on sgmii autoneg ++- Better document link speed for sgmii reg ++- Use standard define for sgmii reg ++- Imlement nvmem support to expose switch EFUSE ++- Rework PHY calibration with the use of NVMEM producer/consumer ++- Update DT with new NVMEM property ++- Move aneg validation for 2500-basex in pcs_config ++- Move r50Ohm table and function to PHY driver ++ ++Christian Marangi (3): ++ dt-bindings: net: dsa: Add Airoha AN8855 Gigabit Switch documentation ++ net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver ++ net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY ++ ++ .../bindings/net/dsa/airoha,an8855.yaml | 242 ++ ++ MAINTAINERS | 11 + ++ drivers/net/dsa/Kconfig | 9 + ++ drivers/net/dsa/Makefile | 1 + ++ drivers/net/dsa/an8855.c | 2138 +++++++++++++++++ ++ drivers/net/dsa/an8855.h | 638 +++++ ++ drivers/net/phy/Kconfig | 5 + ++ drivers/net/phy/Makefile | 1 + ++ drivers/net/phy/air_an8855.c | 268 +++ ++ 9 files changed, 3313 insertions(+) ++ create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855.yaml ++ create mode 100644 drivers/net/dsa/an8855.c ++ create mode 100644 drivers/net/dsa/an8855.h ++ create mode 100644 drivers/net/phy/air_an8855.c ++ ++-- ++2.45.2 ++ ++--- a/drivers/net/dsa/Kconfig +++++ b/drivers/net/dsa/Kconfig ++@@ -24,6 +24,15 @@ config NET_DSA_LOOP ++ This enables support for a fake mock-up switch chip which ++ exercises the DSA APIs. ++ +++ +++config NET_DSA_AN8855 +++ tristate "Airoha AN8855 Ethernet switch support" +++ depends on NET_DSA +++ select NET_DSA_TAG_MTK +++ help +++ This enables support for the Airoha AN8855 Ethernet switch +++ chip. +++ ++ source "drivers/net/dsa/hirschmann/Kconfig" ++ ++ config NET_DSA_LANTIQ_GSWIP ++--- a/drivers/net/dsa/Makefile +++++ b/drivers/net/dsa/Makefile ++@@ -5,6 +5,7 @@ obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o ++ ifdef CONFIG_NET_DSA_LOOP ++ obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdinfo.o ++ endif +++obj-$(CONFIG_NET_DSA_AN8855) += an8855.o ++ obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o ++ obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o ++ obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o ++--- a/drivers/net/phy/Kconfig +++++ b/drivers/net/phy/Kconfig ++@@ -147,6 +147,11 @@ config AIROHA_EN8801SC_PHY ++ help ++ Currently supports the Airoha EN8801SC PHY. ++ +++config AIR_AN8855_PHY +++ tristate "Airoha AN8855 Internal Gigabit PHY" +++ help +++ Currently supports the internal Airoha AN8855 Switch PHY. +++ ++ config AIR_EN8811H_PHY ++ tristate "Airoha EN8811H 2.5 Gigabit PHY" ++ help ++--- a/drivers/net/phy/Makefile +++++ b/drivers/net/phy/Makefile ++@@ -50,6 +50,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) ++ obj-$(CONFIG_ADIN_PHY) += adin.o ++ obj-$(CONFIG_ADIN1100_PHY) += adin1100.o ++ obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o +++obj-$(CONFIG_AIR_AN8855_PHY) += air_an8855.o ++ obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o ++ obj-$(CONFIG_AMD_PHY) += amd.o ++ obj-$(CONFIG_AQUANTIA_PHY) += aquantia/ ++--- a/include/net/dsa.h +++++ b/include/net/dsa.h ++@@ -1356,6 +1356,7 @@ static inline void dsa_tag_generic_flow_ ++ ++ void dsa_unregister_switch(struct dsa_switch *ds); ++ int dsa_register_switch(struct dsa_switch *ds); +++int devm_dsa_register_switch(struct device *dev, struct dsa_switch *ds); ++ void dsa_switch_shutdown(struct dsa_switch *ds); ++ struct dsa_switch *dsa_switch_find(int tree_index, int sw_index); ++ void dsa_flush_workqueue(void); ++--- a/net/dsa/dsa.c +++++ b/net/dsa/dsa.c ++@@ -1560,6 +1560,25 @@ int dsa_register_switch(struct dsa_switc ++ } ++ EXPORT_SYMBOL_GPL(dsa_register_switch); ++ +++static void devm_dsa_unregister_switch(void *data) +++{ +++ struct dsa_switch *ds = data; +++ +++ dsa_unregister_switch(ds); +++} +++ +++int devm_dsa_register_switch(struct device *dev, struct dsa_switch *ds) +++{ +++ int err; +++ +++ err = dsa_register_switch(ds); +++ if (err) +++ return err; +++ +++ return devm_add_action_or_reset(dev, devm_dsa_unregister_switch, ds); +++} +++EXPORT_SYMBOL_GPL(devm_dsa_register_switch); +++ ++ static void dsa_switch_remove(struct dsa_switch *ds) ++ { ++ struct dsa_switch_tree *dst = ds->dst; diff --git a/devices/mediatek_filogic/patches/F35SQA001G.patch b/devices/mediatek_filogic/patches/F35SQA001G.patch new file mode 100644 index 000000000000..29d7db843cd5 --- /dev/null +++ b/devices/mediatek_filogic/patches/F35SQA001G.patch @@ -0,0 +1,63 @@ +From 2d813c84eb52371ee7222c502b85867c8891aac5 Mon Sep 17 00:00:00 2001 +From: Bohdan Chubuk +Date: Mon, 11 Nov 2024 02:04:29 +0200 +Subject: [PATCH] generic: 6.6: mtd: spinand: add support for FORESEE + F35SQA001G + +Add support for FORESEE F35SQA001G SPI NAND. + +Similar to F35SQA002G, but differs in capacity. +Datasheet: + - https://cdn.ozdisan.com/ETicaret_Dosya/704795_871495.pdf + +Tested on Xiaomi AX3000T flashed with OpenWRT. + +Signed-off-by: Bohdan Chubuk +--- + ...d-add-support-for-FORESEE-F35SQA001G.patch | 37 +++++++++++++++++++ + 1 file changed, 37 insertions(+) + create mode 100644 target/linux/generic/pending-6.6/495-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch + +diff --git a/target/linux/generic/pending-6.6/495-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch b/target/linux/generic/pending-6.6/495-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch +new file mode 100644 +index 0000000000000..8cf20332be348 +--- /dev/null ++++ b/target/linux/generic/pending-6.6/495-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch +@@ -0,0 +1,37 @@ ++From b763f9c21084aa01825e21759beeb357eea16a7f Mon Sep 17 00:00:00 2001 ++From: Bohdan Chubuk ++Date: Sun, 10 Nov 2024 22:47:08 +0200 ++Subject: [PATCH] mtd: spinand: add support for FORESEE F35SQA001G ++ ++Add support for FORESEE F35SQA001G SPI NAND. ++ ++Similar to F35SQA002G, but differs in capacity. ++Datasheet: ++ - https://cdn.ozdisan.com/ETicaret_Dosya/704795_871495.pdf ++ ++Tested on Xiaomi AX3000T flashed with OpenWRT. ++ ++Signed-off-by: Bohdan Chubuk ++--- ++ drivers/mtd/nand/spi/foresee.c | 10 ++++++++++ ++ 1 file changed, 10 insertions(+) ++ ++--- a/drivers/mtd/nand/spi/foresee.c +++++ b/drivers/mtd/nand/spi/foresee.c ++@@ -81,6 +81,16 @@ static const struct spinand_info foresee ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&f35sqa002g_ooblayout, ++ f35sqa002g_ecc_get_status)), +++ SPINAND_INFO("F35SQA001G", +++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71, 0x71), +++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), +++ NAND_ECCREQ(1, 512), +++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, +++ &write_cache_variants, +++ &update_cache_variants), +++ SPINAND_HAS_QE_BIT, +++ SPINAND_ECCINFO(&f35sqa002g_ooblayout, +++ f35sqa002g_ecc_get_status)), ++ }; ++ ++ static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = { diff --git a/devices/mediatek_filogic/patches/Remove-ACK-when-TXS-is-lost.patch b/devices/mediatek_filogic/patches/Remove-ACK-when-TXS-is-lost.patch new file mode 100644 index 000000000000..93f0fc539c7f --- /dev/null +++ b/devices/mediatek_filogic/patches/Remove-ACK-when-TXS-is-lost.patch @@ -0,0 +1,43 @@ +From 09255a2b23bc65dc0629ef4688146c1b93bcf73a Mon Sep 17 00:00:00 2001 +From: developer +Date: Wed, 16 Oct 2024 08:47:21 +0800 +Subject: [PATCH] Remove ACK when TXS is lost. + +Change-Id: I3a8a3aee48a0d735932b07e804bc3592d724fcd8 +Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/9758591 +--- + ...6-do-not-report-ACK-when-TXS-is-lost.patch | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + create mode 100644 package/kernel/mt76/patches/0025-mtk-mt76-do-not-report-ACK-when-TXS-is-lost.patch + +diff --git a/package/kernel/mt76/patches/0025-mtk-mt76-do-not-report-ACK-when-TXS-is-lost.patch b/package/kernel/mt76/patches/0025-mtk-mt76-do-not-report-ACK-when-TXS-is-lost.patch +new file mode 100644 +index 0000000000..281ba99193 +--- /dev/null ++++ b/package/kernel/mt76/patches/0025-mtk-mt76-do-not-report-ACK-when-TXS-is-lost.patch +@@ -0,0 +1,22 @@ ++From 4efdf548d28d3afbc367e2cbe365107db1869690 Mon Sep 17 00:00:00 2001 ++From: Peter Chiu ++Date: Wed, 16 Oct 2024 08:41:49 +0800 ++Subject: [PATCH] mtk: mt76: do not report ACK when TXS is lost ++ ++Signed-off-by: Shayne Chen ++--- ++ tx.c | 3 ++- ++ 1 file changed, 2 insertions(+), 1 deletion(-) ++ ++--- a/tx.c +++++ b/tx.c ++@@ -100,7 +100,8 @@ __mt76_tx_status_skb_done(struct mt76_de ++ return; ++ ++ /* Tx status can be unreliable. if it fails, mark the frame as ACKed */ ++- if (flags & MT_TX_CB_TXS_FAILED) { +++ if ((flags & MT_TX_CB_TXS_FAILED) && +++ (dev->drv->drv_flags & MT_DRV_SW_RX_AIRTIME)) { /* Only CE chips do so */ ++ info->status.rates[0].count = 0; ++ info->status.rates[0].idx = -1; ++ info->flags |= IEEE80211_TX_STAT_ACK; +-- +2.47.0 + diff --git a/devices/mediatek_filogic/patches/Winbond-NMBM-fix.patch b/devices/mediatek_filogic/patches/Winbond-NMBM-fix.patch new file mode 100644 index 000000000000..b8bb00e8da47 --- /dev/null +++ b/devices/mediatek_filogic/patches/Winbond-NMBM-fix.patch @@ -0,0 +1,33 @@ +From 0560802d2f5c2bb4346551950e806f77944cf419 Mon Sep 17 00:00:00 2001 +From: Mikhail Zhilkin +Date: Sun, 17 Nov 2024 16:30:31 +0000 +Subject: [PATCH] kernel: quick fix for nmbm with Winbond W25N01KV + +Fixes: https://github.com/openwrt/openwrt/issues/16972 + +Signed-off-by: Mikhail Zhilkin +--- + target/linux/generic/files/drivers/mtd/nand/mtk_bmt_nmbm.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/target/linux/generic/files/drivers/mtd/nand/mtk_bmt_nmbm.c b/target/linux/generic/files/drivers/mtd/nand/mtk_bmt_nmbm.c +index a896e49ec04751..6ec9b388076dea 100644 +--- a/target/linux/generic/files/drivers/mtd/nand/mtk_bmt_nmbm.c ++++ b/target/linux/generic/files/drivers/mtd/nand/mtk_bmt_nmbm.c +@@ -2197,10 +2197,15 @@ static int nmbm_attach(struct nmbm_instance *ni) + return -EINVAL; + } + ++ nlog_info(ni, "ni->signature.spare_size: %u [0x%02x]\n", ++ ni->signature.spare_size, ni->signature.spare_size); ++ nlog_info(ni, "bmtd.mtd->oobsize: %u [0x%02x]\n", ++ bmtd.mtd->oobsize, bmtd.mtd->oobsize); ++ + if (ni->signature.nand_size != bmtd.total_blks << bmtd.blk_shift || + ni->signature.block_size != bmtd.blk_size || + ni->signature.page_size != bmtd.pg_size || +- ni->signature.spare_size != bmtd.mtd->oobsize) { ++ ni->signature.spare_size > bmtd.mtd->oobsize) { + nlog_err(ni, "NMBM configuration mismatch\n"); + return -EINVAL; + } diff --git a/devices/mediatek_mt7622/.config b/devices/mediatek_mt7622/.config index e833088f3724..33cfb9d64900 100644 --- a/devices/mediatek_mt7622/.config +++ b/devices/mediatek_mt7622/.config @@ -1,9 +1,9 @@ CONFIG_TARGET_mediatek=y CONFIG_TARGET_mediatek_mt7622=y +CONFIG_TARGET_DEVICE_mediatek_mt7622_DEVICE_dlink_eagle-pro-ai-m32-a1=n +CONFIG_TARGET_DEVICE_mediatek_mt7622_DEVICE_dlink_eagle-pro-ai-r32-a1=n +CONFIG_TARGET_DEVICE_mediatek_mt7622_DEVICE_elecom_wrc-x3200gst3=n + CONFIG_TARGET_MULTI_PROFILE=y -CONFIG_TARGET_DEVICE_mediatek_mt7622_DEVICE_xiaomi_redmi-router-ax6s=y -CONFIG_TARGET_DEVICE_mediatek_mt7622_DEVICE_linksys_e8450=y -CONFIG_TARGET_DEVICE_mediatek_mt7622_DEVICE_linksys_e8450-ubi=y -CONFIG_TARGET_DEVICE_mediatek_mt7622_DEVICE_ruijie_rg-ew3200gx-pro=y -CONFIG_TARGET_DEVICE_mediatek_mt7622_DEVICE_bananapi_bpi-r64=y + diff --git a/devices/mvebu_cortexa9/.config b/devices/mvebu_cortexa9/.config index 27f264754c4c..8a90d7d5fadc 100644 --- a/devices/mvebu_cortexa9/.config +++ b/devices/mvebu_cortexa9/.config @@ -2,11 +2,9 @@ CONFIG_TARGET_mvebu=y CONFIG_TARGET_mvebu_cortexa9=y CONFIG_TARGET_MULTI_PROFILE=y -CONFIG_TARGET_DEVICE_mvebu_cortexa9_DEVICE_linksys_wrt1200ac=y -CONFIG_TARGET_DEVICE_mvebu_cortexa9_DEVICE_linksys_wrt1900ac-v2=y -CONFIG_TARGET_DEVICE_mvebu_cortexa9_DEVICE_linksys_wrt1900ac-v1=y -CONFIG_TARGET_DEVICE_mvebu_cortexa9_DEVICE_linksys_wrt3200acm=y -CONFIG_TARGET_DEVICE_mvebu_cortexa9_DEVICE_linksys_wrt1900acs=y -CONFIG_TARGET_DEVICE_mvebu_cortexa9_DEVICE_linksys_wrt32x=y +CONFIG_TARGET_DEVICE_mvebu_cortexa9_DEVICE_plathome_openblocks-ax3-4=n +CONFIG_TARGET_DEVICE_mvebu_cortexa9_DEVICE_synology_ds213j=n +CONFIG_TARGET_DEVICE_mvebu_cortexa9_DEVICE_iij_sa-w2=n + CONFIG_TARGET_ROOTFS_TARGZ=n diff --git a/devices/qualcommax_ipq50xx/diy.sh b/devices/qualcommax_ipq50xx/diy.sh index a3ada488b0d0..b27911a5942a 100644 --- a/devices/qualcommax_ipq50xx/diy.sh +++ b/devices/qualcommax_ipq50xx/diy.sh @@ -4,5 +4,5 @@ shopt -s extglob SHELL_FOLDER=$(dirname $(readlink -f "$0")) -rm -rf target/linux/qualcommax package/boot/uboot-envtools package/firmware package/kernel/qca-* -git_clone_path ipq50xx-pr https://github.com/hzyitc/openwrt-redmi-ax3000 target/linux/qualcommax package/firmware package/kernel/qca-nss-dp package/kernel/qca-ssdk package/boot/uboot-envtools +rm -rf target/linux/qualcommax package/firmware/ath11k-firmware package/firmware/ipq-wifi package/kernel/mac80211 package/kernel/qca-nss-dp package/kernel/qca-ssdk package/boot/uboot-envtools package/network/utils/iwinfo +git_clone_path main https://github.com/georgemoussalem/openwrt-fork target/linux/qualcommax package/firmware/ath11k-firmware package/firmware/ipq-wifi package/kernel/mac80211 package/kernel/qca-nss-dp package/kernel/qca-ssdk package/boot/uboot-envtools package/network/utils/iwinfo diff --git a/devices/qualcommax_ipq50xx/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts b/devices/qualcommax_ipq50xx/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts new file mode 100644 index 000000000000..4ddfa2644acc --- /dev/null +++ b/devices/qualcommax_ipq50xx/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: (GPL-2.0+) + +/dts-v1/; +#include "ipq5018.dtsi" +#include "ipq5018-ess.dtsi" +#include +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "GL.iNet GL-B3000"; + compatible = "glinet,gl-b3000", "qcom,ipq5018"; + interrupt-parent = <&intc>; + + aliases { + ethernet1 = &dp2; + label-mac-device = &dp2; + serial0 = &blsp1_uart1; + led-boot = &led_blue; + led-failsafe = &led_blue; + led-running = &led_blue; + led-upgrade = &led_white; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led_blue: status_blue { + label = "blue:status"; + gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>; + }; + + led_white: status_white { + label = "white:status"; + gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; + }; + }; + + reserved-memory { + tz_appps@4a400000 { + no-map; + reg = <0x0 0x4a400000 0x0 0x400000>; + }; + + q6_mem_regions: q6_mem_regions@4b000000 { + no-map; + reg = <0x0 0x4b000000 0x0 0x3000000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; + +&blsp1_uart1 { + pinctrl-0 = <&blsp0_uart_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&dp1 { + status = "okay"; +}; + +&dp2 { + phy-mode = "sgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&ge_phy { + status = "okay"; +}; + +&mdio0 { + status = "okay"; +}; + +&mdio1 { + pinctrl-0 = <&mdio1_pins>; + pinctrl-names = "default"; + reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + status = "okay"; + + // QCA8337 Phy0 -> WAN + qca8337_0: ethernet-phy@0 { + reg = <0>; + }; + // QCA8337 Phy1 -> LAN1 + qca8337_1: ethernet-phy@1 { + reg = <1>; + }; + // QCA8337 Phy3 -> LAN2 + qca8337_2: ethernet-phy@2 { + reg = <2>; + }; + // QCA8337 Phy2 -> IPQ5018 GE Phy + qca8337_3: ethernet-phy@3 { + reg = <3>; + }; + // QCA8337 switch + switch0: ethernet-switch@17 { + compatible = "qca,qca8337"; + reg = <17>; + #address-cells = <1>; + #size-cells = <0>; + switch_cpu_bmp = <0x40>; /* cpu port bitmap */ + switch_lan_bmp = <0x0c>; /* lan port bitmap */ + switch_wan_bmp = <0x02>; /* wan port bitmap */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + switch0cpu: port@0 { + reg = <0>; + label = "cpu"; + phy-mode = "sgmii"; + ethernet = <&dp2>; + qca,sgmii-enable-pll; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + // QCA8337 Phy0 -> WAN + port@1 { + reg = <1>; + label = "wan"; + phy-handle = <&qca8337_0>; + port_id = <1>; + phy_address = <0>; + }; + + // QCA8337 Phy1 -> LAN1 + port@2 { + reg = <2>; + label = "lan1"; + phy-handle = <&qca8337_1>; + port_id = <2>; + phy_address = <1>; + }; + // QCA8337 Phy3 -> LAN2 + port@3 { + reg = <3>; + label = "lan2"; + phy-handle = <&qca8337_2>; + port_id = <3>; + phy_address = <2>; + }; + }; + }; +}; + +&prng { + status = "okay"; +}; + +&q6v5_wcss { + status = "okay"; + memory-region = <&q6_mem_regions>; + firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt", + "ath11k/IPQ5018/hw1.0/m3_fw.mdt", + "ath11k/qcn6122/hw1.0/m3_fw.mdt"; + + boot-args = + ; + + // IPQ5018 + q6_wcss_pd1: pd-1 { + firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt"; + resets = + <&gcc GCC_WCSSAON_RESET>, + <&gcc GCC_WCSS_BCR>, + <&gcc GCC_CE_BCR>; + reset-names = + "wcss_aon_reset", + "wcss_reset", + "ce_reset"; + clocks = + <&gcc GCC_WCSS_AHB_S_CLK>, + <&gcc GCC_WCSS_ACMT_CLK>, + <&gcc GCC_WCSS_AXI_M_CLK>; + clock-names = + "gcc_wcss_ahb_s_clk", + "gcc_wcss_acmt_clk", + "gcc_wcss_axi_m_clk"; + + interrupts-extended = + <&wcss_smp2p_in 8 0>, + <&wcss_smp2p_in 9 0>, + <&wcss_smp2p_in 12 0>, + <&wcss_smp2p_in 11 0>; + interrupt-names = + "fatal", + "ready", + "spawn-ack", + "stop-ack"; + qcom,smem-states = + <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = + "shutdown", + "stop", + "spawn"; + }; + + // QCN6102 5G + q6_wcss_pd3: pd-3 { + firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt"; + interrupts-extended = + <&wcss_smp2p_in 24 0>, + <&wcss_smp2p_in 25 0>, + <&wcss_smp2p_in 28 0>, + <&wcss_smp2p_in 27 0>; + interrupt-names = + "fatal", + "ready", + "spawn-ack", + "stop-ack"; + qcom,smem-states = + <&wcss_smp2p_out 24>, + <&wcss_smp2p_out 25>, + <&wcss_smp2p_out 26>; + qcom,smem-state-names = + "shutdown", + "stop", + "spawn"; + }; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_pins>; + pinctrl-names = "default"; + status = "okay"; + + nand@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&switch { + switch_mac_mode = ; + status = "okay"; + + qcom,port_phyinfo { + // MAC0 -> GE Phy -> QCA8337 Phy2 + port@0 { + port_id = <1>; + mdiobus = <&mdio0>; + phy_address = <7>; + phy_dac = <0x10 0x10>; + }; + // MAC1 ---SGMII---> QCA8337 SerDes + port@1 { + port_id = <2>; + forced-speed = <1000>; + forced-duplex = <1>; + }; + }; +}; + +&tlmm { + blsp0_uart_pins: uart_pins { + blsp0_uart_rx_tx { + pins = "gpio20", "gpio21"; + function = "blsp0_uart0"; + bias-disable; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio27"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + leds_pins: leds_pins { + mux { + pins = "gpio23", "gpio24"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + mdio1_pins: mdio-state { + mdc-pins { + pins = "gpio36"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + mdio-pins { + pins = "gpio37"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + qpic_pins: qpic-state { + clock-pins { + pins = "gpio9"; + function = "qspi_clk"; + drive-strength = <8>; + bias-disable; + }; + cs-pins { + pins = "gpio8"; + function = "qspi_cs"; + drive-strength = <8>; + bias-disable; + }; + data-pins { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "qspi_data"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&wifi0 { + qcom,rproc = <&q6_wcss_pd1>; + qcom,userpd-subsys-name = "q6v5_wcss_userpd1"; + qcom,ath11k-calibration-variant = "GL-iNet-GL-B3000"; + qcom,ath11k-fw-memory-mode = <2>; + qcom,bdf-addr = <0x4c400000>; + status = "okay"; +}; + +&wifi1 { + qcom,rproc = <&q6_wcss_pd3>; + qcom,userpd-subsys-name = "q6v5_wcss_userpd3"; + qcom,ath11k-calibration-variant = "GL-iNet-GL-B3000"; + qcom,ath11k-fw-memory-mode = <2>; + qcom,bdf-addr = <0x4d100000>; + qcom,m3-dump-addr = <0x4df00000>; + status = "okay"; +}; diff --git a/devices/qualcommax_ipq50xx/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-re-cs-03.dts b/devices/qualcommax_ipq50xx/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-re-cs-03.dts new file mode 100644 index 000000000000..c533f1f9ef45 --- /dev/null +++ b/devices/qualcommax_ipq50xx/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-re-cs-03.dts @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "ipq5018.dtsi" +#include "ipq5018-ess.dtsi" + +#include +#include +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "JDCloud RE-CS-03"; + compatible = "jdcloud,re-cs-03", "qcom,ipq5018"; + interrupt-parent = <&intc>; + + aliases { + sdhc1 = &sdhc_1; + serial0 = &blsp1_uart1; + ethernet0 = "/soc/dp1"; + ethernet1 = "/soc/dp2"; + + led-boot = &led_red; + led-failsafe = &led_red; + led-running = &led_blue; + led-upgrade = &led_green; + }; + + chosen { + stdout-path = "serial0"; + bootargs-append = " swiotlb=1 coherent_pool=2M"; + }; + + reserved-memory { + q6_mem_regions: q6_mem_regions@4B000000 { + no-map; + reg = <0x0 0x4B000000 0x0 0x3900000>; + }; + + q6_code_data: q6_code_data@4B000000 { + no-map; + reg = <0x0 0x4B000000 0x0 01000000>; + }; + + q6_ipq5018_data: q6_ipq5018_data@4C000000 { + no-map; + reg = <0x0 0x4C000000 0x0 0xE00000>; + }; + + m3_dump: m3_dump@4CE00000 { + no-map; + reg = <0x0 0x4CE00000 0x0 0x100000>; + }; + + q6_etr_region: q6_etr_dump@4CF00000 { + no-map; + reg = <0x0 0x4CF00000 0x0 0x100000>; + }; + + q6_caldb_region: q6_caldb_region@4D000000 { + no-map; + reg = <0x0 0x4D000000 0x0 0x200000>; + }; + + q6_qcn6122_data1: q6_qcn6122_data1@4D200000 { + no-map; + reg = <0x0 0x4D200000 0x0 0x1000000>; + }; + + m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E200000 { + no-map; + reg = <0x0 0x4E200000 0x0 0x100000>; + }; + + q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E300000 { + no-map; + reg = <0x0 0x4E300000 0x0 0x100000>; + }; + + q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4E400000 { + no-map; + reg = <0x0 0x4E400000 0x0 0x500000>; + }; + }; + + soc { + ess-instance { + num_devices = <0x2>; + + ess-switch@0x39c00000 { + compatible = "qcom,ess-switch-ipq50xx"; + device_id = <0>; + switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/ + cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/ + + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <7>; + }; + port@1 { + port_id = <2>; + forced-speed = <1000>; + forced-duplex = <1>; + }; + }; + }; + + ess-switch1@1 { + compatible = "qcom,ess-switch-qca83xx"; + device_id = <1>; + switch_access_mode = "mdio"; + mdio-bus = <&mdio1>; + reset_gpio = <&tlmm 39 0>; + switch_cpu_bmp = <0x40>; /* cpu port bitmap */ + switch_lan_bmp = <0x1e>; /* lan port bitmap */ + switch_wan_bmp = <0x0>; /* wan port bitmap */ + + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x00010 0x2613a0 /* PORT6 FORCE MODE*/ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <0>; + }; + port@1 { + port_id = <2>; + phy_address = <1>; + }; + port@2 { + port_id = <3>; + phy_address = <2>; + }; + port@3 { + port_id = <4>; + phy_address = <3>; + }; + }; + }; + }; + + dp1 { + device_type = "network"; + compatible = "qcom,nss-dp"; + clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>; + clock-names = "nss-snoc-gmac-axi-clk"; + qcom,id = <1>; + reg = <0x39C00000 0x10000>; + interrupts = ; + qcom,mactype = <2>; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <7>; + mdio-bus = <&mdio0>; + local-mac-address = [000000000000]; + phy-mode = "sgmii"; + qcom,rx-page-mode = <0>; + }; + + dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>; + clock-names = "nss-snoc-gmac-axi-clk"; + qcom,id = <2>; + reg = <0x39D00000 0x10000>; + interrupts = ; + qcom,mactype = <2>; + local-mac-address = [000000000000]; + phy-mode = "sgmii"; + qcom,rx-page-mode = <0>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led_blue: status_blue { + label = "blue:status"; + gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + }; + + led_green: status_green { + label = "green:status"; + gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>; + }; + + led_red: status_red { + label = "red:status"; + gpio = <&tlmm 33 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&blsp1_uart1 { + status = "ok"; +}; + +&mdio0 { + status = "ok"; + + ethernet-phy@0 { + reg = <7>; + }; +}; + +&mdio1 { + pinctrl-0 = <&mdio1_pins>; + pinctrl-names = "default"; + phy-reset-gpio = <&tlmm 39 0>; + status = "ok"; + + ethernet-phy@0 { + reg = <0>; + }; + + ethernet-phy@1 { + reg = <1>; + }; + + ethernet-phy@2 { + reg = <2>; + }; + + ethernet-phy@3 { + reg = <3>; + }; +}; + +&q6v5_wcss { + compatible = "qcom,ipq5018-q6-mpd"; + firmware = "IPQ5018/q6_fw.mdt"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + reg = <0x0cd00000 0x4040>, + <0x1938000 0x8>, + <0x193d204 0x4>; + reg-names = "qdsp6", + "tcsr-msip", + "tcsr-q6"; + resets = <&gcc GCC_WCSSAON_RESET>, + <&gcc GCC_WCSS_Q6_BCR>; + + reset-names = "wcss_aon_reset", + "wcss_q6_reset"; + + clocks = <&gcc GCC_Q6_AXIS_CLK>, + <&gcc GCC_WCSS_ECAHB_CLK>, + <&gcc GCC_Q6_AXIM_CLK>, + <&gcc GCC_Q6_AXIM2_CLK>, + <&gcc GCC_Q6_AHB_CLK>, + <&gcc GCC_Q6_AHB_S_CLK>, + <&gcc GCC_WCSS_AXI_S_CLK>; + clock-names = "gcc_q6_axis_clk", + "gcc_wcss_ecahb_clk", + "gcc_q6_axim_clk", + "gcc_q6_axim2_clk", + "gcc_q6_ahb_clk", + "gcc_q6_ahb_s_clk", + "gcc_wcss_axi_s_clk"; + + memory-region = <&q6_mem_regions>, <&q6_etr_region>, + <&q6_caldb_region>; + + qcom,rproc = <&q6v5_wcss>; + qcom,bootargs_smem = <507>; + boot-args = <0x1 0x4 0x3 0x0F 0x0 0x0>, + <0x2 0x4 0x2 0x12 0x0 0x0>; + + q6_wcss_pd1: remoteproc_pd1@4ab000 { + compatible = "qcom,ipq5018-wcss-ahb-mpd"; + firmware = "IPQ5018/q6_fw.mdt"; + m3_firmware = "IPQ5018/m3_fw.mdt"; + + reg = <0x4ab000 0x20>; + reg-names = "rmb"; + + interrupts-extended = <&wcss_smp2p_in 8 0>, + <&wcss_smp2p_in 9 0>, + <&wcss_smp2p_in 12 0>, + <&wcss_smp2p_in 11 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + resets = <&gcc GCC_WCSSAON_RESET>, + <&gcc GCC_WCSS_BCR>, + <&gcc GCC_CE_BCR>; + reset-names = "wcss_aon_reset", + "wcss_reset", + "ce_reset"; + + clocks = <&gcc GCC_WCSS_AHB_S_CLK>, + <&gcc GCC_WCSS_ACMT_CLK>, + <&gcc GCC_WCSS_AXI_M_CLK>; + clock-names = "gcc_wcss_ahb_s_clk", + "gcc_wcss_acmt_clk", + "gcc_wcss_axi_m_clk"; + + // qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>; + + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + memory-region = <&q6_ipq5018_data>, <&m3_dump>, + <&q6_etr_region>, <&q6_caldb_region>; + }; + + q6_wcss_pd2: remoteproc_pd2 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + firmware = "IPQ5018/q6_fw.mdt"; + m3_firmware = "qcn6122/m3_fw.mdt"; + + interrupts-extended = <&wcss_smp2p_in 16 0>, + <&wcss_smp2p_in 17 0>, + <&wcss_smp2p_in 20 0>, + <&wcss_smp2p_in 19 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 16>, + <&wcss_smp2p_out 17>, + <&wcss_smp2p_out 18>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>, + <&q6_qcn6122_etr_1>, <&q6_qcn6122_caldb_1>; + }; +}; + +&sdhc_1 { + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + status = "ok"; +}; + +&tlmm { + button_pins: button_pins { + mux { + pins = "gpio25", "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + leds_pins: leds_pins { + mux { + pins = "gpio31", "gpio32", "gpio33"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + }; + + mdio1_pins: mdio_pinmux { + mux_0 { + pins = "gpio36"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + mux_1 { + pins = "gpio37"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + emmc_pins: emmc_pins { + emmc_clk { + pins = "gpio9"; + function = "sdc1_clk"; + drive-strength = <8>; + bias-disable; + }; + + emmc_cmd { + pins = "gpio8"; + function = "sdc1_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + emmc_data { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "sdc1_data"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&wifi0 { + qcom,multipd_arch; + qcom,userpd-subsys-name = "q6v5_wcss_userpd1"; + qcom,rproc = <&q6_wcss_pd1>; + qcom,board_id = <0x24>; + qcom,bdf-addr = <0x0 0x4C000000 0x4C000000 0x0 0x0>; + qcom,caldb-addr = <0x0 0x4D000000 0 0 0>; + mem-region = <&q6_ipq5018_data>; + qcom,caldb-size = <0x200000>; + status = "ok"; +}; + +&wifi1 { + qcom,multipd_arch; + qcom,userpd-subsys-name = "q6v5_wcss_userpd2"; + qcom,rproc = <&q6_wcss_pd2>; + qcom,tgt-mem-mode = <1>; + qcom,board_id = <0x60>; + qcom,bdf-addr = <0x0 0x4D200000 0x4CF00000 0x0 0x0>; + qcom,caldb-addr = <0x0 0x4E400000 0 0 0>; + mem-region = <&q6_qcn6122_data1>; + qcom,caldb-size = <0x500000>; + status = "ok"; +}; diff --git a/devices/qualcommax_ipq50xx/patches/diy.patch b/devices/qualcommax_ipq50xx/patches/diy.patch new file mode 100644 index 000000000000..68237719f176 --- /dev/null +++ b/devices/qualcommax_ipq50xx/patches/diy.patch @@ -0,0 +1,111 @@ +--- a/target/linux/qualcommax/image/ipq50xx.mk ++++ b/target/linux/qualcommax/image/ipq50xx.mk +@@ -1,3 +1,28 @@ ++define Device/glinet_gl-b3000 ++ $(call Device/FitImage) ++ $(call Device/UbiFit) ++ SOC := ipq5018 ++ DEVICE_VENDOR := GL.iNET ++ DEVICE_MODEL := GL-B3000 ++ BLOCKSIZE := 128k ++ PAGESIZE := 2048 ++ DEVICE_DTS_CONFIG := config@mp03.5-c1 ++ DEVICE_PACKAGES := ath11k-firmware-qcn6122 ipq-wifi-gl-b3000 ++endef ++TARGET_DEVICES += glinet_gl-b3000 ++ ++define Device/jdcloud_re-cs-03 ++ $(call Device/FitImage) ++ $(call Device/EmmcImage) ++ SOC := ipq5018 ++ BLOCKSIZE := 64k ++ KERNEL_SIZE := 6144k ++ DEVICE_VENDOR := JDCloud ++ DEVICE_MODEL := AX3000 ++ DEVICE_DTS_CONFIG := config@mp03.5-c2 ++endef ++TARGET_DEVICES += jdcloud_re-cs-03 ++ + define Device/linksys_mx_atlas6 + $(call Device/FitImageLzma) + DEVICE_VENDOR := Linksys + +--- a/target/linux/qualcommax/ipq50xx/base-files/etc/board.d/02_network ++++ b/target/linux/qualcommax/ipq50xx/base-files/etc/board.d/02_network +@@ -7,6 +7,10 @@ ipq50xx_setup_interfaces() + { + local board="$1" + case $board in ++ glinet,gl-b3000) ++ ucidef_set_interfaces_lan_wan "lan1 lan2" "wan" ++ ;; ++ jdcloud,re-cs-03|\ + linksys,mx2000|\ + linksys,mx5500) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan" + +--- a/target/linux/qualcommax/ipq50xx/base-files/lib/upgrade/platform.sh ++++ b/target/linux/qualcommax/ipq50xx/base-files/lib/upgrade/platform.sh +@@ -10,6 +10,14 @@ platform_check_image() { + + platform_do_upgrade() { + case "$(board_name)" in ++ glinet,gl-b3000) ++ nand_do_upgrade "$1" ++ ;; ++ jdcloud,re-cs-03) ++ CI_KERNPART="0:HLOS" ++ CI_ROOTPART="rootfs" ++ emmc_do_upgrade "$1" ++ ;; + linksys,mx2000|\ + linksys,mx5500) + platform_do_upgrade_linksys "$1" +@@ -19,3 +27,12 @@ platform_do_upgrade() { + ;; + esac + } ++ ++platform_copy_config() { ++ case "$(board_name)" in ++ jdcloud,re-cs-03) ++ emmc_copy_config ++ ;; ++ esac ++ return 0; ++} + +--- a/target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata ++++ b/target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata +@@ -9,6 +9,15 @@ board=$(board_name) + case "$FIRMWARE" in + "ath11k/IPQ5018/hw1.0/cal-ahb-c000000.wifi.bin") + case "$board" in ++ glinet,gl-b3000) ++ caldata_extract "0:ART" 0x1000 0x20000 ++ addr=$(mtd_get_mac_binary "0:ART" 0x6) ++ ath11k_patch_mac $(macaddr_add $addr 3) 0 ++ ath11k_set_macflag ++ ;; ++ jdcloud,re-cs-03) ++ caldata_extract_mmc "0:ART" 0x1000 0x20000 ++ ;; + linksys,mx2000|\ + linksys,mx5500) + caldata_extract "0:ART" 0x1000 0x20000 +@@ -21,6 +30,15 @@ case "$FIRMWARE" in + ;; + "ath11k/QCN6122/hw1.0/cal-ahb-b00a040.wifi1.bin") + case "$board" in ++ glinet,gl-b3000) ++ caldata_extract "0:ART" 0x26800 0x20000 ++ addr=$(mtd_get_mac_binary "0:ART" 0x6) ++ ath11k_patch_mac $(macaddr_add $addr 4) 0 ++ ath11k_set_macflag ++ ;; ++ jdcloud,re-cs-03) ++ caldata_extract_mmc "0:ART" 0x26800 0x20000 ++ ;; + linksys,mx2000) + caldata_extract "0:ART" 0x26800 0x20000 + label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) diff --git a/devices/qualcommax_ipq60xx/.config b/devices/qualcommax_ipq60xx/.config index 7c2f3b7ded62..6a41fb820168 100644 --- a/devices/qualcommax_ipq60xx/.config +++ b/devices/qualcommax_ipq60xx/.config @@ -2,4 +2,5 @@ CONFIG_TARGET_qualcommax=y CONFIG_TARGET_qualcommax_ipq60xx=y CONFIG_TARGET_MULTI_PROFILE=y CONFIG_TARGET_ALL_PROFILES=y +CONFIG_TARGET_DEVICE_qualcommax_ipq60xx_DEVICE_8devices_mango-dvk=n diff --git a/devices/qualcommax_ipq60xx/diy.sh b/devices/qualcommax_ipq60xx/diy.sh index e17a05a8850c..5da49f038f79 100644 --- a/devices/qualcommax_ipq60xx/diy.sh +++ b/devices/qualcommax_ipq60xx/diy.sh @@ -10,4 +10,4 @@ git_clone_path openwrt-24.10 https://github.com/LiBwrt-op/openwrt-6.x package/fi wget -N https://github.com/openwrt/openwrt/raw/refs/heads/openwrt-24.10/target/linux/qualcommax/ipq60xx/target.mk -P target/linux/qualcommax/ipq60xx/ -rm -rf target/linux/qualcommax/patches-6.6/06*-qca-*.patch \ No newline at end of file +rm -rf target/linux/qualcommax/patches-6.6/06*-qca-*.patch diff --git a/devices/qualcommax_ipq807x/.config b/devices/qualcommax_ipq807x/.config index 4f70e547c3b8..689704a185d8 100644 --- a/devices/qualcommax_ipq807x/.config +++ b/devices/qualcommax_ipq807x/.config @@ -1,12 +1,4 @@ CONFIG_TARGET_qualcommax=y CONFIG_TARGET_qualcommax_ipq807x=y CONFIG_TARGET_MULTI_PROFILE=y -CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_redmi_ax6=y -CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_xiaomi_ax3600=y -CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_xiaomi_ax9000=y -CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_qnap_301w=y -CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_zte_mf269=y -CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_zyxel_nbg7815=y -CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_buffalo_wxr-5950ax12=y -CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_cmcc_rm2-6=y -CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_aliyun_ap8220=y +CONFIG_TARGET_DEVICE_qualcommax_ipq807x_DEVICE_asus_rt-ax89x=n diff --git a/devices/qualcommax_ipq807x/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ap8220.dts b/devices/qualcommax_ipq807x/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ap8220.dts index b691d372a694..6ea150a674c6 100644 --- a/devices/qualcommax_ipq807x/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ap8220.dts +++ b/devices/qualcommax_ipq807x/diy/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ap8220.dts @@ -5,7 +5,6 @@ #include "ipq8074.dtsi" #include "ipq8074-ac-cpu.dtsi" #include "ipq8074-ess.dtsi" -#include "ipq8074-nss.dtsi" #include #include @@ -353,4 +352,4 @@ &dp6 { status = "okay"; phy-handle = <&qca8081_28>; -}; +}; \ No newline at end of file diff --git a/devices/qualcommax_ipq807x/patches/ap8220.patch b/devices/qualcommax_ipq807x/patches/ap8220.patch index 69d5b4048028..7de79be2820d 100644 --- a/devices/qualcommax_ipq807x/patches/ap8220.patch +++ b/devices/qualcommax_ipq807x/patches/ap8220.patch @@ -1,16 +1,16 @@ -From 21bbc6fbed2122945184500e4fdefe2598c1a1e5 Mon Sep 17 00:00:00 2001 -From: coolsnowwolf -Date: Wed, 16 Oct 2024 23:10:43 +0800 -Subject: [PATCH] ipq807x: add support for Aliyun AP8220 +--- a/package/boot/uboot-envtools/files/qualcommax_ipq807x ++++ b/package/boot/uboot-envtools/files/qualcommax_ipq807x +@@ -19,7 +19,8 @@ netgear,wax630) + ;; + compex,wpq873|\ + edgecore,eap102|\ +-zyxel,nbg7815) ++zyxel,nbg7815|\ ++aliyun,ap8220) + idx="$(find_mtd_index 0:appsblenv)" + [ -n "$idx" ] && \ + ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000" "1" ---- - target/linux/qualcommax/image/ipq807x.mk | 13 + - .../qualcommax/ipq807x/base-files/etc/board.d/02_network | 3 + - .../base-files/lib/upgrade/platform.sh | 4 + - 4 files changed, 376 insertions(+) - -diff --git a/target/linux/qualcommax/image/ipq807x.mk b/target/linux/qualcommax/image/ipq807x.mk -index 6406d001311f21..05b0ff8c125f16 100644 --- a/target/linux/qualcommax/image/ipq807x.mk +++ b/target/linux/qualcommax/image/ipq807x.mk @@ -33,6 +33,19 @@ define Build/wax6xx-netgear-tar @@ -46,8 +46,18 @@ index 6406d001311f21..05b0ff8c125f16 100644 asus,rt-ax89x) ucidef_set_interfaces_lan_wan "10g-sfp 10g-copper lan1 lan2 lan3 lan4 lan5 lan6 lan7 lan8" "wan" ;; -diff --git a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh -index 4c8a38c261c972..b0c42dde058a5d 100644 +@@ -80,6 +80,10 @@ ipq807x_setup_macs() + local label_mac="" + + case "$board" in ++ aliyun,ap8220) ++ wan_mac=$(cat /dev/mtd12 | head -n 4 | grep "product.mac" | awk -F " " '{print $2}') ++ lan_mac=$(macaddr_add "$wan_mac" 1) ++ ;; + linksys,mx4200v2) + label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) + for i in $(seq 3 5); do + --- a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh +++ b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh @@ -140,6 +140,10 @@ platform_do_upgrade() { diff --git a/devices/ramips_mt7620/.config b/devices/ramips_mt7620/.config index 494169c257a7..5fdc5832d114 100644 --- a/devices/ramips_mt7620/.config +++ b/devices/ramips_mt7620/.config @@ -2,22 +2,81 @@ CONFIG_TARGET_ramips=y CONFIG_TARGET_ramips_mt7620=y CONFIG_TARGET_MULTI_PROFILE=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_glinet_gl-mt300a=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_glinet_gl-mt300n=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_glinet_gl-mt750=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_hiwifi_hc5661=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_hiwifi_hc5761=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_hiwifi_hc5861=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_hiwifi_r33=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_lenovo_newifi-y1=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_lenovo_newifi-y1s=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_xiaomi_miwifi-mini=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_youku_yk-l1=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_youku_yk-l1c=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_xiaomi_miwifi-r3=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_zbtlink_zbt-we826-32m=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_asus_rt-ac51u=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_asus_rt-ac54u=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_asus_rt-ac51u=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_netcore_nw5212=y -CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_youku_x2=y +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_aigale_ai-br100=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_ampedwireless_b1200ex=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_asus_rp-n53=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_buffalo_whr-300hp2=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_buffalo_whr-600d=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_buffalo_wmr-300=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_comfast_cf-wr800n=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_dlink_dch-m225=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_dlink_dir-806a-b1=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_dlink_dir-810l=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_dlink_dwr-116-a1=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_dovado_tiny-ac=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_edimax_br-6208ac-v2=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_edimax_br-6478ac-v2=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_edimax_ew-7476rpc=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_edimax_ew-7478ac=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_edimax_ew-7478apc=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_humax_e2=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_hootoo_ht-tm05=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_iodata_wn-ac1167gr=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_iodata_wn-ac733gr3=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_iptime_a104ns=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_lb-link_bl-w1200=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_linksys_e1700=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_netgear_ex2700=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_netgear_ex3700=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_netgear_ex6120=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_netgear_ex6130=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_netgear_jwnr2010-v5=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_netgear_wn3000rp-v3=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_netgear_wn3100rp-v2=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_nexx_wt3020-4m=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_nexx_wt3020-8m=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_phicomm_k2-v22.4=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_phicomm_k2-v22.5=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_phicomm_k2g=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_phicomm_psg1208=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_phicomm_psg1218b=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_planex_cs-qr10=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_planex_db-wrt01=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_planex_mzk-750dhp=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_planex_mzk-ex300np=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_planex_mzk-ex750np=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_ralink_mt7620a-evb=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_ralink_mt7620a-mt7530-evb=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_ralink_mt7620a-mt7610e-evb=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_ralink_mt7620a-v22sg-evb=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_ravpower_rp-wd03=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_rostelecom_rt-fl-1=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_rostelecom_s1010=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_sitecom_wlr-4100-v1-002=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_snr_cpe-w4n-mt=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_tplink_archer-c20i=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_tplink_archer-c20-v1=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_tplink_archer-c2-v1=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_tplink_archer-c5-v4=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_tplink_archer-c50-v1=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_tplink_archer-mr200=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_tplink_ec220-g5-v2=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_tplink_re200-v1=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_tplink_re210-v1=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_trendnet_tew-810dr=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_trendnet_tha103ac=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_vonets_var11n-300=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_wavlink_wl-wn530hg4=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_wavlink_wl-wn531g3=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_wavlink_wl-wn531g3-a2=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_wavlink_wl-wn535k1=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_wavlink_wl-wn579x3=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_yukai_bocco=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_zbtlink_zbt-cpe102=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_zbtlink_zbt-wa05=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_zbtlink_zbt-we2026=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_zbtlink_zbt-wr8305rt=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_zte_q7=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_zyxel_keenetic-lite-iii-a=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_zyxel_keenetic-omni=n +CONFIG_TARGET_DEVICE_ramips_mt7620_DEVICE_zyxel_keenetic-omni-ii=n diff --git a/devices/ramips_mt7621/.config b/devices/ramips_mt7621/.config index 0787836d4dba..1b89536ae93d 100644 --- a/devices/ramips_mt7621/.config +++ b/devices/ramips_mt7621/.config @@ -2,60 +2,24 @@ CONFIG_TARGET_ramips=y CONFIG_TARGET_ramips_mt7621=y CONFIG_TARGET_MULTI_PROFILE=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaomi_mi-router-cr660x=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaomi_mi-router-3g=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaomi_mi-router-3-pro=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaomi_mi-router-4=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaomi_mi-router-4a-gigabit=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaomi_mi-router-4a-gigabit-v2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaomi_redmi-router-ac2100=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaomi_mi-router-ac2100=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaoyu_xy-c5=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_lenovo_newifi-d1=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_d-team_newifi-d2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_jdcloud_re-sp-01b=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_glinet_gl-mt1300=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_phicomm_k2p=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_phicomm_k2p-32m=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_asus_rt-ac85p=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_netgear_r6220=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_netgear_r6260=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_netgear_r6700-v2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_netgear_r6800=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_netgear_r6850=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_netgear_r6900-v2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_netgear_r7450=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_netgear_wndr3700-v5=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_oraybox_x3a=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_thunder_timecloud=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_ubnt_edgerouter-x-sfp=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_ubnt_edgerouter-x=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_xiaomi_mi-router-3g-v2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_youhua_wr1200js=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_youku_yk-l2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_jcg_y2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_jcg_q20=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_hiwifi_hc5962=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_asus_rt-n56u-b1=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_gehua_ghl-r-001=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_raisecom_msg1500-x-00=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_zte_e8820s=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_zte_e8820v2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_linksys_ea7500-v2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_linksys_ea8100-v1=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_linksys_ea8100-v2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_linksys_ea7300-v1=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_linksys_ea7300-v2=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_linksys_ea6350-v4=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_linksys_e5600=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_jdcloud_luban=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_h3c_tx1800-plus=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_h3c_tx1801-plus=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_h3c_tx1806=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_zbtlink_zbt-wg3526-32m=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_ht-jsh_0211=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_c-life_xg1=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_hatlab_gateboard-one=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_openfi_5pro=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_jdcloud_re-cp-02=y -CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_yuncore_ax820=y +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_dna_valokuitu-plus-ex400=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_elecom_wrc-1167gs2-b=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_elecom_wrc-1750gsv=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_elecom_wrc-1900gst=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_elecom_wrc-2533ghbk-i=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_elecom_wrc-2533ghbk2-t=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_elecom_wrc-2533gs2=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_elecom_wrc-x3200gst3=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_iodata_wn-gx300gr=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_linksys_re6500=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_mediatek_ap-mt7621a-v60=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_ruijie_rg-ew1200g-pro-v1.1=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_storylink_sap-g3200u3=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_tplink_eap235-wall-v1=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_tplink_eap613-v1=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_tplink_eap615-wall-v1=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_tplink_re350-v1=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_tplink_re650-v2=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_tplink_tl-wpa8631p-v3=n +CONFIG_TARGET_DEVICE_ramips_mt7621_DEVICE_winstars_ws-wn583a6=n + diff --git a/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts b/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts deleted file mode 100644 index 1826a9f20c86..000000000000 --- a/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "mt7621.dtsi" - -#include -#include -#include - -/ { - compatible = "jdcloud,re-cp-02", "mediatek,mt7621-soc"; - model = "JDCloud RE-CP-02"; - - aliases { - label-mac-device = &gmac0; - led-boot = &led_status_blue; - led-failsafe = &led_status_red; - led-running = &led_status_green; - led-upgrade = &led_status_blue; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led_status_red: led-0 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - - led_status_blue: led-1 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - - led_status_green: led-2 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - }; - - keys { - compatible = "gpio-keys"; - - wps { - label = "wps"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&gpio 18 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - compatible = "u-boot,env"; - label = "Config"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "Factory"; - reg = <0x50000 0x40000>; - read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - eeprom_factory_0: eeprom@0 { - reg = <0x0 0xe00>; - }; - - macaddr_factory_3fff4: macaddr@3fff4 { - reg = <0x3fff4 0x6>; - }; - - macaddr_factory_3fffa: macaddr@3fffa { - reg = <0x3fffa 0x6>; - }; - }; - }; - - partition@90000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x90000 0xf70000>; - }; - }; - }; -}; - -&state_default { - gpio { - groups = "uart3", "jtag", "wdt"; - function = "gpio"; - }; -}; - -&sdhci { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&pcie1 { - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - nvmem-cells = <&eeprom_factory_0>; - nvmem-cell-names = "eeprom"; - mediatek,disable-radar-background; - }; -}; - -&gmac0 { - nvmem-cells = <&macaddr_factory_3fff4>; - nvmem-cell-names = "mac-address"; -}; - -&gmac1 { - status = "okay"; - label = "wan"; - - nvmem-cells = <&macaddr_factory_3fffa>; - nvmem-cell-names = "mac-address"; -}; - -&switch0 { - ports { - port@1 { - status = "okay"; - label = "lan1"; - }; - - port@2 { - status = "okay"; - label = "lan2"; - }; - - port@3 { - status = "okay"; - label = "lan3"; - }; - }; -}; - -&xhci { - status = "disabled"; -}; diff --git a/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_zte_e8820s.dts b/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_zte_e8820s.dts index 1a35994c36e3..5d8e1cddfd24 100644 --- a/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_zte_e8820s.dts +++ b/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_zte_e8820s.dts @@ -4,17 +4,16 @@ #include #include -#include / { compatible = "zte,e8820s", "mediatek,mt7621-soc"; model = "ZTE E8820S"; aliases { - led-boot = &power_led; - led-failsafe = &system_led; - led-running = &system_led; - led-upgrade = &system_led; + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; label-mac-device = &gmac0; }; @@ -22,61 +21,41 @@ bootargs = "console=ttyS0,115200"; }; - gpio-leds { + leds { compatible = "gpio-leds"; - power_led: led-power { - function = LED_FUNCTION_POWER; - color = ; + led_power: power { + label = "white:power"; gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; - system_led: led-system { - function = LED_FUNCTION_STATUS; - color = ; + led_sys: sys { + label = "white:sys"; gpios = <&gpio 3 GPIO_ACTIVE_LOW>; }; }; - gpio-keys { + keys { compatible = "gpio-keys"; - button-reset { + reset { label = "reset"; - gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,code = ; }; - button-wifi { - label = "wifi"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - button-wps { + wps { label = "wps"; gpios = <&gpio 8 GPIO_ACTIVE_LOW>; linux,code = ; }; - }; -}; -ðphy4 { - /delete-property/ interrupts; -}; - -&gmac0 { - nvmem-cells = <&macaddr_config_12 0>; - nvmem-cell-names = "mac-address"; -}; - -&gmac1 { - status = "okay"; - label = "wan"; - phy-handle = <ðphy4>; - - nvmem-cells = <&macaddr_config_12 0>; - nvmem-cell-names = "mac-address"; + wifi { + label = "wifi"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; &nand { @@ -88,66 +67,36 @@ #size-cells = <1>; partition@0 { - label = "Bootloader"; - reg = <0x0 0x220000>; + label = "u-boot"; + reg = <0x0 0x80000>; read-only; }; partition@80000 { - compatible = "nvmem-cells"; - label = "config"; - reg = <0x220000 0x140000>; + label = "u-boot-env"; + reg = <0x80000 0x80000>; read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_config_12: macaddr@12 { - compatible = "mac-base"; - reg = <0x12 0x6>; - #nvmem-cell-cells = <1>; - }; - }; }; - partition@360000 { - compatible = "nvmem-cells"; + factory: partition@100000 { label = "factory"; - reg = <0x360000 0x140000>; + reg = <0x100000 0x40000>; read-only; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - eeprom_factory_f000: eeprom@f000 { - reg = <0xf000 0x400>; - }; - - eeprom_factory_f800: eeprom@f800 { - reg = <0xf800 0x200>; - }; - }; }; - partition@4a0000 { + partition@140000 { label = "kernel"; - reg = <0x4a0000 0x400000>; + reg = <0x140000 0x400000>; }; - partition@8a0000 { + partition@540000 { label = "ubi"; - reg = <0x8a0000 0x76e0000>; + reg = <0x540000 0x7a40000>; }; }; }; &pcie { - reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>, - <&gpio 4 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -155,8 +104,7 @@ wifi@0,0 { compatible = "pci14c3,7603"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&eeprom_factory_f000>, <&macaddr_config_12 0>; - nvmem-cell-names = "eeprom", "mac-address"; + mediatek,mtd-eeprom = <&factory 0x0000>; ieee80211-freq-limit = <2400000 2500000>; led { @@ -169,17 +117,25 @@ wifi@0,0 { compatible = "pci14c3,7662"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&eeprom_factory_f800>, <&macaddr_config_12 1>; - nvmem-cell-names = "eeprom", "mac-address"; + mediatek,mtd-eeprom = <&factory 0x8000>; ieee80211-freq-limit = <5000000 6000000>; led { - led-active-low; led-sources = <2>; + led-active-low; }; }; }; +&gmac0 { + mtd-mac-address = <&factory 0xe000>; +}; + +&gmac1 { + mtd-mac-address = <&factory 0xe006>; + status = "okay"; +}; + &switch0 { ports { port@0 { @@ -201,12 +157,18 @@ status = "okay"; label = "lan4"; }; + + port@4 { + status = "okay"; + label = "wan"; + mtd-mac-address = <&factory 0xe000>; + }; }; }; &state_default { gpio { - groups = "jtag", "uart2", "uart3", "wdt"; + groups = "i2c", "jtag", "uart2", "uart3", "wdt"; function = "gpio"; }; }; diff --git a/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_zte_e8820v2.dts b/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_zte_e8820v2.dts new file mode 100644 index 000000000000..4665e0d17ea1 --- /dev/null +++ b/devices/ramips_mt7621/diy/target/linux/ramips/dts/mt7621_zte_e8820v2.dts @@ -0,0 +1,165 @@ +/dts-v1/; + +#include "mt7621.dtsi" + +#include +#include + +/ { + compatible = "zte,e8820v2", "mediatek,mt7621-soc"; + model = "ZTE E8820V2"; + + aliases { + led-boot = &led_sys; + led-failsafe = &led_sys; + led-running = &led_sys; + led-upgrade = &led_sys; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led_sys:sys { + label = "e8820v2:white:sys"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + }; + + led_power:power { + label = "e8820v2:white:power"; + gpios = <&gpio 31 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; + }; +}; + + +&pcie { + status = "okay"; +}; + +&pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x0000>; + + led { + led-active-low; + }; + + }; +}; + +&pcie1 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x8000>; + ieee80211-freq-limit = <5000000 6000000>; + + led { + led-sources = <2>; + led-active-low; + }; + + }; +}; + + +&gmac0 { + mtd-mac-address = <&factory 0xe000>; +}; + +&switch0 { + ports { + port@4 { + status = "okay"; + label = "wan"; + mtd-mac-address = <&factory 0xe006>; + }; + + port@0 { + status = "okay"; + label = "lan1"; + }; + + port@1 { + status = "okay"; + label = "lan2"; + }; + + port@2 { + status = "okay"; + label = "lan3"; + }; + + port@3 { + status = "okay"; + label = "lan4"; + }; + }; +}; + +&state_default { + gpio { + groups = "i2c", "uart2", "uart3", "wdt"; + function = "gpio"; + }; +}; \ No newline at end of file diff --git a/devices/ramips_mt7621/patches/02-cr660x.patch b/devices/ramips_mt7621/patches/02-cr660x.patch index 2fc70c75a3c4..8665f2480fd3 100644 --- a/devices/ramips_mt7621/patches/02-cr660x.patch +++ b/devices/ramips_mt7621/patches/02-cr660x.patch @@ -41,14 +41,14 @@ + PAGESIZE := 2048 + KERNEL_SIZE := 4096k + UBINIZE_OPTS := -E 5 -+ IMAGE_SIZE := 130304k ++ IMAGE_SIZE := 129280k + IMAGES += factory.bin + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \ + check-size + DEVICE_VENDOR := ZTE + DEVICE_MODEL := E8820S -+ DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 uboot-envtools ++ DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 kmod-usb-ledtrig-usbport +endef +TARGET_DEVICES += zte_e8820s + diff --git a/devices/ramips_mt7621/patches/zte_e8820s.patch b/devices/ramips_mt7621/patches/zte_e8820s.patch index ca2c1299b5ef..6ee19811f947 100644 --- a/devices/ramips_mt7621/patches/zte_e8820s.patch +++ b/devices/ramips_mt7621/patches/zte_e8820s.patch @@ -1,191 +1,3 @@ -diff --git a/target/linux/ramips/dts/mt7621_zte_e8820v2.dts b/target/linux/ramips/dts/mt7621_zte_e8820v2.dts -new file mode 100644 -index 000000000000..5a0012441509 ---- /dev/null -+++ b/target/linux/ramips/dts/mt7621_zte_e8820v2.dts -@@ -0,0 +1,181 @@ -+#include "mt7621.dtsi" -+ -+#include -+#include -+ -+/ { -+ compatible = "zte,e8820v2", "mediatek,mt7621-soc"; -+ model = "ZTE E8820V2"; -+ -+ aliases { -+ led-boot = &led_sys; -+ led-failsafe = &led_sys; -+ led-running = &led_sys; -+ led-upgrade = &led_sys; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led_sys: sys { -+ label = "white:sys"; -+ gpios = <&gpio 29 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led_power: power { -+ label = "white:power"; -+ gpios = <&gpio 31 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ keys { -+ compatible = "gpio-keys"; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio 18 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ -+ wps { -+ label = "wps"; -+ gpios = <&gpio 24 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ }; -+}; -+ -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ broken-flash-reset; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x0 0x30000>; -+ read-only; -+ }; -+ -+ partition@30000 { -+ label = "u-boot-env"; -+ reg = <0x30000 0x10000>; -+ read-only; -+ }; -+ -+ factory: partition@40000 { -+ label = "factory"; -+ reg = <0x40000 0x10000>; -+ read-only; -+ }; -+ -+ partition@50000 { -+ compatible = "denx,uimage"; -+ label = "firmware"; -+ reg = <0x50000 0xfb0000>; -+ }; -+ }; -+ }; -+}; -+ -+&pcie { -+ status = "okay"; -+ reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>, -+ <&gpio 4 GPIO_ACTIVE_LOW>; -+}; -+ -+&pcie0 { -+ wifi@0,0 { -+ compatible = "mediatek,mt76"; -+ reg = <0x0000 0 0 0 0>; -+ mediatek,mtd-eeprom = <&factory 0x0000>; -+ nvmem-cells = <&macaddr_factory_e000>; -+ nvmem-cell-names = "mac-address"; -+ -+ led { -+ led-active-low; -+ }; -+ }; -+}; -+ -+&pcie1 { -+ wifi@0,0 { -+ compatible = "mediatek,mt76"; -+ reg = <0x0000 0 0 0 0>; -+ mediatek,mtd-eeprom = <&factory 0x8000>; -+ nvmem-cells = <&macaddr_factory_e006>; -+ nvmem-cell-names = "mac-address"; -+ -+ ieee80211-freq-limit = <5000000 6000000>; -+ led { -+ led-sources = <2>; -+ led-active-low; -+ }; -+ }; -+}; -+ -+ -+&gmac0 { -+ nvmem-cells = <&macaddr_factory_e000>; -+ nvmem-cell-names = "mac-address"; -+}; -+ -+&switch0 { -+ ports { -+ port@0 { -+ status = "okay"; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ status = "okay"; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ status = "okay"; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ status = "okay"; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ status = "okay"; -+ label = "wan"; -+ nvmem-cells = <&macaddr_factory_e006>; -+ nvmem-cell-names = "mac-address"; -+ }; -+ }; -+}; -+ -+&state_default { -+ gpio { -+ groups = "i2c", "uart2", "uart3", "wdt"; -+ function = "gpio"; -+ }; -+}; -+ -+&factory { -+ compatible = "nvmem-cells"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_factory_e000: macaddr@e000 { -+ reg = <0xe000 0x6>; -+ }; -+ -+ macaddr_factory_e006: macaddr@e006 { -+ reg = <0xe006 0x6>; -+ }; -+}; - diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds b/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds index aad2e32b36210..a6a4707fc295d 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds diff --git a/devices/ramips_mt76x8/.config b/devices/ramips_mt76x8/.config index 2e60ecd0b9e6..a7e5848c9d54 100644 --- a/devices/ramips_mt76x8/.config +++ b/devices/ramips_mt76x8/.config @@ -2,18 +2,73 @@ CONFIG_TARGET_ramips=y CONFIG_TARGET_ramips_mt76x8=y CONFIG_TARGET_MULTI_PROFILE=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_asus_rt-ac1200=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_asus_rt-ac1200-v2=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_glinet_gl-mt300n-v2=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_glinet_microuter-n300=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_hiwifi_hc5661a=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_hiwifi_hc5761a=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_hiwifi_hc5861b=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_hiwifi_hc5611=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_xiaomi_miwifi-3a=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_netgear_r6120=y -CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_xiaomi_miwifi-nano=y +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_7links_wlr-1230=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_7links_wlr-1240=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_alfa-network_awusfree1=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_asus_rt-n10p-v3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_asus_rt-n11p-b1=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_asus_rt-n12-vp-b1=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_buffalo_wcr-1166ds=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_comfast_cf-wr617ac=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_comfast_cf-wr758ac-v1=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_comfast_cf-wr758ac-v2=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_cudy_wr1000=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_dlink_dap-1325-a1=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_duzun_dm06=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_elecom_wrc-1167fs=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_glinet_vixmini=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_iptime_a3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_iptime_a604m=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_jotale_js76x8-8m=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_mediatek_mt7628an-eval-board=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_mercury_mac1200r-v2=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_motorola_mwr03=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_netgear_r6020=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_netgear_r6080=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_rakwireless_rak633=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_totolink_a3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_totolink_lr1200=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_archer-c20-v4=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_archer-c20-v5=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_archer-c50-v3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_archer-c50-v4=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_archer-c50-v6=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_archer-mr200-v5=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_re200-v2=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_re200-v3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_re200-v4=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_re205-v3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_re220-v2=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_re305-v1=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_re305-v3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_re365-v1=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-mr3020-v3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-mr3420-v5=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-mr6400-v4=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-mr6400-v5=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wa801nd-v5=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wr802n-v4=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wr840n-v4=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wr840n-v5=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wr841n-v13=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wr841n-v14=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wr842n-v5=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wr850n-v2=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wr902ac-v3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_tplink_tl-wr902ac-v4=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_vocore_vocore2-lite=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_wavlink_wl-wn531a3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_wavlink_wl-wn570ha1=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_wavlink_wl-wn575a3=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_wavlink_wl-wn576a2=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_wavlink_wl-wn577a2=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_wavlink_wl-wn578a2=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_yuncore_cpe200=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_yuncore_m300=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_zbtlink_zbt-we1226=n +CONFIG_TARGET_DEVICE_ramips_mt76x8_DEVICE_zbtlink_zbt-we2426-b=n + + -CONFIG_PACKAGE_kmod-fs-ntfs3-oot=n diff --git a/devices/rockchip_armv8/.config b/devices/rockchip_armv8/.config index 5e7ce8719eb0..9caab4f5fa56 100644 --- a/devices/rockchip_armv8/.config +++ b/devices/rockchip_armv8/.config @@ -4,8 +4,13 @@ CONFIG_TARGET_rockchip_armv8=y CONFIG_TARGET_MULTI_PROFILE=y CONFIG_TARGET_ALL_PROFILES=y +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_mmbox_anas3035=n +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_armsom_sige5=n +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_radxa_rock-pi-4a=n + CONFIG_TARGET_KERNEL_PARTSIZE=32 CONFIG_PACKAGE_kmod-pcie_mhi=m CONFIG_PACKAGE_kmod-ath12k=n + diff --git a/devices/rockchip_armv8/diy.sh b/devices/rockchip_armv8/diy.sh index 9d7e5ddeacda..cc5e6d8b21fe 100644 --- a/devices/rockchip_armv8/diy.sh +++ b/devices/rockchip_armv8/diy.sh @@ -5,18 +5,20 @@ SHELL_FOLDER=$(dirname $(readlink -f "$0")) #bash $SHELL_FOLDER/../common/kernel_6.6.sh -rm -rf package/boot target/linux/rockchip linux/generic +rm -rf package/boot target/linux/rockchip target/linux/generic -git_clone_path master https://github.com/coolsnowwolf/lede package/boot target/linux/rockchip linux/generic +git_clone_path master https://github.com/coolsnowwolf/lede target/linux/rockchip target/linux/generic package/boot wget -N https://github.com/istoreos/istoreos/raw/istoreos-22.03/target/linux/rockchip/patches-5.10/305-r2s-pwm-fan.patch -P target/linux/rockchip/patches-6.6/ wget -N https://github.com/openwrt/openwrt/raw/refs/heads/openwrt-24.10/target/linux/rockchip/Makefile -P target/linux/rockchip/ wget -N https://github.com/coolsnowwolf/lede/raw/master/include/kernel-6.6 -P include/ +wget -N https://github.com/coolsnowwolf/lede/raw/refs/heads/master/include/trusted-firmware-a.mk -P include/ + sed -i "/KernelPackage,ptp/d" package/kernel/linux/modules/other.mk -rm -rf package/boot/uboot-rk35xx/patches/001-cmd-fix_source.patch +wget -N https://patch-diff.githubusercontent.com/raw/openwrt/openwrt/pull/16414.patch -P devices/common/patches/ #sed -i -e "s/configs\/dilusense-\(.*-.*_defconfig\)/configs\/\1/" \ # -e "s/configs\/sharevdi-\(.*-.*_defconfig\)/configs\/\1/" \ diff --git a/devices/rockchip_armv8/patches/fix.patch b/devices/rockchip_armv8/patches/fix.patch deleted file mode 100644 index 3f3efaf94ad5..000000000000 --- a/devices/rockchip_armv8/patches/fix.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/package/boot/uboot-rk35xx/Makefile -+++ b/package/boot/uboot-rk35xx/Makefile -@@ -14,8 +14,8 @@ PKG_SOURCE_PROTO:=git - PKG_SOURCE_URL:=https://github.com/radxa/u-boot - - PKG_SOURCE_DATE:=2024-10-29 --PKG_SOURCE_VERSION:=27398f1e19628407fabb279034653d23c9369f12 --PKG_MIRROR_HASH:=d0469f6c1f0d561d1495844fff2b50bc42af16fa4e33f5f42f092770a2bb4967 -+PKG_SOURCE_VERSION:=00ac933690e0bf6b2adc2ab507e50bff05327729 -+PKG_MIRROR_HASH:= - - include $(INCLUDE_DIR)/u-boot.mk - include $(INCLUDE_DIR)/package.mk