Hardware texture sampler

[jbush001]

http://graphics.stanford.edu/papers/texture_prefetch/texture_prefetch_comp.pdf

Expose through memory mapped registers.
Could also investigate specialized instructions.

Probably requires #63

[jbush001]

See https://github.com/m-labs/milkymist/tree/master/cores/tmu2 for real implementation of a texture sampler that uses a design similar to the paper cited above.

[jbush001]

This will need a way to read texture data from memory. A few options:

• This could load from the L2 cache by sending request in the interface (perhaps via l1_l2_interface). A potential problem with this approach is that it would pollute the cache, as the texture working set is often much larger than the cache.
• It could have a separate AXI interface. This would require an internal AXI arbiter (there is a test arbiter in the fpga directory, but it is not very general and only has two ports).
• Create a separate, simpler internal bus interface that both the L2 cache and the texture samplers talk to, then a bridge between that and the AXI bus. This would simplify Add support for alternative bus interfaces #152. Milkymist uses a somewhat similar approach with the internal "FML" bus protocol.