From 293049f43d5169df2dd0110f9906ac4316d7289d Mon Sep 17 00:00:00 2001 From: Ian McIntyre Date: Sun, 21 May 2023 11:47:25 -0400 Subject: [PATCH 1/5] Skip code generation for fields marked "reserved" The goal is to correct the documentation generated for the CCM CCGR fields. Based on how the combiner works, these fields are generally considered combine-able across all chips. So when we generate code for the 1061 CCM, we're permitted to use the fields from the 1011 CCM. The 1011 CCM has many more reserved gates than the 1062 CCM, so those end up leaking into the documentation. This commit drops the fields that are marked "reserved" in their human-readable description. It's not clear why these are provided in the SVD. By dropping these reserved fields, we change the "field plurality" heuristic that the combiner uses to understand equivalent fieldsets. Notice how the CCGR documentation corrects itself in the 1061 CCM. We also generate less code, and less chance for humans to poke at reserved registers. I'm not a fan of hard-coding this behavior into the SVD importer. But it was easy to prototype. I might consider a transform that does this across all document-able items. I didn't use a 'contains("reserved")' predicate for the field skip. There are some fields that are documented with "all other values are reserved," so that larger-reaching predicate would incorrectly remove those fields. I briefly scanned these changes to make sure removals seemed appropriate. --- CHANGELOG.md | 5 + raltool/src/svd2ir.rs | 6 + src/blocks/imxrt1011/ccm.rs | 416 --------------- src/blocks/imxrt1011/dcdc.rs | 8 - src/blocks/imxrt1011/ocotp.rs | 8 - src/blocks/imxrt1011/usbphy.rs | 584 --------------------- src/blocks/imxrt1015/ccm.rs | 384 +------------- src/blocks/imxrt1015/ocotp.rs | 8 - src/blocks/imxrt1021/can.rs | 512 ------------------ src/blocks/imxrt1021/ccm.rs | 234 ++------- src/blocks/imxrt1021/ocotp.rs | 8 - src/blocks/imxrt1051/ccm.rs | 118 ++--- src/blocks/imxrt1051/ccm_analog.rs | 32 -- src/blocks/imxrt1051/dcdc.rs | 8 - src/blocks/imxrt1051/usbphy.rs | 584 --------------------- src/blocks/imxrt1052/pxp.rs | 528 ------------------- src/blocks/imxrt1061/ccm.rs | 118 ++--- src/blocks/imxrt1061/ccm_analog.rs | 32 -- src/blocks/imxrt1176_cm4/flexram.rs | 136 ----- src/blocks/imxrt1176_cm4/usbphy.rs | 148 +++--- src/blocks/imxrt1176_cm4/xecc_flexspi.rs | 40 -- src/blocks/imxrt1176_cm7/system_control.rs | 13 - 22 files changed, 236 insertions(+), 3694 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 4c4d575eeb2c..9bab8dff2c5b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -48,6 +48,11 @@ Exclude the interrupt vector table when we're building for a target with an operating system. This ensures you can build imxrt-ral in different contexts, like build scripts. +Drop all register fields that are documented as "reserved" (first word of the +description, all lowercase). Dropping these fields changes the combiner's +approach for combining fieldsets, enabling correct documentation for non- +reserved fields. + ## [0.5.0] 2022-12-27 Add support for NXP's i.MX RT 1176 dual-core MCUs. An `"imxrt1176_cm7"` feature diff --git a/raltool/src/svd2ir.rs b/raltool/src/svd2ir.rs index 993df3df8607..2d76d548c902 100644 --- a/raltool/src/svd2ir.rs +++ b/raltool/src/svd2ir.rs @@ -201,6 +201,12 @@ pub fn convert_peripheral(ir: &mut IR, p: &svd::Peripheral) -> anyhow::Result<() warn!("unsupported derived_from in fieldset"); } + if let Some(desc) = &f.description { + if desc.to_lowercase().starts_with("reserved") { + continue; + } + } + let mut field = Field { name: f.name.clone(), description: f.description.clone(), diff --git a/src/blocks/imxrt1011/ccm.rs b/src/blocks/imxrt1011/ccm.rs index 0536c2d4c1c6..cd551aae9195 100644 --- a/src/blocks/imxrt1011/ccm.rs +++ b/src/blocks/imxrt1011/ccm.rs @@ -2059,38 +2059,6 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "trace clock (trace_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; @@ -2150,38 +2118,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG2 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG3 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG4 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "pit clocks (pit_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; @@ -2190,14 +2126,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "adc1 clock (adc1_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; @@ -2206,14 +2134,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "gpt1 bus clock (gpt_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; @@ -2273,14 +2193,6 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "iomuxc_snvs clock (iomuxc_snvs_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; @@ -2305,14 +2217,6 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "OCOTP_CTRL clock (iim_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; @@ -2321,38 +2225,6 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "xbar1 clock (xbar1_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; @@ -2361,73 +2233,9 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG12 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG13 { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG14 { - pub const offset: u32 = 28; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Clock Gating Register 3"] pub mod CCGR3 { - #[doc = "Reserved"] - pub mod CG0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG2 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG3 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "aoi1 clock (aoi1_clk_enable)"] pub mod CG4 { pub const offset: u32 = 8; @@ -2436,22 +2244,6 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG6 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "ewm clocks (ewm_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; @@ -2476,38 +2268,6 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG11 { - pub const offset: u32 = 22; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG12 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG13 { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The OCRAM clock cannot be turned off when the CM cache is running on this device."] pub mod CG14 { pub const offset: u32 = 28; @@ -2551,14 +2311,6 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG3 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sim_m7 clock (sim_m7_clk_enable)"] pub mod CG4 { pub const offset: u32 = 8; @@ -2567,14 +2319,6 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sim_m clocks (sim_m_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; @@ -2599,54 +2343,6 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG11 { - pub const offset: u32 = 22; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG12 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG13 { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG14 { - pub const offset: u32 = 28; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "dma_ps clocks (dma_ps_clk_enable)"] pub mod CG15 { pub const offset: u32 = 30; @@ -2706,14 +2402,6 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG6 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "spdif clock (spdif_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; @@ -2722,14 +2410,6 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sai1 clock (sai1_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; @@ -2738,14 +2418,6 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sai3 clock (sai3_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; @@ -2762,14 +2434,6 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG13 { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "snvs_hp clock (snvs_hp_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; @@ -2797,22 +2461,6 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG2 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "dcdc clocks (dcdc_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; @@ -2821,14 +2469,6 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG4 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared"] pub mod CG5 { pub const offset: u32 = 10; @@ -2845,30 +2485,6 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sim_per clock (sim_per_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; @@ -2885,38 +2501,6 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG12 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG13 { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG14 { - pub const offset: u32 = 28; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Module Enable Overide Register"] pub mod CMEOR { diff --git a/src/blocks/imxrt1011/dcdc.rs b/src/blocks/imxrt1011/dcdc.rs index 435fa8bdfe37..d6bb72e61a4a 100644 --- a/src/blocks/imxrt1011/dcdc.rs +++ b/src/blocks/imxrt1011/dcdc.rs @@ -333,14 +333,6 @@ pub mod REG3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod MISC_DISABLEFET_LOGIC { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Disable stepping for the output VDD_SOC of DCDC"] pub mod DISABLE_STEP { pub const offset: u32 = 30; diff --git a/src/blocks/imxrt1011/ocotp.rs b/src/blocks/imxrt1011/ocotp.rs index 12e4d50b2a6b..63061b942eea 100644 --- a/src/blocks/imxrt1011/ocotp.rs +++ b/src/blocks/imxrt1011/ocotp.rs @@ -707,14 +707,6 @@ pub mod LOCK { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod FIELD_RETURN { - pub const offset: u32 = 28; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)"] pub mod CFG0 { diff --git a/src/blocks/imxrt1011/usbphy.rs b/src/blocks/imxrt1011/usbphy.rs index 87e42b05b030..3f003dcf7be9 100644 --- a/src/blocks/imxrt1011/usbphy.rs +++ b/src/blocks/imxrt1011/usbphy.rs @@ -60,14 +60,6 @@ pub struct RegisterBlock { } #[doc = "USB PHY Power-Down Register"] pub mod PWD { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; @@ -92,14 +84,6 @@ pub mod PWD { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; @@ -132,25 +116,9 @@ pub mod PWD { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Power-Down Register"] pub mod PWD_SET { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; @@ -175,14 +143,6 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; @@ -215,25 +175,9 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Power-Down Register"] pub mod PWD_CLR { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; @@ -258,14 +202,6 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; @@ -298,25 +234,9 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Power-Down Register"] pub mod PWD_TOG { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; @@ -341,14 +261,6 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; @@ -381,14 +293,6 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Transmitter Control Register"] pub mod TX { @@ -400,14 +304,6 @@ pub mod TX { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"] pub mod TXCAL45DN { pub const offset: u32 = 8; @@ -416,14 +312,6 @@ pub mod TX { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"] pub mod TXCAL45DP { pub const offset: u32 = 16; @@ -432,14 +320,6 @@ pub mod TX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"] pub mod USBPHY_TX_EDGECTRL { pub const offset: u32 = 26; @@ -448,14 +328,6 @@ pub mod TX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD5 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Transmitter Control Register"] pub mod TX_SET { @@ -467,14 +339,6 @@ pub mod TX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"] pub mod TXCAL45DN { pub const offset: u32 = 8; @@ -483,14 +347,6 @@ pub mod TX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"] pub mod TXCAL45DP { pub const offset: u32 = 16; @@ -499,14 +355,6 @@ pub mod TX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"] pub mod USBPHY_TX_EDGECTRL { pub const offset: u32 = 26; @@ -515,14 +363,6 @@ pub mod TX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD5 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Transmitter Control Register"] pub mod TX_CLR { @@ -534,14 +374,6 @@ pub mod TX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"] pub mod TXCAL45DN { pub const offset: u32 = 8; @@ -550,14 +382,6 @@ pub mod TX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"] pub mod TXCAL45DP { pub const offset: u32 = 16; @@ -566,14 +390,6 @@ pub mod TX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"] pub mod USBPHY_TX_EDGECTRL { pub const offset: u32 = 26; @@ -582,14 +398,6 @@ pub mod TX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD5 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Transmitter Control Register"] pub mod TX_TOG { @@ -601,14 +409,6 @@ pub mod TX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"] pub mod TXCAL45DN { pub const offset: u32 = 8; @@ -617,14 +417,6 @@ pub mod TX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"] pub mod TXCAL45DP { pub const offset: u32 = 16; @@ -633,14 +425,6 @@ pub mod TX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"] pub mod USBPHY_TX_EDGECTRL { pub const offset: u32 = 26; @@ -649,14 +433,6 @@ pub mod TX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD5 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Receiver Control Register"] pub mod RX { @@ -668,14 +444,6 @@ pub mod RX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; @@ -684,14 +452,6 @@ pub mod RX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; @@ -700,14 +460,6 @@ pub mod RX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Receiver Control Register"] pub mod RX_SET { @@ -719,14 +471,6 @@ pub mod RX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; @@ -735,14 +479,6 @@ pub mod RX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; @@ -751,14 +487,6 @@ pub mod RX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Receiver Control Register"] pub mod RX_CLR { @@ -770,14 +498,6 @@ pub mod RX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; @@ -786,14 +506,6 @@ pub mod RX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; @@ -802,14 +514,6 @@ pub mod RX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Receiver Control Register"] pub mod RX_TOG { @@ -821,14 +525,6 @@ pub mod RX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; @@ -837,14 +533,6 @@ pub mod RX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; @@ -853,14 +541,6 @@ pub mod RX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY General Control Register"] pub mod CTRL { @@ -1064,14 +744,6 @@ pub mod CTRL { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 25; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"] pub mod OTG_ID_VALUE { pub const offset: u32 = 27; @@ -1315,14 +987,6 @@ pub mod CTRL_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 25; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"] pub mod OTG_ID_VALUE { pub const offset: u32 = 27; @@ -1566,14 +1230,6 @@ pub mod CTRL_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 25; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"] pub mod OTG_ID_VALUE { pub const offset: u32 = 27; @@ -1817,14 +1473,6 @@ pub mod CTRL_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 25; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"] pub mod OTG_ID_VALUE { pub const offset: u32 = 27; @@ -1868,14 +1516,6 @@ pub mod CTRL_TOG { } #[doc = "USB PHY Status Register"] pub mod STATUS { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that the device has disconnected while in high-speed host mode."] pub mod HOSTDISCONDETECT_STATUS { pub const offset: u32 = 3; @@ -1884,14 +1524,6 @@ pub mod STATUS { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that the device has been connected on the USB_DP and USB_DM lines."] pub mod DEVPLUGIN_STATUS { pub const offset: u32 = 6; @@ -1900,14 +1532,6 @@ pub mod STATUS { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the results of ID pin on MiniAB plug"] pub mod OTGID_STATUS { pub const offset: u32 = 8; @@ -1916,14 +1540,6 @@ pub mod STATUS { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 9; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that the host is sending a wake-up after suspend and has triggered an interrupt."] pub mod RESUME_STATUS { pub const offset: u32 = 10; @@ -1932,14 +1548,6 @@ pub mod STATUS { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD4 { - pub const offset: u32 = 11; - pub const mask: u32 = 0x001f_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Debug Register"] pub mod DEBUG { @@ -1975,14 +1583,6 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; @@ -1999,14 +1599,6 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; @@ -2015,14 +1607,6 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; @@ -2055,14 +1639,6 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Debug Register"] pub mod DEBUG_SET { @@ -2098,14 +1674,6 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; @@ -2122,14 +1690,6 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; @@ -2138,14 +1698,6 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; @@ -2178,14 +1730,6 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Debug Register"] pub mod DEBUG_CLR { @@ -2221,14 +1765,6 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; @@ -2245,14 +1781,6 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; @@ -2261,14 +1789,6 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; @@ -2301,14 +1821,6 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Debug Register"] pub mod DEBUG_TOG { @@ -2344,14 +1856,6 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; @@ -2368,14 +1872,6 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; @@ -2384,14 +1880,6 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; @@ -2424,14 +1912,6 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI Debug Status Register 0"] pub mod DEBUG0_STATUS { @@ -2462,14 +1942,6 @@ pub mod DEBUG0_STATUS { } #[doc = "UTMI Debug Status Register 1"] pub mod DEBUG1 { - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"] pub mod ENTAILADJVD { pub const offset: u32 = 13; @@ -2478,25 +1950,9 @@ pub mod DEBUG1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x0001_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI Debug Status Register 1"] pub mod DEBUG1_SET { - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"] pub mod ENTAILADJVD { pub const offset: u32 = 13; @@ -2505,25 +1961,9 @@ pub mod DEBUG1_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x0001_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI Debug Status Register 1"] pub mod DEBUG1_CLR { - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"] pub mod ENTAILADJVD { pub const offset: u32 = 13; @@ -2532,25 +1972,9 @@ pub mod DEBUG1_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x0001_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI Debug Status Register 1"] pub mod DEBUG1_TOG { - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"] pub mod ENTAILADJVD { pub const offset: u32 = 13; @@ -2559,14 +1983,6 @@ pub mod DEBUG1_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x0001_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI RTL Version"] pub mod VERSION { diff --git a/src/blocks/imxrt1015/ccm.rs b/src/blocks/imxrt1015/ccm.rs index 24656f45a4fa..394bc6bdc72a 100644 --- a/src/blocks/imxrt1015/ccm.rs +++ b/src/blocks/imxrt1015/ccm.rs @@ -2265,14 +2265,6 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "flexspi_exsc clock (flexspi_exsc_clk_enable)"] - pub mod CG3 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sim_m_clk_r_clk_enable"] pub mod CG4 { pub const offset: u32 = 8; @@ -2297,38 +2289,6 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "trace clock (trace_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; @@ -2388,38 +2348,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG2 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG3 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG4 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "pit clocks (pit_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; @@ -2428,14 +2356,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "adc1 clock (adc1_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; @@ -2444,14 +2364,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "gpt1 bus clock (gpt_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; @@ -2511,14 +2423,6 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "iomuxc_snvs clock (iomuxc_snvs_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; @@ -2543,14 +2447,6 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "OCOTP_CTRL clock (iim_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; @@ -2559,38 +2455,6 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "xbar1 clock (xbar1_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; @@ -2599,7 +2463,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "xbar2 clock (xbar2_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -2607,7 +2471,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "gpio3 clock (gpio3_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -2615,57 +2479,9 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG14 { - pub const offset: u32 = 28; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Clock Gating Register 3"] pub mod CCGR3 { - #[doc = "Reserved"] - pub mod CG0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG2 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG3 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "aoi1 clock (aoi1_clk_enable)"] pub mod CG4 { pub const offset: u32 = 8; @@ -2674,22 +2490,6 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG6 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "ewm clocks (ewm_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; @@ -2714,38 +2514,6 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG11 { - pub const offset: u32 = 22; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG12 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG13 { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The OCRAM clock cannot be turned off when the CM cache is running on this device."] pub mod CG14 { pub const offset: u32 = 28; @@ -2789,7 +2557,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "bee clock(bee_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -2805,14 +2573,6 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sim_m clocks (sim_m_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; @@ -2837,31 +2597,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG11 { - pub const offset: u32 = 22; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] + #[doc = "enc1 clocks (enc1_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -2869,30 +2605,6 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG13 { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG14 { - pub const offset: u32 = 28; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "dma_ps clocks (dma_ps_clk_enable)"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Clock Gating Register 5"] pub mod CCGR5 { @@ -2944,7 +2656,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "aipstz4 clocks (aips_tz4_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; pub const mask: u32 = 0x03 << offset; @@ -2960,14 +2672,6 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sai1 clock (sai1_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; @@ -2976,7 +2680,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "sai2 clock (sai2_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3000,14 +2704,6 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG13 { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "snvs_hp clock (snvs_hp_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; @@ -3035,22 +2731,6 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG2 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "dcdc clocks (dcdc_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; @@ -3059,14 +2739,6 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG4 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared"] pub mod CG5 { pub const offset: u32 = 10; @@ -3083,23 +2755,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] + #[doc = "aips_tz3 clock (aips_tz3_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -3123,15 +2779,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG12 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] + #[doc = "timer1 clocks (timer1_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3139,22 +2787,6 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG14 { - pub const offset: u32 = 28; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Module Enable Overide Register"] pub mod CMEOR { diff --git a/src/blocks/imxrt1015/ocotp.rs b/src/blocks/imxrt1015/ocotp.rs index e2ac69492800..b33f47dc02a4 100644 --- a/src/blocks/imxrt1015/ocotp.rs +++ b/src/blocks/imxrt1015/ocotp.rs @@ -707,14 +707,6 @@ pub mod LOCK { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod FIELD_RETURN { - pub const offset: u32 = 28; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)"] pub mod CFG0 { diff --git a/src/blocks/imxrt1021/can.rs b/src/blocks/imxrt1021/can.rs index cda988119423..bdfd758ce386 100644 --- a/src/blocks/imxrt1021/can.rs +++ b/src/blocks/imxrt1021/can.rs @@ -1677,14 +1677,6 @@ pub mod CS0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 0 ID Register"] pub mod ID0 { @@ -1825,14 +1817,6 @@ pub mod CS1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 1 ID Register"] pub mod ID1 { @@ -1973,14 +1957,6 @@ pub mod CS2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 2 ID Register"] pub mod ID2 { @@ -2121,14 +2097,6 @@ pub mod CS3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 3 ID Register"] pub mod ID3 { @@ -2269,14 +2237,6 @@ pub mod CS4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 4 ID Register"] pub mod ID4 { @@ -2417,14 +2377,6 @@ pub mod CS5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 5 ID Register"] pub mod ID5 { @@ -2565,14 +2517,6 @@ pub mod CS6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 6 ID Register"] pub mod ID6 { @@ -2713,14 +2657,6 @@ pub mod CS7 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 7 ID Register"] pub mod ID7 { @@ -2861,14 +2797,6 @@ pub mod CS8 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 8 ID Register"] pub mod ID8 { @@ -3009,14 +2937,6 @@ pub mod CS9 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 9 ID Register"] pub mod ID9 { @@ -3157,14 +3077,6 @@ pub mod CS10 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 10 ID Register"] pub mod ID10 { @@ -3305,14 +3217,6 @@ pub mod CS11 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 11 ID Register"] pub mod ID11 { @@ -3453,14 +3357,6 @@ pub mod CS12 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 12 ID Register"] pub mod ID12 { @@ -3601,14 +3497,6 @@ pub mod CS13 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 13 ID Register"] pub mod ID13 { @@ -3749,14 +3637,6 @@ pub mod CS14 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 14 ID Register"] pub mod ID14 { @@ -3897,14 +3777,6 @@ pub mod CS15 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 15 ID Register"] pub mod ID15 { @@ -4045,14 +3917,6 @@ pub mod CS16 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 16 ID Register"] pub mod ID16 { @@ -4193,14 +4057,6 @@ pub mod CS17 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 17 ID Register"] pub mod ID17 { @@ -4341,14 +4197,6 @@ pub mod CS18 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 18 ID Register"] pub mod ID18 { @@ -4489,14 +4337,6 @@ pub mod CS19 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 19 ID Register"] pub mod ID19 { @@ -4637,14 +4477,6 @@ pub mod CS20 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 20 ID Register"] pub mod ID20 { @@ -4785,14 +4617,6 @@ pub mod CS21 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 21 ID Register"] pub mod ID21 { @@ -4933,14 +4757,6 @@ pub mod CS22 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 22 ID Register"] pub mod ID22 { @@ -5081,14 +4897,6 @@ pub mod CS23 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 23 ID Register"] pub mod ID23 { @@ -5229,14 +5037,6 @@ pub mod CS24 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 24 ID Register"] pub mod ID24 { @@ -5377,14 +5177,6 @@ pub mod CS25 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 25 ID Register"] pub mod ID25 { @@ -5525,14 +5317,6 @@ pub mod CS26 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 26 ID Register"] pub mod ID26 { @@ -5673,14 +5457,6 @@ pub mod CS27 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 27 ID Register"] pub mod ID27 { @@ -5821,14 +5597,6 @@ pub mod CS28 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 28 ID Register"] pub mod ID28 { @@ -5969,14 +5737,6 @@ pub mod CS29 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 29 ID Register"] pub mod ID29 { @@ -6117,14 +5877,6 @@ pub mod CS30 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 30 ID Register"] pub mod ID30 { @@ -6265,14 +6017,6 @@ pub mod CS31 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 31 ID Register"] pub mod ID31 { @@ -6413,14 +6157,6 @@ pub mod CS32 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 32 ID Register"] pub mod ID32 { @@ -6561,14 +6297,6 @@ pub mod CS33 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 33 ID Register"] pub mod ID33 { @@ -6709,14 +6437,6 @@ pub mod CS34 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 34 ID Register"] pub mod ID34 { @@ -6857,14 +6577,6 @@ pub mod CS35 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 35 ID Register"] pub mod ID35 { @@ -7005,14 +6717,6 @@ pub mod CS36 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 36 ID Register"] pub mod ID36 { @@ -7153,14 +6857,6 @@ pub mod CS37 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 37 ID Register"] pub mod ID37 { @@ -7301,14 +6997,6 @@ pub mod CS38 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 38 ID Register"] pub mod ID38 { @@ -7449,14 +7137,6 @@ pub mod CS39 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 39 ID Register"] pub mod ID39 { @@ -7597,14 +7277,6 @@ pub mod CS40 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 40 ID Register"] pub mod ID40 { @@ -7745,14 +7417,6 @@ pub mod CS41 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 41 ID Register"] pub mod ID41 { @@ -7893,14 +7557,6 @@ pub mod CS42 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 42 ID Register"] pub mod ID42 { @@ -8041,14 +7697,6 @@ pub mod CS43 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 43 ID Register"] pub mod ID43 { @@ -8189,14 +7837,6 @@ pub mod CS44 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 44 ID Register"] pub mod ID44 { @@ -8337,14 +7977,6 @@ pub mod CS45 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 45 ID Register"] pub mod ID45 { @@ -8485,14 +8117,6 @@ pub mod CS46 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 46 ID Register"] pub mod ID46 { @@ -8633,14 +8257,6 @@ pub mod CS47 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 47 ID Register"] pub mod ID47 { @@ -8781,14 +8397,6 @@ pub mod CS48 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 48 ID Register"] pub mod ID48 { @@ -8929,14 +8537,6 @@ pub mod CS49 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 49 ID Register"] pub mod ID49 { @@ -9077,14 +8677,6 @@ pub mod CS50 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 50 ID Register"] pub mod ID50 { @@ -9225,14 +8817,6 @@ pub mod CS51 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 51 ID Register"] pub mod ID51 { @@ -9373,14 +8957,6 @@ pub mod CS52 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 52 ID Register"] pub mod ID52 { @@ -9521,14 +9097,6 @@ pub mod CS53 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 53 ID Register"] pub mod ID53 { @@ -9669,14 +9237,6 @@ pub mod CS54 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 54 ID Register"] pub mod ID54 { @@ -9817,14 +9377,6 @@ pub mod CS55 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 55 ID Register"] pub mod ID55 { @@ -9965,14 +9517,6 @@ pub mod CS56 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 56 ID Register"] pub mod ID56 { @@ -10113,14 +9657,6 @@ pub mod CS57 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 57 ID Register"] pub mod ID57 { @@ -10261,14 +9797,6 @@ pub mod CS58 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 58 ID Register"] pub mod ID58 { @@ -10409,14 +9937,6 @@ pub mod CS59 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 59 ID Register"] pub mod ID59 { @@ -10557,14 +10077,6 @@ pub mod CS60 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 60 ID Register"] pub mod ID60 { @@ -10705,14 +10217,6 @@ pub mod CS61 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 61 ID Register"] pub mod ID61 { @@ -10853,14 +10357,6 @@ pub mod CS62 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 62 ID Register"] pub mod ID62 { @@ -11001,14 +10497,6 @@ pub mod CS63 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CODE { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Message Buffer 63 ID Register"] pub mod ID63 { diff --git a/src/blocks/imxrt1021/ccm.rs b/src/blocks/imxrt1021/ccm.rs index 7d022baaf2c8..33b1123af10d 100644 --- a/src/blocks/imxrt1021/ccm.rs +++ b/src/blocks/imxrt1021/ccm.rs @@ -2533,7 +2533,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can1 clock (can1_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -2541,7 +2541,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can1_serial clock (can1_serial_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; pub const mask: u32 = 0x03 << offset; @@ -2549,7 +2549,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can2 clock (can2_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -2557,7 +2557,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can2_serial clock (can2_serial_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -2624,7 +2624,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpspi3 clocks (lpspi3_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -2632,7 +2632,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpspi4 clocks (lpspi4_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -2640,7 +2640,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "adc2 clock (adc2_clk_enable)"] pub mod CG4 { pub const offset: u32 = 8; pub const mask: u32 = 0x03 << offset; @@ -2648,7 +2648,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enet clock (enet_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -2664,14 +2664,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "adc1 clock (adc1_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; @@ -2680,7 +2672,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "semc_exsc clock (semc_exsc_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -2728,14 +2720,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "gpio5 clock (gpio5_clk_enable)"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Clock Gating Register 2"] pub mod CCGR2 { @@ -2747,14 +2731,6 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "iomuxc_snvs clock (iomuxc_snvs_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; @@ -2779,7 +2755,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpi2c3 clock (lpi2c3_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -2795,38 +2771,6 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG7 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG9 { - pub const offset: u32 = 18; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "xbar1 clock (xbar1_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; @@ -2835,7 +2779,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "xbar2 clock (xbar2_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -2843,7 +2787,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "gpio3 clock (gpio3_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -2851,34 +2795,10 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG14 { - pub const offset: u32 = 28; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Clock Gating Register 3"] pub mod CCGR3 { - #[doc = "Reserved"] - pub mod CG0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] + #[doc = "lpuart5 clock (lpuart5_clk_enable)"] pub mod CG1 { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -2886,7 +2806,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "semc clocks (semc_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -2894,7 +2814,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart6 clock (lpuart6_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -2910,22 +2830,6 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG6 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "ewm clocks (ewm_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; @@ -2950,7 +2854,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp1 clocks (acmp1_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -2958,7 +2862,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp2 clocks (acmp2_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; pub const mask: u32 = 0x03 << offset; @@ -2966,7 +2870,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp3 clocks (acmp3_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -2974,7 +2878,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp4 clocks (acmp4_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3025,7 +2929,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "bee clock(bee_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -3041,14 +2945,6 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG5 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sim_m clocks (sim_m_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; @@ -3073,7 +2969,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "pwm2 clocks (pwm2_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -3081,23 +2977,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG10 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] - pub mod CG11 { - pub const offset: u32 = 22; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] + #[doc = "enc1 clocks (enc1_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3105,7 +2985,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enc2 clocks (enc2_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3113,22 +2993,6 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG14 { - pub const offset: u32 = 28; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "dma_ps clocks (dma_ps_clk_enable)"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Clock Gating Register 5"] pub mod CCGR5 { @@ -3180,7 +3044,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "aipstz4 clocks (aips_tz4_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; pub const mask: u32 = 0x03 << offset; @@ -3196,14 +3060,6 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "sai1 clock (sai1_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; @@ -3212,7 +3068,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "sai2 clock (sai2_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3236,7 +3092,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart7 clock (lpuart7_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3271,7 +3127,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "usdhc1 clocks (usdhc1_clk_enable)"] pub mod CG1 { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -3279,7 +3135,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "usdhc2 clocks (usdhc2_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -3295,14 +3151,6 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG4 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared"] pub mod CG5 { pub const offset: u32 = 10; @@ -3319,7 +3167,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart8 clocks (lpuart8_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -3327,15 +3175,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG8 { - pub const offset: u32 = 16; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Reserved"] + #[doc = "aips_tz3 clock (aips_tz3_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -3359,7 +3199,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpi2c4 serial clock (lpi2c4_serial_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3367,7 +3207,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer1 clocks (timer1_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3375,7 +3215,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer2 clocks (timer2_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3383,14 +3223,6 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Module Enable Overide Register"] pub mod CMEOR { diff --git a/src/blocks/imxrt1021/ocotp.rs b/src/blocks/imxrt1021/ocotp.rs index 7204f6c3ac7c..1fbf038d3305 100644 --- a/src/blocks/imxrt1021/ocotp.rs +++ b/src/blocks/imxrt1021/ocotp.rs @@ -731,14 +731,6 @@ pub mod LOCK { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod FIELD_RETURN { - pub const offset: u32 = 28; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)"] pub mod CFG0 { diff --git a/src/blocks/imxrt1051/ccm.rs b/src/blocks/imxrt1051/ccm.rs index e00afa4a0259..1c02b4241055 100644 --- a/src/blocks/imxrt1051/ccm.rs +++ b/src/blocks/imxrt1051/ccm.rs @@ -2732,7 +2732,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can1 clock (can1_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -2740,7 +2740,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can1_serial clock (can1_serial_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; pub const mask: u32 = 0x03 << offset; @@ -2748,7 +2748,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can2 clock (can2_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -2756,7 +2756,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can2_serial clock (can2_serial_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -2823,7 +2823,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpspi3 clocks (lpspi3_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -2831,7 +2831,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpspi4 clocks (lpspi4_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -2839,7 +2839,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "adc2 clock (adc2_clk_enable)"] pub mod CG4 { pub const offset: u32 = 8; pub const mask: u32 = 0x03 << offset; @@ -2847,7 +2847,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enet clock (enet_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -2863,7 +2863,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "aoi2 clocks (aoi2_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -2879,7 +2879,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "semc_exsc clock (semc_exsc_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -2927,14 +2927,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "gpio5 clock (gpio5_clk_enable)"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Clock Gating Register 2"] pub mod CCGR2 { @@ -2946,7 +2938,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "csi clock (csi_clk_enable)"] pub mod CG1 { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -2978,7 +2970,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpi2c3 clock (lpi2c3_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -2994,7 +2986,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "xbar3 clock (xbar3_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -3002,7 +2994,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "ipmux1 clock (ipmux1_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; pub const mask: u32 = 0x03 << offset; @@ -3010,7 +3002,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "ipmux2 clock (ipmux2_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -3018,7 +3010,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "ipmux3 clock (ipmux3_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3034,7 +3026,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "xbar2 clock (xbar2_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3042,7 +3034,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "gpio3 clock (gpio3_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3050,7 +3042,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lcd clocks (lcd_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3058,7 +3050,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "pxp clocks (pxp_clk_enable)"] pub mod CG15 { pub const offset: u32 = 30; pub const mask: u32 = 0x03 << offset; @@ -3069,7 +3061,7 @@ pub mod CCGR2 { } #[doc = "CCM Clock Gating Register 3"] pub mod CCGR3 { - #[doc = "Reserved"] + #[doc = "flexio2 clocks (flexio2_clk_enable)"] pub mod CG0 { pub const offset: u32 = 0; pub const mask: u32 = 0x03 << offset; @@ -3077,7 +3069,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart5 clock (lpuart5_clk_enable)"] pub mod CG1 { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -3085,7 +3077,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "semc clocks (semc_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -3093,7 +3085,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart6 clock (lpuart6_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -3109,7 +3101,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lcdif pix clock (lcdif_pix_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -3117,7 +3109,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "gpio4 clock (gpio4_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; pub const mask: u32 = 0x03 << offset; @@ -3149,7 +3141,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp1 clocks (acmp1_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3157,7 +3149,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp2 clocks (acmp2_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; pub const mask: u32 = 0x03 << offset; @@ -3165,7 +3157,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp3 clocks (acmp3_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3173,7 +3165,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp4 clocks (acmp4_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3181,7 +3173,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "The OCRAM clock cannot be turned off when the CM cache is running on this device."] + #[doc = "ocram clock (ocram_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3200,7 +3192,7 @@ pub mod CCGR3 { } #[doc = "CCM Clock Gating Register 4"] pub mod CCGR4 { - #[doc = "sim_m7_clk_r_enable"] + #[doc = "sim_m7 register access clock (sim_m7_mainclk_r_enable)"] pub mod CG0 { pub const offset: u32 = 0; pub const mask: u32 = 0x03 << offset; @@ -3224,7 +3216,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "bee clock(bee_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -3240,7 +3232,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "tsc_dig clock (tsc_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -3272,7 +3264,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "pwm2 clocks (pwm2_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -3280,7 +3272,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "pwm3 clocks (pwm3_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3288,7 +3280,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "pwm4 clocks (pwm4_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; pub const mask: u32 = 0x03 << offset; @@ -3296,7 +3288,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enc1 clocks (enc1_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3304,7 +3296,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enc2 clocks (enc2_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3312,7 +3304,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enc3 clocks (enc3_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3320,7 +3312,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "dma_ps clocks (dma_ps_clk_enable)"] + #[doc = "enc4 clocks (enc4_clk_enable)"] pub mod CG15 { pub const offset: u32 = 30; pub const mask: u32 = 0x03 << offset; @@ -3379,7 +3371,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "aipstz4 clocks (aips_tz4_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; pub const mask: u32 = 0x03 << offset; @@ -3395,7 +3387,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "sim_main clock (sim_main_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; pub const mask: u32 = 0x03 << offset; @@ -3411,7 +3403,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "sai2 clock (sai2_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3435,7 +3427,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart7 clock (lpuart7_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3470,7 +3462,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "usdhc1 clocks (usdhc1_clk_enable)"] pub mod CG1 { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -3478,7 +3470,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "usdhc2 clocks (usdhc2_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -3494,7 +3486,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "ipmux4 clock (ipmux4_clk_enable)"] pub mod CG4 { pub const offset: u32 = 8; pub const mask: u32 = 0x03 << offset; @@ -3518,7 +3510,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart8 clocks (lpuart8_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -3526,7 +3518,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer4 clocks (timer4_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; pub const mask: u32 = 0x03 << offset; @@ -3534,7 +3526,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "aips_tz3 clock (aips_tz3_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -3558,7 +3550,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpi2c4 serial clock (lpi2c4_serial_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3566,7 +3558,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer1 clocks (timer1_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3574,7 +3566,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer2 clocks (timer2_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3582,7 +3574,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer3 clocks (timer3_clk_enable)"] pub mod CG15 { pub const offset: u32 = 30; pub const mask: u32 = 0x03 << offset; diff --git a/src/blocks/imxrt1051/ccm_analog.rs b/src/blocks/imxrt1051/ccm_analog.rs index c86ea0cdb3fd..7c8b14e16710 100644 --- a/src/blocks/imxrt1051/ccm_analog.rs +++ b/src/blocks/imxrt1051/ccm_analog.rs @@ -167,14 +167,6 @@ pub mod PLL_ARM { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod PLL_SEL { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."] pub mod LOCK { pub const offset: u32 = 31; @@ -231,14 +223,6 @@ pub mod PLL_ARM_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod PLL_SEL { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."] pub mod LOCK { pub const offset: u32 = 31; @@ -295,14 +279,6 @@ pub mod PLL_ARM_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod PLL_SEL { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."] pub mod LOCK { pub const offset: u32 = 31; @@ -359,14 +335,6 @@ pub mod PLL_ARM_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod PLL_SEL { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."] pub mod LOCK { pub const offset: u32 = 31; diff --git a/src/blocks/imxrt1051/dcdc.rs b/src/blocks/imxrt1051/dcdc.rs index bfbfde9525fb..6d413678056f 100644 --- a/src/blocks/imxrt1051/dcdc.rs +++ b/src/blocks/imxrt1051/dcdc.rs @@ -325,14 +325,6 @@ pub mod REG3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod MISC_DISABLEFET_LOGIC { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Disable stepping for the output VDD_SOC of DCDC"] pub mod DISABLE_STEP { pub const offset: u32 = 30; diff --git a/src/blocks/imxrt1051/usbphy.rs b/src/blocks/imxrt1051/usbphy.rs index 87e42b05b030..3f003dcf7be9 100644 --- a/src/blocks/imxrt1051/usbphy.rs +++ b/src/blocks/imxrt1051/usbphy.rs @@ -60,14 +60,6 @@ pub struct RegisterBlock { } #[doc = "USB PHY Power-Down Register"] pub mod PWD { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; @@ -92,14 +84,6 @@ pub mod PWD { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; @@ -132,25 +116,9 @@ pub mod PWD { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Power-Down Register"] pub mod PWD_SET { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; @@ -175,14 +143,6 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; @@ -215,25 +175,9 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Power-Down Register"] pub mod PWD_CLR { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; @@ -258,14 +202,6 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; @@ -298,25 +234,9 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Power-Down Register"] pub mod PWD_TOG { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; @@ -341,14 +261,6 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; @@ -381,14 +293,6 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Transmitter Control Register"] pub mod TX { @@ -400,14 +304,6 @@ pub mod TX { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"] pub mod TXCAL45DN { pub const offset: u32 = 8; @@ -416,14 +312,6 @@ pub mod TX { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"] pub mod TXCAL45DP { pub const offset: u32 = 16; @@ -432,14 +320,6 @@ pub mod TX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"] pub mod USBPHY_TX_EDGECTRL { pub const offset: u32 = 26; @@ -448,14 +328,6 @@ pub mod TX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD5 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Transmitter Control Register"] pub mod TX_SET { @@ -467,14 +339,6 @@ pub mod TX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"] pub mod TXCAL45DN { pub const offset: u32 = 8; @@ -483,14 +347,6 @@ pub mod TX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"] pub mod TXCAL45DP { pub const offset: u32 = 16; @@ -499,14 +355,6 @@ pub mod TX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"] pub mod USBPHY_TX_EDGECTRL { pub const offset: u32 = 26; @@ -515,14 +363,6 @@ pub mod TX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD5 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Transmitter Control Register"] pub mod TX_CLR { @@ -534,14 +374,6 @@ pub mod TX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"] pub mod TXCAL45DN { pub const offset: u32 = 8; @@ -550,14 +382,6 @@ pub mod TX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"] pub mod TXCAL45DP { pub const offset: u32 = 16; @@ -566,14 +390,6 @@ pub mod TX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"] pub mod USBPHY_TX_EDGECTRL { pub const offset: u32 = 26; @@ -582,14 +398,6 @@ pub mod TX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD5 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Transmitter Control Register"] pub mod TX_TOG { @@ -601,14 +409,6 @@ pub mod TX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"] pub mod TXCAL45DN { pub const offset: u32 = 8; @@ -617,14 +417,6 @@ pub mod TX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"] pub mod TXCAL45DP { pub const offset: u32 = 16; @@ -633,14 +425,6 @@ pub mod TX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 20; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"] pub mod USBPHY_TX_EDGECTRL { pub const offset: u32 = 26; @@ -649,14 +433,6 @@ pub mod TX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD5 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Receiver Control Register"] pub mod RX { @@ -668,14 +444,6 @@ pub mod RX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; @@ -684,14 +452,6 @@ pub mod RX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; @@ -700,14 +460,6 @@ pub mod RX { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Receiver Control Register"] pub mod RX_SET { @@ -719,14 +471,6 @@ pub mod RX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; @@ -735,14 +479,6 @@ pub mod RX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; @@ -751,14 +487,6 @@ pub mod RX_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Receiver Control Register"] pub mod RX_CLR { @@ -770,14 +498,6 @@ pub mod RX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; @@ -786,14 +506,6 @@ pub mod RX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; @@ -802,14 +514,6 @@ pub mod RX_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Receiver Control Register"] pub mod RX_TOG { @@ -821,14 +525,6 @@ pub mod RX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; @@ -837,14 +533,6 @@ pub mod RX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; @@ -853,14 +541,6 @@ pub mod RX_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY General Control Register"] pub mod CTRL { @@ -1064,14 +744,6 @@ pub mod CTRL { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 25; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"] pub mod OTG_ID_VALUE { pub const offset: u32 = 27; @@ -1315,14 +987,6 @@ pub mod CTRL_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 25; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"] pub mod OTG_ID_VALUE { pub const offset: u32 = 27; @@ -1566,14 +1230,6 @@ pub mod CTRL_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 25; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"] pub mod OTG_ID_VALUE { pub const offset: u32 = 27; @@ -1817,14 +1473,6 @@ pub mod CTRL_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 25; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"] pub mod OTG_ID_VALUE { pub const offset: u32 = 27; @@ -1868,14 +1516,6 @@ pub mod CTRL_TOG { } #[doc = "USB PHY Status Register"] pub mod STATUS { - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that the device has disconnected while in high-speed host mode."] pub mod HOSTDISCONDETECT_STATUS { pub const offset: u32 = 3; @@ -1884,14 +1524,6 @@ pub mod STATUS { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 4; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that the device has been connected on the USB_DP and USB_DM lines."] pub mod DEVPLUGIN_STATUS { pub const offset: u32 = 6; @@ -1900,14 +1532,6 @@ pub mod STATUS { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 7; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the results of ID pin on MiniAB plug"] pub mod OTGID_STATUS { pub const offset: u32 = 8; @@ -1916,14 +1540,6 @@ pub mod STATUS { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 9; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that the host is sending a wake-up after suspend and has triggered an interrupt."] pub mod RESUME_STATUS { pub const offset: u32 = 10; @@ -1932,14 +1548,6 @@ pub mod STATUS { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD4 { - pub const offset: u32 = 11; - pub const mask: u32 = 0x001f_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Debug Register"] pub mod DEBUG { @@ -1975,14 +1583,6 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; @@ -1999,14 +1599,6 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; @@ -2015,14 +1607,6 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; @@ -2055,14 +1639,6 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Debug Register"] pub mod DEBUG_SET { @@ -2098,14 +1674,6 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; @@ -2122,14 +1690,6 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; @@ -2138,14 +1698,6 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; @@ -2178,14 +1730,6 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Debug Register"] pub mod DEBUG_CLR { @@ -2221,14 +1765,6 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; @@ -2245,14 +1781,6 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; @@ -2261,14 +1789,6 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; @@ -2301,14 +1821,6 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "USB PHY Debug Register"] pub mod DEBUG_TOG { @@ -2344,14 +1856,6 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; @@ -2368,14 +1872,6 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 13; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; @@ -2384,14 +1880,6 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD2 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; @@ -2424,14 +1912,6 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD3 { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI Debug Status Register 0"] pub mod DEBUG0_STATUS { @@ -2462,14 +1942,6 @@ pub mod DEBUG0_STATUS { } #[doc = "UTMI Debug Status Register 1"] pub mod DEBUG1 { - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"] pub mod ENTAILADJVD { pub const offset: u32 = 13; @@ -2478,25 +1950,9 @@ pub mod DEBUG1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x0001_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI Debug Status Register 1"] pub mod DEBUG1_SET { - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"] pub mod ENTAILADJVD { pub const offset: u32 = 13; @@ -2505,25 +1961,9 @@ pub mod DEBUG1_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x0001_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI Debug Status Register 1"] pub mod DEBUG1_CLR { - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"] pub mod ENTAILADJVD { pub const offset: u32 = 13; @@ -2532,25 +1972,9 @@ pub mod DEBUG1_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x0001_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI Debug Status Register 1"] pub mod DEBUG1_TOG { - #[doc = "Reserved. Note: This bit should remain clear."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"] pub mod ENTAILADJVD { pub const offset: u32 = 13; @@ -2559,14 +1983,6 @@ pub mod DEBUG1_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved."] - pub mod RSVD1 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x0001_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "UTMI RTL Version"] pub mod VERSION { diff --git a/src/blocks/imxrt1052/pxp.rs b/src/blocks/imxrt1052/pxp.rs index 7958f97abed4..4e0c7f1e1a24 100644 --- a/src/blocks/imxrt1052/pxp.rs +++ b/src/blocks/imxrt1052/pxp.rs @@ -151,14 +151,6 @@ pub mod CTRL { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 5; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the clockwise rotation to be applied at the output buffer"] pub mod ROTATE { pub const offset: u32 = 8; @@ -192,14 +184,6 @@ pub mod CTRL { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This bit controls where rotation will occur in the PXP datapath"] pub mod ROT_POS { pub const offset: u32 = 22; @@ -221,14 +205,6 @@ pub mod CTRL { pub const _16X16: u32 = 0x01; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD3 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Enable the PXP to run continuously"] pub mod EN_REPEAT { pub const offset: u32 = 28; @@ -237,14 +213,6 @@ pub mod CTRL { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD4 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This bit must be set to zero for normal operation"] pub mod CLKGATE { pub const offset: u32 = 30; @@ -296,14 +264,6 @@ pub mod CTRL_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 5; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the clockwise rotation to be applied at the output buffer"] pub mod ROTATE { pub const offset: u32 = 8; @@ -337,14 +297,6 @@ pub mod CTRL_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This bit controls where rotation will occur in the PXP datapath"] pub mod ROT_POS { pub const offset: u32 = 22; @@ -366,14 +318,6 @@ pub mod CTRL_SET { pub const _16X16: u32 = 0x01; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD3 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Enable the PXP to run continuously"] pub mod EN_REPEAT { pub const offset: u32 = 28; @@ -382,14 +326,6 @@ pub mod CTRL_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD4 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This bit must be set to zero for normal operation"] pub mod CLKGATE { pub const offset: u32 = 30; @@ -441,14 +377,6 @@ pub mod CTRL_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 5; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the clockwise rotation to be applied at the output buffer"] pub mod ROTATE { pub const offset: u32 = 8; @@ -482,14 +410,6 @@ pub mod CTRL_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This bit controls where rotation will occur in the PXP datapath"] pub mod ROT_POS { pub const offset: u32 = 22; @@ -511,14 +431,6 @@ pub mod CTRL_CLR { pub const _16X16: u32 = 0x01; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD3 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Enable the PXP to run continuously"] pub mod EN_REPEAT { pub const offset: u32 = 28; @@ -527,14 +439,6 @@ pub mod CTRL_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD4 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This bit must be set to zero for normal operation"] pub mod CLKGATE { pub const offset: u32 = 30; @@ -586,14 +490,6 @@ pub mod CTRL_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 5; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the clockwise rotation to be applied at the output buffer"] pub mod ROTATE { pub const offset: u32 = 8; @@ -627,14 +523,6 @@ pub mod CTRL_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x03ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This bit controls where rotation will occur in the PXP datapath"] pub mod ROT_POS { pub const offset: u32 = 22; @@ -656,14 +544,6 @@ pub mod CTRL_TOG { pub const _16X16: u32 = 0x01; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD3 { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Enable the PXP to run continuously"] pub mod EN_REPEAT { pub const offset: u32 = 28; @@ -672,14 +552,6 @@ pub mod CTRL_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD4 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This bit must be set to zero for normal operation"] pub mod CLKGATE { pub const offset: u32 = 30; @@ -747,14 +619,6 @@ pub mod STAT { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD2 { - pub const offset: u32 = 9; - pub const mask: u32 = 0x7f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the X coordinate of the block currently being rendered."] pub mod BLOCKY { pub const offset: u32 = 16; @@ -822,14 +686,6 @@ pub mod STAT_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD2 { - pub const offset: u32 = 9; - pub const mask: u32 = 0x7f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the X coordinate of the block currently being rendered."] pub mod BLOCKY { pub const offset: u32 = 16; @@ -897,14 +753,6 @@ pub mod STAT_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD2 { - pub const offset: u32 = 9; - pub const mask: u32 = 0x7f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the X coordinate of the block currently being rendered."] pub mod BLOCKY { pub const offset: u32 = 16; @@ -972,14 +820,6 @@ pub mod STAT_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD2 { - pub const offset: u32 = 9; - pub const mask: u32 = 0x7f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates the X coordinate of the block currently being rendered."] pub mod BLOCKY { pub const offset: u32 = 16; @@ -1042,14 +882,6 @@ pub mod OUT_CTRL { pub const YVU2P420: u32 = 0x1b; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 5; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Determines how the PXP writes it's output data"] pub mod INTERLACED_OUTPUT { pub const offset: u32 = 8; @@ -1067,14 +899,6 @@ pub mod OUT_CTRL { pub const INTERLACED: u32 = 0x03; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL\\[ALPHA\\]"] pub mod ALPHA_OUTPUT { pub const offset: u32 = 23; @@ -1137,14 +961,6 @@ pub mod OUT_CTRL_SET { pub const YVU2P420: u32 = 0x1b; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 5; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Determines how the PXP writes it's output data"] pub mod INTERLACED_OUTPUT { pub const offset: u32 = 8; @@ -1162,14 +978,6 @@ pub mod OUT_CTRL_SET { pub const INTERLACED: u32 = 0x03; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL\\[ALPHA\\]"] pub mod ALPHA_OUTPUT { pub const offset: u32 = 23; @@ -1232,14 +1040,6 @@ pub mod OUT_CTRL_CLR { pub const YVU2P420: u32 = 0x1b; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 5; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Determines how the PXP writes it's output data"] pub mod INTERLACED_OUTPUT { pub const offset: u32 = 8; @@ -1257,14 +1057,6 @@ pub mod OUT_CTRL_CLR { pub const INTERLACED: u32 = 0x03; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL\\[ALPHA\\]"] pub mod ALPHA_OUTPUT { pub const offset: u32 = 23; @@ -1327,14 +1119,6 @@ pub mod OUT_CTRL_TOG { pub const YVU2P420: u32 = 0x1b; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 5; - pub const mask: u32 = 0x07 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Determines how the PXP writes it's output data"] pub mod INTERLACED_OUTPUT { pub const offset: u32 = 8; @@ -1352,14 +1136,6 @@ pub mod OUT_CTRL_TOG { pub const INTERLACED: u32 = 0x03; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 10; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL\\[ALPHA\\]"] pub mod ALPHA_OUTPUT { pub const offset: u32 = 23; @@ -1409,14 +1185,6 @@ pub mod OUT_PITCH { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD { - pub const offset: u32 = 16; - pub const mask: u32 = 0xffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Output Surface Lower Right Coordinate"] pub mod OUT_LRC { @@ -1428,14 +1196,6 @@ pub mod OUT_LRC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Indicates number of horizontal PIXELS in the output surface (non-rotated)"] pub mod X { pub const offset: u32 = 16; @@ -1444,14 +1204,6 @@ pub mod OUT_LRC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Processed Surface Upper Left Coordinate"] pub mod OUT_PS_ULC { @@ -1463,14 +1215,6 @@ pub mod OUT_PS_ULC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This field indicates the upper left X-coordinate (in pixels) of the processed surface (PS) in the output buffer"] pub mod X { pub const offset: u32 = 16; @@ -1479,14 +1223,6 @@ pub mod OUT_PS_ULC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Processed Surface Lower Right Coordinate"] pub mod OUT_PS_LRC { @@ -1498,14 +1234,6 @@ pub mod OUT_PS_LRC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This field indicates the lower right X-coordinate (in pixels) of the processed surface (PS) in the output frame buffer"] pub mod X { pub const offset: u32 = 16; @@ -1514,14 +1242,6 @@ pub mod OUT_PS_LRC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Alpha Surface Upper Left Coordinate"] pub mod OUT_AS_ULC { @@ -1533,14 +1253,6 @@ pub mod OUT_AS_ULC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This field indicates the upper left X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer"] pub mod X { pub const offset: u32 = 16; @@ -1549,14 +1261,6 @@ pub mod OUT_AS_ULC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Alpha Surface Lower Right Coordinate"] pub mod OUT_AS_LRC { @@ -1568,14 +1272,6 @@ pub mod OUT_AS_LRC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 14; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This field indicates the lower right X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer"] pub mod X { pub const offset: u32 = 16; @@ -1584,14 +1280,6 @@ pub mod OUT_AS_LRC { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Processed Surface (PS) Control Register"] pub mod PS_CTRL { @@ -1642,14 +1330,6 @@ pub mod PS_CTRL { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Verticle pre decimation filter control."] pub mod DECY { pub const offset: u32 = 8; @@ -1684,14 +1364,6 @@ pub mod PS_CTRL { pub const DECX8: u32 = 0x03; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x000f_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Processed Surface (PS) Control Register"] pub mod PS_CTRL_SET { @@ -1742,14 +1414,6 @@ pub mod PS_CTRL_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Verticle pre decimation filter control."] pub mod DECY { pub const offset: u32 = 8; @@ -1784,14 +1448,6 @@ pub mod PS_CTRL_SET { pub const DECX8: u32 = 0x03; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x000f_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Processed Surface (PS) Control Register"] pub mod PS_CTRL_CLR { @@ -1842,14 +1498,6 @@ pub mod PS_CTRL_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Verticle pre decimation filter control."] pub mod DECY { pub const offset: u32 = 8; @@ -1884,14 +1532,6 @@ pub mod PS_CTRL_CLR { pub const DECX8: u32 = 0x03; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x000f_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Processed Surface (PS) Control Register"] pub mod PS_CTRL_TOG { @@ -1942,14 +1582,6 @@ pub mod PS_CTRL_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Verticle pre decimation filter control."] pub mod DECY { pub const offset: u32 = 8; @@ -1984,14 +1616,6 @@ pub mod PS_CTRL_TOG { pub const DECX8: u32 = 0x03; } } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x000f_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "PS Input Buffer Address"] pub mod PS_BUF { @@ -2036,14 +1660,6 @@ pub mod PS_PITCH { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD { - pub const offset: u32 = 16; - pub const mask: u32 = 0xffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "PS Background Color"] pub mod PS_BACKGROUND { @@ -2055,14 +1671,6 @@ pub mod PS_BACKGROUND { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD { - pub const offset: u32 = 24; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "PS Scale Factor Register"] pub mod PS_SCALE { @@ -2074,14 +1682,6 @@ pub mod PS_SCALE { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 15; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This is a two bit integer and 12 bit fractional representation (##"] pub mod YSCALE { pub const offset: u32 = 16; @@ -2090,14 +1690,6 @@ pub mod PS_SCALE { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD2 { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "PS Scale Offset Register"] pub mod PS_OFFSET { @@ -2109,14 +1701,6 @@ pub mod PS_OFFSET { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 12; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "This is a 12 bit fractional representation (0"] pub mod YOFFSET { pub const offset: u32 = 16; @@ -2125,14 +1709,6 @@ pub mod PS_OFFSET { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD2 { - pub const offset: u32 = 28; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "PS Color Key Low"] pub mod PS_CLRKEYLOW { @@ -2144,14 +1720,6 @@ pub mod PS_CLRKEYLOW { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 24; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "PS Color Key High"] pub mod PS_CLRKEYHIGH { @@ -2163,25 +1731,9 @@ pub mod PS_CLRKEYHIGH { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 24; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Alpha Surface Control"] pub mod AS_CTRL { - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Determines how the alpha value is constructed for this alpha surface"] pub mod ALPHA_CTRL { pub const offset: u32 = 1; @@ -2279,14 +1831,6 @@ pub mod AS_CTRL { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 21; - pub const mask: u32 = 0x07ff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Alpha Surface Buffer Pointer"] pub mod AS_BUF { @@ -2309,14 +1853,6 @@ pub mod AS_PITCH { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD { - pub const offset: u32 = 16; - pub const mask: u32 = 0xffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Overlay Color Key Low"] pub mod AS_CLRKEYLOW { @@ -2328,14 +1864,6 @@ pub mod AS_CLRKEYLOW { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 24; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Overlay Color Key High"] pub mod AS_CLRKEYHIGH { @@ -2347,14 +1875,6 @@ pub mod AS_CLRKEYHIGH { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 24; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Color Space Conversion Coefficient Register 0"] pub mod CSC1_COEF0 { @@ -2382,14 +1902,6 @@ pub mod CSC1_COEF0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Bypass the CSC unit in the scaling engine"] pub mod BYPASS { pub const offset: u32 = 30; @@ -2417,14 +1929,6 @@ pub mod CSC1_COEF1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 11; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596)"] pub mod C1 { pub const offset: u32 = 16; @@ -2433,14 +1937,6 @@ pub mod CSC1_COEF1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 27; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Color Space Conversion Coefficient Register 2"] pub mod CSC1_COEF2 { @@ -2452,14 +1948,6 @@ pub mod CSC1_COEF2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD0 { - pub const offset: u32 = 11; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "Two's complement Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813)"] pub mod C2 { pub const offset: u32 = 16; @@ -2468,14 +1956,6 @@ pub mod CSC1_COEF2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD1 { - pub const offset: u32 = 27; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "PXP Power Control Register"] pub mod POWER { @@ -2515,14 +1995,6 @@ pub mod NEXT { pub mod W {} pub mod RW {} } - #[doc = "Reserved, always set to zero."] - pub mod RSVD { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "A pointer to a data structure containing register values to be used when processing the next frame"] pub mod POINTER { pub const offset: u32 = 2; diff --git a/src/blocks/imxrt1061/ccm.rs b/src/blocks/imxrt1061/ccm.rs index 05ee3890132d..f3d3a0bd44f3 100644 --- a/src/blocks/imxrt1061/ccm.rs +++ b/src/blocks/imxrt1061/ccm.rs @@ -2773,7 +2773,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can1 clock (can1_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -2781,7 +2781,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can1_serial clock (can1_serial_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; pub const mask: u32 = 0x03 << offset; @@ -2789,7 +2789,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can2 clock (can2_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -2797,7 +2797,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "can2_serial clock (can2_serial_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -2864,7 +2864,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpspi3 clocks (lpspi3_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -2872,7 +2872,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpspi4 clocks (lpspi4_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -2880,7 +2880,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "adc2 clock (adc2_clk_enable)"] pub mod CG4 { pub const offset: u32 = 8; pub const mask: u32 = 0x03 << offset; @@ -2888,7 +2888,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enet clock (enet_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -2904,7 +2904,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "aoi2 clocks (aoi2_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -2920,7 +2920,7 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "semc_exsc clock (semc_exsc_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -2968,14 +2968,6 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } - #[doc = "gpio5 clock (gpio5_clk_enable)"] - pub mod CG15 { - pub const offset: u32 = 30; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "CCM Clock Gating Register 2"] pub mod CCGR2 { @@ -2987,7 +2979,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "csi clock (csi_clk_enable)"] pub mod CG1 { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -3019,7 +3011,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpi2c3 clock (lpi2c3_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -3035,7 +3027,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "xbar3 clock (xbar3_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -3043,7 +3035,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "ipmux1 clock (ipmux1_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; pub const mask: u32 = 0x03 << offset; @@ -3051,7 +3043,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "ipmux2 clock (ipmux2_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -3059,7 +3051,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "ipmux3 clock (ipmux3_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3075,7 +3067,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "xbar2 clock (xbar2_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3083,7 +3075,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "gpio3 clock (gpio3_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3091,7 +3083,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lcd clocks (lcd_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3099,7 +3091,7 @@ pub mod CCGR2 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "pxp clocks (pxp_clk_enable)"] pub mod CG15 { pub const offset: u32 = 30; pub const mask: u32 = 0x03 << offset; @@ -3110,7 +3102,7 @@ pub mod CCGR2 { } #[doc = "CCM Clock Gating Register 3"] pub mod CCGR3 { - #[doc = "Reserved"] + #[doc = "flexio2 clocks (flexio2_clk_enable)"] pub mod CG0 { pub const offset: u32 = 0; pub const mask: u32 = 0x03 << offset; @@ -3118,7 +3110,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart5 clock (lpuart5_clk_enable)"] pub mod CG1 { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -3126,7 +3118,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "semc clocks (semc_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -3134,7 +3126,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart6 clock (lpuart6_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -3150,7 +3142,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lcdif pix clock (lcdif_pix_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -3158,7 +3150,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "gpio4 clock (gpio4_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; pub const mask: u32 = 0x03 << offset; @@ -3190,7 +3182,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp1 clocks (acmp1_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3198,7 +3190,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp2 clocks (acmp2_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; pub const mask: u32 = 0x03 << offset; @@ -3206,7 +3198,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp3 clocks (acmp3_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3214,7 +3206,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "acmp4 clocks (acmp4_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3222,7 +3214,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "The OCRAM clock cannot be turned off when the CM cache is running on this device."] + #[doc = "ocram clock (ocram_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3241,7 +3233,7 @@ pub mod CCGR3 { } #[doc = "CCM Clock Gating Register 4"] pub mod CCGR4 { - #[doc = "sim_m7_clk_r_enable"] + #[doc = "sim_m7 register access clock (sim_m7_mainclk_r_enable)"] pub mod CG0 { pub const offset: u32 = 0; pub const mask: u32 = 0x03 << offset; @@ -3265,7 +3257,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "bee clock(bee_clk_enable)"] pub mod CG3 { pub const offset: u32 = 6; pub const mask: u32 = 0x03 << offset; @@ -3281,7 +3273,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "tsc_dig clock (tsc_clk_enable)"] pub mod CG5 { pub const offset: u32 = 10; pub const mask: u32 = 0x03 << offset; @@ -3313,7 +3305,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "pwm2 clocks (pwm2_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -3321,7 +3313,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "pwm3 clocks (pwm3_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3329,7 +3321,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "pwm4 clocks (pwm4_clk_enable)"] pub mod CG11 { pub const offset: u32 = 22; pub const mask: u32 = 0x03 << offset; @@ -3337,7 +3329,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enc1 clocks (enc1_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3345,7 +3337,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enc2 clocks (enc2_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3353,7 +3345,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "enc3 clocks (enc3_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3361,7 +3353,7 @@ pub mod CCGR4 { pub mod W {} pub mod RW {} } - #[doc = "dma_ps clocks (dma_ps_clk_enable)"] + #[doc = "enc4 clocks (enc4_clk_enable)"] pub mod CG15 { pub const offset: u32 = 30; pub const mask: u32 = 0x03 << offset; @@ -3420,7 +3412,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "aipstz4 clocks (aips_tz4_clk_enable)"] pub mod CG6 { pub const offset: u32 = 12; pub const mask: u32 = 0x03 << offset; @@ -3436,7 +3428,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "sim_main clock (sim_main_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; pub const mask: u32 = 0x03 << offset; @@ -3452,7 +3444,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "sai2 clock (sai2_clk_enable)"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; @@ -3476,7 +3468,7 @@ pub mod CCGR5 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart7 clock (lpuart7_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3511,7 +3503,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "usdhc1 clocks (usdhc1_clk_enable)"] pub mod CG1 { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -3519,7 +3511,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "usdhc2 clocks (usdhc2_clk_enable)"] pub mod CG2 { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -3535,7 +3527,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "ipmux4 clock (ipmux4_clk_enable)"] pub mod CG4 { pub const offset: u32 = 8; pub const mask: u32 = 0x03 << offset; @@ -3559,7 +3551,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpuart8 clocks (lpuart8_clk_enable)"] pub mod CG7 { pub const offset: u32 = 14; pub const mask: u32 = 0x03 << offset; @@ -3567,7 +3559,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer4 clocks (timer4_clk_enable)"] pub mod CG8 { pub const offset: u32 = 16; pub const mask: u32 = 0x03 << offset; @@ -3575,7 +3567,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "aips_tz3 clock (aips_tz3_clk_enable)"] pub mod CG9 { pub const offset: u32 = 18; pub const mask: u32 = 0x03 << offset; @@ -3599,7 +3591,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "lpi2c4 serial clock (lpi2c4_serial_clk_enable)"] pub mod CG12 { pub const offset: u32 = 24; pub const mask: u32 = 0x03 << offset; @@ -3607,7 +3599,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer1 clocks (timer1_clk_enable)"] pub mod CG13 { pub const offset: u32 = 26; pub const mask: u32 = 0x03 << offset; @@ -3615,7 +3607,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer2 clocks (timer2_clk_enable)"] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3623,7 +3615,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] + #[doc = "timer3 clocks (timer3_clk_enable)"] pub mod CG15 { pub const offset: u32 = 30; pub const mask: u32 = 0x03 << offset; diff --git a/src/blocks/imxrt1061/ccm_analog.rs b/src/blocks/imxrt1061/ccm_analog.rs index a367bc12d179..ba8a39df87d5 100644 --- a/src/blocks/imxrt1061/ccm_analog.rs +++ b/src/blocks/imxrt1061/ccm_analog.rs @@ -167,14 +167,6 @@ pub mod PLL_ARM { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod PLL_SEL { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."] pub mod LOCK { pub const offset: u32 = 31; @@ -231,14 +223,6 @@ pub mod PLL_ARM_SET { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod PLL_SEL { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."] pub mod LOCK { pub const offset: u32 = 31; @@ -295,14 +279,6 @@ pub mod PLL_ARM_CLR { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod PLL_SEL { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."] pub mod LOCK { pub const offset: u32 = 31; @@ -359,14 +335,6 @@ pub mod PLL_ARM_TOG { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod PLL_SEL { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."] pub mod LOCK { pub const offset: u32 = 31; diff --git a/src/blocks/imxrt1176_cm4/flexram.rs b/src/blocks/imxrt1176_cm4/flexram.rs index fd04ae3dad6d..3fae382c671c 100644 --- a/src/blocks/imxrt1176_cm4/flexram.rs +++ b/src/blocks/imxrt1176_cm4/flexram.rs @@ -113,14 +113,6 @@ pub mod TCM_CTRL { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 3; - pub const mask: u32 = 0x1fff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "OCRAM Magic Address Register"] pub mod OCRAM_MAGIC_ADDR { @@ -145,14 +137,6 @@ pub mod OCRAM_MAGIC_ADDR { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 18; - pub const mask: u32 = 0x3fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "DTCM Magic Address Register"] pub mod DTCM_MAGIC_ADDR { @@ -177,14 +161,6 @@ pub mod DTCM_MAGIC_ADDR { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 17; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "ITCM Magic Address Register"] pub mod ITCM_MAGIC_ADDR { @@ -209,14 +185,6 @@ pub mod ITCM_MAGIC_ADDR { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 17; - pub const mask: u32 = 0x7fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Interrupt Status Register"] pub mod INT_STATUS { @@ -454,14 +422,6 @@ pub mod INT_STATUS { pub const OCRAM_PARTIAL_WR_INT_S_1: u32 = 0x01; } } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 18; - pub const mask: u32 = 0x3fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Interrupt Status Enable Register"] pub mod INT_STAT_EN { @@ -699,14 +659,6 @@ pub mod INT_STAT_EN { pub const OCRAM_PARTIAL_WR_INT_S_EN_1: u32 = 0x01; } } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 18; - pub const mask: u32 = 0x3fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Interrupt Enable Register"] pub mod INT_SIG_EN { @@ -944,14 +896,6 @@ pub mod INT_SIG_EN { pub const OCRAM_PARTIAL_WR_INT_SIG_EN_1: u32 = 0x01; } } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 18; - pub const mask: u32 = 0x3fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "OCRAM single-bit ECC Error Information Register"] pub mod OCRAM_ECC_SINGLE_ERROR_INFO { @@ -971,14 +915,6 @@ pub mod OCRAM_ECC_SINGLE_ERROR_INFO { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 16; - pub const mask: u32 = 0xffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "OCRAM single-bit ECC Error Address Register"] pub mod OCRAM_ECC_SINGLE_ERROR_ADDR { @@ -1023,14 +959,6 @@ pub mod OCRAM_ECC_MULTI_ERROR_INFO { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 8; - pub const mask: u32 = 0x00ff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "OCRAM multi-bit ECC Error Address Register"] pub mod OCRAM_ECC_MULTI_ERROR_ADDR { @@ -1107,14 +1035,6 @@ pub mod ITCM_ECC_SINGLE_ERROR_INFO { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "ITCM single-bit ECC Error Address Register"] pub mod ITCM_ECC_SINGLE_ERROR_ADDR { @@ -1191,14 +1111,6 @@ pub mod ITCM_ECC_MULTI_ERROR_INFO { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 20; - pub const mask: u32 = 0x0fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "ITCM multi-bit ECC Error Address Register"] pub mod ITCM_ECC_MULTI_ERROR_ADDR { @@ -1275,14 +1187,6 @@ pub mod D0TCM_ECC_SINGLE_ERROR_INFO { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 19; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "D0TCM single-bit ECC Error Address Register"] pub mod D0TCM_ECC_SINGLE_ERROR_ADDR { @@ -1348,14 +1252,6 @@ pub mod D0TCM_ECC_MULTI_ERROR_INFO { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 19; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "D0TCM multi-bit ECC Error Address Register"] pub mod D0TCM_ECC_MULTI_ERROR_ADDR { @@ -1421,14 +1317,6 @@ pub mod D1TCM_ECC_SINGLE_ERROR_INFO { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 19; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "D1TCM single-bit ECC Error Address Register"] pub mod D1TCM_ECC_SINGLE_ERROR_ADDR { @@ -1494,14 +1382,6 @@ pub mod D1TCM_ECC_MULTI_ERROR_INFO { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 19; - pub const mask: u32 = 0x1fff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "D1TCM multi-bit ECC Error Address Register"] pub mod D1TCM_ECC_MULTI_ERROR_ADDR { @@ -1575,14 +1455,6 @@ pub mod FLEXRAM_CTRL { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 6; - pub const mask: u32 = 0x03ff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "OCRAM Pipeline Status register"] pub mod OCRAM_PIPELINE_STATUS { @@ -1618,12 +1490,4 @@ pub mod OCRAM_PIPELINE_STATUS { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED { - pub const offset: u32 = 4; - pub const mask: u32 = 0x0fff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } diff --git a/src/blocks/imxrt1176_cm4/usbphy.rs b/src/blocks/imxrt1176_cm4/usbphy.rs index 8cf8a7d9f120..3d5f117fe55e 100644 --- a/src/blocks/imxrt1176_cm4/usbphy.rs +++ b/src/blocks/imxrt1176_cm4/usbphy.rs @@ -218,7 +218,7 @@ pub mod PWD { } #[doc = "USB PHY Power-Down Register"] pub mod PWD_SET { - #[doc = "TXPWDFS"] + #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; pub const mask: u32 = 0x01 << offset; @@ -226,7 +226,7 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "TXPWDIBIAS"] + #[doc = "0 = Normal operation"] pub mod TXPWDIBIAS { pub const offset: u32 = 11; pub const mask: u32 = 0x01 << offset; @@ -234,7 +234,7 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "TXPWDV2I"] + #[doc = "0 = Normal operation"] pub mod TXPWDV2I { pub const offset: u32 = 12; pub const mask: u32 = 0x01 << offset; @@ -242,7 +242,7 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "RXPWDENV"] + #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; pub const mask: u32 = 0x01 << offset; @@ -250,7 +250,7 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "RXPWD1PT1"] + #[doc = "0 = Normal operation"] pub mod RXPWD1PT1 { pub const offset: u32 = 18; pub const mask: u32 = 0x01 << offset; @@ -258,7 +258,7 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "RXPWDDIFF"] + #[doc = "0 = Normal operation"] pub mod RXPWDDIFF { pub const offset: u32 = 19; pub const mask: u32 = 0x01 << offset; @@ -266,7 +266,7 @@ pub mod PWD_SET { pub mod W {} pub mod RW {} } - #[doc = "RXPWDRX"] + #[doc = "0 = Normal operation"] pub mod RXPWDRX { pub const offset: u32 = 20; pub const mask: u32 = 0x01 << offset; @@ -277,7 +277,7 @@ pub mod PWD_SET { } #[doc = "USB PHY Power-Down Register"] pub mod PWD_CLR { - #[doc = "TXPWDFS"] + #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; pub const mask: u32 = 0x01 << offset; @@ -285,7 +285,7 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "TXPWDIBIAS"] + #[doc = "0 = Normal operation"] pub mod TXPWDIBIAS { pub const offset: u32 = 11; pub const mask: u32 = 0x01 << offset; @@ -293,7 +293,7 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "TXPWDV2I"] + #[doc = "0 = Normal operation"] pub mod TXPWDV2I { pub const offset: u32 = 12; pub const mask: u32 = 0x01 << offset; @@ -301,7 +301,7 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "RXPWDENV"] + #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; pub const mask: u32 = 0x01 << offset; @@ -309,7 +309,7 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "RXPWD1PT1"] + #[doc = "0 = Normal operation"] pub mod RXPWD1PT1 { pub const offset: u32 = 18; pub const mask: u32 = 0x01 << offset; @@ -317,7 +317,7 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "RXPWDDIFF"] + #[doc = "0 = Normal operation"] pub mod RXPWDDIFF { pub const offset: u32 = 19; pub const mask: u32 = 0x01 << offset; @@ -325,7 +325,7 @@ pub mod PWD_CLR { pub mod W {} pub mod RW {} } - #[doc = "RXPWDRX"] + #[doc = "0 = Normal operation"] pub mod RXPWDRX { pub const offset: u32 = 20; pub const mask: u32 = 0x01 << offset; @@ -336,7 +336,7 @@ pub mod PWD_CLR { } #[doc = "USB PHY Power-Down Register"] pub mod PWD_TOG { - #[doc = "TXPWDFS"] + #[doc = "0 = Normal operation"] pub mod TXPWDFS { pub const offset: u32 = 10; pub const mask: u32 = 0x01 << offset; @@ -344,7 +344,7 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "TXPWDIBIAS"] + #[doc = "0 = Normal operation"] pub mod TXPWDIBIAS { pub const offset: u32 = 11; pub const mask: u32 = 0x01 << offset; @@ -352,7 +352,7 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "TXPWDV2I"] + #[doc = "0 = Normal operation"] pub mod TXPWDV2I { pub const offset: u32 = 12; pub const mask: u32 = 0x01 << offset; @@ -360,7 +360,7 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "RXPWDENV"] + #[doc = "0 = Normal operation"] pub mod RXPWDENV { pub const offset: u32 = 17; pub const mask: u32 = 0x01 << offset; @@ -368,7 +368,7 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "RXPWD1PT1"] + #[doc = "0 = Normal operation"] pub mod RXPWD1PT1 { pub const offset: u32 = 18; pub const mask: u32 = 0x01 << offset; @@ -376,7 +376,7 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "RXPWDDIFF"] + #[doc = "0 = Normal operation"] pub mod RXPWDDIFF { pub const offset: u32 = 19; pub const mask: u32 = 0x01 << offset; @@ -384,7 +384,7 @@ pub mod PWD_TOG { pub mod W {} pub mod RW {} } - #[doc = "RXPWDRX"] + #[doc = "0 = Normal operation"] pub mod RXPWDRX { pub const offset: u32 = 20; pub const mask: u32 = 0x01 << offset; @@ -560,7 +560,7 @@ pub mod RX { } #[doc = "USB PHY Receiver Control Register"] pub mod RX_SET { - #[doc = "ENVADJ"] + #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"] pub mod ENVADJ { pub const offset: u32 = 0; pub const mask: u32 = 0x07 << offset; @@ -568,7 +568,7 @@ pub mod RX_SET { pub mod W {} pub mod RW {} } - #[doc = "DISCONADJ"] + #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; pub const mask: u32 = 0x07 << offset; @@ -576,7 +576,7 @@ pub mod RX_SET { pub mod W {} pub mod RW {} } - #[doc = "RXDBYPASS"] + #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; pub const mask: u32 = 0x01 << offset; @@ -587,7 +587,7 @@ pub mod RX_SET { } #[doc = "USB PHY Receiver Control Register"] pub mod RX_CLR { - #[doc = "ENVADJ"] + #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"] pub mod ENVADJ { pub const offset: u32 = 0; pub const mask: u32 = 0x07 << offset; @@ -595,7 +595,7 @@ pub mod RX_CLR { pub mod W {} pub mod RW {} } - #[doc = "DISCONADJ"] + #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; pub const mask: u32 = 0x07 << offset; @@ -603,7 +603,7 @@ pub mod RX_CLR { pub mod W {} pub mod RW {} } - #[doc = "RXDBYPASS"] + #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; pub const mask: u32 = 0x01 << offset; @@ -614,7 +614,7 @@ pub mod RX_CLR { } #[doc = "USB PHY Receiver Control Register"] pub mod RX_TOG { - #[doc = "ENVADJ"] + #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"] pub mod ENVADJ { pub const offset: u32 = 0; pub const mask: u32 = 0x07 << offset; @@ -622,7 +622,7 @@ pub mod RX_TOG { pub mod W {} pub mod RW {} } - #[doc = "DISCONADJ"] + #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"] pub mod DISCONADJ { pub const offset: u32 = 4; pub const mask: u32 = 0x07 << offset; @@ -630,7 +630,7 @@ pub mod RX_TOG { pub mod W {} pub mod RW {} } - #[doc = "RXDBYPASS"] + #[doc = "0 = Normal operation"] pub mod RXDBYPASS { pub const offset: u32 = 22; pub const mask: u32 = 0x01 << offset; @@ -1631,7 +1631,7 @@ pub mod STATUS { } #[doc = "USB PHY Debug Register"] pub mod DEBUG { - #[doc = "OTGIDPIOLOCK"] + #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"] pub mod OTGIDPIOLOCK { pub const offset: u32 = 0; pub const mask: u32 = 0x01 << offset; @@ -1639,7 +1639,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "DEBUG_INTERFACE_HOLD"] + #[doc = "Use holding registers to assist in timing for external UTMI interface."] pub mod DEBUG_INTERFACE_HOLD { pub const offset: u32 = 1; pub const mask: u32 = 0x01 << offset; @@ -1647,7 +1647,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "HSTPULLDOWN"] + #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"] pub mod HSTPULLDOWN { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -1655,7 +1655,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "ENHSTPULLDOWN"] + #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"] pub mod ENHSTPULLDOWN { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -1663,7 +1663,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "TX2RXCOUNT"] + #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; pub const mask: u32 = 0x0f << offset; @@ -1671,7 +1671,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "ENTX2RXCOUNT"] + #[doc = "Set this bit to allow a countdown to transition in between TX and RX."] pub mod ENTX2RXCOUNT { pub const offset: u32 = 12; pub const mask: u32 = 0x01 << offset; @@ -1679,7 +1679,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "SQUELCHRESETCOUNT"] + #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; pub const mask: u32 = 0x1f << offset; @@ -1687,7 +1687,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "ENSQUELCHRESET"] + #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; pub const mask: u32 = 0x01 << offset; @@ -1695,7 +1695,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "SQUELCHRESETLENGTH"] + #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."] pub mod SQUELCHRESETLENGTH { pub const offset: u32 = 25; pub const mask: u32 = 0x0f << offset; @@ -1703,7 +1703,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "HOST_RESUME_DEBUG"] + #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."] pub mod HOST_RESUME_DEBUG { pub const offset: u32 = 29; pub const mask: u32 = 0x01 << offset; @@ -1711,7 +1711,7 @@ pub mod DEBUG { pub mod W {} pub mod RW {} } - #[doc = "CLKGATE"] + #[doc = "Gate Test Clocks"] pub mod CLKGATE { pub const offset: u32 = 30; pub const mask: u32 = 0x01 << offset; @@ -1722,7 +1722,7 @@ pub mod DEBUG { } #[doc = "USB PHY Debug Register"] pub mod DEBUG_SET { - #[doc = "OTGIDPIOLOCK"] + #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"] pub mod OTGIDPIOLOCK { pub const offset: u32 = 0; pub const mask: u32 = 0x01 << offset; @@ -1730,7 +1730,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "DEBUG_INTERFACE_HOLD"] + #[doc = "Use holding registers to assist in timing for external UTMI interface."] pub mod DEBUG_INTERFACE_HOLD { pub const offset: u32 = 1; pub const mask: u32 = 0x01 << offset; @@ -1738,7 +1738,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "HSTPULLDOWN"] + #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"] pub mod HSTPULLDOWN { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -1746,7 +1746,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "ENHSTPULLDOWN"] + #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"] pub mod ENHSTPULLDOWN { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -1754,7 +1754,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "TX2RXCOUNT"] + #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; pub const mask: u32 = 0x0f << offset; @@ -1762,7 +1762,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "ENTX2RXCOUNT"] + #[doc = "Set this bit to allow a countdown to transition in between TX and RX."] pub mod ENTX2RXCOUNT { pub const offset: u32 = 12; pub const mask: u32 = 0x01 << offset; @@ -1770,7 +1770,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "SQUELCHRESETCOUNT"] + #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; pub const mask: u32 = 0x1f << offset; @@ -1778,7 +1778,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "ENSQUELCHRESET"] + #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; pub const mask: u32 = 0x01 << offset; @@ -1786,7 +1786,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "SQUELCHRESETLENGTH"] + #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."] pub mod SQUELCHRESETLENGTH { pub const offset: u32 = 25; pub const mask: u32 = 0x0f << offset; @@ -1794,7 +1794,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "HOST_RESUME_DEBUG"] + #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."] pub mod HOST_RESUME_DEBUG { pub const offset: u32 = 29; pub const mask: u32 = 0x01 << offset; @@ -1802,7 +1802,7 @@ pub mod DEBUG_SET { pub mod W {} pub mod RW {} } - #[doc = "CLKGATE"] + #[doc = "Gate Test Clocks"] pub mod CLKGATE { pub const offset: u32 = 30; pub const mask: u32 = 0x01 << offset; @@ -1813,7 +1813,7 @@ pub mod DEBUG_SET { } #[doc = "USB PHY Debug Register"] pub mod DEBUG_CLR { - #[doc = "OTGIDPIOLOCK"] + #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"] pub mod OTGIDPIOLOCK { pub const offset: u32 = 0; pub const mask: u32 = 0x01 << offset; @@ -1821,7 +1821,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "DEBUG_INTERFACE_HOLD"] + #[doc = "Use holding registers to assist in timing for external UTMI interface."] pub mod DEBUG_INTERFACE_HOLD { pub const offset: u32 = 1; pub const mask: u32 = 0x01 << offset; @@ -1829,7 +1829,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "HSTPULLDOWN"] + #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"] pub mod HSTPULLDOWN { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -1837,7 +1837,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "ENHSTPULLDOWN"] + #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"] pub mod ENHSTPULLDOWN { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -1845,7 +1845,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "TX2RXCOUNT"] + #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; pub const mask: u32 = 0x0f << offset; @@ -1853,7 +1853,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "ENTX2RXCOUNT"] + #[doc = "Set this bit to allow a countdown to transition in between TX and RX."] pub mod ENTX2RXCOUNT { pub const offset: u32 = 12; pub const mask: u32 = 0x01 << offset; @@ -1861,7 +1861,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "SQUELCHRESETCOUNT"] + #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; pub const mask: u32 = 0x1f << offset; @@ -1869,7 +1869,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "ENSQUELCHRESET"] + #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; pub const mask: u32 = 0x01 << offset; @@ -1877,7 +1877,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "SQUELCHRESETLENGTH"] + #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."] pub mod SQUELCHRESETLENGTH { pub const offset: u32 = 25; pub const mask: u32 = 0x0f << offset; @@ -1885,7 +1885,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "HOST_RESUME_DEBUG"] + #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."] pub mod HOST_RESUME_DEBUG { pub const offset: u32 = 29; pub const mask: u32 = 0x01 << offset; @@ -1893,7 +1893,7 @@ pub mod DEBUG_CLR { pub mod W {} pub mod RW {} } - #[doc = "CLKGATE"] + #[doc = "Gate Test Clocks"] pub mod CLKGATE { pub const offset: u32 = 30; pub const mask: u32 = 0x01 << offset; @@ -1904,7 +1904,7 @@ pub mod DEBUG_CLR { } #[doc = "USB PHY Debug Register"] pub mod DEBUG_TOG { - #[doc = "OTGIDPIOLOCK"] + #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"] pub mod OTGIDPIOLOCK { pub const offset: u32 = 0; pub const mask: u32 = 0x01 << offset; @@ -1912,7 +1912,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "DEBUG_INTERFACE_HOLD"] + #[doc = "Use holding registers to assist in timing for external UTMI interface."] pub mod DEBUG_INTERFACE_HOLD { pub const offset: u32 = 1; pub const mask: u32 = 0x01 << offset; @@ -1920,7 +1920,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "HSTPULLDOWN"] + #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"] pub mod HSTPULLDOWN { pub const offset: u32 = 2; pub const mask: u32 = 0x03 << offset; @@ -1928,7 +1928,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "ENHSTPULLDOWN"] + #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"] pub mod ENHSTPULLDOWN { pub const offset: u32 = 4; pub const mask: u32 = 0x03 << offset; @@ -1936,7 +1936,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "TX2RXCOUNT"] + #[doc = "Delay in between the end of transmit to the beginning of receive"] pub mod TX2RXCOUNT { pub const offset: u32 = 8; pub const mask: u32 = 0x0f << offset; @@ -1944,7 +1944,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "ENTX2RXCOUNT"] + #[doc = "Set this bit to allow a countdown to transition in between TX and RX."] pub mod ENTX2RXCOUNT { pub const offset: u32 = 12; pub const mask: u32 = 0x01 << offset; @@ -1952,7 +1952,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "SQUELCHRESETCOUNT"] + #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."] pub mod SQUELCHRESETCOUNT { pub const offset: u32 = 16; pub const mask: u32 = 0x1f << offset; @@ -1960,7 +1960,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "ENSQUELCHRESET"] + #[doc = "Set bit to allow squelch to reset high-speed receive."] pub mod ENSQUELCHRESET { pub const offset: u32 = 24; pub const mask: u32 = 0x01 << offset; @@ -1968,7 +1968,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "SQUELCHRESETLENGTH"] + #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."] pub mod SQUELCHRESETLENGTH { pub const offset: u32 = 25; pub const mask: u32 = 0x0f << offset; @@ -1976,7 +1976,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "HOST_RESUME_DEBUG"] + #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."] pub mod HOST_RESUME_DEBUG { pub const offset: u32 = 29; pub const mask: u32 = 0x01 << offset; @@ -1984,7 +1984,7 @@ pub mod DEBUG_TOG { pub mod W {} pub mod RW {} } - #[doc = "CLKGATE"] + #[doc = "Gate Test Clocks"] pub mod CLKGATE { pub const offset: u32 = 30; pub const mask: u32 = 0x01 << offset; diff --git a/src/blocks/imxrt1176_cm4/xecc_flexspi.rs b/src/blocks/imxrt1176_cm4/xecc_flexspi.rs index fcf94e721f4f..02120d13cf38 100644 --- a/src/blocks/imxrt1176_cm4/xecc_flexspi.rs +++ b/src/blocks/imxrt1176_cm4/xecc_flexspi.rs @@ -131,14 +131,6 @@ pub mod ERR_STATUS { pub const MULTI_ERR_1: u32 = 0x01; } } - #[doc = "Reserved"] - pub mod RESERVED1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x3fff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Error Interrupt Status Enable Register"] pub mod ERR_STAT_EN { @@ -168,14 +160,6 @@ pub mod ERR_STAT_EN { pub const MULIT_ERR_STAT_EN_1: u32 = 0x01; } } - #[doc = "Reserved"] - pub mod RESERVED1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x3fff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Error Interrupt Enable Register"] pub mod ERR_SIG_EN { @@ -205,14 +189,6 @@ pub mod ERR_SIG_EN { pub const MULTI_ERR_SIG_EN_1: u32 = 0x01; } } - #[doc = "Reserved"] - pub mod RESERVED1 { - pub const offset: u32 = 2; - pub const mask: u32 = 0x3fff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Error Injection On Write Data"] pub mod ERR_DATA_INJ { @@ -290,14 +266,6 @@ pub mod SINGLE_ERR_BIT_FIELD { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED1 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x00ff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "Multiple Error Address"] pub mod MULTI_ERR_ADDR { @@ -342,14 +310,6 @@ pub mod MULTI_ERR_BIT_FIELD { pub mod W {} pub mod RW {} } - #[doc = "Reserved"] - pub mod RESERVED1 { - pub const offset: u32 = 8; - pub const mask: u32 = 0x00ff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } } #[doc = "ECC Region 0 Base Address"] pub mod ECC_BASE_ADDR0 { diff --git a/src/blocks/imxrt1176_cm7/system_control.rs b/src/blocks/imxrt1176_cm7/system_control.rs index 6723a663bcb9..f2624aea8d79 100644 --- a/src/blocks/imxrt1176_cm7/system_control.rs +++ b/src/blocks/imxrt1176_cm7/system_control.rs @@ -1176,19 +1176,6 @@ pub mod HFSR { pub const FORCED_1: u32 = 0x01; } } - #[doc = "Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable."] - pub mod DEBUGEVT { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No Debug event has occurred."] - pub const DEBUGEVT_0: u32 = 0; - #[doc = "Debug event has occurred. The Debug Fault Status Register has been updated."] - pub const DEBUGEVT_1: u32 = 0x01; - } - } } #[doc = "Debug Fault Status Register"] pub mod DFSR { From 34a15ac1e9b4aeef55ade45621723e5bd12ac432 Mon Sep 17 00:00:00 2001 From: Ian McIntyre Date: Sun, 21 May 2023 14:12:00 -0400 Subject: [PATCH 2/5] Add "never combine" configuration for combiner Supply a regex that matches an IR path. If the combiner matches that path, it always signals "not equivalent." This prevents the combiner from combining the element. Apply the configuration to CCM CCGR registers. This fixes the documentation that would not be fixed by the previous commit (it's a superficial documentation change, but nevertheless a good test that the "never combine" behavior is working). --- raltool-cfg.yaml | 8 +++++ raltool/src/combine.rs | 70 +++++++++++++++++++++++++++++++++++-- src/blocks/imxrt1051/ccm.rs | 2 +- src/blocks/imxrt1061/ccm.rs | 6 ++-- 4 files changed, 79 insertions(+), 7 deletions(-) diff --git a/raltool-cfg.yaml b/raltool-cfg.yaml index 65a99f0c1dbd..07675e1f9e8a 100644 --- a/raltool-cfg.yaml +++ b/raltool-cfg.yaml @@ -187,3 +187,11 @@ combines: - iomuxc - iomuxc_gpr - iomuxc_snvs + # IR paths that should never be combined. + # + # These regexes match IR paths. If there's a match, that element is *never* considered for + # combination by the combiner. When applied to blocks, this is a stronger "never combine" + # guarantee than StrictEnumNames. In particular, if an IOMUXC block were in this list, this + # would prevent the 1061 IOMUXC from being combined with the 1062 IOMUXC. + - NeverCombine: + - ccm::regs::Ccgr\d+ diff --git a/raltool/src/combine.rs b/raltool/src/combine.rs index e7744c58623a..7631b04e9e9b 100644 --- a/raltool/src/combine.rs +++ b/raltool/src/combine.rs @@ -1,6 +1,7 @@ //! Helper types to combine and consolidate IRs across devices. use crate::ir; +use regex::Regex; use serde::{Deserialize, Serialize}; use std::{ cmp::Ordering, @@ -103,6 +104,30 @@ where } } +/// Equivalence adapter for checking paths against a set of regexes. +/// +/// If there's a regex match, the element is deemed "never equivalent". +/// This check happens before calling the wrapped equivalence. +struct PathExcluded<'a, Equiv> { + exclusions: &'a [Regex], + equiv: Equiv, +} + +impl Equivalence for PathExcluded<'_, Equiv> +where + Equiv: Equivalence, +{ + fn compare(&self, left: CompareIr, right: CompareIr, path: IrPath) -> bool { + for exclusion in self.exclusions { + if exclusion.is_match(path) { + return false; + } + } + + self.equiv.compare(left, right, path) + } +} + /// Ensure the items in two, possibly non-sorted contiguous /// collections are equivalent. fn equivalent_slices(xs: &[E], ys: &[E], equiv: impl Fn(&E, &E) -> bool) -> bool { @@ -317,15 +342,44 @@ pub struct IrVersions<'ir> { impl<'ir> IrVersions<'ir> { /// Define versions of IR elements from the collection of IRs. pub fn from_irs(irs: &'ir [ir::IR], config: &Config) -> Self { + let exclusions: Vec<_> = config + .never_combine + .iter() + .map(|path| Regex::new(&path).unwrap()) + .collect(); + let exclusions = &exclusions; + let enums = EquivalentEnums { peripherals: &config.strict_enum_names, }; let fieldsets = EquivalentFieldSets { enums }; let blocks = EquivalentBlocks { fieldsets }; + Self { - enums: VersionLookup::from_irs(enums, irs, |ir| &ir.enums), - fieldsets: VersionLookup::from_irs(fieldsets, irs, |ir| &ir.fieldsets), - blocks: VersionLookup::from_irs(blocks, irs, |ir| &ir.blocks), + enums: VersionLookup::from_irs( + PathExcluded { + exclusions, + equiv: enums, + }, + irs, + |ir| &ir.enums, + ), + fieldsets: VersionLookup::from_irs( + PathExcluded { + exclusions, + equiv: fieldsets, + }, + irs, + |ir| &ir.fieldsets, + ), + blocks: VersionLookup::from_irs( + PathExcluded { + exclusions, + equiv: blocks, + }, + irs, + |ir| &ir.blocks, + ), } } /// Access an enum version that corresponds to this IR. @@ -372,6 +426,7 @@ type RefMap<'a, K, V> = HashMap, V>; #[derive(Default)] pub struct Config { strict_enum_names: HashSet, + never_combine: HashSet, } /// Combine all IRs into a single IR. @@ -537,6 +592,12 @@ pub enum Combine { /// always safe to add to this list; however, it means there may be more /// code generated. StrictEnumNames(Vec), + /// The list of patterns (regex string) to never combine. + /// + /// You should design patterns to the IR path names. Note that, unlike + /// transform regexes, these do not implicitly match only starting + /// characters. + NeverCombine(Vec), } impl From for Config @@ -551,6 +612,9 @@ where Combine::StrictEnumNames(peripherals) => { config.strict_enum_names.extend(peripherals); } + Combine::NeverCombine(paths) => { + config.never_combine.extend(paths); + } } } diff --git a/src/blocks/imxrt1051/ccm.rs b/src/blocks/imxrt1051/ccm.rs index 1c02b4241055..7311625bf8a1 100644 --- a/src/blocks/imxrt1051/ccm.rs +++ b/src/blocks/imxrt1051/ccm.rs @@ -2708,7 +2708,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "sim_m_clk_r_clk_enable"] + #[doc = "sim_m or sim_main register access clock (sim_m_mainclk_r_enable)"] pub mod CG4 { pub const offset: u32 = 8; pub const mask: u32 = 0x03 << offset; diff --git a/src/blocks/imxrt1061/ccm.rs b/src/blocks/imxrt1061/ccm.rs index f3d3a0bd44f3..bf4c7d3938bf 100644 --- a/src/blocks/imxrt1061/ccm.rs +++ b/src/blocks/imxrt1061/ccm.rs @@ -2749,7 +2749,7 @@ pub mod CCGR0 { pub mod W {} pub mod RW {} } - #[doc = "sim_m_clk_r_clk_enable"] + #[doc = "sim_m or sim_main register access clock (sim_m_mainclk_r_enable)"] pub mod CG4 { pub const offset: u32 = 8; pub const mask: u32 = 0x03 << offset; @@ -3214,7 +3214,7 @@ pub mod CCGR3 { pub mod W {} pub mod RW {} } - #[doc = "ocram clock (ocram_clk_enable)"] + #[doc = "The OCRAM clock cannot be turned off when the CM cache is running on this device."] pub mod CG14 { pub const offset: u32 = 28; pub const mask: u32 = 0x03 << offset; @@ -3575,7 +3575,7 @@ pub mod CCGR6 { pub mod W {} pub mod RW {} } - #[doc = "sim_per clock (sim_per_clk_enable)"] + #[doc = "sim_axbs_p_clk_enable"] pub mod CG10 { pub const offset: u32 = 20; pub const mask: u32 = 0x03 << offset; From 835fbfbc03d935af5308ca19b8c6ec57b4b702a3 Mon Sep 17 00:00:00 2001 From: Ian McIntyre Date: Sun, 21 May 2023 16:40:59 -0400 Subject: [PATCH 3/5] Add raltool config for strict enum descriptions Similar to strict enum names, this configuration instructs the combiner to compare enum variant descriptions, the human-readable strings associated with items. If they're not equal, then the enums cannot be combined. When applied to IOMUXC peripherals, this ensures that the documentation associated with each enum variant is correct. The next commit checks in the updates. --- raltool-cfg.yaml | 4 ++++ raltool/src/combine.rs | 23 +++++++++++++++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/raltool-cfg.yaml b/raltool-cfg.yaml index 07675e1f9e8a..0eeca9dc0c25 100644 --- a/raltool-cfg.yaml +++ b/raltool-cfg.yaml @@ -187,6 +187,10 @@ combines: - iomuxc - iomuxc_gpr - iomuxc_snvs + - StrictEnumDescs: + - iomuxc + - iomuxc_gpr + - iomuxc_snvs # IR paths that should never be combined. # # These regexes match IR paths. If there's a match, that element is *never* considered for diff --git a/raltool/src/combine.rs b/raltool/src/combine.rs index 7631b04e9e9b..9a44af016f0a 100644 --- a/raltool/src/combine.rs +++ b/raltool/src/combine.rs @@ -149,7 +149,8 @@ fn equivalent_options( #[derive(Clone, Copy)] struct EquivalentEnums<'a> { - peripherals: &'a HashSet, + names: &'a HashSet, + descs: &'a HashSet, } impl Equivalence for EquivalentEnums<'_> { @@ -159,10 +160,13 @@ impl Equivalence for EquivalentEnums<'_> { CompareIr { elem: b, .. }: CompareIr, path: IrPath, ) -> bool { - let assert_name_equivalence = self.peripherals.contains(peripheral_part(path)); + let assert_name_equivalence = self.names.contains(peripheral_part(path)); + let assert_desc_equivalence = self.descs.contains(peripheral_part(path)); a.bit_size == b.bit_size && equivalent_slices(&a.variants, &b.variants, |q, r| { - q.value == r.value && (!assert_name_equivalence || q.name == r.name) + q.value == r.value + && (!assert_name_equivalence || q.name == r.name) + && (!assert_desc_equivalence || q.description == r.description) }) } } @@ -350,7 +354,8 @@ impl<'ir> IrVersions<'ir> { let exclusions = &exclusions; let enums = EquivalentEnums { - peripherals: &config.strict_enum_names, + names: &config.strict_enum_names, + descs: &config.strict_enum_descs, }; let fieldsets = EquivalentFieldSets { enums }; let blocks = EquivalentBlocks { fieldsets }; @@ -426,6 +431,7 @@ type RefMap<'a, K, V> = HashMap, V>; #[derive(Default)] pub struct Config { strict_enum_names: HashSet, + strict_enum_descs: HashSet, never_combine: HashSet, } @@ -592,6 +598,12 @@ pub enum Combine { /// always safe to add to this list; however, it means there may be more /// code generated. StrictEnumNames(Vec), + /// The list of peripheral names that require strict enum description + /// checks. + /// + /// This is even stricter than [`StrictEnumNames`], since it asserts + /// equal descriptions (human-readable descriptions) for each enum variant. + StrictEnumDescs(Vec), /// The list of patterns (regex string) to never combine. /// /// You should design patterns to the IR path names. Note that, unlike @@ -612,6 +624,9 @@ where Combine::StrictEnumNames(peripherals) => { config.strict_enum_names.extend(peripherals); } + Combine::StrictEnumDescs(peripherals) => { + config.strict_enum_descs.extend(peripherals); + } Combine::NeverCombine(paths) => { config.never_combine.extend(paths); } From 7a201567828da55b935304dab2fdb0b081d1d5d5 Mon Sep 17 00:00:00 2001 From: Ian McIntyre Date: Sun, 21 May 2023 16:43:32 -0400 Subject: [PATCH 4/5] Update IOMUXC enum variant documentation Briefly spot-checked the 1061 IOMUXC to make sure the diff of some registers are correct. See the parent commit for context. --- CHANGELOG.md | 2 + src/blocks/imxrt1015/iomuxc_gpr.rs | 8 +- src/blocks/imxrt1015/iomuxc_snvs.rs | 2 +- src/blocks/imxrt1021/iomuxc.rs | 6 +- src/blocks/imxrt1021/iomuxc_gpr.rs | 24 +- src/blocks/imxrt1021/iomuxc_snvs.rs | 2 +- src/blocks/imxrt1051/iomuxc.rs | 454 ++++++++++++++-------------- src/blocks/imxrt1051/iomuxc_gpr.rs | 46 +-- src/blocks/imxrt1061/iomuxc.rs | 182 +++++------ src/blocks/imxrt1061/iomuxc_gpr.rs | 36 +-- src/blocks/imxrt1064/iomuxc.rs | 194 ++++++------ 11 files changed, 479 insertions(+), 477 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 9bab8dff2c5b..8c57eb83541e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -53,6 +53,8 @@ description, all lowercase). Dropping these fields changes the combiner's approach for combining fieldsets, enabling correct documentation for non- reserved fields. +Fix the documentation associated with IOMUXC field values. + ## [0.5.0] 2022-12-27 Add support for NXP's i.MX RT 1176 dual-core MCUs. An `"imxrt1176_cm7"` feature diff --git a/src/blocks/imxrt1015/iomuxc_gpr.rs b/src/blocks/imxrt1015/iomuxc_gpr.rs index e37ed2995c6b..48240243d2ad 100644 --- a/src/blocks/imxrt1015/iomuxc_gpr.rs +++ b/src/blocks/imxrt1015/iomuxc_gpr.rs @@ -845,16 +845,16 @@ pub mod GPR2 { } #[doc = "GPR3 General Purpose Register"] pub mod GPR3 { - #[doc = "Select 128-bit DCP key from 256-bit key from SNVS Master Key"] + #[doc = "Select 128-bit DCP key from 256-bit key from SNVS/OCOTP"] pub mod DCP_KEY_SEL { pub const offset: u32 = 4; pub const mask: u32 = 0x01 << offset; pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select \\[127:0\\] from SNVS Master Key as DCP key"] + #[doc = "Select \\[127:0\\] from SNVS/OCOTP key as DCP key"] pub const DCP_KEY_SEL_0: u32 = 0; - #[doc = "Select \\[255:128\\] from SNVS Master Key as DCP key"] + #[doc = "Select \\[255:128\\] from SNVS/OCOTP key as DCP key"] pub const DCP_KEY_SEL_1: u32 = 0x01; } } @@ -1871,7 +1871,7 @@ pub mod GPR10 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select key from SNVS Master Key."] + #[doc = "Select key from Key MUX (SNVS/OTPMK)."] pub const DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0; #[doc = "Select key from OCOTP (SW_GP2)."] pub const DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01; diff --git a/src/blocks/imxrt1015/iomuxc_snvs.rs b/src/blocks/imxrt1015/iomuxc_snvs.rs index da000980b5b1..713834d584a3 100644 --- a/src/blocks/imxrt1015/iomuxc_snvs.rs +++ b/src/blocks/imxrt1015/iomuxc_snvs.rs @@ -26,7 +26,7 @@ pub mod SW_MUX_CTL_PAD_PMIC_ON_REQ { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5"] + #[doc = "Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5"] pub const ALT5: u32 = 0x05; } } diff --git a/src/blocks/imxrt1021/iomuxc.rs b/src/blocks/imxrt1021/iomuxc.rs index af66a35f5001..5aa424378d7d 100644 --- a/src/blocks/imxrt1021/iomuxc.rs +++ b/src/blocks/imxrt1021/iomuxc.rs @@ -2254,7 +2254,7 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_00 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TMS of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: JTAG_TMS of instance: jtag_mux"] pub const ALT0: u32 = 0; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1"] pub const ALT5: u32 = 0x05; @@ -2285,7 +2285,7 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_01 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TCK of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: JTAG_TCK of instance: jtag_mux"] pub const ALT0: u32 = 0; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1"] pub const ALT5: u32 = 0x05; @@ -2316,7 +2316,7 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_02 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_MOD of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: JTAG_MOD of instance: jtag_mux"] pub const ALT0: u32 = 0; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1"] pub const ALT5: u32 = 0x05; diff --git a/src/blocks/imxrt1021/iomuxc_gpr.rs b/src/blocks/imxrt1021/iomuxc_gpr.rs index 4402d28fde32..c2b319ad8edb 100644 --- a/src/blocks/imxrt1021/iomuxc_gpr.rs +++ b/src/blocks/imxrt1021/iomuxc_gpr.rs @@ -249,7 +249,7 @@ pub mod GPR1 { pub mod RW { #[doc = "OKAY response"] pub const EXC_MON_0: u32 = 0; - #[doc = "SLVError response"] + #[doc = "SLVError response (default)"] pub const EXC_MON_1: u32 = 0x01; } } @@ -273,9 +273,9 @@ pub mod GPR1 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible."] + #[doc = "AHB clock is not running (gated)"] pub const CM7_FORCE_HCLK_EN_0: u32 = 0; - #[doc = "AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible."] + #[doc = "AHB clock is running (enabled)"] pub const CM7_FORCE_HCLK_EN_1: u32 = 0x01; } } @@ -289,9 +289,9 @@ pub mod GPR2 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Enters power saving mode only when chip is in SUSPEND mode"] + #[doc = "none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect"] pub const L2_MEM_EN_POWERSAVING_0: u32 = 0; - #[doc = "Controlled by L2_MEM_DEEPSLEEP bitfield"] + #[doc = "memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels"] pub const L2_MEM_EN_POWERSAVING_1: u32 = 0x01; } } @@ -315,9 +315,9 @@ pub mod GPR2 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode)"] + #[doc = "no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode"] pub const L2_MEM_DEEPSLEEP_0: u32 = 0; - #[doc = "Force memory into deep sleep mode (OCRAM in power saving mode)"] + #[doc = "force memory into deep sleep mode"] pub const L2_MEM_DEEPSLEEP_1: u32 = 0x01; } } @@ -888,9 +888,9 @@ pub mod GPR2 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Timer counter works normally"] + #[doc = "timer counter work normally"] pub const QTIMER1_TMR_CNTS_FREEZE_0: u32 = 0; - #[doc = "Reset counter and ouput flags"] + #[doc = "reset counter and ouput flags"] pub const QTIMER1_TMR_CNTS_FREEZE_1: u32 = 0x01; } } @@ -925,9 +925,9 @@ pub mod GPR3 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select \\[127:0\\] from SNVS Master Key as DCP key"] + #[doc = "Select \\[127:0\\] from snvs/ocotp key as dcp key"] pub const DCP_KEY_SEL_0: u32 = 0; - #[doc = "Select \\[255:128\\] from SNVS Master Key as DCP key"] + #[doc = "Select \\[255:128\\] from snvs/ocotp key as dcp key"] pub const DCP_KEY_SEL_1: u32 = 0x01; } } @@ -2542,7 +2542,7 @@ pub mod GPR10 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select key from SNVS Master Key."] + #[doc = "Select key from Key MUX (SNVS/OTPMK)."] pub const DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0; #[doc = "Select key from OCOTP (SW_GP2)."] pub const DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01; diff --git a/src/blocks/imxrt1021/iomuxc_snvs.rs b/src/blocks/imxrt1021/iomuxc_snvs.rs index 2360c581cf8f..a7afeffeea74 100644 --- a/src/blocks/imxrt1021/iomuxc_snvs.rs +++ b/src/blocks/imxrt1021/iomuxc_snvs.rs @@ -60,7 +60,7 @@ pub mod SW_MUX_CTL_PAD_PMIC_ON_REQ { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5"] + #[doc = "Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5"] pub const ALT5: u32 = 0x05; } } diff --git a/src/blocks/imxrt1051/iomuxc.rs b/src/blocks/imxrt1051/iomuxc.rs index 9f8f9ba00ae5..d47aabf7973c 100644 --- a/src/blocks/imxrt1051/iomuxc.rs +++ b/src/blocks/imxrt1051/iomuxc.rs @@ -966,15 +966,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_04 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA04 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT04 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA02 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: SPDIF_OUT of instance: spdif"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO16 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO04 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1003,15 +1003,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_05 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA05 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT05 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB02 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: SPDIF_IN of instance: spdif"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO17 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO05 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1040,15 +1040,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_06 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA06 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT06 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_DATA of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO18 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO06 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1077,15 +1077,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_07 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA07 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT07 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_SYNC of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO19 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO07 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1114,15 +1114,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_08 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DM00 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT08 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: FLEXCAN2_TX of instance: flexcan2"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_DATA of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT17 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO20 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO08 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1149,17 +1149,17 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_09 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_WE of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT09 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: FLEXCAN2_RX of instance: flexcan2"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_BCLK of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO21 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO09 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1482,19 +1482,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_18 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB03 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: lpuart4"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO22 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: QTIMER3_TIMER3 of instance: qtimer3"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: src"] + #[doc = "Select mux mode: ALT6 mux port: SNVS_VIO_5_CTL of instance: snvs_hp"] pub const ALT6: u32 = 0x06; } } @@ -1521,19 +1521,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_19 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR03 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR11 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: ENET_RDATA01 of instance: enet"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO23 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: QTIMER2_TIMER0 of instance: qtimer2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: src"] + #[doc = "Select mux mode: ALT6 mux port: SNVS_VIO_5 of instance: snvs_hp"] pub const ALT6: u32 = 0x06; } } @@ -2041,17 +2041,17 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_33 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA09 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA11 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: QTIMER1_TIMER1 of instance: qtimer1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM3_PWMA02 of instance: flexpwm3"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART4_RX of instance: lpuart4"] + #[doc = "Select mux mode: ALT2 mux port: USDHC1_RESET_B of instance: usdhc1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: LPSPI4_PCS0 of instance: lpspi4"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA20 of instance: csi"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO19 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -2115,19 +2115,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_35 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA11 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA13 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: QTIMER1_TIMER3 of instance: qtimer1"] + #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT18 of instance: xbar1"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7"] + #[doc = "Select mux mode: ALT2 mux port: GPT1_COMPARE1 of instance: gpt1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: USDHC2_WP of instance: usdhc2"] + #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: sai3"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: LPSPI4_SDI of instance: lpspi4"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA18 of instance: csi"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ENET_COL of instance: enet"] + #[doc = "Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1"] pub const ALT6: u32 = 0x06; } } @@ -2511,21 +2511,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_03 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_TDI of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: FLEXCAN2_RX of instance: flexcan2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: USDHC2_CD_B of instance: usdhc2"] + #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: WDOG1_B of instance: wdog1"] + #[doc = "Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: usb"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: USDHC1_WP of instance: usdhc1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX01 of instance: flexpwm1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_OC of instance: usb"] + #[doc = "Select mux mode: ALT6 mux port: REF_CLK_24M of instance: anatop"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: CCM_PMIC_RDY of instance: ccm"] + #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS0 of instance: lpspi3"] pub const ALT7: u32 = 0x07; } } @@ -2552,21 +2552,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_04 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_TDO of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: src"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXCAN1_TX of instance: flexcan1"] + #[doc = "Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: USDHC1_WP of instance: usdhc1"] + #[doc = "Select mux mode: ALT2 mux port: ENET_TX_DATA03 of instance: enet"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: QTIMER2_TIMER0 of instance: qtimer2"] + #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: ENET_MDIO of instance: enet"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_PWR of instance: usb"] + #[doc = "Select mux mode: ALT6 mux port: PIT_TRIGGER00 of instance: pit"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: EWM_OUT_B of instance: ewm"] + #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS1 of instance: lpspi3"] pub const ALT7: u32 = 0x07; } } @@ -2593,21 +2593,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_05 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_TRSTB of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXCAN1_RX of instance: flexcan1"] + #[doc = "Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: USDHC1_CD_B of instance: usdhc1"] + #[doc = "Select mux mode: ALT2 mux port: ENET_TX_DATA02 of instance: enet"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: QTIMER2_TIMER1 of instance: qtimer2"] + #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: ENET_MDC of instance: enet"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_ID of instance: anatop"] + #[doc = "Select mux mode: ALT6 mux port: XBAR1_INOUT17 of instance: xbar1"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"] + #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS2 of instance: lpspi3"] pub const ALT7: u32 = 0x07; } } @@ -2880,21 +2880,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_12 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: ENET_RX_ER of instance: enet"] + #[doc = "Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: LPSPI1_SDO of instance: lpspi1"] + #[doc = "Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: KPP_COL02 of instance: kpp"] + #[doc = "Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2"] + #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ARM_CM7_TRACE00 of instance: cm7_mxrt"] + #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp"] + #[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"] pub const ALT7: u32 = 0x07; } } @@ -2921,21 +2921,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_13 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: ENET_TX_EN of instance: enet"] + #[doc = "Select mux mode: ALT0 mux port: LPI2C4_SDA of instance: lpi2c4"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: LPSPI1_SDI of instance: lpspi1"] + #[doc = "Select mux mode: ALT1 mux port: GPT1_CLK of instance: gpt1"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: LPUART1_RX of instance: lpuart1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: KPP_ROW02 of instance: kpp"] + #[doc = "Select mux mode: ALT3 mux port: EWM_OUT_B of instance: ewm"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2"] + #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX03 of instance: flexpwm1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ARM_CM7_TRACE01 of instance: cm7_mxrt"] + #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT1_IN of instance: enet"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: SNVS_HP_VIO_5_B of instance: snvs_hp"] + #[doc = "Select mux mode: ALT7 mux port: REF_CLK_24M of instance: anatop"] pub const ALT7: u32 = 0x07; } } @@ -3042,21 +3042,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_00 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_READY of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: USB_OTG2_ID of instance: anatop"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA03 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER0 of instance: qtimer3"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: FLEXCAN2_TX of instance: flexcan2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_CTS_B of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: LPI2C1_SCL of instance: lpi2c1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO15 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: WDOG1_B of instance: wdog1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO16 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT2_OUT of instance: enet"] + #[doc = "Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: KPP_COL04 of instance: kpp"] + #[doc = "Select mux mode: ALT7 mux port: KPP_ROW07 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -3083,21 +3083,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_01 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_CSX00 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: usb"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_SCLK of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: FLEXCAN2_RX of instance: flexcan2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: lpi2c1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO14 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: CCM_PMIC_READY of instance: ccm"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT2_IN of instance: enet"] + #[doc = "Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: KPP_ROW04 of instance: kpp"] + #[doc = "Select mux mode: ALT7 mux port: KPP_COL07 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -3124,21 +3124,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_02 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_CSX01 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: USB_OTG1_ID of instance: anatop"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA00 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER2 of instance: qtimer3"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPSPI4_SCK of instance: lpspi4"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO13 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: ENET_1588_EVENT2_OUT of instance: enet"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO18 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT3_OUT of instance: enet"] + #[doc = "Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: KPP_COL05 of instance: kpp"] + #[doc = "Select mux mode: ALT7 mux port: KPP_ROW06 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -3165,21 +3165,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_03 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_CSX02 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: USB_OTG1_OC of instance: usb"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA02 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER3 of instance: qtimer3"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPSPI4_PCS0 of instance: lpspi4"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO12 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: ENET_1588_EVENT2_IN of instance: enet"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO19 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT3_IN of instance: enet"] + #[doc = "Select mux mode: ALT6 mux port: USDHC2_CD_B of instance: usdhc2"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: KPP_ROW05 of instance: kpp"] + #[doc = "Select mux mode: ALT7 mux port: KPP_COL06 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -3206,21 +3206,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_04 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_CSX03 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: FLEXSPIB_DATA03 of instance: flexspi"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA01 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: ENET_MDC of instance: enet"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPSPI4_SDO of instance: lpspi4"] + #[doc = "Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: SPDIF_SR_CLK of instance: spdif"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO11 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: CSI_PIXCLK of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO20 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: LPSPI1_PCS1 of instance: lpspi1"] + #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA0 of instance: usdhc2"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: KPP_COL06 of instance: kpp"] + #[doc = "Select mux mode: ALT7 mux port: KPP_ROW05 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -3247,21 +3247,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_05 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC1_WP of instance: usdhc1"] + #[doc = "Select mux mode: ALT0 mux port: FLEXSPIB_DATA02 of instance: flexspi"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_SS0_B of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: ENET_MDIO of instance: enet"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPSPI4_SDI of instance: lpspi4"] + #[doc = "Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO10 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: CSI_MCLK of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: LPSPI1_PCS2 of instance: lpspi1"] + #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA1 of instance: usdhc2"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: KPP_ROW06 of instance: kpp"] + #[doc = "Select mux mode: ALT7 mux port: KPP_COL05 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -3288,21 +3288,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_06 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC1_RESET_B of instance: usdhc1"] + #[doc = "Select mux mode: ALT0 mux port: FLEXSPIB_DATA01 of instance: flexspi"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA00 of instance: flexpwm1"] + #[doc = "Select mux mode: ALT1 mux port: LPI2C3_SDA of instance: lpi2c3"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART2_CTS_B of instance: lpuart2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: SPDIF_LOCK of instance: spdif"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO09 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: CSI_VSYNC of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO22 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: LPSPI1_PCS3 of instance: lpspi1"] + #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA2 of instance: usdhc2"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: KPP_COL07 of instance: kpp"] + #[doc = "Select mux mode: ALT7 mux port: KPP_ROW04 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -3329,21 +3329,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_07 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC1_VSELECT of instance: usdhc1"] + #[doc = "Select mux mode: ALT0 mux port: FLEXSPIB_DATA00 of instance: flexspi"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB00 of instance: flexpwm1"] + #[doc = "Select mux mode: ALT1 mux port: LPI2C3_SCL of instance: lpi2c3"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: SPDIF_EXT_CLK of instance: spdif"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO08 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO23 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: LPSPI3_PCS3 of instance: lpspi3"] + #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA3 of instance: usdhc2"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: KPP_ROW07 of instance: kpp"] + #[doc = "Select mux mode: ALT7 mux port: KPP_COL04 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -3370,21 +3370,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_08 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: LPI2C2_SCL of instance: lpi2c2"] + #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_SS1_B of instance: flexspi"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA01 of instance: flexpwm1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2"] + #[doc = "Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: CCM_PMIC_READY of instance: ccm"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO07 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO24 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: LPSPI3_PCS2 of instance: lpspi3"] + #[doc = "Select mux mode: ALT6 mux port: USDHC2_CMD of instance: usdhc2"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: XBAR1_INOUT12 of instance: xbar1"] + #[doc = "Select mux mode: ALT7 mux port: KPP_ROW03 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -3411,21 +3411,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_09 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: LPI2C2_SDA of instance: lpi2c2"] + #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_DQS of instance: flexspi"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB01 of instance: flexpwm1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA01 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2"] + #[doc = "Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO06 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: LPSPI3_PCS1 of instance: lpspi3"] + #[doc = "Select mux mode: ALT6 mux port: USDHC2_CLK of instance: usdhc2"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: XBAR1_INOUT13 of instance: xbar1"] + #[doc = "Select mux mode: ALT7 mux port: KPP_COL03 of instance: kpp"] pub const ALT7: u32 = 0x07; } } @@ -5088,19 +5088,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B0_04 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: usdhc1"] + #[doc = "Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance: usdhc1"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXCAN2_TX of instance: flexcan2"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART7_TX of instance: lpuart7"] + #[doc = "Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_DATA of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: LPSPI1_SDO of instance: lpspi1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXSPIB_SS0_B of instance: flexspi"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO17 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO16 of instance: gpio3"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: FLEXSPI_B_SS0_B of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm"] pub const ALT6: u32 = 0x06; } } @@ -5127,19 +5127,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B0_05 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance: usdhc1"] + #[doc = "Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance: usdhc1"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXCAN2_RX of instance: flexcan2"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB02 of instance: flexpwm1"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7"] + #[doc = "Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: LPSPI1_SDI of instance: lpspi1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXSPIB_DQS of instance: flexspi"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO18 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO17 of instance: gpio3"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: FLEXSPI_B_DQS of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm"] pub const ALT6: u32 = 0x06; } } @@ -5166,17 +5166,17 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_00 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA2 of instance: usdhc2"] + #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA3 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_B_DATA03 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_DATA03 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART6_TX of instance: lpuart6"] + #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT10 of instance: xbar1"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXCAN1_TX of instance: flexcan1"] + #[doc = "Select mux mode: ALT4 mux port: LPUART4_TX of instance: lpuart4"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO20 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO00 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5203,17 +5203,17 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_01 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA3 of instance: usdhc2"] + #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA2 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_B_SCLK of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_DATA02 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6"] + #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: FLEXSPI_A_SS1_B of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXCAN1_RX of instance: flexcan1"] + #[doc = "Select mux mode: ALT4 mux port: LPUART4_RX of instance: lpuart4"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5240,19 +5240,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_02 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC2_CMD of instance: usdhc2"] + #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA1 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_B_DATA00 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_DATA01 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8"] + #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: LPI2C4_SCL of instance: lpi2c4"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: ENET_1588_EVENT1_OUT of instance: enet"] + #[doc = "Select mux mode: ALT4 mux port: FLEXCAN1_TX of instance: flexcan1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO22 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO02 of instance: gpio3"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm"] + #[doc = "Select mux mode: ALT6 mux port: CCM_WAIT of instance: ccm"] pub const ALT6: u32 = 0x06; } } @@ -5279,19 +5279,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_03 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC2_CLK of instance: usdhc2"] + #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA0 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_B_DATA02 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_DATA00 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8"] + #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: LPI2C4_SDA of instance: lpi2c4"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: ENET_1588_EVENT1_IN of instance: enet"] + #[doc = "Select mux mode: ALT4 mux port: FLEXCAN1_RX of instance: flexcan1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO23 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm"] + #[doc = "Select mux mode: ALT6 mux port: CCM_PMIC_READY of instance: ccm"] pub const ALT6: u32 = 0x06; } } @@ -5318,19 +5318,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_04 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA0 of instance: usdhc2"] + #[doc = "Select mux mode: ALT0 mux port: USDHC2_CLK of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_B_DATA01 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_SCLK of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TX_CLK of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPI2C1_SCL of instance: lpi2c1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: ENET_REF_CLK1 of instance: enet"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: EWM_OUT_B of instance: ewm"] + #[doc = "Select mux mode: ALT4 mux port: FLEXSPIA_SS1_B of instance: flexspi"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO24 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO04 of instance: gpio3"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: CCM_WAIT of instance: ccm"] + #[doc = "Select mux mode: ALT6 mux port: CCM_STOP of instance: ccm"] pub const ALT6: u32 = 0x06; } } @@ -5431,17 +5431,17 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_07 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance: usdhc2"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_CSX01 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_SCLK of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_SCLK of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_RX_EN of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART7_RTS_B of instance: lpuart7"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_SCK of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5509,15 +5509,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_09 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA5 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA02 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA01 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TX_EN of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_SDI of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO29 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5546,15 +5546,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_10 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA6 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA01 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA02 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TDATA00 of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: lpi2c2"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS2 of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO30 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5583,15 +5583,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_11 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA7 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_SS0_B of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA03 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TDATA01 of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: lpi2c2"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS3 of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO31 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } diff --git a/src/blocks/imxrt1051/iomuxc_gpr.rs b/src/blocks/imxrt1051/iomuxc_gpr.rs index f819422a9a2a..c451996b44dc 100644 --- a/src/blocks/imxrt1051/iomuxc_gpr.rs +++ b/src/blocks/imxrt1051/iomuxc_gpr.rs @@ -107,7 +107,7 @@ pub mod GPR1 { pub mod RW { #[doc = "ccm.spdif0_clk_root"] pub const SAI1_MCLK3_SEL_0: u32 = 0; - #[doc = "SPDIF_EXT_CLK"] + #[doc = "iomux.spdif_tx_clk2"] pub const SAI1_MCLK3_SEL_1: u32 = 0x01; #[doc = "spdif.spdif_srclk"] pub const SAI1_MCLK3_SEL_2: u32 = 0x02; @@ -124,7 +124,7 @@ pub mod GPR1 { pub mod RW { #[doc = "ccm.spdif0_clk_root"] pub const SAI2_MCLK3_SEL_0: u32 = 0; - #[doc = "SPDIF_EXT_CLK"] + #[doc = "iomux.spdif_tx_clk2"] pub const SAI2_MCLK3_SEL_1: u32 = 0x01; #[doc = "spdif.spdif_srclk"] pub const SAI2_MCLK3_SEL_2: u32 = 0x02; @@ -141,7 +141,7 @@ pub mod GPR1 { pub mod RW { #[doc = "ccm.spdif0_clk_root"] pub const SAI3_MCLK3_SEL_0: u32 = 0; - #[doc = "SPDIF_EXT_CLK"] + #[doc = "iomux.spdif_tx_clk2"] pub const SAI3_MCLK3_SEL_1: u32 = 0x01; #[doc = "spdif.spdif_srclk"] pub const SAI3_MCLK3_SEL_2: u32 = 0x02; @@ -149,7 +149,7 @@ pub mod GPR1 { pub const SAI3_MCLK3_SEL_3: u32 = 0x03; } } - #[doc = "Global interrupt bit (connected to ARM M7 IRQ#41)"] + #[doc = "Global interrupt bit (connected to ARM M7 IRQ#41 and GPC)"] pub mod GINT { pub const offset: u32 = 12; pub const mask: u32 = 0x01 << offset; @@ -169,7 +169,7 @@ pub mod GPR1 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "ENET1 TX reference clock driven by ref_enetpll."] + #[doc = "ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function."] pub const ENET1_CLK_SEL_0: u32 = 0; #[doc = "Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller."] pub const ENET1_CLK_SEL_1: u32 = 0x01; @@ -188,16 +188,16 @@ pub mod GPR1 { pub const USB_EXP_MODE_1: u32 = 0x01; } } - #[doc = "ENET1_TX_CLK data direction control"] + #[doc = "ENET1_TX_CLK data direction control when ENET_REF_CLK1 ALT is selected."] pub mod ENET1_TX_CLK_DIR { pub const offset: u32 = 17; pub const mask: u32 = 0x01 << offset; pub mod R {} pub mod W {} pub mod RW { - #[doc = "ENET1_TX_CLK output driver is disabled"] + #[doc = "ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input."] pub const ENET1_TX_CLK_DIR_0: u32 = 0; - #[doc = "ENET1_TX_CLK output driver is enabled"] + #[doc = "ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0."] pub const ENET1_TX_CLK_DIR_1: u32 = 0x01; } } @@ -273,9 +273,9 @@ pub mod GPR1 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible."] + #[doc = "AHB clock is not running (gated)"] pub const CM7_FORCE_HCLK_EN_0: u32 = 0; - #[doc = "AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible."] + #[doc = "AHB clock is running (enabled)"] pub const CM7_FORCE_HCLK_EN_1: u32 = 0x01; } } @@ -289,9 +289,9 @@ pub mod GPR2 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Enters power saving mode only when chip is in SUSPEND mode"] + #[doc = "none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect"] pub const L2_MEM_EN_POWERSAVING_0: u32 = 0; - #[doc = "Controlled by L2_MEM_DEEPSLEEP bitfield"] + #[doc = "memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels"] pub const L2_MEM_EN_POWERSAVING_1: u32 = 0x01; } } @@ -302,9 +302,9 @@ pub mod GPR2 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode)"] + #[doc = "no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode"] pub const L2_MEM_DEEPSLEEP_0: u32 = 0; - #[doc = "Force memory into deep sleep mode (OCRAM in power saving mode)"] + #[doc = "force memory into deep sleep mode"] pub const L2_MEM_DEEPSLEEP_1: u32 = 0x01; } } @@ -875,9 +875,9 @@ pub mod GPR2 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Timer counter works normally"] + #[doc = "timer counter work normally"] pub const QTIMER1_TMR_CNTS_FREEZE_0: u32 = 0; - #[doc = "Reset counter and ouput flags"] + #[doc = "reset counter and ouput flags"] pub const QTIMER1_TMR_CNTS_FREEZE_1: u32 = 0x01; } } @@ -938,9 +938,9 @@ pub mod GPR3 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select \\[127:0\\] from SNVS Master Key as DCP key"] + #[doc = "Select \\[127:0\\] from snvs/ocotp key as dcp key"] pub const DCP_KEY_SEL_0: u32 = 0; - #[doc = "Select \\[255:128\\] from SNVS Master Key as DCP key"] + #[doc = "Select \\[255:128\\] from snvs/ocotp key as dcp key"] pub const DCP_KEY_SEL_1: u32 = 0x01; } } @@ -1334,9 +1334,9 @@ pub mod GPR5 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "source from GPT2_CAPTURE1"] + #[doc = "source from pad"] pub const GPT2_CAPIN1_SEL_0: u32 = 0; - #[doc = "source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)"] + #[doc = "source from enet1.ipp_do_mac0_timer\\[3\\]"] pub const GPT2_CAPIN1_SEL_1: u32 = 0x01; } } @@ -1347,9 +1347,9 @@ pub mod GPR5 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "event3 source input from ENET_1588_EVENT3_IN"] + #[doc = "event3 source input from pad"] pub const ENET_EVENT3IN_SEL_0: u32 = 0; - #[doc = "event3 source input from GPT2.GPT_COMPARE1"] + #[doc = "event3 source input from gpt2.ipp_do_cmpout1"] pub const ENET_EVENT3IN_SEL_1: u32 = 0x01; } } @@ -2685,7 +2685,7 @@ pub mod GPR10 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select key from SNVS Master Key."] + #[doc = "Select key from Key MUX (SNVS/OTPMK)."] pub const DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0; #[doc = "Select key from OCOTP (SW_GP2)."] pub const DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01; diff --git a/src/blocks/imxrt1061/iomuxc.rs b/src/blocks/imxrt1061/iomuxc.rs index ddc474f5f03c..11c7ee23219a 100644 --- a/src/blocks/imxrt1061/iomuxc.rs +++ b/src/blocks/imxrt1061/iomuxc.rs @@ -1120,15 +1120,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_04 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA04 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT04 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA02 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: SPDIF_OUT of instance: spdif"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO16 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO04 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1157,15 +1157,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_05 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA05 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT05 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB02 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: SPDIF_IN of instance: spdif"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO17 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO05 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1194,15 +1194,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_06 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA06 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT06 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_DATA of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO18 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO06 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1231,15 +1231,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_07 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA07 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT07 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_SYNC of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO19 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO07 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1268,15 +1268,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_08 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DM00 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT08 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: FLEXCAN2_TX of instance: flexcan2"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_DATA of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT17 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO20 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO08 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1652,19 +1652,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_18 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB03 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: lpuart4"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO22 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: QTIMER3_TIMER3 of instance: qtimer3"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: src"] + #[doc = "Select mux mode: ALT6 mux port: SNVS_VIO_5_CTL of instance: snvs_hp"] pub const ALT6: u32 = 0x06; } } @@ -1691,19 +1691,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_19 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR03 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR11 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: ENET_RDATA01 of instance: enet"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO23 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: QTIMER2_TIMER0 of instance: qtimer2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: src"] + #[doc = "Select mux mode: ALT6 mux port: SNVS_VIO_5 of instance: snvs_hp"] pub const ALT6: u32 = 0x06; } } @@ -2727,21 +2727,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_03 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_TDI of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: FLEXCAN2_RX of instance: flexcan2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: USDHC2_CD_B of instance: usdhc2"] + #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: WDOG1_B of instance: wdog1"] + #[doc = "Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: usb"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: USDHC1_WP of instance: usdhc1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX01 of instance: flexpwm1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_OC of instance: usb"] + #[doc = "Select mux mode: ALT6 mux port: REF_CLK_24M of instance: anatop"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: CCM_PMIC_RDY of instance: ccm"] + #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS0 of instance: lpspi3"] pub const ALT7: u32 = 0x07; } } @@ -2768,21 +2768,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_04 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_TDO of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: src"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXCAN1_TX of instance: flexcan1"] + #[doc = "Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: USDHC1_WP of instance: usdhc1"] + #[doc = "Select mux mode: ALT2 mux port: ENET_TX_DATA03 of instance: enet"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: QTIMER2_TIMER0 of instance: qtimer2"] + #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: ENET_MDIO of instance: enet"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_PWR of instance: usb"] + #[doc = "Select mux mode: ALT6 mux port: PIT_TRIGGER00 of instance: pit"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: EWM_OUT_B of instance: ewm"] + #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS1 of instance: lpspi3"] pub const ALT7: u32 = 0x07; } } @@ -2809,21 +2809,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_05 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_TRSTB of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXCAN1_RX of instance: flexcan1"] + #[doc = "Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: USDHC1_CD_B of instance: usdhc1"] + #[doc = "Select mux mode: ALT2 mux port: ENET_TX_DATA02 of instance: enet"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: QTIMER2_TIMER1 of instance: qtimer2"] + #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: ENET_MDC of instance: enet"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_ID of instance: anatop"] + #[doc = "Select mux mode: ALT6 mux port: XBAR1_INOUT17 of instance: xbar1"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"] + #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS2 of instance: lpspi3"] pub const ALT7: u32 = 0x07; } } @@ -3106,21 +3106,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_12 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: ENET_RX_ER of instance: enet"] + #[doc = "Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: LPSPI1_SDO of instance: lpspi1"] + #[doc = "Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: KPP_COL02 of instance: kpp"] + #[doc = "Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2"] + #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ARM_CM7_TRACE00 of instance: cm7_mxrt"] + #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp"] + #[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"] pub const ALT7: u32 = 0x07; } } @@ -3147,21 +3147,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_13 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: ENET_TX_EN of instance: enet"] + #[doc = "Select mux mode: ALT0 mux port: LPI2C4_SDA of instance: lpi2c4"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: LPSPI1_SDI of instance: lpspi1"] + #[doc = "Select mux mode: ALT1 mux port: GPT1_CLK of instance: gpt1"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: LPUART1_RX of instance: lpuart1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: KPP_ROW02 of instance: kpp"] + #[doc = "Select mux mode: ALT3 mux port: EWM_OUT_B of instance: ewm"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2"] + #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX03 of instance: flexpwm1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ARM_CM7_TRACE01 of instance: cm7_mxrt"] + #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT1_IN of instance: enet"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: SNVS_HP_VIO_5_B of instance: snvs_hp"] + #[doc = "Select mux mode: ALT7 mux port: REF_CLK_24M of instance: anatop"] pub const ALT7: u32 = 0x07; } } @@ -5847,17 +5847,17 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_07 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance: usdhc2"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_CSX01 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_SCLK of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_SCLK of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_RX_EN of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART7_RTS_B of instance: lpuart7"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_SCK of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5925,15 +5925,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_09 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA5 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA02 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA01 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TX_EN of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_SDI of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO29 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5962,15 +5962,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_10 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA6 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA01 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA02 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TDATA00 of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: lpi2c2"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS2 of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO30 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5999,15 +5999,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_11 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA7 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_SS0_B of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA03 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TDATA01 of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: lpi2c2"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS3 of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO31 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } diff --git a/src/blocks/imxrt1061/iomuxc_gpr.rs b/src/blocks/imxrt1061/iomuxc_gpr.rs index 67cdb796706e..9153ab31e2c7 100644 --- a/src/blocks/imxrt1061/iomuxc_gpr.rs +++ b/src/blocks/imxrt1061/iomuxc_gpr.rs @@ -125,7 +125,7 @@ pub mod GPR1 { pub mod RW { #[doc = "ccm.spdif0_clk_root"] pub const SAI1_MCLK3_SEL_0: u32 = 0; - #[doc = "SPDIF_EXT_CLK"] + #[doc = "iomux.spdif_tx_clk2"] pub const SAI1_MCLK3_SEL_1: u32 = 0x01; #[doc = "spdif.spdif_srclk"] pub const SAI1_MCLK3_SEL_2: u32 = 0x02; @@ -142,7 +142,7 @@ pub mod GPR1 { pub mod RW { #[doc = "ccm.spdif0_clk_root"] pub const SAI2_MCLK3_SEL_0: u32 = 0; - #[doc = "SPDIF_EXT_CLK"] + #[doc = "iomux.spdif_tx_clk2"] pub const SAI2_MCLK3_SEL_1: u32 = 0x01; #[doc = "spdif.spdif_srclk"] pub const SAI2_MCLK3_SEL_2: u32 = 0x02; @@ -159,7 +159,7 @@ pub mod GPR1 { pub mod RW { #[doc = "ccm.spdif0_clk_root"] pub const SAI3_MCLK3_SEL_0: u32 = 0; - #[doc = "SPDIF_EXT_CLK"] + #[doc = "iomux.spdif_tx_clk2"] pub const SAI3_MCLK3_SEL_1: u32 = 0x01; #[doc = "spdif.spdif_srclk"] pub const SAI3_MCLK3_SEL_2: u32 = 0x02; @@ -187,7 +187,7 @@ pub mod GPR1 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "ENET1 TX reference clock driven by ref_enetpll."] + #[doc = "ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function."] pub const ENET1_CLK_SEL_0: u32 = 0; #[doc = "Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller."] pub const ENET1_CLK_SEL_1: u32 = 0x01; @@ -293,7 +293,7 @@ pub mod GPR1 { pub mod RW { #[doc = "OKAY response"] pub const EXC_MON_0: u32 = 0; - #[doc = "SLVError response"] + #[doc = "SLVError response (default)"] pub const EXC_MON_1: u32 = 0x01; } } @@ -317,9 +317,9 @@ pub mod GPR1 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible."] + #[doc = "AHB clock is not running (gated)"] pub const CM7_FORCE_HCLK_EN_0: u32 = 0; - #[doc = "AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible."] + #[doc = "AHB clock is running (enabled)"] pub const CM7_FORCE_HCLK_EN_1: u32 = 0x01; } } @@ -424,9 +424,9 @@ pub mod GPR2 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Enters power saving mode only when chip is in SUSPEND mode"] + #[doc = "none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect"] pub const L2_MEM_EN_POWERSAVING_0: u32 = 0; - #[doc = "Controlled by L2_MEM_DEEPSLEEP bitfield"] + #[doc = "memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP (priority high to low) to enable power saving levels"] pub const L2_MEM_EN_POWERSAVING_1: u32 = 0x01; } } @@ -450,9 +450,9 @@ pub mod GPR2 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode)"] + #[doc = "no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode"] pub const L2_MEM_DEEPSLEEP_0: u32 = 0; - #[doc = "Force memory into deep sleep mode (OCRAM in power saving mode)"] + #[doc = "force memory into deep sleep mode"] pub const L2_MEM_DEEPSLEEP_1: u32 = 0x01; } } @@ -1023,9 +1023,9 @@ pub mod GPR2 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Timer counter works normally"] + #[doc = "timer counter work normally"] pub const QTIMER1_TMR_CNTS_FREEZE_0: u32 = 0; - #[doc = "Reset counter and ouput flags"] + #[doc = "reset counter and ouput flags"] pub const QTIMER1_TMR_CNTS_FREEZE_1: u32 = 0x01; } } @@ -1086,9 +1086,9 @@ pub mod GPR3 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select \\[127:0\\] from SNVS Master Key as DCP key"] + #[doc = "Select \\[127:0\\] from snvs/ocotp key as dcp key"] pub const DCP_KEY_SEL_0: u32 = 0; - #[doc = "Select \\[255:128\\] from SNVS Master Key as DCP key"] + #[doc = "Select \\[255:128\\] from snvs/ocotp key as dcp key"] pub const DCP_KEY_SEL_1: u32 = 0x01; } } @@ -1412,9 +1412,9 @@ pub mod GPR4 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "ENET stop acknowledge is not asserted"] + #[doc = "ENET1 stop acknowledge is not asserted"] pub const ENET_STOP_ACK_0: u32 = 0; - #[doc = "ENET stop acknowledge is asserted"] + #[doc = "ENET1 stop acknowledge is asserted"] pub const ENET_STOP_ACK_1: u32 = 0x01; } } @@ -2974,7 +2974,7 @@ pub mod GPR10 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select key from SNVS Master Key."] + #[doc = "Select key from Key MUX (SNVS/OTPMK)."] pub const DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0; #[doc = "Select key from OCOTP (SW_GP2)."] pub const DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01; diff --git a/src/blocks/imxrt1064/iomuxc.rs b/src/blocks/imxrt1064/iomuxc.rs index 5996a4c2d5cf..0fed9ee89fae 100644 --- a/src/blocks/imxrt1064/iomuxc.rs +++ b/src/blocks/imxrt1064/iomuxc.rs @@ -1056,15 +1056,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_04 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA04 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT04 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA02 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: SPDIF_OUT of instance: spdif"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO16 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO04 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1093,15 +1093,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_05 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA05 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT05 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB02 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: SPDIF_IN of instance: spdif"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO17 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO05 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1130,15 +1130,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_06 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA06 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT06 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_DATA of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO18 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO06 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1167,15 +1167,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_07 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA07 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT07 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_SYNC of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO19 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO07 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1204,15 +1204,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_08 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: SEMC_DM00 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT08 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: FLEXCAN2_TX of instance: flexcan2"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_DATA of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT17 of instance: xbar1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO20 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO08 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1239,17 +1239,17 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_09 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_WE of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT09 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: FLEXCAN2_RX of instance: flexcan2"] + #[doc = "Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_BCLK of instance: sai2"] + #[doc = "Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO21 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO09 of instance: flexio1"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4"] pub const ALT5: u32 = 0x05; } } @@ -1572,19 +1572,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_18 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB03 of instance: flexpwm4"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: lpuart4"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO22 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: QTIMER3_TIMER3 of instance: qtimer3"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: src"] + #[doc = "Select mux mode: ALT6 mux port: SNVS_VIO_5_CTL of instance: snvs_hp"] pub const ALT6: u32 = 0x06; } } @@ -1611,19 +1611,19 @@ pub mod SW_MUX_CTL_PAD_GPIO_EMC_19 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR03 of instance: semc"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR11 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1"] + #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2"] + #[doc = "Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: ENET_RDATA01 of instance: enet"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO23 of instance: flexio1"] + #[doc = "Select mux mode: ALT4 mux port: QTIMER2_TIMER0 of instance: qtimer2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2"] + #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: src"] + #[doc = "Select mux mode: ALT6 mux port: SNVS_VIO_5 of instance: snvs_hp"] pub const ALT6: u32 = 0x06; } } @@ -2631,21 +2631,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_03 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_TDI of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: FLEXCAN2_RX of instance: flexcan2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: USDHC2_CD_B of instance: usdhc2"] + #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: WDOG1_B of instance: wdog1"] + #[doc = "Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1"] + #[doc = "Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: usb"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: USDHC1_WP of instance: usdhc1"] + #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX01 of instance: flexpwm1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_OC of instance: usb"] + #[doc = "Select mux mode: ALT6 mux port: REF_CLK_24M of instance: anatop"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: CCM_PMIC_RDY of instance: ccm"] + #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS0 of instance: lpspi3"] pub const ALT7: u32 = 0x07; } } @@ -2672,21 +2672,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_04 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_TDO of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: src"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXCAN1_TX of instance: flexcan1"] + #[doc = "Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: USDHC1_WP of instance: usdhc1"] + #[doc = "Select mux mode: ALT2 mux port: ENET_TX_DATA03 of instance: enet"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: QTIMER2_TIMER0 of instance: qtimer2"] + #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: ENET_MDIO of instance: enet"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_PWR of instance: usb"] + #[doc = "Select mux mode: ALT6 mux port: PIT_TRIGGER00 of instance: pit"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: EWM_OUT_B of instance: ewm"] + #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS1 of instance: lpspi3"] pub const ALT7: u32 = 0x07; } } @@ -2713,21 +2713,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_05 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: JTAG_TRSTB of instance: jtag_mux"] + #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXCAN1_RX of instance: flexcan1"] + #[doc = "Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: USDHC1_CD_B of instance: usdhc1"] + #[doc = "Select mux mode: ALT2 mux port: ENET_TX_DATA02 of instance: enet"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: QTIMER2_TIMER1 of instance: qtimer2"] + #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: ENET_MDC of instance: enet"] + #[doc = "Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_ID of instance: anatop"] + #[doc = "Select mux mode: ALT6 mux port: XBAR1_INOUT17 of instance: xbar1"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"] + #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS2 of instance: lpspi3"] pub const ALT7: u32 = 0x07; } } @@ -3010,21 +3010,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_12 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: ENET_RX_ER of instance: enet"] + #[doc = "Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: LPSPI1_SDO of instance: lpspi1"] + #[doc = "Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: KPP_COL02 of instance: kpp"] + #[doc = "Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2"] + #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ARM_CM7_TRACE00 of instance: cm7_mxrt"] + #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp"] + #[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"] pub const ALT7: u32 = 0x07; } } @@ -3051,21 +3051,21 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_13 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: ENET_TX_EN of instance: enet"] + #[doc = "Select mux mode: ALT0 mux port: LPI2C4_SDA of instance: lpi2c4"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: LPSPI1_SDI of instance: lpspi1"] + #[doc = "Select mux mode: ALT1 mux port: GPT1_CLK of instance: gpt1"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3"] + #[doc = "Select mux mode: ALT2 mux port: LPUART1_RX of instance: lpuart1"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: KPP_ROW02 of instance: kpp"] + #[doc = "Select mux mode: ALT3 mux port: EWM_OUT_B of instance: ewm"] pub const ALT3: u32 = 0x03; - #[doc = "Select mux mode: ALT4 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2"] + #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX03 of instance: flexpwm1"] pub const ALT4: u32 = 0x04; #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1"] pub const ALT5: u32 = 0x05; - #[doc = "Select mux mode: ALT6 mux port: ARM_CM7_TRACE01 of instance: cm7_mxrt"] + #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT1_IN of instance: enet"] pub const ALT6: u32 = 0x06; - #[doc = "Select mux mode: ALT7 mux port: SNVS_HP_VIO_5_B of instance: snvs_hp"] + #[doc = "Select mux mode: ALT7 mux port: REF_CLK_24M of instance: anatop"] pub const ALT7: u32 = 0x07; } } @@ -5751,17 +5751,17 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_07 { pub mod R {} pub mod W {} pub mod RW { - #[doc = "Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance: usdhc2"] + #[doc = "Select mux mode: ALT0 mux port: SEMC_CSX01 of instance: semc"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_SCLK of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_SCLK of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_RX_EN of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART7_RTS_B of instance: lpuart7"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_SCK of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5829,15 +5829,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_09 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA5 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA02 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA01 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TX_EN of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_SDI of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO29 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5866,15 +5866,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_10 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA6 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_DATA01 of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA02 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TDATA00 of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: lpi2c2"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS2 of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO30 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } @@ -5903,15 +5903,15 @@ pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_11 { pub mod RW { #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA7 of instance: usdhc2"] pub const ALT0: u32 = 0; - #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_A_SS0_B of instance: flexspi_bus2bit"] + #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA03 of instance: flexspi"] pub const ALT1: u32 = 0x01; - #[doc = "Select mux mode: ALT2 mux port: ENET_TDATA01 of instance: enet"] + #[doc = "Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2"] pub const ALT2: u32 = 0x02; - #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3"] + #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: lpi2c2"] pub const ALT3: u32 = 0x03; #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS3 of instance: lpspi2"] pub const ALT4: u32 = 0x04; - #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO31 of instance: gpio3"] + #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3"] pub const ALT5: u32 = 0x05; } } From 0d3916191ef6847fffbe694bdbf513ae91fdab57 Mon Sep 17 00:00:00 2001 From: Ian McIntyre Date: Tue, 14 May 2024 11:00:17 -0400 Subject: [PATCH 5/5] Patch SVDs with GPIO5 clock gate The 1020, 1050, and 1060 SVDs qualify these fields as reserved, so the previous commits scrubbed the fields. Patch the SVDs to re-introduce the field. --- devices/common_patches/ccm_cg_gpio5.yaml | 11 +++++++++++ devices/imxrt1021.yaml | 1 + devices/imxrt1051.yaml | 1 + devices/imxrt1052.yaml | 1 + devices/imxrt1061.yaml | 1 + devices/imxrt1062.yaml | 1 + devices/imxrt1064.yaml | 1 + src/blocks/imxrt1021/ccm.rs | 8 ++++++++ src/blocks/imxrt1051/ccm.rs | 8 ++++++++ src/blocks/imxrt1061/ccm.rs | 8 ++++++++ 10 files changed, 41 insertions(+) create mode 100644 devices/common_patches/ccm_cg_gpio5.yaml diff --git a/devices/common_patches/ccm_cg_gpio5.yaml b/devices/common_patches/ccm_cg_gpio5.yaml new file mode 100644 index 000000000000..a324d22940a6 --- /dev/null +++ b/devices/common_patches/ccm_cg_gpio5.yaml @@ -0,0 +1,11 @@ +# Clock gate 15 in CCM[CCGR1] is missing from 1050 and 1060 MCUs. +# It isn't reserved according to the reference manual. This +# clock gate is for GPIO5. +CCM: + CCGR1: + _modify: + CG15: + description: gpio5 clock (gpio5_clk_enable) + bitOffset: 30 + bitWidth: 2 + access: read-write diff --git a/devices/imxrt1021.yaml b/devices/imxrt1021.yaml index 642417df5148..f73a4926c9af 100644 --- a/devices/imxrt1021.yaml +++ b/devices/imxrt1021.yaml @@ -2,6 +2,7 @@ _svd: "../svd/imxrt1021.svd" _include: - "common.yaml" + - "common_patches/ccm_cg_gpio5.yaml" - "common_patches/pwm1/submodule_cluster.yaml" - "common_patches/usb.yaml" - "common_patches/dma0/tcd_cluster.yaml" diff --git a/devices/imxrt1051.yaml b/devices/imxrt1051.yaml index 544ff3d21fc4..23c6e63d9482 100644 --- a/devices/imxrt1051.yaml +++ b/devices/imxrt1051.yaml @@ -2,6 +2,7 @@ _svd: "../svd/imxrt1051.svd" _include: - "common.yaml" + - "common_patches/ccm_cg_gpio5.yaml" - "common_patches/pwm1/submodule_cluster.yaml" - "common_patches/usb1.yaml" - "common_patches/dma0/tcd_cluster.yaml" diff --git a/devices/imxrt1052.yaml b/devices/imxrt1052.yaml index 6c17c0077d54..1801994c0ac5 100644 --- a/devices/imxrt1052.yaml +++ b/devices/imxrt1052.yaml @@ -2,6 +2,7 @@ _svd: "../svd/imxrt1052.svd" _include: - "common.yaml" + - "common_patches/ccm_cg_gpio5.yaml" - "common_patches/pwm1/submodule_cluster.yaml" - "common_patches/usb1.yaml" - "common_patches/dma0/tcd_cluster.yaml" diff --git a/devices/imxrt1061.yaml b/devices/imxrt1061.yaml index af3fe86a841c..d3cc86084e06 100644 --- a/devices/imxrt1061.yaml +++ b/devices/imxrt1061.yaml @@ -2,6 +2,7 @@ _svd: "../svd/imxrt1061.svd" _include: - "common.yaml" + - "common_patches/ccm_cg_gpio5.yaml" - "common_patches/pwm1/submodule_cluster.yaml" - "common_patches/usb1.yaml" - "common_patches/dma0/tcd_cluster.yaml" diff --git a/devices/imxrt1062.yaml b/devices/imxrt1062.yaml index 3fc1ddb7fc2a..bf804b9a7807 100644 --- a/devices/imxrt1062.yaml +++ b/devices/imxrt1062.yaml @@ -2,6 +2,7 @@ _svd: "../svd/imxrt1062.svd" _include: - "common.yaml" + - "common_patches/ccm_cg_gpio5.yaml" - "common_patches/pwm1/submodule_cluster.yaml" - "common_patches/usb1.yaml" - "common_patches/dma0/tcd_cluster.yaml" diff --git a/devices/imxrt1064.yaml b/devices/imxrt1064.yaml index b770c6eb436a..cb1a4696d554 100644 --- a/devices/imxrt1064.yaml +++ b/devices/imxrt1064.yaml @@ -2,6 +2,7 @@ _svd: "../svd/imxrt1064.svd" _include: - "common.yaml" + - "common_patches/ccm_cg_gpio5.yaml" - "common_patches/pwm1/submodule_cluster.yaml" - "common_patches/usb1.yaml" - "common_patches/dma0/tcd_cluster.yaml" diff --git a/src/blocks/imxrt1021/ccm.rs b/src/blocks/imxrt1021/ccm.rs index 33b1123af10d..4a428f2b44f3 100644 --- a/src/blocks/imxrt1021/ccm.rs +++ b/src/blocks/imxrt1021/ccm.rs @@ -2720,6 +2720,14 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } + #[doc = "gpio5 clock (gpio5_clk_enable)"] + pub mod CG15 { + pub const offset: u32 = 30; + pub const mask: u32 = 0x03 << offset; + pub mod R {} + pub mod W {} + pub mod RW {} + } } #[doc = "CCM Clock Gating Register 2"] pub mod CCGR2 { diff --git a/src/blocks/imxrt1051/ccm.rs b/src/blocks/imxrt1051/ccm.rs index 7311625bf8a1..b2769dd897a3 100644 --- a/src/blocks/imxrt1051/ccm.rs +++ b/src/blocks/imxrt1051/ccm.rs @@ -2927,6 +2927,14 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } + #[doc = "gpio5 clock (gpio5_clk_enable)"] + pub mod CG15 { + pub const offset: u32 = 30; + pub const mask: u32 = 0x03 << offset; + pub mod R {} + pub mod W {} + pub mod RW {} + } } #[doc = "CCM Clock Gating Register 2"] pub mod CCGR2 { diff --git a/src/blocks/imxrt1061/ccm.rs b/src/blocks/imxrt1061/ccm.rs index bf4c7d3938bf..c85933079c5b 100644 --- a/src/blocks/imxrt1061/ccm.rs +++ b/src/blocks/imxrt1061/ccm.rs @@ -2968,6 +2968,14 @@ pub mod CCGR1 { pub mod W {} pub mod RW {} } + #[doc = "gpio5 clock (gpio5_clk_enable)"] + pub mod CG15 { + pub const offset: u32 = 30; + pub const mask: u32 = 0x03 << offset; + pub mod R {} + pub mod W {} + pub mod RW {} + } } #[doc = "CCM Clock Gating Register 2"] pub mod CCGR2 {