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When I tried to run the example, I encountered an error.
Traceback (most recent call last):
File "/XXX/imagen/codeGen.py", line 921, in <module>
main()
File "/XXX/imagen/codeGen.py", line 915, in main
shutil.copyfile("controllers/LBController.sv",os.path.join(Output,"LBController.sv"))
File "/XXX/anaconda3/envs/common/lib/python3.12/shutil.py", line 260, in copyfile
with open(src, 'rb') as fsrc:
^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: 'controllers/LBController.sv'
It seems that a directory containing some shared SystemVerilog (SV) code is missing from this repository. Could you please check and add the missing directory with the required files?
Thank you!
The text was updated successfully, but these errors were encountered:
Hi!
When I tried to run the example, I encountered an error.
It seems that a directory containing some shared SystemVerilog (SV) code is missing from this repository. Could you please check and add the missing directory with the required files?
Thank you!
The text was updated successfully, but these errors were encountered: