diff --git a/litex/gen/fhdl/expression.py b/litex/gen/fhdl/expression.py
index d06fbe25f1..4760f4641d 100644
--- a/litex/gen/fhdl/expression.py
+++ b/litex/gen/fhdl/expression.py
@@ -96,20 +96,15 @@ def to_signed(r):
 # Print Slice --------------------------------------------------------------------------------------
 
 def _generate_slice(ns, node):
-    length = len(node)
-    assert length >= 1
-    start = 0
-    while isinstance(node, _Slice):
-        start += node.start
-        node = node.value
-    if len(node) == 1:
-        sr = "" # Avoid slicing 1-bit Signals.
+    assert (node.stop - node.start) >= 1
+    if hasattr(node.value, "__len__") and len(node.value) == 1:
+         sr = "" # Avoid slicing 1-bit Signals.
     else:
-        if length > 1:
-            sr = f"[{start+length-1}:{start}]"
+        if (node.stop - node.start) > 1:
+            sr = f"[{node.stop-1}:{node.start}]"
         else:
-            sr = f"[{start}]"
-    r, s = _generate_expression(ns, node)
+            sr = f"[{node.start}]"
+    r, s = _generate_expression(ns, node.value)
     return r + sr, s
 
 # Print Cat ----------------------------------------------------------------------------------------
diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 9092e1e374..91c9c929f4 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -456,6 +456,9 @@ def convert(f, ios=set(), name="top", platform=None,
                 msg += f"- {f.name}\n"
             raise Exception(msg)
 
+    # Lower complex slices.
+    f = lower_complex_slices(f)
+
     # Insert resets.
     insert_resets(f)