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Issues: enjoy-digital/litedram

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#214 opened Aug 3, 2020 by enjoy-digital
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Issues list

Refresh S6DDRPHY enhancement help-wanted
#182 opened Apr 23, 2020 by enjoy-digital
14
Axi port write data error
#342 opened Jun 7, 2023 by Yuxin-Yu
8
LiteDRAM USPDDRPHY unable to meet DDR4 timing requirements? bug? question
#303 opened Mar 28, 2022 by jaccharrison
8
ECP5: Use ODDRX1F for address and command bus enhancement
#194 opened May 15, 2020 by kingoflolz
8
Carrying out the LiteDRAM standalone core initialization manually, through wishbone ctrl interface
#327 opened Feb 28, 2023 by dinaabdelbaky
7
Add support for Etron RPC DRAM new-feature
#211 opened Jul 28, 2020 by jedrzejboczar
7
litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)
#349 opened Oct 5, 2023 by jersey99
5
--top-module 'sim' was not found in the design question
#325 opened Jan 28, 2023 by CarrolXC
5
Add support for DDR3 in MAX10 help-wanted new-feature
#233 opened Feb 15, 2021 by rdolbeau
5
Core Question add-answer-to-wiki question
#219 opened Oct 2, 2020 by vasimr
4
ulx3s example does not work add-answer-to-wiki
#329 opened Apr 1, 2023 by TheZoq2
3
Help generating DDR3 Verilog module for Digilent NexysVideo Artix-7 FPGA regression
#281 opened Oct 10, 2021 by tambewilliam
3
Add Reordering support enhancement help-wanted
#30 opened Aug 22, 2018 by enjoy-digital
3
Wishbone, 2 writes followed by colliding read returns incorrect result, write stuck in FIFO bug?
#358 opened May 6, 2024 by epsilon537
2
LiteDRAMDMAWriter sinks data when not enabled bug?
#356 opened Apr 24, 2024 by DaveBerkeley
2
submodules verilog question
#316 opened Dec 26, 2022 by CarrolXC
2
QuarterRateGENSDRPHY
#308 opened Jun 25, 2022 by machdyne
2
Wrong DQS pattern preamble/postamble bug? question
#225 opened Dec 10, 2020 by jedrzejboczar
2
Native Interface Documentation and Simulation add-answer-to-wiki enhancement question
#220 opened Oct 3, 2020 by vasimr
2
Inconsistencies between SPD data and datasheets. needs-review
#184 opened Apr 25, 2020 by enjoy-digital
2
Adding support to gowin phys in litedram.gen? enhancement
#357 opened Apr 28, 2024 by linhz0hz
1
LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.
#344 opened Aug 17, 2023 by dinaabdelbaky
1
AxSIZE mismatch?
#334 opened Apr 24, 2023 by TheZoq2
1
1
Setting for user_clk question
#333 opened Apr 23, 2023 by ztachip
1
DDR4 reads without DQS at high speeds? question
#328 opened Feb 28, 2023 by alexey-morozov
1
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