From c281c4cdce44867e90f58a04ce9b6983c3a3c5e2 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Wed, 18 Sep 2024 07:18:59 +0200 Subject: [PATCH] Proper FPU initialization --- ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h | 13 +++++++------ .../target/micros/rpi_pico2_rp2350/startup/crt0.cpp | 10 +++++++--- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h b/ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h index edb1d6e39..d6e8b6ff6 100644 --- a/ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h +++ b/ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h @@ -55,26 +55,27 @@ constexpr std::uint32_t hw_per_clocks_clk_peri_ctrl { hw_per_clocks_base + UINT32_C(0x00000048) }; // PSM registers. + constexpr std::uint32_t hw_per_psm_base { UINT32_C(0x40018000) }; constexpr std::uint32_t psm_base { UINT32_C(0x40018000) }; constexpr std::uint32_t psm_frce_on { psm_base + UINT32_C(0x00000000) }; constexpr std::uint32_t psm_frce_off { psm_base + UINT32_C(0x00000004) }; constexpr std::uint32_t psm_wdsel { psm_base + UINT32_C(0x00000008) }; constexpr std::uint32_t psm_done { psm_base + UINT32_C(0x0000000C) }; + // PPB registers. + constexpr std::uint32_t hw_per_ppb_base { UINT32_C(0xE0000000) }; + constexpr std::uint32_t hw_per_ppb_cpacr { hw_per_ppb_base + UINT32_C(0x0000ED88) }; + constexpr std::uint32_t hw_per_ppb_nsacr { hw_per_ppb_base + UINT32_C(0x0000ED8C) }; + + // I/O-Bank registers. constexpr std::uint32_t pads_bank0_base { UINT32_C(0x40038000) }; constexpr std::uint32_t pads_bank0_gpio { UINT32_C(0x40038004) }; - // I/O-Bank registers. constexpr std::uint32_t io_bank0_base { UINT32_C(0x40028000) }; constexpr std::uint32_t io_bank0_status_base { io_bank0_base + UINT32_C(0x00000000) }; constexpr std::uint32_t hw_per_io_bank0 { io_bank0_base }; - constexpr std::uint32_t hw_per_psm_base { UINT32_C(0x40018000) }; - - constexpr std::uint32_t hw_per_ppb_base { UINT32_C(0xE0000000) }; - constexpr std::uint32_t hw_per_ppb_cpacr { hw_per_ppb_base + UINT32_C(0x0000ED88) }; - constexpr std::uint32_t hw_per_xosc_base { UINT32_C(0x40048000) }; constexpr std::uint32_t hw_per_xosc_control { UINT32_C(0x40048000) }; constexpr std::uint32_t hw_per_xosc_status { UINT32_C(0x40048004) }; diff --git a/ref_app/target/micros/rpi_pico2_rp2350/startup/crt0.cpp b/ref_app/target/micros/rpi_pico2_rp2350/startup/crt0.cpp index 2b995abe9..21c58cf27 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/startup/crt0.cpp +++ b/ref_app/target/micros/rpi_pico2_rp2350/startup/crt0.cpp @@ -172,13 +172,17 @@ auto __main_core1() -> void // Synchronize with core 0. mcal::cpu::rp2350::multicore_sync(local::get_cpuid()); - // Initialize the FPU on Core 1: Enable CP10 and CP11. + // Enable the hardware FPU on Core 1. + + mcal::reg::reg_access_static::reg_or(); - // HW_PER_PPB->CPACR.reg |= (std::uint32_t) 0x00F00000UL; mcal::reg::reg_access_static::reg_or(); + std::uint32_t { (3UL << 20U) | (3UL << 22U) }>::reg_or(); // Jump to main on core 1 (and never return). asm volatile("ldr r3, =main");