From bfebca9c3d2f0a395347264868332a1dd0f30316 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Thu, 19 Sep 2024 20:30:50 +0200 Subject: [PATCH] Rectify docs and copyrights on Pico2 rpi2350 --- readme.md | 7 +++++ ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h | 28 +++++++++---------- ref_app/src/mcal/rpi_pico_rp2040/mcal_reg.h | 12 ++++---- .../micros/nxp_imxrt1062/startup/bootdata.cpp | 2 +- .../micros/nxp_imxrt1062/startup/int_vect.cpp | 2 +- .../micros/rpi_pico2_rp2350/startup/crt0.cpp | 1 + .../startup/image_definition_block.cpp | 8 ++++++ .../rpi_pico2_rp2350/startup/int_vect.cpp | 1 + .../micros/rpi_pico2_rp2350/startup/util.cpp | 13 ++++----- .../micros/rpi_pico_rp2040/startup/crt0.cpp | 1 + .../rpi_pico_rp2040/startup/int_vect.cpp | 1 + .../startup/secondary_boot.cpp | 5 ++-- 12 files changed, 49 insertions(+), 32 deletions(-) diff --git a/readme.md b/readme.md index 52b1f196a..882bd838f 100644 --- a/readme.md +++ b/readme.md @@ -446,6 +446,13 @@ dual-core startup originated in and have been taken from (with many thanks) from the `Blinky_Pico_dual_core_nosdk` [repo](https://github.com/Chalandi/Blinky_Pico_dual_core_nosdk). +The `rpi_pico2_rp2350` target configuration employs the +RaspberryPi(R) Pico2 RP2350 with dual-core ARM(R) Cortex(R)-M33 +clocked at $150~\text{MHz}$. It has essentially the same boot +structure as the `2040`. Similarly the dual-core startup was +pioneered by the efforts revealed in the modernized `Blinky_Pico2_dual_core_nosdk` +[repo](https://github.com/Chalandi/Blinky_Pico2_dual_core_nosdk). + Target `v850es_fx2` uses a classic Renesas(R) V850es/Fx2 core. The upd703231 microcontroller derivative on an F-Line _Drive_ _It_ starter kit is used. diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h b/ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h index d6e8b6ff6..726194d86 100644 --- a/ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h +++ b/ref_app/src/mcal/rpi_pico2_rp2350/mcal_reg.h @@ -18,7 +18,7 @@ constexpr std::uint32_t scs_base { UINT32_C(0xE000E000) }; constexpr std::uint32_t nvic_base { scs_base + UINT32_C(0x00000100) }; - // NVIC registers. + // Interrupt control registers. constexpr std::uint32_t nvic_icpr { nvic_base + UINT32_C(0x00000180) }; // SCnSCB registers. @@ -62,6 +62,19 @@ constexpr std::uint32_t psm_wdsel { psm_base + UINT32_C(0x00000008) }; constexpr std::uint32_t psm_done { psm_base + UINT32_C(0x0000000C) }; + // Single-instruction registers. + constexpr std::uint32_t sio_base { UINT32_C(0xD0000000) }; + constexpr std::uint32_t hw_per_sio_base { sio_base }; + constexpr std::uint32_t sio_cpuid { sio_base + UINT32_C(0x00000000) }; + constexpr std::uint32_t sio_gpio_out_set { sio_base + UINT32_C(0x00000018) }; + constexpr std::uint32_t sio_gpio_out_clr { sio_base + UINT32_C(0x00000020) }; + constexpr std::uint32_t sio_gpio_out_xor { sio_base + UINT32_C(0x00000028) }; + constexpr std::uint32_t sio_gpio_oe_set { sio_base + UINT32_C(0x00000038) }; + constexpr std::uint32_t sio_gpio_oe_clr { sio_base + UINT32_C(0x00000040) }; + constexpr std::uint32_t sio_fifo_st { sio_base + UINT32_C(0x00000050) }; + constexpr std::uint32_t sio_fifo_wr { sio_base + UINT32_C(0x00000054) }; + constexpr std::uint32_t sio_fifo_rd { sio_base + UINT32_C(0x00000058) }; + // PPB registers. constexpr std::uint32_t hw_per_ppb_base { UINT32_C(0xE0000000) }; constexpr std::uint32_t hw_per_ppb_cpacr { hw_per_ppb_base + UINT32_C(0x0000ED88) }; @@ -83,19 +96,6 @@ constexpr std::uint32_t hw_per_xosc_startup { UINT32_C(0x4004800C) }; constexpr std::uint32_t hw_per_xosc_count { UINT32_C(0x40048010) }; - // Single-instruction registers. - constexpr std::uint32_t sio_base { UINT32_C(0xD0000000) }; - constexpr std::uint32_t sio_cpuid { sio_base + UINT32_C(0x00000000) }; - constexpr std::uint32_t sio_gpio_out_set { sio_base + UINT32_C(0x00000018) }; - constexpr std::uint32_t sio_gpio_out_clr { sio_base + UINT32_C(0x00000020) }; - constexpr std::uint32_t sio_gpio_out_xor { sio_base + UINT32_C(0x00000028) }; - constexpr std::uint32_t sio_gpio_oe_set { sio_base + UINT32_C(0x00000038) }; - constexpr std::uint32_t sio_gpio_oe_clr { sio_base + UINT32_C(0x00000040) }; - constexpr std::uint32_t sio_fifo_st { sio_base + UINT32_C(0x00000050) }; - constexpr std::uint32_t sio_fifo_wr { sio_base + UINT32_C(0x00000054) }; - constexpr std::uint32_t sio_fifo_rd { sio_base + UINT32_C(0x00000058) }; - - constexpr std::uint32_t hw_per_sio_base { sio_base }; } } diff --git a/ref_app/src/mcal/rpi_pico_rp2040/mcal_reg.h b/ref_app/src/mcal/rpi_pico_rp2040/mcal_reg.h index f6e7d2f1a..68a3cc168 100644 --- a/ref_app/src/mcal/rpi_pico_rp2040/mcal_reg.h +++ b/ref_app/src/mcal/rpi_pico_rp2040/mcal_reg.h @@ -1,5 +1,5 @@ /////////////////////////////////////////////////////////////////////////////// -// Copyright Christopher Kormanyos 2007 - 2024. +// Copyright Christopher Kormanyos 2024. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt // or copy at http://www.boost.org/LICENSE_1_0.txt) @@ -19,11 +19,11 @@ constexpr std::uint32_t nvic_base { scs_base + UINT32_C(0x00000100) }; // Interrupt control registers. - constexpr std::uint32_t nvic_iser { nvic_base + UINT32_C(0x00000000) }; // Offset: 0x000 Interrupt set enable registers. - constexpr std::uint32_t nvic_icer { nvic_base + UINT32_C(0x00000080) }; // Offset: 0x080 Interrupt clear enable registers. - constexpr std::uint32_t nvic_ispr { nvic_base + UINT32_C(0x00000100) }; // Offset: 0x100 Interrupt set pending registers. - constexpr std::uint32_t nvic_icpr { nvic_base + UINT32_C(0x00000180) }; // Offset: 0x180 Interrupt clear pending registers. - constexpr std::uint32_t nvic_ip { nvic_base + UINT32_C(0x00000300) }; // Offset: 0x300 Interrupt priority registers (each one 8 bits wide). + constexpr std::uint32_t nvic_iser { nvic_base + UINT32_C(0x00000000) }; // Offset: 0x000 Interrupt set enable registers. + constexpr std::uint32_t nvic_icer { nvic_base + UINT32_C(0x00000080) }; // Offset: 0x080 Interrupt clear enable registers. + constexpr std::uint32_t nvic_ispr { nvic_base + UINT32_C(0x00000100) }; // Offset: 0x100 Interrupt set pending registers. + constexpr std::uint32_t nvic_icpr { nvic_base + UINT32_C(0x00000180) }; // Offset: 0x180 Interrupt clear pending registers. + constexpr std::uint32_t nvic_ip { nvic_base + UINT32_C(0x00000300) }; // Offset: 0x300 Interrupt priority registers (each one 8 bits wide). // Oscillator registers. constexpr std::uint32_t xosc_base { UINT32_C(0x40024000) }; diff --git a/ref_app/target/micros/nxp_imxrt1062/startup/bootdata.cpp b/ref_app/target/micros/nxp_imxrt1062/startup/bootdata.cpp index 291fe74cb..3e7042223 100644 --- a/ref_app/target/micros/nxp_imxrt1062/startup/bootdata.cpp +++ b/ref_app/target/micros/nxp_imxrt1062/startup/bootdata.cpp @@ -1,6 +1,6 @@ /////////////////////////////////////////////////////////////////////////////// -// Copyright Christopher Kormanyos 2023. // Copyright Amine Chalandi 2023. +// Copyright Christopher Kormanyos 2023. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt // or copy at http://www.boost.org/LICENSE_1_0.txt) diff --git a/ref_app/target/micros/nxp_imxrt1062/startup/int_vect.cpp b/ref_app/target/micros/nxp_imxrt1062/startup/int_vect.cpp index f94e61cff..d40561627 100644 --- a/ref_app/target/micros/nxp_imxrt1062/startup/int_vect.cpp +++ b/ref_app/target/micros/nxp_imxrt1062/startup/int_vect.cpp @@ -1,6 +1,6 @@ /////////////////////////////////////////////////////////////////////////////// -// Copyright Christopher Kormanyos 2007 - 2023. // Copyright Amine Chalandi 2023. +// Copyright Christopher Kormanyos 2007 - 2023. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt // or copy at http://www.boost.org/LICENSE_1_0.txt) diff --git a/ref_app/target/micros/rpi_pico2_rp2350/startup/crt0.cpp b/ref_app/target/micros/rpi_pico2_rp2350/startup/crt0.cpp index 21c58cf27..fc0afeaf8 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/startup/crt0.cpp +++ b/ref_app/target/micros/rpi_pico2_rp2350/startup/crt0.cpp @@ -1,4 +1,5 @@ /////////////////////////////////////////////////////////////////////////////// +// Copyright Amine Chalandi 2024. // Copyright Christopher Kormanyos 2024. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt diff --git a/ref_app/target/micros/rpi_pico2_rp2350/startup/image_definition_block.cpp b/ref_app/target/micros/rpi_pico2_rp2350/startup/image_definition_block.cpp index db9539ce4..2689e8d26 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/startup/image_definition_block.cpp +++ b/ref_app/target/micros/rpi_pico2_rp2350/startup/image_definition_block.cpp @@ -1,3 +1,11 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Amine Chalandi 2024. +// Copyright Christopher Kormanyos 2024. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + /****************************************************************************************** Filename : image_definition_block.c diff --git a/ref_app/target/micros/rpi_pico2_rp2350/startup/int_vect.cpp b/ref_app/target/micros/rpi_pico2_rp2350/startup/int_vect.cpp index 362bb9dc4..5c283607c 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/startup/int_vect.cpp +++ b/ref_app/target/micros/rpi_pico2_rp2350/startup/int_vect.cpp @@ -1,4 +1,5 @@ /////////////////////////////////////////////////////////////////////////////// +// Copyright Amine Chalandi 2024. // Copyright Christopher Kormanyos 2024. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt diff --git a/ref_app/target/micros/rpi_pico2_rp2350/startup/util.cpp b/ref_app/target/micros/rpi_pico2_rp2350/startup/util.cpp index 93be2b147..c9ac2e076 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/startup/util.cpp +++ b/ref_app/target/micros/rpi_pico2_rp2350/startup/util.cpp @@ -1,14 +1,13 @@ /////////////////////////////////////////////////////////////////////////////// +// Copyright Amine Chalandi 2024. // Copyright Christopher Kormanyos 2024. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt // or copy at http://www.boost.org/LICENSE_1_0.txt) // -// Originally taken from: -// // *************************************************************************************** -// Filename : util.s +// Filename : util.s (now util.cpp) // // Author : Chalandi Amine // @@ -22,8 +21,8 @@ #include -extern "C" auto arch_spin_lock (std::uint32_t*) noexcept -> void __attribute__((naked)); -extern "C" auto arch_spin_unlock(std::uint32_t*) noexcept -> void __attribute__((naked)); +extern "C" auto arch_spin_lock (std::uint32_t*) noexcept -> void __attribute__((naked)); +extern "C" auto arch_spin_unlock(std::uint32_t*) noexcept -> void __attribute__((naked)); extern "C" auto arch_spin_lock(std::uint32_t*) noexcept -> void @@ -37,7 +36,7 @@ auto arch_spin_lock(std::uint32_t*) noexcept -> void asm volatile("cmp r2, #0"); // Check if successful asm volatile("bne .L_loop"); // Retry if not asm volatile("dmb"); // Ensure memory ordering after acquiring the lock - asm volatile("bx lr"); // Return if successful + asm volatile("bx lr"); // Return unconditionally } extern "C" @@ -46,5 +45,5 @@ auto arch_spin_unlock(std::uint32_t*) noexcept -> void asm volatile("dmb"); // Ensure memory operations before unlocking asm volatile("mov r1, #0"); // Clear the lock asm volatile("stl r1, [r0]"); // Store with release semantics - asm volatile("bx lr"); // Return + asm volatile("bx lr"); // Return unconditionally } diff --git a/ref_app/target/micros/rpi_pico_rp2040/startup/crt0.cpp b/ref_app/target/micros/rpi_pico_rp2040/startup/crt0.cpp index dc98a816e..ea58f1e1d 100644 --- a/ref_app/target/micros/rpi_pico_rp2040/startup/crt0.cpp +++ b/ref_app/target/micros/rpi_pico_rp2040/startup/crt0.cpp @@ -1,4 +1,5 @@ /////////////////////////////////////////////////////////////////////////////// +// Copyright Amine Chalandi 2024. // Copyright Christopher Kormanyos 2024. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt diff --git a/ref_app/target/micros/rpi_pico_rp2040/startup/int_vect.cpp b/ref_app/target/micros/rpi_pico_rp2040/startup/int_vect.cpp index fd461ba18..2067e93be 100644 --- a/ref_app/target/micros/rpi_pico_rp2040/startup/int_vect.cpp +++ b/ref_app/target/micros/rpi_pico_rp2040/startup/int_vect.cpp @@ -1,4 +1,5 @@ /////////////////////////////////////////////////////////////////////////////// +// Copyright Amine Chalandi 2024. // Copyright Christopher Kormanyos 2024. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt diff --git a/ref_app/target/micros/rpi_pico_rp2040/startup/secondary_boot.cpp b/ref_app/target/micros/rpi_pico_rp2040/startup/secondary_boot.cpp index ba615d259..84e7c4d93 100644 --- a/ref_app/target/micros/rpi_pico_rp2040/startup/secondary_boot.cpp +++ b/ref_app/target/micros/rpi_pico_rp2040/startup/secondary_boot.cpp @@ -1,14 +1,13 @@ /////////////////////////////////////////////////////////////////////////////// +// Copyright Amine Chalandi 2024. // Copyright Christopher Kormanyos 2024. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt // or copy at http://www.boost.org/LICENSE_1_0.txt) // -// Originally taken from: - /****************************************************************************************** - Filename : SecondaryBoot.c + Filename : SecondaryBoot.c (now secondary_boot.cpp) Core : ARM Cortex-M0+