From d10b9f5ea5c1f2f25eaf592d1f912f2b8522d453 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Tue, 10 Sep 2024 20:00:27 +0200 Subject: [PATCH 1/7] Add but not yet use rpi pico2 2350 files --- readme.md | 2 +- ref_app/ref_app.vcxproj | 144 + ref_app/ref_app.vcxproj.filters | 135 + .../mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.c | 81 + .../mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.h | 35 + .../rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armcc.h | 885 + .../Mcal/Cmsis/cmsis_armclang.h | 707 + .../Mcal/Cmsis/cmsis_armclang_ltm.h | 1928 + .../rpi_pico2_rp2350/Mcal/Cmsis/cmsis_clang.h | 708 + .../Mcal/Cmsis/cmsis_compiler.h | 292 + .../rpi_pico2_rp2350/Mcal/Cmsis/cmsis_gcc.h | 1006 + .../Mcal/Cmsis/cmsis_iccarm.h | 1002 + .../Mcal/Cmsis/cmsis_version.h | 44 + .../Mcal/Cmsis/core_cm0plus.h | 1103 + .../rpi_pico2_rp2350/Mcal/Cmsis/core_cm33.h | 3245 + .../Mcal/Cmsis/m-profile/armv7m_cachel1.h | 439 + .../Mcal/Cmsis/m-profile/armv7m_mpu.h | 273 + .../Mcal/Cmsis/m-profile/armv81m_pac.h | 203 + .../Mcal/Cmsis/m-profile/armv8m_mpu.h | 421 + .../Mcal/Cmsis/m-profile/armv8m_pmu.h | 335 + .../Mcal/Cmsis/m-profile/cmsis_armclang_m.h | 818 + .../Mcal/Cmsis/m-profile/cmsis_clang_m.h | 824 + .../Mcal/Cmsis/m-profile/cmsis_gcc_m.h | 717 + .../Mcal/Cmsis/m-profile/cmsis_iccarm_m.h | 1043 + .../Mcal/Cmsis/m-profile/cmsis_tiarmclang_m.h | 1451 + .../rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv7.h | 275 + .../rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv8.h | 352 + .../rpi_pico2_rp2350/Mcal/Cmsis/tz_context.h | 68 + .../src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c | 155 + .../src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.h | 41 + .../mcal/rpi_pico2_rp2350/Mcal/Gpio/Gpio.h | 62 + .../src/mcal/rpi_pico2_rp2350/Mcal/RP2350.h | 75029 ++++++++++ .../src/mcal/rpi_pico2_rp2350/Mcal/RP2350.svd | 105849 +++++++++++++++ .../Mcal/SysTickTimer/SysTickTimer.c | 68 + .../Mcal/SysTickTimer/SysTickTimer.h | 107 + .../src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.c | 1019 + .../src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.h | 257 + .../rpi_pico2_rp2350/Mcal/USB/usb_hwreg.h | 87 + .../rpi_pico2_rp2350/Mcal/USB/usb_types.h | 133 + ref_app/target.vcxproj | 11 + ref_app/target.vcxproj.filters | 50 +- .../Startup/Core/ARM/IntVect.c | 229 + .../rpi_pico2_rp2350/Startup/Core/ARM/boot.s | 0 .../Startup/Core/ARM/core_arch.h | 26 + .../Startup/Core/ARM/image_definition_block.c | 27 + .../rpi_pico2_rp2350/Startup/Core/ARM/util.s | 34 + .../micros/rpi_pico2_rp2350/Startup/Startup.c | 205 + .../rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld | 144 + .../make/rpi_pico2_rp2350_files.gmk | 18 + .../make/rpi_pico2_rp2350_flags.gmk | 53 + .../rpi_pico_rp2040/make/rpi_pico_rp2040.ld | 8 +- .../make/rpi_pico_rp2040_files.gmk | 2 +- .../make/rpi_pico_rp2040_flags.gmk | 4 +- .../startup/secondary_boot.cpp | 4 +- 54 files changed, 202145 insertions(+), 13 deletions(-) create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.c create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armcc.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armclang.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armclang_ltm.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_clang.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_compiler.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_gcc.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_iccarm.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_version.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/core_cm0plus.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/core_cm33.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv7m_cachel1.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv7m_mpu.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv81m_pac.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv8m_mpu.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv8m_pmu.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_armclang_m.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_clang_m.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_gcc_m.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_iccarm_m.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_tiarmclang_m.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv7.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv8.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/tz_context.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Gpio/Gpio.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/RP2350.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/RP2350.svd create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.c create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.c create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/usb_hwreg.h create mode 100644 ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/usb_types.h create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/IntVect.c create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/boot.s create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/image_definition_block.c create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/util.s create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Startup/Startup.c create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk diff --git a/readme.md b/readme.md index 43843d6fb..702090602 100644 --- a/readme.md +++ b/readme.md @@ -450,7 +450,7 @@ The program toggles the GPIO status LED at GPIO index `0x47`. The `rpi_pico_rp2040` target configuration employs the RaspberryPi(R) Pico RP2040 with dual-core ARM(R) Cortex(R)-M0+ clocked at $133~\text{MHz}$. The low-level startup boots through -core 0. Core 0 then starts up core 1 (via a specifiec protocol). +core 0. Core 0 then starts up core 1 (via a specific protocol). Core 1 subsequently carries out the blinky application, while core 0 enters an endless, idle loop. Ozone debug files are supplied for this system for those interested. diff --git a/ref_app/ref_app.vcxproj b/ref_app/ref_app.vcxproj index f996cf13f..1037a7adc 100644 --- a/ref_app/ref_app.vcxproj +++ b/ref_app/ref_app.vcxproj @@ -572,6 +572,22 @@ true true + + true + true + + + true + true + + + true + true + + + true + true + true true @@ -1843,6 +1859,130 @@ true true + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + true true @@ -2951,6 +3091,10 @@ true true + + true + true + true true diff --git a/ref_app/ref_app.vcxproj.filters b/ref_app/ref_app.vcxproj.filters index 062153ca0..ca4c97ed3 100644 --- a/ref_app/ref_app.vcxproj.filters +++ b/ref_app/ref_app.vcxproj.filters @@ -224,6 +224,33 @@ {98c591b9-2325-4112-a69c-62feaabd4e6b} + + {34136d78-e14c-4045-8d0d-0ad16f33ec9a} + + + {2f061ca1-4483-4a8b-aaee-0ccff4b22769} + + + {2cf60274-f899-454e-8fcc-690618c7ad0e} + + + {f73dba03-036f-4f98-9729-fc2d7336ff26} + + + {4dec0385-4f5d-4129-81b5-da74716ebd79} + + + {5f7361ff-0d9a-4223-bcef-30455fe7d1ea} + + + {efd86679-8e03-4f9d-a44a-2bebc5ab607b} + + + {5e0acfbd-219f-4b10-a237-ea58c3677e31} + + + {2ba6be78-d4c7-4100-ae31-1b1e8ac645a5} + @@ -1117,6 +1144,18 @@ src\mcal\stm32l432 + + src\mcal\rpi_pico2_rp2350\Mcal\Clock + + + src\mcal\rpi_pico2_rp2350\Mcal\Cpu + + + src\mcal\rpi_pico2_rp2350\Mcal\SysTickTimer + + + src\mcal\rpi_pico2_rp2350\Mcal\USB + @@ -2586,6 +2625,99 @@ src\mcal\stm32l432 + + src\mcal\rpi_pico2_rp2350\Mcal + + + src\mcal\rpi_pico2_rp2350\Mcal\Clock + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cmsis\m-profile + + + src\mcal\rpi_pico2_rp2350\Mcal\Cpu + + + src\mcal\rpi_pico2_rp2350\Mcal\Gpio + + + src\mcal\rpi_pico2_rp2350\Mcal\SysTickTimer + + + src\mcal\rpi_pico2_rp2350\Mcal\USB + + + src\mcal\rpi_pico2_rp2350\Mcal\USB + + + src\mcal\rpi_pico2_rp2350\Mcal\USB + @@ -2780,6 +2912,9 @@ src\cmake + + src\mcal\rpi_pico2_rp2350\Mcal + diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.c b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.c new file mode 100644 index 000000000..871074d67 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.c @@ -0,0 +1,81 @@ +/****************************************************************************************** + Filename : Clock.c + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : Clock initialization for RP2350 + +******************************************************************************************/ + +//============================================================================= +// Includes +//============================================================================= +#include "Clock.h" + + +//----------------------------------------------------------------------------------------- +/// \brief RP2350_ClockInit function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +void RP2350_ClockInit(void) +{ + /* Init the clock XOSC */ + HW_PER_XOSC->STARTUP.bit.X4 = 0U; + HW_PER_XOSC->STARTUP.bit.DELAY = 47U; + HW_PER_XOSC->CTRL.bit.FREQ_RANGE = HW_PER_XOSC->STATUS.bit.FREQ_RANGE; + HW_PER_XOSC->CTRL.bit.ENABLE = XOSC_CTRL_ENABLE_ENABLE; + while(HW_PER_XOSC->STATUS.bit.STABLE != 1U); + + /* Switch the ref clock to use the xosc clock as source */ + HW_PER_CLOCKS->CLK_REF_CTRL.bit.SRC = CLOCKS_CLK_REF_CTRL_SRC_xosc_clksrc; + while(HW_PER_CLOCKS->CLK_REF_SELECTED.reg != (1ul << CLOCKS_CLK_REF_CTRL_SRC_xosc_clksrc)); + + while(HW_PER_CLOCKS->CLK_REF_DIV.bit.INT != 1); + + /* Release the reset of PLL_SYS */ + HW_PER_RESETS->RESET.bit.PLL_SYS = 0U; + while(HW_PER_RESETS->RESET_DONE.bit.PLL_SYS != 1); + + /* Configure the PLL_SYS */ + HW_PER_PLL_SYS->CS.bit.REFDIV = 1U; + HW_PER_PLL_SYS->FBDIV_INT.bit.FBDIV_INT = 125U; + HW_PER_PLL_SYS->PRIM.bit.POSTDIV1 = 5U; + HW_PER_PLL_SYS->PRIM.bit.POSTDIV2 = 2U; + + HW_PER_PLL_SYS->PWR.bit.PD = 0U; + HW_PER_PLL_SYS->PWR.bit.VCOPD = 0U; + HW_PER_PLL_SYS->PWR.bit.POSTDIVPD = 0U; + + while(HW_PER_PLL_SYS->CS.bit.LOCK != 1U); + + /* Switch the system clock to use the PLL */ + + if(HW_PER_CLOCKS->CLK_SYS_DIV.reg != 0x10000ul) + HW_PER_CLOCKS->CLK_SYS_DIV.reg = 0x10000ul; + + HW_PER_CLOCKS->CLK_SYS_CTRL.bit.AUXSRC = CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_pll_sys; + HW_PER_CLOCKS->CLK_SYS_CTRL.bit.SRC = CLOCKS_CLK_SYS_CTRL_SRC_clksrc_clk_sys_aux; + + while(HW_PER_CLOCKS->CLK_SYS_SELECTED.bit.CLK_SYS_SELECTED != (1ul << CLOCKS_CLK_SYS_CTRL_SRC_clksrc_clk_sys_aux)); + + /* Enable clock for peripheral */ + HW_PER_CLOCKS->CLK_PERI_CTRL.bit.ENABLE = 1U; + + /* Release reset on IO_BANK0 */ + HW_PER_RESETS->RESET.bit.IO_BANK0 = 0U; + + /* Wait for reset to be done */ + /* Release reset is done on IO_BANK0 */ + while(HW_PER_RESETS->RESET_DONE.bit.IO_BANK0 != 1); +} diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.h new file mode 100644 index 000000000..e1a1f1c87 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Clock/Clock.h @@ -0,0 +1,35 @@ +/****************************************************************************************** + Filename : Clock.h + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : Clock initialization header file for RP2350 + +******************************************************************************************/ +#ifndef __RP2350_CLOCK_H__ +#define __RP2350_CLOCK_H__ + +//============================================================================= +// Includes +//============================================================================= +#include "RP2350.h" +#include "Platform_Types.h" + + + +//============================================================================= +// Functions prototype +//============================================================================= +void RP2350_ClockInit(void); + + + +#endif /*__RP2350_CLOCK_H__*/ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armcc.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armcc.h new file mode 100644 index 000000000..237ff6ec3 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armcc.h @@ -0,0 +1,885 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.2.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armclang.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armclang.h new file mode 100644 index 000000000..446d21a91 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armclang.h @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".bss.noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_armclang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_armclang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_armclang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armclang_ltm.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armclang_ltm.h new file mode 100644 index 000000000..1e255d590 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_clang.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_clang.h new file mode 100644 index 000000000..364d18e14 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_clang.h @@ -0,0 +1,708 @@ +/**************************************************************************//** + * @file cmsis_clang.h + * @brief CMSIS compiler LLVM/Clang header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CLANG_H +#define __CMSIS_CLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) +#include +#else +#error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin +#define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED +#define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT +#define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER +#define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT +#define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS +#define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' +#include "./a-profile/cmsis_clang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' +#include "./r-profile/cmsis_clang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' +#include "./m-profile/cmsis_clang_m.h" +#else +#error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_CLANG_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_compiler.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_compiler.h new file mode 100644 index 000000000..cf3f5b027 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_compiler.h @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Compiler Generic Header File + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler above 6.10.1 (armclang) + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + +/* + * TI Arm Clang Compiler (tiarmclang) + */ +#elif defined (__ti__) + #include "cmsis_tiarmclang.h" + + +/* + * LLVM/Clang Compiler + */ +#elif defined ( __clang__ ) + #include "cmsis_clang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_iccarm_a.h" + #elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_iccarm_r.h" + #elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_iccarm_m.h" + #else + #error "Unknown Arm architecture profile" + #endif + + +/* + * TI Arm Compiler (armcl) + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_gcc.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_gcc.h new file mode 100644 index 000000000..4771466f0 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_gcc.h @@ -0,0 +1,1006 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +#pragma GCC system_header /* treat file as system include file */ + +#include + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return (result); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ + return (int16_t)__builtin_bswap16(value); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__ARM_ARCH_ISA_THUMB >= 2) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if (__ARM_FEATURE_SAT >= 1) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return (result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) + /** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __enable_fault_irq(void) + { + __ASM volatile ("cpsie f" : : : "memory"); + } + + + /** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __disable_fault_irq(void) + { + __ASM volatile ("cpsid f" : : : "memory"); + } +#endif + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define __SADD8 __sadd8 + #define __QADD8 __qadd8 + #define __SHADD8 __shadd8 + #define __UADD8 __uadd8 + #define __UQADD8 __uqadd8 + #define __UHADD8 __uhadd8 + #define __SSUB8 __ssub8 + #define __QSUB8 __qsub8 + #define __SHSUB8 __shsub8 + #define __USUB8 __usub8 + #define __UQSUB8 __uqsub8 + #define __UHSUB8 __uhsub8 + #define __SADD16 __sadd16 + #define __QADD16 __qadd16 + #define __SHADD16 __shadd16 + #define __UADD16 __uadd16 + #define __UQADD16 __uqadd16 + #define __UHADD16 __uhadd16 + #define __SSUB16 __ssub16 + #define __QSUB16 __qsub16 + #define __SHSUB16 __shsub16 + #define __USUB16 __usub16 + #define __UQSUB16 __uqsub16 + #define __UHSUB16 __uhsub16 + #define __SASX __sasx + #define __QASX __qasx + #define __SHASX __shasx + #define __UASX __uasx + #define __UQASX __uqasx + #define __UHASX __uhasx + #define __SSAX __ssax + #define __QSAX __qsax + #define __SHSAX __shsax + #define __USAX __usax + #define __UQSAX __uqsax + #define __UHSAX __uhsax + #define __USAD8 __usad8 + #define __USADA8 __usada8 + #define __SSAT16 __ssat16 + #define __USAT16 __usat16 + #define __UXTB16 __uxtb16 + #define __UXTAB16 __uxtab16 + #define __SXTB16 __sxtb16 + #define __SXTAB16 __sxtab16 + #define __SMUAD __smuad + #define __SMUADX __smuadx + #define __SMLAD __smlad + #define __SMLADX __smladx + #define __SMLALD __smlald + #define __SMLALDX __smlaldx + #define __SMUSD __smusd + #define __SMUSDX __smusdx + #define __SMLSD __smlsd + #define __SMLSDX __smlsdx + #define __SMLSLD __smlsld + #define __SMLSLDX __smlsldx + #define __SEL __sel + #define __QADD __qadd + #define __QSUB __qsub + + #define __PKHBT(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + #define __PKHTB(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) + { + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); + } +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_gcc_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_gcc_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_gcc_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_iccarm.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_iccarm.h new file mode 100644 index 000000000..65b824b00 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_version.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_version.h new file mode 100644 index 000000000..849a8a4a1 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/cmsis_version.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2009-2023 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core Version Definitions + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS-Core(M) Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */ + +/* CMSIS-Core(A) Version definitions */ +#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#endif diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/core_cm0plus.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/core_cm0plus.h new file mode 100644 index 000000000..1ee945756 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/core_cm0plus.h @@ -0,0 +1,1103 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/* NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/core_cm33.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/core_cm33.h new file mode 100644 index 000000000..464bfdd26 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/core_cm33.h @@ -0,0 +1,3245 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be written. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be written + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv7m_cachel1.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv7m_cachel1.h new file mode 100644 index 000000000..d7338a72e --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv7m_cachel1.h @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later + */ + +#ifndef ARM_ARMV7M_CACHEL1_H +#define ARM_ARMV7M_CACHEL1_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + __ALIGNED(__SCB_DCACHE_LINE_SIZE) + #endif + ; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + #if !defined(__OPTIMIZE__) + /* + * For the endless loop issue with no optimization builds. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack. If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + /* Clean and invalidate the local variable cache. */ + #if defined(__ICCARM__) + /* As we can't align the stack to the cache line size, invalidate each of the variables */ + SCB->DCCIMVAC = (uint32_t)&locals.sets; + SCB->DCCIMVAC = (uint32_t)&locals.ways; + SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; + #else + SCB->DCCIMVAC = (uint32_t)&locals; + #endif + __DSB(); + __ISB(); + #endif + + locals.ccsidr = SCB->CCSIDR; + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (locals.ways-- != 0U); + } while(locals.sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_ARMV7M_CACHEL1_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv7m_mpu.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv7m_mpu.h new file mode 100644 index 000000000..5a4eba231 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv7m_mpu.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv7-M MPU + */ + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv81m_pac.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv81m_pac.h new file mode 100644 index 000000000..648cf8864 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv81m_pac.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension + */ + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv8m_mpu.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv8m_mpu.h new file mode 100644 index 000000000..d743af12c --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv8m_mpu.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv8m_pmu.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv8m_pmu.h new file mode 100644 index 000000000..fb1653317 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/armv8m_pmu.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PMU API for Armv8.1-M PMU + */ + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_armclang_m.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_armclang_m.h new file mode 100644 index 000000000..82fb6d46f --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_armclang_m.h @@ -0,0 +1,818 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File + */ + +#ifndef __CMSIS_ARMCLANG_M_H +#define __CMSIS_ARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif +#endif /* (__ARM_ARCH >= 8) */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_M_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_clang_m.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_clang_m.h new file mode 100644 index 000000000..a59444266 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_clang_m.h @@ -0,0 +1,824 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler LLVM/Clang Header File + */ + +#ifndef __CMSIS_CLANG_M_H +#define __CMSIS_CLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __stack +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __stack_limit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __stack_seal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CMSIS_CLANG_M_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_gcc_m.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_gcc_m.h new file mode 100644 index 000000000..54d1f5495 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_gcc_m.h @@ -0,0 +1,717 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler GCC Header File + */ + +#ifndef __CMSIS_GCC_M_H +#define __CMSIS_GCC_M_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +#include + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct __copy_table { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct __zero_table { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CMSIS_GCC_M_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_iccarm_m.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_iccarm_m.h new file mode 100644 index 000000000..cfc6f8083 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_iccarm_m.h @@ -0,0 +1,1043 @@ +/* + * Copyright (c) 2017-2021 IAR Systems + * Copyright (c) 2017-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_M_H__ +#define __CMSIS_ICCARM_M_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #elif __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if defined(__cplusplus) && __cplusplus >= 201103L + #define __NO_RETURN [[noreturn]] + #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define __NO_RETURN _Noreturn + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2) + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + #endif + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if (defined (__ARM_FP) && (__ARM_FP >= 1)) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + + /* + * __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations. + * As a workaround we use inline assembly and a memory barrier. + * (IAR issue EWARM-11901) + */ + #define __CLREX() (__ASM volatile ("CLREX" ::: "memory")) + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!(defined (__ARM_FP) && (__ARM_FP >= 1))) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extension and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ or __ARM_ARCH_8_1M_MAIN__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_M_H__ */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_tiarmclang_m.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_tiarmclang_m.h new file mode 100644 index 000000000..5b193a17a --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/m-profile/cmsis_tiarmclang_m.h @@ -0,0 +1,1451 @@ +/* + * Copyright (c) 2023-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler TIARMClang Header File + */ + +#ifndef __CMSIS_TIARMCLANG_M_H +#define __CMSIS_TIARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _c_int00 +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __STACK_END +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __STACK_SIZE +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +/* __ARM_FEATURE_SAT is wrong for for Armv8-M Baseline devices */ +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_TIARMCLANG_M_H */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv7.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv7.h new file mode 100644 index 000000000..6e27fe321 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.1 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* \brief MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* \brief MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* \brief MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* \brief MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* \brief MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* \brief MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* \brief MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* \brief MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* \brief MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* \brief MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* \brief Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv8.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv8.h new file mode 100644 index 000000000..3de16efc8 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/tz_context.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/tz_context.h new file mode 100644 index 000000000..e095956a8 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cmsis/tz_context.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2017-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core(M) Context Management for Armv8-M TrustZone + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c new file mode 100644 index 000000000..9f6d3d785 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c @@ -0,0 +1,155 @@ +/****************************************************************************************** + Filename : Cpu.c + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : Cpu initialization for RP2350 + +******************************************************************************************/ + +//============================================================================= +// Includes +//============================================================================= +#include "Cpu.h" +#include "core_arch.h" + +//============================================================================= +// Globals +//============================================================================= +static volatile uint32 u32MulticoreSync = 0; + + +//----------------------------------------------------------------------------------------- +/// \brief RP2350_MulticoreSync function +/// +/// \param CpuId : The cpu core identifier +/// +/// \return void +//----------------------------------------------------------------------------------------- +void RP2350_MulticoreSync(uint32 CpuId) +{ + u32MulticoreSync |= (1UL << CpuId); + + while(u32MulticoreSync != MULTICORE_SYNC_MASK); +} + +//----------------------------------------------------------------------------------------- +/// \brief RP2350_StartCore1 function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +void RP2350_InitCore(void) +{ + /* we came here from the RP2350 BootRom and SBL */ + /* Reset core1 to start from a known state */ + + HW_PER_PSM->FRCE_OFF.bit.PROC1 = 1U; + + while((HW_PER_PSM->DONE.bit.PROC1 == 1U)); + + HW_PER_PSM->FRCE_OFF.bit.PROC1 = 0U; + + while((HW_PER_PSM->DONE.bit.PROC1 != 1U)); + + /* Reset peripheral to start from a known state */ + HW_PER_RESETS->RESET.bit.IO_BANK0 = 1U; + HW_PER_RESETS->RESET.bit.PADS_BANK0 = 1U; + + while((HW_PER_RESETS->RESET_DONE.bit.IO_BANK0 == 1U) || (HW_PER_RESETS->RESET_DONE.bit.PADS_BANK0 == 1U)); + + HW_PER_RESETS->RESET.bit.IO_BANK0 = 0U; + HW_PER_RESETS->RESET.bit.PADS_BANK0 = 0U; + + while((HW_PER_RESETS->RESET_DONE.bit.IO_BANK0 == 0U) || (HW_PER_RESETS->RESET_DONE.bit.PADS_BANK0 == 0U)); + +} + +//----------------------------------------------------------------------------------------- +/// \brief RP2350_StartCore1 function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +boolean RP2350_StartCore1(void) +{ + extern uint32 __INTVECT_Core1[2]; + + /* Flush the mailbox */ + while(HW_PER_SIO->FIFO_ST.bit.VLD == 1UL) + { + (void)HW_PER_SIO->FIFO_RD.reg; + } + + /* Send 0 to wakeup the core 1 */ + HW_PER_SIO->FIFO_WR.reg = 0; + CORE_ARCH_SEND_EVENT_INST(); + + while(HW_PER_SIO->FIFO_ST.bit.VLD != 1UL); + + if(HW_PER_SIO->FIFO_RD.reg != 0U) + { + return(FALSE); + } + + /* Send 1 to synchronize with Core 1*/ + HW_PER_SIO->FIFO_WR.reg = 1; + CORE_ARCH_SEND_EVENT_INST(); + + while(HW_PER_SIO->FIFO_ST.bit.VLD != 1UL); + + if(HW_PER_SIO->FIFO_RD.reg != 1U) + { + return(FALSE); + } + + /* Send the VTOR address */ + HW_PER_SIO->FIFO_WR.reg = (uint32)(&__INTVECT_Core1[0]); + CORE_ARCH_SEND_EVENT_INST(); + + while(HW_PER_SIO->FIFO_ST.bit.VLD != 1UL); + + if(HW_PER_SIO->FIFO_RD.reg != (uint32)(&__INTVECT_Core1[0])) + { + return(FALSE); + } + + /* Send the stack pointer value */ + HW_PER_SIO->FIFO_WR.reg = (uint32)__INTVECT_Core1[0]; + CORE_ARCH_SEND_EVENT_INST(); + + while(HW_PER_SIO->FIFO_ST.bit.VLD != 1UL); + + if(HW_PER_SIO->FIFO_RD.reg != (uint32)__INTVECT_Core1[0]) + { + return(FALSE); + } + + /* Send the reset handler */ + HW_PER_SIO->FIFO_WR.reg = (uint32)__INTVECT_Core1[1]; + CORE_ARCH_SEND_EVENT_INST(); + + while(HW_PER_SIO->FIFO_ST.bit.VLD != 1UL); + + + if(HW_PER_SIO->FIFO_RD.reg != (uint32)__INTVECT_Core1[1]) + { + return(FALSE); + } + + /* Clear the stiky bits of the FIFO_ST on core 0 */ + HW_PER_SIO->FIFO_ST.reg = 0xFFu; + + return(TRUE); +} + diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.h new file mode 100644 index 000000000..a11e59adf --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.h @@ -0,0 +1,41 @@ +/****************************************************************************************** + Filename : Cpu.h + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : Cpu initialization header file for RP2350 + +******************************************************************************************/ +#ifndef __RP2350_CPU_H__ +#define __RP2350_CPU_H__ + +//============================================================================= +// Includes +//============================================================================= +#include "RP2350.h" +#include "Platform_Types.h" + +//============================================================================= +// Defines +//============================================================================= +#define CPU_CORE0_ID 0UL +#define CPU_CORE1_ID 1UL + +#define MULTICORE_SYNC_MASK (uint32)((1UL << CPU_CORE0_ID) | (1UL << CPU_CORE1_ID)) + +//============================================================================= +// Functions prototype +//============================================================================= +void RP2350_MulticoreSync(uint32 CpuId); +boolean RP2350_StartCore1(void); +void RP2350_InitCore(void); + +#endif /*__RP2350_CPU_H__*/ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Gpio/Gpio.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Gpio/Gpio.h new file mode 100644 index 000000000..9967e0642 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Gpio/Gpio.h @@ -0,0 +1,62 @@ +/****************************************************************************************** + Filename : Gpio.h + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : GPIO driver header file for RP2350 + +******************************************************************************************/ +#ifndef __RP2350_GPIO_H__ +#define __RP2350_GPIO_H__ + +//============================================================================= +// Includes +//============================================================================= +#include "RP2350.h" +#include "Platform_Types.h" + +//============================================================================= +// Macros +//============================================================================= +#define GPIO_SET_DIRECTION_OUTPUT(pin) HW_PER_SIO->GPIO_OE_CLR.bit.GPIO_OE_CLR |= 1UL<GPIO_OUT_CLR.bit.GPIO_OUT_CLR |= 1UL<GPIO##pin##_CTRL.bit.FUNCSEL = IO_BANK0_GPIO##pin##_CTRL_FUNCSEL_siob_proc_##pin; \ + HW_PER_SIO->GPIO_OE_SET.bit.GPIO_OE_SET |= 1UL<GPIO##pin.bit.ISO = 0u + +#define PIO_SET_DIRECTION_OUTPUT(id, pin) HW_PER_SIO->GPIO_OE_CLR.bit.GPIO_OE_CLR |= 1UL<GPIO_OUT_CLR.bit.GPIO_OUT_CLR |= 1UL<GPIO##pin##_CTRL.bit.FUNCSEL = IO_BANK0_GPIO##pin##_CTRL_FUNCSEL_pio##id##_##pin; \ + HW_PER_SIO->GPIO_OE_SET.bit.GPIO_OE_SET |= 1UL<GPIO_OUT_SET.bit.GPIO_OUT_SET |= 1UL<GPIO_OUT_CLR.bit.GPIO_OUT_CLR |= 1UL<GPIO_OUT_XOR.bit.GPIO_OUT_XOR |= 1UL< max+1, can be changed on-the-fly */ + } bit; + } CLK_GPOUT0_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_GPOUT0_SELECTED : 1; /*!< This slice does not have a glitchless mux (only the AUX_SRC + field is present, not SRC) so this register is hardwired + to 0x1. */ + uint32_t : 31; + } bit; + } CLK_GPOUT0_SELECTED; + + union { + __IOM uint32_t reg; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + + struct { + uint32_t : 5; + __IOM uint32_t AUXSRC : 4; /*!< Selects the auxiliary clock source, will glitch when switching */ + uint32_t : 1; + __IOM uint32_t KILL : 1; /*!< Asynchronously kills the clock generator, enable must be set + low before deasserting kill */ + __IOM uint32_t ENABLE : 1; /*!< Starts and stops the clock generator cleanly */ + __IOM uint32_t DC50 : 1; /*!< Enables duty cycle correction for odd divisors, can be changed + on-the-fly */ + uint32_t : 3; + __IOM uint32_t PHASE : 2; /*!< This delays the enable signal by up to 3 cycles of the input + clock This must be set before the clock is enabled to have + any effect */ + uint32_t : 2; + __IOM uint32_t NUDGE : 1; /*!< An edge on this signal shifts the phase of the output by 1 cycle + of the input clock This can be done at any time */ + uint32_t : 7; + __IM uint32_t ENABLED : 1; /*!< clock generator is enabled */ + uint32_t : 3; + } bit; + } CLK_GPOUT1_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_GPOUT1_DIV */ + + struct { + __IOM uint32_t FRAC : 16; /*!< Fractional component of the divisor, can be changed on-the-fly */ + __IOM uint32_t INT : 16; /*!< Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly */ + } bit; + } CLK_GPOUT1_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_GPOUT1_SELECTED : 1; /*!< This slice does not have a glitchless mux (only the AUX_SRC + field is present, not SRC) so this register is hardwired + to 0x1. */ + uint32_t : 31; + } bit; + } CLK_GPOUT1_SELECTED; + + union { + __IOM uint32_t reg; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + + struct { + uint32_t : 5; + __IOM uint32_t AUXSRC : 4; /*!< Selects the auxiliary clock source, will glitch when switching */ + uint32_t : 1; + __IOM uint32_t KILL : 1; /*!< Asynchronously kills the clock generator, enable must be set + low before deasserting kill */ + __IOM uint32_t ENABLE : 1; /*!< Starts and stops the clock generator cleanly */ + __IOM uint32_t DC50 : 1; /*!< Enables duty cycle correction for odd divisors, can be changed + on-the-fly */ + uint32_t : 3; + __IOM uint32_t PHASE : 2; /*!< This delays the enable signal by up to 3 cycles of the input + clock This must be set before the clock is enabled to have + any effect */ + uint32_t : 2; + __IOM uint32_t NUDGE : 1; /*!< An edge on this signal shifts the phase of the output by 1 cycle + of the input clock This can be done at any time */ + uint32_t : 7; + __IM uint32_t ENABLED : 1; /*!< clock generator is enabled */ + uint32_t : 3; + } bit; + } CLK_GPOUT2_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_GPOUT2_DIV */ + + struct { + __IOM uint32_t FRAC : 16; /*!< Fractional component of the divisor, can be changed on-the-fly */ + __IOM uint32_t INT : 16; /*!< Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly */ + } bit; + } CLK_GPOUT2_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_GPOUT2_SELECTED : 1; /*!< This slice does not have a glitchless mux (only the AUX_SRC + field is present, not SRC) so this register is hardwired + to 0x1. */ + uint32_t : 31; + } bit; + } CLK_GPOUT2_SELECTED; + + union { + __IOM uint32_t reg; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + + struct { + uint32_t : 5; + __IOM uint32_t AUXSRC : 4; /*!< Selects the auxiliary clock source, will glitch when switching */ + uint32_t : 1; + __IOM uint32_t KILL : 1; /*!< Asynchronously kills the clock generator, enable must be set + low before deasserting kill */ + __IOM uint32_t ENABLE : 1; /*!< Starts and stops the clock generator cleanly */ + __IOM uint32_t DC50 : 1; /*!< Enables duty cycle correction for odd divisors, can be changed + on-the-fly */ + uint32_t : 3; + __IOM uint32_t PHASE : 2; /*!< This delays the enable signal by up to 3 cycles of the input + clock This must be set before the clock is enabled to have + any effect */ + uint32_t : 2; + __IOM uint32_t NUDGE : 1; /*!< An edge on this signal shifts the phase of the output by 1 cycle + of the input clock This can be done at any time */ + uint32_t : 7; + __IM uint32_t ENABLED : 1; /*!< clock generator is enabled */ + uint32_t : 3; + } bit; + } CLK_GPOUT3_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_GPOUT3_DIV */ + + struct { + __IOM uint32_t FRAC : 16; /*!< Fractional component of the divisor, can be changed on-the-fly */ + __IOM uint32_t INT : 16; /*!< Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly */ + } bit; + } CLK_GPOUT3_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_GPOUT3_SELECTED : 1; /*!< This slice does not have a glitchless mux (only the AUX_SRC + field is present, not SRC) so this register is hardwired + to 0x1. */ + uint32_t : 31; + } bit; + } CLK_GPOUT3_SELECTED; + + union { + __IOM uint32_t reg; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + + struct { + __IOM uint32_t SRC : 2; /*!< Selects the clock source glitchlessly, can be changed on-the-fly */ + uint32_t : 3; + __IOM uint32_t AUXSRC : 2; /*!< Selects the auxiliary clock source, will glitch when switching */ + uint32_t : 25; + } bit; + } CLK_REF_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_REF_DIV */ + + struct { + uint32_t : 16; + __IOM uint32_t INT : 8; /*!< Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly */ + uint32_t : 8; + } bit; + } CLK_REF_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_REF_SELECTED : 4; /*!< The glitchless multiplexer does not switch instantaneously (to + avoid glitches), so software should poll this register + to wait for the switch to complete. This register contains + one decoded bit for each of the clock sources enumerated + in the CTRL SRC field. At most one of these bits will be + set at any time, indicating that clock is currently present + at the output of the glitchless mux. Whilst switching is + in progress, this register may briefly show all-0s. */ + uint32_t : 28; + } bit; + } CLK_REF_SELECTED; + + union { + __IOM uint32_t reg; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + + struct { + __IOM uint32_t SRC : 1; /*!< Selects the clock source glitchlessly, can be changed on-the-fly */ + uint32_t : 4; + __IOM uint32_t AUXSRC : 3; /*!< Selects the auxiliary clock source, will glitch when switching */ + uint32_t : 24; + } bit; + } CLK_SYS_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_SYS_DIV */ + + struct { + __IOM uint32_t FRAC : 16; /*!< Fractional component of the divisor, can be changed on-the-fly */ + __IOM uint32_t INT : 16; /*!< Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly */ + } bit; + } CLK_SYS_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_SYS_SELECTED : 2; /*!< The glitchless multiplexer does not switch instantaneously (to + avoid glitches), so software should poll this register + to wait for the switch to complete. This register contains + one decoded bit for each of the clock sources enumerated + in the CTRL SRC field. At most one of these bits will be + set at any time, indicating that clock is currently present + at the output of the glitchless mux. Whilst switching is + in progress, this register may briefly show all-0s. */ + uint32_t : 30; + } bit; + } CLK_SYS_SELECTED; + + union { + __IOM uint32_t reg; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + + struct { + uint32_t : 5; + __IOM uint32_t AUXSRC : 3; /*!< Selects the auxiliary clock source, will glitch when switching */ + uint32_t : 2; + __IOM uint32_t KILL : 1; /*!< Asynchronously kills the clock generator, enable must be set + low before deasserting kill */ + __IOM uint32_t ENABLE : 1; /*!< Starts and stops the clock generator cleanly */ + uint32_t : 16; + __IM uint32_t ENABLED : 1; /*!< clock generator is enabled */ + uint32_t : 3; + } bit; + } CLK_PERI_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_PERI_DIV */ + + struct { + uint32_t : 16; + __IOM uint32_t INT : 2; /*!< Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly */ + uint32_t : 14; + } bit; + } CLK_PERI_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_PERI_SELECTED : 1; /*!< This slice does not have a glitchless mux (only the AUX_SRC + field is present, not SRC) so this register is hardwired + to 0x1. */ + uint32_t : 31; + } bit; + } CLK_PERI_SELECTED; + + union { + __IOM uint32_t reg; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + + struct { + uint32_t : 5; + __IOM uint32_t AUXSRC : 3; /*!< Selects the auxiliary clock source, will glitch when switching */ + uint32_t : 2; + __IOM uint32_t KILL : 1; /*!< Asynchronously kills the clock generator, enable must be set + low before deasserting kill */ + __IOM uint32_t ENABLE : 1; /*!< Starts and stops the clock generator cleanly */ + uint32_t : 4; + __IOM uint32_t PHASE : 2; /*!< This delays the enable signal by up to 3 cycles of the input + clock This must be set before the clock is enabled to have + any effect */ + uint32_t : 2; + __IOM uint32_t NUDGE : 1; /*!< An edge on this signal shifts the phase of the output by 1 cycle + of the input clock This can be done at any time */ + uint32_t : 7; + __IM uint32_t ENABLED : 1; /*!< clock generator is enabled */ + uint32_t : 3; + } bit; + } CLK_HSTX_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_HSTX_DIV */ + + struct { + uint32_t : 16; + __IOM uint32_t INT : 2; /*!< Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly */ + uint32_t : 14; + } bit; + } CLK_HSTX_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_HSTX_SELECTED : 1; /*!< This slice does not have a glitchless mux (only the AUX_SRC + field is present, not SRC) so this register is hardwired + to 0x1. */ + uint32_t : 31; + } bit; + } CLK_HSTX_SELECTED; + + union { + __IOM uint32_t reg; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + + struct { + uint32_t : 5; + __IOM uint32_t AUXSRC : 3; /*!< Selects the auxiliary clock source, will glitch when switching */ + uint32_t : 2; + __IOM uint32_t KILL : 1; /*!< Asynchronously kills the clock generator, enable must be set + low before deasserting kill */ + __IOM uint32_t ENABLE : 1; /*!< Starts and stops the clock generator cleanly */ + uint32_t : 4; + __IOM uint32_t PHASE : 2; /*!< This delays the enable signal by up to 3 cycles of the input + clock This must be set before the clock is enabled to have + any effect */ + uint32_t : 2; + __IOM uint32_t NUDGE : 1; /*!< An edge on this signal shifts the phase of the output by 1 cycle + of the input clock This can be done at any time */ + uint32_t : 7; + __IM uint32_t ENABLED : 1; /*!< clock generator is enabled */ + uint32_t : 3; + } bit; + } CLK_USB_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_USB_DIV */ + + struct { + uint32_t : 16; + __IOM uint32_t INT : 4; /*!< Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly */ + uint32_t : 12; + } bit; + } CLK_USB_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_USB_SELECTED : 1; /*!< This slice does not have a glitchless mux (only the AUX_SRC + field is present, not SRC) so this register is hardwired + to 0x1. */ + uint32_t : 31; + } bit; + } CLK_USB_SELECTED; + + union { + __IOM uint32_t reg; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + + struct { + uint32_t : 5; + __IOM uint32_t AUXSRC : 3; /*!< Selects the auxiliary clock source, will glitch when switching */ + uint32_t : 2; + __IOM uint32_t KILL : 1; /*!< Asynchronously kills the clock generator, enable must be set + low before deasserting kill */ + __IOM uint32_t ENABLE : 1; /*!< Starts and stops the clock generator cleanly */ + uint32_t : 4; + __IOM uint32_t PHASE : 2; /*!< This delays the enable signal by up to 3 cycles of the input + clock This must be set before the clock is enabled to have + any effect */ + uint32_t : 2; + __IOM uint32_t NUDGE : 1; /*!< An edge on this signal shifts the phase of the output by 1 cycle + of the input clock This can be done at any time */ + uint32_t : 7; + __IM uint32_t ENABLED : 1; /*!< clock generator is enabled */ + uint32_t : 3; + } bit; + } CLK_ADC_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_ADC_DIV */ + + struct { + uint32_t : 16; + __IOM uint32_t INT : 4; /*!< Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly */ + uint32_t : 12; + } bit; + } CLK_ADC_DIV; + + union { + __IOM uint32_t reg; /*!< Indicates which src is currently selected (one-hot) */ + + struct { + __IM uint32_t CLK_ADC_SELECTED : 1; /*!< This slice does not have a glitchless mux (only the AUX_SRC + field is present, not SRC) so this register is hardwired + to 0x1. */ + uint32_t : 31; + } bit; + } CLK_ADC_SELECTED; + + union { + __IOM uint32_t reg; /*!< DFTCLK_XOSC_CTRL */ + + struct { + __IOM uint32_t SRC : 2; /*!< SRC */ + uint32_t : 30; + } bit; + } DFTCLK_XOSC_CTRL; + + union { + __IOM uint32_t reg; /*!< DFTCLK_ROSC_CTRL */ + + struct { + __IOM uint32_t SRC : 2; /*!< SRC */ + uint32_t : 30; + } bit; + } DFTCLK_ROSC_CTRL; + + union { + __IOM uint32_t reg; /*!< DFTCLK_LPOSC_CTRL */ + + struct { + __IOM uint32_t SRC : 2; /*!< SRC */ + uint32_t : 30; + } bit; + } DFTCLK_LPOSC_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_SYS_RESUS_CTRL */ + + struct { + __IOM uint32_t TIMEOUT : 8; /*!< This is expressed as a number of clk_ref cycles and must be + >= 2x clk_ref_freq/min_clk_tst_freq */ + __IOM uint32_t ENABLE : 1; /*!< Enable resus */ + uint32_t : 3; + __IOM uint32_t FRCE : 1; /*!< Force a resus, for test purposes only */ + uint32_t : 3; + __IOM uint32_t CLEAR : 1; /*!< For clearing the resus after the fault that triggered it has + been corrected */ + uint32_t : 15; + } bit; + } CLK_SYS_RESUS_CTRL; + + union { + __IOM uint32_t reg; /*!< CLK_SYS_RESUS_STATUS */ + + struct { + __IM uint32_t RESUSSED : 1; /*!< Clock has been resuscitated, correct the error then send ctrl_clear=1 */ + uint32_t : 31; + } bit; + } CLK_SYS_RESUS_STATUS; + + union { + __IOM uint32_t reg; /*!< Reference clock frequency in kHz */ + + struct { + __IOM uint32_t FC0_REF_KHZ : 20; /*!< FC0_REF_KHZ */ + uint32_t : 12; + } bit; + } FC0_REF_KHZ; + + union { + __IOM uint32_t reg; /*!< Minimum pass frequency in kHz. This is optional. Set to 0 if + you are not using the pass/fail flags */ + + struct { + __IOM uint32_t FC0_MIN_KHZ : 25; /*!< FC0_MIN_KHZ */ + uint32_t : 7; + } bit; + } FC0_MIN_KHZ; + + union { + __IOM uint32_t reg; /*!< Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff + if you are not using the pass/fail flags */ + + struct { + __IOM uint32_t FC0_MAX_KHZ : 25; /*!< FC0_MAX_KHZ */ + uint32_t : 7; + } bit; + } FC0_MAX_KHZ; + + union { + __IOM uint32_t reg; /*!< Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period */ + + struct { + __IOM uint32_t FC0_DELAY : 3; /*!< FC0_DELAY */ + uint32_t : 29; + } bit; + } FC0_DELAY; + + union { + __IOM uint32_t reg; /*!< The test interval is 0.98us * 2**interval, but let's call it + 1us * 2**interval The default gives a test interval of + 250us */ + + struct { + __IOM uint32_t FC0_INTERVAL : 4; /*!< FC0_INTERVAL */ + uint32_t : 28; + } bit; + } FC0_INTERVAL; + + union { + __IOM uint32_t reg; /*!< Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count */ + + struct { + __IOM uint32_t FC0_SRC : 8; /*!< FC0_SRC */ + uint32_t : 24; + } bit; + } FC0_SRC; + + union { + __IOM uint32_t reg; /*!< Frequency counter status */ + + struct { + __IM uint32_t PASS : 1; /*!< Test passed */ + uint32_t : 3; + __IM uint32_t DONE : 1; /*!< Test complete */ + uint32_t : 3; + __IM uint32_t RUNNING : 1; /*!< Test running */ + uint32_t : 3; + __IM uint32_t WAITING : 1; /*!< Waiting for test clock to start */ + uint32_t : 3; + __IM uint32_t FAIL : 1; /*!< Test failed */ + uint32_t : 3; + __IM uint32_t SLOW : 1; /*!< Test clock slower than expected, only valid when status_done=1 */ + uint32_t : 3; + __IM uint32_t FAST : 1; /*!< Test clock faster than expected, only valid when status_done=1 */ + uint32_t : 3; + __IM uint32_t DIED : 1; /*!< Test clock stopped during test */ + uint32_t : 3; + } bit; + } FC0_STATUS; + + union { + __IOM uint32_t reg; /*!< Result of frequency measurement, only valid when status_done=1 */ + + struct { + __IM uint32_t FRAC : 5; /*!< FRAC */ + __IM uint32_t KHZ : 25; /*!< KHZ */ + uint32_t : 2; + } bit; + } FC0_RESULT; + + union { + __IOM uint32_t reg; /*!< enable clock in wake mode */ + + struct { + __IOM uint32_t CLK_SYS_CLOCKS : 1; /*!< CLK_SYS_CLOCKS */ + __IOM uint32_t CLK_SYS_ACCESSCTRL : 1; /*!< CLK_SYS_ACCESSCTRL */ + __IOM uint32_t CLK_ADC : 1; /*!< CLK_ADC */ + __IOM uint32_t CLK_SYS_ADC : 1; /*!< CLK_SYS_ADC */ + __IOM uint32_t CLK_SYS_BOOTRAM : 1; /*!< CLK_SYS_BOOTRAM */ + __IOM uint32_t CLK_SYS_BUSCTRL : 1; /*!< CLK_SYS_BUSCTRL */ + __IOM uint32_t CLK_SYS_BUSFABRIC : 1; /*!< CLK_SYS_BUSFABRIC */ + __IOM uint32_t CLK_SYS_DMA : 1; /*!< CLK_SYS_DMA */ + __IOM uint32_t CLK_SYS_GLITCH_DETECTOR : 1;/*!< CLK_SYS_GLITCH_DETECTOR */ + __IOM uint32_t CLK_HSTX : 1; /*!< CLK_HSTX */ + __IOM uint32_t CLK_SYS_HSTX : 1; /*!< CLK_SYS_HSTX */ + __IOM uint32_t CLK_SYS_I2C0 : 1; /*!< CLK_SYS_I2C0 */ + __IOM uint32_t CLK_SYS_I2C1 : 1; /*!< CLK_SYS_I2C1 */ + __IOM uint32_t CLK_SYS_IO : 1; /*!< CLK_SYS_IO */ + __IOM uint32_t CLK_SYS_JTAG : 1; /*!< CLK_SYS_JTAG */ + __IOM uint32_t CLK_REF_OTP : 1; /*!< CLK_REF_OTP */ + __IOM uint32_t CLK_SYS_OTP : 1; /*!< CLK_SYS_OTP */ + __IOM uint32_t CLK_SYS_PADS : 1; /*!< CLK_SYS_PADS */ + __IOM uint32_t CLK_SYS_PIO0 : 1; /*!< CLK_SYS_PIO0 */ + __IOM uint32_t CLK_SYS_PIO1 : 1; /*!< CLK_SYS_PIO1 */ + __IOM uint32_t CLK_SYS_PIO2 : 1; /*!< CLK_SYS_PIO2 */ + __IOM uint32_t CLK_SYS_PLL_SYS : 1; /*!< CLK_SYS_PLL_SYS */ + __IOM uint32_t CLK_SYS_PLL_USB : 1; /*!< CLK_SYS_PLL_USB */ + __IOM uint32_t CLK_REF_POWMAN : 1; /*!< CLK_REF_POWMAN */ + __IOM uint32_t CLK_SYS_POWMAN : 1; /*!< CLK_SYS_POWMAN */ + __IOM uint32_t CLK_SYS_PWM : 1; /*!< CLK_SYS_PWM */ + __IOM uint32_t CLK_SYS_RESETS : 1; /*!< CLK_SYS_RESETS */ + __IOM uint32_t CLK_SYS_ROM : 1; /*!< CLK_SYS_ROM */ + __IOM uint32_t CLK_SYS_ROSC : 1; /*!< CLK_SYS_ROSC */ + __IOM uint32_t CLK_SYS_PSM : 1; /*!< CLK_SYS_PSM */ + __IOM uint32_t CLK_SYS_SHA256 : 1; /*!< CLK_SYS_SHA256 */ + __IOM uint32_t CLK_SYS_SIO : 1; /*!< CLK_SYS_SIO */ + } bit; + } WAKE_EN0; + + union { + __IOM uint32_t reg; /*!< enable clock in wake mode */ + + struct { + __IOM uint32_t CLK_PERI_SPI0 : 1; /*!< CLK_PERI_SPI0 */ + __IOM uint32_t CLK_SYS_SPI0 : 1; /*!< CLK_SYS_SPI0 */ + __IOM uint32_t CLK_PERI_SPI1 : 1; /*!< CLK_PERI_SPI1 */ + __IOM uint32_t CLK_SYS_SPI1 : 1; /*!< CLK_SYS_SPI1 */ + __IOM uint32_t CLK_SYS_SRAM0 : 1; /*!< CLK_SYS_SRAM0 */ + __IOM uint32_t CLK_SYS_SRAM1 : 1; /*!< CLK_SYS_SRAM1 */ + __IOM uint32_t CLK_SYS_SRAM2 : 1; /*!< CLK_SYS_SRAM2 */ + __IOM uint32_t CLK_SYS_SRAM3 : 1; /*!< CLK_SYS_SRAM3 */ + __IOM uint32_t CLK_SYS_SRAM4 : 1; /*!< CLK_SYS_SRAM4 */ + __IOM uint32_t CLK_SYS_SRAM5 : 1; /*!< CLK_SYS_SRAM5 */ + __IOM uint32_t CLK_SYS_SRAM6 : 1; /*!< CLK_SYS_SRAM6 */ + __IOM uint32_t CLK_SYS_SRAM7 : 1; /*!< CLK_SYS_SRAM7 */ + __IOM uint32_t CLK_SYS_SRAM8 : 1; /*!< CLK_SYS_SRAM8 */ + __IOM uint32_t CLK_SYS_SRAM9 : 1; /*!< CLK_SYS_SRAM9 */ + __IOM uint32_t CLK_SYS_SYSCFG : 1; /*!< CLK_SYS_SYSCFG */ + __IOM uint32_t CLK_SYS_SYSINFO : 1; /*!< CLK_SYS_SYSINFO */ + __IOM uint32_t CLK_SYS_TBMAN : 1; /*!< CLK_SYS_TBMAN */ + __IOM uint32_t CLK_REF_TICKS : 1; /*!< CLK_REF_TICKS */ + __IOM uint32_t CLK_SYS_TICKS : 1; /*!< CLK_SYS_TICKS */ + __IOM uint32_t CLK_SYS_TIMER0 : 1; /*!< CLK_SYS_TIMER0 */ + __IOM uint32_t CLK_SYS_TIMER1 : 1; /*!< CLK_SYS_TIMER1 */ + __IOM uint32_t CLK_SYS_TRNG : 1; /*!< CLK_SYS_TRNG */ + __IOM uint32_t CLK_PERI_UART0 : 1; /*!< CLK_PERI_UART0 */ + __IOM uint32_t CLK_SYS_UART0 : 1; /*!< CLK_SYS_UART0 */ + __IOM uint32_t CLK_PERI_UART1 : 1; /*!< CLK_PERI_UART1 */ + __IOM uint32_t CLK_SYS_UART1 : 1; /*!< CLK_SYS_UART1 */ + __IOM uint32_t CLK_SYS_USBCTRL : 1; /*!< CLK_SYS_USBCTRL */ + __IOM uint32_t CLK_USB : 1; /*!< CLK_USB */ + __IOM uint32_t CLK_SYS_WATCHDOG : 1; /*!< CLK_SYS_WATCHDOG */ + __IOM uint32_t CLK_SYS_XIP : 1; /*!< CLK_SYS_XIP */ + __IOM uint32_t CLK_SYS_XOSC : 1; /*!< CLK_SYS_XOSC */ + uint32_t : 1; + } bit; + } WAKE_EN1; + + union { + __IOM uint32_t reg; /*!< enable clock in sleep mode */ + + struct { + __IOM uint32_t CLK_SYS_CLOCKS : 1; /*!< CLK_SYS_CLOCKS */ + __IOM uint32_t CLK_SYS_ACCESSCTRL : 1; /*!< CLK_SYS_ACCESSCTRL */ + __IOM uint32_t CLK_ADC : 1; /*!< CLK_ADC */ + __IOM uint32_t CLK_SYS_ADC : 1; /*!< CLK_SYS_ADC */ + __IOM uint32_t CLK_SYS_BOOTRAM : 1; /*!< CLK_SYS_BOOTRAM */ + __IOM uint32_t CLK_SYS_BUSCTRL : 1; /*!< CLK_SYS_BUSCTRL */ + __IOM uint32_t CLK_SYS_BUSFABRIC : 1; /*!< CLK_SYS_BUSFABRIC */ + __IOM uint32_t CLK_SYS_DMA : 1; /*!< CLK_SYS_DMA */ + __IOM uint32_t CLK_SYS_GLITCH_DETECTOR : 1;/*!< CLK_SYS_GLITCH_DETECTOR */ + __IOM uint32_t CLK_HSTX : 1; /*!< CLK_HSTX */ + __IOM uint32_t CLK_SYS_HSTX : 1; /*!< CLK_SYS_HSTX */ + __IOM uint32_t CLK_SYS_I2C0 : 1; /*!< CLK_SYS_I2C0 */ + __IOM uint32_t CLK_SYS_I2C1 : 1; /*!< CLK_SYS_I2C1 */ + __IOM uint32_t CLK_SYS_IO : 1; /*!< CLK_SYS_IO */ + __IOM uint32_t CLK_SYS_JTAG : 1; /*!< CLK_SYS_JTAG */ + __IOM uint32_t CLK_REF_OTP : 1; /*!< CLK_REF_OTP */ + __IOM uint32_t CLK_SYS_OTP : 1; /*!< CLK_SYS_OTP */ + __IOM uint32_t CLK_SYS_PADS : 1; /*!< CLK_SYS_PADS */ + __IOM uint32_t CLK_SYS_PIO0 : 1; /*!< CLK_SYS_PIO0 */ + __IOM uint32_t CLK_SYS_PIO1 : 1; /*!< CLK_SYS_PIO1 */ + __IOM uint32_t CLK_SYS_PIO2 : 1; /*!< CLK_SYS_PIO2 */ + __IOM uint32_t CLK_SYS_PLL_SYS : 1; /*!< CLK_SYS_PLL_SYS */ + __IOM uint32_t CLK_SYS_PLL_USB : 1; /*!< CLK_SYS_PLL_USB */ + __IOM uint32_t CLK_REF_POWMAN : 1; /*!< CLK_REF_POWMAN */ + __IOM uint32_t CLK_SYS_POWMAN : 1; /*!< CLK_SYS_POWMAN */ + __IOM uint32_t CLK_SYS_PWM : 1; /*!< CLK_SYS_PWM */ + __IOM uint32_t CLK_SYS_RESETS : 1; /*!< CLK_SYS_RESETS */ + __IOM uint32_t CLK_SYS_ROM : 1; /*!< CLK_SYS_ROM */ + __IOM uint32_t CLK_SYS_ROSC : 1; /*!< CLK_SYS_ROSC */ + __IOM uint32_t CLK_SYS_PSM : 1; /*!< CLK_SYS_PSM */ + __IOM uint32_t CLK_SYS_SHA256 : 1; /*!< CLK_SYS_SHA256 */ + __IOM uint32_t CLK_SYS_SIO : 1; /*!< CLK_SYS_SIO */ + } bit; + } SLEEP_EN0; + + union { + __IOM uint32_t reg; /*!< enable clock in sleep mode */ + + struct { + __IOM uint32_t CLK_PERI_SPI0 : 1; /*!< CLK_PERI_SPI0 */ + __IOM uint32_t CLK_SYS_SPI0 : 1; /*!< CLK_SYS_SPI0 */ + __IOM uint32_t CLK_PERI_SPI1 : 1; /*!< CLK_PERI_SPI1 */ + __IOM uint32_t CLK_SYS_SPI1 : 1; /*!< CLK_SYS_SPI1 */ + __IOM uint32_t CLK_SYS_SRAM0 : 1; /*!< CLK_SYS_SRAM0 */ + __IOM uint32_t CLK_SYS_SRAM1 : 1; /*!< CLK_SYS_SRAM1 */ + __IOM uint32_t CLK_SYS_SRAM2 : 1; /*!< CLK_SYS_SRAM2 */ + __IOM uint32_t CLK_SYS_SRAM3 : 1; /*!< CLK_SYS_SRAM3 */ + __IOM uint32_t CLK_SYS_SRAM4 : 1; /*!< CLK_SYS_SRAM4 */ + __IOM uint32_t CLK_SYS_SRAM5 : 1; /*!< CLK_SYS_SRAM5 */ + __IOM uint32_t CLK_SYS_SRAM6 : 1; /*!< CLK_SYS_SRAM6 */ + __IOM uint32_t CLK_SYS_SRAM7 : 1; /*!< CLK_SYS_SRAM7 */ + __IOM uint32_t CLK_SYS_SRAM8 : 1; /*!< CLK_SYS_SRAM8 */ + __IOM uint32_t CLK_SYS_SRAM9 : 1; /*!< CLK_SYS_SRAM9 */ + __IOM uint32_t CLK_SYS_SYSCFG : 1; /*!< CLK_SYS_SYSCFG */ + __IOM uint32_t CLK_SYS_SYSINFO : 1; /*!< CLK_SYS_SYSINFO */ + __IOM uint32_t CLK_SYS_TBMAN : 1; /*!< CLK_SYS_TBMAN */ + __IOM uint32_t CLK_REF_TICKS : 1; /*!< CLK_REF_TICKS */ + __IOM uint32_t CLK_SYS_TICKS : 1; /*!< CLK_SYS_TICKS */ + __IOM uint32_t CLK_SYS_TIMER0 : 1; /*!< CLK_SYS_TIMER0 */ + __IOM uint32_t CLK_SYS_TIMER1 : 1; /*!< CLK_SYS_TIMER1 */ + __IOM uint32_t CLK_SYS_TRNG : 1; /*!< CLK_SYS_TRNG */ + __IOM uint32_t CLK_PERI_UART0 : 1; /*!< CLK_PERI_UART0 */ + __IOM uint32_t CLK_SYS_UART0 : 1; /*!< CLK_SYS_UART0 */ + __IOM uint32_t CLK_PERI_UART1 : 1; /*!< CLK_PERI_UART1 */ + __IOM uint32_t CLK_SYS_UART1 : 1; /*!< CLK_SYS_UART1 */ + __IOM uint32_t CLK_SYS_USBCTRL : 1; /*!< CLK_SYS_USBCTRL */ + __IOM uint32_t CLK_USB : 1; /*!< CLK_USB */ + __IOM uint32_t CLK_SYS_WATCHDOG : 1; /*!< CLK_SYS_WATCHDOG */ + __IOM uint32_t CLK_SYS_XIP : 1; /*!< CLK_SYS_XIP */ + __IOM uint32_t CLK_SYS_XOSC : 1; /*!< CLK_SYS_XOSC */ + uint32_t : 1; + } bit; + } SLEEP_EN1; + + union { + __IOM uint32_t reg; /*!< indicates the state of the clock enable */ + + struct { + __IM uint32_t CLK_SYS_CLOCKS : 1; /*!< CLK_SYS_CLOCKS */ + __IM uint32_t CLK_SYS_ACCESSCTRL : 1; /*!< CLK_SYS_ACCESSCTRL */ + __IM uint32_t CLK_ADC : 1; /*!< CLK_ADC */ + __IM uint32_t CLK_SYS_ADC : 1; /*!< CLK_SYS_ADC */ + __IM uint32_t CLK_SYS_BOOTRAM : 1; /*!< CLK_SYS_BOOTRAM */ + __IM uint32_t CLK_SYS_BUSCTRL : 1; /*!< CLK_SYS_BUSCTRL */ + __IM uint32_t CLK_SYS_BUSFABRIC : 1; /*!< CLK_SYS_BUSFABRIC */ + __IM uint32_t CLK_SYS_DMA : 1; /*!< CLK_SYS_DMA */ + __IM uint32_t CLK_SYS_GLITCH_DETECTOR : 1;/*!< CLK_SYS_GLITCH_DETECTOR */ + __IM uint32_t CLK_HSTX : 1; /*!< CLK_HSTX */ + __IM uint32_t CLK_SYS_HSTX : 1; /*!< CLK_SYS_HSTX */ + __IM uint32_t CLK_SYS_I2C0 : 1; /*!< CLK_SYS_I2C0 */ + __IM uint32_t CLK_SYS_I2C1 : 1; /*!< CLK_SYS_I2C1 */ + __IM uint32_t CLK_SYS_IO : 1; /*!< CLK_SYS_IO */ + __IM uint32_t CLK_SYS_JTAG : 1; /*!< CLK_SYS_JTAG */ + __IM uint32_t CLK_REF_OTP : 1; /*!< CLK_REF_OTP */ + __IM uint32_t CLK_SYS_OTP : 1; /*!< CLK_SYS_OTP */ + __IM uint32_t CLK_SYS_PADS : 1; /*!< CLK_SYS_PADS */ + __IM uint32_t CLK_SYS_PIO0 : 1; /*!< CLK_SYS_PIO0 */ + __IM uint32_t CLK_SYS_PIO1 : 1; /*!< CLK_SYS_PIO1 */ + __IM uint32_t CLK_SYS_PIO2 : 1; /*!< CLK_SYS_PIO2 */ + __IM uint32_t CLK_SYS_PLL_SYS : 1; /*!< CLK_SYS_PLL_SYS */ + __IM uint32_t CLK_SYS_PLL_USB : 1; /*!< CLK_SYS_PLL_USB */ + __IM uint32_t CLK_REF_POWMAN : 1; /*!< CLK_REF_POWMAN */ + __IM uint32_t CLK_SYS_POWMAN : 1; /*!< CLK_SYS_POWMAN */ + __IM uint32_t CLK_SYS_PWM : 1; /*!< CLK_SYS_PWM */ + __IM uint32_t CLK_SYS_RESETS : 1; /*!< CLK_SYS_RESETS */ + __IM uint32_t CLK_SYS_ROM : 1; /*!< CLK_SYS_ROM */ + __IM uint32_t CLK_SYS_ROSC : 1; /*!< CLK_SYS_ROSC */ + __IM uint32_t CLK_SYS_PSM : 1; /*!< CLK_SYS_PSM */ + __IM uint32_t CLK_SYS_SHA256 : 1; /*!< CLK_SYS_SHA256 */ + __IM uint32_t CLK_SYS_SIO : 1; /*!< CLK_SYS_SIO */ + } bit; + } ENABLED0; + + union { + __IOM uint32_t reg; /*!< indicates the state of the clock enable */ + + struct { + __IM uint32_t CLK_PERI_SPI0 : 1; /*!< CLK_PERI_SPI0 */ + __IM uint32_t CLK_SYS_SPI0 : 1; /*!< CLK_SYS_SPI0 */ + __IM uint32_t CLK_PERI_SPI1 : 1; /*!< CLK_PERI_SPI1 */ + __IM uint32_t CLK_SYS_SPI1 : 1; /*!< CLK_SYS_SPI1 */ + __IM uint32_t CLK_SYS_SRAM0 : 1; /*!< CLK_SYS_SRAM0 */ + __IM uint32_t CLK_SYS_SRAM1 : 1; /*!< CLK_SYS_SRAM1 */ + __IM uint32_t CLK_SYS_SRAM2 : 1; /*!< CLK_SYS_SRAM2 */ + __IM uint32_t CLK_SYS_SRAM3 : 1; /*!< CLK_SYS_SRAM3 */ + __IM uint32_t CLK_SYS_SRAM4 : 1; /*!< CLK_SYS_SRAM4 */ + __IM uint32_t CLK_SYS_SRAM5 : 1; /*!< CLK_SYS_SRAM5 */ + __IM uint32_t CLK_SYS_SRAM6 : 1; /*!< CLK_SYS_SRAM6 */ + __IM uint32_t CLK_SYS_SRAM7 : 1; /*!< CLK_SYS_SRAM7 */ + __IM uint32_t CLK_SYS_SRAM8 : 1; /*!< CLK_SYS_SRAM8 */ + __IM uint32_t CLK_SYS_SRAM9 : 1; /*!< CLK_SYS_SRAM9 */ + __IM uint32_t CLK_SYS_SYSCFG : 1; /*!< CLK_SYS_SYSCFG */ + __IM uint32_t CLK_SYS_SYSINFO : 1; /*!< CLK_SYS_SYSINFO */ + __IM uint32_t CLK_SYS_TBMAN : 1; /*!< CLK_SYS_TBMAN */ + __IM uint32_t CLK_REF_TICKS : 1; /*!< CLK_REF_TICKS */ + __IM uint32_t CLK_SYS_TICKS : 1; /*!< CLK_SYS_TICKS */ + __IM uint32_t CLK_SYS_TIMER0 : 1; /*!< CLK_SYS_TIMER0 */ + __IM uint32_t CLK_SYS_TIMER1 : 1; /*!< CLK_SYS_TIMER1 */ + __IM uint32_t CLK_SYS_TRNG : 1; /*!< CLK_SYS_TRNG */ + __IM uint32_t CLK_PERI_UART0 : 1; /*!< CLK_PERI_UART0 */ + __IM uint32_t CLK_SYS_UART0 : 1; /*!< CLK_SYS_UART0 */ + __IM uint32_t CLK_PERI_UART1 : 1; /*!< CLK_PERI_UART1 */ + __IM uint32_t CLK_SYS_UART1 : 1; /*!< CLK_SYS_UART1 */ + __IM uint32_t CLK_SYS_USBCTRL : 1; /*!< CLK_SYS_USBCTRL */ + __IM uint32_t CLK_USB : 1; /*!< CLK_USB */ + __IM uint32_t CLK_SYS_WATCHDOG : 1; /*!< CLK_SYS_WATCHDOG */ + __IM uint32_t CLK_SYS_XIP : 1; /*!< CLK_SYS_XIP */ + __IM uint32_t CLK_SYS_XOSC : 1; /*!< CLK_SYS_XOSC */ + uint32_t : 1; + } bit; + } ENABLED1; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t CLK_SYS_RESUS : 1; /*!< CLK_SYS_RESUS */ + uint32_t : 31; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable */ + + struct { + __IOM uint32_t CLK_SYS_RESUS : 1; /*!< CLK_SYS_RESUS */ + uint32_t : 31; + } bit; + } INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force */ + + struct { + __IOM uint32_t CLK_SYS_RESUS : 1; /*!< CLK_SYS_RESUS */ + uint32_t : 31; + } bit; + } INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing */ + + struct { + __IM uint32_t CLK_SYS_RESUS : 1; /*!< CLK_SYS_RESUS */ + uint32_t : 31; + } bit; + } INTS; +} CLOCKS_Type; /*!< Size = 212 (0xd4) */ + + + +/* =========================================================================================================================== */ +/* ================ TICKS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TICKS (TICKS) + */ + +typedef struct { /*!< TICKS Structure */ + + union { + __IOM uint32_t reg; /*!< Controls the tick generator */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< start / stop tick generation */ + __IM uint32_t RUNNING : 1; /*!< Is the tick generator running? */ + uint32_t : 30; + } bit; + } PROC0_CTRL; + + union { + __IOM uint32_t reg; /*!< PROC0_CYCLES */ + + struct { + __IOM uint32_t PROC0_CYCLES : 9; /*!< Total number of clk_tick cycles before the next tick. */ + uint32_t : 23; + } bit; + } PROC0_CYCLES; + + union { + __IOM uint32_t reg; /*!< PROC0_COUNT */ + + struct { + __IM uint32_t PROC0_COUNT : 9; /*!< Count down timer: the remaining number clk_tick cycles before + the next tick is generated. */ + uint32_t : 23; + } bit; + } PROC0_COUNT; + + union { + __IOM uint32_t reg; /*!< Controls the tick generator */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< start / stop tick generation */ + __IM uint32_t RUNNING : 1; /*!< Is the tick generator running? */ + uint32_t : 30; + } bit; + } PROC1_CTRL; + + union { + __IOM uint32_t reg; /*!< PROC1_CYCLES */ + + struct { + __IOM uint32_t PROC1_CYCLES : 9; /*!< Total number of clk_tick cycles before the next tick. */ + uint32_t : 23; + } bit; + } PROC1_CYCLES; + + union { + __IOM uint32_t reg; /*!< PROC1_COUNT */ + + struct { + __IM uint32_t PROC1_COUNT : 9; /*!< Count down timer: the remaining number clk_tick cycles before + the next tick is generated. */ + uint32_t : 23; + } bit; + } PROC1_COUNT; + + union { + __IOM uint32_t reg; /*!< Controls the tick generator */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< start / stop tick generation */ + __IM uint32_t RUNNING : 1; /*!< Is the tick generator running? */ + uint32_t : 30; + } bit; + } TIMER0_CTRL; + + union { + __IOM uint32_t reg; /*!< TIMER0_CYCLES */ + + struct { + __IOM uint32_t TIMER0_CYCLES : 9; /*!< Total number of clk_tick cycles before the next tick. */ + uint32_t : 23; + } bit; + } TIMER0_CYCLES; + + union { + __IOM uint32_t reg; /*!< TIMER0_COUNT */ + + struct { + __IM uint32_t TIMER0_COUNT : 9; /*!< Count down timer: the remaining number clk_tick cycles before + the next tick is generated. */ + uint32_t : 23; + } bit; + } TIMER0_COUNT; + + union { + __IOM uint32_t reg; /*!< Controls the tick generator */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< start / stop tick generation */ + __IM uint32_t RUNNING : 1; /*!< Is the tick generator running? */ + uint32_t : 30; + } bit; + } TIMER1_CTRL; + + union { + __IOM uint32_t reg; /*!< TIMER1_CYCLES */ + + struct { + __IOM uint32_t TIMER1_CYCLES : 9; /*!< Total number of clk_tick cycles before the next tick. */ + uint32_t : 23; + } bit; + } TIMER1_CYCLES; + + union { + __IOM uint32_t reg; /*!< TIMER1_COUNT */ + + struct { + __IM uint32_t TIMER1_COUNT : 9; /*!< Count down timer: the remaining number clk_tick cycles before + the next tick is generated. */ + uint32_t : 23; + } bit; + } TIMER1_COUNT; + + union { + __IOM uint32_t reg; /*!< Controls the tick generator */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< start / stop tick generation */ + __IM uint32_t RUNNING : 1; /*!< Is the tick generator running? */ + uint32_t : 30; + } bit; + } WATCHDOG_CTRL; + + union { + __IOM uint32_t reg; /*!< WATCHDOG_CYCLES */ + + struct { + __IOM uint32_t WATCHDOG_CYCLES : 9; /*!< Total number of clk_tick cycles before the next tick. */ + uint32_t : 23; + } bit; + } WATCHDOG_CYCLES; + + union { + __IOM uint32_t reg; /*!< WATCHDOG_COUNT */ + + struct { + __IM uint32_t WATCHDOG_COUNT : 9; /*!< Count down timer: the remaining number clk_tick cycles before + the next tick is generated. */ + uint32_t : 23; + } bit; + } WATCHDOG_COUNT; + + union { + __IOM uint32_t reg; /*!< Controls the tick generator */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< start / stop tick generation */ + __IM uint32_t RUNNING : 1; /*!< Is the tick generator running? */ + uint32_t : 30; + } bit; + } RISCV_CTRL; + + union { + __IOM uint32_t reg; /*!< RISCV_CYCLES */ + + struct { + __IOM uint32_t RISCV_CYCLES : 9; /*!< Total number of clk_tick cycles before the next tick. */ + uint32_t : 23; + } bit; + } RISCV_CYCLES; + + union { + __IOM uint32_t reg; /*!< RISCV_COUNT */ + + struct { + __IM uint32_t RISCV_COUNT : 9; /*!< Count down timer: the remaining number clk_tick cycles before + the next tick is generated. */ + uint32_t : 23; + } bit; + } RISCV_COUNT; +} TICKS_Type; /*!< Size = 72 (0x48) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_BANK0 (PADS_BANK0) + */ + +typedef struct { /*!< PADS_BANK0 Structure */ + + union { + __IOM uint32_t reg; /*!< Voltage select. Per bank control */ + + struct { + __IOM uint32_t VOLTAGE_SELECT : 1; /*!< VOLTAGE_SELECT */ + uint32_t : 31; + } bit; + } VOLTAGE_SELECT; + + union { + __IOM uint32_t reg; /*!< GPIO0 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO0; + + union { + __IOM uint32_t reg; /*!< GPIO1 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO1; + + union { + __IOM uint32_t reg; /*!< GPIO2 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO2; + + union { + __IOM uint32_t reg; /*!< GPIO3 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO3; + + union { + __IOM uint32_t reg; /*!< GPIO4 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO4; + + union { + __IOM uint32_t reg; /*!< GPIO5 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO5; + + union { + __IOM uint32_t reg; /*!< GPIO6 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO6; + + union { + __IOM uint32_t reg; /*!< GPIO7 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO7; + + union { + __IOM uint32_t reg; /*!< GPIO8 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO8; + + union { + __IOM uint32_t reg; /*!< GPIO9 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO9; + + union { + __IOM uint32_t reg; /*!< GPIO10 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO10; + + union { + __IOM uint32_t reg; /*!< GPIO11 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO11; + + union { + __IOM uint32_t reg; /*!< GPIO12 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO12; + + union { + __IOM uint32_t reg; /*!< GPIO13 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO13; + + union { + __IOM uint32_t reg; /*!< GPIO14 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO14; + + union { + __IOM uint32_t reg; /*!< GPIO15 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO15; + + union { + __IOM uint32_t reg; /*!< GPIO16 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO16; + + union { + __IOM uint32_t reg; /*!< GPIO17 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO17; + + union { + __IOM uint32_t reg; /*!< GPIO18 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO18; + + union { + __IOM uint32_t reg; /*!< GPIO19 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO19; + + union { + __IOM uint32_t reg; /*!< GPIO20 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO20; + + union { + __IOM uint32_t reg; /*!< GPIO21 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO21; + + union { + __IOM uint32_t reg; /*!< GPIO22 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO22; + + union { + __IOM uint32_t reg; /*!< GPIO23 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO23; + + union { + __IOM uint32_t reg; /*!< GPIO24 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO24; + + union { + __IOM uint32_t reg; /*!< GPIO25 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO25; + + union { + __IOM uint32_t reg; /*!< GPIO26 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO26; + + union { + __IOM uint32_t reg; /*!< GPIO27 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO27; + + union { + __IOM uint32_t reg; /*!< GPIO28 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO28; + + union { + __IOM uint32_t reg; /*!< GPIO29 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO29; + + union { + __IOM uint32_t reg; /*!< GPIO30 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO30; + + union { + __IOM uint32_t reg; /*!< GPIO31 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO31; + + union { + __IOM uint32_t reg; /*!< GPIO32 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO32; + + union { + __IOM uint32_t reg; /*!< GPIO33 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO33; + + union { + __IOM uint32_t reg; /*!< GPIO34 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO34; + + union { + __IOM uint32_t reg; /*!< GPIO35 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO35; + + union { + __IOM uint32_t reg; /*!< GPIO36 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO36; + + union { + __IOM uint32_t reg; /*!< GPIO37 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO37; + + union { + __IOM uint32_t reg; /*!< GPIO38 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO38; + + union { + __IOM uint32_t reg; /*!< GPIO39 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO39; + + union { + __IOM uint32_t reg; /*!< GPIO40 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO40; + + union { + __IOM uint32_t reg; /*!< GPIO41 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO41; + + union { + __IOM uint32_t reg; /*!< GPIO42 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO42; + + union { + __IOM uint32_t reg; /*!< GPIO43 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO43; + + union { + __IOM uint32_t reg; /*!< GPIO44 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO44; + + union { + __IOM uint32_t reg; /*!< GPIO45 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO45; + + union { + __IOM uint32_t reg; /*!< GPIO46 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO46; + + union { + __IOM uint32_t reg; /*!< GPIO47 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO47; + + union { + __IOM uint32_t reg; /*!< SWCLK */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } SWCLK; + + union { + __IOM uint32_t reg; /*!< SWD */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } SWD; +} PADS_BANK0_Type; /*!< Size = 204 (0xcc) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_QSPI (PADS_QSPI) + */ + +typedef struct { /*!< PADS_QSPI Structure */ + + union { + __IOM uint32_t reg; /*!< Voltage select. Per bank control */ + + struct { + __IOM uint32_t VOLTAGE_SELECT : 1; /*!< VOLTAGE_SELECT */ + uint32_t : 31; + } bit; + } VOLTAGE_SELECT; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SCLK */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO_QSPI_SCLK; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD0 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO_QSPI_SD0; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD1 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO_QSPI_SD1; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD2 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO_QSPI_SD2; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD3 */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO_QSPI_SD3; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SS */ + + struct { + __IOM uint32_t SLEWFAST : 1; /*!< Slew rate control. 1 = Fast, 0 = Slow */ + __IOM uint32_t SCHMITT : 1; /*!< Enable schmitt trigger */ + __IOM uint32_t PDE : 1; /*!< Pull down enable */ + __IOM uint32_t PUE : 1; /*!< Pull up enable */ + __IOM uint32_t DRIVE : 2; /*!< Drive strength. */ + __IOM uint32_t IE : 1; /*!< Input enable */ + __IOM uint32_t OD : 1; /*!< Output disable. Has priority over output enable from peripherals */ + __IOM uint32_t ISO : 1; /*!< Pad isolation control. Remove this once the pad is configured + by software. */ + uint32_t : 23; + } bit; + } GPIO_QSPI_SS; +} PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_QSPI (IO_QSPI) + */ + +typedef struct { /*!< IO_QSPI Structure */ + + union { + __IOM uint32_t reg; /*!< USBPHY_DP_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } USBPHY_DP_STATUS; + + union { + __IOM uint32_t reg; /*!< USBPHY_DP_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } USBPHY_DP_CTRL; + + union { + __IOM uint32_t reg; /*!< USBPHY_DM_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } USBPHY_DM_STATUS; + + union { + __IOM uint32_t reg; /*!< USBPHY_DM_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } USBPHY_DM_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SCLK_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO_QSPI_SCLK_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SCLK_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO_QSPI_SCLK_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SS_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO_QSPI_SS_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SS_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO_QSPI_SS_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD0_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO_QSPI_SD0_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD0_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO_QSPI_SD0_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD1_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO_QSPI_SD1_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD1_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO_QSPI_SD1_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD2_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO_QSPI_SD2_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD2_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO_QSPI_SD2_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD3_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO_QSPI_SD3_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO_QSPI_SD3_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO_QSPI_SD3_CTRL; + __IM uint32_t RESERVED[112]; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC0_SECURE */ + + struct { + __IM uint32_t USBPHY_DP : 1; /*!< USBPHY_DP */ + __IM uint32_t USBPHY_DM : 1; /*!< USBPHY_DM */ + __IM uint32_t GPIO_QSPI_SCLK : 1; /*!< GPIO_QSPI_SCLK */ + __IM uint32_t GPIO_QSPI_SS : 1; /*!< GPIO_QSPI_SS */ + __IM uint32_t GPIO_QSPI_SD0 : 1; /*!< GPIO_QSPI_SD0 */ + __IM uint32_t GPIO_QSPI_SD1 : 1; /*!< GPIO_QSPI_SD1 */ + __IM uint32_t GPIO_QSPI_SD2 : 1; /*!< GPIO_QSPI_SD2 */ + __IM uint32_t GPIO_QSPI_SD3 : 1; /*!< GPIO_QSPI_SD3 */ + uint32_t : 24; + } bit; + } IRQSUMMARY_PROC0_SECURE; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC0_NONSECURE */ + + struct { + __IM uint32_t USBPHY_DP : 1; /*!< USBPHY_DP */ + __IM uint32_t USBPHY_DM : 1; /*!< USBPHY_DM */ + __IM uint32_t GPIO_QSPI_SCLK : 1; /*!< GPIO_QSPI_SCLK */ + __IM uint32_t GPIO_QSPI_SS : 1; /*!< GPIO_QSPI_SS */ + __IM uint32_t GPIO_QSPI_SD0 : 1; /*!< GPIO_QSPI_SD0 */ + __IM uint32_t GPIO_QSPI_SD1 : 1; /*!< GPIO_QSPI_SD1 */ + __IM uint32_t GPIO_QSPI_SD2 : 1; /*!< GPIO_QSPI_SD2 */ + __IM uint32_t GPIO_QSPI_SD3 : 1; /*!< GPIO_QSPI_SD3 */ + uint32_t : 24; + } bit; + } IRQSUMMARY_PROC0_NONSECURE; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC1_SECURE */ + + struct { + __IM uint32_t USBPHY_DP : 1; /*!< USBPHY_DP */ + __IM uint32_t USBPHY_DM : 1; /*!< USBPHY_DM */ + __IM uint32_t GPIO_QSPI_SCLK : 1; /*!< GPIO_QSPI_SCLK */ + __IM uint32_t GPIO_QSPI_SS : 1; /*!< GPIO_QSPI_SS */ + __IM uint32_t GPIO_QSPI_SD0 : 1; /*!< GPIO_QSPI_SD0 */ + __IM uint32_t GPIO_QSPI_SD1 : 1; /*!< GPIO_QSPI_SD1 */ + __IM uint32_t GPIO_QSPI_SD2 : 1; /*!< GPIO_QSPI_SD2 */ + __IM uint32_t GPIO_QSPI_SD3 : 1; /*!< GPIO_QSPI_SD3 */ + uint32_t : 24; + } bit; + } IRQSUMMARY_PROC1_SECURE; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC1_NONSECURE */ + + struct { + __IM uint32_t USBPHY_DP : 1; /*!< USBPHY_DP */ + __IM uint32_t USBPHY_DM : 1; /*!< USBPHY_DM */ + __IM uint32_t GPIO_QSPI_SCLK : 1; /*!< GPIO_QSPI_SCLK */ + __IM uint32_t GPIO_QSPI_SS : 1; /*!< GPIO_QSPI_SS */ + __IM uint32_t GPIO_QSPI_SD0 : 1; /*!< GPIO_QSPI_SD0 */ + __IM uint32_t GPIO_QSPI_SD1 : 1; /*!< GPIO_QSPI_SD1 */ + __IM uint32_t GPIO_QSPI_SD2 : 1; /*!< GPIO_QSPI_SD2 */ + __IM uint32_t GPIO_QSPI_SD3 : 1; /*!< GPIO_QSPI_SD3 */ + uint32_t : 24; + } bit; + } IRQSUMMARY_PROC1_NONSECURE; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_DORMANT_WAKE_SECURE */ + + struct { + __IM uint32_t USBPHY_DP : 1; /*!< USBPHY_DP */ + __IM uint32_t USBPHY_DM : 1; /*!< USBPHY_DM */ + __IM uint32_t GPIO_QSPI_SCLK : 1; /*!< GPIO_QSPI_SCLK */ + __IM uint32_t GPIO_QSPI_SS : 1; /*!< GPIO_QSPI_SS */ + __IM uint32_t GPIO_QSPI_SD0 : 1; /*!< GPIO_QSPI_SD0 */ + __IM uint32_t GPIO_QSPI_SD1 : 1; /*!< GPIO_QSPI_SD1 */ + __IM uint32_t GPIO_QSPI_SD2 : 1; /*!< GPIO_QSPI_SD2 */ + __IM uint32_t GPIO_QSPI_SD3 : 1; /*!< GPIO_QSPI_SD3 */ + uint32_t : 24; + } bit; + } IRQSUMMARY_DORMANT_WAKE_SECURE; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE */ + + struct { + __IM uint32_t USBPHY_DP : 1; /*!< USBPHY_DP */ + __IM uint32_t USBPHY_DM : 1; /*!< USBPHY_DM */ + __IM uint32_t GPIO_QSPI_SCLK : 1; /*!< GPIO_QSPI_SCLK */ + __IM uint32_t GPIO_QSPI_SS : 1; /*!< GPIO_QSPI_SS */ + __IM uint32_t GPIO_QSPI_SD0 : 1; /*!< GPIO_QSPI_SD0 */ + __IM uint32_t GPIO_QSPI_SD1 : 1; /*!< GPIO_QSPI_SD1 */ + __IM uint32_t GPIO_QSPI_SD2 : 1; /*!< GPIO_QSPI_SD2 */ + __IM uint32_t GPIO_QSPI_SD3 : 1; /*!< GPIO_QSPI_SD3 */ + uint32_t : 24; + } bit; + } IRQSUMMARY_DORMANT_WAKE_NONSECURE; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IOM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IOM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc0 */ + + struct { + __IOM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IOM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IOM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IOM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IOM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IOM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } PROC0_INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc0 */ + + struct { + __IOM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IOM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IOM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IOM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IOM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IOM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } PROC0_INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc0 */ + + struct { + __IM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } PROC0_INTS; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc1 */ + + struct { + __IOM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IOM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IOM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IOM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IOM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IOM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } PROC1_INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc1 */ + + struct { + __IOM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IOM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IOM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IOM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IOM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IOM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } PROC1_INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc1 */ + + struct { + __IM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } PROC1_INTS; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for dormant_wake */ + + struct { + __IOM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IOM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IOM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IOM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IOM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IOM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for dormant_wake */ + + struct { + __IOM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IOM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IOM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IOM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IOM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IOM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IOM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for dormant_wake */ + + struct { + __IM uint32_t USBPHY_DP_LEVEL_LOW : 1; /*!< USBPHY_DP_LEVEL_LOW */ + __IM uint32_t USBPHY_DP_LEVEL_HIGH : 1; /*!< USBPHY_DP_LEVEL_HIGH */ + __IM uint32_t USBPHY_DP_EDGE_LOW : 1; /*!< USBPHY_DP_EDGE_LOW */ + __IM uint32_t USBPHY_DP_EDGE_HIGH : 1; /*!< USBPHY_DP_EDGE_HIGH */ + __IM uint32_t USBPHY_DM_LEVEL_LOW : 1; /*!< USBPHY_DM_LEVEL_LOW */ + __IM uint32_t USBPHY_DM_LEVEL_HIGH : 1; /*!< USBPHY_DM_LEVEL_HIGH */ + __IM uint32_t USBPHY_DM_EDGE_LOW : 1; /*!< USBPHY_DM_EDGE_LOW */ + __IM uint32_t USBPHY_DM_EDGE_HIGH : 1; /*!< USBPHY_DM_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< GPIO_QSPI_SCLK_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SCLK_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< GPIO_QSPI_SCLK_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< GPIO_QSPI_SCLK_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< GPIO_QSPI_SS_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SS_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< GPIO_QSPI_SS_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< GPIO_QSPI_SS_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD0_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD0_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< GPIO_QSPI_SD0_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD0_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD1_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD1_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< GPIO_QSPI_SD1_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD1_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD2_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD2_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< GPIO_QSPI_SD2_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD2_EDGE_HIGH */ + __IM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< GPIO_QSPI_SD3_LEVEL_LOW */ + __IM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< GPIO_QSPI_SD3_LEVEL_HIGH */ + __IM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< GPIO_QSPI_SD3_EDGE_LOW */ + __IM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< GPIO_QSPI_SD3_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTS; +} IO_QSPI_Type; /*!< Size = 576 (0x240) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_BANK0 (IO_BANK0) + */ + +typedef struct { /*!< IO_BANK0 Structure */ + + union { + __IOM uint32_t reg; /*!< GPIO0_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO0_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO0_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO0_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO1_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO1_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO1_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO1_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO2_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO2_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO2_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO2_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO3_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO3_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO3_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO3_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO4_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO4_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO4_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO4_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO5_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO5_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO5_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO5_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO6_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO6_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO6_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO6_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO7_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO7_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO7_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO7_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO8_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO8_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO8_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO8_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO9_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO9_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO9_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO9_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO10_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO10_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO10_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO10_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO11_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO11_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO11_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO11_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO12_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO12_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO12_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO12_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO13_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO13_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO13_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO13_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO14_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO14_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO14_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO14_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO15_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO15_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO15_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO15_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO16_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO16_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO16_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO16_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO17_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO17_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO17_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO17_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO18_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO18_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO18_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO18_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO19_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO19_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO19_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO19_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO20_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO20_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO20_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO20_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO21_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO21_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO21_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO21_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO22_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO22_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO22_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO22_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO23_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO23_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO23_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO23_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO24_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO24_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO24_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO24_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO25_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO25_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO25_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO25_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO26_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO26_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO26_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO26_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO27_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO27_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO27_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO27_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO28_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO28_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO28_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO28_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO29_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO29_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO29_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO29_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO30_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO30_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO30_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO30_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO31_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO31_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO31_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO31_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO32_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO32_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO32_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO32_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO33_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO33_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO33_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO33_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO34_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO34_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO34_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO34_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO35_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO35_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO35_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO35_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO36_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO36_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO36_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO36_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO37_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO37_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO37_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO37_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO38_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO38_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO38_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO38_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO39_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO39_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO39_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO39_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO40_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO40_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO40_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO40_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO41_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO41_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO41_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO41_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO42_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO42_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO42_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO42_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO43_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO43_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO43_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO43_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO44_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO44_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO44_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO44_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO45_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO45_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO45_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO45_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO46_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO46_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO46_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO46_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO47_STATUS */ + + struct { + uint32_t : 9; + __IM uint32_t OUTTOPAD : 1; /*!< output signal to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t OETOPAD : 1; /*!< output enable to pad after register override is applied */ + uint32_t : 3; + __IM uint32_t INFROMPAD : 1; /*!< input signal from pad, before filtering and override are applied */ + uint32_t : 8; + __IM uint32_t IRQTOPROC : 1; /*!< interrupt to processors, after override is applied */ + uint32_t : 5; + } bit; + } GPIO47_STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO47_CTRL */ + + struct { + __IOM uint32_t FUNCSEL : 5; /*!< 0-31 -> selects pin function according to the gpio table 31 + == NULL */ + uint32_t : 7; + __IOM uint32_t OUTOVER : 2; /*!< OUTOVER */ + __IOM uint32_t OEOVER : 2; /*!< OEOVER */ + __IOM uint32_t INOVER : 2; /*!< INOVER */ + uint32_t : 10; + __IOM uint32_t IRQOVER : 2; /*!< IRQOVER */ + uint32_t : 2; + } bit; + } GPIO47_CTRL; + __IM uint32_t RESERVED[32]; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC0_SECURE0 */ + + struct { + __IM uint32_t GPIO0 : 1; /*!< GPIO0 */ + __IM uint32_t GPIO1 : 1; /*!< GPIO1 */ + __IM uint32_t GPIO2 : 1; /*!< GPIO2 */ + __IM uint32_t GPIO3 : 1; /*!< GPIO3 */ + __IM uint32_t GPIO4 : 1; /*!< GPIO4 */ + __IM uint32_t GPIO5 : 1; /*!< GPIO5 */ + __IM uint32_t GPIO6 : 1; /*!< GPIO6 */ + __IM uint32_t GPIO7 : 1; /*!< GPIO7 */ + __IM uint32_t GPIO8 : 1; /*!< GPIO8 */ + __IM uint32_t GPIO9 : 1; /*!< GPIO9 */ + __IM uint32_t GPIO10 : 1; /*!< GPIO10 */ + __IM uint32_t GPIO11 : 1; /*!< GPIO11 */ + __IM uint32_t GPIO12 : 1; /*!< GPIO12 */ + __IM uint32_t GPIO13 : 1; /*!< GPIO13 */ + __IM uint32_t GPIO14 : 1; /*!< GPIO14 */ + __IM uint32_t GPIO15 : 1; /*!< GPIO15 */ + __IM uint32_t GPIO16 : 1; /*!< GPIO16 */ + __IM uint32_t GPIO17 : 1; /*!< GPIO17 */ + __IM uint32_t GPIO18 : 1; /*!< GPIO18 */ + __IM uint32_t GPIO19 : 1; /*!< GPIO19 */ + __IM uint32_t GPIO20 : 1; /*!< GPIO20 */ + __IM uint32_t GPIO21 : 1; /*!< GPIO21 */ + __IM uint32_t GPIO22 : 1; /*!< GPIO22 */ + __IM uint32_t GPIO23 : 1; /*!< GPIO23 */ + __IM uint32_t GPIO24 : 1; /*!< GPIO24 */ + __IM uint32_t GPIO25 : 1; /*!< GPIO25 */ + __IM uint32_t GPIO26 : 1; /*!< GPIO26 */ + __IM uint32_t GPIO27 : 1; /*!< GPIO27 */ + __IM uint32_t GPIO28 : 1; /*!< GPIO28 */ + __IM uint32_t GPIO29 : 1; /*!< GPIO29 */ + __IM uint32_t GPIO30 : 1; /*!< GPIO30 */ + __IM uint32_t GPIO31 : 1; /*!< GPIO31 */ + } bit; + } IRQSUMMARY_PROC0_SECURE0; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC0_SECURE1 */ + + struct { + __IM uint32_t GPIO32 : 1; /*!< GPIO32 */ + __IM uint32_t GPIO33 : 1; /*!< GPIO33 */ + __IM uint32_t GPIO34 : 1; /*!< GPIO34 */ + __IM uint32_t GPIO35 : 1; /*!< GPIO35 */ + __IM uint32_t GPIO36 : 1; /*!< GPIO36 */ + __IM uint32_t GPIO37 : 1; /*!< GPIO37 */ + __IM uint32_t GPIO38 : 1; /*!< GPIO38 */ + __IM uint32_t GPIO39 : 1; /*!< GPIO39 */ + __IM uint32_t GPIO40 : 1; /*!< GPIO40 */ + __IM uint32_t GPIO41 : 1; /*!< GPIO41 */ + __IM uint32_t GPIO42 : 1; /*!< GPIO42 */ + __IM uint32_t GPIO43 : 1; /*!< GPIO43 */ + __IM uint32_t GPIO44 : 1; /*!< GPIO44 */ + __IM uint32_t GPIO45 : 1; /*!< GPIO45 */ + __IM uint32_t GPIO46 : 1; /*!< GPIO46 */ + __IM uint32_t GPIO47 : 1; /*!< GPIO47 */ + uint32_t : 16; + } bit; + } IRQSUMMARY_PROC0_SECURE1; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC0_NONSECURE0 */ + + struct { + __IM uint32_t GPIO0 : 1; /*!< GPIO0 */ + __IM uint32_t GPIO1 : 1; /*!< GPIO1 */ + __IM uint32_t GPIO2 : 1; /*!< GPIO2 */ + __IM uint32_t GPIO3 : 1; /*!< GPIO3 */ + __IM uint32_t GPIO4 : 1; /*!< GPIO4 */ + __IM uint32_t GPIO5 : 1; /*!< GPIO5 */ + __IM uint32_t GPIO6 : 1; /*!< GPIO6 */ + __IM uint32_t GPIO7 : 1; /*!< GPIO7 */ + __IM uint32_t GPIO8 : 1; /*!< GPIO8 */ + __IM uint32_t GPIO9 : 1; /*!< GPIO9 */ + __IM uint32_t GPIO10 : 1; /*!< GPIO10 */ + __IM uint32_t GPIO11 : 1; /*!< GPIO11 */ + __IM uint32_t GPIO12 : 1; /*!< GPIO12 */ + __IM uint32_t GPIO13 : 1; /*!< GPIO13 */ + __IM uint32_t GPIO14 : 1; /*!< GPIO14 */ + __IM uint32_t GPIO15 : 1; /*!< GPIO15 */ + __IM uint32_t GPIO16 : 1; /*!< GPIO16 */ + __IM uint32_t GPIO17 : 1; /*!< GPIO17 */ + __IM uint32_t GPIO18 : 1; /*!< GPIO18 */ + __IM uint32_t GPIO19 : 1; /*!< GPIO19 */ + __IM uint32_t GPIO20 : 1; /*!< GPIO20 */ + __IM uint32_t GPIO21 : 1; /*!< GPIO21 */ + __IM uint32_t GPIO22 : 1; /*!< GPIO22 */ + __IM uint32_t GPIO23 : 1; /*!< GPIO23 */ + __IM uint32_t GPIO24 : 1; /*!< GPIO24 */ + __IM uint32_t GPIO25 : 1; /*!< GPIO25 */ + __IM uint32_t GPIO26 : 1; /*!< GPIO26 */ + __IM uint32_t GPIO27 : 1; /*!< GPIO27 */ + __IM uint32_t GPIO28 : 1; /*!< GPIO28 */ + __IM uint32_t GPIO29 : 1; /*!< GPIO29 */ + __IM uint32_t GPIO30 : 1; /*!< GPIO30 */ + __IM uint32_t GPIO31 : 1; /*!< GPIO31 */ + } bit; + } IRQSUMMARY_PROC0_NONSECURE0; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC0_NONSECURE1 */ + + struct { + __IM uint32_t GPIO32 : 1; /*!< GPIO32 */ + __IM uint32_t GPIO33 : 1; /*!< GPIO33 */ + __IM uint32_t GPIO34 : 1; /*!< GPIO34 */ + __IM uint32_t GPIO35 : 1; /*!< GPIO35 */ + __IM uint32_t GPIO36 : 1; /*!< GPIO36 */ + __IM uint32_t GPIO37 : 1; /*!< GPIO37 */ + __IM uint32_t GPIO38 : 1; /*!< GPIO38 */ + __IM uint32_t GPIO39 : 1; /*!< GPIO39 */ + __IM uint32_t GPIO40 : 1; /*!< GPIO40 */ + __IM uint32_t GPIO41 : 1; /*!< GPIO41 */ + __IM uint32_t GPIO42 : 1; /*!< GPIO42 */ + __IM uint32_t GPIO43 : 1; /*!< GPIO43 */ + __IM uint32_t GPIO44 : 1; /*!< GPIO44 */ + __IM uint32_t GPIO45 : 1; /*!< GPIO45 */ + __IM uint32_t GPIO46 : 1; /*!< GPIO46 */ + __IM uint32_t GPIO47 : 1; /*!< GPIO47 */ + uint32_t : 16; + } bit; + } IRQSUMMARY_PROC0_NONSECURE1; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC1_SECURE0 */ + + struct { + __IM uint32_t GPIO0 : 1; /*!< GPIO0 */ + __IM uint32_t GPIO1 : 1; /*!< GPIO1 */ + __IM uint32_t GPIO2 : 1; /*!< GPIO2 */ + __IM uint32_t GPIO3 : 1; /*!< GPIO3 */ + __IM uint32_t GPIO4 : 1; /*!< GPIO4 */ + __IM uint32_t GPIO5 : 1; /*!< GPIO5 */ + __IM uint32_t GPIO6 : 1; /*!< GPIO6 */ + __IM uint32_t GPIO7 : 1; /*!< GPIO7 */ + __IM uint32_t GPIO8 : 1; /*!< GPIO8 */ + __IM uint32_t GPIO9 : 1; /*!< GPIO9 */ + __IM uint32_t GPIO10 : 1; /*!< GPIO10 */ + __IM uint32_t GPIO11 : 1; /*!< GPIO11 */ + __IM uint32_t GPIO12 : 1; /*!< GPIO12 */ + __IM uint32_t GPIO13 : 1; /*!< GPIO13 */ + __IM uint32_t GPIO14 : 1; /*!< GPIO14 */ + __IM uint32_t GPIO15 : 1; /*!< GPIO15 */ + __IM uint32_t GPIO16 : 1; /*!< GPIO16 */ + __IM uint32_t GPIO17 : 1; /*!< GPIO17 */ + __IM uint32_t GPIO18 : 1; /*!< GPIO18 */ + __IM uint32_t GPIO19 : 1; /*!< GPIO19 */ + __IM uint32_t GPIO20 : 1; /*!< GPIO20 */ + __IM uint32_t GPIO21 : 1; /*!< GPIO21 */ + __IM uint32_t GPIO22 : 1; /*!< GPIO22 */ + __IM uint32_t GPIO23 : 1; /*!< GPIO23 */ + __IM uint32_t GPIO24 : 1; /*!< GPIO24 */ + __IM uint32_t GPIO25 : 1; /*!< GPIO25 */ + __IM uint32_t GPIO26 : 1; /*!< GPIO26 */ + __IM uint32_t GPIO27 : 1; /*!< GPIO27 */ + __IM uint32_t GPIO28 : 1; /*!< GPIO28 */ + __IM uint32_t GPIO29 : 1; /*!< GPIO29 */ + __IM uint32_t GPIO30 : 1; /*!< GPIO30 */ + __IM uint32_t GPIO31 : 1; /*!< GPIO31 */ + } bit; + } IRQSUMMARY_PROC1_SECURE0; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC1_SECURE1 */ + + struct { + __IM uint32_t GPIO32 : 1; /*!< GPIO32 */ + __IM uint32_t GPIO33 : 1; /*!< GPIO33 */ + __IM uint32_t GPIO34 : 1; /*!< GPIO34 */ + __IM uint32_t GPIO35 : 1; /*!< GPIO35 */ + __IM uint32_t GPIO36 : 1; /*!< GPIO36 */ + __IM uint32_t GPIO37 : 1; /*!< GPIO37 */ + __IM uint32_t GPIO38 : 1; /*!< GPIO38 */ + __IM uint32_t GPIO39 : 1; /*!< GPIO39 */ + __IM uint32_t GPIO40 : 1; /*!< GPIO40 */ + __IM uint32_t GPIO41 : 1; /*!< GPIO41 */ + __IM uint32_t GPIO42 : 1; /*!< GPIO42 */ + __IM uint32_t GPIO43 : 1; /*!< GPIO43 */ + __IM uint32_t GPIO44 : 1; /*!< GPIO44 */ + __IM uint32_t GPIO45 : 1; /*!< GPIO45 */ + __IM uint32_t GPIO46 : 1; /*!< GPIO46 */ + __IM uint32_t GPIO47 : 1; /*!< GPIO47 */ + uint32_t : 16; + } bit; + } IRQSUMMARY_PROC1_SECURE1; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC1_NONSECURE0 */ + + struct { + __IM uint32_t GPIO0 : 1; /*!< GPIO0 */ + __IM uint32_t GPIO1 : 1; /*!< GPIO1 */ + __IM uint32_t GPIO2 : 1; /*!< GPIO2 */ + __IM uint32_t GPIO3 : 1; /*!< GPIO3 */ + __IM uint32_t GPIO4 : 1; /*!< GPIO4 */ + __IM uint32_t GPIO5 : 1; /*!< GPIO5 */ + __IM uint32_t GPIO6 : 1; /*!< GPIO6 */ + __IM uint32_t GPIO7 : 1; /*!< GPIO7 */ + __IM uint32_t GPIO8 : 1; /*!< GPIO8 */ + __IM uint32_t GPIO9 : 1; /*!< GPIO9 */ + __IM uint32_t GPIO10 : 1; /*!< GPIO10 */ + __IM uint32_t GPIO11 : 1; /*!< GPIO11 */ + __IM uint32_t GPIO12 : 1; /*!< GPIO12 */ + __IM uint32_t GPIO13 : 1; /*!< GPIO13 */ + __IM uint32_t GPIO14 : 1; /*!< GPIO14 */ + __IM uint32_t GPIO15 : 1; /*!< GPIO15 */ + __IM uint32_t GPIO16 : 1; /*!< GPIO16 */ + __IM uint32_t GPIO17 : 1; /*!< GPIO17 */ + __IM uint32_t GPIO18 : 1; /*!< GPIO18 */ + __IM uint32_t GPIO19 : 1; /*!< GPIO19 */ + __IM uint32_t GPIO20 : 1; /*!< GPIO20 */ + __IM uint32_t GPIO21 : 1; /*!< GPIO21 */ + __IM uint32_t GPIO22 : 1; /*!< GPIO22 */ + __IM uint32_t GPIO23 : 1; /*!< GPIO23 */ + __IM uint32_t GPIO24 : 1; /*!< GPIO24 */ + __IM uint32_t GPIO25 : 1; /*!< GPIO25 */ + __IM uint32_t GPIO26 : 1; /*!< GPIO26 */ + __IM uint32_t GPIO27 : 1; /*!< GPIO27 */ + __IM uint32_t GPIO28 : 1; /*!< GPIO28 */ + __IM uint32_t GPIO29 : 1; /*!< GPIO29 */ + __IM uint32_t GPIO30 : 1; /*!< GPIO30 */ + __IM uint32_t GPIO31 : 1; /*!< GPIO31 */ + } bit; + } IRQSUMMARY_PROC1_NONSECURE0; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_PROC1_NONSECURE1 */ + + struct { + __IM uint32_t GPIO32 : 1; /*!< GPIO32 */ + __IM uint32_t GPIO33 : 1; /*!< GPIO33 */ + __IM uint32_t GPIO34 : 1; /*!< GPIO34 */ + __IM uint32_t GPIO35 : 1; /*!< GPIO35 */ + __IM uint32_t GPIO36 : 1; /*!< GPIO36 */ + __IM uint32_t GPIO37 : 1; /*!< GPIO37 */ + __IM uint32_t GPIO38 : 1; /*!< GPIO38 */ + __IM uint32_t GPIO39 : 1; /*!< GPIO39 */ + __IM uint32_t GPIO40 : 1; /*!< GPIO40 */ + __IM uint32_t GPIO41 : 1; /*!< GPIO41 */ + __IM uint32_t GPIO42 : 1; /*!< GPIO42 */ + __IM uint32_t GPIO43 : 1; /*!< GPIO43 */ + __IM uint32_t GPIO44 : 1; /*!< GPIO44 */ + __IM uint32_t GPIO45 : 1; /*!< GPIO45 */ + __IM uint32_t GPIO46 : 1; /*!< GPIO46 */ + __IM uint32_t GPIO47 : 1; /*!< GPIO47 */ + uint32_t : 16; + } bit; + } IRQSUMMARY_PROC1_NONSECURE1; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_DORMANT_WAKE_SECURE0 */ + + struct { + __IM uint32_t GPIO0 : 1; /*!< GPIO0 */ + __IM uint32_t GPIO1 : 1; /*!< GPIO1 */ + __IM uint32_t GPIO2 : 1; /*!< GPIO2 */ + __IM uint32_t GPIO3 : 1; /*!< GPIO3 */ + __IM uint32_t GPIO4 : 1; /*!< GPIO4 */ + __IM uint32_t GPIO5 : 1; /*!< GPIO5 */ + __IM uint32_t GPIO6 : 1; /*!< GPIO6 */ + __IM uint32_t GPIO7 : 1; /*!< GPIO7 */ + __IM uint32_t GPIO8 : 1; /*!< GPIO8 */ + __IM uint32_t GPIO9 : 1; /*!< GPIO9 */ + __IM uint32_t GPIO10 : 1; /*!< GPIO10 */ + __IM uint32_t GPIO11 : 1; /*!< GPIO11 */ + __IM uint32_t GPIO12 : 1; /*!< GPIO12 */ + __IM uint32_t GPIO13 : 1; /*!< GPIO13 */ + __IM uint32_t GPIO14 : 1; /*!< GPIO14 */ + __IM uint32_t GPIO15 : 1; /*!< GPIO15 */ + __IM uint32_t GPIO16 : 1; /*!< GPIO16 */ + __IM uint32_t GPIO17 : 1; /*!< GPIO17 */ + __IM uint32_t GPIO18 : 1; /*!< GPIO18 */ + __IM uint32_t GPIO19 : 1; /*!< GPIO19 */ + __IM uint32_t GPIO20 : 1; /*!< GPIO20 */ + __IM uint32_t GPIO21 : 1; /*!< GPIO21 */ + __IM uint32_t GPIO22 : 1; /*!< GPIO22 */ + __IM uint32_t GPIO23 : 1; /*!< GPIO23 */ + __IM uint32_t GPIO24 : 1; /*!< GPIO24 */ + __IM uint32_t GPIO25 : 1; /*!< GPIO25 */ + __IM uint32_t GPIO26 : 1; /*!< GPIO26 */ + __IM uint32_t GPIO27 : 1; /*!< GPIO27 */ + __IM uint32_t GPIO28 : 1; /*!< GPIO28 */ + __IM uint32_t GPIO29 : 1; /*!< GPIO29 */ + __IM uint32_t GPIO30 : 1; /*!< GPIO30 */ + __IM uint32_t GPIO31 : 1; /*!< GPIO31 */ + } bit; + } IRQSUMMARY_DORMANT_WAKE_SECURE0; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_DORMANT_WAKE_SECURE1 */ + + struct { + __IM uint32_t GPIO32 : 1; /*!< GPIO32 */ + __IM uint32_t GPIO33 : 1; /*!< GPIO33 */ + __IM uint32_t GPIO34 : 1; /*!< GPIO34 */ + __IM uint32_t GPIO35 : 1; /*!< GPIO35 */ + __IM uint32_t GPIO36 : 1; /*!< GPIO36 */ + __IM uint32_t GPIO37 : 1; /*!< GPIO37 */ + __IM uint32_t GPIO38 : 1; /*!< GPIO38 */ + __IM uint32_t GPIO39 : 1; /*!< GPIO39 */ + __IM uint32_t GPIO40 : 1; /*!< GPIO40 */ + __IM uint32_t GPIO41 : 1; /*!< GPIO41 */ + __IM uint32_t GPIO42 : 1; /*!< GPIO42 */ + __IM uint32_t GPIO43 : 1; /*!< GPIO43 */ + __IM uint32_t GPIO44 : 1; /*!< GPIO44 */ + __IM uint32_t GPIO45 : 1; /*!< GPIO45 */ + __IM uint32_t GPIO46 : 1; /*!< GPIO46 */ + __IM uint32_t GPIO47 : 1; /*!< GPIO47 */ + uint32_t : 16; + } bit; + } IRQSUMMARY_DORMANT_WAKE_SECURE1; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE0 */ + + struct { + __IM uint32_t GPIO0 : 1; /*!< GPIO0 */ + __IM uint32_t GPIO1 : 1; /*!< GPIO1 */ + __IM uint32_t GPIO2 : 1; /*!< GPIO2 */ + __IM uint32_t GPIO3 : 1; /*!< GPIO3 */ + __IM uint32_t GPIO4 : 1; /*!< GPIO4 */ + __IM uint32_t GPIO5 : 1; /*!< GPIO5 */ + __IM uint32_t GPIO6 : 1; /*!< GPIO6 */ + __IM uint32_t GPIO7 : 1; /*!< GPIO7 */ + __IM uint32_t GPIO8 : 1; /*!< GPIO8 */ + __IM uint32_t GPIO9 : 1; /*!< GPIO9 */ + __IM uint32_t GPIO10 : 1; /*!< GPIO10 */ + __IM uint32_t GPIO11 : 1; /*!< GPIO11 */ + __IM uint32_t GPIO12 : 1; /*!< GPIO12 */ + __IM uint32_t GPIO13 : 1; /*!< GPIO13 */ + __IM uint32_t GPIO14 : 1; /*!< GPIO14 */ + __IM uint32_t GPIO15 : 1; /*!< GPIO15 */ + __IM uint32_t GPIO16 : 1; /*!< GPIO16 */ + __IM uint32_t GPIO17 : 1; /*!< GPIO17 */ + __IM uint32_t GPIO18 : 1; /*!< GPIO18 */ + __IM uint32_t GPIO19 : 1; /*!< GPIO19 */ + __IM uint32_t GPIO20 : 1; /*!< GPIO20 */ + __IM uint32_t GPIO21 : 1; /*!< GPIO21 */ + __IM uint32_t GPIO22 : 1; /*!< GPIO22 */ + __IM uint32_t GPIO23 : 1; /*!< GPIO23 */ + __IM uint32_t GPIO24 : 1; /*!< GPIO24 */ + __IM uint32_t GPIO25 : 1; /*!< GPIO25 */ + __IM uint32_t GPIO26 : 1; /*!< GPIO26 */ + __IM uint32_t GPIO27 : 1; /*!< GPIO27 */ + __IM uint32_t GPIO28 : 1; /*!< GPIO28 */ + __IM uint32_t GPIO29 : 1; /*!< GPIO29 */ + __IM uint32_t GPIO30 : 1; /*!< GPIO30 */ + __IM uint32_t GPIO31 : 1; /*!< GPIO31 */ + } bit; + } IRQSUMMARY_DORMANT_WAKE_NONSECURE0; + + union { + __IOM uint32_t reg; /*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE1 */ + + struct { + __IM uint32_t GPIO32 : 1; /*!< GPIO32 */ + __IM uint32_t GPIO33 : 1; /*!< GPIO33 */ + __IM uint32_t GPIO34 : 1; /*!< GPIO34 */ + __IM uint32_t GPIO35 : 1; /*!< GPIO35 */ + __IM uint32_t GPIO36 : 1; /*!< GPIO36 */ + __IM uint32_t GPIO37 : 1; /*!< GPIO37 */ + __IM uint32_t GPIO38 : 1; /*!< GPIO38 */ + __IM uint32_t GPIO39 : 1; /*!< GPIO39 */ + __IM uint32_t GPIO40 : 1; /*!< GPIO40 */ + __IM uint32_t GPIO41 : 1; /*!< GPIO41 */ + __IM uint32_t GPIO42 : 1; /*!< GPIO42 */ + __IM uint32_t GPIO43 : 1; /*!< GPIO43 */ + __IM uint32_t GPIO44 : 1; /*!< GPIO44 */ + __IM uint32_t GPIO45 : 1; /*!< GPIO45 */ + __IM uint32_t GPIO46 : 1; /*!< GPIO46 */ + __IM uint32_t GPIO47 : 1; /*!< GPIO47 */ + uint32_t : 16; + } bit; + } IRQSUMMARY_DORMANT_WAKE_NONSECURE1; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } INTR0; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } INTR1; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } INTR2; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IOM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IOM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IOM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IOM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } INTR3; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IOM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IOM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IOM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IOM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IOM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IOM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IOM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IOM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IOM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IOM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IOM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IOM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IOM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IOM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IOM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IOM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } INTR4; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IOM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IOM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IOM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IOM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IOM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IOM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IOM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IOM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IOM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IOM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IOM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IOM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IOM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IOM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IOM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IOM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } INTR5; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc0 */ + + struct { + __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } PROC0_INTE0; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc0 */ + + struct { + __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } PROC0_INTE1; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc0 */ + + struct { + __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } PROC0_INTE2; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc0 */ + + struct { + __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IOM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IOM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IOM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IOM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IOM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IOM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IOM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IOM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } PROC0_INTE3; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc0 */ + + struct { + __IOM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IOM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IOM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IOM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IOM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IOM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IOM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IOM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IOM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IOM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IOM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IOM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IOM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IOM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IOM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IOM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IOM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IOM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IOM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IOM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IOM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IOM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IOM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IOM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IOM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IOM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IOM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IOM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IOM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IOM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IOM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IOM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } PROC0_INTE4; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc0 */ + + struct { + __IOM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IOM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IOM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IOM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IOM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IOM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IOM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IOM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IOM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IOM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IOM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IOM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IOM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IOM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IOM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IOM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IOM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IOM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IOM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IOM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IOM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IOM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IOM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IOM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IOM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IOM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IOM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IOM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IOM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IOM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IOM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IOM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } PROC0_INTE5; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc0 */ + + struct { + __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } PROC0_INTF0; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc0 */ + + struct { + __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } PROC0_INTF1; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc0 */ + + struct { + __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } PROC0_INTF2; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc0 */ + + struct { + __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IOM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IOM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IOM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IOM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IOM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IOM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IOM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IOM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } PROC0_INTF3; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc0 */ + + struct { + __IOM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IOM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IOM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IOM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IOM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IOM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IOM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IOM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IOM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IOM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IOM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IOM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IOM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IOM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IOM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IOM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IOM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IOM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IOM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IOM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IOM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IOM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IOM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IOM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IOM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IOM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IOM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IOM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IOM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IOM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IOM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IOM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } PROC0_INTF4; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc0 */ + + struct { + __IOM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IOM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IOM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IOM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IOM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IOM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IOM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IOM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IOM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IOM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IOM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IOM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IOM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IOM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IOM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IOM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IOM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IOM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IOM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IOM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IOM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IOM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IOM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IOM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IOM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IOM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IOM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IOM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IOM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IOM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IOM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IOM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } PROC0_INTF5; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc0 */ + + struct { + __IM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } PROC0_INTS0; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc0 */ + + struct { + __IM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } PROC0_INTS1; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc0 */ + + struct { + __IM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } PROC0_INTS2; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc0 */ + + struct { + __IM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } PROC0_INTS3; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc0 */ + + struct { + __IM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } PROC0_INTS4; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc0 */ + + struct { + __IM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } PROC0_INTS5; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc1 */ + + struct { + __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } PROC1_INTE0; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc1 */ + + struct { + __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } PROC1_INTE1; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc1 */ + + struct { + __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } PROC1_INTE2; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc1 */ + + struct { + __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IOM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IOM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IOM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IOM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IOM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IOM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IOM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IOM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } PROC1_INTE3; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc1 */ + + struct { + __IOM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IOM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IOM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IOM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IOM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IOM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IOM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IOM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IOM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IOM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IOM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IOM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IOM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IOM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IOM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IOM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IOM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IOM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IOM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IOM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IOM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IOM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IOM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IOM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IOM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IOM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IOM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IOM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IOM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IOM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IOM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IOM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } PROC1_INTE4; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for proc1 */ + + struct { + __IOM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IOM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IOM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IOM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IOM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IOM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IOM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IOM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IOM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IOM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IOM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IOM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IOM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IOM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IOM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IOM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IOM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IOM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IOM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IOM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IOM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IOM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IOM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IOM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IOM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IOM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IOM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IOM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IOM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IOM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IOM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IOM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } PROC1_INTE5; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc1 */ + + struct { + __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } PROC1_INTF0; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc1 */ + + struct { + __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } PROC1_INTF1; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc1 */ + + struct { + __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } PROC1_INTF2; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc1 */ + + struct { + __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IOM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IOM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IOM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IOM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IOM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IOM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IOM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IOM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } PROC1_INTF3; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc1 */ + + struct { + __IOM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IOM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IOM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IOM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IOM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IOM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IOM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IOM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IOM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IOM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IOM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IOM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IOM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IOM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IOM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IOM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IOM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IOM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IOM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IOM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IOM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IOM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IOM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IOM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IOM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IOM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IOM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IOM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IOM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IOM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IOM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IOM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } PROC1_INTF4; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for proc1 */ + + struct { + __IOM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IOM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IOM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IOM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IOM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IOM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IOM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IOM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IOM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IOM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IOM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IOM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IOM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IOM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IOM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IOM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IOM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IOM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IOM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IOM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IOM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IOM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IOM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IOM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IOM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IOM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IOM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IOM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IOM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IOM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IOM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IOM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } PROC1_INTF5; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc1 */ + + struct { + __IM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } PROC1_INTS0; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc1 */ + + struct { + __IM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } PROC1_INTS1; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc1 */ + + struct { + __IM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } PROC1_INTS2; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc1 */ + + struct { + __IM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } PROC1_INTS3; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc1 */ + + struct { + __IM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } PROC1_INTS4; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for proc1 */ + + struct { + __IM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } PROC1_INTS5; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for dormant_wake */ + + struct { + __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTE0; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for dormant_wake */ + + struct { + __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTE1; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for dormant_wake */ + + struct { + __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTE2; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for dormant_wake */ + + struct { + __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IOM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IOM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IOM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IOM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IOM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IOM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IOM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IOM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTE3; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for dormant_wake */ + + struct { + __IOM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IOM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IOM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IOM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IOM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IOM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IOM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IOM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IOM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IOM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IOM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IOM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IOM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IOM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IOM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IOM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IOM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IOM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IOM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IOM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IOM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IOM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IOM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IOM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IOM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IOM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IOM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IOM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IOM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IOM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IOM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IOM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTE4; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for dormant_wake */ + + struct { + __IOM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IOM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IOM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IOM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IOM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IOM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IOM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IOM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IOM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IOM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IOM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IOM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IOM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IOM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IOM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IOM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IOM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IOM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IOM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IOM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IOM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IOM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IOM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IOM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IOM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IOM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IOM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IOM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IOM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IOM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IOM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IOM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTE5; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for dormant_wake */ + + struct { + __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTF0; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for dormant_wake */ + + struct { + __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTF1; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for dormant_wake */ + + struct { + __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTF2; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for dormant_wake */ + + struct { + __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IOM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IOM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IOM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IOM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IOM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IOM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IOM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IOM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTF3; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for dormant_wake */ + + struct { + __IOM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IOM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IOM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IOM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IOM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IOM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IOM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IOM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IOM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IOM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IOM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IOM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IOM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IOM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IOM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IOM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IOM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IOM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IOM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IOM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IOM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IOM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IOM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IOM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IOM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IOM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IOM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IOM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IOM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IOM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IOM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IOM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTF4; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for dormant_wake */ + + struct { + __IOM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IOM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IOM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IOM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IOM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IOM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IOM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IOM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IOM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IOM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IOM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IOM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IOM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IOM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IOM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IOM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IOM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IOM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IOM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IOM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IOM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IOM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IOM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IOM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IOM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IOM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IOM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IOM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IOM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IOM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IOM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IOM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTF5; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for dormant_wake */ + + struct { + __IM uint32_t GPIO0_LEVEL_LOW : 1; /*!< GPIO0_LEVEL_LOW */ + __IM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< GPIO0_LEVEL_HIGH */ + __IM uint32_t GPIO0_EDGE_LOW : 1; /*!< GPIO0_EDGE_LOW */ + __IM uint32_t GPIO0_EDGE_HIGH : 1; /*!< GPIO0_EDGE_HIGH */ + __IM uint32_t GPIO1_LEVEL_LOW : 1; /*!< GPIO1_LEVEL_LOW */ + __IM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< GPIO1_LEVEL_HIGH */ + __IM uint32_t GPIO1_EDGE_LOW : 1; /*!< GPIO1_EDGE_LOW */ + __IM uint32_t GPIO1_EDGE_HIGH : 1; /*!< GPIO1_EDGE_HIGH */ + __IM uint32_t GPIO2_LEVEL_LOW : 1; /*!< GPIO2_LEVEL_LOW */ + __IM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< GPIO2_LEVEL_HIGH */ + __IM uint32_t GPIO2_EDGE_LOW : 1; /*!< GPIO2_EDGE_LOW */ + __IM uint32_t GPIO2_EDGE_HIGH : 1; /*!< GPIO2_EDGE_HIGH */ + __IM uint32_t GPIO3_LEVEL_LOW : 1; /*!< GPIO3_LEVEL_LOW */ + __IM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< GPIO3_LEVEL_HIGH */ + __IM uint32_t GPIO3_EDGE_LOW : 1; /*!< GPIO3_EDGE_LOW */ + __IM uint32_t GPIO3_EDGE_HIGH : 1; /*!< GPIO3_EDGE_HIGH */ + __IM uint32_t GPIO4_LEVEL_LOW : 1; /*!< GPIO4_LEVEL_LOW */ + __IM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< GPIO4_LEVEL_HIGH */ + __IM uint32_t GPIO4_EDGE_LOW : 1; /*!< GPIO4_EDGE_LOW */ + __IM uint32_t GPIO4_EDGE_HIGH : 1; /*!< GPIO4_EDGE_HIGH */ + __IM uint32_t GPIO5_LEVEL_LOW : 1; /*!< GPIO5_LEVEL_LOW */ + __IM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< GPIO5_LEVEL_HIGH */ + __IM uint32_t GPIO5_EDGE_LOW : 1; /*!< GPIO5_EDGE_LOW */ + __IM uint32_t GPIO5_EDGE_HIGH : 1; /*!< GPIO5_EDGE_HIGH */ + __IM uint32_t GPIO6_LEVEL_LOW : 1; /*!< GPIO6_LEVEL_LOW */ + __IM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< GPIO6_LEVEL_HIGH */ + __IM uint32_t GPIO6_EDGE_LOW : 1; /*!< GPIO6_EDGE_LOW */ + __IM uint32_t GPIO6_EDGE_HIGH : 1; /*!< GPIO6_EDGE_HIGH */ + __IM uint32_t GPIO7_LEVEL_LOW : 1; /*!< GPIO7_LEVEL_LOW */ + __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< GPIO7_LEVEL_HIGH */ + __IM uint32_t GPIO7_EDGE_LOW : 1; /*!< GPIO7_EDGE_LOW */ + __IM uint32_t GPIO7_EDGE_HIGH : 1; /*!< GPIO7_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTS0; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for dormant_wake */ + + struct { + __IM uint32_t GPIO8_LEVEL_LOW : 1; /*!< GPIO8_LEVEL_LOW */ + __IM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< GPIO8_LEVEL_HIGH */ + __IM uint32_t GPIO8_EDGE_LOW : 1; /*!< GPIO8_EDGE_LOW */ + __IM uint32_t GPIO8_EDGE_HIGH : 1; /*!< GPIO8_EDGE_HIGH */ + __IM uint32_t GPIO9_LEVEL_LOW : 1; /*!< GPIO9_LEVEL_LOW */ + __IM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< GPIO9_LEVEL_HIGH */ + __IM uint32_t GPIO9_EDGE_LOW : 1; /*!< GPIO9_EDGE_LOW */ + __IM uint32_t GPIO9_EDGE_HIGH : 1; /*!< GPIO9_EDGE_HIGH */ + __IM uint32_t GPIO10_LEVEL_LOW : 1; /*!< GPIO10_LEVEL_LOW */ + __IM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< GPIO10_LEVEL_HIGH */ + __IM uint32_t GPIO10_EDGE_LOW : 1; /*!< GPIO10_EDGE_LOW */ + __IM uint32_t GPIO10_EDGE_HIGH : 1; /*!< GPIO10_EDGE_HIGH */ + __IM uint32_t GPIO11_LEVEL_LOW : 1; /*!< GPIO11_LEVEL_LOW */ + __IM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< GPIO11_LEVEL_HIGH */ + __IM uint32_t GPIO11_EDGE_LOW : 1; /*!< GPIO11_EDGE_LOW */ + __IM uint32_t GPIO11_EDGE_HIGH : 1; /*!< GPIO11_EDGE_HIGH */ + __IM uint32_t GPIO12_LEVEL_LOW : 1; /*!< GPIO12_LEVEL_LOW */ + __IM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< GPIO12_LEVEL_HIGH */ + __IM uint32_t GPIO12_EDGE_LOW : 1; /*!< GPIO12_EDGE_LOW */ + __IM uint32_t GPIO12_EDGE_HIGH : 1; /*!< GPIO12_EDGE_HIGH */ + __IM uint32_t GPIO13_LEVEL_LOW : 1; /*!< GPIO13_LEVEL_LOW */ + __IM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< GPIO13_LEVEL_HIGH */ + __IM uint32_t GPIO13_EDGE_LOW : 1; /*!< GPIO13_EDGE_LOW */ + __IM uint32_t GPIO13_EDGE_HIGH : 1; /*!< GPIO13_EDGE_HIGH */ + __IM uint32_t GPIO14_LEVEL_LOW : 1; /*!< GPIO14_LEVEL_LOW */ + __IM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< GPIO14_LEVEL_HIGH */ + __IM uint32_t GPIO14_EDGE_LOW : 1; /*!< GPIO14_EDGE_LOW */ + __IM uint32_t GPIO14_EDGE_HIGH : 1; /*!< GPIO14_EDGE_HIGH */ + __IM uint32_t GPIO15_LEVEL_LOW : 1; /*!< GPIO15_LEVEL_LOW */ + __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< GPIO15_LEVEL_HIGH */ + __IM uint32_t GPIO15_EDGE_LOW : 1; /*!< GPIO15_EDGE_LOW */ + __IM uint32_t GPIO15_EDGE_HIGH : 1; /*!< GPIO15_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTS1; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for dormant_wake */ + + struct { + __IM uint32_t GPIO16_LEVEL_LOW : 1; /*!< GPIO16_LEVEL_LOW */ + __IM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< GPIO16_LEVEL_HIGH */ + __IM uint32_t GPIO16_EDGE_LOW : 1; /*!< GPIO16_EDGE_LOW */ + __IM uint32_t GPIO16_EDGE_HIGH : 1; /*!< GPIO16_EDGE_HIGH */ + __IM uint32_t GPIO17_LEVEL_LOW : 1; /*!< GPIO17_LEVEL_LOW */ + __IM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< GPIO17_LEVEL_HIGH */ + __IM uint32_t GPIO17_EDGE_LOW : 1; /*!< GPIO17_EDGE_LOW */ + __IM uint32_t GPIO17_EDGE_HIGH : 1; /*!< GPIO17_EDGE_HIGH */ + __IM uint32_t GPIO18_LEVEL_LOW : 1; /*!< GPIO18_LEVEL_LOW */ + __IM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< GPIO18_LEVEL_HIGH */ + __IM uint32_t GPIO18_EDGE_LOW : 1; /*!< GPIO18_EDGE_LOW */ + __IM uint32_t GPIO18_EDGE_HIGH : 1; /*!< GPIO18_EDGE_HIGH */ + __IM uint32_t GPIO19_LEVEL_LOW : 1; /*!< GPIO19_LEVEL_LOW */ + __IM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< GPIO19_LEVEL_HIGH */ + __IM uint32_t GPIO19_EDGE_LOW : 1; /*!< GPIO19_EDGE_LOW */ + __IM uint32_t GPIO19_EDGE_HIGH : 1; /*!< GPIO19_EDGE_HIGH */ + __IM uint32_t GPIO20_LEVEL_LOW : 1; /*!< GPIO20_LEVEL_LOW */ + __IM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< GPIO20_LEVEL_HIGH */ + __IM uint32_t GPIO20_EDGE_LOW : 1; /*!< GPIO20_EDGE_LOW */ + __IM uint32_t GPIO20_EDGE_HIGH : 1; /*!< GPIO20_EDGE_HIGH */ + __IM uint32_t GPIO21_LEVEL_LOW : 1; /*!< GPIO21_LEVEL_LOW */ + __IM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< GPIO21_LEVEL_HIGH */ + __IM uint32_t GPIO21_EDGE_LOW : 1; /*!< GPIO21_EDGE_LOW */ + __IM uint32_t GPIO21_EDGE_HIGH : 1; /*!< GPIO21_EDGE_HIGH */ + __IM uint32_t GPIO22_LEVEL_LOW : 1; /*!< GPIO22_LEVEL_LOW */ + __IM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< GPIO22_LEVEL_HIGH */ + __IM uint32_t GPIO22_EDGE_LOW : 1; /*!< GPIO22_EDGE_LOW */ + __IM uint32_t GPIO22_EDGE_HIGH : 1; /*!< GPIO22_EDGE_HIGH */ + __IM uint32_t GPIO23_LEVEL_LOW : 1; /*!< GPIO23_LEVEL_LOW */ + __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< GPIO23_LEVEL_HIGH */ + __IM uint32_t GPIO23_EDGE_LOW : 1; /*!< GPIO23_EDGE_LOW */ + __IM uint32_t GPIO23_EDGE_HIGH : 1; /*!< GPIO23_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTS2; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for dormant_wake */ + + struct { + __IM uint32_t GPIO24_LEVEL_LOW : 1; /*!< GPIO24_LEVEL_LOW */ + __IM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< GPIO24_LEVEL_HIGH */ + __IM uint32_t GPIO24_EDGE_LOW : 1; /*!< GPIO24_EDGE_LOW */ + __IM uint32_t GPIO24_EDGE_HIGH : 1; /*!< GPIO24_EDGE_HIGH */ + __IM uint32_t GPIO25_LEVEL_LOW : 1; /*!< GPIO25_LEVEL_LOW */ + __IM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< GPIO25_LEVEL_HIGH */ + __IM uint32_t GPIO25_EDGE_LOW : 1; /*!< GPIO25_EDGE_LOW */ + __IM uint32_t GPIO25_EDGE_HIGH : 1; /*!< GPIO25_EDGE_HIGH */ + __IM uint32_t GPIO26_LEVEL_LOW : 1; /*!< GPIO26_LEVEL_LOW */ + __IM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< GPIO26_LEVEL_HIGH */ + __IM uint32_t GPIO26_EDGE_LOW : 1; /*!< GPIO26_EDGE_LOW */ + __IM uint32_t GPIO26_EDGE_HIGH : 1; /*!< GPIO26_EDGE_HIGH */ + __IM uint32_t GPIO27_LEVEL_LOW : 1; /*!< GPIO27_LEVEL_LOW */ + __IM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< GPIO27_LEVEL_HIGH */ + __IM uint32_t GPIO27_EDGE_LOW : 1; /*!< GPIO27_EDGE_LOW */ + __IM uint32_t GPIO27_EDGE_HIGH : 1; /*!< GPIO27_EDGE_HIGH */ + __IM uint32_t GPIO28_LEVEL_LOW : 1; /*!< GPIO28_LEVEL_LOW */ + __IM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< GPIO28_LEVEL_HIGH */ + __IM uint32_t GPIO28_EDGE_LOW : 1; /*!< GPIO28_EDGE_LOW */ + __IM uint32_t GPIO28_EDGE_HIGH : 1; /*!< GPIO28_EDGE_HIGH */ + __IM uint32_t GPIO29_LEVEL_LOW : 1; /*!< GPIO29_LEVEL_LOW */ + __IM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< GPIO29_LEVEL_HIGH */ + __IM uint32_t GPIO29_EDGE_LOW : 1; /*!< GPIO29_EDGE_LOW */ + __IM uint32_t GPIO29_EDGE_HIGH : 1; /*!< GPIO29_EDGE_HIGH */ + __IM uint32_t GPIO30_LEVEL_LOW : 1; /*!< GPIO30_LEVEL_LOW */ + __IM uint32_t GPIO30_LEVEL_HIGH : 1; /*!< GPIO30_LEVEL_HIGH */ + __IM uint32_t GPIO30_EDGE_LOW : 1; /*!< GPIO30_EDGE_LOW */ + __IM uint32_t GPIO30_EDGE_HIGH : 1; /*!< GPIO30_EDGE_HIGH */ + __IM uint32_t GPIO31_LEVEL_LOW : 1; /*!< GPIO31_LEVEL_LOW */ + __IM uint32_t GPIO31_LEVEL_HIGH : 1; /*!< GPIO31_LEVEL_HIGH */ + __IM uint32_t GPIO31_EDGE_LOW : 1; /*!< GPIO31_EDGE_LOW */ + __IM uint32_t GPIO31_EDGE_HIGH : 1; /*!< GPIO31_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTS3; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for dormant_wake */ + + struct { + __IM uint32_t GPIO32_LEVEL_LOW : 1; /*!< GPIO32_LEVEL_LOW */ + __IM uint32_t GPIO32_LEVEL_HIGH : 1; /*!< GPIO32_LEVEL_HIGH */ + __IM uint32_t GPIO32_EDGE_LOW : 1; /*!< GPIO32_EDGE_LOW */ + __IM uint32_t GPIO32_EDGE_HIGH : 1; /*!< GPIO32_EDGE_HIGH */ + __IM uint32_t GPIO33_LEVEL_LOW : 1; /*!< GPIO33_LEVEL_LOW */ + __IM uint32_t GPIO33_LEVEL_HIGH : 1; /*!< GPIO33_LEVEL_HIGH */ + __IM uint32_t GPIO33_EDGE_LOW : 1; /*!< GPIO33_EDGE_LOW */ + __IM uint32_t GPIO33_EDGE_HIGH : 1; /*!< GPIO33_EDGE_HIGH */ + __IM uint32_t GPIO34_LEVEL_LOW : 1; /*!< GPIO34_LEVEL_LOW */ + __IM uint32_t GPIO34_LEVEL_HIGH : 1; /*!< GPIO34_LEVEL_HIGH */ + __IM uint32_t GPIO34_EDGE_LOW : 1; /*!< GPIO34_EDGE_LOW */ + __IM uint32_t GPIO34_EDGE_HIGH : 1; /*!< GPIO34_EDGE_HIGH */ + __IM uint32_t GPIO35_LEVEL_LOW : 1; /*!< GPIO35_LEVEL_LOW */ + __IM uint32_t GPIO35_LEVEL_HIGH : 1; /*!< GPIO35_LEVEL_HIGH */ + __IM uint32_t GPIO35_EDGE_LOW : 1; /*!< GPIO35_EDGE_LOW */ + __IM uint32_t GPIO35_EDGE_HIGH : 1; /*!< GPIO35_EDGE_HIGH */ + __IM uint32_t GPIO36_LEVEL_LOW : 1; /*!< GPIO36_LEVEL_LOW */ + __IM uint32_t GPIO36_LEVEL_HIGH : 1; /*!< GPIO36_LEVEL_HIGH */ + __IM uint32_t GPIO36_EDGE_LOW : 1; /*!< GPIO36_EDGE_LOW */ + __IM uint32_t GPIO36_EDGE_HIGH : 1; /*!< GPIO36_EDGE_HIGH */ + __IM uint32_t GPIO37_LEVEL_LOW : 1; /*!< GPIO37_LEVEL_LOW */ + __IM uint32_t GPIO37_LEVEL_HIGH : 1; /*!< GPIO37_LEVEL_HIGH */ + __IM uint32_t GPIO37_EDGE_LOW : 1; /*!< GPIO37_EDGE_LOW */ + __IM uint32_t GPIO37_EDGE_HIGH : 1; /*!< GPIO37_EDGE_HIGH */ + __IM uint32_t GPIO38_LEVEL_LOW : 1; /*!< GPIO38_LEVEL_LOW */ + __IM uint32_t GPIO38_LEVEL_HIGH : 1; /*!< GPIO38_LEVEL_HIGH */ + __IM uint32_t GPIO38_EDGE_LOW : 1; /*!< GPIO38_EDGE_LOW */ + __IM uint32_t GPIO38_EDGE_HIGH : 1; /*!< GPIO38_EDGE_HIGH */ + __IM uint32_t GPIO39_LEVEL_LOW : 1; /*!< GPIO39_LEVEL_LOW */ + __IM uint32_t GPIO39_LEVEL_HIGH : 1; /*!< GPIO39_LEVEL_HIGH */ + __IM uint32_t GPIO39_EDGE_LOW : 1; /*!< GPIO39_EDGE_LOW */ + __IM uint32_t GPIO39_EDGE_HIGH : 1; /*!< GPIO39_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTS4; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for dormant_wake */ + + struct { + __IM uint32_t GPIO40_LEVEL_LOW : 1; /*!< GPIO40_LEVEL_LOW */ + __IM uint32_t GPIO40_LEVEL_HIGH : 1; /*!< GPIO40_LEVEL_HIGH */ + __IM uint32_t GPIO40_EDGE_LOW : 1; /*!< GPIO40_EDGE_LOW */ + __IM uint32_t GPIO40_EDGE_HIGH : 1; /*!< GPIO40_EDGE_HIGH */ + __IM uint32_t GPIO41_LEVEL_LOW : 1; /*!< GPIO41_LEVEL_LOW */ + __IM uint32_t GPIO41_LEVEL_HIGH : 1; /*!< GPIO41_LEVEL_HIGH */ + __IM uint32_t GPIO41_EDGE_LOW : 1; /*!< GPIO41_EDGE_LOW */ + __IM uint32_t GPIO41_EDGE_HIGH : 1; /*!< GPIO41_EDGE_HIGH */ + __IM uint32_t GPIO42_LEVEL_LOW : 1; /*!< GPIO42_LEVEL_LOW */ + __IM uint32_t GPIO42_LEVEL_HIGH : 1; /*!< GPIO42_LEVEL_HIGH */ + __IM uint32_t GPIO42_EDGE_LOW : 1; /*!< GPIO42_EDGE_LOW */ + __IM uint32_t GPIO42_EDGE_HIGH : 1; /*!< GPIO42_EDGE_HIGH */ + __IM uint32_t GPIO43_LEVEL_LOW : 1; /*!< GPIO43_LEVEL_LOW */ + __IM uint32_t GPIO43_LEVEL_HIGH : 1; /*!< GPIO43_LEVEL_HIGH */ + __IM uint32_t GPIO43_EDGE_LOW : 1; /*!< GPIO43_EDGE_LOW */ + __IM uint32_t GPIO43_EDGE_HIGH : 1; /*!< GPIO43_EDGE_HIGH */ + __IM uint32_t GPIO44_LEVEL_LOW : 1; /*!< GPIO44_LEVEL_LOW */ + __IM uint32_t GPIO44_LEVEL_HIGH : 1; /*!< GPIO44_LEVEL_HIGH */ + __IM uint32_t GPIO44_EDGE_LOW : 1; /*!< GPIO44_EDGE_LOW */ + __IM uint32_t GPIO44_EDGE_HIGH : 1; /*!< GPIO44_EDGE_HIGH */ + __IM uint32_t GPIO45_LEVEL_LOW : 1; /*!< GPIO45_LEVEL_LOW */ + __IM uint32_t GPIO45_LEVEL_HIGH : 1; /*!< GPIO45_LEVEL_HIGH */ + __IM uint32_t GPIO45_EDGE_LOW : 1; /*!< GPIO45_EDGE_LOW */ + __IM uint32_t GPIO45_EDGE_HIGH : 1; /*!< GPIO45_EDGE_HIGH */ + __IM uint32_t GPIO46_LEVEL_LOW : 1; /*!< GPIO46_LEVEL_LOW */ + __IM uint32_t GPIO46_LEVEL_HIGH : 1; /*!< GPIO46_LEVEL_HIGH */ + __IM uint32_t GPIO46_EDGE_LOW : 1; /*!< GPIO46_EDGE_LOW */ + __IM uint32_t GPIO46_EDGE_HIGH : 1; /*!< GPIO46_EDGE_HIGH */ + __IM uint32_t GPIO47_LEVEL_LOW : 1; /*!< GPIO47_LEVEL_LOW */ + __IM uint32_t GPIO47_LEVEL_HIGH : 1; /*!< GPIO47_LEVEL_HIGH */ + __IM uint32_t GPIO47_EDGE_LOW : 1; /*!< GPIO47_EDGE_LOW */ + __IM uint32_t GPIO47_EDGE_HIGH : 1; /*!< GPIO47_EDGE_HIGH */ + } bit; + } DORMANT_WAKE_INTS5; +} IO_BANK0_Type; /*!< Size = 800 (0x320) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSINFO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SYSINFO (SYSINFO) + */ + +typedef struct { /*!< SYSINFO Structure */ + + union { + __IOM uint32_t reg; /*!< JEDEC JEP-106 compliant chip identifier. */ + + struct { + __IM uint32_t STOP_BIT : 1; /*!< STOP_BIT */ + __IM uint32_t MANUFACTURER : 11; /*!< MANUFACTURER */ + __IM uint32_t PART : 16; /*!< PART */ + __IM uint32_t REVISION : 4; /*!< REVISION */ + } bit; + } CHIP_ID; + + union { + __IOM uint32_t reg; /*!< PACKAGE_SEL */ + + struct { + __IM uint32_t PACKAGE_SEL : 1; /*!< PACKAGE_SEL */ + uint32_t : 31; + } bit; + } PACKAGE_SEL; + + union { + __IOM uint32_t reg; /*!< Platform register. Allows software to know what environment + it is running in during pre-production development. Post-production, + the PLATFORM is always ASIC, non-SIM. */ + + struct { + __IM uint32_t FPGA : 1; /*!< FPGA */ + __IM uint32_t ASIC : 1; /*!< ASIC */ + __IM uint32_t HDLSIM : 1; /*!< HDLSIM */ + __IM uint32_t BATCHSIM : 1; /*!< BATCHSIM */ + __IM uint32_t GATESIM : 1; /*!< GATESIM */ + uint32_t : 27; + } bit; + } PLATFORM; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t reg; /*!< Git hash of the chip source. Used to identify chip version. */ + + struct { + __IM uint32_t GITREF_RP2350 : 32; /*!< GITREF_RP2350 */ + } bit; + } GITREF_RP2350; +} SYSINFO_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ SHA256 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SHA-256 hash function implementation (SHA256) + */ + +typedef struct { /*!< SHA256 Structure */ + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __OM uint32_t START : 1; /*!< Write 1 to prepare the SHA-256 core for a new checksum. The + SUMx registers are initialised to the proper values (fractional + bits of square roots of first 8 primes) and internal counters + are cleared. This immediately forces WDATA_RDY and SUM_VLD + high. START must be written before initiating a DMA transfer + to the SHA-256 core, because the core will always request + 16 transfers at a time (1 512-bit block). Additionally, + the DMA channel should be configured for a multiple of + 16 32-bit transfers. */ + __IM uint32_t WDATA_RDY : 1; /*!< If 1, the SHA-256 core is ready to accept more data through + the WDATA register. After writing 16 words, this flag will + go low for 57 cycles whilst the core completes its digest. */ + __IM uint32_t SUM_VLD : 1; /*!< If 1, the SHA-256 checksum presented in registers SUM0 through + SUM7 is currently valid. Goes low when WDATA is first written, + then returns high once 16 words have been written and the + digest of the current 512-bit block has subsequently completed. */ + uint32_t : 1; + __IOM uint32_t ERR_WDATA_NOT_RDY : 1; /*!< Set when a write occurs whilst the SHA-256 core is not ready + for data (WDATA_RDY is low). Write one to clear. */ + uint32_t : 3; + __IOM uint32_t DMA_SIZE : 2; /*!< Configure DREQ logic for the correct DMA data size. Must be + configured before the DMA channel is triggered. The SHA-256 + core's DREQ logic requests one entire block of data at + once, since there is no FIFO, and data goes straight into + the core's message schedule and digest hardware. Therefore, + when transferring data with DMA, CSR_DMA_SIZE must be configured + in advance so that the correct number of transfers can + be requested per block. */ + uint32_t : 2; + __IOM uint32_t BSWAP : 1; /*!< Enable byte swapping of 32-bit values at the point they are + committed to the SHA message scheduler. This block's bus + interface assembles byte/halfword data into message words + in little-endian order, so that DMAing the same buffer + with different transfer sizes always gives the same result + on a little-endian system like RP2350. However, when marshalling + bytes into blocks, SHA expects that the first byte is the + *most significant* in each message word. To resolve this, + once the bus interface has accumulated 32 bits of data + (either a word write, two halfword writes in little-endian + order, or four byte writes in little-endian order) the + final value can be byte-swapped before passing to the actual + SHA core. This feature is enabled by default because using + the SHA core to checksum byte buffers is expected to be + more common than having preformatted SHA message words + lying around. */ + uint32_t : 19; + } bit; + } CSR; + + union { + __IOM uint32_t reg; /*!< Write data register */ + + struct { + __OM uint32_t WDATA : 32; /*!< After pulsing START and writing 16 words of data to this register, + WDATA_RDY will go low and the SHA-256 core will complete + the digest of the current 512-bit block. Software is responsible + for ensuring the data is correctly padded and terminated + to a whole number of 512-bit blocks. After this, WDATA_RDY + will return high, and more data can be written (if any). + This register supports word, halfword and byte writes, + so that DMA from non-word-aligned buffers can be supported. + The total amount of data per block remains the same (16 + words, 32 halfwords or 64 bytes) and byte/halfword transfers + must not be mixed within a block. */ + } bit; + } WDATA; + + union { + __IOM uint32_t reg; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + + struct { + __IM uint32_t SUM0 : 32; /*!< SUM0 */ + } bit; + } SUM0; + + union { + __IOM uint32_t reg; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + + struct { + __IM uint32_t SUM1 : 32; /*!< SUM1 */ + } bit; + } SUM1; + + union { + __IOM uint32_t reg; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + + struct { + __IM uint32_t SUM2 : 32; /*!< SUM2 */ + } bit; + } SUM2; + + union { + __IOM uint32_t reg; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + + struct { + __IM uint32_t SUM3 : 32; /*!< SUM3 */ + } bit; + } SUM3; + + union { + __IOM uint32_t reg; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + + struct { + __IM uint32_t SUM4 : 32; /*!< SUM4 */ + } bit; + } SUM4; + + union { + __IOM uint32_t reg; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + + struct { + __IM uint32_t SUM5 : 32; /*!< SUM5 */ + } bit; + } SUM5; + + union { + __IOM uint32_t reg; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + + struct { + __IM uint32_t SUM6 : 32; /*!< SUM6 */ + } bit; + } SUM6; + + union { + __IOM uint32_t reg; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + + struct { + __IM uint32_t SUM7 : 32; /*!< SUM7 */ + } bit; + } SUM7; +} SHA256_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ HSTX_FIFO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FIFO status and write access for HSTX (HSTX_FIFO) + */ + +typedef struct { /*!< HSTX_FIFO Structure */ + + union { + __IOM uint32_t reg; /*!< FIFO status */ + + struct { + __IM uint32_t LEVEL : 8; /*!< LEVEL */ + __IM uint32_t FULL : 1; /*!< FULL */ + __IM uint32_t EMPTY : 1; /*!< EMPTY */ + __IOM uint32_t WOF : 1; /*!< FIFO was written when full. Write 1 to clear. */ + uint32_t : 21; + } bit; + } STAT; + + union { + __IOM uint32_t reg; /*!< Write access to FIFO */ + + struct { + __OM uint32_t FIFO : 32; /*!< FIFO */ + } bit; + } FIFO; +} HSTX_FIFO_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ HSTX_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. (HSTX_CTRL) + */ + +typedef struct { /*!< HSTX_CTRL Structure */ + + union { + __IOM uint32_t reg; /*!< CSR */ + + struct { + __IOM uint32_t EN : 1; /*!< When EN is 1, the HSTX will shift out data as it appears in + the FIFO. As long as there is data, the HSTX shift register + will shift once per clock cycle, and the frequency of popping + from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. + When EN is 0, the FIFO is not popped. The shift counter + and clock generator are also reset to their initial state + for as long as EN is low. Note the initial phase of the + clock generator can be configured by the CLKPHASE field. + Once the HSTX is enabled again, and data is pushed to the + FIFO, the generated clock's first rising edge will be one + half-period after the first data is launched. */ + __IOM uint32_t EXPAND_EN : 1; /*!< Enable the command expander. When 0, raw FIFO data is passed + directly to the output shift register. When 1, the command + expander can perform simple operations such as run length + decoding on data between the FIFO and the shift register. + Do not change CXPD_EN whilst EN is set. It's safe to set + CXPD_EN simultaneously with setting EN. */ + uint32_t : 2; + __IOM uint32_t COUPLED_MODE : 1; /*!< Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked + *directly* from the system clock (not just from some other + clock source of the same frequency) for this synchronous + interface to function correctly. When COUPLED_MODE is set, + BITx_SEL_P and SEL_N indices 24 through 31 will select + bits from the 8-bit PIO-to-HSTX path, rather than shifter + bits. Indices of 0 through 23 will still index the shift + register as normal. The PIO outputs connected to the PIO-to-HSTX + bus are those same outputs that would appear on the HSTX-capable + pins if those pins' FUNCSELs were set to PIO instead of + HSTX. For example, if HSTX is on GPIOs 12 through 19, then + PIO outputs 12 through 19 are connected to the HSTX when + coupled mode is engaged. */ + __IOM uint32_t COUPLED_SEL : 2; /*!< Select which PIO to use for coupled mode operation. */ + uint32_t : 1; + __IOM uint32_t SHIFT : 5; /*!< How many bits to right-rotate the shift register by each cycle. + The use of a rotate rather than a shift allows left shifts + to be emulated, by subtracting the left-shift amount from + 32. It also allows data to be repeated, when the product + of SHIFT and N_SHIFTS is greater than 32. */ + uint32_t : 3; + __IOM uint32_t N_SHIFTS : 5; /*!< Number of times to shift the shift register before refilling + it from the FIFO. (A count of how many times it has been + shifted, *not* the total shift distance.) A register value + of 0 means shift 32 times. */ + uint32_t : 3; + __IOM uint32_t CLKPHASE : 4; /*!< Set the initial phase of the generated clock. A CLKPHASE of + 0 means the clock is initially low, and the first rising + edge occurs after one half period of the generated clock + (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE + by 1 will advance the initial clock phase by one half clk_hstx + period. For example, if CLKDIV=2 and CLKPHASE=1: * The + clock will be initially low * The first rising edge will + be 0.5 clk_hstx cycles after asserting first data * The + first falling edge will be 1.5 clk_hstx cycles after asserting + first data This configuration would be suitable for serialising + at a bit rate of clk_hstx with a centre-aligned DDR clock. + When the HSTX is halted by clearing CSR_EN, the clock generator + will return to its initial phase as configured by the CLKPHASE + field. Note CLKPHASE must be strictly less than double + the value of CLKDIV (one full period), else its operation + is undefined. */ + __IOM uint32_t CLKDIV : 4; /*!< Clock period of the generated clock, measured in HSTX clock + cycles. Can be odd or even. The generated clock advances + only on cycles where the shift register shifts. For example, + a clkdiv of 5 would generate a complete output clock period + for every 5 HSTX clocks (or every 10 half-clocks). A CLKDIV + value of 0 is mapped to a period of 16 HSTX clock cycles. */ + } bit; + } CSR; + + union { + __IOM uint32_t reg; /*!< Data control register for output bit 0 */ + + struct { + __IOM uint32_t SEL_P : 5; /*!< Shift register data bit select for the first half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t SEL_N : 5; /*!< Shift register data bit select for the second half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t INV : 1; /*!< Invert this data output (logical NOT) */ + __IOM uint32_t CLK : 1; /*!< Connect this output to the generated clock, rather than the + data shift register. SEL_P and SEL_N are ignored if this + bit is set, but INV can still be set to generate an antiphase + clock. */ + uint32_t : 14; + } bit; + } BIT0; + + union { + __IOM uint32_t reg; /*!< Data control register for output bit 1 */ + + struct { + __IOM uint32_t SEL_P : 5; /*!< Shift register data bit select for the first half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t SEL_N : 5; /*!< Shift register data bit select for the second half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t INV : 1; /*!< Invert this data output (logical NOT) */ + __IOM uint32_t CLK : 1; /*!< Connect this output to the generated clock, rather than the + data shift register. SEL_P and SEL_N are ignored if this + bit is set, but INV can still be set to generate an antiphase + clock. */ + uint32_t : 14; + } bit; + } BIT1; + + union { + __IOM uint32_t reg; /*!< Data control register for output bit 2 */ + + struct { + __IOM uint32_t SEL_P : 5; /*!< Shift register data bit select for the first half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t SEL_N : 5; /*!< Shift register data bit select for the second half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t INV : 1; /*!< Invert this data output (logical NOT) */ + __IOM uint32_t CLK : 1; /*!< Connect this output to the generated clock, rather than the + data shift register. SEL_P and SEL_N are ignored if this + bit is set, but INV can still be set to generate an antiphase + clock. */ + uint32_t : 14; + } bit; + } BIT2; + + union { + __IOM uint32_t reg; /*!< Data control register for output bit 3 */ + + struct { + __IOM uint32_t SEL_P : 5; /*!< Shift register data bit select for the first half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t SEL_N : 5; /*!< Shift register data bit select for the second half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t INV : 1; /*!< Invert this data output (logical NOT) */ + __IOM uint32_t CLK : 1; /*!< Connect this output to the generated clock, rather than the + data shift register. SEL_P and SEL_N are ignored if this + bit is set, but INV can still be set to generate an antiphase + clock. */ + uint32_t : 14; + } bit; + } BIT3; + + union { + __IOM uint32_t reg; /*!< Data control register for output bit 4 */ + + struct { + __IOM uint32_t SEL_P : 5; /*!< Shift register data bit select for the first half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t SEL_N : 5; /*!< Shift register data bit select for the second half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t INV : 1; /*!< Invert this data output (logical NOT) */ + __IOM uint32_t CLK : 1; /*!< Connect this output to the generated clock, rather than the + data shift register. SEL_P and SEL_N are ignored if this + bit is set, but INV can still be set to generate an antiphase + clock. */ + uint32_t : 14; + } bit; + } BIT4; + + union { + __IOM uint32_t reg; /*!< Data control register for output bit 5 */ + + struct { + __IOM uint32_t SEL_P : 5; /*!< Shift register data bit select for the first half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t SEL_N : 5; /*!< Shift register data bit select for the second half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t INV : 1; /*!< Invert this data output (logical NOT) */ + __IOM uint32_t CLK : 1; /*!< Connect this output to the generated clock, rather than the + data shift register. SEL_P and SEL_N are ignored if this + bit is set, but INV can still be set to generate an antiphase + clock. */ + uint32_t : 14; + } bit; + } BIT5; + + union { + __IOM uint32_t reg; /*!< Data control register for output bit 6 */ + + struct { + __IOM uint32_t SEL_P : 5; /*!< Shift register data bit select for the first half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t SEL_N : 5; /*!< Shift register data bit select for the second half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t INV : 1; /*!< Invert this data output (logical NOT) */ + __IOM uint32_t CLK : 1; /*!< Connect this output to the generated clock, rather than the + data shift register. SEL_P and SEL_N are ignored if this + bit is set, but INV can still be set to generate an antiphase + clock. */ + uint32_t : 14; + } bit; + } BIT6; + + union { + __IOM uint32_t reg; /*!< Data control register for output bit 7 */ + + struct { + __IOM uint32_t SEL_P : 5; /*!< Shift register data bit select for the first half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t SEL_N : 5; /*!< Shift register data bit select for the second half of the HSTX + clock cycle */ + uint32_t : 3; + __IOM uint32_t INV : 1; /*!< Invert this data output (logical NOT) */ + __IOM uint32_t CLK : 1; /*!< Connect this output to the generated clock, rather than the + data shift register. SEL_P and SEL_N are ignored if this + bit is set, but INV can still be set to generate an antiphase + clock. */ + uint32_t : 14; + } bit; + } BIT7; + + union { + __IOM uint32_t reg; /*!< Configure the optional shifter inside the command expander */ + + struct { + __IOM uint32_t RAW_SHIFT : 5; /*!< How many bits to right-rotate the shift register by each time + data is pushed to the output shifter, when the current + command is a raw data command. */ + uint32_t : 3; + __IOM uint32_t RAW_N_SHIFTS : 5; /*!< Number of times to consume from the shift register before refilling + it from the FIFO, when the current command is a raw data + command. A register value of 0 means shift 32 times. */ + uint32_t : 3; + __IOM uint32_t ENC_SHIFT : 5; /*!< How many bits to right-rotate the shift register by each time + data is pushed to the output shifter, when the current + command is an encoded data command (e.g. TMDS). */ + uint32_t : 3; + __IOM uint32_t ENC_N_SHIFTS : 5; /*!< Number of times to consume from the shift register before refilling + it from the FIFO, when the current command is an encoded + data command (e.g. TMDS). A register value of 0 means shift + 32 times. */ + uint32_t : 3; + } bit; + } EXPAND_SHIFT; + + union { + __IOM uint32_t reg; /*!< Configure the optional TMDS encoder inside the command expander */ + + struct { + __IOM uint32_t L0_ROT : 5; /*!< Right-rotate applied to the current shifter data before the + lane 0 TMDS encoder. */ + __IOM uint32_t L0_NBITS : 3; /*!< Number of valid data bits for the lane 0 TMDS encoder, starting + from bit 7 of the rotated data. Field values of 0 -> 7 + encode counts of 1 -> 8 bits. */ + __IOM uint32_t L1_ROT : 5; /*!< Right-rotate applied to the current shifter data before the + lane 1 TMDS encoder. */ + __IOM uint32_t L1_NBITS : 3; /*!< Number of valid data bits for the lane 1 TMDS encoder, starting + from bit 7 of the rotated data. Field values of 0 -> 7 + encode counts of 1 -> 8 bits. */ + __IOM uint32_t L2_ROT : 5; /*!< Right-rotate applied to the current shifter data before the + lane 2 TMDS encoder. */ + __IOM uint32_t L2_NBITS : 3; /*!< Number of valid data bits for the lane 2 TMDS encoder, starting + from bit 7 of the rotated data. Field values of 0 -> 7 + encode counts of 1 -> 8 bits. */ + uint32_t : 8; + } bit; + } EXPAND_TMDS; +} HSTX_CTRL_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ EPPB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Cortex-M33 EPPB vendor register block for RP2350 (EPPB) + */ + +typedef struct { /*!< EPPB Structure */ + + union { + __IOM uint32_t reg; /*!< NMI mask for IRQs 0 through 31. This register is core-local, + and is reset by a processor warm reset. */ + + struct { + __IOM uint32_t NMI_MASK0 : 32; /*!< NMI_MASK0 */ + } bit; + } NMI_MASK0; + + union { + __IOM uint32_t reg; /*!< NMI mask for IRQs 0 though 51. This register is core-local, + and is reset by a processor warm reset. */ + + struct { + __IOM uint32_t NMI_MASK1 : 20; /*!< NMI_MASK1 */ + uint32_t : 12; + } bit; + } NMI_MASK1; + + union { + __IOM uint32_t reg; /*!< Nonstandard sleep control register */ + + struct { + __IOM uint32_t LIGHT_SLEEP : 1; /*!< By default, any processor sleep will deassert the system-level + clock request. Reenabling the clocks incurs 5 cycles of + additional latency on wakeup. Setting LIGHT_SLEEP to 1 + keeps the clock request asserted during a normal sleep + (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep + sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will + always deassert the system-level clock request. */ + __IOM uint32_t WICENREQ : 1; /*!< Request that the next processor deep sleep is a WIC sleep. After + setting this bit, before sleeping, poll WICENACK to ensure + the processor interrupt controller has acknowledged the + change. */ + __IM uint32_t WICENACK : 1; /*!< Status signal from the processor's interrupt controller. Changes + to WICENREQ are eventually reflected in WICENACK. */ + uint32_t : 29; + } bit; + } SLEEPCTRL; +} EPPB_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ PPB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TEAL registers accessible through the debug interface (PPB) + */ + +typedef struct { /*!< PPB Structure */ + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM0; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM1; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM2; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM3; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM4; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM5; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM6; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM7; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM8; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM9; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM10; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM11; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM12; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM13; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM14; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM15; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM16; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM17; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM18; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM19; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM20; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM21; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM22; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM23; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM24; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM25; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM26; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM27; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM28; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM29; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM30; + + union { + __IOM uint32_t reg; /*!< Provides the interface for generating Instrumentation packets */ + + struct { + __IOM uint32_t STIMULUS : 32; /*!< Data to write to the Stimulus Port FIFO, for forwarding as an + Instrumentation packet. The size of write access determines + the type of Instrumentation packet generated. */ + } bit; + } ITM_STIM31; + __IM uint32_t RESERVED[864]; + + union { + __IOM uint32_t reg; /*!< Provide an individual enable bit for each ITM_STIM register */ + + struct { + __IOM uint32_t STIMENA : 32; /*!< For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + + m) is enabled */ + } bit; + } ITM_TER0; + __IM uint32_t RESERVED1[15]; + + union { + __IOM uint32_t reg; /*!< Controls which stimulus ports can be accessed by unprivileged + code */ + + struct { + __IOM uint32_t PRIVMASK : 4; /*!< Bit mask to enable tracing on ITM stimulus ports */ + uint32_t : 28; + } bit; + } ITM_TPR; + __IM uint32_t RESERVED2[15]; + + union { + __IOM uint32_t reg; /*!< Configures and controls transfers through the ITM interface */ + + struct { + __IOM uint32_t ITMENA : 1; /*!< Enables the ITM */ + __IOM uint32_t TSENA : 1; /*!< Enables Local timestamp generation */ + __IOM uint32_t SYNCENA : 1; /*!< Enables Synchronization packet transmission for a synchronous + TPIU */ + __IOM uint32_t TXENA : 1; /*!< Enables forwarding of hardware event packet from the DWT unit + to the ITM for output to the TPIU */ + __IOM uint32_t SWOENA : 1; /*!< Enables asynchronous clocking of the timestamp counter */ + __IOM uint32_t STALLENA : 1; /*!< Stall the PE to guarantee delivery of Data Trace packets. */ + uint32_t : 2; + __IOM uint32_t TSPRESCALE : 2; /*!< Local timestamp prescaler, used with the trace packet reference + clock */ + __IOM uint32_t GTSFREQ : 2; /*!< Defines how often the ITM generates a global timestamp, based + on the global timestamp clock frequency, or disables generation + of global timestamps */ + uint32_t : 4; + __IOM uint32_t TRACEBUSID : 7; /*!< Identifier for multi-source trace stream formatting. If multi-source + trace is in use, the debugger must write a unique non-zero + trace ID value to this field */ + __IM uint32_t BUSY : 1; /*!< Indicates whether the ITM is currently processing events */ + uint32_t : 8; + } bit; + } ITM_TCR; + __IM uint32_t RESERVED3[27]; + + union { + __IOM uint32_t reg; /*!< Integration Mode: Read ATB Ready */ + + struct { + __IM uint32_t ATREADY : 1; /*!< A read of this bit returns the value of ATREADY */ + __IM uint32_t AFVALID : 1; /*!< A read of this bit returns the value of AFVALID */ + uint32_t : 30; + } bit; + } INT_ATREADY; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t reg; /*!< Integration Mode: Write ATB Valid */ + + struct { + __IOM uint32_t ATREADY : 1; /*!< A write to this bit gives the value of ATVALID */ + __IOM uint32_t AFREADY : 1; /*!< A write to this bit gives the value of AFREADY */ + uint32_t : 30; + } bit; + } INT_ATVALID; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t reg; /*!< Integration Mode Control Register */ + + struct { + __IOM uint32_t IME : 1; /*!< Integration mode enable bit - The possible values are: 0 - The + trace unit is not in integration mode. 1 - The trace unit + is in integration mode. This mode enables: A debug agent + to perform topology detection. SoC test software to perform + integration testing. */ + uint32_t : 31; + } bit; + } ITM_ITCTRL; + __IM uint32_t RESERVED6[46]; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t ARCHPART : 12; /*!< Defines the architecture of the component */ + __IM uint32_t ARCHVER : 4; /*!< Defines the architecture version of the component */ + __IM uint32_t REVISION : 4; /*!< Defines the architecture revision of the component */ + __IM uint32_t PRESENT : 1; /*!< Defines that the DEVARCH register is present */ + __IM uint32_t ARCHITECT : 11; /*!< Defines the architect of the component. Bits [31:28] are the + JEP106 continuation code (JEP106 bank ID, minus 1) and + bits [27:21] are the JEP106 ID code. */ + } bit; + } ITM_DEVARCH; + __IM uint32_t RESERVED7[3]; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t MAJOR : 4; /*!< Component major type */ + __IM uint32_t SUB : 4; /*!< Component sub-type */ + uint32_t : 24; + } bit; + } ITM_DEVTYPE; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t DES_2 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t SIZE : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } ITM_PIDR4; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IOM uint32_t ITM_PIDR5 : 32; /*!< ITM_PIDR5 */ + } bit; + } ITM_PIDR5; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IOM uint32_t ITM_PIDR6 : 32; /*!< ITM_PIDR6 */ + } bit; + } ITM_PIDR6; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IOM uint32_t ITM_PIDR7 : 32; /*!< ITM_PIDR7 */ + } bit; + } ITM_PIDR7; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t PART_0 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } ITM_PIDR0; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t PART_1 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t DES_0 : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } ITM_PIDR1; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t DES_1 : 3; /*!< See CoreSight Architecture Specification */ + __IM uint32_t JEDEC : 1; /*!< See CoreSight Architecture Specification */ + __IM uint32_t REVISION : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } ITM_PIDR2; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t CMOD : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t REVAND : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } ITM_PIDR3; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t PRMBL_0 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } ITM_CIDR0; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t PRMBL_1 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t CLASS : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } ITM_CIDR1; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t PRMBL_2 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } ITM_CIDR2; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the ITM */ + + struct { + __IM uint32_t PRMBL_3 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } ITM_CIDR3; + + union { + __IOM uint32_t reg; /*!< Provides configuration and status information for the DWT unit, + and used to control features of the unit */ + + struct { + __IOM uint32_t CYCCNTENA : 1; /*!< Enables CYCCNT */ + __IOM uint32_t POSTPRESET : 4; /*!< Reload value for the POSTCNT counter */ + __IOM uint32_t POSTINIT : 4; /*!< Initial value for the POSTCNT counter */ + __IOM uint32_t CYCTAP : 1; /*!< Selects the position of the POSTCNT tap on the CYCCNT counter */ + __IOM uint32_t SYNCTAP : 2; /*!< Selects the position of the synchronization packet counter tap + on the CYCCNT counter. This determines the Synchronization + packet rate */ + __IOM uint32_t PCSAMPLENA : 1; /*!< Enables use of POSTCNT counter as a timer for Periodic PC Sample + packet generation */ + uint32_t : 3; + __IOM uint32_t EXTTRCENA : 1; /*!< Enables generation of Exception Trace packets */ + __IOM uint32_t CPIEVTENA : 1; /*!< Enables DWT_CPICNT counter */ + __IOM uint32_t EXCEVTENA : 1; /*!< Enables DWT_EXCCNT counter */ + __IOM uint32_t SLEEPEVTENA : 1; /*!< Enable DWT_SLEEPCNT counter */ + __IOM uint32_t LSUEVTENA : 1; /*!< Enables DWT_LSUCNT counter */ + __IOM uint32_t FOLDEVTENA : 1; /*!< Enables DWT_FOLDCNT counter */ + __IOM uint32_t CYCEVTENA : 1; /*!< Enables Event Counter packet generation on POSTCNT underflow */ + __IOM uint32_t CYCDISS : 1; /*!< Controls whether the cycle counter is disabled in Secure state */ + __IM uint32_t NOPRFCNT : 1; /*!< Indicates whether the implementation does not include the profiling + counters */ + __IM uint32_t NOCYCCNT : 1; /*!< Indicates whether the implementation does not include a cycle + counter */ + __IM uint32_t NOEXTTRIG : 1; /*!< Reserved, RAZ */ + __IM uint32_t NOTRCPKT : 1; /*!< Indicates whether the implementation does not support trace */ + __IM uint32_t NUMCOMP : 4; /*!< Number of DWT comparators implemented */ + } bit; + } DWT_CTRL; + + union { + __IOM uint32_t reg; /*!< Shows or sets the value of the processor cycle counter, CYCCNT */ + + struct { + __IOM uint32_t CYCCNT : 32; /*!< Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA + == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to + zero */ + } bit; + } DWT_CYCCNT; + __IM uint32_t RESERVED8; + + union { + __IOM uint32_t reg; /*!< Counts the total cycles spent in exception processing */ + + struct { + __IOM uint32_t EXCCNT : 8; /*!< Counts one on each cycle when all of the following are true: + - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction + is executed, see DWT_CPICNT. - An exception-entry or exception-exit + related operation is in progress. - Either SecureNoninvasiveDebugAllowed( + == TRUE, or NS-Req for the operation is set to Non-secure + and NoninvasiveDebugAllowed() == TRUE. */ + uint32_t : 24; + } bit; + } DWT_EXCCNT; + __IM uint32_t RESERVED9; + + union { + __IOM uint32_t reg; /*!< Increments on the additional cycles required to execute all + load or store instructions */ + + struct { + __IOM uint32_t LSUCNT : 8; /*!< Counts one on each cycle when all of the following are true: + - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction + is executed, see DWT_CPICNT. - No exception-entry or exception-exit + operation is in progress, see DWT_EXCCNT. - A load-store + operation is in progress. - Either SecureNoninvasiveDebugAllowed() + == TRUE, or NS-Req for the operation is set to Non-secure + and NoninvasiveDebugAllowed() == TRUE. */ + uint32_t : 24; + } bit; + } DWT_LSUCNT; + + union { + __IOM uint32_t reg; /*!< Increments on the additional cycles required to execute all + load or store instructions */ + + struct { + __IOM uint32_t FOLDCNT : 8; /*!< Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA + == 1 and DEMCR.TRCENA == 1. - At least two instructions + are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() + == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() + == TRUE. The counter is incremented by the number of instructions + executed, minus one */ + uint32_t : 24; + } bit; + } DWT_FOLDCNT; + __IM uint32_t RESERVED10; + + union { + __IOM uint32_t reg; /*!< Provides a reference value for use by watchpoint comparator + 0 */ + + struct { + __IOM uint32_t DWT_COMP0 : 32; /*!< DWT_COMP0 */ + } bit; + } DWT_COMP0; + __IM uint32_t RESERVED11; + + union { + __IOM uint32_t reg; /*!< Controls the operation of watchpoint comparator 0 */ + + struct { + __IOM uint32_t MATCH : 4; /*!< Controls the type of match generated by this comparator */ + __IOM uint32_t ACTION : 2; /*!< Defines the action on a match. This field is ignored and the + comparator generates no actions if it is disabled by MATCH */ + uint32_t : 4; + __IOM uint32_t DATAVSIZE : 2; /*!< Defines the size of the object being watched for by Data Value + and Data Address comparators */ + uint32_t : 12; + __IM uint32_t MATCHED : 1; /*!< Set to 1 when the comparator matches */ + uint32_t : 2; + __IM uint32_t ID : 5; /*!< Identifies the capabilities for MATCH for comparator *n */ + } bit; + } DWT_FUNCTION0; + __IM uint32_t RESERVED12; + + union { + __IOM uint32_t reg; /*!< Provides a reference value for use by watchpoint comparator + 1 */ + + struct { + __IOM uint32_t DWT_COMP1 : 32; /*!< DWT_COMP1 */ + } bit; + } DWT_COMP1; + __IM uint32_t RESERVED13; + + union { + __IOM uint32_t reg; /*!< Controls the operation of watchpoint comparator 1 */ + + struct { + __IOM uint32_t MATCH : 4; /*!< Controls the type of match generated by this comparator */ + __IOM uint32_t ACTION : 2; /*!< Defines the action on a match. This field is ignored and the + comparator generates no actions if it is disabled by MATCH */ + uint32_t : 4; + __IOM uint32_t DATAVSIZE : 2; /*!< Defines the size of the object being watched for by Data Value + and Data Address comparators */ + uint32_t : 12; + __IM uint32_t MATCHED : 1; /*!< Set to 1 when the comparator matches */ + uint32_t : 2; + __IM uint32_t ID : 5; /*!< Identifies the capabilities for MATCH for comparator *n */ + } bit; + } DWT_FUNCTION1; + __IM uint32_t RESERVED14; + + union { + __IOM uint32_t reg; /*!< Provides a reference value for use by watchpoint comparator + 2 */ + + struct { + __IOM uint32_t DWT_COMP2 : 32; /*!< DWT_COMP2 */ + } bit; + } DWT_COMP2; + __IM uint32_t RESERVED15; + + union { + __IOM uint32_t reg; /*!< Controls the operation of watchpoint comparator 2 */ + + struct { + __IOM uint32_t MATCH : 4; /*!< Controls the type of match generated by this comparator */ + __IOM uint32_t ACTION : 2; /*!< Defines the action on a match. This field is ignored and the + comparator generates no actions if it is disabled by MATCH */ + uint32_t : 4; + __IOM uint32_t DATAVSIZE : 2; /*!< Defines the size of the object being watched for by Data Value + and Data Address comparators */ + uint32_t : 12; + __IM uint32_t MATCHED : 1; /*!< Set to 1 when the comparator matches */ + uint32_t : 2; + __IM uint32_t ID : 5; /*!< Identifies the capabilities for MATCH for comparator *n */ + } bit; + } DWT_FUNCTION2; + __IM uint32_t RESERVED16; + + union { + __IOM uint32_t reg; /*!< Provides a reference value for use by watchpoint comparator + 3 */ + + struct { + __IOM uint32_t DWT_COMP3 : 32; /*!< DWT_COMP3 */ + } bit; + } DWT_COMP3; + __IM uint32_t RESERVED17; + + union { + __IOM uint32_t reg; /*!< Controls the operation of watchpoint comparator 3 */ + + struct { + __IOM uint32_t MATCH : 4; /*!< Controls the type of match generated by this comparator */ + __IOM uint32_t ACTION : 2; /*!< Defines the action on a match. This field is ignored and the + comparator generates no actions if it is disabled by MATCH */ + uint32_t : 4; + __IOM uint32_t DATAVSIZE : 2; /*!< Defines the size of the object being watched for by Data Value + and Data Address comparators */ + uint32_t : 12; + __IM uint32_t MATCHED : 1; /*!< Set to 1 when the comparator matches */ + uint32_t : 2; + __IM uint32_t ID : 5; /*!< Identifies the capabilities for MATCH for comparator *n */ + } bit; + } DWT_FUNCTION3; + __IM uint32_t RESERVED18[984]; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t ARCHPART : 12; /*!< Defines the architecture of the component */ + __IM uint32_t ARCHVER : 4; /*!< Defines the architecture version of the component */ + __IM uint32_t REVISION : 4; /*!< Defines the architecture revision of the component */ + __IM uint32_t PRESENT : 1; /*!< Defines that the DEVARCH register is present */ + __IM uint32_t ARCHITECT : 11; /*!< Defines the architect of the component. Bits [31:28] are the + JEP106 continuation code (JEP106 bank ID, minus 1) and + bits [27:21] are the JEP106 ID code. */ + } bit; + } DWT_DEVARCH; + __IM uint32_t RESERVED19[3]; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t MAJOR : 4; /*!< Component major type */ + __IM uint32_t SUB : 4; /*!< Component sub-type */ + uint32_t : 24; + } bit; + } DWT_DEVTYPE; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t DES_2 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t SIZE : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DWT_PIDR4; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IOM uint32_t DWT_PIDR5 : 32; /*!< DWT_PIDR5 */ + } bit; + } DWT_PIDR5; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IOM uint32_t DWT_PIDR6 : 32; /*!< DWT_PIDR6 */ + } bit; + } DWT_PIDR6; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IOM uint32_t DWT_PIDR7 : 32; /*!< DWT_PIDR7 */ + } bit; + } DWT_PIDR7; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t PART_0 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DWT_PIDR0; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t PART_1 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t DES_0 : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DWT_PIDR1; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t DES_1 : 3; /*!< See CoreSight Architecture Specification */ + __IM uint32_t JEDEC : 1; /*!< See CoreSight Architecture Specification */ + __IM uint32_t REVISION : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DWT_PIDR2; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t CMOD : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t REVAND : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DWT_PIDR3; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t PRMBL_0 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DWT_CIDR0; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t PRMBL_1 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t CLASS : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DWT_CIDR1; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t PRMBL_2 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DWT_CIDR2; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the DWT */ + + struct { + __IM uint32_t PRMBL_3 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DWT_CIDR3; + + union { + __IOM uint32_t reg; /*!< Provides FPB implementation information, and the global enable + for the FPB unit */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< Enables the FPB */ + __IOM uint32_t KEY : 1; /*!< Writes to the FP_CTRL are ignored unless KEY is concurrently + written to one */ + uint32_t : 2; + __IM uint32_t NUM_CODE_7_4_ : 4; /*!< Indicates the number of implemented instruction address comparators. + Zero indicates no Instruction Address comparators are implemented. + The Instruction Address comparators are numbered from 0 + to NUM_CODE - 1 */ + __IM uint32_t NUM_LIT : 4; /*!< Indicates the number of implemented literal address comparators. + The Literal Address comparators are numbered from NUM_CODE + to NUM_CODE + NUM_LIT - 1 */ + __IM uint32_t NUM_CODE_14_12_ : 3; /*!< Indicates the number of implemented instruction address comparators. + Zero indicates no Instruction Address comparators are implemented. + The Instruction Address comparators are numbered from 0 + to NUM_CODE - 1 */ + uint32_t : 13; + __IM uint32_t REV : 4; /*!< Flash Patch and Breakpoint Unit architecture revision */ + } bit; + } FP_CTRL; + + union { + __IOM uint32_t reg; /*!< Indicates whether the implementation supports Flash Patch remap + and, if it does, holds the target address for remap */ + + struct { + uint32_t : 5; + __IM uint32_t REMAP : 24; /*!< Holds the bits[28:5] of the Flash Patch remap address */ + __IM uint32_t RMPSPT : 1; /*!< Indicates whether the FPB unit supports the Flash Patch remap + function */ + uint32_t : 2; + } bit; + } FP_REMAP; + + union { + __IOM uint32_t reg; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + + struct { + __IOM uint32_t BE : 1; /*!< Selects between flashpatch and breakpoint functionality */ + uint32_t : 31; + } bit; + } FP_COMP0; + + union { + __IOM uint32_t reg; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + + struct { + __IOM uint32_t BE : 1; /*!< Selects between flashpatch and breakpoint functionality */ + uint32_t : 31; + } bit; + } FP_COMP1; + + union { + __IOM uint32_t reg; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + + struct { + __IOM uint32_t BE : 1; /*!< Selects between flashpatch and breakpoint functionality */ + uint32_t : 31; + } bit; + } FP_COMP2; + + union { + __IOM uint32_t reg; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + + struct { + __IOM uint32_t BE : 1; /*!< Selects between flashpatch and breakpoint functionality */ + uint32_t : 31; + } bit; + } FP_COMP3; + + union { + __IOM uint32_t reg; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + + struct { + __IOM uint32_t BE : 1; /*!< Selects between flashpatch and breakpoint functionality */ + uint32_t : 31; + } bit; + } FP_COMP4; + + union { + __IOM uint32_t reg; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + + struct { + __IOM uint32_t BE : 1; /*!< Selects between flashpatch and breakpoint functionality */ + uint32_t : 31; + } bit; + } FP_COMP5; + + union { + __IOM uint32_t reg; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + + struct { + __IOM uint32_t BE : 1; /*!< Selects between flashpatch and breakpoint functionality */ + uint32_t : 31; + } bit; + } FP_COMP6; + + union { + __IOM uint32_t reg; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + + struct { + __IOM uint32_t BE : 1; /*!< Selects between flashpatch and breakpoint functionality */ + uint32_t : 31; + } bit; + } FP_COMP7; + __IM uint32_t RESERVED20[997]; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FPB */ + + struct { + __IM uint32_t ARCHPART : 12; /*!< Defines the architecture of the component */ + __IM uint32_t ARCHVER : 4; /*!< Defines the architecture version of the component */ + __IM uint32_t REVISION : 4; /*!< Defines the architecture revision of the component */ + __IM uint32_t PRESENT : 1; /*!< Defines that the DEVARCH register is present */ + __IM uint32_t ARCHITECT : 11; /*!< Defines the architect of the component. Bits [31:28] are the + JEP106 continuation code (JEP106 bank ID, minus 1) and + bits [27:21] are the JEP106 ID code. */ + } bit; + } FP_DEVARCH; + __IM uint32_t RESERVED21[3]; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FPB */ + + struct { + __IM uint32_t MAJOR : 4; /*!< Component major type */ + __IM uint32_t SUB : 4; /*!< Component sub-type */ + uint32_t : 24; + } bit; + } FP_DEVTYPE; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IM uint32_t DES_2 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t SIZE : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } FP_PIDR4; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IOM uint32_t FP_PIDR5 : 32; /*!< FP_PIDR5 */ + } bit; + } FP_PIDR5; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IOM uint32_t FP_PIDR6 : 32; /*!< FP_PIDR6 */ + } bit; + } FP_PIDR6; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IOM uint32_t FP_PIDR7 : 32; /*!< FP_PIDR7 */ + } bit; + } FP_PIDR7; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IM uint32_t PART_0 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } FP_PIDR0; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IM uint32_t PART_1 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t DES_0 : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } FP_PIDR1; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IM uint32_t DES_1 : 3; /*!< See CoreSight Architecture Specification */ + __IM uint32_t JEDEC : 1; /*!< See CoreSight Architecture Specification */ + __IM uint32_t REVISION : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } FP_PIDR2; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IM uint32_t CMOD : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t REVAND : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } FP_PIDR3; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IM uint32_t PRMBL_0 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } FP_CIDR0; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IM uint32_t PRMBL_1 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t CLASS : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } FP_CIDR1; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IM uint32_t PRMBL_2 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } FP_CIDR2; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the FP */ + + struct { + __IM uint32_t PRMBL_3 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } FP_CIDR3; + __IM uint32_t RESERVED22[11265]; + + union { + __IOM uint32_t reg; /*!< Provides information about the interrupt controller */ + + struct { + __IM uint32_t INTLINESNUM : 4; /*!< Indicates the number of the highest implemented register in + each of the NVIC control register sets, or in the case + of NVIC_IPR*n, 4×INTLINESNUM */ + uint32_t : 28; + } bit; + } ICTR; + + union { + __IOM uint32_t reg; /*!< Provides IMPLEMENTATION DEFINED configuration and control options */ + + struct { + __IOM uint32_t DISMCYCINT : 1; /*!< Disable dual-issue. */ + uint32_t : 1; + __IOM uint32_t DISFOLD : 1; /*!< Disable dual-issue. */ + uint32_t : 6; + __IOM uint32_t DISOOFP : 1; /*!< Disable out-of-order FP instruction completion */ + __IOM uint32_t FPEXCODIS : 1; /*!< Disable FPU exception outputs */ + uint32_t : 1; + __IOM uint32_t DISITMATBFLUSH : 1; /*!< Disable ATB Flush */ + uint32_t : 16; + __IOM uint32_t EXTEXCLALL : 1; /*!< External Exclusives Allowed with no MPU */ + uint32_t : 2; + } bit; + } ACTLR; + __IM uint32_t RESERVED23; + + union { + __IOM uint32_t reg; /*!< Use the SysTick Control and Status Register to enable the SysTick + features. */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled. */ + __IOM uint32_t TICKINT : 1; /*!< Enables SysTick exception request: 0 = Counting down to zero + does not assert the SysTick exception request. 1 = Counting + down to zero to asserts the SysTick exception request. */ + __IOM uint32_t CLKSOURCE : 1; /*!< SysTick clock source. Always reads as one if SYST_CALIB reports + NOREF. Selects the SysTick timer clock source: 0 = External + reference clock. 1 = Processor clock. */ + uint32_t : 13; + __IM uint32_t COUNTFLAG : 1; /*!< Returns 1 if timer counted to 0 since last time this was read. + Clears on read by application or debugger. */ + uint32_t : 15; + } bit; + } SYST_CSR; + + union { + __IOM uint32_t reg; /*!< Use the SysTick Reload Value Register to specify the start value + to load into the current value register when the counter + reaches 0. It can be any value between 0 and 0x00FFFFFF. + A start value of 0 is possible, but has no effect because + the SysTick interrupt and COUNTFLAG are activated when + counting from 1 to 0. The reset value of this register + is UNKNOWN. To generate a multi-shot timer with a period + of N processor clock cycles, use a RELOAD value of N-1. + For example, if the SysTick interrupt is required every + 100 clock pulses, set RELOAD to 99. */ + + struct { + __IOM uint32_t RELOAD : 24; /*!< Value to load into the SysTick Current Value Register when the + counter reaches 0. */ + uint32_t : 8; + } bit; + } SYST_RVR; + + union { + __IOM uint32_t reg; /*!< Use the SysTick Current Value Register to find the current value + in the register. The reset value of this register is UNKNOWN. */ + + struct { + __IOM uint32_t CURRENT : 24; /*!< Reads return the current value of the SysTick counter. This + register is write-clear. Writing to it with any value clears + the register to 0. Clearing this register also clears the + COUNTFLAG bit of the SysTick Control and Status Register. */ + uint32_t : 8; + } bit; + } SYST_CVR; + + union { + __IOM uint32_t reg; /*!< Use the SysTick Calibration Value Register to enable software + to scale to any required speed using divide and multiply. */ + + struct { + __IM uint32_t TENMS : 24; /*!< An optional Reload value to be used for 10ms (100Hz) timing, + subject to system clock skew errors. If the value reads + as 0, the calibration value is not known. */ + uint32_t : 6; + __IM uint32_t SKEW : 1; /*!< If reads as 1, the calibration value for 10ms is inexact (due + to clock frequency). */ + __IM uint32_t NOREF : 1; /*!< If reads as 1, the Reference clock is not provided - the CLKSOURCE + bit of the SysTick Control and Status register will be + forced to 1 and cannot be cleared to 0. */ + } bit; + } SYST_CALIB; + __IM uint32_t RESERVED24[56]; + + union { + __IOM uint32_t reg; /*!< Enables or reads the enabled state of each group of 32 interrupts */ + + struct { + __IOM uint32_t SETENA : 32; /*!< For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + + m is enabled */ + } bit; + } NVIC_ISER0; + + union { + __IOM uint32_t reg; /*!< Enables or reads the enabled state of each group of 32 interrupts */ + + struct { + __IOM uint32_t SETENA : 32; /*!< For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + + m is enabled */ + } bit; + } NVIC_ISER1; + __IM uint32_t RESERVED25[30]; + + union { + __IOM uint32_t reg; /*!< Clears or reads the enabled state of each group of 32 interrupts */ + + struct { + __IOM uint32_t CLRENA : 32; /*!< For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + + m is enabled */ + } bit; + } NVIC_ICER0; + + union { + __IOM uint32_t reg; /*!< Clears or reads the enabled state of each group of 32 interrupts */ + + struct { + __IOM uint32_t CLRENA : 32; /*!< For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + + m is enabled */ + } bit; + } NVIC_ICER1; + __IM uint32_t RESERVED26[30]; + + union { + __IOM uint32_t reg; /*!< Enables or reads the pending state of each group of 32 interrupts */ + + struct { + __IOM uint32_t SETPEND : 32; /*!< For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + + m is pending */ + } bit; + } NVIC_ISPR0; + + union { + __IOM uint32_t reg; /*!< Enables or reads the pending state of each group of 32 interrupts */ + + struct { + __IOM uint32_t SETPEND : 32; /*!< For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + + m is pending */ + } bit; + } NVIC_ISPR1; + __IM uint32_t RESERVED27[30]; + + union { + __IOM uint32_t reg; /*!< Clears or reads the pending state of each group of 32 interrupts */ + + struct { + __IOM uint32_t CLRPEND : 32; /*!< For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + + m is pending */ + } bit; + } NVIC_ICPR0; + + union { + __IOM uint32_t reg; /*!< Clears or reads the pending state of each group of 32 interrupts */ + + struct { + __IOM uint32_t CLRPEND : 32; /*!< For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + + m is pending */ + } bit; + } NVIC_ICPR1; + __IM uint32_t RESERVED28[30]; + + union { + __IOM uint32_t reg; /*!< For each group of 32 interrupts, shows the active state of each + interrupt */ + + struct { + __IOM uint32_t ACTIVE : 32; /*!< For ACTIVE[m] in NVIC_IABR*n, indicates the active state for + interrupt 32*n+m */ + } bit; + } NVIC_IABR0; + + union { + __IOM uint32_t reg; /*!< For each group of 32 interrupts, shows the active state of each + interrupt */ + + struct { + __IOM uint32_t ACTIVE : 32; /*!< For ACTIVE[m] in NVIC_IABR*n, indicates the active state for + interrupt 32*n+m */ + } bit; + } NVIC_IABR1; + __IM uint32_t RESERVED29[30]; + + union { + __IOM uint32_t reg; /*!< For each group of 32 interrupts, determines whether each interrupt + targets Non-secure or Secure state */ + + struct { + __IOM uint32_t ITNS : 32; /*!< For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state + for interrupt 32*n+m */ + } bit; + } NVIC_ITNS0; + + union { + __IOM uint32_t reg; /*!< For each group of 32 interrupts, determines whether each interrupt + targets Non-secure or Secure state */ + + struct { + __IOM uint32_t ITNS : 32; /*!< For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state + for interrupt 32*n+m */ + } bit; + } NVIC_ITNS1; + __IM uint32_t RESERVED30[30]; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR0; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR1; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR2; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR3; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR4; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR5; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR6; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR7; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR8; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR9; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR10; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR11; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR12; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR13; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR14; + + union { + __IOM uint32_t reg; /*!< Sets or reads interrupt priorities */ + + struct { + uint32_t : 4; + __IOM uint32_t PRI_N0 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+0, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N1 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+1, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N2 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+2, + or RES0 if the PE does not implement this interrupt */ + uint32_t : 4; + __IOM uint32_t PRI_N3 : 4; /*!< For register NVIC_IPRn, the priority of interrupt number 4*n+3, + or RES0 if the PE does not implement this interrupt */ + } bit; + } NVIC_IPR15; + __IM uint32_t RESERVED31[560]; + + union { + __IOM uint32_t reg; /*!< Provides identification information for the PE, including an + implementer code for the device and a device ID number */ + + struct { + __IM uint32_t REVISION : 4; /*!< IMPLEMENTATION DEFINED revision number for the device */ + __IM uint32_t PARTNO : 12; /*!< IMPLEMENTATION DEFINED primary part number for the device */ + __IM uint32_t ARCHITECTURE : 4; /*!< Defines the Architecture implemented by the PE */ + __IM uint32_t VARIANT : 4; /*!< IMPLEMENTATION DEFINED variant number. Typically, this field + is used to distinguish between different product variants, + or major revisions of a product */ + __IM uint32_t IMPLEMENTER : 8; /*!< This field must hold an implementer code that has been assigned + by ARM */ + } bit; + } CPUID; + + union { + __IOM uint32_t reg; /*!< Controls and provides status information for NMI, PendSV, SysTick + and interrupts */ + + struct { + __IM uint32_t VECTACTIVE : 9; /*!< The exception number of the current executing exception */ + uint32_t : 2; + __IM uint32_t RETTOBASE : 1; /*!< In Handler mode, indicates whether there is more than one active + exception */ + __IM uint32_t VECTPENDING : 9; /*!< The exception number of the highest priority pending and enabled + interrupt */ + uint32_t : 1; + __IM uint32_t ISRPENDING : 1; /*!< Indicates whether an external interrupt, generated by the NVIC, + is pending */ + __IM uint32_t ISRPREEMPT : 1; /*!< Indicates whether a pending exception will be serviced on exit + from debug halt state */ + __IOM uint32_t STTNS : 1; /*!< Controls whether in a single SysTick implementation, the SysTick + is Secure or Non-secure */ + __IOM uint32_t PENDSTCLR : 1; /*!< Allows the SysTick exception pend state to be cleared `FTSSS */ + __IM uint32_t PENDSTSET : 1; /*!< Indicates whether the SysTick `FTSSS exception is pending */ + __IOM uint32_t PENDSVCLR : 1; /*!< Allows the PendSV exception pend state to be cleared `FTSSS */ + __IM uint32_t PENDSVSET : 1; /*!< Indicates whether the PendSV `FTSSS exception is pending */ + uint32_t : 1; + __IOM uint32_t PENDNMICLR : 1; /*!< Allows the NMI exception pend state to be cleared */ + __IM uint32_t PENDNMISET : 1; /*!< Indicates whether the NMI exception is pending */ + } bit; + } ICSR; + + union { + __IOM uint32_t reg; /*!< The VTOR indicates the offset of the vector table base address + from memory address 0x00000000. */ + + struct { + uint32_t : 7; + __IOM uint32_t TBLOFF : 25; /*!< Vector table base offset field. It contains bits[31:7] of the + offset of the table base from the bottom of the memory + map. */ + } bit; + } VTOR; + + union { + __IOM uint32_t reg; /*!< Use the Application Interrupt and Reset Control Register to: + determine data endianness, clear all active state information + from debug halt mode, request a system reset. */ + + struct { + uint32_t : 1; + __IOM uint32_t VECTCLRACTIVE : 1; /*!< Clears all active state information for fixed and configurable + exceptions. This bit: is self-clearing, can only be set + by the DAP when the core is halted. When set: clears all + active exception status of the processor, forces a return + to Thread mode, forces an IPSR of 0. A debugger must re-initialize + the stack. */ + __IOM uint32_t SYSRESETREQ : 1; /*!< Writing 1 to this bit causes the SYSRESETREQ signal to the outer + system to be asserted to request a reset. The intention + is to force a large system reset of all major components + except for debug. The C_HALT bit in the DHCSR is cleared + as a result of the system reset requested. The debugger + does not lose contact with the device. */ + __IOM uint32_t SYSRESETREQS : 1; /*!< System reset request, Secure state only. 0 SYSRESETREQ functionality + is available to both Security states. 1 SYSRESETREQ functionality + is only available to Secure state. */ + uint32_t : 4; + __IOM uint32_t PRIGROUP : 3; /*!< Interrupt priority grouping field. This field determines the + split of group priority from subpriority. See https://developer.arm.com/d + cumentation/100235/0004/the-cortex-m33-peripherals/system-control-block/a + plication-interrupt-and-reset-control-register?lang=en */ + uint32_t : 2; + __IOM uint32_t BFHFNMINS : 1; /*!< BusFault, HardFault, and NMI Non-secure enable. 0 BusFault, + HardFault, and NMI are Secure. 1 BusFault and NMI are Non-secure + and exceptions can target Non-secure HardFault. */ + __IOM uint32_t PRIS : 1; /*!< Prioritize Secure exceptions. The value of this bit defines + whether Secure exception priority boosting is enabled. + 0 Priority ranges of Secure and Non-secure exceptions are + identical. 1 Non-secure exceptions are de-prioritized. */ + __IM uint32_t ENDIANESS : 1; /*!< Data endianness implemented: 0 = Little-endian. */ + __IOM uint32_t VECTKEY : 16; /*!< Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, + otherwise the write is ignored. */ + } bit; + } AIRCR; + + union { + __IOM uint32_t reg; /*!< System Control Register. Use the System Control Register for + power-management functions: signal to the system when the + processor can enter a low power state, control how the + processor enters and exits low power states. */ + + struct { + uint32_t : 1; + __IOM uint32_t SLEEPONEXIT : 1; /*!< Indicates sleep-on-exit when returning from Handler mode to + Thread mode: 0 = Do not sleep when returning to Thread + mode. 1 = Enter sleep, or deep sleep, on return from an + ISR to Thread mode. Setting this bit to 1 enables an interrupt + driven application to avoid returning to an empty main + application. */ + __IOM uint32_t SLEEPDEEP : 1; /*!< Controls whether the processor uses sleep or deep sleep as its + low power mode: 0 = Sleep. 1 = Deep sleep. */ + __IOM uint32_t SLEEPDEEPS : 1; /*!< 0 SLEEPDEEP is available to both security states 1 SLEEPDEEP + is only available to Secure state */ + __IOM uint32_t SEVONPEND : 1; /*!< Send Event on Pending bit: 0 = Only enabled interrupts or events + can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled + interrupts, can wakeup the processor. When an event or + interrupt becomes pending, the event signal wakes up the + processor from WFE. If the processor is not waiting for + an event, the event is registered and affects the next + WFE. The processor also wakes up on execution of an SEV + instruction or an external event. */ + uint32_t : 27; + } bit; + } SCR; + + union { + __IOM uint32_t reg; /*!< Sets or returns configuration and control data */ + + struct { + __IM uint32_t RES1_1 : 1; /*!< Reserved, RES1 */ + __IOM uint32_t USERSETMPEND : 1; /*!< Determines whether unprivileged accesses are permitted to pend + interrupts via the STIR */ + uint32_t : 1; + __IOM uint32_t UNALIGN_TRP : 1; /*!< Controls the trapping of unaligned word or halfword accesses */ + __IOM uint32_t DIV_0_TRP : 1; /*!< Controls the generation of a DIVBYZERO UsageFault when attempting + to perform integer division by zero */ + uint32_t : 3; + __IOM uint32_t BFHFNMIGN : 1; /*!< Determines the effect of precise BusFaults on handlers running + at a requested priority less than 0 */ + __IM uint32_t RES1 : 1; /*!< Reserved, RES1 */ + __IOM uint32_t STKOFHFNMIGN : 1; /*!< Controls the effect of a stack limit violation while executing + at a requested priority less than 0 */ + uint32_t : 5; + __IM uint32_t DC : 1; /*!< Enables data caching of all data accesses to Normal memory `FTSSS */ + __IM uint32_t IC : 1; /*!< This is a global enable bit for instruction caches in the selected + Security state */ + __IM uint32_t BP : 1; /*!< Enables program flow prediction `FTSSS */ + uint32_t : 13; + } bit; + } CCR; + + union { + __IOM uint32_t reg; /*!< Sets or returns priority for system handlers 4 - 7 */ + + struct { + uint32_t : 5; + __IOM uint32_t PRI_4_3 : 3; /*!< Priority of system handler 4, SecureFault */ + uint32_t : 5; + __IOM uint32_t PRI_5_3 : 3; /*!< Priority of system handler 5, SecureFault */ + uint32_t : 5; + __IOM uint32_t PRI_6_3 : 3; /*!< Priority of system handler 6, SecureFault */ + uint32_t : 5; + __IOM uint32_t PRI_7_3 : 3; /*!< Priority of system handler 7, SecureFault */ + } bit; + } SHPR1; + + union { + __IOM uint32_t reg; /*!< Sets or returns priority for system handlers 8 - 11 */ + + struct { + __IM uint32_t PRI_8 : 8; /*!< Reserved, RES0 */ + __IM uint32_t PRI_9 : 8; /*!< Reserved, RES0 */ + __IM uint32_t PRI_10 : 8; /*!< Reserved, RES0 */ + uint32_t : 5; + __IOM uint32_t PRI_11_3 : 3; /*!< Priority of system handler 11, SecureFault */ + } bit; + } SHPR2; + + union { + __IOM uint32_t reg; /*!< Sets or returns priority for system handlers 12 - 15 */ + + struct { + uint32_t : 5; + __IOM uint32_t PRI_12_3 : 3; /*!< Priority of system handler 12, SecureFault */ + __IM uint32_t PRI_13 : 8; /*!< Reserved, RES0 */ + uint32_t : 5; + __IOM uint32_t PRI_14_3 : 3; /*!< Priority of system handler 14, SecureFault */ + uint32_t : 5; + __IOM uint32_t PRI_15_3 : 3; /*!< Priority of system handler 15, SecureFault */ + } bit; + } SHPR3; + + union { + __IOM uint32_t reg; /*!< Provides access to the active and pending status of system exceptions */ + + struct { + __IOM uint32_t MEMFAULTACT : 1; /*!< `IAAMO the active state of the MemManage exception `FTSSS */ + __IOM uint32_t BUSFAULTACT : 1; /*!< `IAAMO the active state of the BusFault exception */ + __IOM uint32_t HARDFAULTACT : 1; /*!< Indicates and allows limited modification of the active state + of the HardFault exception `FTSSS */ + __IOM uint32_t USGFAULTACT : 1; /*!< `IAAMO the active state of the UsageFault exception `FTSSS */ + __IOM uint32_t SECUREFAULTACT : 1; /*!< `IAAMO the active state of the SecureFault exception */ + __IOM uint32_t NMIACT : 1; /*!< `IAAMO the active state of the NMI exception */ + uint32_t : 1; + __IOM uint32_t SVCALLACT : 1; /*!< `IAAMO the active state of the SVCall exception `FTSSS */ + __IOM uint32_t MONITORACT : 1; /*!< `IAAMO the active state of the DebugMonitor exception */ + uint32_t : 1; + __IOM uint32_t PENDSVACT : 1; /*!< `IAAMO the active state of the PendSV exception `FTSSS */ + __IOM uint32_t SYSTICKACT : 1; /*!< `IAAMO the active state of the SysTick exception `FTSSS */ + __IOM uint32_t USGFAULTPENDED : 1; /*!< The UsageFault exception is banked between Security states, + `IAAMO the pending state of the UsageFault exception `FTSSS */ + __IOM uint32_t MEMFAULTPENDED : 1; /*!< `IAAMO the pending state of the MemManage exception `FTSSS */ + __IOM uint32_t BUSFAULTPENDED : 1; /*!< `IAAMO the pending state of the BusFault exception */ + __IOM uint32_t SVCALLPENDED : 1; /*!< `IAAMO the pending state of the SVCall exception `FTSSS */ + __IOM uint32_t MEMFAULTENA : 1; /*!< `DW the MemManage exception is enabled `FTSSS */ + __IOM uint32_t BUSFAULTENA : 1; /*!< `DW the BusFault exception is enabled */ + __IOM uint32_t USGFAULTENA : 1; /*!< `DW the UsageFault exception is enabled `FTSSS */ + __IOM uint32_t SECUREFAULTENA : 1; /*!< `DW the SecureFault exception is enabled */ + __IOM uint32_t SECUREFAULTPENDED : 1; /*!< `IAAMO the pending state of the SecureFault exception */ + __IOM uint32_t HARDFAULTPENDED : 1; /*!< `IAAMO the pending state of the HardFault exception `CTTSSS */ + uint32_t : 10; + } bit; + } SHCSR; + + union { + __IOM uint32_t reg; /*!< Contains the three Configurable Fault Status Registers. 31:16 + UFSR: Provides information on UsageFault exceptions 15:8 + BFSR: Provides information on BusFault exceptions 7:0 MMFSR: + Provides information on MemManage exceptions */ + + struct { + __IOM uint32_t MMFSR : 8; /*!< Provides information on MemManage exceptions */ + __IOM uint32_t BFSR_IBUSERR : 1; /*!< Records whether a BusFault on an instruction prefetch has occurred */ + __IOM uint32_t BFSR_PRECISERR : 1; /*!< Records whether a precise data access error has occurred */ + __IOM uint32_t BFSR_IMPRECISERR : 1; /*!< Records whether an imprecise data access error has occurred */ + __IOM uint32_t BFSR_UNSTKERR : 1; /*!< Records whether a derived BusFault occurred during exception + return unstacking */ + __IOM uint32_t BFSR_STKERR : 1; /*!< Records whether a derived BusFault occurred during exception + entry stacking */ + __IOM uint32_t BFSR_LSPERR : 1; /*!< Records whether a BusFault occurred during FP lazy state preservation */ + uint32_t : 1; + __IOM uint32_t BFSR_BFARVALID : 1; /*!< Indicates validity of the contents of the BFAR register */ + __IOM uint32_t UFSR_UNDEFINSTR : 1; /*!< Sticky flag indicating whether an undefined instruction error + has occurred */ + __IOM uint32_t UFSR_INVSTATE : 1; /*!< Sticky flag indicating whether an EPSR.T or EPSR.IT validity + error has occurred */ + __IOM uint32_t UFSR_INVPC : 1; /*!< Sticky flag indicating whether an integrity check error has + occurred */ + __IOM uint32_t UFSR_NOCP : 1; /*!< Sticky flag indicating whether a coprocessor disabled or not + present error has occurred */ + __IOM uint32_t UFSR_STKOF : 1; /*!< Sticky flag indicating whether a stack overflow error has occurred */ + uint32_t : 3; + __IOM uint32_t UFSR_UNALIGNED : 1; /*!< Sticky flag indicating whether an unaligned access error has + occurred */ + __IOM uint32_t UFSR_DIVBYZERO : 1; /*!< Sticky flag indicating whether an integer division by zero error + has occurred */ + uint32_t : 6; + } bit; + } CFSR; + + union { + __IOM uint32_t reg; /*!< Shows the cause of any HardFaults */ + + struct { + uint32_t : 1; + __IOM uint32_t VECTTBL : 1; /*!< Indicates when a fault has occurred because of a vector table + read error on exception processing */ + uint32_t : 28; + __IOM uint32_t FORCED : 1; /*!< Indicates that a fault with configurable priority has been escalated + to a HardFault exception, because it could not be made + active, because of priority, or because it was disabled */ + __IOM uint32_t DEBUGEVT : 1; /*!< Indicates when a Debug event has occurred */ + } bit; + } HFSR; + + union { + __IOM uint32_t reg; /*!< Shows which debug event occurred */ + + struct { + __IOM uint32_t HALTED : 1; /*!< Sticky flag indicating that a Halt request debug event or Step + debug event has occurred */ + __IOM uint32_t BKPT : 1; /*!< Sticky flag indicating whether a Breakpoint debug event has + occurred */ + __IOM uint32_t DWTTRAP : 1; /*!< Sticky flag indicating whether a Watchpoint debug event has + occurred */ + __IOM uint32_t VCATCH : 1; /*!< Sticky flag indicating whether a Vector catch debug event has + occurred */ + __IOM uint32_t EXTERNAL : 1; /*!< Sticky flag indicating whether an External debug request debug + event has occurred */ + uint32_t : 27; + } bit; + } DFSR; + + union { + __IOM uint32_t reg; /*!< Shows the address of the memory location that caused an MPU + fault */ + + struct { + __IOM uint32_t ADDRESS : 32; /*!< This register is updated with the address of a location that + produced a MemManage fault. The MMFSR shows the cause of + the fault, and whether this field is valid. This field + is valid only when MMFSR.MMARVALID is set, otherwise it + is UNKNOWN */ + } bit; + } MMFAR; + + union { + __IOM uint32_t reg; /*!< Shows the address associated with a precise data access BusFault */ + + struct { + __IOM uint32_t ADDRESS : 32; /*!< This register is updated with the address of a location that + produced a BusFault. The BFSR shows the reason for the + fault. This field is valid only when BFSR.BFARVALID is + set, otherwise it is UNKNOWN */ + } bit; + } BFAR; + __IM uint32_t RESERVED32; + + union { + __IOM uint32_t reg; /*!< Gives top-level information about the instruction set supported + by the PE */ + + struct { + __IM uint32_t STATE0 : 4; /*!< A32 instruction set support */ + __IM uint32_t STATE1 : 4; /*!< T32 instruction set support */ + uint32_t : 24; + } bit; + } ID_PFR0; + + union { + __IOM uint32_t reg; /*!< Gives information about the programmers' model and Extensions + support */ + + struct { + uint32_t : 4; + __IM uint32_t SECURITY : 4; /*!< Identifies whether the Security Extension is implemented */ + __IM uint32_t MPROGMOD : 4; /*!< Identifies support for the M-Profile programmers' model support */ + uint32_t : 20; + } bit; + } ID_PFR1; + + union { + __IOM uint32_t reg; /*!< Provides top level information about the debug system */ + + struct { + uint32_t : 20; + __IM uint32_t MPROFDBG : 4; /*!< Indicates the supported M-profile debug architecture */ + uint32_t : 8; + } bit; + } ID_DFR0; + + union { + __IOM uint32_t reg; /*!< Provides information about the IMPLEMENTATION DEFINED features + of the PE */ + + struct { + __IM uint32_t IMPDEF0 : 4; /*!< IMPLEMENTATION DEFINED meaning */ + __IM uint32_t IMPDEF1 : 4; /*!< IMPLEMENTATION DEFINED meaning */ + __IM uint32_t IMPDEF2 : 4; /*!< IMPLEMENTATION DEFINED meaning */ + __IM uint32_t IMPDEF3 : 4; /*!< IMPLEMENTATION DEFINED meaning */ + uint32_t : 16; + } bit; + } ID_AFR0; + + union { + __IOM uint32_t reg; /*!< Provides information about the implemented memory model and + memory management support */ + + struct { + uint32_t : 4; + __IM uint32_t PMSA : 4; /*!< Indicates support for the protected memory system architecture + (PMSA) */ + __IM uint32_t OUTERSHR : 4; /*!< Indicates the outermost shareability domain implemented */ + __IM uint32_t SHARELVL : 4; /*!< Indicates the number of shareability levels implemented */ + __IM uint32_t TCM : 4; /*!< Indicates support for tightly coupled memories (TCMs) */ + __IM uint32_t AUXREG : 4; /*!< Indicates support for Auxiliary Control Registers */ + uint32_t : 8; + } bit; + } ID_MMFR0; + + union { + __IOM uint32_t reg; /*!< Provides information about the implemented memory model and + memory management support */ + + struct { + __IOM uint32_t ID_MMFR1 : 32; /*!< ID_MMFR1 */ + } bit; + } ID_MMFR1; + + union { + __IOM uint32_t reg; /*!< Provides information about the implemented memory model and + memory management support */ + + struct { + uint32_t : 24; + __IM uint32_t WFISTALL : 4; /*!< Indicates the support for Wait For Interrupt (WFI) stalling */ + uint32_t : 4; + } bit; + } ID_MMFR2; + + union { + __IOM uint32_t reg; /*!< Provides information about the implemented memory model and + memory management support */ + + struct { + __IM uint32_t CMAINTVA : 4; /*!< Indicates the supported cache maintenance operations by address */ + __IM uint32_t CMAINTSW : 4; /*!< Indicates the supported cache maintenance operations by set/way */ + __IM uint32_t BPMAINT : 4; /*!< Indicates the supported branch predictor maintenance */ + uint32_t : 20; + } bit; + } ID_MMFR3; + + union { + __IOM uint32_t reg; /*!< Provides information about the instruction set implemented by + the PE */ + + struct { + uint32_t : 4; + __IM uint32_t BITCOUNT : 4; /*!< Indicates the supported bit count instructions */ + __IM uint32_t BITFIELD : 4; /*!< Indicates the supported bit field instructions */ + __IM uint32_t CMPBRANCH : 4; /*!< Indicates the supported combined Compare and Branch instructions */ + __IM uint32_t COPROC : 4; /*!< Indicates the supported Coprocessor instructions */ + __IM uint32_t DEBUG : 4; /*!< Indicates the implemented Debug instructions */ + __IM uint32_t DIVIDE : 4; /*!< Indicates the supported Divide instructions */ + uint32_t : 4; + } bit; + } ID_ISAR0; + + union { + __IOM uint32_t reg; /*!< Provides information about the instruction set implemented by + the PE */ + + struct { + uint32_t : 12; + __IM uint32_t EXTEND : 4; /*!< Indicates the implemented Extend instructions */ + __IM uint32_t IFTHEN : 4; /*!< Indicates the implemented If-Then instructions */ + __IM uint32_t IMMEDIATE : 4; /*!< Indicates the implemented for data-processing instructions with + long immediates */ + __IM uint32_t INTERWORK : 4; /*!< Indicates the implemented Interworking instructions */ + uint32_t : 4; + } bit; + } ID_ISAR1; + + union { + __IOM uint32_t reg; /*!< Provides information about the instruction set implemented by + the PE */ + + struct { + __IM uint32_t LOADSTORE : 4; /*!< Indicates the implemented additional load/store instructions */ + __IM uint32_t MEMHINT : 4; /*!< Indicates the implemented Memory Hint instructions */ + __IM uint32_t MULTIACCESSINT : 4; /*!< Indicates the support for interruptible multi-access instructions */ + __IM uint32_t MULT : 4; /*!< Indicates the implemented additional Multiply instructions */ + __IM uint32_t MULTS : 4; /*!< Indicates the implemented advanced signed Multiply instructions */ + __IM uint32_t MULTU : 4; /*!< Indicates the implemented advanced unsigned Multiply instructions */ + uint32_t : 4; + __IM uint32_t REVERSAL : 4; /*!< Indicates the implemented Reversal instructions */ + } bit; + } ID_ISAR2; + + union { + __IOM uint32_t reg; /*!< Provides information about the instruction set implemented by + the PE */ + + struct { + __IM uint32_t SATURATE : 4; /*!< Indicates the implemented saturating instructions */ + __IM uint32_t SIMD : 4; /*!< Indicates the implemented SIMD instructions */ + __IM uint32_t SVC : 4; /*!< Indicates the implemented SVC instructions */ + __IM uint32_t SYNCHPRIM : 4; /*!< Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate + the implemented Synchronization Primitive instructions */ + __IM uint32_t TABBRANCH : 4; /*!< Indicates the implemented Table Branch instructions */ + __IM uint32_t T32COPY : 4; /*!< Indicates the support for T32 non flag-setting MOV instructions */ + __IM uint32_t TRUENOP : 4; /*!< Indicates the implemented true NOP instructions */ + uint32_t : 4; + } bit; + } ID_ISAR3; + + union { + __IOM uint32_t reg; /*!< Provides information about the instruction set implemented by + the PE */ + + struct { + __IM uint32_t UNPRIV : 4; /*!< Indicates the implemented unprivileged instructions */ + __IM uint32_t WITHSHIFTS : 4; /*!< Indicates the support for writeback addressing modes */ + __IM uint32_t WRITEBACK : 4; /*!< Indicates the support for writeback addressing modes */ + uint32_t : 4; + __IM uint32_t BARRIER : 4; /*!< Indicates the implemented Barrier instructions */ + __IM uint32_t SYNCPRIM_FRAC : 4; /*!< Used in conjunction with ID_ISAR3.SynchPrim to indicate the + implemented Synchronization Primitive instructions */ + __IM uint32_t PSR_M : 4; /*!< Indicates the implemented M profile instructions to modify the + PSRs */ + uint32_t : 4; + } bit; + } ID_ISAR4; + + union { + __IOM uint32_t reg; /*!< Provides information about the instruction set implemented by + the PE */ + + struct { + __IOM uint32_t ID_ISAR5 : 32; /*!< ID_ISAR5 */ + } bit; + } ID_ISAR5; + __IM uint32_t RESERVED33; + + union { + __IOM uint32_t reg; /*!< Provides information about the architecture of the caches. CTR + is RES0 if CLIDR is zero. */ + + struct { + __IM uint32_t IMINLINE : 4; /*!< Log2 of the number of words in the smallest cache line of all + the instruction caches that are controlled by the PE */ + uint32_t : 10; + __IM uint32_t RES1_1 : 2; /*!< Reserved, RES1 */ + __IM uint32_t DMINLINE : 4; /*!< Log2 of the number of words in the smallest cache line of all + the data caches and unified caches that are controlled + by the PE */ + __IM uint32_t ERG : 4; /*!< Log2 of the number of words of the maximum size of the reservation + granule that has been implemented for the Load-Exclusive + and Store-Exclusive instructions */ + __IM uint32_t CWG : 4; /*!< Log2 of the number of words of the maximum size of memory that + can be overwritten as a result of the eviction of a cache + entry that has had a memory location in it modified */ + uint32_t : 3; + __IM uint32_t RES1 : 1; /*!< Reserved, RES1 */ + } bit; + } CTR; + __IM uint32_t RESERVED34[2]; + + union { + __IOM uint32_t reg; /*!< Specifies the access privileges for coprocessors and the FP + Extension */ + + struct { + __IOM uint32_t CP0 : 2; /*!< Controls access privileges for coprocessor 0 */ + __IOM uint32_t CP1 : 2; /*!< Controls access privileges for coprocessor 1 */ + __IOM uint32_t CP2 : 2; /*!< Controls access privileges for coprocessor 2 */ + __IOM uint32_t CP3 : 2; /*!< Controls access privileges for coprocessor 3 */ + __IOM uint32_t CP4 : 2; /*!< Controls access privileges for coprocessor 4 */ + __IOM uint32_t CP5 : 2; /*!< Controls access privileges for coprocessor 5 */ + __IOM uint32_t CP6 : 2; /*!< Controls access privileges for coprocessor 6 */ + __IOM uint32_t CP7 : 2; /*!< Controls access privileges for coprocessor 7 */ + uint32_t : 4; + __IOM uint32_t CP10 : 2; /*!< Defines the access rights for the floating-point functionality */ + __IOM uint32_t CP11 : 2; /*!< The value in this field is ignored. If the implementation does + not include the FP Extension, this field is RAZ/WI. If + the value of this bit is not programmed to the same value + as the CP10 field, then the value is UNKNOWN */ + uint32_t : 8; + } bit; + } CPACR; + + union { + __IOM uint32_t reg; /*!< Defines the Non-secure access permissions for both the FP Extension + and coprocessors CP0 to CP7 */ + + struct { + __IOM uint32_t CP0 : 1; /*!< Enables Non-secure access to coprocessor CP0 */ + __IOM uint32_t CP1 : 1; /*!< Enables Non-secure access to coprocessor CP1 */ + __IOM uint32_t CP2 : 1; /*!< Enables Non-secure access to coprocessor CP2 */ + __IOM uint32_t CP3 : 1; /*!< Enables Non-secure access to coprocessor CP3 */ + __IOM uint32_t CP4 : 1; /*!< Enables Non-secure access to coprocessor CP4 */ + __IOM uint32_t CP5 : 1; /*!< Enables Non-secure access to coprocessor CP5 */ + __IOM uint32_t CP6 : 1; /*!< Enables Non-secure access to coprocessor CP6 */ + __IOM uint32_t CP7 : 1; /*!< Enables Non-secure access to coprocessor CP7 */ + uint32_t : 2; + __IOM uint32_t CP10 : 1; /*!< Enables Non-secure access to the Floating-point Extension */ + __IOM uint32_t CP11 : 1; /*!< Enables Non-secure access to the Floating-point Extension */ + uint32_t : 20; + } bit; + } NSACR; + + union { + __IOM uint32_t reg; /*!< The MPU Type Register indicates how many regions the MPU `FTSSS + supports */ + + struct { + __IM uint32_t SEPARATE : 1; /*!< Indicates support for separate instructions and data address + regions */ + uint32_t : 7; + __IM uint32_t DREGION : 8; /*!< Number of regions supported by the MPU */ + uint32_t : 16; + } bit; + } MPU_TYPE; + + union { + __IOM uint32_t reg; /*!< Enables the MPU and, when the MPU is enabled, controls whether + the default memory map is enabled as a background region + for privileged accesses, and whether the MPU is enabled + for HardFaults, NMIs, and exception handlers when FAULTMASK + is set to 1 */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< Enables the MPU */ + __IOM uint32_t HFNMIENA : 1; /*!< Controls whether handlers executing with priority less than + 0 access memory with the MPU enabled or disabled. This + applies to HardFaults, NMIs, and exception handlers when + FAULTMASK is set to 1 */ + __IOM uint32_t PRIVDEFENA : 1; /*!< Controls whether the default memory map is enabled for privileged + software */ + uint32_t : 29; + } bit; + } MPU_CTRL; + + union { + __IOM uint32_t reg; /*!< Selects the region currently accessed by MPU_RBAR and MPU_RLAR */ + + struct { + __IOM uint32_t REGION : 3; /*!< Indicates the memory region accessed by MPU_RBAR and MPU_RLAR */ + uint32_t : 29; + } bit; + } MPU_RNR; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the base address + of the currently selected MPU region `FTSSS */ + + struct { + __IOM uint32_t XN : 1; /*!< Defines whether code can be executed from this region */ + __IOM uint32_t AP : 2; /*!< Defines the access permissions for this region */ + __IOM uint32_t SH : 2; /*!< Defines the Shareability domain of this region for Normal memory */ + __IOM uint32_t BASE : 27; /*!< Contains bits [31:5] of the lower inclusive limit of the selected + MPU memory region. This value is zero extended to provide + the base address to be checked against */ + } bit; + } MPU_RBAR; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region `FTSSS */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable */ + __IOM uint32_t ATTRINDX : 3; /*!< Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 + fields */ + uint32_t : 1; + __IOM uint32_t LIMIT : 27; /*!< Contains bits [31:5] of the upper inclusive limit of the selected + MPU memory region. This value is postfixed with 0x1F to + provide the limit address to be checked against */ + } bit; + } MPU_RLAR; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the base address + of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS */ + + struct { + __IOM uint32_t XN : 1; /*!< Defines whether code can be executed from this region */ + __IOM uint32_t AP : 2; /*!< Defines the access permissions for this region */ + __IOM uint32_t SH : 2; /*!< Defines the Shareability domain of this region for Normal memory */ + __IOM uint32_t BASE : 27; /*!< Contains bits [31:5] of the lower inclusive limit of the selected + MPU memory region. This value is zero extended to provide + the base address to be checked against */ + } bit; + } MPU_RBAR_A1; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) + `FTSSS */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable */ + __IOM uint32_t ATTRINDX : 3; /*!< Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 + fields */ + uint32_t : 1; + __IOM uint32_t LIMIT : 27; /*!< Contains bits [31:5] of the upper inclusive limit of the selected + MPU memory region. This value is postfixed with 0x1F to + provide the limit address to be checked against */ + } bit; + } MPU_RLAR_A1; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the base address + of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS */ + + struct { + __IOM uint32_t XN : 1; /*!< Defines whether code can be executed from this region */ + __IOM uint32_t AP : 2; /*!< Defines the access permissions for this region */ + __IOM uint32_t SH : 2; /*!< Defines the Shareability domain of this region for Normal memory */ + __IOM uint32_t BASE : 27; /*!< Contains bits [31:5] of the lower inclusive limit of the selected + MPU memory region. This value is zero extended to provide + the base address to be checked against */ + } bit; + } MPU_RBAR_A2; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) + `FTSSS */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable */ + __IOM uint32_t ATTRINDX : 3; /*!< Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 + fields */ + uint32_t : 1; + __IOM uint32_t LIMIT : 27; /*!< Contains bits [31:5] of the upper inclusive limit of the selected + MPU memory region. This value is postfixed with 0x1F to + provide the limit address to be checked against */ + } bit; + } MPU_RLAR_A2; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the base address + of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS */ + + struct { + __IOM uint32_t XN : 1; /*!< Defines whether code can be executed from this region */ + __IOM uint32_t AP : 2; /*!< Defines the access permissions for this region */ + __IOM uint32_t SH : 2; /*!< Defines the Shareability domain of this region for Normal memory */ + __IOM uint32_t BASE : 27; /*!< Contains bits [31:5] of the lower inclusive limit of the selected + MPU memory region. This value is zero extended to provide + the base address to be checked against */ + } bit; + } MPU_RBAR_A3; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) + `FTSSS */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable */ + __IOM uint32_t ATTRINDX : 3; /*!< Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 + fields */ + uint32_t : 1; + __IOM uint32_t LIMIT : 27; /*!< Contains bits [31:5] of the upper inclusive limit of the selected + MPU memory region. This value is postfixed with 0x1F to + provide the limit address to be checked against */ + } bit; + } MPU_RLAR_A3; + __IM uint32_t RESERVED35; + + union { + __IOM uint32_t reg; /*!< Along with MPU_MAIR1, provides the memory attribute encodings + corresponding to the AttrIndex values */ + + struct { + __IOM uint32_t ATTR0 : 8; /*!< Memory attribute encoding for MPU regions with an AttrIndex + of 0 */ + __IOM uint32_t ATTR1 : 8; /*!< Memory attribute encoding for MPU regions with an AttrIndex + of 1 */ + __IOM uint32_t ATTR2 : 8; /*!< Memory attribute encoding for MPU regions with an AttrIndex + of 2 */ + __IOM uint32_t ATTR3 : 8; /*!< Memory attribute encoding for MPU regions with an AttrIndex + of 3 */ + } bit; + } MPU_MAIR0; + + union { + __IOM uint32_t reg; /*!< Along with MPU_MAIR0, provides the memory attribute encodings + corresponding to the AttrIndex values */ + + struct { + __IOM uint32_t ATTR4 : 8; /*!< Memory attribute encoding for MPU regions with an AttrIndex + of 4 */ + __IOM uint32_t ATTR5 : 8; /*!< Memory attribute encoding for MPU regions with an AttrIndex + of 5 */ + __IOM uint32_t ATTR6 : 8; /*!< Memory attribute encoding for MPU regions with an AttrIndex + of 6 */ + __IOM uint32_t ATTR7 : 8; /*!< Memory attribute encoding for MPU regions with an AttrIndex + of 7 */ + } bit; + } MPU_MAIR1; + __IM uint32_t RESERVED36[2]; + + union { + __IOM uint32_t reg; /*!< Allows enabling of the Security Attribution Unit */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< Enables the SAU */ + __IOM uint32_t ALLNS : 1; /*!< When SAU_CTRL.ENABLE is 0 this bit controls if the memory is + marked as Non-secure or Secure */ + uint32_t : 30; + } bit; + } SAU_CTRL; + + union { + __IOM uint32_t reg; /*!< Indicates the number of regions implemented by the Security + Attribution Unit */ + + struct { + __IM uint32_t SREGION : 8; /*!< The number of implemented SAU regions */ + uint32_t : 24; + } bit; + } SAU_TYPE; + + union { + __IOM uint32_t reg; /*!< Selects the region currently accessed by SAU_RBAR and SAU_RLAR */ + + struct { + __IOM uint32_t REGION : 8; /*!< Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR */ + uint32_t : 24; + } bit; + } SAU_RNR; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the base address + of the currently selected SAU region */ + + struct { + uint32_t : 5; + __IOM uint32_t BADDR : 27; /*!< Holds bits [31:5] of the base address for the selected SAU region */ + } bit; + } SAU_RBAR; + + union { + __IOM uint32_t reg; /*!< Provides indirect read and write access to the limit address + of the currently selected SAU region */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< SAU region enable */ + __IOM uint32_t NSC : 1; /*!< Controls whether Non-secure state is permitted to execute an + SG instruction from this region */ + uint32_t : 3; + __IOM uint32_t LADDR : 27; /*!< Holds bits [31:5] of the limit address for the selected SAU + region */ + } bit; + } SAU_RLAR; + + union { + __IOM uint32_t reg; /*!< Provides information about any security related faults */ + + struct { + __IOM uint32_t INVEP : 1; /*!< This bit is set if a function call from the Non-secure state + or exception targets a non-SG instruction in the Secure + state. This bit is also set if the target address is a + SG instruction, but there is no matching SAU/IDAU region + with the NSC flag set */ + __IOM uint32_t INVIS : 1; /*!< This bit is set if the integrity signature in an exception stack + frame is found to be invalid during the unstacking operation */ + __IOM uint32_t INVER : 1; /*!< This can be caused by EXC_RETURN.DCRS being set to 0 when returning + from an exception in the Non-secure state, or by EXC_RETURN.ES + being set to 1 when returning from an exception in the + Non-secure state */ + __IOM uint32_t AUVIOL : 1; /*!< Sticky flag indicating that an attempt was made to access parts + of the address space that are marked as Secure with NS-Req + for the transaction set to Non-secure. This bit is not + set if the violation occurred during lazy state preservation. + See LSPERR */ + __IOM uint32_t INVTRAN : 1; /*!< Sticky flag indicating that an exception was raised due to a + branch that was not flagged as being domain crossing causing + a transition from Secure to Non-secure memory */ + __IOM uint32_t LSPERR : 1; /*!< Stick flag indicating that an SAU or IDAU violation occurred + during the lazy preservation of floating-point state */ + __IOM uint32_t SFARVALID : 1; /*!< This bit is set when the SFAR register contains a valid value. + As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, + this bit can be cleared by other exceptions, such as BusFault */ + __IOM uint32_t LSERR : 1; /*!< Sticky flag indicating that an error occurred during lazy state + activation or deactivation */ + uint32_t : 24; + } bit; + } SFSR; + + union { + __IOM uint32_t reg; /*!< Shows the address of the memory location that caused a Security + violation */ + + struct { + __IOM uint32_t ADDRESS : 32; /*!< The address of an access that caused a attribution unit violation. + This field is only valid when SFSR.SFARVALID is set. This + allows the actual flip flops associated with this register + to be shared with other fault address registers. If an + implementation chooses to share the storage in this way, + care must be taken to not leak Secure address information + to the Non-secure state. One way of achieving this is to + share the SFAR register with the MMFAR_S register, which + is not accessible to the Non-secure state */ + } bit; + } SFAR; + __IM uint32_t RESERVED37; + + union { + __IOM uint32_t reg; /*!< Controls halting debug */ + + struct { + __IOM uint32_t C_DEBUGEN : 1; /*!< Enable Halting debug */ + __IOM uint32_t C_HALT : 1; /*!< PE enter Debug state halt request */ + __IOM uint32_t C_STEP : 1; /*!< Enable single instruction step */ + __IOM uint32_t C_MASKINTS : 1; /*!< When debug is enabled, the debugger can write to this bit to + mask PendSV, SysTick and external configurable interrupts */ + uint32_t : 1; + __IOM uint32_t C_SNAPSTALL : 1; /*!< Allow imprecise entry to Debug state */ + uint32_t : 10; + __IM uint32_t S_REGRDY : 1; /*!< Handshake flag to transfers through the DCRDR */ + __IM uint32_t S_HALT : 1; /*!< Indicates whether the PE is in Debug state */ + __IM uint32_t S_SLEEP : 1; /*!< Indicates whether the PE is sleeping */ + __IM uint32_t S_LOCKUP : 1; /*!< Indicates whether the PE is in Lockup state */ + __IM uint32_t S_SDE : 1; /*!< Indicates whether Secure invasive debug is allowed */ + uint32_t : 3; + __IM uint32_t S_RETIRE_ST : 1; /*!< Set to 1 every time the PE retires one of more instructions */ + __IM uint32_t S_RESET_ST : 1; /*!< Indicates whether the PE has been reset since the last read + of the DHCSR */ + __IM uint32_t S_RESTART_ST : 1; /*!< Indicates the PE has processed a request to clear DHCSR.C_HALT + to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT + from 1 to 0, or an External Restart Request */ + uint32_t : 5; + } bit; + } DHCSR; + + union { + __IOM uint32_t reg; /*!< With the DCRDR, provides debug access to the general-purpose + registers, special-purpose registers, and the FP extension + registers. A write to the DCRSR specifies the register + to transfer, whether the transfer is a read or write, and + starts the transfer */ + + struct { + __IOM uint32_t REGSEL : 7; /*!< Specifies the general-purpose register, special-purpose register, + or FP register to transfer */ + uint32_t : 9; + __IOM uint32_t REGWNR : 1; /*!< Specifies the access type for the transfer */ + uint32_t : 15; + } bit; + } DCRSR; + + union { + __IOM uint32_t reg; /*!< With the DCRSR, provides debug access to the general-purpose + registers, special-purpose registers, and the FP Extension + registers. If the Main Extension is implemented, it can + also be used for message passing between an external debugger + and a debug agent running on the PE */ + + struct { + __IOM uint32_t DBGTMP : 32; /*!< Provides debug access for reading and writing the general-purpose + registers, special-purpose registers, and Floating-point + Extension registers */ + } bit; + } DCRDR; + + union { + __IOM uint32_t reg; /*!< Manages vector catch behavior and DebugMonitor handling when + debugging */ + + struct { + __IOM uint32_t VC_CORERESET : 1; /*!< Enable Reset Vector Catch. This causes a warm reset to halt + a running system */ + uint32_t : 3; + __IOM uint32_t VC_MMERR : 1; /*!< Enable halting debug trap on a MemManage exception */ + __IOM uint32_t VC_NOCPERR : 1; /*!< Enable halting debug trap on a UsageFault caused by an access + to a coprocessor */ + __IOM uint32_t VC_CHKERR : 1; /*!< Enable halting debug trap on a UsageFault exception caused by + a checking error, for example an alignment check error */ + __IOM uint32_t VC_STATERR : 1; /*!< Enable halting debug trap on a UsageFault exception caused by + a state information error, for example an Undefined Instruction + exception */ + __IOM uint32_t VC_BUSERR : 1; /*!< BusFault exception halting debug vector catch enable */ + __IOM uint32_t VC_INTERR : 1; /*!< Enable halting debug vector catch for faults during exception + entry and return */ + __IOM uint32_t VC_HARDERR : 1; /*!< HardFault exception halting debug vector catch enable */ + __IOM uint32_t VC_SFERR : 1; /*!< SecureFault exception halting debug vector catch enable */ + uint32_t : 4; + __IOM uint32_t MON_EN : 1; /*!< Enable the DebugMonitor exception */ + __IOM uint32_t MON_PEND : 1; /*!< Sets or clears the pending state of the DebugMonitor exception */ + __IOM uint32_t MON_STEP : 1; /*!< Enable DebugMonitor stepping */ + __IOM uint32_t MON_REQ : 1; /*!< DebugMonitor semaphore bit */ + __IM uint32_t SDME : 1; /*!< Indicates whether the DebugMonitor targets the Secure or the + Non-secure state and whether debug events are allowed in + Secure state */ + uint32_t : 3; + __IOM uint32_t TRCENA : 1; /*!< Global enable for all DWT and ITM features */ + uint32_t : 7; + } bit; + } DEMCR; + __IM uint32_t RESERVED38[2]; + + union { + __IOM uint32_t reg; /*!< Provides control and status information for Secure debug */ + + struct { + __IOM uint32_t SBRSELEN : 1; /*!< Controls whether the SBRSEL field or the current Security state + of the processor selects which version of the memory-mapped + Banked registers are accessed to the debugger */ + __IOM uint32_t SBRSEL : 1; /*!< If SBRSELEN is 1 this bit selects whether the Non-secure or + the Secure version of the memory-mapped Banked registers + are accessible to the debugger */ + uint32_t : 14; + __IOM uint32_t CDS : 1; /*!< This field indicates the current Security state of the processor */ + __IOM uint32_t CDSKEY : 1; /*!< Writes to the CDS bit are ignored unless CDSKEY is concurrently + written to zero */ + uint32_t : 14; + } bit; + } DSCSR; + __IM uint32_t RESERVED39[61]; + + union { + __IOM uint32_t reg; /*!< Provides a mechanism for software to generate an interrupt */ + + struct { + __IOM uint32_t INTID : 9; /*!< Indicates the interrupt to be pended. The value written is (ExceptionNumber + - 16) */ + uint32_t : 23; + } bit; + } STIR; + __IM uint32_t RESERVED40[12]; + + union { + __IOM uint32_t reg; /*!< Holds control data for the Floating-point extension */ + + struct { + __IOM uint32_t LSPACT : 1; /*!< Indicates whether lazy preservation of the floating-point state + is active */ + __IOM uint32_t USER : 1; /*!< Indicates the privilege level of the software executing when + the PE allocated the floating-point stack frame */ + __IOM uint32_t S : 1; /*!< Security status of the floating-point context. This bit is only + present in the Secure version of the register, and behaves + as RAZ/WI when accessed from the Non-secure state. This + bit is updated whenever lazy state preservation is activated, + or when a floating-point instruction is executed */ + __IOM uint32_t THREAD : 1; /*!< Indicates the PE mode when it allocated the floating-point stack + frame */ + __IOM uint32_t HFRDY : 1; /*!< Indicates whether the software executing when the PE allocated + the floating-point stack frame was able to set the HardFault + exception to pending */ + __IOM uint32_t MMRDY : 1; /*!< Indicates whether the software executing when the PE allocated + the floating-point stack frame was able to set the MemManage + exception to pending */ + __IOM uint32_t BFRDY : 1; /*!< Indicates whether the software executing when the PE allocated + the floating-point stack frame was able to set the BusFault + exception to pending */ + __IOM uint32_t SFRDY : 1; /*!< Indicates whether the software executing when the PE allocated + the floating-point stack frame was able to set the SecureFault + exception to pending. This bit is only present in the Secure + version of the register, and behaves as RAZ/WI when accessed + from the Non-secure state */ + __IOM uint32_t MONRDY : 1; /*!< Indicates whether the software executing when the PE allocated + the floating-point stack frame was able to set the DebugMonitor + exception to pending */ + __IOM uint32_t SPLIMVIOL : 1; /*!< This bit is banked between the Security states and indicates + whether the floating-point context violates the stack pointer + limit that was active when lazy state preservation was + activated. SPLIMVIOL modifies the lazy floating-point state + preservation behavior */ + __IOM uint32_t UFRDY : 1; /*!< Indicates whether the software executing when the PE allocated + the floating-point stack frame was able to set the UsageFault + exception to pending */ + uint32_t : 15; + __IOM uint32_t TS : 1; /*!< Treat floating-point registers as Secure enable */ + __IOM uint32_t CLRONRETS : 1; /*!< This bit controls whether the CLRONRET bit is writeable from + the Non-secure state */ + __IOM uint32_t CLRONRET : 1; /*!< Clear floating-point caller saved registers on exception return */ + __IOM uint32_t LSPENS : 1; /*!< This bit controls whether the LSPEN bit is writeable from the + Non-secure state */ + __IOM uint32_t LSPEN : 1; /*!< Enables lazy context save of floating-point state */ + __IOM uint32_t ASPEN : 1; /*!< When this bit is set to 1, execution of a floating-point instruction + sets the CONTROL.FPCA bit to 1 */ + } bit; + } FPCCR; + + union { + __IOM uint32_t reg; /*!< Holds the location of the unpopulated floating-point register + space allocated on an exception stack frame */ + + struct { + uint32_t : 3; + __IOM uint32_t ADDRESS : 29; /*!< The location of the unpopulated floating-point register space + allocated on an exception stack frame */ + } bit; + } FPCAR; + + union { + __IOM uint32_t reg; /*!< Holds the default values for the floating-point status control + data that the PE assigns to the FPSCR when it creates a + new floating-point context */ + + struct { + uint32_t : 22; + __IOM uint32_t RMODE : 2; /*!< Default value for FPSCR.RMode */ + __IOM uint32_t FZ : 1; /*!< Default value for FPSCR.FZ */ + __IOM uint32_t DN : 1; /*!< Default value for FPSCR.DN */ + __IOM uint32_t AHP : 1; /*!< Default value for FPSCR.AHP */ + uint32_t : 5; + } bit; + } FPDSCR; + + union { + __IOM uint32_t reg; /*!< Describes the features provided by the Floating-point Extension */ + + struct { + __IM uint32_t SIMDREG : 4; /*!< Indicates size of FP register file */ + __IM uint32_t FPSP : 4; /*!< Indicates support for FP single-precision operations */ + __IM uint32_t FPDP : 4; /*!< Indicates support for FP double-precision operations */ + uint32_t : 4; + __IM uint32_t FPDIVIDE : 4; /*!< Indicates the support for FP divide operations */ + __IM uint32_t FPSQRT : 4; /*!< Indicates the support for FP square root operations */ + uint32_t : 4; + __IM uint32_t FPROUND : 4; /*!< Indicates the rounding modes supported by the FP Extension */ + } bit; + } MVFR0; + + union { + __IOM uint32_t reg; /*!< Describes the features provided by the Floating-point Extension */ + + struct { + __IM uint32_t FPFTZ : 4; /*!< Indicates whether subnormals are always flushed-to-zero */ + __IM uint32_t FPDNAN : 4; /*!< Indicates whether the FP hardware implementation supports NaN + propagation */ + uint32_t : 16; + __IM uint32_t FPHP : 4; /*!< Indicates whether the FP Extension implements half-precision + FP conversion instructions */ + __IM uint32_t FMAC : 4; /*!< Indicates whether the FP Extension implements the fused multiply + accumulate instructions */ + } bit; + } MVFR1; + + union { + __IOM uint32_t reg; /*!< Describes the features provided by the Floating-point Extension */ + + struct { + uint32_t : 4; + __IM uint32_t FPMISC : 4; /*!< Indicates support for miscellaneous FP features */ + uint32_t : 24; + } bit; + } MVFR2; + __IM uint32_t RESERVED41[28]; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t ARCHPART : 12; /*!< Defines the architecture of the component */ + __IM uint32_t ARCHVER : 4; /*!< Defines the architecture version of the component */ + __IM uint32_t REVISION : 4; /*!< Defines the architecture revision of the component */ + __IM uint32_t PRESENT : 1; /*!< Defines that the DEVARCH register is present */ + __IM uint32_t ARCHITECT : 11; /*!< Defines the architect of the component. Bits [31:28] are the + JEP106 continuation code (JEP106 bank ID, minus 1) and + bits [27:21] are the JEP106 ID code. */ + } bit; + } DDEVARCH; + __IM uint32_t RESERVED42[3]; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t MAJOR : 4; /*!< CoreSight major type */ + __IM uint32_t SUB : 4; /*!< Component sub-type */ + uint32_t : 24; + } bit; + } DDEVTYPE; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t DES_2 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t SIZE : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DPIDR4; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IOM uint32_t DPIDR5 : 32; /*!< DPIDR5 */ + } bit; + } DPIDR5; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IOM uint32_t DPIDR6 : 32; /*!< DPIDR6 */ + } bit; + } DPIDR6; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IOM uint32_t DPIDR7 : 32; /*!< DPIDR7 */ + } bit; + } DPIDR7; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t PART_0 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DPIDR0; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t PART_1 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t DES_0 : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DPIDR1; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t DES_1 : 3; /*!< See CoreSight Architecture Specification */ + __IM uint32_t JEDEC : 1; /*!< See CoreSight Architecture Specification */ + __IM uint32_t REVISION : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DPIDR2; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t CMOD : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t REVAND : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DPIDR3; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t PRMBL_0 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DCIDR0; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t PRMBL_1 : 4; /*!< See CoreSight Architecture Specification */ + __IM uint32_t CLASS : 4; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DCIDR1; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t PRMBL_2 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DCIDR2; + + union { + __IOM uint32_t reg; /*!< Provides CoreSight discovery information for the SCS */ + + struct { + __IM uint32_t PRMBL_3 : 8; /*!< See CoreSight Architecture Specification */ + uint32_t : 24; + } bit; + } DCIDR3; + __IM uint32_t RESERVED43[51201]; + + union { + __IOM uint32_t reg; /*!< Programming Control Register */ + + struct { + __IOM uint32_t EN : 1; /*!< Trace Unit Enable */ + uint32_t : 31; + } bit; + } TRCPRGCTLR; + __IM uint32_t RESERVED44; + + union { + __IOM uint32_t reg; /*!< The TRCSTATR indicates the ETM-Teal status */ + + struct { + __IM uint32_t IDLE : 1; /*!< Indicates that the trace unit is inactive */ + __IM uint32_t PMSTABLE : 1; /*!< Indicates whether the ETM-Teal registers are stable and can + be read */ + uint32_t : 30; + } bit; + } TRCSTATR; + + union { + __IOM uint32_t reg; /*!< The TRCCONFIGR sets the basic tracing options for the trace + unit */ + + struct { + uint32_t : 3; + __IOM uint32_t BB : 1; /*!< Branch broadcast mode */ + __IOM uint32_t CCI : 1; /*!< Cycle counting in instruction trace */ + __IOM uint32_t COND : 6; /*!< Conditional instruction tracing */ + __IOM uint32_t TS : 1; /*!< Global timestamp tracing */ + __IOM uint32_t RS : 1; /*!< Return stack enable */ + uint32_t : 19; + } bit; + } TRCCONFIGR; + __IM uint32_t RESERVED45[3]; + + union { + __IOM uint32_t reg; /*!< The TRCEVENTCTL0R controls the tracing of events in the trace + stream. The events also drive the ETM-Teal external outputs. */ + + struct { + __IOM uint32_t SEL0 : 3; /*!< Selects the resource number, based on the value of TYPE0: When + TYPE1 is 0, selects a single selected resource from 0-15 + defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean + combined resource pair from 0-7 defined by SEL0[2:0] */ + uint32_t : 4; + __IOM uint32_t TYPE0 : 1; /*!< Selects the resource type for event 0 */ + __IOM uint32_t SEL1 : 3; /*!< Selects the resource number, based on the value of TYPE1: When + TYPE1 is 0, selects a single selected resource from 0-15 + defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean + combined resource pair from 0-7 defined by SEL1[2:0] */ + uint32_t : 4; + __IOM uint32_t TYPE1 : 1; /*!< Selects the resource type for event 1 */ + uint32_t : 16; + } bit; + } TRCEVENTCTL0R; + + union { + __IOM uint32_t reg; /*!< The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R + behave */ + + struct { + __IOM uint32_t INSTEN0 : 1; /*!< One bit per event, to enable generation of an event element + in the instruction trace stream when the selected event + occurs */ + __IOM uint32_t INSTEN1 : 1; /*!< One bit per event, to enable generation of an event element + in the instruction trace stream when the selected event + occurs */ + uint32_t : 9; + __IOM uint32_t ATB : 1; /*!< ATB enabled */ + __IOM uint32_t LPOVERRIDE : 1; /*!< Low power state behavior override */ + uint32_t : 19; + } bit; + } TRCEVENTCTL1R; + __IM uint32_t RESERVED46; + + union { + __IOM uint32_t reg; /*!< The TRCSTALLCTLR enables ETM-Teal to stall the processor if + the ETM-Teal FIFO goes over the programmed level to minimize + risk of overflow */ + + struct { + uint32_t : 2; + __IOM uint32_t LEVEL : 2; /*!< Threshold at which stalling becomes active. This provides four + levels. This level can be varied to optimize the level + of invasion caused by stalling, balanced against the risk + of a FIFO overflow */ + uint32_t : 4; + __IOM uint32_t ISTALL : 1; /*!< Stall processor based on instruction trace buffer space */ + uint32_t : 1; + __IM uint32_t INSTPRIORITY : 1; /*!< Reserved, RES0 */ + uint32_t : 21; + } bit; + } TRCSTALLCTLR; + + union { + __IOM uint32_t reg; /*!< The TRCTSCTLR controls the insertion of global timestamps into + the trace stream. A timestamp is always inserted into the + instruction trace stream */ + + struct { + __IOM uint32_t SEL0 : 2; /*!< Selects the resource number, based on the value of TYPE0: When + TYPE1 is 0, selects a single selected resource from 0-15 + defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean + combined resource pair from 0-7 defined by SEL0[2:0] */ + uint32_t : 5; + __IOM uint32_t TYPE0 : 1; /*!< Selects the resource type for event 0 */ + uint32_t : 24; + } bit; + } TRCTSCTLR; + + union { + __IOM uint32_t reg; /*!< The TRCSYNCPR specifies the period of trace synchronization + of the trace streams. TRCSYNCPR defines a number of bytes + of trace between requests for trace synchronization. This + value is always a power of two */ + + struct { + __IM uint32_t PERIOD : 5; /*!< Defines the number of bytes of trace between trace synchronization + requests as a total of the number of bytes generated by + the instruction stream. The number of bytes is 2N where + N is the value of this field: - A value of zero disables + these periodic trace synchronization requests, but does + not disable other trace synchronization requests. - The + minimum value that can be programmed, other than zero, + is 8, providing a minimum trace synchronization period + of 256 bytes. - The maximum value is 20, providing a maximum + trace synchronization period of 2^20 bytes */ + uint32_t : 27; + } bit; + } TRCSYNCPR; + + union { + __IOM uint32_t reg; /*!< The TRCCCCTLR sets the threshold value for instruction trace + cycle counting. The threshold represents the minimum interval + between cycle count trace packets */ + + struct { + __IOM uint32_t THRESHOLD : 12; /*!< Instruction trace cycle count threshold */ + uint32_t : 20; + } bit; + } TRCCCCTLR; + __IM uint32_t RESERVED47[17]; + + union { + __IOM uint32_t reg; /*!< The TRCVICTLR controls instruction trace filtering */ + + struct { + __IOM uint32_t SEL0 : 2; /*!< Selects the resource number, based on the value of TYPE0: When + TYPE1 is 0, selects a single selected resource from 0-15 + defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean + combined resource pair from 0-7 defined by SEL0[2:0] */ + uint32_t : 5; + __IOM uint32_t TYPE0 : 1; /*!< Selects the resource type for event 0 */ + uint32_t : 1; + __IOM uint32_t SSSTATUS : 1; /*!< Indicates the current status of the start/stop logic */ + __IOM uint32_t TRCRESET : 1; /*!< Selects whether a reset exception must always be traced */ + __IOM uint32_t TRCERR : 1; /*!< Selects whether a system error exception must always be traced */ + uint32_t : 4; + __IOM uint32_t EXLEVEL_S0 : 1; /*!< In Secure state, each bit controls whether instruction tracing + is enabled for the corresponding exception level */ + uint32_t : 2; + __IOM uint32_t EXLEVEL_S3 : 1; /*!< In Secure state, each bit controls whether instruction tracing + is enabled for the corresponding exception level */ + uint32_t : 12; + } bit; + } TRCVICTLR; + __IM uint32_t RESERVED48[47]; + + union { + __IOM uint32_t reg; /*!< The TRCCNTRLDVR defines the reload value for the reduced function + counter */ + + struct { + __IOM uint32_t VALUE : 16; /*!< Defines the reload value for the counter. This value is loaded + into the counter each time the reload event occurs */ + uint32_t : 16; + } bit; + } TRCCNTRLDVR0; + __IM uint32_t RESERVED49[15]; + + union { + __IOM uint32_t reg; /*!< TRCIDR8 */ + + struct { + __IM uint32_t MAXSPEC : 32; /*!< reads as `ImpDef */ + } bit; + } TRCIDR8; + + union { + __IOM uint32_t reg; /*!< TRCIDR9 */ + + struct { + __IM uint32_t NUMP0KEY : 32; /*!< reads as `ImpDef */ + } bit; + } TRCIDR9; + + union { + __IOM uint32_t reg; /*!< TRCIDR10 */ + + struct { + __IM uint32_t NUMP1KEY : 32; /*!< reads as `ImpDef */ + } bit; + } TRCIDR10; + + union { + __IOM uint32_t reg; /*!< TRCIDR11 */ + + struct { + __IM uint32_t NUMP1SPC : 32; /*!< reads as `ImpDef */ + } bit; + } TRCIDR11; + + union { + __IOM uint32_t reg; /*!< TRCIDR12 */ + + struct { + __IM uint32_t NUMCONDKEY : 32; /*!< reads as `ImpDef */ + } bit; + } TRCIDR12; + + union { + __IOM uint32_t reg; /*!< TRCIDR13 */ + + struct { + __IM uint32_t NUMCONDSPC : 32; /*!< reads as `ImpDef */ + } bit; + } TRCIDR13; + __IM uint32_t RESERVED50[10]; + + union { + __IOM uint32_t reg; /*!< The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC + features, and enables any features that are provided */ + + struct { + __IM uint32_t SUPPORT : 4; /*!< Reserved, RES0 */ + uint32_t : 28; + } bit; + } TRCIMSPEC; + __IM uint32_t RESERVED51[7]; + + union { + __IOM uint32_t reg; /*!< TRCIDR0 */ + + struct { + __IM uint32_t RES1 : 1; /*!< Reserved, RES1 */ + __IM uint32_t INSTP0 : 2; /*!< reads as `ImpDef */ + __IM uint32_t TRCDATA : 2; /*!< reads as `ImpDef */ + __IM uint32_t TRCBB : 1; /*!< reads as `ImpDef */ + __IM uint32_t TRCCOND : 1; /*!< reads as `ImpDef */ + __IM uint32_t TRCCCI : 1; /*!< reads as `ImpDef */ + uint32_t : 1; + __IM uint32_t RETSTACK : 1; /*!< reads as `ImpDef */ + __IM uint32_t NUMEVENT : 2; /*!< reads as `ImpDef */ + __IM uint32_t CONDTYPE : 2; /*!< reads as `ImpDef */ + __IM uint32_t QFILT : 1; /*!< reads as `ImpDef */ + __IM uint32_t QSUPP : 2; /*!< reads as `ImpDef */ + __IM uint32_t TRCEXDATA : 1; /*!< reads as `ImpDef */ + uint32_t : 6; + __IM uint32_t TSSIZE : 5; /*!< reads as `ImpDef */ + __IM uint32_t COMMOPT : 1; /*!< reads as `ImpDef */ + uint32_t : 2; + } bit; + } TRCIDR0; + + union { + __IOM uint32_t reg; /*!< TRCIDR1 */ + + struct { + __IM uint32_t REVISION : 4; /*!< reads as `ImpDef */ + __IM uint32_t TRCARCHMIN : 4; /*!< reads as 0b0000 */ + __IM uint32_t TRCARCHMAJ : 4; /*!< reads as 0b0100 */ + __IM uint32_t RES1 : 4; /*!< Reserved, RES1 */ + uint32_t : 8; + __IM uint32_t DESIGNER : 8; /*!< reads as `ImpDef */ + } bit; + } TRCIDR1; + + union { + __IOM uint32_t reg; /*!< TRCIDR2 */ + + struct { + __IM uint32_t IASIZE : 5; /*!< reads as `ImpDef */ + __IM uint32_t CIDSIZE : 5; /*!< reads as `ImpDef */ + __IM uint32_t VMIDSIZE : 5; /*!< reads as `ImpDef */ + __IM uint32_t DASIZE : 5; /*!< reads as `ImpDef */ + __IM uint32_t DVSIZE : 5; /*!< reads as `ImpDef */ + __IM uint32_t CCSIZE : 4; /*!< reads as `ImpDef */ + uint32_t : 3; + } bit; + } TRCIDR2; + + union { + __IOM uint32_t reg; /*!< TRCIDR3 */ + + struct { + __IM uint32_t CCITMIN : 12; /*!< reads as `ImpDef */ + uint32_t : 4; + __IM uint32_t EXLEVEL_S : 4; /*!< reads as `ImpDef */ + __IM uint32_t EXLEVEL_NS : 4; /*!< reads as `ImpDef */ + __IM uint32_t TRCERR : 1; /*!< reads as `ImpDef */ + __IM uint32_t SYNCPR : 1; /*!< reads as `ImpDef */ + __IM uint32_t STALLCTL : 1; /*!< reads as `ImpDef */ + __IM uint32_t SYSSTALL : 1; /*!< reads as `ImpDef */ + __IM uint32_t NUMPROC : 3; /*!< reads as `ImpDef */ + __IM uint32_t NOOVERFLOW : 1; /*!< reads as `ImpDef */ + } bit; + } TRCIDR3; + + union { + __IOM uint32_t reg; /*!< TRCIDR4 */ + + struct { + __IM uint32_t NUMACPAIRS : 4; /*!< reads as `ImpDef */ + __IM uint32_t NUMDVC : 4; /*!< reads as `ImpDef */ + __IM uint32_t SUPPDAC : 1; /*!< reads as `ImpDef */ + uint32_t : 3; + __IM uint32_t NUMPC : 4; /*!< reads as `ImpDef */ + __IM uint32_t NUMRSPAIR : 4; /*!< reads as `ImpDef */ + __IM uint32_t NUMSSCC : 4; /*!< reads as `ImpDef */ + __IM uint32_t NUMCIDC : 4; /*!< reads as `ImpDef */ + __IM uint32_t NUMVMIDC : 4; /*!< reads as `ImpDef */ + } bit; + } TRCIDR4; + + union { + __IOM uint32_t reg; /*!< TRCIDR5 */ + + struct { + __IM uint32_t NUMEXTIN : 9; /*!< reads as `ImpDef */ + __IM uint32_t NUMEXTINSEL : 3; /*!< reads as `ImpDef */ + uint32_t : 4; + __IM uint32_t TRACEIDSIZE : 6; /*!< reads as 0x07 */ + __IM uint32_t ATBTRIG : 1; /*!< reads as `ImpDef */ + __IM uint32_t LPOVERRIDE : 1; /*!< reads as `ImpDef */ + uint32_t : 1; + __IM uint32_t NUMSEQSTATE : 3; /*!< reads as `ImpDef */ + __IM uint32_t NUMCNTR : 3; /*!< reads as `ImpDef */ + __IM uint32_t REDFUNCNTR : 1; /*!< reads as `ImpDef */ + } bit; + } TRCIDR5; + + union { + __IOM uint32_t reg; /*!< TRCIDR6 */ + + struct { + __IOM uint32_t TRCIDR6 : 32; /*!< TRCIDR6 */ + } bit; + } TRCIDR6; + + union { + __IOM uint32_t reg; /*!< TRCIDR7 */ + + struct { + __IOM uint32_t TRCIDR7 : 32; /*!< TRCIDR7 */ + } bit; + } TRCIDR7; + __IM uint32_t RESERVED52[2]; + + union { + __IOM uint32_t reg; /*!< The TRCRSCTLR controls the trace resources */ + + struct { + __IOM uint32_t SELECT : 8; /*!< Selects one or more resources from the wanted group. One bit + is provided per resource from the group */ + uint32_t : 8; + __IOM uint32_t GROUP : 3; /*!< Selects a group of resource */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< Inverts the selected resources */ + __IOM uint32_t PAIRINV : 1; /*!< Inverts the result of a combined pair of resources. This bit + is only implemented on the lower register for a pair of + resource selectors */ + uint32_t : 10; + } bit; + } TRCRSCTLR2; + + union { + __IOM uint32_t reg; /*!< The TRCRSCTLR controls the trace resources */ + + struct { + __IOM uint32_t SELECT : 8; /*!< Selects one or more resources from the wanted group. One bit + is provided per resource from the group */ + uint32_t : 8; + __IOM uint32_t GROUP : 3; /*!< Selects a group of resource */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< Inverts the selected resources */ + __IOM uint32_t PAIRINV : 1; /*!< Inverts the result of a combined pair of resources. This bit + is only implemented on the lower register for a pair of + resource selectors */ + uint32_t : 10; + } bit; + } TRCRSCTLR3; + __IM uint32_t RESERVED53[36]; + + union { + __IOM uint32_t reg; /*!< Controls the corresponding single-shot comparator resource */ + + struct { + __IM uint32_t INST : 1; /*!< Reserved, RES0 */ + __IM uint32_t DA : 1; /*!< Reserved, RES0 */ + __IM uint32_t DV : 1; /*!< Reserved, RES0 */ + __IM uint32_t PC : 1; /*!< Reserved, RES1 */ + uint32_t : 27; + __IOM uint32_t STATUS : 1; /*!< Single-shot status bit. Indicates if any of the comparators, + that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched */ + } bit; + } TRCSSCSR; + __IM uint32_t RESERVED54[7]; + + union { + __IOM uint32_t reg; /*!< Selects the PE comparator inputs for Single-shot control */ + + struct { + __IOM uint32_t PC : 4; /*!< Selects one or more PE comparator inputs for Single-shot control. + TRCIDR4.NUMPC defines the size of the PC field. 1 bit is + provided for each implemented PE comparator input. For + example, if bit[1] == 1 this selects PE comparator input + 1 for Single-shot control */ + uint32_t : 28; + } bit; + } TRCSSPCICR; + __IM uint32_t RESERVED55[19]; + + union { + __IOM uint32_t reg; /*!< Requests the system to provide power to the trace unit */ + + struct { + uint32_t : 3; + __IOM uint32_t PU : 1; /*!< Powerup request bit: */ + uint32_t : 28; + } bit; + } TRCPDCR; + + union { + __IOM uint32_t reg; /*!< Returns the following information about the trace unit: - OS + Lock status. - Core power domain status. - Power interruption + status */ + + struct { + __IM uint32_t POWER : 1; /*!< Power status bit: */ + __IM uint32_t STICKYPD : 1; /*!< Sticky powerdown status bit. Indicates whether the trace register + state is valid: */ + uint32_t : 3; + __IM uint32_t OSLK : 1; /*!< OS Lock status bit: */ + uint32_t : 26; + } bit; + } TRCPDSR; + __IM uint32_t RESERVED56[755]; + + union { + __IOM uint32_t reg; /*!< Trace Integration ATB Identification Register */ + + struct { + __IOM uint32_t ID : 7; /*!< Trace ID */ + uint32_t : 25; + } bit; + } TRCITATBIDR; + __IM uint32_t RESERVED57[3]; + + union { + __IOM uint32_t reg; /*!< Trace Integration Instruction ATB In Register */ + + struct { + __IOM uint32_t ATREADYM : 1; /*!< Integration Mode instruction ATREADYM in */ + __IOM uint32_t AFVALIDM : 1; /*!< Integration Mode instruction AFVALIDM in */ + uint32_t : 30; + } bit; + } TRCITIATBINR; + __IM uint32_t RESERVED58; + + union { + __IOM uint32_t reg; /*!< Trace Integration Instruction ATB Out Register */ + + struct { + __IOM uint32_t ATVALID : 1; /*!< Integration Mode instruction ATVALID out */ + __IOM uint32_t AFREADY : 1; /*!< Integration Mode instruction AFREADY out */ + uint32_t : 30; + } bit; + } TRCITIATBOUTR; + __IM uint32_t RESERVED59[40]; + + union { + __IOM uint32_t reg; /*!< Claim Tag Set Register */ + + struct { + __IOM uint32_t SET0 : 1; /*!< When a write to one of these bits occurs, with the value: */ + __IOM uint32_t SET1 : 1; /*!< When a write to one of these bits occurs, with the value: */ + __IOM uint32_t SET2 : 1; /*!< When a write to one of these bits occurs, with the value: */ + __IOM uint32_t SET3 : 1; /*!< When a write to one of these bits occurs, with the value: */ + uint32_t : 28; + } bit; + } TRCCLAIMSET; + + union { + __IOM uint32_t reg; /*!< Claim Tag Clear Register */ + + struct { + __IOM uint32_t CLR0 : 1; /*!< When a write to one of these bits occurs, with the value: */ + __IOM uint32_t CLR1 : 1; /*!< When a write to one of these bits occurs, with the value: */ + __IOM uint32_t CLR2 : 1; /*!< When a write to one of these bits occurs, with the value: */ + __IOM uint32_t CLR3 : 1; /*!< When a write to one of these bits occurs, with the value: */ + uint32_t : 28; + } bit; + } TRCCLAIMCLR; + __IM uint32_t RESERVED60[4]; + + union { + __IOM uint32_t reg; /*!< Returns the level of tracing that the trace unit can support */ + + struct { + __IM uint32_t NSID : 2; /*!< Indicates whether the trace unit supports Non-secure invasive + debug: */ + __IM uint32_t NSNID : 2; /*!< Indicates whether the system enables the trace unit to support + Non-secure non-invasive debug: */ + __IM uint32_t SID : 2; /*!< Indicates whether the trace unit supports Secure invasive debug: */ + __IM uint32_t SNID : 2; /*!< Indicates whether the system enables the trace unit to support + Secure non-invasive debug: */ + uint32_t : 24; + } bit; + } TRCAUTHSTATUS; + + union { + __IOM uint32_t reg; /*!< TRCDEVARCH */ + + struct { + __IM uint32_t ARCHID : 16; /*!< reads as 0b0100101000010011 */ + __IM uint32_t REVISION : 4; /*!< reads as 0b0000 */ + __IM uint32_t PRESENT : 1; /*!< reads as 0b1 */ + __IM uint32_t ARCHITECT : 11; /*!< reads as 0b01000111011 */ + } bit; + } TRCDEVARCH; + __IM uint32_t RESERVED61[2]; + + union { + __IOM uint32_t reg; /*!< TRCDEVID */ + + struct { + __IOM uint32_t TRCDEVID : 32; /*!< TRCDEVID */ + } bit; + } TRCDEVID; + + union { + __IOM uint32_t reg; /*!< TRCDEVTYPE */ + + struct { + __IM uint32_t MAJOR : 4; /*!< reads as 0b0011 */ + __IM uint32_t SUB : 4; /*!< reads as 0b0001 */ + uint32_t : 24; + } bit; + } TRCDEVTYPE; + + union { + __IOM uint32_t reg; /*!< TRCPIDR4 */ + + struct { + __IM uint32_t DES_2 : 4; /*!< reads as `ImpDef */ + __IM uint32_t SIZE : 4; /*!< reads as `ImpDef */ + uint32_t : 24; + } bit; + } TRCPIDR4; + + union { + __IOM uint32_t reg; /*!< TRCPIDR5 */ + + struct { + __IOM uint32_t TRCPIDR5 : 32; /*!< TRCPIDR5 */ + } bit; + } TRCPIDR5; + + union { + __IOM uint32_t reg; /*!< TRCPIDR6 */ + + struct { + __IOM uint32_t TRCPIDR6 : 32; /*!< TRCPIDR6 */ + } bit; + } TRCPIDR6; + + union { + __IOM uint32_t reg; /*!< TRCPIDR7 */ + + struct { + __IOM uint32_t TRCPIDR7 : 32; /*!< TRCPIDR7 */ + } bit; + } TRCPIDR7; + + union { + __IOM uint32_t reg; /*!< TRCPIDR0 */ + + struct { + __IM uint32_t PART_0 : 8; /*!< reads as `ImpDef */ + uint32_t : 24; + } bit; + } TRCPIDR0; + + union { + __IOM uint32_t reg; /*!< TRCPIDR1 */ + + struct { + __IM uint32_t PART_0 : 4; /*!< reads as `ImpDef */ + __IM uint32_t DES_0 : 4; /*!< reads as `ImpDef */ + uint32_t : 24; + } bit; + } TRCPIDR1; + + union { + __IOM uint32_t reg; /*!< TRCPIDR2 */ + + struct { + __IM uint32_t DES_0 : 3; /*!< reads as `ImpDef */ + __IM uint32_t JEDEC : 1; /*!< reads as 0b1 */ + __IM uint32_t REVISION : 4; /*!< reads as `ImpDef */ + uint32_t : 24; + } bit; + } TRCPIDR2; + + union { + __IOM uint32_t reg; /*!< TRCPIDR3 */ + + struct { + __IM uint32_t CMOD : 4; /*!< reads as `ImpDef */ + __IM uint32_t REVAND : 4; /*!< reads as `ImpDef */ + uint32_t : 24; + } bit; + } TRCPIDR3; + + union { + __IOM uint32_t reg; /*!< TRCCIDR0 */ + + struct { + __IM uint32_t PRMBL_0 : 8; /*!< reads as 0b00001101 */ + uint32_t : 24; + } bit; + } TRCCIDR0; + + union { + __IOM uint32_t reg; /*!< TRCCIDR1 */ + + struct { + __IM uint32_t PRMBL_1 : 4; /*!< reads as 0b0000 */ + __IM uint32_t CLASS : 4; /*!< reads as 0b1001 */ + uint32_t : 24; + } bit; + } TRCCIDR1; + + union { + __IOM uint32_t reg; /*!< TRCCIDR2 */ + + struct { + __IM uint32_t PRMBL_2 : 8; /*!< reads as 0b00000101 */ + uint32_t : 24; + } bit; + } TRCCIDR2; + + union { + __IOM uint32_t reg; /*!< TRCCIDR3 */ + + struct { + __IM uint32_t PRMBL_3 : 8; /*!< reads as 0b10110001 */ + uint32_t : 24; + } bit; + } TRCCIDR3; + + union { + __IOM uint32_t reg; /*!< CTI Control Register */ + + struct { + __IOM uint32_t GLBEN : 1; /*!< Enables or disables the CTI */ + uint32_t : 31; + } bit; + } CTICONTROL; + __IM uint32_t RESERVED62[3]; + + union { + __IOM uint32_t reg; /*!< CTI Interrupt Acknowledge Register */ + + struct { + __IOM uint32_t INTACK : 8; /*!< Acknowledges the corresponding ctitrigout output. There is one + bit of the register for each ctitrigout output. When a + 1 is written to a bit in this register, the corresponding + ctitrigout is acknowledged, causing it to be cleared. */ + uint32_t : 24; + } bit; + } CTIINTACK; + + union { + __IOM uint32_t reg; /*!< CTI Application Trigger Set Register */ + + struct { + __IOM uint32_t APPSET : 4; /*!< Setting a bit HIGH generates a channel event for the selected + channel. There is one bit of the register for each channel */ + uint32_t : 28; + } bit; + } CTIAPPSET; + + union { + __IOM uint32_t reg; /*!< CTI Application Trigger Clear Register */ + + struct { + __IOM uint32_t APPCLEAR : 4; /*!< Sets the corresponding bits in the CTIAPPSET to 0. There is + one bit of the register for each channel. */ + uint32_t : 28; + } bit; + } CTIAPPCLEAR; + + union { + __IOM uint32_t reg; /*!< CTI Application Pulse Register */ + + struct { + __IOM uint32_t APPULSE : 4; /*!< Setting a bit HIGH generates a channel event pulse for the selected + channel. There is one bit of the register for each channel. */ + uint32_t : 28; + } bit; + } CTIAPPPULSE; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGINEN : 4; /*!< Enables a cross trigger event to the corresponding channel when + a ctitrigin input is activated. There is one bit of the + field for each of the four channels */ + uint32_t : 28; + } bit; + } CTIINEN0; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGINEN : 4; /*!< Enables a cross trigger event to the corresponding channel when + a ctitrigin input is activated. There is one bit of the + field for each of the four channels */ + uint32_t : 28; + } bit; + } CTIINEN1; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGINEN : 4; /*!< Enables a cross trigger event to the corresponding channel when + a ctitrigin input is activated. There is one bit of the + field for each of the four channels */ + uint32_t : 28; + } bit; + } CTIINEN2; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGINEN : 4; /*!< Enables a cross trigger event to the corresponding channel when + a ctitrigin input is activated. There is one bit of the + field for each of the four channels */ + uint32_t : 28; + } bit; + } CTIINEN3; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGINEN : 4; /*!< Enables a cross trigger event to the corresponding channel when + a ctitrigin input is activated. There is one bit of the + field for each of the four channels */ + uint32_t : 28; + } bit; + } CTIINEN4; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGINEN : 4; /*!< Enables a cross trigger event to the corresponding channel when + a ctitrigin input is activated. There is one bit of the + field for each of the four channels */ + uint32_t : 28; + } bit; + } CTIINEN5; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGINEN : 4; /*!< Enables a cross trigger event to the corresponding channel when + a ctitrigin input is activated. There is one bit of the + field for each of the four channels */ + uint32_t : 28; + } bit; + } CTIINEN6; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGINEN : 4; /*!< Enables a cross trigger event to the corresponding channel when + a ctitrigin input is activated. There is one bit of the + field for each of the four channels */ + uint32_t : 28; + } bit; + } CTIINEN7; + __IM uint32_t RESERVED63[24]; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGOUTEN : 4; /*!< Enables a cross trigger event to ctitrigout when the corresponding + channel is activated. There is one bit of the field for + each of the four channels. */ + uint32_t : 28; + } bit; + } CTIOUTEN0; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGOUTEN : 4; /*!< Enables a cross trigger event to ctitrigout when the corresponding + channel is activated. There is one bit of the field for + each of the four channels. */ + uint32_t : 28; + } bit; + } CTIOUTEN1; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGOUTEN : 4; /*!< Enables a cross trigger event to ctitrigout when the corresponding + channel is activated. There is one bit of the field for + each of the four channels. */ + uint32_t : 28; + } bit; + } CTIOUTEN2; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGOUTEN : 4; /*!< Enables a cross trigger event to ctitrigout when the corresponding + channel is activated. There is one bit of the field for + each of the four channels. */ + uint32_t : 28; + } bit; + } CTIOUTEN3; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGOUTEN : 4; /*!< Enables a cross trigger event to ctitrigout when the corresponding + channel is activated. There is one bit of the field for + each of the four channels. */ + uint32_t : 28; + } bit; + } CTIOUTEN4; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGOUTEN : 4; /*!< Enables a cross trigger event to ctitrigout when the corresponding + channel is activated. There is one bit of the field for + each of the four channels. */ + uint32_t : 28; + } bit; + } CTIOUTEN5; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGOUTEN : 4; /*!< Enables a cross trigger event to ctitrigout when the corresponding + channel is activated. There is one bit of the field for + each of the four channels. */ + uint32_t : 28; + } bit; + } CTIOUTEN6; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IOM uint32_t TRIGOUTEN : 4; /*!< Enables a cross trigger event to ctitrigout when the corresponding + channel is activated. There is one bit of the field for + each of the four channels. */ + uint32_t : 28; + } bit; + } CTIOUTEN7; + __IM uint32_t RESERVED64[28]; + + union { + __IOM uint32_t reg; /*!< CTI Trigger to Channel Enable Registers */ + + struct { + __IM uint32_t TRIGINSTATUS : 8; /*!< Shows the status of the ctitrigin inputs. There is one bit of + the field for each trigger input.Because the register provides + a view of the raw ctitrigin inputs, the reset value is + UNKNOWN. */ + uint32_t : 24; + } bit; + } CTITRIGINSTATUS; + + union { + __IOM uint32_t reg; /*!< CTI Trigger In Status Register */ + + struct { + __IM uint32_t TRIGOUTSTATUS : 8; /*!< Shows the status of the ctitrigout outputs. There is one bit + of the field for each trigger output. */ + uint32_t : 24; + } bit; + } CTITRIGOUTSTATUS; + + union { + __IOM uint32_t reg; /*!< CTI Channel In Status Register */ + + struct { + __IM uint32_t CTICHOUTSTATUS : 4; /*!< Shows the status of the ctichout outputs. There is one bit of + the field for each channel output */ + uint32_t : 28; + } bit; + } CTICHINSTATUS; + __IM uint32_t RESERVED65; + + union { + __IOM uint32_t reg; /*!< Enable CTI Channel Gate register */ + + struct { + __IOM uint32_t CTIGATEEN0 : 1; /*!< Enable ctichout0. Set to 0 to disable channel propagation. */ + __IOM uint32_t CTIGATEEN1 : 1; /*!< Enable ctichout1. Set to 0 to disable channel propagation. */ + __IOM uint32_t CTIGATEEN2 : 1; /*!< Enable ctichout2. Set to 0 to disable channel propagation. */ + __IOM uint32_t CTIGATEEN3 : 1; /*!< Enable ctichout3. Set to 0 to disable channel propagation. */ + uint32_t : 28; + } bit; + } CTIGATE; + + union { + __IOM uint32_t reg; /*!< External Multiplexer Control register */ + + struct { + __IOM uint32_t ASICCTL : 32; /*!< ASICCTL */ + } bit; + } ASICCTL; + __IM uint32_t RESERVED66[871]; + + union { + __IOM uint32_t reg; /*!< Integration Test Channel Output register */ + + struct { + __IOM uint32_t CTCHOUT : 4; /*!< Sets the value of the ctichout outputs */ + uint32_t : 28; + } bit; + } ITCHOUT; + + union { + __IOM uint32_t reg; /*!< Integration Test Trigger Output register */ + + struct { + __IOM uint32_t CTTRIGOUT : 8; /*!< Sets the value of the ctitrigout outputs */ + uint32_t : 24; + } bit; + } ITTRIGOUT; + __IM uint32_t RESERVED67[2]; + + union { + __IOM uint32_t reg; /*!< Integration Test Channel Input register */ + + struct { + __IM uint32_t CTCHIN : 4; /*!< Reads the value of the ctichin inputs. */ + uint32_t : 28; + } bit; + } ITCHIN; + __IM uint32_t RESERVED68[2]; + + union { + __IOM uint32_t reg; /*!< Integration Mode Control register */ + + struct { + __IOM uint32_t IME : 1; /*!< Integration Mode Enable */ + uint32_t : 31; + } bit; + } ITCTRL; + __IM uint32_t RESERVED69[46]; + + union { + __IOM uint32_t reg; /*!< Device Architecture register */ + + struct { + __IM uint32_t ARCHID : 16; /*!< Indicates the component */ + __IM uint32_t REVISION : 4; /*!< Indicates the architecture revision */ + __IM uint32_t PRESENT : 1; /*!< Indicates whether the DEVARCH register is present */ + __IM uint32_t ARCHITECT : 11; /*!< Indicates the component architect */ + } bit; + } DEVARCH; + __IM uint32_t RESERVED70[2]; + + union { + __IOM uint32_t reg; /*!< Device Configuration register */ + + struct { + __IM uint32_t EXTMUXNUM : 5; /*!< Indicates the number of multiplexers available on Trigger Inputs + and Trigger Outputs that are using asicctl. The default + value of 0b00000 indicates that no multiplexing is present. + This value of this bit depends on the Verilog define EXTMUXNUM + that you must change accordingly. */ + uint32_t : 3; + __IM uint32_t NUMTRIG : 8; /*!< Number of ECT triggers available. */ + __IM uint32_t NUMCH : 4; /*!< Number of ECT channels available */ + uint32_t : 12; + } bit; + } DEVID; + + union { + __IOM uint32_t reg; /*!< Device Type Identifier register */ + + struct { + __IM uint32_t MAJOR : 4; /*!< Major classification of the type of the debug component as specified + in the ARM Architecture Specification for this debug and + trace component. */ + __IM uint32_t SUB : 4; /*!< Sub-classification of the type of the debug component as specified + in the ARM Architecture Specification within the major + classification as specified in the MAJOR field. */ + uint32_t : 24; + } bit; + } DEVTYPE; + + union { + __IOM uint32_t reg; /*!< CoreSight Peripheral ID4 */ + + struct { + __IM uint32_t DES_2 : 4; /*!< Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify + the designer of the component. */ + __IM uint32_t SIZE : 4; /*!< Always 0b0000. Indicates that the device only occupies 4KB of + memory */ + uint32_t : 24; + } bit; + } PIDR4; + + union { + __IOM uint32_t reg; /*!< CoreSight Peripheral ID5 */ + + struct { + __IOM uint32_t PIDR5 : 32; /*!< PIDR5 */ + } bit; + } PIDR5; + + union { + __IOM uint32_t reg; /*!< CoreSight Peripheral ID6 */ + + struct { + __IOM uint32_t PIDR6 : 32; /*!< PIDR6 */ + } bit; + } PIDR6; + + union { + __IOM uint32_t reg; /*!< CoreSight Peripheral ID7 */ + + struct { + __IOM uint32_t PIDR7 : 32; /*!< PIDR7 */ + } bit; + } PIDR7; + + union { + __IOM uint32_t reg; /*!< CoreSight Peripheral ID0 */ + + struct { + __IM uint32_t PART_0 : 8; /*!< Bits[7:0] of the 12-bit part number of the component. The designer + of the component assigns this part number. */ + uint32_t : 24; + } bit; + } PIDR0; + + union { + __IOM uint32_t reg; /*!< CoreSight Peripheral ID1 */ + + struct { + __IM uint32_t PART_1 : 4; /*!< Bits[11:8] of the 12-bit part number of the component. The designer + of the component assigns this part number. */ + __IM uint32_t DES_0 : 4; /*!< Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify + the designer of the component. */ + uint32_t : 24; + } bit; + } PIDR1; + + union { + __IOM uint32_t reg; /*!< CoreSight Peripheral ID2 */ + + struct { + __IM uint32_t DES_1 : 3; /*!< Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify + the designer of the component. */ + __IM uint32_t JEDEC : 1; /*!< Always 1. Indicates that the JEDEC-assigned designer ID is used. */ + __IM uint32_t REVISION : 4; /*!< This device is at r1p0 */ + uint32_t : 24; + } bit; + } PIDR2; + + union { + __IOM uint32_t reg; /*!< CoreSight Peripheral ID3 */ + + struct { + __IM uint32_t CMOD : 4; /*!< Customer Modified. Indicates whether the customer has modified + the behavior of the component. In most cases, this field + is 0b0000. Customers change this value when they make authorized + modifications to this component. */ + __IM uint32_t REVAND : 4; /*!< Indicates minor errata fixes specific to the revision of the + component being used, for example metal fixes after implementation. + In most cases, this field is 0b0000. ARM recommends that + the component designers ensure that a metal fix can change + this field if required, for example, by driving it from + registers that reset to 0b0000. */ + uint32_t : 24; + } bit; + } PIDR3; + + union { + __IOM uint32_t reg; /*!< CoreSight Component ID0 */ + + struct { + __IM uint32_t PRMBL_0 : 8; /*!< Preamble[0]. Contains bits[7:0] of the component identification + code */ + uint32_t : 24; + } bit; + } CIDR0; + + union { + __IOM uint32_t reg; /*!< CoreSight Component ID1 */ + + struct { + __IM uint32_t PRMBL_1 : 4; /*!< Preamble[1]. Contains bits[11:8] of the component identification + code. */ + __IM uint32_t CLASS : 4; /*!< Class of the component, for example, whether the component is + a ROM table or a generic CoreSight component. Contains + bits[15:12] of the component identification code. */ + uint32_t : 24; + } bit; + } CIDR1; + + union { + __IOM uint32_t reg; /*!< CoreSight Component ID2 */ + + struct { + __IM uint32_t PRMBL_2 : 8; /*!< Preamble[2]. Contains bits[23:16] of the component identification + code. */ + uint32_t : 24; + } bit; + } CIDR2; + + union { + __IOM uint32_t reg; /*!< CoreSight Component ID3 */ + + struct { + __IM uint32_t PRMBL_3 : 8; /*!< Preamble[3]. Contains bits[31:24] of the component identification + code. */ + uint32_t : 24; + } bit; + } CIDR3; +} PPB_Type; /*!< Size = 274432 (0x43000) */ + + + +/* =========================================================================================================================== */ +/* ================ QMI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPI Memory Interface. + + Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. (QMI) + */ + +typedef struct { /*!< QMI Structure */ + + union { + __IOM uint32_t reg; /*!< Control and status for direct serial mode Direct serial mode + allows the processor to send and receive raw serial frames, + for programming, configuration and control of the external + memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable direct mode. In direct mode, software controls the chip + select lines, and can perform direct SPI transfers by pushing + data to the DIRECT_TX FIFO, and popping the same amount + of data from the DIRECT_RX FIFO. Memory-mapped accesses + will generate bus errors when direct serial mode is enabled. */ + __IM uint32_t BUSY : 1; /*!< Direct mode busy flag. If 1, data is currently being shifted + in/out (or would be if the interface were not stalled on + the RX FIFO), and the chip select must not yet be deasserted. + The busy flag will also be set to 1 if a memory-mapped + transfer is still in progress when direct mode is enabled. + Direct mode blocks new memory-mapped transfers, but can't + halt a transfer that is already in progress. If there is + a chance that memory-mapped transfers may be in progress, + the busy flag should be polled for 0 before asserting the + chip select. (In practice you will usually discover this + timing condition through other means, because any subsequent + memory-mapped transfers when direct mode is enabled will + return bus errors, which are difficult to ignore.) */ + __IOM uint32_t ASSERT_CS0N : 1; /*!< When 1, assert (i.e. drive low) the CS0n chip select line. Note + that this applies even when DIRECT_CSR_EN is 0. */ + __IOM uint32_t ASSERT_CS1N : 1; /*!< When 1, assert (i.e. drive low) the CS1n chip select line. Note + that this applies even when DIRECT_CSR_EN is 0. */ + uint32_t : 2; + __IOM uint32_t AUTO_CS0N : 1; /*!< When 1, automatically assert the CS0n chip select line whenever + the BUSY flag is set. */ + __IOM uint32_t AUTO_CS1N : 1; /*!< When 1, automatically assert the CS1n chip select line whenever + the BUSY flag is set. */ + uint32_t : 2; + __IM uint32_t TXFULL : 1; /*!< When 1, the DIRECT_TX FIFO is currently full. If the processor + tries to write more data, that data will be ignored. */ + __IM uint32_t TXEMPTY : 1; /*!< When 1, the DIRECT_TX FIFO is currently empty. Unless the processor + pushes more data, transmission will stop and BUSY will + go low once the current 8-bit serial frame completes. */ + __IM uint32_t TXLEVEL : 3; /*!< Current level of DIRECT_TX FIFO */ + uint32_t : 1; + __IM uint32_t RXEMPTY : 1; /*!< When 1, the DIRECT_RX FIFO is currently empty. If the processor + attempts to read more data, the FIFO state is not affected, + but the value returned to the processor is undefined. */ + __IM uint32_t RXFULL : 1; /*!< When 1, the DIRECT_RX FIFO is currently full. The serial interface + will be stalled until data is popped; the interface will + not begin a new serial frame when the DIRECT_TX FIFO is + empty or the DIRECT_RX FIFO is full. */ + __IM uint32_t RXLEVEL : 3; /*!< Current level of DIRECT_RX FIFO */ + uint32_t : 1; + __IOM uint32_t CLKDIV : 8; /*!< Clock divisor for direct serial mode. Divisors of 1..255 are + encoded directly, and the maximum divisor of 256 is encoded + by a value of CLKDIV=0. The clock divisor can be changed + on-the-fly by software, without halting or otherwise coordinating + with the serial interface. The serial interface will sample + the latest clock divisor each time it begins the transmission + of a new byte. */ + __IOM uint32_t RXDELAY : 2; /*!< Delay the read data sample timing, in units of one half of a + system clock cycle. (Not necessarily half of an SCK cycle.) */ + } bit; + } DIRECT_CSR; + + union { + __IOM uint32_t reg; /*!< Transmit FIFO for direct mode */ + + struct { + __OM uint32_t DATA : 16; /*!< Data pushed here will be clocked out falling edges of SCK (or + before the very first rising edge of SCK, if this is the + first pulse). For each byte clocked out, the interface + will simultaneously sample one byte, on rising edges of + SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, + the least-significant byte is transmitted first. */ + __OM uint32_t IWIDTH : 2; /*!< Configure whether this FIFO record is transferred with single/dual/quad + interface width (0/1/2). Different widths can be mixed + freely. */ + __OM uint32_t DWIDTH : 1; /*!< Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX + DATA field, and return an 8-bit value in the 8 LSBs of + DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and + 16-bit transfers can be mixed freely. */ + __OM uint32_t OE : 1; /*!< Output enable (active-high). For single width (SPI), this field + is ignored, and SD0 is always set to output, with SD1 always + set to input. For dual and quad width (DSPI/QSPI), this + sets whether the relevant SDx pads are set to output whilst + transferring this FIFO record. In this case the command/address + should have OE set, and the data transfer should have OE + set or clear depending on the direction of the transfer. */ + __OM uint32_t NOPUSH : 1; /*!< Inhibit the RX FIFO push that would correspond to this TX FIFO + entry. Useful to avoid garbage appearing in the RX FIFO + when pushing the command at the beginning of a SPI transfer. */ + uint32_t : 11; + } bit; + } DIRECT_TX; + + union { + __IOM uint32_t reg; /*!< Receive FIFO for direct mode */ + + struct { + __IM uint32_t DIRECT_RX : 16; /*!< With each byte clocked out on the serial interface, one byte + will simultaneously be clocked in, and will appear in this + FIFO. The serial interface will stall when this FIFO is + full, to avoid dropping data. When 16-bit data is pushed + into the TX FIFO, the corresponding RX FIFO push will also + contain 16 bits of data. The least-significant byte is + the first one received. */ + uint32_t : 16; + } bit; + } DIRECT_RX; + + union { + __IOM uint32_t reg; /*!< Timing configuration register for memory address window 0. */ + + struct { + __IOM uint32_t CLKDIV : 8; /*!< Clock divisor. Odd and even divisors are supported. Defines + the SCK clock period in units of 1 system clock cycle. + Divisors 1..255 are encoded directly, and a divisor of + 256 is encoded with a value of CLKDIV=0. The clock divisor + can be changed on-the-fly, even when the QMI is currently + accessing memory in this address window. All other parameters + must only be changed when the QMI is idle. If software + is increasing CLKDIV in anticipation of an increase in + the system clock frequency, a dummy access to either memory + window (and appropriate processor barriers/fences) must + be inserted after the Mx_TIMING write to ensure the SCK + divisor change is in effect _before_ the system clock is + changed. */ + __IOM uint32_t RXDELAY : 3; /*!< Delay the read data sample timing, in units of one half of a + system clock cycle. (Not necessarily half of an SCK cycle.) + An RXDELAY of 0 means the sample is captured at the SDI + input registers simultaneously with the rising edge of + SCK launched from the SCK output register. At higher SCK + frequencies, RXDELAY may need to be increased to account + for the round trip delay of the pads, and the clock-to-Q + delay of the QSPI memory device. */ + uint32_t : 1; + __IOM uint32_t MIN_DESELECT : 5; /*!< After this window's chip select is deasserted, it remains deasserted + for half an SCK cycle (rounded up to an integer number + of system clock cycles), plus MIN_DESELECT additional system + clock cycles, before the QMI reasserts either chip select + pin. Nonzero values may be required for PSRAM devices which + enforce a longer minimum CS deselect time, so that they + can perform internal DRAM refresh cycles whilst deselected. */ + __IOM uint32_t MAX_SELECT : 6; /*!< Enforce a maximum assertion duration for this window's chip + select, in units of 64 system clock cycles. If 0, the QMI + is permitted to keep the chip select asserted indefinitely + when servicing sequential memory accesses (see COOLDOWN). + This feature is required to meet timing constraints of + PSRAM devices, which specify a maximum chip select assertion + so they can perform DRAM refresh cycles. See also MIN_DESELECT, + which can enforce a minimum deselect time. If a memory + access is in progress at the time MAX_SELECT is reached, + the QMI will wait for the access to complete before deasserting + the chip select. This additional time must be accounted + for to calculate a safe MAX_SELECT value. In the worst + case, this may be a fully-formed serial transfer, including + command prefix and address, with a data payload as large + as one cache line. */ + __IOM uint32_t SELECT_HOLD : 2; /*!< Add up to three additional system clock cycles of active hold + between the last falling edge of SCK and the deassertion + of this window's chip select. The default hold time is + one system clock cycle. Note that flash datasheets usually + give chip select active hold time from the last *rising* + edge of SCK, and so even zero hold from the last falling + edge would be safe. Note that this is a minimum hold time + guaranteed by the QMI: the actual chip select active hold + may be slightly longer for read transfers with low clock + divisors and/or high sample delays. Specifically, if the + point two cycles after the last RX data sample is later + than the last SCK falling edge, then the hold time is measured + from *this* point. Note also that, in case the final SCK + pulse is masked to save energy (true for non-DTR reads + when COOLDOWN is disabled or PAGE_BREAK is reached), all + of QMI's timing logic behaves as though the clock pulse + were still present. The SELECT_HOLD time is applied from + the point where the last SCK falling edge would be if the + clock pulse were not masked. */ + __IOM uint32_t SELECT_SETUP : 1; /*!< Add up to one additional system clock cycle of setup between + chip select assertion and the first rising edge of SCK. + The default setup time is one half SCK period, which is + usually sufficient except for very high SCK frequencies + with some flash devices. */ + uint32_t : 2; + __IOM uint32_t PAGEBREAK : 2; /*!< When page break is enabled, chip select will automatically deassert + when crossing certain power-of-2-aligned address boundaries. + The next access will always begin a new read/write SPI + burst, even if the address of the next access follows in + sequence with the last access before the page boundary. + Some flash and PSRAM devices forbid crossing page boundaries + with a single read/write transfer, or restrict the operating + frequency for transfers that do cross page a boundary. + This option allows the QMI to safely support those devices. + This field has no effect when COOLDOWN is disabled. */ + __IOM uint32_t COOLDOWN : 2; /*!< Chip select cooldown period. When a memory transfer finishes, + the chip select remains asserted for 64 x COOLDOWN system + clock cycles, plus half an SCK clock period (rounded up + for odd SCK divisors). After this cooldown expires, the + chip select is always deasserted to save power. If the + next memory access arrives within the cooldown period, + the QMI may be able to append more SCK cycles to the currently + ongoing SPI transfer, rather than starting a new transfer. + This reduces access latency and increases bus throughput. + Specifically, the next access must be in the same direction + (read/write), access the same memory window (chip select + 0/1), and follow sequentially the address of the last transfer. + If any of these are false, the new access will first deassert + the chip select, then begin a new transfer. If COOLDOWN + is 0, the address alignment configured by PAGEBREAK has + been reached, or the total chip select assertion limit + MAX_SELECT has been reached, the cooldown period is skipped, + and the chip select will always be deasserted one half + SCK period after the transfer finishes. */ + } bit; + } M0_TIMING; + + union { + __IOM uint32_t reg; /*!< Read transfer format configuration for memory address window + 0. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M0_RFMT register is configured to support a basic 03h serial + read transfer with no additional configuration. */ + + struct { + __IOM uint32_t PREFIX_WIDTH : 2; /*!< The transfer width used for the command prefix, if any */ + __IOM uint32_t ADDR_WIDTH : 2; /*!< The transfer width used for the address. The address phase always + transfers 24 bits in total. */ + __IOM uint32_t SUFFIX_WIDTH : 2; /*!< The width used for the post-address command suffix, if any */ + __IOM uint32_t DUMMY_WIDTH : 2; /*!< The width used for the dummy phase, if any. If width is single, + SD0/MOSI is held asserted low during the dummy phase, and + SD1...SD3 are tristated. If width is dual/quad, all IOs + are tristated during the dummy phase. */ + __IOM uint32_t DATA_WIDTH : 2; /*!< The width used for the data transfer */ + uint32_t : 2; + __IOM uint32_t PREFIX_LEN : 1; /*!< Length of command prefix, in units of 8 bits. (i.e. 2 cycles + for quad width, 4 for dual, 8 for single) */ + uint32_t : 1; + __IOM uint32_t SUFFIX_LEN : 2; /*!< Length of post-address command suffix, in units of 4 bits. (i.e. + 1 cycle for quad width, 2 for dual, 4 for single) Only + values of 0 and 8 bits are supported. */ + __IOM uint32_t DUMMY_LEN : 3; /*!< Length of dummy phase between command suffix and data phase, + in units of 4 bits. (i.e. 1 cycle for quad width, 2 for + dual, 4 for single) */ + uint32_t : 9; + __IOM uint32_t DTR : 1; /*!< Enable double transfer rate (DTR) for read commands: address, + suffix and read data phases are active on both edges of + SCK. SDO data is launched centre-aligned on each SCK edge, + and SDI data is captured on the SCK edge that follows its + launch. DTR is implemented by halving the clock rate; SCK + has a period of 2 x CLK_DIV throughout the transfer. The + prefix and dummy phases are still single transfer rate. + If the suffix is quad-width, it must be 0 or 8 bits in + length, to ensure an even number of SCK edges. */ + uint32_t : 3; + } bit; + } M0_RFMT; + + union { + __IOM uint32_t reg; /*!< Command constants used for reads from memory address window + 0. The reset value of the M0_RCMD register is configured + to support a basic 03h serial read transfer with no additional + configuration. */ + + struct { + __IOM uint32_t PREFIX : 8; /*!< The command prefix bits to prepend on each new transfer, if + Mx_RFMT_PREFIX_LEN is nonzero. */ + __IOM uint32_t SUFFIX : 8; /*!< The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN + is nonzero. */ + uint32_t : 16; + } bit; + } M0_RCMD; + + union { + __IOM uint32_t reg; /*!< Write transfer format configuration for memory address window + 0. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M0_WFMT register is configured to support a basic 02h serial + write transfer. However, writes to this window must first + be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory + is read-only by default. */ + + struct { + __IOM uint32_t PREFIX_WIDTH : 2; /*!< The transfer width used for the command prefix, if any */ + __IOM uint32_t ADDR_WIDTH : 2; /*!< The transfer width used for the address. The address phase always + transfers 24 bits in total. */ + __IOM uint32_t SUFFIX_WIDTH : 2; /*!< The width used for the post-address command suffix, if any */ + __IOM uint32_t DUMMY_WIDTH : 2; /*!< The width used for the dummy phase, if any. If width is single, + SD0/MOSI is held asserted low during the dummy phase, and + SD1...SD3 are tristated. If width is dual/quad, all IOs + are tristated during the dummy phase. */ + __IOM uint32_t DATA_WIDTH : 2; /*!< The width used for the data transfer */ + uint32_t : 2; + __IOM uint32_t PREFIX_LEN : 1; /*!< Length of command prefix, in units of 8 bits. (i.e. 2 cycles + for quad width, 4 for dual, 8 for single) */ + uint32_t : 1; + __IOM uint32_t SUFFIX_LEN : 2; /*!< Length of post-address command suffix, in units of 4 bits. (i.e. + 1 cycle for quad width, 2 for dual, 4 for single) Only + values of 0 and 8 bits are supported. */ + __IOM uint32_t DUMMY_LEN : 3; /*!< Length of dummy phase between command suffix and data phase, + in units of 4 bits. (i.e. 1 cycle for quad width, 2 for + dual, 4 for single) */ + uint32_t : 9; + __IOM uint32_t DTR : 1; /*!< Enable double transfer rate (DTR) for write commands: address, + suffix and write data phases are active on both edges of + SCK. SDO data is launched centre-aligned on each SCK edge, + and SDI data is captured on the SCK edge that follows its + launch. DTR is implemented by halving the clock rate; SCK + has a period of 2 x CLK_DIV throughout the transfer. The + prefix and dummy phases are still single transfer rate. + If the suffix is quad-width, it must be 0 or 8 bits in + length, to ensure an even number of SCK edges. */ + uint32_t : 3; + } bit; + } M0_WFMT; + + union { + __IOM uint32_t reg; /*!< Command constants used for writes to memory address window 0. + The reset value of the M0_WCMD register is configured to + support a basic 02h serial write transfer with no additional + configuration. */ + + struct { + __IOM uint32_t PREFIX : 8; /*!< The command prefix bits to prepend on each new transfer, if + Mx_WFMT_PREFIX_LEN is nonzero. */ + __IOM uint32_t SUFFIX : 8; /*!< The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN + is nonzero. */ + uint32_t : 16; + } bit; + } M0_WCMD; + + union { + __IOM uint32_t reg; /*!< Timing configuration register for memory address window 1. */ + + struct { + __IOM uint32_t CLKDIV : 8; /*!< Clock divisor. Odd and even divisors are supported. Defines + the SCK clock period in units of 1 system clock cycle. + Divisors 1..255 are encoded directly, and a divisor of + 256 is encoded with a value of CLKDIV=0. The clock divisor + can be changed on-the-fly, even when the QMI is currently + accessing memory in this address window. All other parameters + must only be changed when the QMI is idle. If software + is increasing CLKDIV in anticipation of an increase in + the system clock frequency, a dummy access to either memory + window (and appropriate processor barriers/fences) must + be inserted after the Mx_TIMING write to ensure the SCK + divisor change is in effect _before_ the system clock is + changed. */ + __IOM uint32_t RXDELAY : 3; /*!< Delay the read data sample timing, in units of one half of a + system clock cycle. (Not necessarily half of an SCK cycle.) + An RXDELAY of 0 means the sample is captured at the SDI + input registers simultaneously with the rising edge of + SCK launched from the SCK output register. At higher SCK + frequencies, RXDELAY may need to be increased to account + for the round trip delay of the pads, and the clock-to-Q + delay of the QSPI memory device. */ + uint32_t : 1; + __IOM uint32_t MIN_DESELECT : 5; /*!< After this window's chip select is deasserted, it remains deasserted + for half an SCK cycle (rounded up to an integer number + of system clock cycles), plus MIN_DESELECT additional system + clock cycles, before the QMI reasserts either chip select + pin. Nonzero values may be required for PSRAM devices which + enforce a longer minimum CS deselect time, so that they + can perform internal DRAM refresh cycles whilst deselected. */ + __IOM uint32_t MAX_SELECT : 6; /*!< Enforce a maximum assertion duration for this window's chip + select, in units of 64 system clock cycles. If 0, the QMI + is permitted to keep the chip select asserted indefinitely + when servicing sequential memory accesses (see COOLDOWN). + This feature is required to meet timing constraints of + PSRAM devices, which specify a maximum chip select assertion + so they can perform DRAM refresh cycles. See also MIN_DESELECT, + which can enforce a minimum deselect time. If a memory + access is in progress at the time MAX_SELECT is reached, + the QMI will wait for the access to complete before deasserting + the chip select. This additional time must be accounted + for to calculate a safe MAX_SELECT value. In the worst + case, this may be a fully-formed serial transfer, including + command prefix and address, with a data payload as large + as one cache line. */ + __IOM uint32_t SELECT_HOLD : 2; /*!< Add up to three additional system clock cycles of active hold + between the last falling edge of SCK and the deassertion + of this window's chip select. The default hold time is + one system clock cycle. Note that flash datasheets usually + give chip select active hold time from the last *rising* + edge of SCK, and so even zero hold from the last falling + edge would be safe. Note that this is a minimum hold time + guaranteed by the QMI: the actual chip select active hold + may be slightly longer for read transfers with low clock + divisors and/or high sample delays. Specifically, if the + point two cycles after the last RX data sample is later + than the last SCK falling edge, then the hold time is measured + from *this* point. Note also that, in case the final SCK + pulse is masked to save energy (true for non-DTR reads + when COOLDOWN is disabled or PAGE_BREAK is reached), all + of QMI's timing logic behaves as though the clock pulse + were still present. The SELECT_HOLD time is applied from + the point where the last SCK falling edge would be if the + clock pulse were not masked. */ + __IOM uint32_t SELECT_SETUP : 1; /*!< Add up to one additional system clock cycle of setup between + chip select assertion and the first rising edge of SCK. + The default setup time is one half SCK period, which is + usually sufficient except for very high SCK frequencies + with some flash devices. */ + uint32_t : 2; + __IOM uint32_t PAGEBREAK : 2; /*!< When page break is enabled, chip select will automatically deassert + when crossing certain power-of-2-aligned address boundaries. + The next access will always begin a new read/write SPI + burst, even if the address of the next access follows in + sequence with the last access before the page boundary. + Some flash and PSRAM devices forbid crossing page boundaries + with a single read/write transfer, or restrict the operating + frequency for transfers that do cross page a boundary. + This option allows the QMI to safely support those devices. + This field has no effect when COOLDOWN is disabled. */ + __IOM uint32_t COOLDOWN : 2; /*!< Chip select cooldown period. When a memory transfer finishes, + the chip select remains asserted for 64 x COOLDOWN system + clock cycles, plus half an SCK clock period (rounded up + for odd SCK divisors). After this cooldown expires, the + chip select is always deasserted to save power. If the + next memory access arrives within the cooldown period, + the QMI may be able to append more SCK cycles to the currently + ongoing SPI transfer, rather than starting a new transfer. + This reduces access latency and increases bus throughput. + Specifically, the next access must be in the same direction + (read/write), access the same memory window (chip select + 0/1), and follow sequentially the address of the last transfer. + If any of these are false, the new access will first deassert + the chip select, then begin a new transfer. If COOLDOWN + is 0, the address alignment configured by PAGEBREAK has + been reached, or the total chip select assertion limit + MAX_SELECT has been reached, the cooldown period is skipped, + and the chip select will always be deasserted one half + SCK period after the transfer finishes. */ + } bit; + } M1_TIMING; + + union { + __IOM uint32_t reg; /*!< Read transfer format configuration for memory address window + 1. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M1_RFMT register is configured to support a basic 03h serial + read transfer with no additional configuration. */ + + struct { + __IOM uint32_t PREFIX_WIDTH : 2; /*!< The transfer width used for the command prefix, if any */ + __IOM uint32_t ADDR_WIDTH : 2; /*!< The transfer width used for the address. The address phase always + transfers 24 bits in total. */ + __IOM uint32_t SUFFIX_WIDTH : 2; /*!< The width used for the post-address command suffix, if any */ + __IOM uint32_t DUMMY_WIDTH : 2; /*!< The width used for the dummy phase, if any. If width is single, + SD0/MOSI is held asserted low during the dummy phase, and + SD1...SD3 are tristated. If width is dual/quad, all IOs + are tristated during the dummy phase. */ + __IOM uint32_t DATA_WIDTH : 2; /*!< The width used for the data transfer */ + uint32_t : 2; + __IOM uint32_t PREFIX_LEN : 1; /*!< Length of command prefix, in units of 8 bits. (i.e. 2 cycles + for quad width, 4 for dual, 8 for single) */ + uint32_t : 1; + __IOM uint32_t SUFFIX_LEN : 2; /*!< Length of post-address command suffix, in units of 4 bits. (i.e. + 1 cycle for quad width, 2 for dual, 4 for single) Only + values of 0 and 8 bits are supported. */ + __IOM uint32_t DUMMY_LEN : 3; /*!< Length of dummy phase between command suffix and data phase, + in units of 4 bits. (i.e. 1 cycle for quad width, 2 for + dual, 4 for single) */ + uint32_t : 9; + __IOM uint32_t DTR : 1; /*!< Enable double transfer rate (DTR) for read commands: address, + suffix and read data phases are active on both edges of + SCK. SDO data is launched centre-aligned on each SCK edge, + and SDI data is captured on the SCK edge that follows its + launch. DTR is implemented by halving the clock rate; SCK + has a period of 2 x CLK_DIV throughout the transfer. The + prefix and dummy phases are still single transfer rate. + If the suffix is quad-width, it must be 0 or 8 bits in + length, to ensure an even number of SCK edges. */ + uint32_t : 3; + } bit; + } M1_RFMT; + + union { + __IOM uint32_t reg; /*!< Command constants used for reads from memory address window + 1. The reset value of the M1_RCMD register is configured + to support a basic 03h serial read transfer with no additional + configuration. */ + + struct { + __IOM uint32_t PREFIX : 8; /*!< The command prefix bits to prepend on each new transfer, if + Mx_RFMT_PREFIX_LEN is nonzero. */ + __IOM uint32_t SUFFIX : 8; /*!< The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN + is nonzero. */ + uint32_t : 16; + } bit; + } M1_RCMD; + + union { + __IOM uint32_t reg; /*!< Write transfer format configuration for memory address window + 1. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M1_WFMT register is configured to support a basic 02h serial + write transfer. However, writes to this window must first + be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory + is read-only by default. */ + + struct { + __IOM uint32_t PREFIX_WIDTH : 2; /*!< The transfer width used for the command prefix, if any */ + __IOM uint32_t ADDR_WIDTH : 2; /*!< The transfer width used for the address. The address phase always + transfers 24 bits in total. */ + __IOM uint32_t SUFFIX_WIDTH : 2; /*!< The width used for the post-address command suffix, if any */ + __IOM uint32_t DUMMY_WIDTH : 2; /*!< The width used for the dummy phase, if any. If width is single, + SD0/MOSI is held asserted low during the dummy phase, and + SD1...SD3 are tristated. If width is dual/quad, all IOs + are tristated during the dummy phase. */ + __IOM uint32_t DATA_WIDTH : 2; /*!< The width used for the data transfer */ + uint32_t : 2; + __IOM uint32_t PREFIX_LEN : 1; /*!< Length of command prefix, in units of 8 bits. (i.e. 2 cycles + for quad width, 4 for dual, 8 for single) */ + uint32_t : 1; + __IOM uint32_t SUFFIX_LEN : 2; /*!< Length of post-address command suffix, in units of 4 bits. (i.e. + 1 cycle for quad width, 2 for dual, 4 for single) Only + values of 0 and 8 bits are supported. */ + __IOM uint32_t DUMMY_LEN : 3; /*!< Length of dummy phase between command suffix and data phase, + in units of 4 bits. (i.e. 1 cycle for quad width, 2 for + dual, 4 for single) */ + uint32_t : 9; + __IOM uint32_t DTR : 1; /*!< Enable double transfer rate (DTR) for write commands: address, + suffix and write data phases are active on both edges of + SCK. SDO data is launched centre-aligned on each SCK edge, + and SDI data is captured on the SCK edge that follows its + launch. DTR is implemented by halving the clock rate; SCK + has a period of 2 x CLK_DIV throughout the transfer. The + prefix and dummy phases are still single transfer rate. + If the suffix is quad-width, it must be 0 or 8 bits in + length, to ensure an even number of SCK edges. */ + uint32_t : 3; + } bit; + } M1_WFMT; + + union { + __IOM uint32_t reg; /*!< Command constants used for writes to memory address window 1. + The reset value of the M1_WCMD register is configured to + support a basic 02h serial write transfer with no additional + configuration. */ + + struct { + __IOM uint32_t PREFIX : 8; /*!< The command prefix bits to prepend on each new transfer, if + Mx_WFMT_PREFIX_LEN is nonzero. */ + __IOM uint32_t SUFFIX : 8; /*!< The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN + is nonzero. */ + uint32_t : 16; + } bit; + } M1_WCMD; + + union { + __IOM uint32_t reg; /*!< Configure address translation for XIP virtual addresses 0x000000 + through 0x3fffff (a 4 MiB window starting at +0 MiB). Address + translation allows a program image to be executed in place + at multiple physical flash addresses (for example, a double-buffered + flash image for over-the-air updates), without the overhead + of position-independent code. At reset, the address translation + registers are initialised to an identity mapping, so that + they can be ignored if address translation is not required. + Note that the XIP cache is fully virtually addressed, so + a cache flush is required after changing the address translation. */ + + struct { + __IOM uint32_t BASE : 12; /*!< Physical address base for this virtual address range, in units + of 4 kiB (one flash sector). Taking a 24-bit virtual address, + firstly bits 23:22 (the two MSBs) are masked to zero, and + then BASE is added to bits 23:12 (the upper 12 bits) to + form the physical address. Translation wraps on a 16 MiB + boundary. */ + uint32_t : 4; + __IOM uint32_t SIZE : 11; /*!< Translation aperture size for this virtual address range, in + units of 4 kiB (one flash sector). Bits 21:12 of the virtual + address are compared to SIZE. Offsets greater than SIZE + return a bus error, and do not cause a QSPI access. */ + uint32_t : 5; + } bit; + } ATRANS0; + + union { + __IOM uint32_t reg; /*!< Configure address translation for XIP virtual addresses 0x400000 + through 0x7fffff (a 4 MiB window starting at +4 MiB). Address + translation allows a program image to be executed in place + at multiple physical flash addresses (for example, a double-buffered + flash image for over-the-air updates), without the overhead + of position-independent code. At reset, the address translation + registers are initialised to an identity mapping, so that + they can be ignored if address translation is not required. + Note that the XIP cache is fully virtually addressed, so + a cache flush is required after changing the address translation. */ + + struct { + __IOM uint32_t BASE : 12; /*!< Physical address base for this virtual address range, in units + of 4 kiB (one flash sector). Taking a 24-bit virtual address, + firstly bits 23:22 (the two MSBs) are masked to zero, and + then BASE is added to bits 23:12 (the upper 12 bits) to + form the physical address. Translation wraps on a 16 MiB + boundary. */ + uint32_t : 4; + __IOM uint32_t SIZE : 11; /*!< Translation aperture size for this virtual address range, in + units of 4 kiB (one flash sector). Bits 21:12 of the virtual + address are compared to SIZE. Offsets greater than SIZE + return a bus error, and do not cause a QSPI access. */ + uint32_t : 5; + } bit; + } ATRANS1; + + union { + __IOM uint32_t reg; /*!< Configure address translation for XIP virtual addresses 0x800000 + through 0xbfffff (a 4 MiB window starting at +8 MiB). Address + translation allows a program image to be executed in place + at multiple physical flash addresses (for example, a double-buffered + flash image for over-the-air updates), without the overhead + of position-independent code. At reset, the address translation + registers are initialised to an identity mapping, so that + they can be ignored if address translation is not required. + Note that the XIP cache is fully virtually addressed, so + a cache flush is required after changing the address translation. */ + + struct { + __IOM uint32_t BASE : 12; /*!< Physical address base for this virtual address range, in units + of 4 kiB (one flash sector). Taking a 24-bit virtual address, + firstly bits 23:22 (the two MSBs) are masked to zero, and + then BASE is added to bits 23:12 (the upper 12 bits) to + form the physical address. Translation wraps on a 16 MiB + boundary. */ + uint32_t : 4; + __IOM uint32_t SIZE : 11; /*!< Translation aperture size for this virtual address range, in + units of 4 kiB (one flash sector). Bits 21:12 of the virtual + address are compared to SIZE. Offsets greater than SIZE + return a bus error, and do not cause a QSPI access. */ + uint32_t : 5; + } bit; + } ATRANS2; + + union { + __IOM uint32_t reg; /*!< Configure address translation for XIP virtual addresses 0xc00000 + through 0xffffff (a 4 MiB window starting at +12 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + + struct { + __IOM uint32_t BASE : 12; /*!< Physical address base for this virtual address range, in units + of 4 kiB (one flash sector). Taking a 24-bit virtual address, + firstly bits 23:22 (the two MSBs) are masked to zero, and + then BASE is added to bits 23:12 (the upper 12 bits) to + form the physical address. Translation wraps on a 16 MiB + boundary. */ + uint32_t : 4; + __IOM uint32_t SIZE : 11; /*!< Translation aperture size for this virtual address range, in + units of 4 kiB (one flash sector). Bits 21:12 of the virtual + address are compared to SIZE. Offsets greater than SIZE + return a bus error, and do not cause a QSPI access. */ + uint32_t : 5; + } bit; + } ATRANS3; + + union { + __IOM uint32_t reg; /*!< Configure address translation for XIP virtual addresses 0x1000000 + through 0x13fffff (a 4 MiB window starting at +16 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + + struct { + __IOM uint32_t BASE : 12; /*!< Physical address base for this virtual address range, in units + of 4 kiB (one flash sector). Taking a 24-bit virtual address, + firstly bits 23:22 (the two MSBs) are masked to zero, and + then BASE is added to bits 23:12 (the upper 12 bits) to + form the physical address. Translation wraps on a 16 MiB + boundary. */ + uint32_t : 4; + __IOM uint32_t SIZE : 11; /*!< Translation aperture size for this virtual address range, in + units of 4 kiB (one flash sector). Bits 21:12 of the virtual + address are compared to SIZE. Offsets greater than SIZE + return a bus error, and do not cause a QSPI access. */ + uint32_t : 5; + } bit; + } ATRANS4; + + union { + __IOM uint32_t reg; /*!< Configure address translation for XIP virtual addresses 0x1400000 + through 0x17fffff (a 4 MiB window starting at +20 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + + struct { + __IOM uint32_t BASE : 12; /*!< Physical address base for this virtual address range, in units + of 4 kiB (one flash sector). Taking a 24-bit virtual address, + firstly bits 23:22 (the two MSBs) are masked to zero, and + then BASE is added to bits 23:12 (the upper 12 bits) to + form the physical address. Translation wraps on a 16 MiB + boundary. */ + uint32_t : 4; + __IOM uint32_t SIZE : 11; /*!< Translation aperture size for this virtual address range, in + units of 4 kiB (one flash sector). Bits 21:12 of the virtual + address are compared to SIZE. Offsets greater than SIZE + return a bus error, and do not cause a QSPI access. */ + uint32_t : 5; + } bit; + } ATRANS5; + + union { + __IOM uint32_t reg; /*!< Configure address translation for XIP virtual addresses 0x1800000 + through 0x1bfffff (a 4 MiB window starting at +24 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + + struct { + __IOM uint32_t BASE : 12; /*!< Physical address base for this virtual address range, in units + of 4 kiB (one flash sector). Taking a 24-bit virtual address, + firstly bits 23:22 (the two MSBs) are masked to zero, and + then BASE is added to bits 23:12 (the upper 12 bits) to + form the physical address. Translation wraps on a 16 MiB + boundary. */ + uint32_t : 4; + __IOM uint32_t SIZE : 11; /*!< Translation aperture size for this virtual address range, in + units of 4 kiB (one flash sector). Bits 21:12 of the virtual + address are compared to SIZE. Offsets greater than SIZE + return a bus error, and do not cause a QSPI access. */ + uint32_t : 5; + } bit; + } ATRANS6; + + union { + __IOM uint32_t reg; /*!< Configure address translation for XIP virtual addresses 0x1c00000 + through 0x1ffffff (a 4 MiB window starting at +28 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + + struct { + __IOM uint32_t BASE : 12; /*!< Physical address base for this virtual address range, in units + of 4 kiB (one flash sector). Taking a 24-bit virtual address, + firstly bits 23:22 (the two MSBs) are masked to zero, and + then BASE is added to bits 23:12 (the upper 12 bits) to + form the physical address. Translation wraps on a 16 MiB + boundary. */ + uint32_t : 4; + __IOM uint32_t SIZE : 11; /*!< Translation aperture size for this virtual address range, in + units of 4 kiB (one flash sector). Bits 21:12 of the virtual + address are compared to SIZE. Offsets greater than SIZE + return a bus error, and do not cause a QSPI access. */ + uint32_t : 5; + } bit; + } ATRANS7; +} QMI_Type; /*!< Size = 84 (0x54) */ + + + +/* =========================================================================================================================== */ +/* ================ XIP_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPI flash execute-in-place block (XIP_CTRL) + */ + +typedef struct { /*!< XIP_CTRL Structure */ + + union { + __IOM uint32_t reg; /*!< Cache control register. Read-only from a Non-secure context. */ + + struct { + __IOM uint32_t EN_SECURE : 1; /*!< When 1, enable the cache for Secure accesses. When enabled, + Secure XIP accesses to the cached (addr[26] == 0) window + will query the cache, and QSPI accesses are performed only + if the requested data is not present. When disabled, Secure + access ignore the cache contents, and always access the + QSPI interface. Accesses to the uncached (addr[26] == 1) + window will never query the cache, irrespective of this + bit. There is no cache-as-SRAM address window. Cache lines + are allocated for SRAM-like use by individually pinning + them, and keeping the cache enabled. */ + __IOM uint32_t EN_NONSECURE : 1; /*!< When 1, enable the cache for Non-secure accesses. When enabled, + Non-secure XIP accesses to the cached (addr[26] == 0) window + will query the cache, and QSPI accesses are performed only + if the requested data is not present. When disabled, Secure + access ignore the cache contents, and always access the + QSPI interface. Accesses to the uncached (addr[26] == 1) + window will never query the cache, irrespective of this + bit. */ + uint32_t : 1; + __IOM uint32_t POWER_DOWN : 1; /*!< When 1, the cache memories are powered down. They retain state, + but can not be accessed. This reduces static power dissipation. + Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE + to 0, i.e. the cache cannot be enabled when powered down. */ + __IOM uint32_t NO_UNCACHED_SEC : 1; /*!< When 1, Secure accesses to the uncached window (addr[27:26] + == 1) will generate a bus error. This may reduce the number + of SAU/MPU/PMP regions required to protect flash contents. + Note this does not disable access to the uncached, untranslated + window -- see NO_UNTRANSLATED_SEC. */ + __IOM uint32_t NO_UNCACHED_NONSEC : 1; /*!< When 1, Non-secure accesses to the uncached window (addr[27:26] + == 1) will generate a bus error. This may reduce the number + of SAU/MPU/PMP regions required to protect flash contents. + Note this does not disable access to the uncached, untranslated + window -- see NO_UNTRANSLATED_SEC. */ + __IOM uint32_t NO_UNTRANSLATED_SEC : 1; /*!< When 1, Secure accesses to the uncached, untranslated window + (addr[27:26] == 3) will generate a bus error. */ + __IOM uint32_t NO_UNTRANSLATED_NONSEC : 1;/*!< When 1, Non-secure accesses to the uncached, untranslated window + (addr[27:26] == 3) will generate a bus error. */ + __IOM uint32_t MAINT_NONSEC : 1; /*!< When 0, Non-secure accesses to the cache maintenance address + window (addr[27] == 1, addr[26] == 0) will generate a bus + error. When 1, Non-secure accesses can perform cache maintenance + operations by writing to the cache maintenance address + window. Cache maintenance operations may be used to corrupt + Secure data by invalidating cache lines inappropriately, + or map Secure content into a Non-secure region by pinning + cache lines. Therefore this bit should generally be set + to 0, unless Secure code is not using the cache. Care should + also be taken to clear the cache data memory and tag memory + before granting maintenance operations to Non-secure code. */ + __IOM uint32_t SPLIT_WAYS : 1; /*!< When 1, route all cached+Secure accesses to way 0 of the cache, + and route all cached+Non-secure accesses to way 1 of the + cache. This partitions the cache into two half-sized direct-mapped + regions, such that Non-secure code can not observe cache + line state changes caused by Secure execution. A full cache + flush is required when changing the value of SPLIT_WAYS. + The flush should be performed whilst SPLIT_WAYS is 0, so + that both cache ways are accessible for invalidation. */ + __IOM uint32_t WRITABLE_M0 : 1; /*!< If 1, enable writes to XIP memory window 0 (addresses 0x10000000 + through 0x10ffffff, and their uncached mirrors). If 0, + this region is read-only. XIP memory is *read-only by default*. + This bit must be set to enable writes if a RAM device is + attached on QSPI chip select 0. The default read-only behaviour + avoids two issues with writing to a read-only QSPI device + (e.g. flash). First, a write will initially appear to succeed + due to caching, but the data will eventually be lost when + the written line is evicted, causing unpredictable behaviour. + Second, when a written line is evicted, it will cause a + write command to be issued to the flash, which can break + the flash out of its continuous read mode. After this point, + flash reads will return garbage. This is a security concern, + as it allows Non-secure software to break Secure flash + reads if it has permission to write to any flash address. + Note the read-only behaviour is implemented by downgrading + writes to reads, so writes will still cause allocation + of an address, but have no other effect. */ + __IOM uint32_t WRITABLE_M1 : 1; /*!< If 1, enable writes to XIP memory window 1 (addresses 0x11000000 + through 0x11ffffff, and their uncached mirrors). If 0, + this region is read-only. XIP memory is *read-only by default*. + This bit must be set to enable writes if a RAM device is + attached on QSPI chip select 1. The default read-only behaviour + avoids two issues with writing to a read-only QSPI device + (e.g. flash). First, a write will initially appear to succeed + due to caching, but the data will eventually be lost when + the written line is evicted, causing unpredictable behaviour. + Second, when a written line is evicted, it will cause a + write command to be issued to the flash, which can break + the flash out of its continuous read mode. After this point, + flash reads will return garbage. This is a security concern, + as it allows Non-secure software to break Secure flash + reads if it has permission to write to any flash address. + Note the read-only behaviour is implemented by downgrading + writes to reads, so writes will still cause allocation + of an address, but have no other effect. */ + uint32_t : 20; + } bit; + } CTRL; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< STAT */ + + struct { + uint32_t : 1; + __IM uint32_t FIFO_EMPTY : 1; /*!< When 1, indicates the XIP streaming FIFO is completely empty. */ + __IM uint32_t FIFO_FULL : 1; /*!< When 1, indicates the XIP streaming FIFO is completely full. + The streaming FIFO is 2 entries deep, so the full and empty + flag allow its level to be ascertained. */ + uint32_t : 29; + } bit; + } STAT; + + union { + __IOM uint32_t reg; /*!< Cache Hit counter */ + + struct { + __IOM uint32_t CTR_HIT : 32; /*!< A 32 bit saturating counter that increments upon each cache + hit, i.e. when an XIP access is serviced directly from + cached data. Write any value to clear. */ + } bit; + } CTR_HIT; + + union { + __IOM uint32_t reg; /*!< Cache Access counter */ + + struct { + __IOM uint32_t CTR_ACC : 32; /*!< A 32 bit saturating counter that increments upon each XIP access, + whether the cache is hit or not. This includes noncacheable + accesses. Write any value to clear. */ + } bit; + } CTR_ACC; + + union { + __IOM uint32_t reg; /*!< FIFO stream address */ + + struct { + uint32_t : 2; + __IOM uint32_t STREAM_ADDR : 30; /*!< The address of the next word to be streamed from flash to the + streaming FIFO. Increments automatically after each flash + access. Write the initial access address here before starting + a streaming read. */ + } bit; + } STREAM_ADDR; + + union { + __IOM uint32_t reg; /*!< FIFO stream control */ + + struct { + __IOM uint32_t STREAM_CTR : 22; /*!< Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to + transfer a linear data block from flash to the streaming + FIFO. Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. Write 0 to halt an + in-progress stream, and discard any in-flight read, so + that a new stream can immediately be started (after draining + the FIFO and reinitialising STREAM_ADDR) */ + uint32_t : 10; + } bit; + } STREAM_CTR; + + union { + __IOM uint32_t reg; /*!< FIFO stream data */ + + struct { + __IM uint32_t STREAM_FIFO : 32; /*!< Streamed data is buffered here, for retrieval by the system + DMA. This FIFO can also be accessed via the XIP_AUX slave, + to avoid exposing the DMA to bus stalls caused by other + XIP traffic. */ + } bit; + } STREAM_FIFO; +} XIP_CTRL_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ XIP_AUX ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Auxiliary DMA access to XIP FIFOs, via fast AHB bus access (XIP_AUX) + */ + +typedef struct { /*!< XIP_AUX Structure */ + + union { + __IOM uint32_t reg; /*!< Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) */ + + struct { + __IM uint32_t STREAM : 32; /*!< STREAM */ + } bit; + } STREAM; + + union { + __IOM uint32_t reg; /*!< Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) */ + + struct { + __OM uint32_t DATA : 16; /*!< Data pushed here will be clocked out falling edges of SCK (or + before the very first rising edge of SCK, if this is the + first pulse). For each byte clocked out, the interface + will simultaneously sample one byte, on rising edges of + SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, + the least-significant byte is transmitted first. */ + __OM uint32_t IWIDTH : 2; /*!< Configure whether this FIFO record is transferred with single/dual/quad + interface width (0/1/2). Different widths can be mixed + freely. */ + __OM uint32_t DWIDTH : 1; /*!< Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX + DATA field, and return an 8-bit value in the 8 LSBs of + DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and + 16-bit transfers can be mixed freely. */ + __OM uint32_t OE : 1; /*!< Output enable (active-high). For single width (SPI), this field + is ignored, and SD0 is always set to output, with SD1 always + set to input. For dual and quad width (DSPI/QSPI), this + sets whether the relevant SDx pads are set to output whilst + transferring this FIFO record. In this case the command/address + should have OE set, and the data transfer should have OE + set or clear depending on the direction of the transfer. */ + __OM uint32_t NOPUSH : 1; /*!< Inhibit the RX FIFO push that would correspond to this TX FIFO + entry. Useful to avoid garbage appearing in the RX FIFO + when pushing the command at the beginning of a SPI transfer. */ + uint32_t : 11; + } bit; + } QMI_DIRECT_TX; + + union { + __IOM uint32_t reg; /*!< Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) */ + + struct { + __IM uint32_t QMI_DIRECT_RX : 16; /*!< With each byte clocked out on the serial interface, one byte + will simultaneously be clocked in, and will appear in this + FIFO. The serial interface will stall when this FIFO is + full, to avoid dropping data. When 16-bit data is pushed + into the TX FIFO, the corresponding RX FIFO push will also + contain 16 bits of data. The least-significant byte is + the first one received. */ + uint32_t : 16; + } bit; + } QMI_DIRECT_RX; +} XIP_AUX_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for various chip control signals (SYSCFG) + */ + +typedef struct { /*!< SYSCFG Structure */ + + union { + __IOM uint32_t reg; /*!< Configuration for processors */ + + struct { + __IM uint32_t PROC0_HALTED : 1; /*!< Indication that proc0 has halted */ + __IM uint32_t PROC1_HALTED : 1; /*!< Indication that proc1 has halted */ + uint32_t : 30; + } bit; + } PROC_CONFIG; + + union { + __IOM uint32_t reg; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 0...31. */ + + struct { + __IOM uint32_t GPIO : 32; /*!< GPIO */ + } bit; + } PROC_IN_SYNC_BYPASS; + + union { + __IOM uint32_t reg; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 32...47. USB GPIO 56..57 + QSPI GPIO 58..63 */ + + struct { + __IOM uint32_t GPIO : 16; /*!< GPIO */ + uint32_t : 8; + __IOM uint32_t USB_DP : 1; /*!< USB_DP */ + __IOM uint32_t USB_DM : 1; /*!< USB_DM */ + __IOM uint32_t QSPI_SCK : 1; /*!< QSPI_SCK */ + __IOM uint32_t QSPI_CSN : 1; /*!< QSPI_CSN */ + __IOM uint32_t QSPI_SD : 4; /*!< QSPI_SD */ + } bit; + } PROC_IN_SYNC_BYPASS_HI; + + union { + __IOM uint32_t reg; /*!< Directly control the chip SWD debug port */ + + struct { + __IM uint32_t SWDO : 1; /*!< Observe the value of SWDIO output. */ + __IOM uint32_t SWDI : 1; /*!< Directly drive SWDIO input, if ATTACH is set */ + __IOM uint32_t SWCLK : 1; /*!< Directly drive SWCLK, if ATTACH is set */ + __IOM uint32_t ATTACH : 1; /*!< Attach chip debug port to syscfg controls, and disconnect it + from external SWD pads. */ + uint32_t : 28; + } bit; + } DBGFORCE; + + union { + __IOM uint32_t reg; /*!< Control PD pins to memories. Set high to put memories to a low + power state. In this state the memories will retain contents + but not be accessible Use with caution */ + + struct { + __IOM uint32_t SRAM0 : 1; /*!< SRAM0 */ + __IOM uint32_t SRAM1 : 1; /*!< SRAM1 */ + __IOM uint32_t SRAM2 : 1; /*!< SRAM2 */ + __IOM uint32_t SRAM3 : 1; /*!< SRAM3 */ + __IOM uint32_t SRAM4 : 1; /*!< SRAM4 */ + __IOM uint32_t SRAM5 : 1; /*!< SRAM5 */ + __IOM uint32_t SRAM6 : 1; /*!< SRAM6 */ + __IOM uint32_t SRAM7 : 1; /*!< SRAM7 */ + __IOM uint32_t SRAM8 : 1; /*!< SRAM8 */ + __IOM uint32_t SRAM9 : 1; /*!< SRAM9 */ + __IOM uint32_t USB : 1; /*!< USB */ + __IOM uint32_t ROM : 1; /*!< ROM */ + __IOM uint32_t BOOTRAM : 1; /*!< BOOTRAM */ + uint32_t : 19; + } bit; + } MEMPOWERDOWN; + + union { + __IOM uint32_t reg; /*!< Auxiliary system control register */ + + struct { + __IOM uint32_t AUXCTRL : 8; /*!< * Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is + XORed into the TRNG ROSC output as an additional, uncorrelated + entropy source. When set, this behaviour is disabled. * + Bit 0: Force POWMAN clock to switch to LPOSC, by asserting + its WDRESET input. This must be set before initiating a + watchdog reset of the RSM from a stage that includes CLOCKS, + if POWMAN is running from clk_ref at the point that the + watchdog reset takes place. Otherwise, the short pulse + generated on clk_ref by the reset of the CLOCKS block may + affect POWMAN register state. */ + uint32_t : 24; + } bit; + } AUXCTRL; +} SYSCFG_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ XOSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls the crystal oscillator (XOSC) + */ + +typedef struct { /*!< XOSC Structure */ + + union { + __IOM uint32_t reg; /*!< Crystal Oscillator Control */ + + struct { + __IOM uint32_t FREQ_RANGE : 12; /*!< The 12-bit code is intended to give some protection against + accidental writes. An invalid setting will retain the previous + value. The actual value being used can be read from STATUS_FREQ_RANGE */ + __IOM uint32_t ENABLE : 12; /*!< On power-up this field is initialised to DISABLE and the chip + runs from the ROSC. If the chip has subsequently been programmed + to run from the XOSC then setting this field to DISABLE + may lock-up the chip. If this is a concern then run the + clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against + accidental writes. An invalid setting will retain the previous + value. The actual value being used can be read from STATUS_ENABLED */ + uint32_t : 8; + } bit; + } CTRL; + + union { + __IOM uint32_t reg; /*!< Crystal Oscillator Status */ + + struct { + __IM uint32_t FREQ_RANGE : 2; /*!< The current frequency range setting */ + uint32_t : 10; + __IM uint32_t ENABLED : 1; /*!< Oscillator is enabled but not necessarily running and stable, + resets to 0 */ + uint32_t : 11; + __IOM uint32_t BADWRITE : 1; /*!< An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE + or DORMANT */ + uint32_t : 6; + __IM uint32_t STABLE : 1; /*!< Oscillator is running and stable */ + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< Crystal Oscillator pause control */ + + struct { + __IOM uint32_t DORMANT : 32; /*!< This is used to save power by pausing the XOSC On power-up this + field is initialised to WAKE An invalid write will also + select WAKE Warning: stop the PLLs before selecting dormant + mode Warning: setup the irq before selecting dormant mode */ + } bit; + } DORMANT; + + union { + __IOM uint32_t reg; /*!< Controls the startup delay */ + + struct { + __IOM uint32_t DELAY : 14; /*!< in multiples of 256*xtal_period. The reset value of 0xc4 corresponds + to approx 50 000 cycles. */ + uint32_t : 6; + __IOM uint32_t X4 : 1; /*!< Multiplies the startup_delay by 4, just in case. The reset value + is controlled by a mask-programmable tiecell and is provided + in case we are booting from XOSC and the default startup + delay is insufficient. The reset value is 0x0. */ + uint32_t : 11; + } bit; + } STARTUP; + + union { + __IOM uint32_t reg; /*!< A down counter running at the xosc frequency which counts to + zero and stops. Can be used for short software pauses when + setting up time sensitive hardware. To start the counter, + write a non-zero value. Reads will return 1 while the count + is running and 0 when it has finished. Minimum count value + is 4. Count values <4 will be treated as count value =4. + Note that synchronisation to the register clock domain + costs 2 register clock cycles and the counter cannot compensate + for that. */ + + struct { + __IOM uint32_t COUNT : 16; /*!< COUNT */ + uint32_t : 16; + } bit; + } COUNT; +} XOSC_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ PLL_SYS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PLL_SYS (PLL_SYS) + */ + +typedef struct { /*!< PLL_SYS Structure */ + + union { + __IOM uint32_t reg; /*!< Control and Status GENERAL CONSTRAINTS: Reference clock frequency + min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO + frequency min=750MHz, max=1600MHz */ + + struct { + __IOM uint32_t REFDIV : 6; /*!< Divides the PLL input reference clock. Behaviour is undefined + for div=0. PLL output will be unpredictable during refdiv + changes, wait for lock=1 before using it. */ + uint32_t : 2; + __IOM uint32_t BYPASS : 1; /*!< Passes the reference clock to the output instead of the divided + VCO. The VCO continues to run so the user can switch between + the reference clock and the divided VCO but the output + will glitch when doing so. */ + uint32_t : 21; + __IOM uint32_t LOCK_N : 1; /*!< PLL is not locked Ideally this is cleared when PLL lock is seen + and this should never normally be set */ + __IM uint32_t LOCK : 1; /*!< PLL is locked */ + } bit; + } CS; + + union { + __IOM uint32_t reg; /*!< Controls the PLL power modes. */ + + struct { + __IOM uint32_t PD : 1; /*!< PLL powerdown To save power set high when PLL output not required. */ + uint32_t : 1; + __IOM uint32_t DSMPD : 1; /*!< PLL DSM powerdown Nothing is achieved by setting this low. */ + __IOM uint32_t POSTDIVPD : 1; /*!< PLL post divider powerdown To save power set high when PLL output + not required or bypass=1. */ + uint32_t : 1; + __IOM uint32_t VCOPD : 1; /*!< PLL VCO powerdown To save power set high when PLL output not + required or bypass=1. */ + uint32_t : 26; + } bit; + } PWR; + + union { + __IOM uint32_t reg; /*!< Feedback divisor (note: this PLL does not support fractional + division) */ + + struct { + __IOM uint32_t FBDIV_INT : 12; /*!< see ctrl reg description for constraints */ + uint32_t : 20; + } bit; + } FBDIV_INT; + + union { + __IOM uint32_t reg; /*!< Controls the PLL post dividers for the primary output (note: + this PLL does not have a secondary output) the primary + output is driven from VCO divided by postdiv1*postdiv2 */ + + struct { + uint32_t : 12; + __IOM uint32_t POSTDIV2 : 3; /*!< divide by 1-7 */ + uint32_t : 1; + __IOM uint32_t POSTDIV1 : 3; /*!< divide by 1-7 */ + uint32_t : 13; + } bit; + } PRIM; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IOM uint32_t LOCK_N_STICKY : 1; /*!< LOCK_N_STICKY */ + uint32_t : 31; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable */ + + struct { + __IOM uint32_t LOCK_N_STICKY : 1; /*!< LOCK_N_STICKY */ + uint32_t : 31; + } bit; + } INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force */ + + struct { + __IOM uint32_t LOCK_N_STICKY : 1; /*!< LOCK_N_STICKY */ + uint32_t : 31; + } bit; + } INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing */ + + struct { + __IM uint32_t LOCK_N_STICKY : 1; /*!< LOCK_N_STICKY */ + uint32_t : 31; + } bit; + } INTS; +} PLL_SYS_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ ACCESSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Hardware access control registers (ACCESSCTRL) + */ + +typedef struct { /*!< ACCESSCTRL Structure */ + + union { + __IOM uint32_t reg; /*!< Once a LOCK bit is written to 1, ACCESSCTRL silently ignores + writes from that master. LOCK is writable only by a Secure, + Privileged processor or debugger. LOCK bits are only writable + when their value is zero. Once set, they can never be cleared, + except by a full reset of ACCESSCTRL Setting the LOCK bit + does not affect whether an access raises a bus error. Unprivileged + writes, or writes from the DMA, will continue to raise + bus errors. All other accesses will continue not to. */ + + struct { + __IOM uint32_t CORE0 : 1; /*!< CORE0 */ + __IOM uint32_t CORE1 : 1; /*!< CORE1 */ + __IM uint32_t DMA : 1; /*!< DMA */ + __IOM uint32_t DEBUG : 1; /*!< DEBUG */ + uint32_t : 28; + } bit; + } LOCK; + + union { + __IOM uint32_t reg; /*!< Force core 1's bus accesses to always be Non-secure, no matter + the core's internal state. Useful for schemes where one + core is designated as the Non-secure core, since some peripherals + may filter individual registers internally based on security + state but not on master ID. */ + + struct { + uint32_t : 1; + __IOM uint32_t CORE1 : 1; /*!< CORE1 */ + uint32_t : 30; + } bit; + } FORCE_CORE_NS; + + union { + __IOM uint32_t reg; /*!< Write 1 to reset all ACCESSCTRL configuration, except for the + LOCK and FORCE_CORE_NS registers. This bit is used in the + RP2350 bootrom to quickly restore ACCESSCTRL to a known + state during the boot path. Note that, like all registers + in ACCESSCTRL, this register is not writable when the writer's + corresponding LOCK bit is set, therefore a master which + has been locked out of ACCESSCTRL can not use the CFGRESET + register to disturb its contents. */ + + struct { + __OM uint32_t CFGRESET : 1; /*!< CFGRESET */ + uint32_t : 31; + } bit; + } CFGRESET; + + union { + __IOM uint32_t reg; /*!< Control whether GPIO0...31 are accessible to Non-secure code. + Writable only by a Secure, Privileged processor or debugger. + 0 -> Secure access only 1 -> Secure + Non-secure access */ + + struct { + __IOM uint32_t GPIO_NSMASK0 : 32; /*!< GPIO_NSMASK0 */ + } bit; + } GPIO_NSMASK0; + + union { + __IOM uint32_t reg; /*!< Control whether GPIO32..47 are accessible to Non-secure code, + and whether QSPI and USB bitbang are accessible through + the Non-secure SIO. Writable only by a Secure, Privileged + processor or debugger. */ + + struct { + __IOM uint32_t GPIO : 16; /*!< GPIO */ + uint32_t : 8; + __IOM uint32_t USB_DP : 1; /*!< USB_DP */ + __IOM uint32_t USB_DM : 1; /*!< USB_DM */ + __IOM uint32_t QSPI_SCK : 1; /*!< QSPI_SCK */ + __IOM uint32_t QSPI_CSN : 1; /*!< QSPI_CSN */ + __IOM uint32_t QSPI_SD : 4; /*!< QSPI_SD */ + } bit; + } GPIO_NSMASK1; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + ROM, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, ROM can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, ROM can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, ROM can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, ROM can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, ROM can be accessed by core 0, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, ROM can be accessed by core 1, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, ROM can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, ROM can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } ROM; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_MAIN, and at what security/privilege levels they can + do so. Defaults to fully open access. This register is + writable only from a Secure, Privileged processor or debugger, + with the exception of the NSU bit, which becomes Non-secure-Privileged-wr + table when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, XIP_MAIN can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, XIP_MAIN can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, XIP_MAIN can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, XIP_MAIN can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, XIP_MAIN can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, XIP_MAIN can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } XIP_MAIN; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM0, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM0 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM0 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM0 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM0 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM0 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM0 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM0 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM0; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM1, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM1 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM1 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM1 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM1 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM1 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM1 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM1 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM1; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM2, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM2 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM2 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM2 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM2 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM2 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM2 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM2 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM2; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM3, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM3 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM3 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM3 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM3 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM3 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM3 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM3 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM3; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM4, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM4 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM4 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM4 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM4 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM4 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM4 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM4 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM4; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM5, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM5 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM5 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM5 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM5 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM5 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM5 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM5 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM5; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM6, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM6 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM6 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM6 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM6 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM6 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM6 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM6 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM6; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM7, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM7 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM7 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM7 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM7 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM7 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM7 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM7 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM7; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM8, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM8 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM8 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM8 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM8 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM8 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM8 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM8 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM8; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM9, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SRAM9 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SRAM9 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SRAM9 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SRAM9 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SRAM9 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SRAM9 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SRAM9 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SRAM9; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + DMA, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, DMA can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, DMA can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, DMA can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, DMA can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, DMA can be accessed by core 0, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, DMA can be accessed by core 1, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, DMA can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, DMA can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } DMA; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + USBCTRL, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, USBCTRL can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, USBCTRL can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, USBCTRL can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, USBCTRL can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, USBCTRL can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, USBCTRL can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, USBCTRL can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } USBCTRL; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PIO0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, PIO0 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, PIO0 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, PIO0 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, PIO0 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, PIO0 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, PIO0 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, PIO0 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } PIO0; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PIO1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, PIO1 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, PIO1 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, PIO1 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, PIO1 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, PIO1 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, PIO1 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, PIO1 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } PIO1; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PIO2, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, PIO2 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, PIO2 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, PIO2 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, PIO2 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, PIO2 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, PIO2 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, PIO2 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } PIO2; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + CORESIGHT_TRACE, and at what security/privilege levels + they can do so. Defaults to Secure, Privileged processor + or debug access only. This register is writable only from + a Secure, Privileged processor or debugger, with the exception + of the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from + a Non-secure, Unprivileged context. This bit is writable + from a Non-secure, Privileged context, if and only if the + NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, CORESIGHT_TRACE can be accessed from + a Secure, Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged + context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } CORESIGHT_TRACE; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + CORESIGHT_PERIPH, and at what security/privilege levels + they can do so. Defaults to Secure, Privileged processor + or debug access only. This register is writable only from + a Secure, Privileged processor or debugger, with the exception + of the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed + from a Non-secure, Unprivileged context. This bit is writable + from a Non-secure, Privileged context, if and only if the + NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from + a Secure, Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged + context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } CORESIGHT_PERIPH; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SYSINFO, and at what security/privilege levels they can + do so. Defaults to fully open access. This register is + writable only from a Secure, Privileged processor or debugger, + with the exception of the NSU bit, which becomes Non-secure-Privileged-wr + table when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SYSINFO can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SYSINFO can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SYSINFO can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SYSINFO can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SYSINFO can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SYSINFO can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SYSINFO can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SYSINFO; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + RESETS, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, RESETS can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, RESETS can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, RESETS can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, RESETS can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, RESETS can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, RESETS can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, RESETS can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, RESETS can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } RESETS; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + IO_BANK0, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, IO_BANK0 can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, IO_BANK0 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, IO_BANK0 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, IO_BANK0 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, IO_BANK0 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, IO_BANK0 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } IO_BANK0; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + IO_BANK1, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, IO_BANK1 can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, IO_BANK1 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, IO_BANK1 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, IO_BANK1 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, IO_BANK1 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, IO_BANK1 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } IO_BANK1; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PADS_BANK0, and at what security/privilege levels they + can do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, PADS_BANK0 can be accessed from a + Non-secure, Unprivileged context. This bit is writable + from a Non-secure, Privileged context, if and only if the + NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, PADS_BANK0 can be accessed from a + Secure, Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, PADS_BANK0 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, PADS_BANK0 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } PADS_BANK0; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PADS_QSPI, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, PADS_QSPI can be accessed from a + Non-secure, Unprivileged context. This bit is writable + from a Non-secure, Privileged context, if and only if the + NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, PADS_QSPI can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, PADS_QSPI can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, PADS_QSPI can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, PADS_QSPI can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, PADS_QSPI can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, PADS_QSPI can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } PADS_QSPI; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + BUSCTRL, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, BUSCTRL can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, BUSCTRL can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, BUSCTRL can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, BUSCTRL can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, BUSCTRL can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, BUSCTRL can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, BUSCTRL can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } BUSCTRL; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + ADC0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, ADC0 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, ADC0 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, ADC0 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, ADC0 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, ADC0 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, ADC0 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, ADC0 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } ADC0; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + HSTX, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, HSTX can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, HSTX can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, HSTX can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, HSTX can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, HSTX can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, HSTX can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, HSTX can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, HSTX can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } HSTX; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + I2C0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, I2C0 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, I2C0 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, I2C0 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, I2C0 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, I2C0 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, I2C0 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, I2C0 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } I2C0; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + I2C1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, I2C1 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, I2C1 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, I2C1 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, I2C1 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, I2C1 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, I2C1 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, I2C1 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } I2C1; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PWM, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, PWM can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, PWM can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, PWM can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, PWM can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, PWM can be accessed by core 0, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, PWM can be accessed by core 1, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, PWM can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, PWM can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } PWM; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SPI0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SPI0 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SPI0 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SPI0 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SPI0 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SPI0 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SPI0 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SPI0 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SPI0; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SPI1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SPI1 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SPI1 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SPI1 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SPI1 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SPI1 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SPI1 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SPI1 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SPI1; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TIMER0, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, TIMER0 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, TIMER0 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, TIMER0 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, TIMER0 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, TIMER0 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, TIMER0 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, TIMER0 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } TIMER0; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TIMER1, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, TIMER1 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, TIMER1 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, TIMER1 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, TIMER1 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, TIMER1 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, TIMER1 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, TIMER1 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } TIMER1; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + UART0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, UART0 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, UART0 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, UART0 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, UART0 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, UART0 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, UART0 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, UART0 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, UART0 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } UART0; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + UART1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, UART1 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, UART1 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, UART1 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, UART1 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, UART1 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, UART1 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, UART1 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, UART1 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } UART1; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + OTP, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, OTP can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, OTP can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, OTP can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, OTP can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, OTP can be accessed by core 0, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, OTP can be accessed by core 1, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, OTP can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, OTP can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } OTP; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TBMAN, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, TBMAN can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, TBMAN can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, TBMAN can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, TBMAN can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, TBMAN can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, TBMAN can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, TBMAN can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } TBMAN; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + POWMAN, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, POWMAN can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, POWMAN can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, POWMAN can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, POWMAN can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, POWMAN can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, POWMAN can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, POWMAN can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } POWMAN; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TRNG, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, TRNG can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, TRNG can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, TRNG can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, TRNG can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, TRNG can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, TRNG can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, TRNG can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, TRNG can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } TRNG; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SHA256, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged access only. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SHA256 can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SHA256 can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SHA256 can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SHA256 can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SHA256 can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SHA256 can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SHA256 can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SHA256; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SYSCFG, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, SYSCFG can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, SYSCFG can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, SYSCFG can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, SYSCFG can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, SYSCFG can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, SYSCFG can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, SYSCFG can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } SYSCFG; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + CLOCKS, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, CLOCKS can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, CLOCKS can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, CLOCKS can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, CLOCKS can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, CLOCKS can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, CLOCKS can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, CLOCKS can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } CLOCKS; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XOSC, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, XOSC can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, XOSC can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, XOSC can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, XOSC can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, XOSC can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, XOSC can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, XOSC can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, XOSC can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } XOSC; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + ROSC, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, ROSC can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, ROSC can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, ROSC can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, ROSC can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, ROSC can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, ROSC can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, ROSC can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, ROSC can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } ROSC; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PLL_SYS, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, PLL_SYS can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, PLL_SYS can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, PLL_SYS can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, PLL_SYS can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, PLL_SYS can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, PLL_SYS can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, PLL_SYS can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } PLL_SYS; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PLL_USB, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, PLL_USB can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, PLL_USB can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, PLL_USB can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, PLL_USB can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, PLL_USB can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, PLL_USB can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, PLL_USB can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } PLL_USB; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TICKS, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, TICKS can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, TICKS can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, TICKS can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, TICKS can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, TICKS can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, TICKS can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, TICKS can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, TICKS can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } TICKS; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + WATCHDOG, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, WATCHDOG can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, WATCHDOG can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, WATCHDOG can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, WATCHDOG can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, WATCHDOG can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, WATCHDOG can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, WATCHDOG can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } WATCHDOG; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + RSM, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, RSM can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, RSM can be accessed from a Non-secure, Privileged context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, RSM can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, RSM can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, RSM can be accessed by core 0, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, RSM can be accessed by core 1, at security/privilege levels + permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, RSM can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, RSM can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } RSM; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_CTRL, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, XIP_CTRL can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, XIP_CTRL can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, XIP_CTRL can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, XIP_CTRL can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, XIP_CTRL can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, XIP_CTRL can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } XIP_CTRL; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_QMI, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, XIP_QMI can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, XIP_QMI can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, XIP_QMI can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, XIP_QMI can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, XIP_QMI can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, XIP_QMI can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, XIP_QMI can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } XIP_QMI; + + union { + __IOM uint32_t reg; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_AUX, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged access only. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + + struct { + __IOM uint32_t NSU : 1; /*!< If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, + Unprivileged context. This bit is writable from a Non-secure, + Privileged context, if and only if the NSP bit is set. */ + __IOM uint32_t NSP : 1; /*!< If 1, XIP_AUX can be accessed from a Non-secure, Privileged + context. */ + __IOM uint32_t SU : 1; /*!< If 1, and SP is also set, XIP_AUX can be accessed from a Secure, + Unprivileged context. */ + __IOM uint32_t SP : 1; /*!< If 1, XIP_AUX can be accessed from a Secure, Privileged context. */ + __IOM uint32_t CORE0 : 1; /*!< If 1, XIP_AUX can be accessed by core 0, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t CORE1 : 1; /*!< If 1, XIP_AUX can be accessed by core 1, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DMA : 1; /*!< If 1, XIP_AUX can be accessed by the DMA, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + __IOM uint32_t DBG : 1; /*!< If 1, XIP_AUX can be accessed by the debugger, at security/privilege + levels permitted by SP/NSP/SU/NSU in this register. */ + uint32_t : 24; + } bit; + } XIP_AUX; +} ACCESSCTRL_Type; /*!< Size = 236 (0xec) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0 (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + + union { + __IOM uint32_t reg; /*!< Data Register, UARTDR */ + + struct { + __IOM uint32_t DATA : 8; /*!< Receive (read) data character. Transmit (write) data character. */ + __IM uint32_t FE : 1; /*!< Framing error. When set to 1, it indicates that the received + character did not have a valid stop bit (a valid stop bit + is 1). In FIFO mode, this error is associated with the + character at the top of the FIFO. */ + __IM uint32_t PE : 1; /*!< Parity error. When set to 1, it indicates that the parity of + the received data character does not match the parity that + the EPS and SPS bits in the Line Control Register, UARTLCR_H. + In FIFO mode, this error is associated with the character + at the top of the FIFO. */ + __IM uint32_t BE : 1; /*!< Break error. This bit is set to 1 if a break condition was detected, + indicating that the received data input was held LOW for + longer than a full-word transmission time (defined as start, + data, parity and stop bits). In FIFO mode, this error is + associated with the character at the top of the FIFO. When + a break occurs, only one 0 character is loaded into the + FIFO. The next character is only enabled after the receive + data input goes to a 1 (marking state), and the next valid + start bit is received. */ + __IM uint32_t OE : 1; /*!< Overrun error. This bit is set to 1 if data is received and + the receive FIFO is already full. This is cleared to 0 + once there is an empty space in the FIFO and a new character + can be written to it. */ + uint32_t : 20; + } bit; + } UARTDR; + + union { + __IOM uint32_t reg; /*!< Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ + + struct { + __IOM uint32_t FE : 1; /*!< Framing error. When set to 1, it indicates that the received + character did not have a valid stop bit (a valid stop bit + is 1). This bit is cleared to 0 by a write to UARTECR. + In FIFO mode, this error is associated with the character + at the top of the FIFO. */ + __IOM uint32_t PE : 1; /*!< Parity error. When set to 1, it indicates that the parity of + the received data character does not match the parity that + the EPS and SPS bits in the Line Control Register, UARTLCR_H. + This bit is cleared to 0 by a write to UARTECR. In FIFO + mode, this error is associated with the character at the + top of the FIFO. */ + __IOM uint32_t BE : 1; /*!< Break error. This bit is set to 1 if a break condition was detected, + indicating that the received data input was held LOW for + longer than a full-word transmission time (defined as start, + data, parity, and stop bits). This bit is cleared to 0 + after a write to UARTECR. In FIFO mode, this error is associated + with the character at the top of the FIFO. When a break + occurs, only one 0 character is loaded into the FIFO. The + next character is only enabled after the receive data input + goes to a 1 (marking state) and the next valid start bit + is received. */ + __IOM uint32_t OE : 1; /*!< Overrun error. This bit is set to 1 if data is received and + the FIFO is already full. This bit is cleared to 0 by a + write to UARTECR. The FIFO contents remain valid because + no more data is written when the FIFO is full, only the + contents of the shift register are overwritten. The CPU + must now read the data, to empty the FIFO. */ + uint32_t : 28; + } bit; + } UARTRSR; + __IM uint32_t RESERVED[4]; + + union { + __IOM uint32_t reg; /*!< Flag Register, UARTFR */ + + struct { + __IM uint32_t CTS : 1; /*!< Clear to send. This bit is the complement of the UART clear + to send, nUARTCTS, modem status input. That is, the bit + is 1 when nUARTCTS is LOW. */ + __IM uint32_t DSR : 1; /*!< Data set ready. This bit is the complement of the UART data + set ready, nUARTDSR, modem status input. That is, the bit + is 1 when nUARTDSR is LOW. */ + __IM uint32_t DCD : 1; /*!< Data carrier detect. This bit is the complement of the UART + data carrier detect, nUARTDCD, modem status input. That + is, the bit is 1 when nUARTDCD is LOW. */ + __IM uint32_t BUSY : 1; /*!< UART busy. If this bit is set to 1, the UART is busy transmitting + data. This bit remains set until the complete byte, including + all the stop bits, has been sent from the shift register. + This bit is set as soon as the transmit FIFO becomes non-empty, + regardless of whether the UART is enabled or not. */ + __IM uint32_t RXFE : 1; /*!< Receive FIFO empty. The meaning of this bit depends on the state + of the FEN bit in the UARTLCR_H Register. If the FIFO is + disabled, this bit is set when the receive holding register + is empty. If the FIFO is enabled, the RXFE bit is set when + the receive FIFO is empty. */ + __IM uint32_t TXFF : 1; /*!< Transmit FIFO full. The meaning of this bit depends on the state + of the FEN bit in the UARTLCR_H Register. If the FIFO is + disabled, this bit is set when the transmit holding register + is full. If the FIFO is enabled, the TXFF bit is set when + the transmit FIFO is full. */ + __IM uint32_t RXFF : 1; /*!< Receive FIFO full. The meaning of this bit depends on the state + of the FEN bit in the UARTLCR_H Register. If the FIFO is + disabled, this bit is set when the receive holding register + is full. If the FIFO is enabled, the RXFF bit is set when + the receive FIFO is full. */ + __IM uint32_t TXFE : 1; /*!< Transmit FIFO empty. The meaning of this bit depends on the + state of the FEN bit in the Line Control Register, UARTLCR_H. + If the FIFO is disabled, this bit is set when the transmit + holding register is empty. If the FIFO is enabled, the + TXFE bit is set when the transmit FIFO is empty. This bit + does not indicate if there is data in the transmit shift + register. */ + __IM uint32_t RI : 1; /*!< Ring indicator. This bit is the complement of the UART ring + indicator, nUARTRI, modem status input. That is, the bit + is 1 when nUARTRI is LOW. */ + uint32_t : 23; + } bit; + } UARTFR; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< IrDA Low-Power Counter Register, UARTILPR */ + + struct { + __IOM uint32_t ILPDVSR : 8; /*!< 8-bit low-power divisor value. These bits are cleared to 0 at + reset. */ + uint32_t : 24; + } bit; + } UARTILPR; + + union { + __IOM uint32_t reg; /*!< Integer Baud Rate Register, UARTIBRD */ + + struct { + __IOM uint32_t BAUD_DIVINT : 16; /*!< The integer baud rate divisor. These bits are cleared to 0 on + reset. */ + uint32_t : 16; + } bit; + } UARTIBRD; + + union { + __IOM uint32_t reg; /*!< Fractional Baud Rate Register, UARTFBRD */ + + struct { + __IOM uint32_t BAUD_DIVFRAC : 6; /*!< The fractional baud rate divisor. These bits are cleared to + 0 on reset. */ + uint32_t : 26; + } bit; + } UARTFBRD; + + union { + __IOM uint32_t reg; /*!< Line Control Register, UARTLCR_H */ + + struct { + __IOM uint32_t BRK : 1; /*!< Send break. If this bit is set to 1, a low-level is continually + output on the UARTTXD output, after completing transmission + of the current character. For the proper execution of the + break command, the software must set this bit for at least + two complete frames. For normal use, this bit must be cleared + to 0. */ + __IOM uint32_t PEN : 1; /*!< Parity enable: 0 = parity is disabled and no parity bit added + to the data frame 1 = parity checking and generation is + enabled. */ + __IOM uint32_t EPS : 1; /*!< Even parity select. Controls the type of parity the UART uses + during transmission and reception: 0 = odd parity. The + UART generates or checks for an odd number of 1s in the + data and parity bits. 1 = even parity. The UART generates + or checks for an even number of 1s in the data and parity + bits. This bit has no effect when the PEN bit disables + parity checking and generation. */ + __IOM uint32_t STP2 : 1; /*!< Two stop bits select. If this bit is set to 1, two stop bits + are transmitted at the end of the frame. The receive logic + does not check for two stop bits being received. */ + __IOM uint32_t FEN : 1; /*!< Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, + the FIFOs become 1-byte-deep holding registers 1 = transmit + and receive FIFO buffers are enabled (FIFO mode). */ + __IOM uint32_t WLEN : 2; /*!< Word length. These bits indicate the number of data bits transmitted + or received in a frame as follows: b11 = 8 bits b10 = 7 + bits b01 = 6 bits b00 = 5 bits. */ + __IOM uint32_t SPS : 1; /*!< Stick parity select. 0 = stick parity is disabled 1 = either: + * if the EPS bit is 0 then the parity bit is transmitted + and checked as a 1 * if the EPS bit is 1 then the parity + bit is transmitted and checked as a 0. This bit has no + effect when the PEN bit disables parity checking and generation. */ + uint32_t : 24; + } bit; + } UARTLCR_H; + + union { + __IOM uint32_t reg; /*!< Control Register, UARTCR */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< UART enable: 0 = UART is disabled. If the UART is disabled in + the middle of transmission or reception, it completes the + current character before stopping. 1 = the UART is enabled. + Data transmission and reception occurs for either UART + signals or SIR signals depending on the setting of the + SIREN bit. */ + __IOM uint32_t SIREN : 1; /*!< SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains + LOW (no light pulse generated), and signal transitions + on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. + Data is transmitted and received on nSIROUT and SIRIN. + UARTTXD remains HIGH, in the marking state. Signal transitions + on UARTRXD or modem status inputs have no effect. This + bit has no effect if the UARTEN bit disables the UART. */ + __IOM uint32_t SIRLP : 1; /*!< SIR low-power IrDA mode. This bit selects the IrDA encoding + mode. If this bit is cleared to 0, low-level bits are transmitted + as an active high pulse with a width of 3 / 16th of the + bit period. If this bit is set to 1, low-level bits are + transmitted with a pulse width that is 3 times the period + of the IrLPBaud16 input signal, regardless of the selected + bit rate. Setting this bit uses less power, but might reduce + transmission distances. */ + uint32_t : 4; + __IOM uint32_t LBE : 1; /*!< Loopback enable. If this bit is set to 1 and the SIREN bit is + set to 1 and the SIRTEST bit in the Test Control Register, + UARTTCR is set to 1, then the nSIROUT path is inverted, + and fed through to the SIRIN path. The SIRTEST bit in the + test register must be set to 1 to override the normal half-duplex + SIR operation. This must be the requirement for accessing + the test registers during normal operation, and SIRTEST + must be cleared to 0 when loopback testing is finished. + This feature reduces the amount of external coupling required + during system test. If this bit is set to 1, and the SIRTEST + bit is set to 0, the UARTTXD path is fed through to the + UARTRXD path. In either SIR mode or UART mode, when this + bit is set, the modem outputs are also fed through to the + modem inputs. This bit is cleared to 0 on reset, to disable + loopback. */ + __IOM uint32_t TXE : 1; /*!< Transmit enable. If this bit is set to 1, the transmit section + of the UART is enabled. Data transmission occurs for either + UART signals, or SIR signals depending on the setting of + the SIREN bit. When the UART is disabled in the middle + of transmission, it completes the current character before + stopping. */ + __IOM uint32_t RXE : 1; /*!< Receive enable. If this bit is set to 1, the receive section + of the UART is enabled. Data reception occurs for either + UART signals or SIR signals depending on the setting of + the SIREN bit. When the UART is disabled in the middle + of reception, it completes the current character before + stopping. */ + __IOM uint32_t DTR : 1; /*!< Data transmit ready. This bit is the complement of the UART + data transmit ready, nUARTDTR, modem status output. That + is, when the bit is programmed to a 1 then nUARTDTR is + LOW. */ + __IOM uint32_t RTS : 1; /*!< Request to send. This bit is the complement of the UART request + to send, nUARTRTS, modem status output. That is, when the + bit is programmed to a 1 then nUARTRTS is LOW. */ + __IOM uint32_t OUT1 : 1; /*!< This bit is the complement of the UART Out1 (nUARTOut1) modem + status output. That is, when the bit is programmed to a + 1 the output is 0. For DTE this can be used as Data Carrier + Detect (DCD). */ + __IOM uint32_t OUT2 : 1; /*!< This bit is the complement of the UART Out2 (nUARTOut2) modem + status output. That is, when the bit is programmed to a + 1, the output is 0. For DTE this can be used as Ring Indicator + (RI). */ + __IOM uint32_t RTSEN : 1; /*!< RTS hardware flow control enable. If this bit is set to 1, RTS + hardware flow control is enabled. Data is only requested + when there is space in the receive FIFO for it to be received. */ + __IOM uint32_t CTSEN : 1; /*!< CTS hardware flow control enable. If this bit is set to 1, CTS + hardware flow control is enabled. Data is only transmitted + when the nUARTCTS signal is asserted. */ + uint32_t : 16; + } bit; + } UARTCR; + + union { + __IOM uint32_t reg; /*!< Interrupt FIFO Level Select Register, UARTIFLS */ + + struct { + __IOM uint32_t TXIFLSEL : 3; /*!< Transmit interrupt FIFO level select. The trigger points for + the transmit interrupt are as follows: b000 = Transmit + FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes + <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full + b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit + FIFO becomes <= 7 / 8 full b101-b111 = reserved. */ + __IOM uint32_t RXIFLSEL : 3; /*!< Receive interrupt FIFO level select. The trigger points for + the receive interrupt are as follows: b000 = Receive FIFO + becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 + / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 + = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO + becomes >= 7 / 8 full b101-b111 = reserved. */ + uint32_t : 26; + } bit; + } UARTIFLS; + + union { + __IOM uint32_t reg; /*!< Interrupt Mask Set/Clear Register, UARTIMSC */ + + struct { + __IOM uint32_t RIMIM : 1; /*!< nUARTRI modem interrupt mask. A read returns the current mask + for the UARTRIINTR interrupt. On a write of 1, the mask + of the UARTRIINTR interrupt is set. A write of 0 clears + the mask. */ + __IOM uint32_t CTSMIM : 1; /*!< nUARTCTS modem interrupt mask. A read returns the current mask + for the UARTCTSINTR interrupt. On a write of 1, the mask + of the UARTCTSINTR interrupt is set. A write of 0 clears + the mask. */ + __IOM uint32_t DCDMIM : 1; /*!< nUARTDCD modem interrupt mask. A read returns the current mask + for the UARTDCDINTR interrupt. On a write of 1, the mask + of the UARTDCDINTR interrupt is set. A write of 0 clears + the mask. */ + __IOM uint32_t DSRMIM : 1; /*!< nUARTDSR modem interrupt mask. A read returns the current mask + for the UARTDSRINTR interrupt. On a write of 1, the mask + of the UARTDSRINTR interrupt is set. A write of 0 clears + the mask. */ + __IOM uint32_t RXIM : 1; /*!< Receive interrupt mask. A read returns the current mask for + the UARTRXINTR interrupt. On a write of 1, the mask of + the UARTRXINTR interrupt is set. A write of 0 clears the + mask. */ + __IOM uint32_t TXIM : 1; /*!< Transmit interrupt mask. A read returns the current mask for + the UARTTXINTR interrupt. On a write of 1, the mask of + the UARTTXINTR interrupt is set. A write of 0 clears the + mask. */ + __IOM uint32_t RTIM : 1; /*!< Receive timeout interrupt mask. A read returns the current mask + for the UARTRTINTR interrupt. On a write of 1, the mask + of the UARTRTINTR interrupt is set. A write of 0 clears + the mask. */ + __IOM uint32_t FEIM : 1; /*!< Framing error interrupt mask. A read returns the current mask + for the UARTFEINTR interrupt. On a write of 1, the mask + of the UARTFEINTR interrupt is set. A write of 0 clears + the mask. */ + __IOM uint32_t PEIM : 1; /*!< Parity error interrupt mask. A read returns the current mask + for the UARTPEINTR interrupt. On a write of 1, the mask + of the UARTPEINTR interrupt is set. A write of 0 clears + the mask. */ + __IOM uint32_t BEIM : 1; /*!< Break error interrupt mask. A read returns the current mask + for the UARTBEINTR interrupt. On a write of 1, the mask + of the UARTBEINTR interrupt is set. A write of 0 clears + the mask. */ + __IOM uint32_t OEIM : 1; /*!< Overrun error interrupt mask. A read returns the current mask + for the UARTOEINTR interrupt. On a write of 1, the mask + of the UARTOEINTR interrupt is set. A write of 0 clears + the mask. */ + uint32_t : 21; + } bit; + } UARTIMSC; + + union { + __IOM uint32_t reg; /*!< Raw Interrupt Status Register, UARTRIS */ + + struct { + __IM uint32_t RIRMIS : 1; /*!< nUARTRI modem interrupt status. Returns the raw interrupt state + of the UARTRIINTR interrupt. */ + __IM uint32_t CTSRMIS : 1; /*!< nUARTCTS modem interrupt status. Returns the raw interrupt state + of the UARTCTSINTR interrupt. */ + __IM uint32_t DCDRMIS : 1; /*!< nUARTDCD modem interrupt status. Returns the raw interrupt state + of the UARTDCDINTR interrupt. */ + __IM uint32_t DSRRMIS : 1; /*!< nUARTDSR modem interrupt status. Returns the raw interrupt state + of the UARTDSRINTR interrupt. */ + __IM uint32_t RXRIS : 1; /*!< Receive interrupt status. Returns the raw interrupt state of + the UARTRXINTR interrupt. */ + __IM uint32_t TXRIS : 1; /*!< Transmit interrupt status. Returns the raw interrupt state of + the UARTTXINTR interrupt. */ + __IM uint32_t RTRIS : 1; /*!< Receive timeout interrupt status. Returns the raw interrupt + state of the UARTRTINTR interrupt. a */ + __IM uint32_t FERIS : 1; /*!< Framing error interrupt status. Returns the raw interrupt state + of the UARTFEINTR interrupt. */ + __IM uint32_t PERIS : 1; /*!< Parity error interrupt status. Returns the raw interrupt state + of the UARTPEINTR interrupt. */ + __IM uint32_t BERIS : 1; /*!< Break error interrupt status. Returns the raw interrupt state + of the UARTBEINTR interrupt. */ + __IM uint32_t OERIS : 1; /*!< Overrun error interrupt status. Returns the raw interrupt state + of the UARTOEINTR interrupt. */ + uint32_t : 21; + } bit; + } UARTRIS; + + union { + __IOM uint32_t reg; /*!< Masked Interrupt Status Register, UARTMIS */ + + struct { + __IM uint32_t RIMMIS : 1; /*!< nUARTRI modem masked interrupt status. Returns the masked interrupt + state of the UARTRIINTR interrupt. */ + __IM uint32_t CTSMMIS : 1; /*!< nUARTCTS modem masked interrupt status. Returns the masked interrupt + state of the UARTCTSINTR interrupt. */ + __IM uint32_t DCDMMIS : 1; /*!< nUARTDCD modem masked interrupt status. Returns the masked interrupt + state of the UARTDCDINTR interrupt. */ + __IM uint32_t DSRMMIS : 1; /*!< nUARTDSR modem masked interrupt status. Returns the masked interrupt + state of the UARTDSRINTR interrupt. */ + __IM uint32_t RXMIS : 1; /*!< Receive masked interrupt status. Returns the masked interrupt + state of the UARTRXINTR interrupt. */ + __IM uint32_t TXMIS : 1; /*!< Transmit masked interrupt status. Returns the masked interrupt + state of the UARTTXINTR interrupt. */ + __IM uint32_t RTMIS : 1; /*!< Receive timeout masked interrupt status. Returns the masked + interrupt state of the UARTRTINTR interrupt. */ + __IM uint32_t FEMIS : 1; /*!< Framing error masked interrupt status. Returns the masked interrupt + state of the UARTFEINTR interrupt. */ + __IM uint32_t PEMIS : 1; /*!< Parity error masked interrupt status. Returns the masked interrupt + state of the UARTPEINTR interrupt. */ + __IM uint32_t BEMIS : 1; /*!< Break error masked interrupt status. Returns the masked interrupt + state of the UARTBEINTR interrupt. */ + __IM uint32_t OEMIS : 1; /*!< Overrun error masked interrupt status. Returns the masked interrupt + state of the UARTOEINTR interrupt. */ + uint32_t : 21; + } bit; + } UARTMIS; + + union { + __IOM uint32_t reg; /*!< Interrupt Clear Register, UARTICR */ + + struct { + __IOM uint32_t RIMIC : 1; /*!< nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. */ + __IOM uint32_t CTSMIC : 1; /*!< nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. */ + __IOM uint32_t DCDMIC : 1; /*!< nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. */ + __IOM uint32_t DSRMIC : 1; /*!< nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. */ + __IOM uint32_t RXIC : 1; /*!< Receive interrupt clear. Clears the UARTRXINTR interrupt. */ + __IOM uint32_t TXIC : 1; /*!< Transmit interrupt clear. Clears the UARTTXINTR interrupt. */ + __IOM uint32_t RTIC : 1; /*!< Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. */ + __IOM uint32_t FEIC : 1; /*!< Framing error interrupt clear. Clears the UARTFEINTR interrupt. */ + __IOM uint32_t PEIC : 1; /*!< Parity error interrupt clear. Clears the UARTPEINTR interrupt. */ + __IOM uint32_t BEIC : 1; /*!< Break error interrupt clear. Clears the UARTBEINTR interrupt. */ + __IOM uint32_t OEIC : 1; /*!< Overrun error interrupt clear. Clears the UARTOEINTR interrupt. */ + uint32_t : 21; + } bit; + } UARTICR; + + union { + __IOM uint32_t reg; /*!< DMA Control Register, UARTDMACR */ + + struct { + __IOM uint32_t RXDMAE : 1; /*!< Receive DMA enable. If this bit is set to 1, DMA for the receive + FIFO is enabled. */ + __IOM uint32_t TXDMAE : 1; /*!< Transmit DMA enable. If this bit is set to 1, DMA for the transmit + FIFO is enabled. */ + __IOM uint32_t DMAONERR : 1; /*!< DMA on error. If this bit is set to 1, the DMA receive request + outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when + the UART error interrupt is asserted. */ + uint32_t : 29; + } bit; + } UARTDMACR; + __IM uint32_t RESERVED2[997]; + + union { + __IOM uint32_t reg; /*!< UARTPeriphID0 Register */ + + struct { + __IM uint32_t PARTNUMBER0 : 8; /*!< These bits read back as 0x11 */ + uint32_t : 24; + } bit; + } UARTPERIPHID0; + + union { + __IOM uint32_t reg; /*!< UARTPeriphID1 Register */ + + struct { + __IM uint32_t PARTNUMBER1 : 4; /*!< These bits read back as 0x0 */ + __IM uint32_t DESIGNER0 : 4; /*!< These bits read back as 0x1 */ + uint32_t : 24; + } bit; + } UARTPERIPHID1; + + union { + __IOM uint32_t reg; /*!< UARTPeriphID2 Register */ + + struct { + __IM uint32_t DESIGNER1 : 4; /*!< These bits read back as 0x4 */ + __IM uint32_t REVISION : 4; /*!< This field depends on the revision of the UART: r1p0 0x0 r1p1 + 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 */ + uint32_t : 24; + } bit; + } UARTPERIPHID2; + + union { + __IOM uint32_t reg; /*!< UARTPeriphID3 Register */ + + struct { + __IM uint32_t CONFIGURATION : 8; /*!< These bits read back as 0x00 */ + uint32_t : 24; + } bit; + } UARTPERIPHID3; + + union { + __IOM uint32_t reg; /*!< UARTPCellID0 Register */ + + struct { + __IM uint32_t UARTPCELLID0 : 8; /*!< These bits read back as 0x0D */ + uint32_t : 24; + } bit; + } UARTPCELLID0; + + union { + __IOM uint32_t reg; /*!< UARTPCellID1 Register */ + + struct { + __IM uint32_t UARTPCELLID1 : 8; /*!< These bits read back as 0xF0 */ + uint32_t : 24; + } bit; + } UARTPCELLID1; + + union { + __IOM uint32_t reg; /*!< UARTPCellID2 Register */ + + struct { + __IM uint32_t UARTPCELLID2 : 8; /*!< These bits read back as 0x05 */ + uint32_t : 24; + } bit; + } UARTPCELLID2; + + union { + __IOM uint32_t reg; /*!< UARTPCellID3 Register */ + + struct { + __IM uint32_t UARTPCELLID3 : 8; /*!< These bits read back as 0xB1 */ + uint32_t : 24; + } bit; + } UARTPCELLID3; +} UART0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ ROSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ROSC (ROSC) + */ + +typedef struct { /*!< ROSC Structure */ + + union { + __IOM uint32_t reg; /*!< Ring Oscillator control */ + + struct { + __IOM uint32_t FREQ_RANGE : 12; /*!< Controls the number of delay stages in the ROSC ring LOW uses + stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages + 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used + because its frequency exceeds design specifications The + clock output will not glitch when changing the range up + one step at a time The clock output will glitch when changing + the range down Note: the values here are gray coded which + is why HIGH comes before TOOHIGH */ + __IOM uint32_t ENABLE : 12; /*!< On power-up this field is initialised to ENABLE The system clock + must be switched to another source before setting this + field to DISABLE otherwise the chip will lock up The 12-bit + code is intended to give some protection against accidental + writes. An invalid setting will enable the oscillator. */ + uint32_t : 8; + } bit; + } CTRL; + + union { + __IOM uint32_t reg; /*!< The FREQA & FREQB registers control the frequency by controlling + the drive strength of each stage The drive strength has + 4 levels determined by the number of bits set Increasing + the number of bits set increases the drive strength and + increases the oscillation frequency 0 bits set is the default + drive strength 1 bit set doubles the drive strength 2 bits + set triples drive strength 3 bits set quadruples drive + strength For frequency randomisation set both DS0_RANDOM=1 + & DS1_RANDOM=1 */ + + struct { + __IOM uint32_t DS0 : 3; /*!< Stage 0 drive strength */ + __IOM uint32_t DS0_RANDOM : 1; /*!< Randomises the stage 0 drive strength */ + __IOM uint32_t DS1 : 3; /*!< Stage 1 drive strength */ + __IOM uint32_t DS1_RANDOM : 1; /*!< Randomises the stage 1 drive strength */ + __IOM uint32_t DS2 : 3; /*!< Stage 2 drive strength */ + uint32_t : 1; + __IOM uint32_t DS3 : 3; /*!< Stage 3 drive strength */ + uint32_t : 1; + __IOM uint32_t PASSWD : 16; /*!< Set to 0x9696 to apply the settings Any other value in this + field will set all drive strengths to 0 */ + } bit; + } FREQA; + + union { + __IOM uint32_t reg; /*!< For a detailed description see freqa register */ + + struct { + __IOM uint32_t DS4 : 3; /*!< Stage 4 drive strength */ + uint32_t : 1; + __IOM uint32_t DS5 : 3; /*!< Stage 5 drive strength */ + uint32_t : 1; + __IOM uint32_t DS6 : 3; /*!< Stage 6 drive strength */ + uint32_t : 1; + __IOM uint32_t DS7 : 3; /*!< Stage 7 drive strength */ + uint32_t : 1; + __IOM uint32_t PASSWD : 16; /*!< Set to 0x9696 to apply the settings Any other value in this + field will set all drive strengths to 0 */ + } bit; + } FREQB; + + union { + __IOM uint32_t reg; /*!< Loads a value to the LFSR randomiser */ + + struct { + __IOM uint32_t SEED : 32; /*!< SEED */ + } bit; + } RANDOM; + + union { + __IOM uint32_t reg; /*!< Ring Oscillator pause control */ + + struct { + __IOM uint32_t DORMANT : 32; /*!< This is used to save power by pausing the ROSC On power-up this + field is initialised to WAKE An invalid write will also + select WAKE Warning: setup the irq before selecting dormant + mode */ + } bit; + } DORMANT; + + union { + __IOM uint32_t reg; /*!< Controls the output divider */ + + struct { + __IOM uint32_t DIV : 16; /*!< set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 + divides by div any other value sets div=128 this register + resets to div=32 */ + uint32_t : 16; + } bit; + } DIV; + + union { + __IOM uint32_t reg; /*!< Controls the phase shifted output */ + + struct { + __IOM uint32_t SHIFT : 2; /*!< phase shift the phase-shifted output by SHIFT input clocks this + can be changed on-the-fly must be set to 0 before setting + div=1 */ + __IOM uint32_t FLIP : 1; /*!< invert the phase-shifted output this is ignored when div=1 */ + __IOM uint32_t ENABLE : 1; /*!< enable the phase-shifted output this can be changed on-the-fly */ + __IOM uint32_t PASSWD : 8; /*!< set to 0xaa any other value enables the output with shift=0 */ + uint32_t : 20; + } bit; + } PHASE; + + union { + __IOM uint32_t reg; /*!< Ring Oscillator Status */ + + struct { + uint32_t : 12; + __IM uint32_t ENABLED : 1; /*!< Oscillator is enabled but not necessarily running and stable + this resets to 0 but transitions to 1 during chip startup */ + uint32_t : 3; + __IM uint32_t DIV_RUNNING : 1; /*!< post-divider is running this resets to 0 but transitions to + 1 during chip startup */ + uint32_t : 7; + __IOM uint32_t BADWRITE : 1; /*!< An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE + or FREQA or FREQB or DIV or PHASE or DORMANT */ + uint32_t : 6; + __IM uint32_t STABLE : 1; /*!< Oscillator is running and stable */ + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< This just reads the state of the oscillator output so randomness + is compromised if the ring oscillator is stopped or run + at a harmonic of the bus frequency */ + + struct { + __IM uint32_t RANDOMBIT : 1; /*!< RANDOMBIT */ + uint32_t : 31; + } bit; + } RANDOMBIT; + + union { + __IOM uint32_t reg; /*!< A down counter running at the ROSC frequency which counts to + zero and stops. To start the counter write a non-zero value. + Can be used for short software pauses when setting up time + sensitive hardware. */ + + struct { + __IOM uint32_t COUNT : 16; /*!< COUNT */ + uint32_t : 16; + } bit; + } COUNT; +} ROSC_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ POWMAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use (POWMAN) + */ + +typedef struct { /*!< POWMAN Structure */ + + union { + __IOM uint32_t reg; /*!< Indicates a bad password has been used */ + + struct { + __IOM uint32_t BADPASSWD : 1; /*!< BADPASSWD */ + uint32_t : 31; + } bit; + } BADPASSWD; + + union { + __IOM uint32_t reg; /*!< Voltage Regulator Control */ + + struct { + uint32_t : 4; + __IOM uint32_t HT_TH : 3; /*!< high temperature protection threshold regulator power transistors + are disabled when junction temperature exceeds threshold + 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C + 101 - 125C 110 - 135C 111 - 150C */ + uint32_t : 1; + __IOM uint32_t DISABLE_VOLTAGE_LIMIT : 1; /*!< 0=not disabled, 1=enabled */ + uint32_t : 3; + __IOM uint32_t ISOLATE : 1; /*!< isolates the VREG control interface 0 - not isolated (default) + 1 - isolated */ + __IOM uint32_t UNLOCK : 1; /*!< unlocks the VREG control interface after power up 0 - Locked + (default) 1 - Unlocked It cannot be relocked when it is + unlocked. */ + uint32_t : 1; + __IOM uint32_t RST_N : 1; /*!< returns the regulator to its startup settings 0 - reset 1 - + not reset (default) */ + uint32_t : 16; + } bit; + } VREG_CTRL; + + union { + __IOM uint32_t reg; /*!< Voltage Regulator Status */ + + struct { + __IM uint32_t STARTUP : 1; /*!< startup status 0=startup complete, 1=starting up */ + uint32_t : 3; + __IM uint32_t VOUT_OK : 1; /*!< output regulation status 0=not in regulation, 1=in regulation */ + uint32_t : 27; + } bit; + } VREG_STS; + + union { + __IOM uint32_t reg; /*!< Voltage Regulator Settings */ + + struct { + uint32_t : 1; + __IOM uint32_t HIZ : 1; /*!< high impedance mode select 0=not in high impedance mode, 1=in + high impedance mode */ + uint32_t : 2; + __IOM uint32_t VSEL : 5; /*!< output voltage select the regulator output voltage is limited + to 1.3V unless the voltage limit is disabled using the + disable_voltage_limit field in the vreg_ctrl register 00000 + - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 + - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 + - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) + 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V + 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V + 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V + 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V + 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V */ + uint32_t : 6; + __IM uint32_t UPDATE_IN_PROGRESS : 1; /*!< regulator state is being updated writes to the vreg register + will be ignored when this field is set */ + uint32_t : 16; + } bit; + } VREG; + + union { + __IOM uint32_t reg; /*!< Voltage Regulator Low Power Entry Settings */ + + struct { + uint32_t : 1; + __IOM uint32_t HIZ : 1; /*!< high impedance mode select 0=not in high impedance mode, 1=in + high impedance mode */ + __IOM uint32_t MODE : 1; /*!< selects either normal (switching) mode or low power (linear) + mode low power mode can only be selected for output voltages + up to 1.3V 0 = normal mode (switching) 1 = low power mode + (linear) */ + uint32_t : 1; + __IOM uint32_t VSEL : 5; /*!< output voltage select the regulator output voltage is limited + to 1.3V unless the voltage limit is disabled using the + disable_voltage_limit field in the vreg_ctrl register 00000 + - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 + - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 + - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) + 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V + 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V + 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V + 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V + 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V */ + uint32_t : 23; + } bit; + } VREG_LP_ENTRY; + + union { + __IOM uint32_t reg; /*!< Voltage Regulator Low Power Exit Settings */ + + struct { + uint32_t : 1; + __IOM uint32_t HIZ : 1; /*!< high impedance mode select 0=not in high impedance mode, 1=in + high impedance mode */ + __IOM uint32_t MODE : 1; /*!< selects either normal (switching) mode or low power (linear) + mode low power mode can only be selected for output voltages + up to 1.3V 0 = normal mode (switching) 1 = low power mode + (linear) */ + uint32_t : 1; + __IOM uint32_t VSEL : 5; /*!< output voltage select the regulator output voltage is limited + to 1.3V unless the voltage limit is disabled using the + disable_voltage_limit field in the vreg_ctrl register 00000 + - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 + - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 + - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) + 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V + 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V + 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V + 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V + 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V */ + uint32_t : 23; + } bit; + } VREG_LP_EXIT; + + union { + __IOM uint32_t reg; /*!< Brown-out Detection Control */ + + struct { + uint32_t : 12; + __IOM uint32_t ISOLATE : 1; /*!< isolates the brown-out detection control interface 0 - not isolated + (default) 1 - isolated */ + uint32_t : 19; + } bit; + } BOD_CTRL; + + union { + __IOM uint32_t reg; /*!< Brown-out Detection Settings */ + + struct { + __IOM uint32_t EN : 1; /*!< enable brown-out detection 0=not enabled, 1=enabled */ + uint32_t : 3; + __IOM uint32_t VSEL : 5; /*!< threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V + 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V + 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) + 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V + 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V */ + uint32_t : 23; + } bit; + } BOD; + + union { + __IOM uint32_t reg; /*!< Brown-out Detection Low Power Entry Settings */ + + struct { + __IOM uint32_t EN : 1; /*!< enable brown-out detection 0=not enabled, 1=enabled */ + uint32_t : 3; + __IOM uint32_t VSEL : 5; /*!< threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V + 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V + 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) + 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V + 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V */ + uint32_t : 23; + } bit; + } BOD_LP_ENTRY; + + union { + __IOM uint32_t reg; /*!< Brown-out Detection Low Power Exit Settings */ + + struct { + __IOM uint32_t EN : 1; /*!< enable brown-out detection 0=not enabled, 1=enabled */ + uint32_t : 3; + __IOM uint32_t VSEL : 5; /*!< threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V + 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V + 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) + 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V + 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V */ + uint32_t : 23; + } bit; + } BOD_LP_EXIT; + + union { + __IOM uint32_t reg; /*!< Low power oscillator control register. */ + + struct { + __IOM uint32_t MODE : 2; /*!< This feature has been removed */ + uint32_t : 2; + __IOM uint32_t TRIM : 6; /*!< Frequency trim - the trim step is typically 1% of the reset + frequency, but can be up to 3% */ + uint32_t : 22; + } bit; + } LPOSC; + + union { + __IOM uint32_t reg; /*!< Chip reset control and status */ + + struct { + __IOM uint32_t DOUBLE_TAP : 1; /*!< This flag is set by double-tapping RUN. It tells bootcode to + go into the bootloader. */ + uint32_t : 3; + __IOM uint32_t RESCUE_FLAG : 1; /*!< This is set by a rescue reset from the RP-AP. Its purpose is + to halt before the bootrom before booting from flash in + order to recover from a boot lock-up. The debugger can + then attach once the bootrom has been halted and flash + some working code that does not lock up. */ + uint32_t : 11; + __IM uint32_t HAD_POR : 1; /*!< Last reset was from the power-on reset This resets: double_tap + flag yes DP yes RPAP yes rescue_flag yes timer yes powman + yes swcore yes psm yes then starts the power sequencer */ + __IM uint32_t HAD_BOR : 1; /*!< Last reset was from the brown-out detection block This resets: + double_tap flag yes DP yes RPAP yes rescue_flag yes timer + yes powman yes swcore yes psm yes then starts the power + sequencer */ + __IM uint32_t HAD_RUN_LOW : 1; /*!< Last reset was from the RUN pin This resets: double_tap flag + no DP yes RPAP yes rescue_flag yes timer yes powman yes + swcore yes psm yes then starts the power sequencer */ + __IM uint32_t HAD_DP_RESET_REQ : 1; /*!< Last reset was an reset request from the arm debugger This resets: + double_tap flag no DP no RPAP no rescue_flag yes timer + yes powman yes swcore yes psm yes then starts the power + sequencer */ + uint32_t : 1; + __IM uint32_t HAD_RESCUE : 1; /*!< Last reset was a rescue reset from the debugger This resets: + double_tap flag no DP no RPAP no rescue_flag no, it sets + this flag timer yes powman yes swcore yes psm yes then + starts the power sequencer */ + __IM uint32_t HAD_WATCHDOG_RESET_POWMAN_ASYNC : 1;/*!< Last reset was a watchdog timeout which was configured to reset + the power manager asynchronously This resets: double_tap + flag no DP no RPAP no rescue_flag no timer yes powman yes + swcore yes psm yes then starts the power sequencer */ + __IM uint32_t HAD_WATCHDOG_RESET_POWMAN : 1;/*!< Last reset was a watchdog timeout which was configured to reset + the power manager This resets: double_tap flag no DP no + RPAP no rescue_flag no timer yes powman yes swcore yes + psm yes then starts the power sequencer */ + __IM uint32_t HAD_WATCHDOG_RESET_SWCORE : 1;/*!< Last reset was a watchdog timeout which was configured to reset + the switched-core This resets: double_tap flag no DP no + RPAP no rescue_flag no timer no powman no swcore yes psm + yes then starts the power sequencer */ + __IM uint32_t HAD_SWCORE_PD : 1; /*!< Last reset was a switched core powerdown This resets: double_tap + flag no DP no RPAP no rescue_flag no timer no powman no + swcore yes psm yes then starts the power sequencer */ + __IM uint32_t HAD_GLITCH_DETECT : 1; /*!< Last reset was due to a power supply glitch This resets: double_tap + flag no DP no RPAP no rescue_flag no timer no powman no + swcore no psm yes and does not change the power state */ + __IM uint32_t HAD_HZD_SYS_RESET_REQ : 1; /*!< Last reset was a system reset from the hazard debugger This + resets: double_tap flag no DP no RPAP no rescue_flag no + timer no powman no swcore no psm yes and does not change + the power state */ + __IM uint32_t HAD_WATCHDOG_RESET_RSM : 1;/*!< Last reset was a watchdog timeout which was configured to reset + the power-on state machine This resets: double_tap flag + no DP no RPAP no rescue_flag no timer no powman no swcore + no psm yes and does not change the power state */ + uint32_t : 3; + } bit; + } CHIP_RESET; + + union { + __IOM uint32_t reg; /*!< Allows a watchdog reset to reset the internal state of powman + in addition to the power-on state machine (PSM). Note that + powman ignores watchdog resets that do not select at least + the CLOCKS stage or earlier stages in the PSM. If using + these bits, it's recommended to set PSM_WDSEL to all-ones + in addition to the desired bits in this register. Failing + to select CLOCKS or earlier will result in the POWMAN_WDSEL + register having no effect. */ + + struct { + __IOM uint32_t RESET_POWMAN_ASYNC : 1; /*!< If set to 1, a watchdog reset will restore powman defaults, + reset the timer, reset the switched core domain and run + the full power-on state machine (PSM) sequence This does + not rely on clk_ref running */ + uint32_t : 3; + __IOM uint32_t RESET_POWMAN : 1; /*!< If set to 1, a watchdog reset will restore powman defaults, + reset the timer, reset the switched core power domain and + run the full power-on state machine (PSM) sequence This + relies on clk_ref running. Use reset_powman_async if that + may not be true */ + uint32_t : 3; + __IOM uint32_t RESET_SWCORE : 1; /*!< If set to 1, a watchdog reset will reset the switched core power + domain and run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect + as a power-on reset for the switched core power domain */ + uint32_t : 3; + __IOM uint32_t RESET_RSM : 1; /*!< If set to 1, a watchdog reset will run the full power-on state + machine (PSM) sequence From a user perspective it is the + same as setting RSM_WDSEL_PROC_COLD From a hardware debug + perspective it has the same effect as a reset from a glitch + detector */ + uint32_t : 19; + } bit; + } WDSEL; + + union { + __IOM uint32_t reg; /*!< For configuration of the power sequencer Writes are ignored + while POWMAN_STATE_CHANGING=1 */ + + struct { + __IOM uint32_t HW_PWRUP_SRAM1 : 1; /*!< Specifies the power state of SRAM1 when powering up swcore from + a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up 1=no change */ + __IOM uint32_t HW_PWRUP_SRAM0 : 1; /*!< Specifies the power state of SRAM0 when powering up swcore from + a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up 1=no change */ + uint32_t : 2; + __IOM uint32_t USE_VREG_LP : 1; /*!< Set to 0 to prevent automatic switching to vreg low power mode + when switched-core is powered down This setting takes effect + when the swcore is next powered down */ + __IOM uint32_t USE_VREG_HP : 1; /*!< Set to 0 to prevent automatic switching to vreg high power mode + when switched-core is powered up This setting takes effect + when the swcore is next powered up */ + __IOM uint32_t USE_BOD_LP : 1; /*!< Set to 0 to prevent automatic switching to bod low power mode + when switched-core is powered down This setting takes effect + when the swcore is next powered down */ + __IOM uint32_t USE_BOD_HP : 1; /*!< Set to 0 to prevent automatic switching to bod high power mode + when switched-core is powered up This setting takes effect + when the swcore is next powered up */ + __IOM uint32_t RUN_LPOSC_IN_LP : 1; /*!< Set to 0 to stop the low power osc when the switched-core is + powered down, which is unwise if using it to clock the + timer This setting takes effect when the swcore is next + powered down */ + uint32_t : 3; + __IOM uint32_t USE_FAST_POWCK : 1; /*!< selects the reference clock (clk_ref) as the source of the POWMAN + clock when switched-core is powered. The POWMAN clock always + switches to the slow clock (lposc) when switched-core is + powered down because the fast clock stops running. 0 always + run the POWMAN clock from the slow clock (lposc) 1 run + the POWMAN clock from the fast clock when available This + setting takes effect when a power up sequence is next run */ + uint32_t : 3; + __IM uint32_t USING_VREG_LP : 1; /*!< Indicates the voltage regulator (VREG) mode 0 = VREG high power + mode which is the default 1 = VREG low power mode */ + __IM uint32_t USING_BOD_LP : 1; /*!< Indicates the brown-out detector (BOD) mode 0 = BOD high power + mode which is the default 1 = BOD low power mode */ + uint32_t : 2; + __IM uint32_t USING_FAST_POWCK : 1; /*!< 0 indicates the POWMAN clock is running from the low power oscillator + (32kHz) 1 indicates the POWMAN clock is running from the + reference clock (2-50MHz) */ + uint32_t : 11; + } bit; + } SEQ_CFG; + + union { + __IOM uint32_t reg; /*!< This register controls the power state of the 4 power domains. + The current power state is indicated in POWMAN_STATE_CURRENT + which is read-only. To change the state, write to POWMAN_STATE_REQ. + The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds + to the power states defined in the datasheet: bit 3 = SWCORE + bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered + up 1 = powered down When POWMAN_STATE_REQ is written, the + POWMAN_STATE_WAITING flag is set while the Power Manager + determines what is required. If an invalid transition is + requested the Power Manager will still register the request + in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ + flag. It will then implement the power-up requests and + ignore the power down requests. To do nothing would risk + entering an unrecoverable lock-up state. Invalid requests + are: any combination of power up and power down requests + any request that results in swcore boing powered and xip + unpowered If the request is to power down the switched-core + domain then POWMAN_STATE_WAITING stays active until the + processors halt. During this time the POWMAN_STATE_REQ + field can be re-written to change or cancel the request. + When the power state transition begins the POWMAN_STATE_WAITING_flag + is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN + register writes are ignored until the transition completes. */ + + struct { + __IM uint32_t CURRENT : 4; /*!< CURRENT */ + __IOM uint32_t REQ : 4; /*!< REQ */ + __IOM uint32_t REQ_IGNORED : 1; /*!< REQ_IGNORED */ + __IOM uint32_t PWRUP_WHILE_WAITING : 1; /*!< Request ignored because of a pending pwrup request. See current_pwrup_req. + Note this blocks powering up AND powering down. */ + __IM uint32_t BAD_SW_REQ : 1; /*!< Bad software initiated state request. No action taken. */ + __IM uint32_t BAD_HW_REQ : 1; /*!< Bad hardware initiated state request. Went back to state 0 (i.e. + everything powered up) */ + __IM uint32_t WAITING : 1; /*!< WAITING */ + __IM uint32_t CHANGING : 1; /*!< CHANGING */ + uint32_t : 18; + } bit; + } STATE; + + union { + __IOM uint32_t reg; /*!< POW_FASTDIV */ + + struct { + __IOM uint32_t POW_FASTDIV : 11; /*!< divides the POWMAN clock to provide a tick for the delay module + and state machines when clk_pow is running from the slow + clock it is not divided when clk_pow is running from the + fast clock it is divided by tick_div */ + uint32_t : 21; + } bit; + } POW_FASTDIV; + + union { + __IOM uint32_t reg; /*!< power state machine delays */ + + struct { + __IOM uint32_t SWCORE_STEP : 4; /*!< timing between the swcore power state machine steps measured + in units of the lposc period, 0 gives a delay of 1 unit */ + __IOM uint32_t XIP_STEP : 4; /*!< timing between the xip power state machine steps measured in + units of the lposc period, 0 gives a delay of 1 unit */ + __IOM uint32_t SRAM_STEP : 8; /*!< timing between the sram0 and sram1 power state machine steps + measured in units of the powman tick period (>=1us), 0 + gives a delay of 1 unit */ + uint32_t : 16; + } bit; + } POW_DELAY; + + union { + __IOM uint32_t reg; /*!< Configures a gpio as a power mode aware control output */ + + struct { + __IOM uint32_t GPIO_SELECT : 6; /*!< selects from gpio 0->30 set to 31 to disable this feature */ + uint32_t : 2; + __IOM uint32_t INIT : 1; /*!< INIT */ + uint32_t : 3; + __IOM uint32_t INIT_STATE : 1; /*!< INIT_STATE */ + __IOM uint32_t LP_ENTRY_STATE : 1; /*!< output level when entering the low power state */ + __IOM uint32_t LP_EXIT_STATE : 1; /*!< output level when exiting the low power state */ + uint32_t : 17; + } bit; + } EXT_CTRL0; + + union { + __IOM uint32_t reg; /*!< Configures a gpio as a power mode aware control output */ + + struct { + __IOM uint32_t GPIO_SELECT : 6; /*!< selects from gpio 0->30 set to 31 to disable this feature */ + uint32_t : 2; + __IOM uint32_t INIT : 1; /*!< INIT */ + uint32_t : 3; + __IOM uint32_t INIT_STATE : 1; /*!< INIT_STATE */ + __IOM uint32_t LP_ENTRY_STATE : 1; /*!< output level when entering the low power state */ + __IOM uint32_t LP_EXIT_STATE : 1; /*!< output level when exiting the low power state */ + uint32_t : 17; + } bit; + } EXT_CTRL1; + + union { + __IOM uint32_t reg; /*!< Select a GPIO to use as a time reference, the source can be + used to drive the low power clock at 32kHz, or to provide + a 1ms tick to the timer, or provide a 1Hz tick to the timer. + The tick selection is controlled by the POWMAN_TIMER register. */ + + struct { + __IOM uint32_t SOURCE_SEL : 2; /*!< 0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22 */ + uint32_t : 2; + __IOM uint32_t DRIVE_LPCK : 1; /*!< Use the selected GPIO to drive the 32kHz low power clock, in + place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 */ + uint32_t : 27; + } bit; + } EXT_TIME_REF; + + union { + __IOM uint32_t reg; /*!< Informs the AON Timer of the integer component of the clock + frequency when running off the LPOSC. */ + + struct { + __IOM uint32_t LPOSC_FREQ_KHZ_INT : 6; /*!< Integer component of the LPOSC or GPIO clock source frequency + in kHz. Default = 32 This field must only be written when + POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 */ + uint32_t : 26; + } bit; + } LPOSC_FREQ_KHZ_INT; + + union { + __IOM uint32_t reg; /*!< Informs the AON Timer of the fractional component of the clock + frequency when running off the LPOSC. */ + + struct { + __IOM uint32_t LPOSC_FREQ_KHZ_FRAC : 16; /*!< Fractional component of the LPOSC or GPIO clock source frequency + in kHz. Default = 0.768 This field must only be written + when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 */ + uint32_t : 16; + } bit; + } LPOSC_FREQ_KHZ_FRAC; + + union { + __IOM uint32_t reg; /*!< Informs the AON Timer of the integer component of the clock + frequency when running off the XOSC. */ + + struct { + __IOM uint32_t XOSC_FREQ_KHZ_INT : 16; /*!< Integer component of the XOSC frequency in kHz. Default = 12000 + Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 + or POWMAN_TIMER_USING_XOSC=0 */ + uint32_t : 16; + } bit; + } XOSC_FREQ_KHZ_INT; + + union { + __IOM uint32_t reg; /*!< Informs the AON Timer of the fractional component of the clock + frequency when running off the XOSC. */ + + struct { + __IOM uint32_t XOSC_FREQ_KHZ_FRAC : 16; /*!< Fractional component of the XOSC frequency in kHz. This field + must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 */ + uint32_t : 16; + } bit; + } XOSC_FREQ_KHZ_FRAC; + + union { + __IOM uint32_t reg; /*!< SET_TIME_63TO48 */ + + struct { + __IOM uint32_t SET_TIME_63TO48 : 16; /*!< For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UP + ER and POWMAN_READ_TIME_LOWER. This field must only be + written when POWMAN_TIMER_RUN=0 */ + uint32_t : 16; + } bit; + } SET_TIME_63TO48; + + union { + __IOM uint32_t reg; /*!< SET_TIME_47TO32 */ + + struct { + __IOM uint32_t SET_TIME_47TO32 : 16; /*!< For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UP + ER and POWMAN_READ_TIME_LOWER. This field must only be + written when POWMAN_TIMER_RUN=0 */ + uint32_t : 16; + } bit; + } SET_TIME_47TO32; + + union { + __IOM uint32_t reg; /*!< SET_TIME_31TO16 */ + + struct { + __IOM uint32_t SET_TIME_31TO16 : 16; /*!< For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UP + ER and POWMAN_READ_TIME_LOWER. This field must only be + written when POWMAN_TIMER_RUN=0 */ + uint32_t : 16; + } bit; + } SET_TIME_31TO16; + + union { + __IOM uint32_t reg; /*!< SET_TIME_15TO0 */ + + struct { + __IOM uint32_t SET_TIME_15TO0 : 16; /*!< For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UP + ER and POWMAN_READ_TIME_LOWER. This field must only be + written when POWMAN_TIMER_RUN=0 */ + uint32_t : 16; + } bit; + } SET_TIME_15TO0; + + union { + __IOM uint32_t reg; /*!< READ_TIME_UPPER */ + + struct { + __IM uint32_t READ_TIME_UPPER : 32; /*!< For reading bits 63:32 of the timer. When reading all 64 bits + it is possible for the LOWER count to rollover during the + read. It is recommended to read UPPER, then LOWER, then + re-read UPPER and, if it has changed, re-read LOWER. */ + } bit; + } READ_TIME_UPPER; + + union { + __IOM uint32_t reg; /*!< READ_TIME_LOWER */ + + struct { + __IM uint32_t READ_TIME_LOWER : 32; /*!< For reading bits 31:0 of the timer. */ + } bit; + } READ_TIME_LOWER; + + union { + __IOM uint32_t reg; /*!< ALARM_TIME_63TO48 */ + + struct { + __IOM uint32_t ALARM_TIME_63TO48 : 16; /*!< This field must only be written when POWMAN_ALARM_ENAB=0 */ + uint32_t : 16; + } bit; + } ALARM_TIME_63TO48; + + union { + __IOM uint32_t reg; /*!< ALARM_TIME_47TO32 */ + + struct { + __IOM uint32_t ALARM_TIME_47TO32 : 16; /*!< This field must only be written when POWMAN_ALARM_ENAB=0 */ + uint32_t : 16; + } bit; + } ALARM_TIME_47TO32; + + union { + __IOM uint32_t reg; /*!< ALARM_TIME_31TO16 */ + + struct { + __IOM uint32_t ALARM_TIME_31TO16 : 16; /*!< This field must only be written when POWMAN_ALARM_ENAB=0 */ + uint32_t : 16; + } bit; + } ALARM_TIME_31TO16; + + union { + __IOM uint32_t reg; /*!< ALARM_TIME_15TO0 */ + + struct { + __IOM uint32_t ALARM_TIME_15TO0 : 16; /*!< This field must only be written when POWMAN_ALARM_ENAB=0 */ + uint32_t : 16; + } bit; + } ALARM_TIME_15TO0; + + union { + __IOM uint32_t reg; /*!< TIMER */ + + struct { + __IOM uint32_t NONSEC_WRITE : 1; /*!< Control whether Non-secure software can write to the timer registers. + All other registers are hardwired to be inaccessible to + Non-secure. */ + __IOM uint32_t RUN : 1; /*!< Timer enable. Setting this bit causes the timer to begin counting + up from its current value. Clearing this bit stops the + timer from counting. Before enabling the timer, set the + POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure + the count rate, and initialise the current time by writing + to SET_TIME_63TO48 through SET_TIME_15TO0. You must not + write to the SET_TIME_x registers when the timer is running. + Once configured, start the timer by setting POWMAN_TIMER_RUN=1. + This will start the timer running from the LPOSC. When + the XOSC is available switch the reference clock to XOSC + then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 */ + __OM uint32_t CLEAR : 1; /*!< Clears the timer, does not disable the timer and does not affect + the alarm. This control can be written at any time. */ + uint32_t : 1; + __IOM uint32_t ALARM_ENAB : 1; /*!< Enables the alarm. The alarm must be disabled while writing + the alarm time. */ + __IOM uint32_t PWRUP_ON_ALARM : 1; /*!< Alarm wakes the chip from low power mode */ + __IOM uint32_t ALARM : 1; /*!< Alarm has fired. Write to 1 to clear the alarm. */ + uint32_t : 1; + __OM uint32_t USE_LPOSC : 1; /*!< Switch to lposc as the source of the 1kHz timer tick */ + __OM uint32_t USE_XOSC : 1; /*!< switch to xosc as the source of the 1kHz timer tick */ + __OM uint32_t USE_GPIO_1KHZ : 1; /*!< switch to gpio as the source of the 1kHz timer tick */ + uint32_t : 2; + __IOM uint32_t USE_GPIO_1HZ : 1; /*!< Selects the gpio source as the reference for the sec counter. + The msec counter will continue to use the lposc or xosc + reference. */ + uint32_t : 2; + __IM uint32_t USING_XOSC : 1; /*!< Timer is running from xosc */ + __IM uint32_t USING_LPOSC : 1; /*!< Timer is running from lposc */ + __IM uint32_t USING_GPIO_1KHZ : 1; /*!< Timer is running from a 1khz gpio source */ + __IM uint32_t USING_GPIO_1HZ : 1; /*!< Timer is synchronised to a 1hz gpio source */ + uint32_t : 12; + } bit; + } TIMER; + + union { + __IOM uint32_t reg; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + + struct { + __IOM uint32_t SOURCE : 6; /*!< SOURCE */ + __IOM uint32_t ENABLE : 1; /*!< Set to 1 to enable the wakeup source. Set to 0 to disable the + wakeup source and clear a pending wakeup event. If using + edge detect a latched edge needs to be cleared by writing + 1 to the status register also. */ + __IOM uint32_t DIRECTION : 1; /*!< DIRECTION */ + __IOM uint32_t MODE : 1; /*!< Edge or level detect. Edge will detect a 0 to 1 transition (or + 1 to 0 transition). Level will detect a 1 or 0. Both types + of event get latched into the current_pwrup_req register. */ + __IOM uint32_t STATUS : 1; /*!< Status of gpio wakeup. Write to 1 to clear a latched edge detect. */ + __IM uint32_t RAW_STATUS : 1; /*!< Value of selected gpio pin (only if enable == 1) */ + uint32_t : 21; + } bit; + } PWRUP0; + + union { + __IOM uint32_t reg; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + + struct { + __IOM uint32_t SOURCE : 6; /*!< SOURCE */ + __IOM uint32_t ENABLE : 1; /*!< Set to 1 to enable the wakeup source. Set to 0 to disable the + wakeup source and clear a pending wakeup event. If using + edge detect a latched edge needs to be cleared by writing + 1 to the status register also. */ + __IOM uint32_t DIRECTION : 1; /*!< DIRECTION */ + __IOM uint32_t MODE : 1; /*!< Edge or level detect. Edge will detect a 0 to 1 transition (or + 1 to 0 transition). Level will detect a 1 or 0. Both types + of event get latched into the current_pwrup_req register. */ + __IOM uint32_t STATUS : 1; /*!< Status of gpio wakeup. Write to 1 to clear a latched edge detect. */ + __IM uint32_t RAW_STATUS : 1; /*!< Value of selected gpio pin (only if enable == 1) */ + uint32_t : 21; + } bit; + } PWRUP1; + + union { + __IOM uint32_t reg; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + + struct { + __IOM uint32_t SOURCE : 6; /*!< SOURCE */ + __IOM uint32_t ENABLE : 1; /*!< Set to 1 to enable the wakeup source. Set to 0 to disable the + wakeup source and clear a pending wakeup event. If using + edge detect a latched edge needs to be cleared by writing + 1 to the status register also. */ + __IOM uint32_t DIRECTION : 1; /*!< DIRECTION */ + __IOM uint32_t MODE : 1; /*!< Edge or level detect. Edge will detect a 0 to 1 transition (or + 1 to 0 transition). Level will detect a 1 or 0. Both types + of event get latched into the current_pwrup_req register. */ + __IOM uint32_t STATUS : 1; /*!< Status of gpio wakeup. Write to 1 to clear a latched edge detect. */ + __IM uint32_t RAW_STATUS : 1; /*!< Value of selected gpio pin (only if enable == 1) */ + uint32_t : 21; + } bit; + } PWRUP2; + + union { + __IOM uint32_t reg; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + + struct { + __IOM uint32_t SOURCE : 6; /*!< SOURCE */ + __IOM uint32_t ENABLE : 1; /*!< Set to 1 to enable the wakeup source. Set to 0 to disable the + wakeup source and clear a pending wakeup event. If using + edge detect a latched edge needs to be cleared by writing + 1 to the status register also. */ + __IOM uint32_t DIRECTION : 1; /*!< DIRECTION */ + __IOM uint32_t MODE : 1; /*!< Edge or level detect. Edge will detect a 0 to 1 transition (or + 1 to 0 transition). Level will detect a 1 or 0. Both types + of event get latched into the current_pwrup_req register. */ + __IOM uint32_t STATUS : 1; /*!< Status of gpio wakeup. Write to 1 to clear a latched edge detect. */ + __IM uint32_t RAW_STATUS : 1; /*!< Value of selected gpio pin (only if enable == 1) */ + uint32_t : 21; + } bit; + } PWRUP3; + + union { + __IOM uint32_t reg; /*!< Indicates current powerup request state pwrup events can be + cleared by removing the enable from the pwrup register. + The alarm pwrup req can be cleared by clearing timer.alarm_enab + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup + 6 = alarm_pwrup */ + + struct { + __IM uint32_t CURRENT_PWRUP_REQ : 7; /*!< CURRENT_PWRUP_REQ */ + uint32_t : 25; + } bit; + } CURRENT_PWRUP_REQ; + + union { + __IOM uint32_t reg; /*!< Indicates which pwrup source triggered the last switched-core + power up 0 = chip reset, for the source of the last reset + see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 + 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup */ + + struct { + __IM uint32_t LAST_SWCORE_PWRUP : 7; /*!< LAST_SWCORE_PWRUP */ + uint32_t : 25; + } bit; + } LAST_SWCORE_PWRUP; + + union { + __IOM uint32_t reg; /*!< DBG_PWRCFG */ + + struct { + __IOM uint32_t IGNORE : 1; /*!< Ignore pwrup req from debugger. If pwrup req is asserted then + this will prevent power down and set powerdown blocked. + Set ignore to stop paying attention to pwrup_req */ + uint32_t : 31; + } bit; + } DBG_PWRCFG; + + union { + __IOM uint32_t reg; /*!< Tell the bootrom to ignore the BOOT0..3 registers following + the next RSM reset (e.g. the next core power down/up). + If an early boot stage has soft-locked some OTP pages in + order to protect their contents from later stages, there + is a risk that Secure code running at a later stage can + unlock the pages by powering the core up and down. This + register can be used to ensure that the bootloader runs + as normal on the next power up, preventing Secure code + at a later stage from accessing OTP in its unlocked state. + Should be used in conjunction with the OTP BOOTDIS register. */ + + struct { + __IOM uint32_t NOW : 1; /*!< When powman resets the RSM, the current value of BOOTDIS_NEXT + is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + The bootrom checks this flag before reading the BOOT0..3 + registers. If it is set, the bootrom clears it, and ignores + the BOOT registers. This prevents Secure software from + diverting the boot path before a bootloader has had the + chance to soft lock OTP pages containing sensitive data. */ + __IOM uint32_t NEXT : 1; /*!< This flag always ORs writes into its current contents. It can + be set but not cleared by software. The BOOTDIS_NEXT bit + is OR'd into the BOOTDIS_NOW bit when the core is powered + down. Simultaneously, the BOOTDIS_NEXT bit is cleared. + Setting this bit means that the BOOT0..3 registers will + be ignored following the next reset of the RSM by powman. + This flag should be set by an early boot stage that has + soft-locked OTP pages, to prevent later stages from unlocking + it by power cycling. */ + uint32_t : 30; + } bit; + } BOOTDIS; + + union { + __IOM uint32_t reg; /*!< DBGCONFIG */ + + struct { + __IOM uint32_t DP_INSTID : 4; /*!< Configure DP instance ID for SWD multidrop selection. Recommend + that this is NOT changed until you require debug access + in multi-chip environment */ + uint32_t : 28; + } bit; + } DBGCONFIG; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t SCRATCH0 : 32; /*!< SCRATCH0 */ + } bit; + } SCRATCH0; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t SCRATCH1 : 32; /*!< SCRATCH1 */ + } bit; + } SCRATCH1; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t SCRATCH2 : 32; /*!< SCRATCH2 */ + } bit; + } SCRATCH2; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t SCRATCH3 : 32; /*!< SCRATCH3 */ + } bit; + } SCRATCH3; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t SCRATCH4 : 32; /*!< SCRATCH4 */ + } bit; + } SCRATCH4; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t SCRATCH5 : 32; /*!< SCRATCH5 */ + } bit; + } SCRATCH5; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t SCRATCH6 : 32; /*!< SCRATCH6 */ + } bit; + } SCRATCH6; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t SCRATCH7 : 32; /*!< SCRATCH7 */ + } bit; + } SCRATCH7; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t BOOT0 : 32; /*!< BOOT0 */ + } bit; + } BOOT0; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t BOOT1 : 32; /*!< BOOT1 */ + } bit; + } BOOT1; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t BOOT2 : 32; /*!< BOOT2 */ + } bit; + } BOOT2; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists in low power mode */ + + struct { + __IOM uint32_t BOOT3 : 32; /*!< BOOT3 */ + } bit; + } BOOT3; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IOM uint32_t VREG_OUTPUT_LOW : 1; /*!< VREG_OUTPUT_LOW */ + __IM uint32_t TIMER : 1; /*!< TIMER */ + __IM uint32_t STATE_REQ_IGNORED : 1; /*!< Source is state.req_ignored */ + __IM uint32_t PWRUP_WHILE_WAITING : 1; /*!< Source is state.pwrup_while_waiting */ + uint32_t : 28; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable */ + + struct { + __IOM uint32_t VREG_OUTPUT_LOW : 1; /*!< VREG_OUTPUT_LOW */ + __IOM uint32_t TIMER : 1; /*!< TIMER */ + __IOM uint32_t STATE_REQ_IGNORED : 1; /*!< Source is state.req_ignored */ + __IOM uint32_t PWRUP_WHILE_WAITING : 1; /*!< Source is state.pwrup_while_waiting */ + uint32_t : 28; + } bit; + } INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force */ + + struct { + __IOM uint32_t VREG_OUTPUT_LOW : 1; /*!< VREG_OUTPUT_LOW */ + __IOM uint32_t TIMER : 1; /*!< TIMER */ + __IOM uint32_t STATE_REQ_IGNORED : 1; /*!< Source is state.req_ignored */ + __IOM uint32_t PWRUP_WHILE_WAITING : 1; /*!< Source is state.pwrup_while_waiting */ + uint32_t : 28; + } bit; + } INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing */ + + struct { + __IM uint32_t VREG_OUTPUT_LOW : 1; /*!< VREG_OUTPUT_LOW */ + __IM uint32_t TIMER : 1; /*!< TIMER */ + __IM uint32_t STATE_REQ_IGNORED : 1; /*!< Source is state.req_ignored */ + __IM uint32_t PWRUP_WHILE_WAITING : 1; /*!< Source is state.pwrup_while_waiting */ + uint32_t : 28; + } bit; + } INTS; +} POWMAN_Type; /*!< Size = 240 (0xf0) */ + + + +/* =========================================================================================================================== */ +/* ================ WATCHDOG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief WATCHDOG (WATCHDOG) + */ + +typedef struct { /*!< WATCHDOG Structure */ + + union { + __IOM uint32_t reg; /*!< Watchdog control The rst_wdsel register determines which subsystems + are reset when the watchdog is triggered. The watchdog + can be triggered in software. */ + + struct { + __IM uint32_t TIME : 24; /*!< Indicates the time in usec before a watchdog reset will be triggered */ + __IOM uint32_t PAUSE_JTAG : 1; /*!< Pause the watchdog timer when JTAG is accessing the bus fabric */ + __IOM uint32_t PAUSE_DBG0 : 1; /*!< Pause the watchdog timer when processor 0 is in debug mode */ + __IOM uint32_t PAUSE_DBG1 : 1; /*!< Pause the watchdog timer when processor 1 is in debug mode */ + uint32_t : 3; + __IOM uint32_t ENABLE : 1; /*!< When not enabled the watchdog timer is paused */ + __OM uint32_t TRIGGER : 1; /*!< Trigger a watchdog reset */ + } bit; + } CTRL; + + union { + __IOM uint32_t reg; /*!< Load the watchdog timer. The maximum setting is 0xffffff which + corresponds to approximately 16 seconds. */ + + struct { + __OM uint32_t LOAD : 24; /*!< LOAD */ + uint32_t : 8; + } bit; + } LOAD; + + union { + __IOM uint32_t reg; /*!< Logs the reason for the last reset. Both bits are zero for the + case of a hardware reset. Additionally, as of RP2350, a + debugger warm reset of either core (SYSRESETREQ or hartreset) + will also clear the watchdog reason register, so that software + loaded under the debugger following a watchdog timeout + will not continue to see the timeout condition. */ + + struct { + __IM uint32_t TIMER : 1; /*!< TIMER */ + __IM uint32_t FORCE : 1; /*!< FORCE */ + uint32_t : 30; + } bit; + } REASON; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists through soft reset of + the chip. */ + + struct { + __IOM uint32_t SCRATCH0 : 32; /*!< SCRATCH0 */ + } bit; + } SCRATCH0; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists through soft reset of + the chip. */ + + struct { + __IOM uint32_t SCRATCH1 : 32; /*!< SCRATCH1 */ + } bit; + } SCRATCH1; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists through soft reset of + the chip. */ + + struct { + __IOM uint32_t SCRATCH2 : 32; /*!< SCRATCH2 */ + } bit; + } SCRATCH2; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists through soft reset of + the chip. */ + + struct { + __IOM uint32_t SCRATCH3 : 32; /*!< SCRATCH3 */ + } bit; + } SCRATCH3; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists through soft reset of + the chip. */ + + struct { + __IOM uint32_t SCRATCH4 : 32; /*!< SCRATCH4 */ + } bit; + } SCRATCH4; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists through soft reset of + the chip. */ + + struct { + __IOM uint32_t SCRATCH5 : 32; /*!< SCRATCH5 */ + } bit; + } SCRATCH5; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists through soft reset of + the chip. */ + + struct { + __IOM uint32_t SCRATCH6 : 32; /*!< SCRATCH6 */ + } bit; + } SCRATCH6; + + union { + __IOM uint32_t reg; /*!< Scratch register. Information persists through soft reset of + the chip. */ + + struct { + __IOM uint32_t SCRATCH7 : 32; /*!< SCRATCH7 */ + } bit; + } SCRATCH7; +} WATCHDOG_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA with separate read and write masters (DMA) + */ + +typedef struct { /*!< DMA Structure */ + + union { + __IOM uint32_t reg; /*!< DMA Channel 0 Read Address pointer */ + + struct { + __IOM uint32_t CH0_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH0_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 0 Write Address pointer */ + + struct { + __IOM uint32_t CH0_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH0_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 0 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH0_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 0 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH0_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 CTRL register */ + + struct { + __IOM uint32_t CH0_AL1_CTRL : 32; /*!< CH0_AL1_CTRL */ + } bit; + } CH0_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 READ_ADDR register */ + + struct { + __IOM uint32_t CH0_AL1_READ_ADDR : 32; /*!< CH0_AL1_READ_ADDR */ + } bit; + } CH0_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH0_AL1_WRITE_ADDR : 32; /*!< CH0_AL1_WRITE_ADDR */ + } bit; + } CH0_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG : 32;/*!< CH0_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH0_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 CTRL register */ + + struct { + __IOM uint32_t CH0_AL2_CTRL : 32; /*!< CH0_AL2_CTRL */ + } bit; + } CH0_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH0_AL2_TRANS_COUNT : 32; /*!< CH0_AL2_TRANS_COUNT */ + } bit; + } CH0_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 READ_ADDR register */ + + struct { + __IOM uint32_t CH0_AL2_READ_ADDR : 32; /*!< CH0_AL2_READ_ADDR */ + } bit; + } CH0_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG : 32;/*!< CH0_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH0_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 CTRL register */ + + struct { + __IOM uint32_t CH0_AL3_CTRL : 32; /*!< CH0_AL3_CTRL */ + } bit; + } CH0_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH0_AL3_WRITE_ADDR : 32; /*!< CH0_AL3_WRITE_ADDR */ + } bit; + } CH0_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH0_AL3_TRANS_COUNT : 32; /*!< CH0_AL3_TRANS_COUNT */ + } bit; + } CH0_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 0 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH0_AL3_READ_ADDR_TRIG : 32;/*!< CH0_AL3_READ_ADDR_TRIG */ + } bit; + } CH0_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 1 Read Address pointer */ + + struct { + __IOM uint32_t CH1_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 1 Write Address pointer */ + + struct { + __IOM uint32_t CH1_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 1 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH1_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 1 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH1_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 CTRL register */ + + struct { + __IOM uint32_t CH1_AL1_CTRL : 32; /*!< CH1_AL1_CTRL */ + } bit; + } CH1_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 READ_ADDR register */ + + struct { + __IOM uint32_t CH1_AL1_READ_ADDR : 32; /*!< CH1_AL1_READ_ADDR */ + } bit; + } CH1_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH1_AL1_WRITE_ADDR : 32; /*!< CH1_AL1_WRITE_ADDR */ + } bit; + } CH1_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG : 32;/*!< CH1_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH1_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 CTRL register */ + + struct { + __IOM uint32_t CH1_AL2_CTRL : 32; /*!< CH1_AL2_CTRL */ + } bit; + } CH1_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH1_AL2_TRANS_COUNT : 32; /*!< CH1_AL2_TRANS_COUNT */ + } bit; + } CH1_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 READ_ADDR register */ + + struct { + __IOM uint32_t CH1_AL2_READ_ADDR : 32; /*!< CH1_AL2_READ_ADDR */ + } bit; + } CH1_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG : 32;/*!< CH1_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH1_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 CTRL register */ + + struct { + __IOM uint32_t CH1_AL3_CTRL : 32; /*!< CH1_AL3_CTRL */ + } bit; + } CH1_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH1_AL3_WRITE_ADDR : 32; /*!< CH1_AL3_WRITE_ADDR */ + } bit; + } CH1_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH1_AL3_TRANS_COUNT : 32; /*!< CH1_AL3_TRANS_COUNT */ + } bit; + } CH1_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 1 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH1_AL3_READ_ADDR_TRIG : 32;/*!< CH1_AL3_READ_ADDR_TRIG */ + } bit; + } CH1_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 2 Read Address pointer */ + + struct { + __IOM uint32_t CH2_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 2 Write Address pointer */ + + struct { + __IOM uint32_t CH2_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH2_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 2 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 2 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH2_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 CTRL register */ + + struct { + __IOM uint32_t CH2_AL1_CTRL : 32; /*!< CH2_AL1_CTRL */ + } bit; + } CH2_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 READ_ADDR register */ + + struct { + __IOM uint32_t CH2_AL1_READ_ADDR : 32; /*!< CH2_AL1_READ_ADDR */ + } bit; + } CH2_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH2_AL1_WRITE_ADDR : 32; /*!< CH2_AL1_WRITE_ADDR */ + } bit; + } CH2_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG : 32;/*!< CH2_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH2_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 CTRL register */ + + struct { + __IOM uint32_t CH2_AL2_CTRL : 32; /*!< CH2_AL2_CTRL */ + } bit; + } CH2_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH2_AL2_TRANS_COUNT : 32; /*!< CH2_AL2_TRANS_COUNT */ + } bit; + } CH2_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 READ_ADDR register */ + + struct { + __IOM uint32_t CH2_AL2_READ_ADDR : 32; /*!< CH2_AL2_READ_ADDR */ + } bit; + } CH2_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG : 32;/*!< CH2_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH2_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 CTRL register */ + + struct { + __IOM uint32_t CH2_AL3_CTRL : 32; /*!< CH2_AL3_CTRL */ + } bit; + } CH2_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH2_AL3_WRITE_ADDR : 32; /*!< CH2_AL3_WRITE_ADDR */ + } bit; + } CH2_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH2_AL3_TRANS_COUNT : 32; /*!< CH2_AL3_TRANS_COUNT */ + } bit; + } CH2_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 2 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH2_AL3_READ_ADDR_TRIG : 32;/*!< CH2_AL3_READ_ADDR_TRIG */ + } bit; + } CH2_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 3 Read Address pointer */ + + struct { + __IOM uint32_t CH3_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH3_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 3 Write Address pointer */ + + struct { + __IOM uint32_t CH3_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 3 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 3 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH3_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 CTRL register */ + + struct { + __IOM uint32_t CH3_AL1_CTRL : 32; /*!< CH3_AL1_CTRL */ + } bit; + } CH3_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 READ_ADDR register */ + + struct { + __IOM uint32_t CH3_AL1_READ_ADDR : 32; /*!< CH3_AL1_READ_ADDR */ + } bit; + } CH3_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH3_AL1_WRITE_ADDR : 32; /*!< CH3_AL1_WRITE_ADDR */ + } bit; + } CH3_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG : 32;/*!< CH3_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH3_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 CTRL register */ + + struct { + __IOM uint32_t CH3_AL2_CTRL : 32; /*!< CH3_AL2_CTRL */ + } bit; + } CH3_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH3_AL2_TRANS_COUNT : 32; /*!< CH3_AL2_TRANS_COUNT */ + } bit; + } CH3_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 READ_ADDR register */ + + struct { + __IOM uint32_t CH3_AL2_READ_ADDR : 32; /*!< CH3_AL2_READ_ADDR */ + } bit; + } CH3_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG : 32;/*!< CH3_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH3_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 CTRL register */ + + struct { + __IOM uint32_t CH3_AL3_CTRL : 32; /*!< CH3_AL3_CTRL */ + } bit; + } CH3_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH3_AL3_WRITE_ADDR : 32; /*!< CH3_AL3_WRITE_ADDR */ + } bit; + } CH3_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH3_AL3_TRANS_COUNT : 32; /*!< CH3_AL3_TRANS_COUNT */ + } bit; + } CH3_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 3 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH3_AL3_READ_ADDR_TRIG : 32;/*!< CH3_AL3_READ_ADDR_TRIG */ + } bit; + } CH3_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 4 Read Address pointer */ + + struct { + __IOM uint32_t CH4_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH4_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 4 Write Address pointer */ + + struct { + __IOM uint32_t CH4_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH4_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 4 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH4_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 4 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH4_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 CTRL register */ + + struct { + __IOM uint32_t CH4_AL1_CTRL : 32; /*!< CH4_AL1_CTRL */ + } bit; + } CH4_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 READ_ADDR register */ + + struct { + __IOM uint32_t CH4_AL1_READ_ADDR : 32; /*!< CH4_AL1_READ_ADDR */ + } bit; + } CH4_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH4_AL1_WRITE_ADDR : 32; /*!< CH4_AL1_WRITE_ADDR */ + } bit; + } CH4_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG : 32;/*!< CH4_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH4_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 CTRL register */ + + struct { + __IOM uint32_t CH4_AL2_CTRL : 32; /*!< CH4_AL2_CTRL */ + } bit; + } CH4_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH4_AL2_TRANS_COUNT : 32; /*!< CH4_AL2_TRANS_COUNT */ + } bit; + } CH4_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 READ_ADDR register */ + + struct { + __IOM uint32_t CH4_AL2_READ_ADDR : 32; /*!< CH4_AL2_READ_ADDR */ + } bit; + } CH4_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG : 32;/*!< CH4_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH4_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 CTRL register */ + + struct { + __IOM uint32_t CH4_AL3_CTRL : 32; /*!< CH4_AL3_CTRL */ + } bit; + } CH4_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH4_AL3_WRITE_ADDR : 32; /*!< CH4_AL3_WRITE_ADDR */ + } bit; + } CH4_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH4_AL3_TRANS_COUNT : 32; /*!< CH4_AL3_TRANS_COUNT */ + } bit; + } CH4_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 4 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH4_AL3_READ_ADDR_TRIG : 32;/*!< CH4_AL3_READ_ADDR_TRIG */ + } bit; + } CH4_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 5 Read Address pointer */ + + struct { + __IOM uint32_t CH5_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH5_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 5 Write Address pointer */ + + struct { + __IOM uint32_t CH5_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH5_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 5 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH5_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 5 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH5_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 CTRL register */ + + struct { + __IOM uint32_t CH5_AL1_CTRL : 32; /*!< CH5_AL1_CTRL */ + } bit; + } CH5_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 READ_ADDR register */ + + struct { + __IOM uint32_t CH5_AL1_READ_ADDR : 32; /*!< CH5_AL1_READ_ADDR */ + } bit; + } CH5_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH5_AL1_WRITE_ADDR : 32; /*!< CH5_AL1_WRITE_ADDR */ + } bit; + } CH5_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG : 32;/*!< CH5_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH5_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 CTRL register */ + + struct { + __IOM uint32_t CH5_AL2_CTRL : 32; /*!< CH5_AL2_CTRL */ + } bit; + } CH5_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH5_AL2_TRANS_COUNT : 32; /*!< CH5_AL2_TRANS_COUNT */ + } bit; + } CH5_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 READ_ADDR register */ + + struct { + __IOM uint32_t CH5_AL2_READ_ADDR : 32; /*!< CH5_AL2_READ_ADDR */ + } bit; + } CH5_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG : 32;/*!< CH5_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH5_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 CTRL register */ + + struct { + __IOM uint32_t CH5_AL3_CTRL : 32; /*!< CH5_AL3_CTRL */ + } bit; + } CH5_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH5_AL3_WRITE_ADDR : 32; /*!< CH5_AL3_WRITE_ADDR */ + } bit; + } CH5_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH5_AL3_TRANS_COUNT : 32; /*!< CH5_AL3_TRANS_COUNT */ + } bit; + } CH5_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 5 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH5_AL3_READ_ADDR_TRIG : 32;/*!< CH5_AL3_READ_ADDR_TRIG */ + } bit; + } CH5_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 6 Read Address pointer */ + + struct { + __IOM uint32_t CH6_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH6_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 6 Write Address pointer */ + + struct { + __IOM uint32_t CH6_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH6_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 6 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH6_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 6 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH6_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 CTRL register */ + + struct { + __IOM uint32_t CH6_AL1_CTRL : 32; /*!< CH6_AL1_CTRL */ + } bit; + } CH6_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 READ_ADDR register */ + + struct { + __IOM uint32_t CH6_AL1_READ_ADDR : 32; /*!< CH6_AL1_READ_ADDR */ + } bit; + } CH6_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH6_AL1_WRITE_ADDR : 32; /*!< CH6_AL1_WRITE_ADDR */ + } bit; + } CH6_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG : 32;/*!< CH6_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH6_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 CTRL register */ + + struct { + __IOM uint32_t CH6_AL2_CTRL : 32; /*!< CH6_AL2_CTRL */ + } bit; + } CH6_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH6_AL2_TRANS_COUNT : 32; /*!< CH6_AL2_TRANS_COUNT */ + } bit; + } CH6_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 READ_ADDR register */ + + struct { + __IOM uint32_t CH6_AL2_READ_ADDR : 32; /*!< CH6_AL2_READ_ADDR */ + } bit; + } CH6_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG : 32;/*!< CH6_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH6_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 CTRL register */ + + struct { + __IOM uint32_t CH6_AL3_CTRL : 32; /*!< CH6_AL3_CTRL */ + } bit; + } CH6_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH6_AL3_WRITE_ADDR : 32; /*!< CH6_AL3_WRITE_ADDR */ + } bit; + } CH6_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH6_AL3_TRANS_COUNT : 32; /*!< CH6_AL3_TRANS_COUNT */ + } bit; + } CH6_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 6 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH6_AL3_READ_ADDR_TRIG : 32;/*!< CH6_AL3_READ_ADDR_TRIG */ + } bit; + } CH6_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 7 Read Address pointer */ + + struct { + __IOM uint32_t CH7_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH7_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 7 Write Address pointer */ + + struct { + __IOM uint32_t CH7_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH7_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 7 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH7_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 7 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH7_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 CTRL register */ + + struct { + __IOM uint32_t CH7_AL1_CTRL : 32; /*!< CH7_AL1_CTRL */ + } bit; + } CH7_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 READ_ADDR register */ + + struct { + __IOM uint32_t CH7_AL1_READ_ADDR : 32; /*!< CH7_AL1_READ_ADDR */ + } bit; + } CH7_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH7_AL1_WRITE_ADDR : 32; /*!< CH7_AL1_WRITE_ADDR */ + } bit; + } CH7_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG : 32;/*!< CH7_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH7_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 CTRL register */ + + struct { + __IOM uint32_t CH7_AL2_CTRL : 32; /*!< CH7_AL2_CTRL */ + } bit; + } CH7_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH7_AL2_TRANS_COUNT : 32; /*!< CH7_AL2_TRANS_COUNT */ + } bit; + } CH7_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 READ_ADDR register */ + + struct { + __IOM uint32_t CH7_AL2_READ_ADDR : 32; /*!< CH7_AL2_READ_ADDR */ + } bit; + } CH7_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG : 32;/*!< CH7_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH7_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 CTRL register */ + + struct { + __IOM uint32_t CH7_AL3_CTRL : 32; /*!< CH7_AL3_CTRL */ + } bit; + } CH7_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH7_AL3_WRITE_ADDR : 32; /*!< CH7_AL3_WRITE_ADDR */ + } bit; + } CH7_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH7_AL3_TRANS_COUNT : 32; /*!< CH7_AL3_TRANS_COUNT */ + } bit; + } CH7_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 7 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH7_AL3_READ_ADDR_TRIG : 32;/*!< CH7_AL3_READ_ADDR_TRIG */ + } bit; + } CH7_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 8 Read Address pointer */ + + struct { + __IOM uint32_t CH8_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH8_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 8 Write Address pointer */ + + struct { + __IOM uint32_t CH8_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH8_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 8 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH8_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 8 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH8_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 CTRL register */ + + struct { + __IOM uint32_t CH8_AL1_CTRL : 32; /*!< CH8_AL1_CTRL */ + } bit; + } CH8_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 READ_ADDR register */ + + struct { + __IOM uint32_t CH8_AL1_READ_ADDR : 32; /*!< CH8_AL1_READ_ADDR */ + } bit; + } CH8_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH8_AL1_WRITE_ADDR : 32; /*!< CH8_AL1_WRITE_ADDR */ + } bit; + } CH8_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG : 32;/*!< CH8_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH8_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 CTRL register */ + + struct { + __IOM uint32_t CH8_AL2_CTRL : 32; /*!< CH8_AL2_CTRL */ + } bit; + } CH8_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH8_AL2_TRANS_COUNT : 32; /*!< CH8_AL2_TRANS_COUNT */ + } bit; + } CH8_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 READ_ADDR register */ + + struct { + __IOM uint32_t CH8_AL2_READ_ADDR : 32; /*!< CH8_AL2_READ_ADDR */ + } bit; + } CH8_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG : 32;/*!< CH8_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH8_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 CTRL register */ + + struct { + __IOM uint32_t CH8_AL3_CTRL : 32; /*!< CH8_AL3_CTRL */ + } bit; + } CH8_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH8_AL3_WRITE_ADDR : 32; /*!< CH8_AL3_WRITE_ADDR */ + } bit; + } CH8_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH8_AL3_TRANS_COUNT : 32; /*!< CH8_AL3_TRANS_COUNT */ + } bit; + } CH8_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 8 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH8_AL3_READ_ADDR_TRIG : 32;/*!< CH8_AL3_READ_ADDR_TRIG */ + } bit; + } CH8_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 9 Read Address pointer */ + + struct { + __IOM uint32_t CH9_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH9_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 9 Write Address pointer */ + + struct { + __IOM uint32_t CH9_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH9_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 9 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH9_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 9 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH9_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 CTRL register */ + + struct { + __IOM uint32_t CH9_AL1_CTRL : 32; /*!< CH9_AL1_CTRL */ + } bit; + } CH9_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 READ_ADDR register */ + + struct { + __IOM uint32_t CH9_AL1_READ_ADDR : 32; /*!< CH9_AL1_READ_ADDR */ + } bit; + } CH9_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH9_AL1_WRITE_ADDR : 32; /*!< CH9_AL1_WRITE_ADDR */ + } bit; + } CH9_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG : 32;/*!< CH9_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH9_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 CTRL register */ + + struct { + __IOM uint32_t CH9_AL2_CTRL : 32; /*!< CH9_AL2_CTRL */ + } bit; + } CH9_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH9_AL2_TRANS_COUNT : 32; /*!< CH9_AL2_TRANS_COUNT */ + } bit; + } CH9_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 READ_ADDR register */ + + struct { + __IOM uint32_t CH9_AL2_READ_ADDR : 32; /*!< CH9_AL2_READ_ADDR */ + } bit; + } CH9_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG : 32;/*!< CH9_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH9_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 CTRL register */ + + struct { + __IOM uint32_t CH9_AL3_CTRL : 32; /*!< CH9_AL3_CTRL */ + } bit; + } CH9_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH9_AL3_WRITE_ADDR : 32; /*!< CH9_AL3_WRITE_ADDR */ + } bit; + } CH9_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH9_AL3_TRANS_COUNT : 32; /*!< CH9_AL3_TRANS_COUNT */ + } bit; + } CH9_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 9 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH9_AL3_READ_ADDR_TRIG : 32;/*!< CH9_AL3_READ_ADDR_TRIG */ + } bit; + } CH9_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 10 Read Address pointer */ + + struct { + __IOM uint32_t CH10_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH10_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 10 Write Address pointer */ + + struct { + __IOM uint32_t CH10_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH10_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 10 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH10_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 10 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH10_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 CTRL register */ + + struct { + __IOM uint32_t CH10_AL1_CTRL : 32; /*!< CH10_AL1_CTRL */ + } bit; + } CH10_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 READ_ADDR register */ + + struct { + __IOM uint32_t CH10_AL1_READ_ADDR : 32; /*!< CH10_AL1_READ_ADDR */ + } bit; + } CH10_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH10_AL1_WRITE_ADDR : 32; /*!< CH10_AL1_WRITE_ADDR */ + } bit; + } CH10_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + + struct { + __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG : 32;/*!< CH10_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH10_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 CTRL register */ + + struct { + __IOM uint32_t CH10_AL2_CTRL : 32; /*!< CH10_AL2_CTRL */ + } bit; + } CH10_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH10_AL2_TRANS_COUNT : 32; /*!< CH10_AL2_TRANS_COUNT */ + } bit; + } CH10_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 READ_ADDR register */ + + struct { + __IOM uint32_t CH10_AL2_READ_ADDR : 32; /*!< CH10_AL2_READ_ADDR */ + } bit; + } CH10_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG : 32;/*!< CH10_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH10_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 CTRL register */ + + struct { + __IOM uint32_t CH10_AL3_CTRL : 32; /*!< CH10_AL3_CTRL */ + } bit; + } CH10_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH10_AL3_WRITE_ADDR : 32; /*!< CH10_AL3_WRITE_ADDR */ + } bit; + } CH10_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH10_AL3_TRANS_COUNT : 32; /*!< CH10_AL3_TRANS_COUNT */ + } bit; + } CH10_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 10 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH10_AL3_READ_ADDR_TRIG : 32;/*!< CH10_AL3_READ_ADDR_TRIG */ + } bit; + } CH10_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 11 Read Address pointer */ + + struct { + __IOM uint32_t CH11_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH11_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 11 Write Address pointer */ + + struct { + __IOM uint32_t CH11_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH11_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 11 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH11_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 11 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH11_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 CTRL register */ + + struct { + __IOM uint32_t CH11_AL1_CTRL : 32; /*!< CH11_AL1_CTRL */ + } bit; + } CH11_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 READ_ADDR register */ + + struct { + __IOM uint32_t CH11_AL1_READ_ADDR : 32; /*!< CH11_AL1_READ_ADDR */ + } bit; + } CH11_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH11_AL1_WRITE_ADDR : 32; /*!< CH11_AL1_WRITE_ADDR */ + } bit; + } CH11_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + + struct { + __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG : 32;/*!< CH11_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH11_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 CTRL register */ + + struct { + __IOM uint32_t CH11_AL2_CTRL : 32; /*!< CH11_AL2_CTRL */ + } bit; + } CH11_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH11_AL2_TRANS_COUNT : 32; /*!< CH11_AL2_TRANS_COUNT */ + } bit; + } CH11_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 READ_ADDR register */ + + struct { + __IOM uint32_t CH11_AL2_READ_ADDR : 32; /*!< CH11_AL2_READ_ADDR */ + } bit; + } CH11_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG : 32;/*!< CH11_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH11_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 CTRL register */ + + struct { + __IOM uint32_t CH11_AL3_CTRL : 32; /*!< CH11_AL3_CTRL */ + } bit; + } CH11_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH11_AL3_WRITE_ADDR : 32; /*!< CH11_AL3_WRITE_ADDR */ + } bit; + } CH11_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH11_AL3_TRANS_COUNT : 32; /*!< CH11_AL3_TRANS_COUNT */ + } bit; + } CH11_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 11 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH11_AL3_READ_ADDR_TRIG : 32;/*!< CH11_AL3_READ_ADDR_TRIG */ + } bit; + } CH11_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 12 Read Address pointer */ + + struct { + __IOM uint32_t CH12_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH12_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 12 Write Address pointer */ + + struct { + __IOM uint32_t CH12_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH12_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 12 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH12_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 12 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH12_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 CTRL register */ + + struct { + __IOM uint32_t CH12_AL1_CTRL : 32; /*!< CH12_AL1_CTRL */ + } bit; + } CH12_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 READ_ADDR register */ + + struct { + __IOM uint32_t CH12_AL1_READ_ADDR : 32; /*!< CH12_AL1_READ_ADDR */ + } bit; + } CH12_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH12_AL1_WRITE_ADDR : 32; /*!< CH12_AL1_WRITE_ADDR */ + } bit; + } CH12_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + + struct { + __IOM uint32_t CH12_AL1_TRANS_COUNT_TRIG : 32;/*!< CH12_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH12_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 CTRL register */ + + struct { + __IOM uint32_t CH12_AL2_CTRL : 32; /*!< CH12_AL2_CTRL */ + } bit; + } CH12_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH12_AL2_TRANS_COUNT : 32; /*!< CH12_AL2_TRANS_COUNT */ + } bit; + } CH12_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 READ_ADDR register */ + + struct { + __IOM uint32_t CH12_AL2_READ_ADDR : 32; /*!< CH12_AL2_READ_ADDR */ + } bit; + } CH12_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH12_AL2_WRITE_ADDR_TRIG : 32;/*!< CH12_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH12_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 CTRL register */ + + struct { + __IOM uint32_t CH12_AL3_CTRL : 32; /*!< CH12_AL3_CTRL */ + } bit; + } CH12_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH12_AL3_WRITE_ADDR : 32; /*!< CH12_AL3_WRITE_ADDR */ + } bit; + } CH12_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH12_AL3_TRANS_COUNT : 32; /*!< CH12_AL3_TRANS_COUNT */ + } bit; + } CH12_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 12 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH12_AL3_READ_ADDR_TRIG : 32;/*!< CH12_AL3_READ_ADDR_TRIG */ + } bit; + } CH12_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 13 Read Address pointer */ + + struct { + __IOM uint32_t CH13_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH13_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 13 Write Address pointer */ + + struct { + __IOM uint32_t CH13_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH13_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 13 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH13_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 13 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH13_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 CTRL register */ + + struct { + __IOM uint32_t CH13_AL1_CTRL : 32; /*!< CH13_AL1_CTRL */ + } bit; + } CH13_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 READ_ADDR register */ + + struct { + __IOM uint32_t CH13_AL1_READ_ADDR : 32; /*!< CH13_AL1_READ_ADDR */ + } bit; + } CH13_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH13_AL1_WRITE_ADDR : 32; /*!< CH13_AL1_WRITE_ADDR */ + } bit; + } CH13_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + + struct { + __IOM uint32_t CH13_AL1_TRANS_COUNT_TRIG : 32;/*!< CH13_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH13_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 CTRL register */ + + struct { + __IOM uint32_t CH13_AL2_CTRL : 32; /*!< CH13_AL2_CTRL */ + } bit; + } CH13_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH13_AL2_TRANS_COUNT : 32; /*!< CH13_AL2_TRANS_COUNT */ + } bit; + } CH13_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 READ_ADDR register */ + + struct { + __IOM uint32_t CH13_AL2_READ_ADDR : 32; /*!< CH13_AL2_READ_ADDR */ + } bit; + } CH13_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH13_AL2_WRITE_ADDR_TRIG : 32;/*!< CH13_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH13_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 CTRL register */ + + struct { + __IOM uint32_t CH13_AL3_CTRL : 32; /*!< CH13_AL3_CTRL */ + } bit; + } CH13_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH13_AL3_WRITE_ADDR : 32; /*!< CH13_AL3_WRITE_ADDR */ + } bit; + } CH13_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH13_AL3_TRANS_COUNT : 32; /*!< CH13_AL3_TRANS_COUNT */ + } bit; + } CH13_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 13 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH13_AL3_READ_ADDR_TRIG : 32;/*!< CH13_AL3_READ_ADDR_TRIG */ + } bit; + } CH13_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 14 Read Address pointer */ + + struct { + __IOM uint32_t CH14_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH14_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 14 Write Address pointer */ + + struct { + __IOM uint32_t CH14_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH14_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 14 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH14_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 14 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH14_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 CTRL register */ + + struct { + __IOM uint32_t CH14_AL1_CTRL : 32; /*!< CH14_AL1_CTRL */ + } bit; + } CH14_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 READ_ADDR register */ + + struct { + __IOM uint32_t CH14_AL1_READ_ADDR : 32; /*!< CH14_AL1_READ_ADDR */ + } bit; + } CH14_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH14_AL1_WRITE_ADDR : 32; /*!< CH14_AL1_WRITE_ADDR */ + } bit; + } CH14_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + + struct { + __IOM uint32_t CH14_AL1_TRANS_COUNT_TRIG : 32;/*!< CH14_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH14_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 CTRL register */ + + struct { + __IOM uint32_t CH14_AL2_CTRL : 32; /*!< CH14_AL2_CTRL */ + } bit; + } CH14_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH14_AL2_TRANS_COUNT : 32; /*!< CH14_AL2_TRANS_COUNT */ + } bit; + } CH14_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 READ_ADDR register */ + + struct { + __IOM uint32_t CH14_AL2_READ_ADDR : 32; /*!< CH14_AL2_READ_ADDR */ + } bit; + } CH14_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH14_AL2_WRITE_ADDR_TRIG : 32;/*!< CH14_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH14_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 CTRL register */ + + struct { + __IOM uint32_t CH14_AL3_CTRL : 32; /*!< CH14_AL3_CTRL */ + } bit; + } CH14_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH14_AL3_WRITE_ADDR : 32; /*!< CH14_AL3_WRITE_ADDR */ + } bit; + } CH14_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH14_AL3_TRANS_COUNT : 32; /*!< CH14_AL3_TRANS_COUNT */ + } bit; + } CH14_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 14 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH14_AL3_READ_ADDR_TRIG : 32;/*!< CH14_AL3_READ_ADDR_TRIG */ + } bit; + } CH14_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< DMA Channel 15 Read Address pointer */ + + struct { + __IOM uint32_t CH15_READ_ADDR : 32; /*!< This register updates automatically each time a read completes. + The current value is the next address to be read by this + channel. */ + } bit; + } CH15_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 15 Write Address pointer */ + + struct { + __IOM uint32_t CH15_WRITE_ADDR : 32; /*!< This register updates automatically each time a write completes. + The current value is the next address to be written by + this channel. */ + } bit; + } CH15_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< DMA Channel 15 Transfer Count */ + + struct { + __IOM uint32_t COUNT : 28; /*!< 28-bit transfer count (256 million transfers maximum). Program + the number of bus transfers a channel will perform before + halting. Note that, if transfers are larger than one byte + in size, this is not equal to the number of bytes transferred + (see CTRL_DATA_SIZE). When the channel is active, reading + this register shows the number of transfers remaining, + updating automatically each time a write transfer completes. + Writing this register sets the RELOAD value for the transfer + counter. Each time this channel is triggered, the RELOAD + value is copied into the live transfer counter. The channel + can be started multiple times, and will perform the same + number of transfers each time, as programmed by most recent + write. The RELOAD value can be observed at CHx_DBG_TCR. + If TRANS_COUNT is used as a trigger, the written value + is used immediately as the length of the new transfer sequence, + as well as being written to RELOAD. */ + __IOM uint32_t MODE : 4; /*!< When MODE is 0x0, the transfer count decrements with each transfer + until 0, and then the channel triggers the next channel + indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer + count decrements with each transfer until 0, and then the + channel re-triggers itself, in addition to the trigger + indicated by CTRL_CHAIN_TO. This is useful for e.g. an + endless ring-buffer DMA with periodic interrupts. When + MODE is 0xf, the transfer count does not decrement. The + DMA channel performs an endless sequence of transfers, + never triggering other channels or raising interrupts, + until an ABORT is raised. All other values are reserved. */ + } bit; + } CH15_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< DMA Channel 15 Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< DMA Channel Enable. When 1, the channel will respond to triggering + events, which will cause it to become BUSY and start transferring + data. When 0, the channel will ignore triggers, stop issuing + transfers, and pause the current transfer sequence (i.e. + BUSY will remain high if already high) */ + __IOM uint32_t HIGH_PRIORITY : 1; /*!< HIGH_PRIORITY gives a channel preferential treatment in issue + scheduling: in each scheduling round, all high priority + channels are considered first, and then only a single low + priority channel, before returning to the high priority + channels. This only affects the order in which the DMA + schedules channels. The DMA's bus priority is not changed. + If the DMA is not saturated then a low priority channel + will see no loss of throughput. */ + __IOM uint32_t DATA_SIZE : 2; /*!< Set the size of each bus transfer (byte/halfword/word). READ_ADDR + and WRITE_ADDR advance by this amount (1/2/4 bytes) with + each transfer. */ + __IOM uint32_t INCR_READ : 1; /*!< If 1, the read address increments with each transfer. If 0, + each read is directed to the same, initial address. Generally + this should be disabled for peripheral-to-memory transfers. */ + __IOM uint32_t INCR_READ_REV : 1; /*!< If 1, and INCR_READ is 1, the read address is decremented rather + than incremented with each transfer. If 1, and INCR_READ + is 0, this otherwise-unused combination causes the read + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t INCR_WRITE : 1; /*!< If 1, the write address increments with each transfer. If 0, + each write is directed to the same, initial address. Generally + this should be disabled for memory-to-peripheral transfers. */ + __IOM uint32_t INCR_WRITE_REV : 1; /*!< If 1, and INCR_WRITE is 1, the write address is decremented + rather than incremented with each transfer. If 1, and INCR_WRITE + is 0, this otherwise-unused combination causes the write + address to be incremented by twice the transfer size, i.e. + skipping over alternate addresses. */ + __IOM uint32_t RING_SIZE : 4; /*!< Size of address wrap region. If 0, don't wrap. For values n + > 0, only the lower n bits of the address will change. + This wraps the address on a (1 << n) byte boundary, facilitating + access to naturally-aligned ring buffers. Ring sizes between + 2 and 32768 bytes are possible. This can apply to either + read or write addresses, based on value of RING_SEL. */ + __IOM uint32_t RING_SEL : 1; /*!< Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) + boundary. If 1, write addresses are wrapped. */ + __IOM uint32_t CHAIN_TO : 4; /*!< When this channel completes, it will trigger the channel indicated + by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Note this field resets to 0, so channels 1 and above will + chain to channel 0 by default. Set this field to avoid + this behaviour. */ + __IOM uint32_t TREQ_SEL : 6; /*!< Select a Transfer Request signal. The channel uses the transfer + request signal to pace its data transfer rate. Sources + for TREQ signals are internal (TIMERS) or external (DREQ, + a Data Request from the system). 0x0 to 0x3a -> select + DREQ n as TREQ */ + __IOM uint32_t IRQ_QUIET : 1; /*!< In QUIET mode, the channel does not generate IRQs at the end + of every transfer block. Instead, an IRQ is raised when + NULL is written to a trigger register, indicating the end + of a control block chain. This reduces the number of interrupts + to be serviced by the CPU when transferring a DMA chain + of many small control blocks. */ + __IOM uint32_t BSWAP : 1; /*!< Apply byte-swap transformation to DMA data. For byte data, this + has no effect. For halfword data, the two bytes of each + halfword are swapped. For word data, the four bytes of + each word are swapped to reverse order. */ + __IOM uint32_t SNIFF_EN : 1; /*!< If 1, this channel's data transfers are visible to the sniff + hardware, and each transfer will advance the state of the + checksum. This only applies if the sniff hardware is enabled, + and has this channel selected. This allows checksum to + be enabled or disabled on a per-control- block basis. */ + __IM uint32_t BUSY : 1; /*!< This flag goes high when the channel starts a new transfer sequence, + and low when the last transfer of that sequence completes. + Clearing EN while BUSY is high pauses the channel, and + BUSY will stay high while paused. To terminate a sequence + early (and clear the BUSY flag), see CHAN_ABORT. */ + uint32_t : 2; + __IOM uint32_t WRITE_ERROR : 1; /*!< If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus + error was encountered (will not be earlier, or more than + 5 transfers later) */ + __IOM uint32_t READ_ERROR : 1; /*!< If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error + was encountered (will not be earlier, or more than 3 transfers + later) */ + __IM uint32_t AHB_ERROR : 1; /*!< Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel + halts when it encounters any bus error, and always raises + its channel IRQ flag. */ + } bit; + } CH15_CTRL_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 CTRL register */ + + struct { + __IOM uint32_t CH15_AL1_CTRL : 32; /*!< CH15_AL1_CTRL */ + } bit; + } CH15_AL1_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 READ_ADDR register */ + + struct { + __IOM uint32_t CH15_AL1_READ_ADDR : 32; /*!< CH15_AL1_READ_ADDR */ + } bit; + } CH15_AL1_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH15_AL1_WRITE_ADDR : 32; /*!< CH15_AL1_WRITE_ADDR */ + } bit; + } CH15_AL1_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + + struct { + __IOM uint32_t CH15_AL1_TRANS_COUNT_TRIG : 32;/*!< CH15_AL1_TRANS_COUNT_TRIG */ + } bit; + } CH15_AL1_TRANS_COUNT_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 CTRL register */ + + struct { + __IOM uint32_t CH15_AL2_CTRL : 32; /*!< CH15_AL2_CTRL */ + } bit; + } CH15_AL2_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH15_AL2_TRANS_COUNT : 32; /*!< CH15_AL2_TRANS_COUNT */ + } bit; + } CH15_AL2_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 READ_ADDR register */ + + struct { + __IOM uint32_t CH15_AL2_READ_ADDR : 32; /*!< CH15_AL2_READ_ADDR */ + } bit; + } CH15_AL2_READ_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH15_AL2_WRITE_ADDR_TRIG : 32;/*!< CH15_AL2_WRITE_ADDR_TRIG */ + } bit; + } CH15_AL2_WRITE_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 CTRL register */ + + struct { + __IOM uint32_t CH15_AL3_CTRL : 32; /*!< CH15_AL3_CTRL */ + } bit; + } CH15_AL3_CTRL; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 WRITE_ADDR register */ + + struct { + __IOM uint32_t CH15_AL3_WRITE_ADDR : 32; /*!< CH15_AL3_WRITE_ADDR */ + } bit; + } CH15_AL3_WRITE_ADDR; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 TRANS_COUNT register */ + + struct { + __IOM uint32_t CH15_AL3_TRANS_COUNT : 32; /*!< CH15_AL3_TRANS_COUNT */ + } bit; + } CH15_AL3_TRANS_COUNT; + + union { + __IOM uint32_t reg; /*!< Alias for channel 15 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + + struct { + __IOM uint32_t CH15_AL3_READ_ADDR_TRIG : 32;/*!< CH15_AL3_READ_ADDR_TRIG */ + } bit; + } CH15_AL3_READ_ADDR_TRIG; + + union { + __IOM uint32_t reg; /*!< Interrupt Status (raw) */ + + struct { + __IOM uint32_t INTR : 16; /*!< Raw interrupt status for DMA Channels 0..15. Bit n corresponds + to channel n. Ignores any masking or forcing. Channel interrupts + can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + Channel interrupts can be routed to either of four system-level + IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple + system-level interrupts might be used to allow NVIC IRQ + preemption for more time-critical channels, to spread IRQ + load across different cores, or to target IRQs to different + security domains. It is also valid to ignore the multiple + IRQs, and just use INTE0/INTS0/IRQ 0. If this register + is accessed at a security/privilege level less than that + of a given channel (as defined by that channel's SECCFG_CHx + register), then that channel's interrupt status will read + as 0, ignore writes. */ + uint32_t : 16; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enables for IRQ 0 */ + + struct { + __IOM uint32_t INTE0 : 16; /*!< Set bit n to pass interrupts from channel n to DMA IRQ 0. Note + this bit has no effect if the channel security/privilege + level, defined by SECCFG_CHx, is greater than the IRQ security/privilege + defined by SECCFG_IRQ0. */ + uint32_t : 16; + } bit; + } INTE0; + + union { + __IOM uint32_t reg; /*!< Force Interrupts */ + + struct { + __IOM uint32_t INTF0 : 16; /*!< Write 1s to force the corresponding bits in INTS0. The interrupt + remains asserted until INTF0 is cleared. */ + uint32_t : 16; + } bit; + } INTF0; + + union { + __IOM uint32_t reg; /*!< Interrupt Status for IRQ 0 */ + + struct { + __IOM uint32_t INTS0 : 16; /*!< Indicates active channel interrupt requests which are currently + causing IRQ 0 to be asserted. Channel interrupts can be + cleared by writing a bit mask here. Channels with a security/privilege + (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, + and ignore writes. */ + uint32_t : 16; + } bit; + } INTS0; + + union { + __IOM uint32_t reg; /*!< Interrupt Status (raw) */ + + struct { + __IOM uint32_t INTR1 : 16; /*!< Raw interrupt status for DMA Channels 0..15. Bit n corresponds + to channel n. Ignores any masking or forcing. Channel interrupts + can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + Channel interrupts can be routed to either of four system-level + IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple + system-level interrupts might be used to allow NVIC IRQ + preemption for more time-critical channels, to spread IRQ + load across different cores, or to target IRQs to different + security domains. It is also valid to ignore the multiple + IRQs, and just use INTE0/INTS0/IRQ 0. If this register + is accessed at a security/privilege level less than that + of a given channel (as defined by that channel's SECCFG_CHx + register), then that channel's interrupt status will read + as 0, ignore writes. */ + uint32_t : 16; + } bit; + } INTR1; + + union { + __IOM uint32_t reg; /*!< Interrupt Enables for IRQ 1 */ + + struct { + __IOM uint32_t INTE1 : 16; /*!< Set bit n to pass interrupts from channel n to DMA IRQ 1. Note + this bit has no effect if the channel security/privilege + level, defined by SECCFG_CHx, is greater than the IRQ security/privilege + defined by SECCFG_IRQ1. */ + uint32_t : 16; + } bit; + } INTE1; + + union { + __IOM uint32_t reg; /*!< Force Interrupts */ + + struct { + __IOM uint32_t INTF1 : 16; /*!< Write 1s to force the corresponding bits in INTS1. The interrupt + remains asserted until INTF1 is cleared. */ + uint32_t : 16; + } bit; + } INTF1; + + union { + __IOM uint32_t reg; /*!< Interrupt Status for IRQ 1 */ + + struct { + __IOM uint32_t INTS1 : 16; /*!< Indicates active channel interrupt requests which are currently + causing IRQ 1 to be asserted. Channel interrupts can be + cleared by writing a bit mask here. Channels with a security/privilege + (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, + and ignore writes. */ + uint32_t : 16; + } bit; + } INTS1; + + union { + __IOM uint32_t reg; /*!< Interrupt Status (raw) */ + + struct { + __IOM uint32_t INTR2 : 16; /*!< Raw interrupt status for DMA Channels 0..15. Bit n corresponds + to channel n. Ignores any masking or forcing. Channel interrupts + can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + Channel interrupts can be routed to either of four system-level + IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple + system-level interrupts might be used to allow NVIC IRQ + preemption for more time-critical channels, to spread IRQ + load across different cores, or to target IRQs to different + security domains. It is also valid to ignore the multiple + IRQs, and just use INTE0/INTS0/IRQ 0. If this register + is accessed at a security/privilege level less than that + of a given channel (as defined by that channel's SECCFG_CHx + register), then that channel's interrupt status will read + as 0, ignore writes. */ + uint32_t : 16; + } bit; + } INTR2; + + union { + __IOM uint32_t reg; /*!< Interrupt Enables for IRQ 2 */ + + struct { + __IOM uint32_t INTE2 : 16; /*!< Set bit n to pass interrupts from channel n to DMA IRQ 2. Note + this bit has no effect if the channel security/privilege + level, defined by SECCFG_CHx, is greater than the IRQ security/privilege + defined by SECCFG_IRQ2. */ + uint32_t : 16; + } bit; + } INTE2; + + union { + __IOM uint32_t reg; /*!< Force Interrupts */ + + struct { + __IOM uint32_t INTF2 : 16; /*!< Write 1s to force the corresponding bits in INTS2. The interrupt + remains asserted until INTF2 is cleared. */ + uint32_t : 16; + } bit; + } INTF2; + + union { + __IOM uint32_t reg; /*!< Interrupt Status for IRQ 2 */ + + struct { + __IOM uint32_t INTS2 : 16; /*!< Indicates active channel interrupt requests which are currently + causing IRQ 2 to be asserted. Channel interrupts can be + cleared by writing a bit mask here. Channels with a security/privilege + (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, + and ignore writes. */ + uint32_t : 16; + } bit; + } INTS2; + + union { + __IOM uint32_t reg; /*!< Interrupt Status (raw) */ + + struct { + __IOM uint32_t INTR3 : 16; /*!< Raw interrupt status for DMA Channels 0..15. Bit n corresponds + to channel n. Ignores any masking or forcing. Channel interrupts + can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + Channel interrupts can be routed to either of four system-level + IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple + system-level interrupts might be used to allow NVIC IRQ + preemption for more time-critical channels, to spread IRQ + load across different cores, or to target IRQs to different + security domains. It is also valid to ignore the multiple + IRQs, and just use INTE0/INTS0/IRQ 0. If this register + is accessed at a security/privilege level less than that + of a given channel (as defined by that channel's SECCFG_CHx + register), then that channel's interrupt status will read + as 0, ignore writes. */ + uint32_t : 16; + } bit; + } INTR3; + + union { + __IOM uint32_t reg; /*!< Interrupt Enables for IRQ 3 */ + + struct { + __IOM uint32_t INTE3 : 16; /*!< Set bit n to pass interrupts from channel n to DMA IRQ 3. Note + this bit has no effect if the channel security/privilege + level, defined by SECCFG_CHx, is greater than the IRQ security/privilege + defined by SECCFG_IRQ3. */ + uint32_t : 16; + } bit; + } INTE3; + + union { + __IOM uint32_t reg; /*!< Force Interrupts */ + + struct { + __IOM uint32_t INTF3 : 16; /*!< Write 1s to force the corresponding bits in INTS3. The interrupt + remains asserted until INTF3 is cleared. */ + uint32_t : 16; + } bit; + } INTF3; + + union { + __IOM uint32_t reg; /*!< Interrupt Status for IRQ 3 */ + + struct { + __IOM uint32_t INTS3 : 16; /*!< Indicates active channel interrupt requests which are currently + causing IRQ 3 to be asserted. Channel interrupts can be + cleared by writing a bit mask here. Channels with a security/privilege + (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, + and ignore writes. */ + uint32_t : 16; + } bit; + } INTS3; + + union { + __IOM uint32_t reg; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + + struct { + __IOM uint32_t Y : 16; /*!< Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional + timer. */ + __IOM uint32_t X : 16; /*!< Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional + timer. */ + } bit; + } TIMER0; + + union { + __IOM uint32_t reg; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + + struct { + __IOM uint32_t Y : 16; /*!< Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional + timer. */ + __IOM uint32_t X : 16; /*!< Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional + timer. */ + } bit; + } TIMER1; + + union { + __IOM uint32_t reg; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + + struct { + __IOM uint32_t Y : 16; /*!< Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional + timer. */ + __IOM uint32_t X : 16; /*!< Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional + timer. */ + } bit; + } TIMER2; + + union { + __IOM uint32_t reg; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + + struct { + __IOM uint32_t Y : 16; /*!< Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional + timer. */ + __IOM uint32_t X : 16; /*!< Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional + timer. */ + } bit; + } TIMER3; + + union { + __IOM uint32_t reg; /*!< Trigger one or more channels simultaneously */ + + struct { + __OM uint32_t MULTI_CHAN_TRIGGER : 16; /*!< Each bit in this register corresponds to a DMA channel. Writing + a 1 to the relevant bit is the same as writing to that + channel's trigger register; the channel will start if it + is currently enabled and not already busy. */ + uint32_t : 16; + } bit; + } MULTI_CHAN_TRIGGER; + + union { + __IOM uint32_t reg; /*!< Sniffer Control */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable sniffer */ + __IOM uint32_t DMACH : 4; /*!< DMA channel for Sniffer to observe */ + __IOM uint32_t CALC : 4; /*!< CALC */ + __IOM uint32_t BSWAP : 1; /*!< Locally perform a byte reverse on the sniffed data, before feeding + into checksum. Note that the sniff hardware is downstream + of the DMA channel byteswap performed in the read master: + if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, + their effects cancel from the sniffer's point of view. */ + __IOM uint32_t OUT_REV : 1; /*!< If set, the result appears bit-reversed when read. This does + not affect the way the checksum is calculated; the result + is transformed on-the-fly between the result register and + the bus. */ + __IOM uint32_t OUT_INV : 1; /*!< If set, the result appears inverted (bitwise complement) when + read. This does not affect the way the checksum is calculated; + the result is transformed on-the-fly between the result + register and the bus. */ + uint32_t : 20; + } bit; + } SNIFF_CTRL; + + union { + __IOM uint32_t reg; /*!< Data accumulator for sniff hardware */ + + struct { + __IOM uint32_t SNIFF_DATA : 32; /*!< Write an initial seed value here before starting a DMA transfer + on the channel indicated by SNIFF_CTRL_DMACH. The hardware + will update this register each time it observes a read + from the indicated channel. Once the channel completes, + the final result can be read from this register. */ + } bit; + } SNIFF_DATA; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< Debug RAF, WAF, TDF levels */ + + struct { + __IM uint32_t TDF_LVL : 8; /*!< Current Transfer-Data-FIFO fill level */ + __IM uint32_t WAF_LVL : 8; /*!< Current Write-Address-FIFO fill level */ + __IM uint32_t RAF_LVL : 8; /*!< Current Read-Address-FIFO fill level */ + uint32_t : 8; + } bit; + } FIFO_LEVELS; + + union { + __IOM uint32_t reg; /*!< Abort an in-progress transfer sequence on one or more channels */ + + struct { + __OM uint32_t CHAN_ABORT : 16; /*!< Each bit corresponds to a channel. Writing a 1 aborts whatever + transfer sequence is in progress on that channel. The bit + will remain high until any in-flight transfers have been + flushed through the address and data FIFOs. After writing, + this register must be polled until it returns all-zero. + Until this point, it is unsafe to restart the channel. */ + uint32_t : 16; + } bit; + } CHAN_ABORT; + + union { + __IOM uint32_t reg; /*!< The number of channels this DMA instance is equipped with. This + DMA supports up to 16 hardware channels, but can be configured + with as few as one, to minimise silicon area. */ + + struct { + __IM uint32_t N_CHANNELS : 5; /*!< N_CHANNELS */ + uint32_t : 27; + } bit; + } N_CHANNELS; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 0. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH0; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 1. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH1; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 2. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH2; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 3. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH3; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 4. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH4; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 5. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH5; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 6. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH6; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 7. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH7; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 8. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH8; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 9. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH9; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 10. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH10; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 11. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH11; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 12. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH12; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 13. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH13; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 14. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH14; + + union { + __IOM uint32_t reg; /*!< Security configuration for channel 15. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged channel. If 1, this channel performs Privileged bus + accesses. If 0, it performs Unprivileged bus accesses. + If 1, this channel is controllable only from a Privileged + context of the same Secure/Non-secure level, or any context + of a higher Secure/Non-secure level. */ + __IOM uint32_t S : 1; /*!< Secure channel. If 1, this channel performs Secure bus accesses. + If 0, it performs Non-secure bus accesses. If 1, this channel + is controllable only from a Secure context. */ + __IOM uint32_t LOCK : 1; /*!< LOCK is 0 at reset, and is set to 1 automatically upon a successful + write to this channel's control registers. That is, a write + to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + Once its LOCK bit is set, this register becomes read-only. + A failed write, for example due to the write's privilege + being lower than that specified in the channel's SECCFG + register, will not set the LOCK bit. */ + uint32_t : 29; + } bit; + } SECCFG_CH15; + + union { + __IOM uint32_t reg; /*!< Security configuration for IRQ 0. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged IRQ. If 1, this IRQ's control registers can only + be accessed from a Privileged context. If 0, this IRQ's + control registers can be accessed from an Unprivileged + context, but Privileged channels (as per SECCFG_CHx) are + masked from the IRQ status, and this IRQ's registers can + not be used to acknowledge the channel interrupts of Privileged + channels. */ + __IOM uint32_t S : 1; /*!< Secure IRQ. If 1, this IRQ's control registers can only be accessed + from a Secure context. If 0, this IRQ's control registers + can be accessed from a Non-secure context, but Secure channels + (as per SECCFG_CHx) are masked from the IRQ status, and + this IRQ's registers can not be used to acknowledge the + channel interrupts of Secure channels. */ + uint32_t : 30; + } bit; + } SECCFG_IRQ0; + + union { + __IOM uint32_t reg; /*!< Security configuration for IRQ 1. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged IRQ. If 1, this IRQ's control registers can only + be accessed from a Privileged context. If 0, this IRQ's + control registers can be accessed from an Unprivileged + context, but Privileged channels (as per SECCFG_CHx) are + masked from the IRQ status, and this IRQ's registers can + not be used to acknowledge the channel interrupts of Privileged + channels. */ + __IOM uint32_t S : 1; /*!< Secure IRQ. If 1, this IRQ's control registers can only be accessed + from a Secure context. If 0, this IRQ's control registers + can be accessed from a Non-secure context, but Secure channels + (as per SECCFG_CHx) are masked from the IRQ status, and + this IRQ's registers can not be used to acknowledge the + channel interrupts of Secure channels. */ + uint32_t : 30; + } bit; + } SECCFG_IRQ1; + + union { + __IOM uint32_t reg; /*!< Security configuration for IRQ 2. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged IRQ. If 1, this IRQ's control registers can only + be accessed from a Privileged context. If 0, this IRQ's + control registers can be accessed from an Unprivileged + context, but Privileged channels (as per SECCFG_CHx) are + masked from the IRQ status, and this IRQ's registers can + not be used to acknowledge the channel interrupts of Privileged + channels. */ + __IOM uint32_t S : 1; /*!< Secure IRQ. If 1, this IRQ's control registers can only be accessed + from a Secure context. If 0, this IRQ's control registers + can be accessed from a Non-secure context, but Secure channels + (as per SECCFG_CHx) are masked from the IRQ status, and + this IRQ's registers can not be used to acknowledge the + channel interrupts of Secure channels. */ + uint32_t : 30; + } bit; + } SECCFG_IRQ2; + + union { + __IOM uint32_t reg; /*!< Security configuration for IRQ 3. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + + struct { + __IOM uint32_t P : 1; /*!< Privileged IRQ. If 1, this IRQ's control registers can only + be accessed from a Privileged context. If 0, this IRQ's + control registers can be accessed from an Unprivileged + context, but Privileged channels (as per SECCFG_CHx) are + masked from the IRQ status, and this IRQ's registers can + not be used to acknowledge the channel interrupts of Privileged + channels. */ + __IOM uint32_t S : 1; /*!< Secure IRQ. If 1, this IRQ's control registers can only be accessed + from a Secure context. If 0, this IRQ's control registers + can be accessed from a Non-secure context, but Secure channels + (as per SECCFG_CHx) are masked from the IRQ status, and + this IRQ's registers can not be used to acknowledge the + channel interrupts of Secure channels. */ + uint32_t : 30; + } bit; + } SECCFG_IRQ3; + + union { + __IOM uint32_t reg; /*!< Miscellaneous security configuration */ + + struct { + __IOM uint32_t SNIFF_P : 1; /*!< If 1, the sniffer can see data transfers from Privileged channels, + and can itself only be accessed from a privileged context, + or from a Secure context when SNIFF_S is 0. If 0, the sniffer + can be accessed from either a Privileged or Unprivileged + context (with sufficient security level) but can not see + transfers from Privileged channels. */ + __IOM uint32_t SNIFF_S : 1; /*!< If 1, the sniffer can see data transfers from Secure channels, + and can itself only be accessed from a Secure context. + If 0, the sniffer can be accessed from either a Secure + or Non-secure context, but can not see data transfers of + Secure channels. */ + __IOM uint32_t TIMER0_P : 1; /*!< If 1, the TIMER0 register is only accessible from a Privileged + (or more Secure) context, and timer DREQ 0 is only visible + to Privileged (or more Secure) channels. */ + __IOM uint32_t TIMER0_S : 1; /*!< If 1, the TIMER0 register is only accessible from a Secure context, + and timer DREQ 0 is only visible to Secure channels. */ + __IOM uint32_t TIMER1_P : 1; /*!< If 1, the TIMER1 register is only accessible from a Privileged + (or more Secure) context, and timer DREQ 1 is only visible + to Privileged (or more Secure) channels. */ + __IOM uint32_t TIMER1_S : 1; /*!< If 1, the TIMER1 register is only accessible from a Secure context, + and timer DREQ 1 is only visible to Secure channels. */ + __IOM uint32_t TIMER2_P : 1; /*!< If 1, the TIMER2 register is only accessible from a Privileged + (or more Secure) context, and timer DREQ 2 is only visible + to Privileged (or more Secure) channels. */ + __IOM uint32_t TIMER2_S : 1; /*!< If 1, the TIMER2 register is only accessible from a Secure context, + and timer DREQ 2 is only visible to Secure channels. */ + __IOM uint32_t TIMER3_P : 1; /*!< If 1, the TIMER3 register is only accessible from a Privileged + (or more Secure) context, and timer DREQ 3 is only visible + to Privileged (or more Secure) channels. */ + __IOM uint32_t TIMER3_S : 1; /*!< If 1, the TIMER3 register is only accessible from a Secure context, + and timer DREQ 3 is only visible to Secure channels. */ + uint32_t : 22; + } bit; + } SECCFG_MISC; + __IM uint32_t RESERVED2[11]; + + union { + __IOM uint32_t reg; /*!< Control register for DMA MPU. Accessible only from a Privileged + context. */ + + struct { + uint32_t : 1; + __IOM uint32_t P : 1; /*!< Determine whether an address not covered by an active MPU region + is Privileged (1) or Unprivileged (0) */ + __IOM uint32_t S : 1; /*!< Determine whether an address not covered by an active MPU region + is Secure (1) or Non-secure (0) */ + __IOM uint32_t NS_HIDE_ADDR : 1; /*!< By default, when a region's S bit is clear, Non-secure-Privileged + reads can see the region's base address and limit address. + Set this bit to make the addresses appear as 0 to Non-secure + reads, even when the region is Non-secure, to avoid leaking + information about the processor SAU map. */ + uint32_t : 28; + } bit; + } MPU_CTRL; + + union { + __IOM uint32_t reg; /*!< Base address register for MPU region 0. Writable only from a + Secure, Privileged context. */ + + struct { + uint32_t : 5; + __IOM uint32_t ADDR : 27; /*!< This MPU region matches addresses where addr[31:5] (the 27 most + significant bits) are greater than or equal to BAR_ADDR, + and less than or equal to LAR_ADDR. Readable from any Privileged + context, if and only if this region's S bit is clear, and + MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only + from a Secure, Privileged context. */ + } bit; + } MPU_BAR0; + + union { + __IOM uint32_t reg; /*!< Limit address register for MPU region 0. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable. If 1, any address within range specified by the + base address (BAR_ADDR) and limit address (LAR_ADDR) has + the attributes specified by S and P. */ + __IOM uint32_t P : 1; /*!< Determines the Privileged/Unprivileged (=1/0) status of addresses + matching this region, if this region is enabled. Writable + from any Privileged context, if and only if the S bit is + clear. Otherwise, writable only from a Secure, Privileged + context. */ + __IOM uint32_t S : 1; /*!< Determines the Secure/Non-secure (=1/0) status of addresses + matching this region, if this region is enabled. */ + uint32_t : 2; + __IOM uint32_t ADDR : 27; /*!< Limit address bits 31:5. Readable from any Privileged context, + if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR + is clear. Otherwise readable only from a Secure, Privileged + context. */ + } bit; + } MPU_LAR0; + + union { + __IOM uint32_t reg; /*!< Base address register for MPU region 1. Writable only from a + Secure, Privileged context. */ + + struct { + uint32_t : 5; + __IOM uint32_t ADDR : 27; /*!< This MPU region matches addresses where addr[31:5] (the 27 most + significant bits) are greater than or equal to BAR_ADDR, + and less than or equal to LAR_ADDR. Readable from any Privileged + context, if and only if this region's S bit is clear, and + MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only + from a Secure, Privileged context. */ + } bit; + } MPU_BAR1; + + union { + __IOM uint32_t reg; /*!< Limit address register for MPU region 1. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable. If 1, any address within range specified by the + base address (BAR_ADDR) and limit address (LAR_ADDR) has + the attributes specified by S and P. */ + __IOM uint32_t P : 1; /*!< Determines the Privileged/Unprivileged (=1/0) status of addresses + matching this region, if this region is enabled. Writable + from any Privileged context, if and only if the S bit is + clear. Otherwise, writable only from a Secure, Privileged + context. */ + __IOM uint32_t S : 1; /*!< Determines the Secure/Non-secure (=1/0) status of addresses + matching this region, if this region is enabled. */ + uint32_t : 2; + __IOM uint32_t ADDR : 27; /*!< Limit address bits 31:5. Readable from any Privileged context, + if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR + is clear. Otherwise readable only from a Secure, Privileged + context. */ + } bit; + } MPU_LAR1; + + union { + __IOM uint32_t reg; /*!< Base address register for MPU region 2. Writable only from a + Secure, Privileged context. */ + + struct { + uint32_t : 5; + __IOM uint32_t ADDR : 27; /*!< This MPU region matches addresses where addr[31:5] (the 27 most + significant bits) are greater than or equal to BAR_ADDR, + and less than or equal to LAR_ADDR. Readable from any Privileged + context, if and only if this region's S bit is clear, and + MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only + from a Secure, Privileged context. */ + } bit; + } MPU_BAR2; + + union { + __IOM uint32_t reg; /*!< Limit address register for MPU region 2. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable. If 1, any address within range specified by the + base address (BAR_ADDR) and limit address (LAR_ADDR) has + the attributes specified by S and P. */ + __IOM uint32_t P : 1; /*!< Determines the Privileged/Unprivileged (=1/0) status of addresses + matching this region, if this region is enabled. Writable + from any Privileged context, if and only if the S bit is + clear. Otherwise, writable only from a Secure, Privileged + context. */ + __IOM uint32_t S : 1; /*!< Determines the Secure/Non-secure (=1/0) status of addresses + matching this region, if this region is enabled. */ + uint32_t : 2; + __IOM uint32_t ADDR : 27; /*!< Limit address bits 31:5. Readable from any Privileged context, + if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR + is clear. Otherwise readable only from a Secure, Privileged + context. */ + } bit; + } MPU_LAR2; + + union { + __IOM uint32_t reg; /*!< Base address register for MPU region 3. Writable only from a + Secure, Privileged context. */ + + struct { + uint32_t : 5; + __IOM uint32_t ADDR : 27; /*!< This MPU region matches addresses where addr[31:5] (the 27 most + significant bits) are greater than or equal to BAR_ADDR, + and less than or equal to LAR_ADDR. Readable from any Privileged + context, if and only if this region's S bit is clear, and + MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only + from a Secure, Privileged context. */ + } bit; + } MPU_BAR3; + + union { + __IOM uint32_t reg; /*!< Limit address register for MPU region 3. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable. If 1, any address within range specified by the + base address (BAR_ADDR) and limit address (LAR_ADDR) has + the attributes specified by S and P. */ + __IOM uint32_t P : 1; /*!< Determines the Privileged/Unprivileged (=1/0) status of addresses + matching this region, if this region is enabled. Writable + from any Privileged context, if and only if the S bit is + clear. Otherwise, writable only from a Secure, Privileged + context. */ + __IOM uint32_t S : 1; /*!< Determines the Secure/Non-secure (=1/0) status of addresses + matching this region, if this region is enabled. */ + uint32_t : 2; + __IOM uint32_t ADDR : 27; /*!< Limit address bits 31:5. Readable from any Privileged context, + if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR + is clear. Otherwise readable only from a Secure, Privileged + context. */ + } bit; + } MPU_LAR3; + + union { + __IOM uint32_t reg; /*!< Base address register for MPU region 4. Writable only from a + Secure, Privileged context. */ + + struct { + uint32_t : 5; + __IOM uint32_t ADDR : 27; /*!< This MPU region matches addresses where addr[31:5] (the 27 most + significant bits) are greater than or equal to BAR_ADDR, + and less than or equal to LAR_ADDR. Readable from any Privileged + context, if and only if this region's S bit is clear, and + MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only + from a Secure, Privileged context. */ + } bit; + } MPU_BAR4; + + union { + __IOM uint32_t reg; /*!< Limit address register for MPU region 4. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable. If 1, any address within range specified by the + base address (BAR_ADDR) and limit address (LAR_ADDR) has + the attributes specified by S and P. */ + __IOM uint32_t P : 1; /*!< Determines the Privileged/Unprivileged (=1/0) status of addresses + matching this region, if this region is enabled. Writable + from any Privileged context, if and only if the S bit is + clear. Otherwise, writable only from a Secure, Privileged + context. */ + __IOM uint32_t S : 1; /*!< Determines the Secure/Non-secure (=1/0) status of addresses + matching this region, if this region is enabled. */ + uint32_t : 2; + __IOM uint32_t ADDR : 27; /*!< Limit address bits 31:5. Readable from any Privileged context, + if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR + is clear. Otherwise readable only from a Secure, Privileged + context. */ + } bit; + } MPU_LAR4; + + union { + __IOM uint32_t reg; /*!< Base address register for MPU region 5. Writable only from a + Secure, Privileged context. */ + + struct { + uint32_t : 5; + __IOM uint32_t ADDR : 27; /*!< This MPU region matches addresses where addr[31:5] (the 27 most + significant bits) are greater than or equal to BAR_ADDR, + and less than or equal to LAR_ADDR. Readable from any Privileged + context, if and only if this region's S bit is clear, and + MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only + from a Secure, Privileged context. */ + } bit; + } MPU_BAR5; + + union { + __IOM uint32_t reg; /*!< Limit address register for MPU region 5. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable. If 1, any address within range specified by the + base address (BAR_ADDR) and limit address (LAR_ADDR) has + the attributes specified by S and P. */ + __IOM uint32_t P : 1; /*!< Determines the Privileged/Unprivileged (=1/0) status of addresses + matching this region, if this region is enabled. Writable + from any Privileged context, if and only if the S bit is + clear. Otherwise, writable only from a Secure, Privileged + context. */ + __IOM uint32_t S : 1; /*!< Determines the Secure/Non-secure (=1/0) status of addresses + matching this region, if this region is enabled. */ + uint32_t : 2; + __IOM uint32_t ADDR : 27; /*!< Limit address bits 31:5. Readable from any Privileged context, + if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR + is clear. Otherwise readable only from a Secure, Privileged + context. */ + } bit; + } MPU_LAR5; + + union { + __IOM uint32_t reg; /*!< Base address register for MPU region 6. Writable only from a + Secure, Privileged context. */ + + struct { + uint32_t : 5; + __IOM uint32_t ADDR : 27; /*!< This MPU region matches addresses where addr[31:5] (the 27 most + significant bits) are greater than or equal to BAR_ADDR, + and less than or equal to LAR_ADDR. Readable from any Privileged + context, if and only if this region's S bit is clear, and + MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only + from a Secure, Privileged context. */ + } bit; + } MPU_BAR6; + + union { + __IOM uint32_t reg; /*!< Limit address register for MPU region 6. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable. If 1, any address within range specified by the + base address (BAR_ADDR) and limit address (LAR_ADDR) has + the attributes specified by S and P. */ + __IOM uint32_t P : 1; /*!< Determines the Privileged/Unprivileged (=1/0) status of addresses + matching this region, if this region is enabled. Writable + from any Privileged context, if and only if the S bit is + clear. Otherwise, writable only from a Secure, Privileged + context. */ + __IOM uint32_t S : 1; /*!< Determines the Secure/Non-secure (=1/0) status of addresses + matching this region, if this region is enabled. */ + uint32_t : 2; + __IOM uint32_t ADDR : 27; /*!< Limit address bits 31:5. Readable from any Privileged context, + if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR + is clear. Otherwise readable only from a Secure, Privileged + context. */ + } bit; + } MPU_LAR6; + + union { + __IOM uint32_t reg; /*!< Base address register for MPU region 7. Writable only from a + Secure, Privileged context. */ + + struct { + uint32_t : 5; + __IOM uint32_t ADDR : 27; /*!< This MPU region matches addresses where addr[31:5] (the 27 most + significant bits) are greater than or equal to BAR_ADDR, + and less than or equal to LAR_ADDR. Readable from any Privileged + context, if and only if this region's S bit is clear, and + MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only + from a Secure, Privileged context. */ + } bit; + } MPU_BAR7; + + union { + __IOM uint32_t reg; /*!< Limit address register for MPU region 7. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + + struct { + __IOM uint32_t EN : 1; /*!< Region enable. If 1, any address within range specified by the + base address (BAR_ADDR) and limit address (LAR_ADDR) has + the attributes specified by S and P. */ + __IOM uint32_t P : 1; /*!< Determines the Privileged/Unprivileged (=1/0) status of addresses + matching this region, if this region is enabled. Writable + from any Privileged context, if and only if the S bit is + clear. Otherwise, writable only from a Secure, Privileged + context. */ + __IOM uint32_t S : 1; /*!< Determines the Secure/Non-secure (=1/0) status of addresses + matching this region, if this region is enabled. */ + uint32_t : 2; + __IOM uint32_t ADDR : 27; /*!< Limit address bits 31:5. Readable from any Privileged context, + if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR + is clear. Otherwise readable only from a Secure, Privileged + context. */ + } bit; + } MPU_LAR7; + __IM uint32_t RESERVED3[175]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH0_DBG_CTDREQ : 6; /*!< CH0_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH0_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH0_DBG_TCR : 32; /*!< CH0_DBG_TCR */ + } bit; + } CH0_DBG_TCR; + __IM uint32_t RESERVED4[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH1_DBG_CTDREQ : 6; /*!< CH1_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH1_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH1_DBG_TCR : 32; /*!< CH1_DBG_TCR */ + } bit; + } CH1_DBG_TCR; + __IM uint32_t RESERVED5[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH2_DBG_CTDREQ : 6; /*!< CH2_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH2_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH2_DBG_TCR : 32; /*!< CH2_DBG_TCR */ + } bit; + } CH2_DBG_TCR; + __IM uint32_t RESERVED6[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH3_DBG_CTDREQ : 6; /*!< CH3_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH3_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH3_DBG_TCR : 32; /*!< CH3_DBG_TCR */ + } bit; + } CH3_DBG_TCR; + __IM uint32_t RESERVED7[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH4_DBG_CTDREQ : 6; /*!< CH4_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH4_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH4_DBG_TCR : 32; /*!< CH4_DBG_TCR */ + } bit; + } CH4_DBG_TCR; + __IM uint32_t RESERVED8[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH5_DBG_CTDREQ : 6; /*!< CH5_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH5_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH5_DBG_TCR : 32; /*!< CH5_DBG_TCR */ + } bit; + } CH5_DBG_TCR; + __IM uint32_t RESERVED9[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH6_DBG_CTDREQ : 6; /*!< CH6_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH6_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH6_DBG_TCR : 32; /*!< CH6_DBG_TCR */ + } bit; + } CH6_DBG_TCR; + __IM uint32_t RESERVED10[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH7_DBG_CTDREQ : 6; /*!< CH7_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH7_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH7_DBG_TCR : 32; /*!< CH7_DBG_TCR */ + } bit; + } CH7_DBG_TCR; + __IM uint32_t RESERVED11[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH8_DBG_CTDREQ : 6; /*!< CH8_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH8_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH8_DBG_TCR : 32; /*!< CH8_DBG_TCR */ + } bit; + } CH8_DBG_TCR; + __IM uint32_t RESERVED12[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH9_DBG_CTDREQ : 6; /*!< CH9_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH9_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH9_DBG_TCR : 32; /*!< CH9_DBG_TCR */ + } bit; + } CH9_DBG_TCR; + __IM uint32_t RESERVED13[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH10_DBG_CTDREQ : 6; /*!< CH10_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH10_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH10_DBG_TCR : 32; /*!< CH10_DBG_TCR */ + } bit; + } CH10_DBG_TCR; + __IM uint32_t RESERVED14[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH11_DBG_CTDREQ : 6; /*!< CH11_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH11_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH11_DBG_TCR : 32; /*!< CH11_DBG_TCR */ + } bit; + } CH11_DBG_TCR; + __IM uint32_t RESERVED15[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH12_DBG_CTDREQ : 6; /*!< CH12_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH12_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH12_DBG_TCR : 32; /*!< CH12_DBG_TCR */ + } bit; + } CH12_DBG_TCR; + __IM uint32_t RESERVED16[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH13_DBG_CTDREQ : 6; /*!< CH13_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH13_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH13_DBG_TCR : 32; /*!< CH13_DBG_TCR */ + } bit; + } CH13_DBG_TCR; + __IM uint32_t RESERVED17[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH14_DBG_CTDREQ : 6; /*!< CH14_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH14_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH14_DBG_TCR : 32; /*!< CH14_DBG_TCR */ + } bit; + } CH14_DBG_TCR; + __IM uint32_t RESERVED18[14]; + + union { + __IOM uint32_t reg; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + + struct { + __IOM uint32_t CH15_DBG_CTDREQ : 6; /*!< CH15_DBG_CTDREQ */ + uint32_t : 26; + } bit; + } CH15_DBG_CTDREQ; + + union { + __IOM uint32_t reg; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + + struct { + __IM uint32_t CH15_DBG_TCR : 32; /*!< CH15_DBG_TCR */ + } bit; + } CH15_DBG_TCR; +} DMA_Type; /*!< Size = 3016 (0xbc8) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls time and alarms + + time is a 64 bit value indicating the time since power-on + + timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr + + An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing (TIMER0) + */ + +typedef struct { /*!< TIMER0 Structure */ + + union { + __IOM uint32_t reg; /*!< Write to bits 63:32 of time always write timelw before timehw */ + + struct { + __OM uint32_t TIMEHW : 32; /*!< TIMEHW */ + } bit; + } TIMEHW; + + union { + __IOM uint32_t reg; /*!< Write to bits 31:0 of time writes do not get copied to time + until timehw is written */ + + struct { + __OM uint32_t TIMELW : 32; /*!< TIMELW */ + } bit; + } TIMELW; + + union { + __IOM uint32_t reg; /*!< Read from bits 63:32 of time always read timelr before timehr */ + + struct { + __IM uint32_t TIMEHR : 32; /*!< TIMEHR */ + } bit; + } TIMEHR; + + union { + __IOM uint32_t reg; /*!< Read from bits 31:0 of time */ + + struct { + __IM uint32_t TIMELR : 32; /*!< TIMELR */ + } bit; + } TIMELR; + + union { + __IOM uint32_t reg; /*!< Arm alarm 0, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM0 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + + struct { + __IOM uint32_t ALARM0 : 32; /*!< ALARM0 */ + } bit; + } ALARM0; + + union { + __IOM uint32_t reg; /*!< Arm alarm 1, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM1 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + + struct { + __IOM uint32_t ALARM1 : 32; /*!< ALARM1 */ + } bit; + } ALARM1; + + union { + __IOM uint32_t reg; /*!< Arm alarm 2, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM2 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + + struct { + __IOM uint32_t ALARM2 : 32; /*!< ALARM2 */ + } bit; + } ALARM2; + + union { + __IOM uint32_t reg; /*!< Arm alarm 3, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM3 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + + struct { + __IOM uint32_t ALARM3 : 32; /*!< ALARM3 */ + } bit; + } ALARM3; + + union { + __IOM uint32_t reg; /*!< Indicates the armed/disarmed status of each alarm. A write to + the corresponding ALARMx register arms the alarm. Alarms + automatically disarm upon firing, but writing ones here + will disarm immediately without waiting to fire. */ + + struct { + __IOM uint32_t ARMED : 4; /*!< ARMED */ + uint32_t : 28; + } bit; + } ARMED; + + union { + __IOM uint32_t reg; /*!< Raw read from bits 63:32 of time (no side effects) */ + + struct { + __IM uint32_t TIMERAWH : 32; /*!< TIMERAWH */ + } bit; + } TIMERAWH; + + union { + __IOM uint32_t reg; /*!< Raw read from bits 31:0 of time (no side effects) */ + + struct { + __IM uint32_t TIMERAWL : 32; /*!< TIMERAWL */ + } bit; + } TIMERAWL; + + union { + __IOM uint32_t reg; /*!< Set bits high to enable pause when the corresponding debug ports + are active */ + + struct { + uint32_t : 1; + __IOM uint32_t DBG0 : 1; /*!< Pause when processor 0 is in debug mode */ + __IOM uint32_t DBG1 : 1; /*!< Pause when processor 1 is in debug mode */ + uint32_t : 29; + } bit; + } DBGPAUSE; + + union { + __IOM uint32_t reg; /*!< Set high to pause the timer */ + + struct { + __IOM uint32_t PAUSE : 1; /*!< PAUSE */ + uint32_t : 31; + } bit; + } PAUSE; + + union { + __IOM uint32_t reg; /*!< Set locked bit to disable write access to timer Once set, cannot + be cleared (without a reset) */ + + struct { + __IOM uint32_t LOCKED : 1; /*!< LOCKED */ + uint32_t : 31; + } bit; + } LOCKED; + + union { + __IOM uint32_t reg; /*!< Selects the source for the timer. Defaults to the normal tick + configured in the ticks block (typically configured to + 1 microsecond). Writing to 1 will ignore the tick and count + clk_sys cycles instead. */ + + struct { + __IOM uint32_t CLK_SYS : 1; /*!< CLK_SYS */ + uint32_t : 31; + } bit; + } SOURCE; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IOM uint32_t ALARM_0 : 1; /*!< ALARM_0 */ + __IOM uint32_t ALARM_1 : 1; /*!< ALARM_1 */ + __IOM uint32_t ALARM_2 : 1; /*!< ALARM_2 */ + __IOM uint32_t ALARM_3 : 1; /*!< ALARM_3 */ + uint32_t : 28; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable */ + + struct { + __IOM uint32_t ALARM_0 : 1; /*!< ALARM_0 */ + __IOM uint32_t ALARM_1 : 1; /*!< ALARM_1 */ + __IOM uint32_t ALARM_2 : 1; /*!< ALARM_2 */ + __IOM uint32_t ALARM_3 : 1; /*!< ALARM_3 */ + uint32_t : 28; + } bit; + } INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force */ + + struct { + __IOM uint32_t ALARM_0 : 1; /*!< ALARM_0 */ + __IOM uint32_t ALARM_1 : 1; /*!< ALARM_1 */ + __IOM uint32_t ALARM_2 : 1; /*!< ALARM_2 */ + __IOM uint32_t ALARM_3 : 1; /*!< ALARM_3 */ + uint32_t : 28; + } bit; + } INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing */ + + struct { + __IM uint32_t ALARM_0 : 1; /*!< ALARM_0 */ + __IM uint32_t ALARM_1 : 1; /*!< ALARM_1 */ + __IM uint32_t ALARM_2 : 1; /*!< ALARM_2 */ + __IM uint32_t ALARM_3 : 1; /*!< ALARM_3 */ + uint32_t : 28; + } bit; + } INTS; +} TIMER0_Type; /*!< Size = 76 (0x4c) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Simple PWM (PWM) + */ + +typedef struct { /*!< PWM Structure */ + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH0_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH0_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH0_CTR : 16; /*!< CH0_CTR */ + uint32_t : 16; + } bit; + } CH0_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH0_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH0_TOP : 16; /*!< CH0_TOP */ + uint32_t : 16; + } bit; + } CH0_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH1_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH1_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH1_CTR : 16; /*!< CH1_CTR */ + uint32_t : 16; + } bit; + } CH1_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH1_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH1_TOP : 16; /*!< CH1_TOP */ + uint32_t : 16; + } bit; + } CH1_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH2_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH2_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH2_CTR : 16; /*!< CH2_CTR */ + uint32_t : 16; + } bit; + } CH2_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH2_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH2_TOP : 16; /*!< CH2_TOP */ + uint32_t : 16; + } bit; + } CH2_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH3_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH3_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH3_CTR : 16; /*!< CH3_CTR */ + uint32_t : 16; + } bit; + } CH3_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH3_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH3_TOP : 16; /*!< CH3_TOP */ + uint32_t : 16; + } bit; + } CH3_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH4_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH4_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH4_CTR : 16; /*!< CH4_CTR */ + uint32_t : 16; + } bit; + } CH4_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH4_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH4_TOP : 16; /*!< CH4_TOP */ + uint32_t : 16; + } bit; + } CH4_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH5_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH5_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH5_CTR : 16; /*!< CH5_CTR */ + uint32_t : 16; + } bit; + } CH5_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH5_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH5_TOP : 16; /*!< CH5_TOP */ + uint32_t : 16; + } bit; + } CH5_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH6_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH6_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH6_CTR : 16; /*!< CH6_CTR */ + uint32_t : 16; + } bit; + } CH6_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH6_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH6_TOP : 16; /*!< CH6_TOP */ + uint32_t : 16; + } bit; + } CH6_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH7_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH7_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH7_CTR : 16; /*!< CH7_CTR */ + uint32_t : 16; + } bit; + } CH7_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH7_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH7_TOP : 16; /*!< CH7_TOP */ + uint32_t : 16; + } bit; + } CH7_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH8_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH8_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH8_CTR : 16; /*!< CH8_CTR */ + uint32_t : 16; + } bit; + } CH8_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH8_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH8_TOP : 16; /*!< CH8_TOP */ + uint32_t : 16; + } bit; + } CH8_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH9_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH9_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH9_CTR : 16; /*!< CH9_CTR */ + uint32_t : 16; + } bit; + } CH9_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH9_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH9_TOP : 16; /*!< CH9_TOP */ + uint32_t : 16; + } bit; + } CH9_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH10_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH10_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH10_CTR : 16; /*!< CH10_CTR */ + uint32_t : 16; + } bit; + } CH10_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH10_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH10_TOP : 16; /*!< CH10_TOP */ + uint32_t : 16; + } bit; + } CH10_TOP; + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< Enable the PWM channel. */ + __IOM uint32_t PH_CORRECT : 1; /*!< 1: Enable phase-correct modulation. 0: Trailing-edge */ + __IOM uint32_t A_INV : 1; /*!< Invert output A */ + __IOM uint32_t B_INV : 1; /*!< Invert output B */ + __IOM uint32_t DIVMODE : 2; /*!< DIVMODE */ + __OM uint32_t PH_RET : 1; /*!< Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running. */ + __OM uint32_t PH_ADV : 1; /*!< Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must + be running at less than full speed (div_int + div_frac + / 16 > 1) */ + uint32_t : 24; + } bit; + } CH11_CSR; + + union { + __IOM uint32_t reg; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + + struct { + __IOM uint32_t FRAC : 4; /*!< FRAC */ + __IOM uint32_t INT : 8; /*!< INT */ + uint32_t : 20; + } bit; + } CH11_DIV; + + union { + __IOM uint32_t reg; /*!< Direct access to the PWM counter */ + + struct { + __IOM uint32_t CH11_CTR : 16; /*!< CH11_CTR */ + uint32_t : 16; + } bit; + } CH11_CTR; + + union { + __IOM uint32_t reg; /*!< Counter compare values */ + + struct { + __IOM uint32_t A : 16; /*!< A */ + __IOM uint32_t B : 16; /*!< B */ + } bit; + } CH11_CC; + + union { + __IOM uint32_t reg; /*!< Counter wrap value */ + + struct { + __IOM uint32_t CH11_TOP : 16; /*!< CH11_TOP */ + uint32_t : 16; + } bit; + } CH11_TOP; + + union { + __IOM uint32_t reg; /*!< This register aliases the CSR_EN bits for all channels. Writing + to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect + sync. For each channel, there is only one physical EN register + bit, which can be accessed through here or CHx_CSR. */ + + struct { + __IOM uint32_t CH0 : 1; /*!< CH0 */ + __IOM uint32_t CH1 : 1; /*!< CH1 */ + __IOM uint32_t CH2 : 1; /*!< CH2 */ + __IOM uint32_t CH3 : 1; /*!< CH3 */ + __IOM uint32_t CH4 : 1; /*!< CH4 */ + __IOM uint32_t CH5 : 1; /*!< CH5 */ + __IOM uint32_t CH6 : 1; /*!< CH6 */ + __IOM uint32_t CH7 : 1; /*!< CH7 */ + __IOM uint32_t CH8 : 1; /*!< CH8 */ + __IOM uint32_t CH9 : 1; /*!< CH9 */ + __IOM uint32_t CH10 : 1; /*!< CH10 */ + __IOM uint32_t CH11 : 1; /*!< CH11 */ + uint32_t : 20; + } bit; + } EN; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IOM uint32_t CH0 : 1; /*!< CH0 */ + __IOM uint32_t CH1 : 1; /*!< CH1 */ + __IOM uint32_t CH2 : 1; /*!< CH2 */ + __IOM uint32_t CH3 : 1; /*!< CH3 */ + __IOM uint32_t CH4 : 1; /*!< CH4 */ + __IOM uint32_t CH5 : 1; /*!< CH5 */ + __IOM uint32_t CH6 : 1; /*!< CH6 */ + __IOM uint32_t CH7 : 1; /*!< CH7 */ + __IOM uint32_t CH8 : 1; /*!< CH8 */ + __IOM uint32_t CH9 : 1; /*!< CH9 */ + __IOM uint32_t CH10 : 1; /*!< CH10 */ + __IOM uint32_t CH11 : 1; /*!< CH11 */ + uint32_t : 20; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for irq0 */ + + struct { + __IOM uint32_t CH0 : 1; /*!< CH0 */ + __IOM uint32_t CH1 : 1; /*!< CH1 */ + __IOM uint32_t CH2 : 1; /*!< CH2 */ + __IOM uint32_t CH3 : 1; /*!< CH3 */ + __IOM uint32_t CH4 : 1; /*!< CH4 */ + __IOM uint32_t CH5 : 1; /*!< CH5 */ + __IOM uint32_t CH6 : 1; /*!< CH6 */ + __IOM uint32_t CH7 : 1; /*!< CH7 */ + __IOM uint32_t CH8 : 1; /*!< CH8 */ + __IOM uint32_t CH9 : 1; /*!< CH9 */ + __IOM uint32_t CH10 : 1; /*!< CH10 */ + __IOM uint32_t CH11 : 1; /*!< CH11 */ + uint32_t : 20; + } bit; + } IRQ0_INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for irq0 */ + + struct { + __IOM uint32_t CH0 : 1; /*!< CH0 */ + __IOM uint32_t CH1 : 1; /*!< CH1 */ + __IOM uint32_t CH2 : 1; /*!< CH2 */ + __IOM uint32_t CH3 : 1; /*!< CH3 */ + __IOM uint32_t CH4 : 1; /*!< CH4 */ + __IOM uint32_t CH5 : 1; /*!< CH5 */ + __IOM uint32_t CH6 : 1; /*!< CH6 */ + __IOM uint32_t CH7 : 1; /*!< CH7 */ + __IOM uint32_t CH8 : 1; /*!< CH8 */ + __IOM uint32_t CH9 : 1; /*!< CH9 */ + __IOM uint32_t CH10 : 1; /*!< CH10 */ + __IOM uint32_t CH11 : 1; /*!< CH11 */ + uint32_t : 20; + } bit; + } IRQ0_INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for irq0 */ + + struct { + __IM uint32_t CH0 : 1; /*!< CH0 */ + __IM uint32_t CH1 : 1; /*!< CH1 */ + __IM uint32_t CH2 : 1; /*!< CH2 */ + __IM uint32_t CH3 : 1; /*!< CH3 */ + __IM uint32_t CH4 : 1; /*!< CH4 */ + __IM uint32_t CH5 : 1; /*!< CH5 */ + __IM uint32_t CH6 : 1; /*!< CH6 */ + __IM uint32_t CH7 : 1; /*!< CH7 */ + __IM uint32_t CH8 : 1; /*!< CH8 */ + __IM uint32_t CH9 : 1; /*!< CH9 */ + __IM uint32_t CH10 : 1; /*!< CH10 */ + __IM uint32_t CH11 : 1; /*!< CH11 */ + uint32_t : 20; + } bit; + } IRQ0_INTS; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for irq1 */ + + struct { + __IOM uint32_t CH0 : 1; /*!< CH0 */ + __IOM uint32_t CH1 : 1; /*!< CH1 */ + __IOM uint32_t CH2 : 1; /*!< CH2 */ + __IOM uint32_t CH3 : 1; /*!< CH3 */ + __IOM uint32_t CH4 : 1; /*!< CH4 */ + __IOM uint32_t CH5 : 1; /*!< CH5 */ + __IOM uint32_t CH6 : 1; /*!< CH6 */ + __IOM uint32_t CH7 : 1; /*!< CH7 */ + __IOM uint32_t CH8 : 1; /*!< CH8 */ + __IOM uint32_t CH9 : 1; /*!< CH9 */ + __IOM uint32_t CH10 : 1; /*!< CH10 */ + __IOM uint32_t CH11 : 1; /*!< CH11 */ + uint32_t : 20; + } bit; + } IRQ1_INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for irq1 */ + + struct { + __IOM uint32_t CH0 : 1; /*!< CH0 */ + __IOM uint32_t CH1 : 1; /*!< CH1 */ + __IOM uint32_t CH2 : 1; /*!< CH2 */ + __IOM uint32_t CH3 : 1; /*!< CH3 */ + __IOM uint32_t CH4 : 1; /*!< CH4 */ + __IOM uint32_t CH5 : 1; /*!< CH5 */ + __IOM uint32_t CH6 : 1; /*!< CH6 */ + __IOM uint32_t CH7 : 1; /*!< CH7 */ + __IOM uint32_t CH8 : 1; /*!< CH8 */ + __IOM uint32_t CH9 : 1; /*!< CH9 */ + __IOM uint32_t CH10 : 1; /*!< CH10 */ + __IOM uint32_t CH11 : 1; /*!< CH11 */ + uint32_t : 20; + } bit; + } IRQ1_INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for irq1 */ + + struct { + __IM uint32_t CH0 : 1; /*!< CH0 */ + __IM uint32_t CH1 : 1; /*!< CH1 */ + __IM uint32_t CH2 : 1; /*!< CH2 */ + __IM uint32_t CH3 : 1; /*!< CH3 */ + __IM uint32_t CH4 : 1; /*!< CH4 */ + __IM uint32_t CH5 : 1; /*!< CH5 */ + __IM uint32_t CH6 : 1; /*!< CH6 */ + __IM uint32_t CH7 : 1; /*!< CH7 */ + __IM uint32_t CH8 : 1; /*!< CH8 */ + __IM uint32_t CH9 : 1; /*!< CH9 */ + __IM uint32_t CH10 : 1; /*!< CH10 */ + __IM uint32_t CH11 : 1; /*!< CH11 */ + uint32_t : 20; + } bit; + } IRQ1_INTS; +} PWM_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Control and data interface to SAR ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + + union { + __IOM uint32_t reg; /*!< ADC Control and Status */ + + struct { + __IOM uint32_t EN : 1; /*!< Power on ADC and enable its clock. 1 - enabled. 0 - disabled. */ + __IOM uint32_t TS_EN : 1; /*!< Power on temperature sensor. 1 - enabled. 0 - disabled. */ + __OM uint32_t START_ONCE : 1; /*!< Start a single conversion. Self-clearing. Ignored if start_many + is asserted. */ + __IOM uint32_t START_MANY : 1; /*!< Continuously perform conversions whilst this bit is 1. A new + conversion will start immediately after the previous finishes. */ + uint32_t : 4; + __IM uint32_t READY : 1; /*!< 1 if the ADC is ready to start a new conversion. Implies any + previous conversion has completed. 0 whilst conversion + in progress. */ + __IM uint32_t ERR : 1; /*!< The most recent ADC conversion encountered an error; result + is undefined or noisy. */ + __IOM uint32_t ERR_STICKY : 1; /*!< Some past ADC conversion encountered an error. Write 1 to clear. */ + uint32_t : 1; + __IOM uint32_t AINSEL : 4; /*!< Select analog mux input. Updated automatically in round-robin + mode. This is corrected for the package option so only + ADC channels which are bonded are available, and in the + correct order */ + __IOM uint32_t RROBIN : 9; /*!< Round-robin sampling. 1 bit per channel. Set all bits to 0 to + disable. Otherwise, the ADC will cycle through each enabled + channel in a round-robin fashion. The first channel to + be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected + channel. */ + uint32_t : 7; + } bit; + } CS; + + union { + __IOM uint32_t reg; /*!< Result of most recent ADC conversion */ + + struct { + __IM uint32_t RESULT : 12; /*!< RESULT */ + uint32_t : 20; + } bit; + } RESULT; + + union { + __IOM uint32_t reg; /*!< FIFO control and status */ + + struct { + __IOM uint32_t EN : 1; /*!< If 1: write result to the FIFO after each conversion. */ + __IOM uint32_t SHIFT : 1; /*!< If 1: FIFO results are right-shifted to be one byte in size. + Enables DMA to byte buffers. */ + __IOM uint32_t ERR : 1; /*!< If 1: conversion error bit appears in the FIFO alongside the + result */ + __IOM uint32_t DREQ_EN : 1; /*!< If 1: assert DMA requests when FIFO contains data */ + uint32_t : 4; + __IM uint32_t EMPTY : 1; /*!< EMPTY */ + __IM uint32_t FULL : 1; /*!< FULL */ + __IOM uint32_t UNDER : 1; /*!< 1 if the FIFO has been underflowed. Write 1 to clear. */ + __IOM uint32_t OVER : 1; /*!< 1 if the FIFO has been overflowed. Write 1 to clear. */ + uint32_t : 4; + __IM uint32_t LEVEL : 4; /*!< The number of conversion results currently waiting in the FIFO */ + uint32_t : 4; + __IOM uint32_t THRESH : 4; /*!< DREQ/IRQ asserted when level >= threshold */ + uint32_t : 4; + } bit; + } FCS; + + union { + __IOM uint32_t reg; /*!< Conversion result FIFO */ + + struct { + __IM uint32_t VAL : 12; /*!< VAL */ + uint32_t : 3; + __IM uint32_t ERR : 1; /*!< 1 if this particular sample experienced a conversion error. + Remains in the same location if the sample is shifted. */ + uint32_t : 16; + } bit; + } FIFO; + + union { + __IOM uint32_t reg; /*!< Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. The divider + is reset when either of these fields are written. Total + period is 1 + INT + FRAC / 256 */ + + struct { + __IOM uint32_t FRAC : 8; /*!< Fractional part of clock divisor. First-order delta-sigma. */ + __IOM uint32_t INT : 16; /*!< Integer part of clock divisor. */ + uint32_t : 8; + } bit; + } DIV; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t FIFO : 1; /*!< Triggered when the sample FIFO reaches a certain level. This + level can be programmed via the FCS_THRESH field. */ + uint32_t : 31; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable */ + + struct { + __IOM uint32_t FIFO : 1; /*!< Triggered when the sample FIFO reaches a certain level. This + level can be programmed via the FCS_THRESH field. */ + uint32_t : 31; + } bit; + } INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force */ + + struct { + __IOM uint32_t FIFO : 1; /*!< Triggered when the sample FIFO reaches a certain level. This + level can be programmed via the FCS_THRESH field. */ + uint32_t : 31; + } bit; + } INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing */ + + struct { + __IM uint32_t FIFO : 1; /*!< Triggered when the sample FIFO reaches a certain level. This + level can be programmed via the FCS_THRESH field. */ + uint32_t : 31; + } bit; + } INTS; +} ADC_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + + union { + __IOM uint32_t reg; /*!< I2C Control Register. This register can be written only when + the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] + register being set to 0. Writes at other times have no + effect. Read/Write Access: - bit 10 is read only. - bit + 11 is read only - bit 16 is read only - bit 17 is read + only - bits 18 and 19 are read only. */ + + struct { + __IOM uint32_t MASTER_MODE : 1; /*!< This bit controls whether the DW_apb_i2c master is enabled. + NOTE: Software should ensure that if this bit is written + with '1' then bit 6 should also be written with a '1'. */ + __IOM uint32_t SPEED : 2; /*!< These bits control at which speed the DW_apb_i2c operates; its + setting is relevant only if one is operating the DW_apb_i2c + in master mode. Hardware protects against illegal values + being programmed by software. These bits must be programmed + appropriately for slave mode also, as it is used to capture + correct value of spike filter as per the speed mode. This + register should be programmed only with a value in the + range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates + this register with the value of IC_MAX_SPEED_MODE. 1: standard + mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode + plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: + This field is not applicable when IC_ULTRA_FAST_MODE=1 */ + __IOM uint32_t IC_10BITADDR_SLAVE : 1; /*!< When acting as a slave, this bit controls whether the DW_apb_i2c + responds to 7- or 10-bit addresses. - 0: 7-bit addressing. + The DW_apb_i2c ignores transactions that involve 10-bit + addressing; for 7-bit addressing, only the lower 7 bits + of the IC_SAR register are compared. - 1: 10-bit addressing. + The DW_apb_i2c responds to only 10-bit addressing transfers + that match the full 10 bits of the IC_SAR register. */ + __IOM uint32_t IC_10BITADDR_MASTER : 1; /*!< Controls whether the DW_apb_i2c starts its transfers in 7- or + 10-bit addressing mode when acting as a master. - 0: 7-bit + addressing - 1: 10-bit addressing */ + __IOM uint32_t IC_RESTART_EN : 1; /*!< Determines whether RESTART conditions may be sent when acting + as a master. Some older slaves do not support handling + RESTART conditions; however, RESTART conditions are used + in several DW_apb_i2c operations. When RESTART is disabled, + the master is prohibited from performing the following + functions: - Sending a START BYTE - Performing any high-speed + mode operation - High-speed mode operation - Performing + direction changes in combined format mode - Performing + a read operation with a 10-bit address By replacing RESTART + condition followed by a STOP and a subsequent START condition, + split operations are broken down into multiple DW_apb_i2c + transfers. If the above operations are performed, it will + result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT + register. Reset value: ENABLED */ + __IOM uint32_t IC_SLAVE_DISABLE : 1; /*!< This bit controls whether I2C has its slave disabled, which + means once the presetn signal is applied, then this bit + is set and the slave is disabled. If this bit is set (slave + is disabled), DW_apb_i2c functions only as a master and + does not perform any action that requires a slave. NOTE: + Software should ensure that if this bit is written with + 0, then bit 0 should also be written with a 0. */ + __IOM uint32_t STOP_DET_IFADDRESSED : 1; /*!< In slave mode: - 1'b1: issues the STOP_DET interrupt only when + it is addressed. - 1'b0: issues the STOP_DET irrespective + of whether it's addressed or not. Reset value: 0x0 NOTE: + During a general call address, this slave does not issue + the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, + even if the slave responds to the general call address + by generating ACK. The STOP_DET interrupt is generated + only when the transmitted address matches the slave address + (SAR). */ + __IOM uint32_t TX_EMPTY_CTRL : 1; /*!< This bit controls the generation of the TX_EMPTY interrupt, + as described in the IC_RAW_INTR_STAT register. Reset value: + 0x0. */ + __IOM uint32_t RX_FIFO_FULL_HLD_CTRL : 1; /*!< This bit controls whether DW_apb_i2c should hold the bus when + the Rx FIFO is physically full to its RX_BUFFER_DEPTH, + as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset + value: 0x0. */ + __IM uint32_t STOP_DET_IF_MASTER_ACTIVE : 1;/*!< Master issues the STOP_DET interrupt irrespective of whether + master is active or not */ + uint32_t : 21; + } bit; + } IC_CON; + + union { + __IOM uint32_t reg; /*!< I2C Target Address Register This register is 12 bits wide, and + bits 31:12 are reserved. This register can be written to + only when IC_ENABLE[0] is set to 0. Note: If the software + or application is aware that the DW_apb_i2c is not using + the TAR address for the pending commands in the Tx FIFO, + then it is possible to update the TAR address even while + the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not + necessary to perform any write to this register if DW_apb_i2c + is enabled as an I2C slave only. */ + + struct { + __IOM uint32_t IC_TAR : 10; /*!< This is the target address for any master transaction. When + transmitting a General Call, these bits are ignored. To + generate a START BYTE, the CPU needs to write only once + into these bits. If the IC_TAR and IC_SAR are the same, + loopback exists but the FIFOs are shared between master + and slave, so full loopback is not feasible. Only one direction + loopback mode is supported (simplex), not duplex. A master + cannot transmit to itself; it can transmit to only a slave. */ + __IOM uint32_t GC_OR_START : 1; /*!< If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set + to 0, then this bit indicates whether a General Call or + START byte command is to be performed by the DW_apb_i2c. + - 0: General Call Address - after issuing a General Call, + only writes may be performed. Attempting to issue a read + command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT + register. The DW_apb_i2c remains in General Call mode until + the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE + Reset value: 0x0 */ + __IOM uint32_t SPECIAL : 1; /*!< This bit indicates whether software performs a Device-ID or + General Call or START BYTE command. - 0: ignore bit 10 + GC_OR_START and use IC_TAR normally - 1: perform special + I2C command as specified in Device_ID or GC_OR_START bit + Reset value: 0x0 */ + uint32_t : 20; + } bit; + } IC_TAR; + + union { + __IOM uint32_t reg; /*!< I2C Slave Address Register */ + + struct { + __IOM uint32_t IC_SAR : 10; /*!< The IC_SAR holds the slave address when the I2C is operating + as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + This register can be written only when the I2C interface + is disabled, which corresponds to the IC_ENABLE[0] register + being set to 0. Writes at other times have no effect. Note: + The default values cannot be any of the reserved address + locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The + correct operation of the device is not guaranteed if you + program the IC_SAR or IC_TAR to a reserved value. Refer + to <> for a complete list + of these reserved values. */ + uint32_t : 22; + } bit; + } IC_SAR; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< I2C Rx/Tx Data Buffer and Command Register; this is the register + the CPU writes to when filling the TX FIFO and the CPU + reads from when retrieving bytes from RX FIFO. The size + of the register changes as follows: Write: - 11 bits when + IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 + Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 + bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order + for the DW_apb_i2c to continue acknowledging reads, a read + command should be written for every byte that is to be + received; otherwise the DW_apb_i2c will stop acknowledging. */ + + struct { + __IOM uint32_t DAT : 8; /*!< This register contains the data to be transmitted or received + on the I2C bus. If you are writing to this register and + want to perform a read, bits 7:0 (DAT) are ignored by the + DW_apb_i2c. However, when you read this register, these + bits return the value of data received on the DW_apb_i2c + interface. Reset value: 0x0 */ + __OM uint32_t CMD : 1; /*!< This bit controls whether a read or a write is performed. This + bit does not control the direction when the DW_apb_i2con + acts as a slave. It controls only the direction when it + acts as a master. When a command is entered in the TX FIFO, + this bit distinguishes the write and read commands. In + slave-receiver mode, this bit is a 'don't care' because + writes to this register are not required. In slave-transmitter + mode, a '0' indicates that the data in IC_DATA_CMD is to + be transmitted. When programming this bit, you should remember + the following: attempting to perform a read operation after + a General Call command has been sent results in a TX_ABRT + interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless + bit 11 (SPECIAL) in the IC_TAR register has been cleared. + If a '1' is written to this bit after receiving a RD_REQ + interrupt, then a TX_ABRT interrupt occurs. Reset value: + 0x0 */ + __OM uint32_t STOP : 1; /*!< This bit controls whether a STOP is issued after the byte is + sent or received. - 1 - STOP is issued after this byte, + regardless of whether or not the Tx FIFO is empty. If the + Tx FIFO is not empty, the master immediately tries to start + a new transfer by issuing a START and arbitrating for the + bus. - 0 - STOP is not issued after this byte, regardless + of whether or not the Tx FIFO is empty. If the Tx FIFO + is not empty, the master continues the current transfer + by sending/receiving data bytes according to the value + of the CMD bit. If the Tx FIFO is empty, the master holds + the SCL line low and stalls the bus until a new command + is available in the Tx FIFO. Reset value: 0x0 */ + __OM uint32_t RESTART : 1; /*!< This bit controls whether a RESTART is issued before the byte + is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART + is issued before the data is sent/received (according to + the value of CMD), regardless of whether or not the transfer + direction is changing from the previous command; if IC_RESTART_EN + is 0, a STOP followed by a START is issued instead. 0 - + If IC_RESTART_EN is 1, a RESTART is issued only if the + transfer direction is changing from the previous command; + if IC_RESTART_EN is 0, a STOP followed by a START is issued + instead. Reset value: 0x0 */ + __IM uint32_t FIRST_DATA_BYTE : 1; /*!< Indicates the first data byte received after the address phase + for receive transfer in Master receiver or Slave receiver + mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, + 1. The user has to perform two APB Reads to IC_DATA_CMD + in order to get status on 11 bit. 2. In order to read the + 11 bit, the user has to perform the first data byte read + [7:0] (offset 0x10) and then perform the second read [15:8] + (offset 0x11) in order to know the status of 11 bit (whether + the data received in previous read is a first data byte + or not). 3. The 11th bit is an optional read field, user + can ignore 2nd byte read [15:8] (offset 0x11) if not interested + in FIRST_DATA_BYTE status. */ + uint32_t : 20; + } bit; + } IC_DATA_CMD; + + union { + __IOM uint32_t reg; /*!< Standard Speed I2C Clock SCL High Count Register */ + + struct { + __IOM uint32_t IC_SS_SCL_HCNT : 16; /*!< This register must be set before any I2C bus transaction can + take place to ensure proper I/O timing. This register sets + the SCL clock high-period count for standard speed. For + more information, refer to 'IC_CLK Frequency Configuration'. + This register can be written only when the I2C interface + is disabled which corresponds to the IC_ENABLE[0] register + being set to 0. Writes at other times have no effect. The + minimum valid value is 6; hardware prevents values less + than this being written, and if attempted results in 6 + being set. For designs with APB_DATA_WIDTH = 8, the order + of programming is important to ensure the correct operation + of the DW_apb_i2c. The lower byte must be programmed first. + Then the upper byte is programmed. NOTE: This register + must not be programmed to a value higher than 65525, because + DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle + condition when this counter reaches a value of IC_SS_SCL_HCNT + + 10. */ + uint32_t : 16; + } bit; + } IC_SS_SCL_HCNT; + + union { + __IOM uint32_t reg; /*!< Standard Speed I2C Clock SCL Low Count Register */ + + struct { + __IOM uint32_t IC_SS_SCL_LCNT : 16; /*!< This register must be set before any I2C bus transaction can + take place to ensure proper I/O timing. This register sets + the SCL clock low period count for standard speed. For + more information, refer to 'IC_CLK Frequency Configuration' + This register can be written only when the I2C interface + is disabled which corresponds to the IC_ENABLE[0] register + being set to 0. Writes at other times have no effect. The + minimum valid value is 8; hardware prevents values less + than this being written, and if attempted, results in 8 + being set. For designs with APB_DATA_WIDTH = 8, the order + of programming is important to ensure the correct operation + of DW_apb_i2c. The lower byte must be programmed first, + and then the upper byte is programmed. */ + uint32_t : 16; + } bit; + } IC_SS_SCL_LCNT; + + union { + __IOM uint32_t reg; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ + + struct { + __IOM uint32_t IC_FS_SCL_HCNT : 16; /*!< This register must be set before any I2C bus transaction can + take place to ensure proper I/O timing. This register sets + the SCL clock high-period count for fast mode or fast mode + plus. It is used in high-speed mode to send the Master + Code and START BYTE or General CALL. For more information, + refer to 'IC_CLK Frequency Configuration'. This register + goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE + = standard. This register can be written only when the + I2C interface is disabled, which corresponds to the IC_ENABLE[0] + register being set to 0. Writes at other times have no + effect. The minimum valid value is 6; hardware prevents + values less than this being written, and if attempted results + in 6 being set. For designs with APB_DATA_WIDTH == 8 the + order of programming is important to ensure the correct + operation of the DW_apb_i2c. The lower byte must be programmed + first. Then the upper byte is programmed. */ + uint32_t : 16; + } bit; + } IC_FS_SCL_HCNT; + + union { + __IOM uint32_t reg; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ + + struct { + __IOM uint32_t IC_FS_SCL_LCNT : 16; /*!< This register must be set before any I2C bus transaction can + take place to ensure proper I/O timing. This register sets + the SCL clock low period count for fast speed. It is used + in high-speed mode to send the Master Code and START BYTE + or General CALL. For more information, refer to 'IC_CLK + Frequency Configuration'. This register goes away and becomes + read-only returning 0s if IC_MAX_SPEED_MODE = standard. + This register can be written only when the I2C interface + is disabled, which corresponds to the IC_ENABLE[0] register + being set to 0. Writes at other times have no effect. The + minimum valid value is 8; hardware prevents values less + than this being written, and if attempted results in 8 + being set. For designs with APB_DATA_WIDTH = 8 the order + of programming is important to ensure the correct operation + of the DW_apb_i2c. The lower byte must be programmed first. + Then the upper byte is programmed. If the value is less + than 8 then the count value gets changed to 8. */ + uint32_t : 16; + } bit; + } IC_FS_SCL_LCNT; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t reg; /*!< I2C Interrupt Status Register Each bit in this register has + a corresponding mask bit in the IC_INTR_MASK register. + These bits are cleared by reading the matching interrupt + clear register. The unmasked raw versions of these bits + are available in the IC_RAW_INTR_STAT register. */ + + struct { + __IM uint32_t R_RX_UNDER : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER + bit. Reset value: 0x0 */ + __IM uint32_t R_RX_OVER : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER + bit. Reset value: 0x0 */ + __IM uint32_t R_RX_FULL : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL + bit. Reset value: 0x0 */ + __IM uint32_t R_TX_OVER : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER + bit. Reset value: 0x0 */ + __IM uint32_t R_TX_EMPTY : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY + bit. Reset value: 0x0 */ + __IM uint32_t R_RD_REQ : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ + bit. Reset value: 0x0 */ + __IM uint32_t R_TX_ABRT : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT + bit. Reset value: 0x0 */ + __IM uint32_t R_RX_DONE : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE + bit. Reset value: 0x0 */ + __IM uint32_t R_ACTIVITY : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY + bit. Reset value: 0x0 */ + __IM uint32_t R_STOP_DET : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET + bit. Reset value: 0x0 */ + __IM uint32_t R_START_DET : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_START_DET + bit. Reset value: 0x0 */ + __IM uint32_t R_GEN_CALL : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL + bit. Reset value: 0x0 */ + __IM uint32_t R_RESTART_DET : 1; /*!< See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET + bit. Reset value: 0x0 */ + uint32_t : 19; + } bit; + } IC_INTR_STAT; + + union { + __IOM uint32_t reg; /*!< I2C Interrupt Mask Register. These bits mask their corresponding + interrupt status bits. This register is active low; a value + of 0 masks the interrupt, whereas a value of 1 unmasks + the interrupt. */ + + struct { + __IOM uint32_t M_RX_UNDER : 1; /*!< This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + Reset value: 0x1 */ + __IOM uint32_t M_RX_OVER : 1; /*!< This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + Reset value: 0x1 */ + __IOM uint32_t M_RX_FULL : 1; /*!< This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + Reset value: 0x1 */ + __IOM uint32_t M_TX_OVER : 1; /*!< This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + Reset value: 0x1 */ + __IOM uint32_t M_TX_EMPTY : 1; /*!< This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + Reset value: 0x1 */ + __IOM uint32_t M_RD_REQ : 1; /*!< This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + Reset value: 0x1 */ + __IOM uint32_t M_TX_ABRT : 1; /*!< This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + Reset value: 0x1 */ + __IOM uint32_t M_RX_DONE : 1; /*!< This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + Reset value: 0x1 */ + __IOM uint32_t M_ACTIVITY : 1; /*!< This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + Reset value: 0x0 */ + __IOM uint32_t M_STOP_DET : 1; /*!< This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + Reset value: 0x0 */ + __IOM uint32_t M_START_DET : 1; /*!< This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + Reset value: 0x0 */ + __IOM uint32_t M_GEN_CALL : 1; /*!< This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + Reset value: 0x1 */ + __IOM uint32_t M_RESTART_DET : 1; /*!< This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + Reset value: 0x0 */ + uint32_t : 19; + } bit; + } IC_INTR_MASK; + + union { + __IOM uint32_t reg; /*!< I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, + these bits are not masked so they always show the true + status of the DW_apb_i2c. */ + + struct { + __IM uint32_t RX_UNDER : 1; /*!< Set if the processor attempts to read the receive buffer when + it is empty by reading from the IC_DATA_CMD register. If + the module is disabled (IC_ENABLE[0]=0), this bit keeps + its level until the master or slave state machines go into + idle, and when ic_en goes to 0, this interrupt is cleared. + Reset value: 0x0 */ + __IM uint32_t RX_OVER : 1; /*!< Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH + and an additional byte is received from an external I2C + device. The DW_apb_i2c acknowledges this, but any data + bytes received after the FIFO is full are lost. If the + module is disabled (IC_ENABLE[0]=0), this bit keeps its + level until the master or slave state machines go into + idle, and when ic_en goes to 0, this interrupt is cleared. + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) + is programmed to HIGH, then the RX_OVER interrupt never + occurs, because the Rx FIFO never overflows. Reset value: + 0x0 */ + __IM uint32_t RX_FULL : 1; /*!< Set when the receive buffer reaches or goes above the RX_TL + threshold in the IC_RX_TL register. It is automatically + cleared by hardware when buffer level goes below the threshold. + If the module is disabled (IC_ENABLE[0]=0), the RX FIFO + is flushed and held in reset; therefore the RX FIFO is + not full. So this bit is cleared once the IC_ENABLE bit + 0 is programmed with a 0, regardless of the activity that + continues. Reset value: 0x0 */ + __IM uint32_t TX_OVER : 1; /*!< Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH + and the processor attempts to issue another I2C command + by writing to the IC_DATA_CMD register. When the module + is disabled, this bit keeps its level until the master + or slave state machines go into idle, and when ic_en goes + to 0, this interrupt is cleared. Reset value: 0x0 */ + __IM uint32_t TX_EMPTY : 1; /*!< The behavior of the TX_EMPTY interrupt status differs based + on the TX_EMPTY_CTRL selection in the IC_CON register. + - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the + transmit buffer is at or below the threshold value set + in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This + bit is set to 1 when the transmit buffer is at or below + the threshold value set in the IC_TX_TL register and the + transmission of the address/data from the internal shift + register for the most recently popped command is completed. + It is automatically cleared by hardware when the buffer + level goes above the threshold. When IC_ENABLE[0] is set + to 0, the TX FIFO is flushed and held in reset. There the + TX FIFO looks like it has no data within it, so this bit + is set to 1, provided there is activity in the master or + slave state machines. When there is no longer any activity, + then with ic_en=0, this bit is set to 0. Reset value: 0x0. */ + __IM uint32_t RD_REQ : 1; /*!< This bit is set to 1 when DW_apb_i2c is acting as a slave and + another I2C master is attempting to read data from DW_apb_i2c. + The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) + until this interrupt is serviced, which means that the + slave has been addressed by a remote master that is asking + for data to be transferred. The processor must respond + to this interrupt and then write the requested data to + the IC_DATA_CMD register. This bit is set to 0 just after + the processor reads the IC_CLR_RD_REQ register. Reset value: + 0x0 */ + __IM uint32_t TX_ABRT : 1; /*!< This bit indicates if DW_apb_i2c, as an I2C transmitter, is + unable to complete the intended actions on the contents + of the transmit FIFO. This situation can occur both as + an I2C master or an I2C slave, and is referred to as a + 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE + register indicates the reason why the transmit abort takes + places. Note: The DW_apb_i2c flushes/resets/empties the + TX_FIFO and RX_FIFO whenever there is a transmit abort + caused by any of the events tracked by the IC_TX_ABRT_SOURCE + register. The FIFOs remains in this flushed state until + the register IC_CLR_TX_ABRT is read. Once this read is + performed, the Tx FIFO is then ready to accept more data + bytes from the APB interface. Reset value: 0x0 */ + __IM uint32_t RX_DONE : 1; /*!< When the DW_apb_i2c is acting as a slave-transmitter, this bit + is set to 1 if the master does not acknowledge a transmitted + byte. This occurs on the last byte of the transmission, + indicating that the transmission is done. Reset value: + 0x0 */ + __IM uint32_t ACTIVITY : 1; /*!< This bit captures DW_apb_i2c activity and stays set until it + is cleared. There are four ways to clear it: - Disabling + the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - + Reading the IC_CLR_INTR register - System reset Once this + bit is set, it stays set unless one of the four methods + is used to clear it. Even if the DW_apb_i2c module is idle, + this bit remains set until cleared, indicating that there + was activity on the bus. Reset value: 0x0 */ + __IM uint32_t STOP_DET : 1; /*!< Indicates whether a STOP condition has occurred on the I2C interface + regardless of whether DW_apb_i2c is operating in slave + or master mode. In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED) + the STOP_DET interrupt will be issued only if slave is + addressed. Note: During a general call address, this slave + does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, + even if the slave responds to the general call address + by generating ACK. The STOP_DET interrupt is generated + only when the transmitted address matches the slave address + (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the + STOP_DET interrupt is issued irrespective of whether it + is being addressed. In Master Mode: - If IC_CON[10]=1'b1 + (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will + be issued only if Master is active. - If IC_CON[10]=1'b0 + (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued + irrespective of whether master is active or not. Reset + value: 0x0 */ + __IM uint32_t START_DET : 1; /*!< Indicates whether a START or RESTART condition has occurred + on the I2C interface regardless of whether DW_apb_i2c is + operating in slave or master mode. Reset value: 0x0 */ + __IM uint32_t GEN_CALL : 1; /*!< Set only when a General Call address is received and it is acknowledged. + It stays set until it is cleared either by disabling DW_apb_i2c + or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. + DW_apb_i2c stores the received data in the Rx buffer. Reset + value: 0x0 */ + __IM uint32_t RESTART_DET : 1; /*!< Indicates whether a RESTART condition has occurred on the I2C + interface when DW_apb_i2c is operating in Slave mode and + the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + Note: However, in high-speed mode or during a START BYTE + transfer, the RESTART comes before the address field as + per the I2C protocol. In this case, the slave is not the + addressed slave when the RESTART is issued, therefore DW_apb_i2c + does not generate the RESTART_DET interrupt. Reset value: + 0x0 */ + uint32_t : 19; + } bit; + } IC_RAW_INTR_STAT; + + union { + __IOM uint32_t reg; /*!< I2C Receive FIFO Threshold Register */ + + struct { + __IOM uint32_t RX_TL : 8; /*!< Receive FIFO Threshold Level. Controls the level of entries + (or above) that triggers the RX_FULL interrupt (bit 2 in + IC_RAW_INTR_STAT register). The valid range is 0-255, with + the additional restriction that hardware does not allow + this value to be set to a value larger than the depth of + the buffer. If an attempt is made to do that, the actual + value set will be the maximum depth of the buffer. A value + of 0 sets the threshold for 1 entry, and a value of 255 + sets the threshold for 256 entries. */ + uint32_t : 24; + } bit; + } IC_RX_TL; + + union { + __IOM uint32_t reg; /*!< I2C Transmit FIFO Threshold Register */ + + struct { + __IOM uint32_t TX_TL : 8; /*!< Transmit FIFO Threshold Level. Controls the level of entries + (or below) that trigger the TX_EMPTY interrupt (bit 4 in + IC_RAW_INTR_STAT register). The valid range is 0-255, with + the additional restriction that it may not be set to value + larger than the depth of the buffer. If an attempt is made + to do that, the actual value set will be the maximum depth + of the buffer. A value of 0 sets the threshold for 0 entries, + and a value of 255 sets the threshold for 255 entries. */ + uint32_t : 24; + } bit; + } IC_TX_TL; + + union { + __IOM uint32_t reg; /*!< Clear Combined and Individual Interrupt Register */ + + struct { + __IM uint32_t CLR_INTR : 1; /*!< Read this register to clear the combined interrupt, all individual + interrupts, and the IC_TX_ABRT_SOURCE register. This bit + does not clear hardware clearable interrupts but software + clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE + register for an exception to clearing IC_TX_ABRT_SOURCE. + Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_INTR; + + union { + __IOM uint32_t reg; /*!< Clear RX_UNDER Interrupt Register */ + + struct { + __IM uint32_t CLR_RX_UNDER : 1; /*!< Read this register to clear the RX_UNDER interrupt (bit 0) of + the IC_RAW_INTR_STAT register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_RX_UNDER; + + union { + __IOM uint32_t reg; /*!< Clear RX_OVER Interrupt Register */ + + struct { + __IM uint32_t CLR_RX_OVER : 1; /*!< Read this register to clear the RX_OVER interrupt (bit 1) of + the IC_RAW_INTR_STAT register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_RX_OVER; + + union { + __IOM uint32_t reg; /*!< Clear TX_OVER Interrupt Register */ + + struct { + __IM uint32_t CLR_TX_OVER : 1; /*!< Read this register to clear the TX_OVER interrupt (bit 3) of + the IC_RAW_INTR_STAT register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_TX_OVER; + + union { + __IOM uint32_t reg; /*!< Clear RD_REQ Interrupt Register */ + + struct { + __IM uint32_t CLR_RD_REQ : 1; /*!< Read this register to clear the RD_REQ interrupt (bit 5) of + the IC_RAW_INTR_STAT register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_RD_REQ; + + union { + __IOM uint32_t reg; /*!< Clear TX_ABRT Interrupt Register */ + + struct { + __IM uint32_t CLR_TX_ABRT : 1; /*!< Read this register to clear the TX_ABRT interrupt (bit 6) of + the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE + register. This also releases the TX FIFO from the flushed/reset + state, allowing more writes to the TX FIFO. Refer to Bit + 9 of the IC_TX_ABRT_SOURCE register for an exception to + clearing IC_TX_ABRT_SOURCE. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_TX_ABRT; + + union { + __IOM uint32_t reg; /*!< Clear RX_DONE Interrupt Register */ + + struct { + __IM uint32_t CLR_RX_DONE : 1; /*!< Read this register to clear the RX_DONE interrupt (bit 7) of + the IC_RAW_INTR_STAT register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_RX_DONE; + + union { + __IOM uint32_t reg; /*!< Clear ACTIVITY Interrupt Register */ + + struct { + __IM uint32_t CLR_ACTIVITY : 1; /*!< Reading this register clears the ACTIVITY interrupt if the I2C + is not active anymore. If the I2C module is still active + on the bus, the ACTIVITY interrupt bit continues to be + set. It is automatically cleared by hardware if the module + is disabled and if there is no further activity on the + bus. The value read from this register to get status of + the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT + register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_ACTIVITY; + + union { + __IOM uint32_t reg; /*!< Clear STOP_DET Interrupt Register */ + + struct { + __IM uint32_t CLR_STOP_DET : 1; /*!< Read this register to clear the STOP_DET interrupt (bit 9) of + the IC_RAW_INTR_STAT register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_STOP_DET; + + union { + __IOM uint32_t reg; /*!< Clear START_DET Interrupt Register */ + + struct { + __IM uint32_t CLR_START_DET : 1; /*!< Read this register to clear the START_DET interrupt (bit 10) + of the IC_RAW_INTR_STAT register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_START_DET; + + union { + __IOM uint32_t reg; /*!< Clear GEN_CALL Interrupt Register */ + + struct { + __IM uint32_t CLR_GEN_CALL : 1; /*!< Read this register to clear the GEN_CALL interrupt (bit 11) + of IC_RAW_INTR_STAT register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_GEN_CALL; + + union { + __IOM uint32_t reg; /*!< I2C Enable Register */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c + (TX and RX FIFOs are held in an erased state) - 1: Enables + DW_apb_i2c Software can disable DW_apb_i2c while it is + active. However, it is important that care be taken to + ensure that DW_apb_i2c is disabled properly. A recommended + procedure is described in 'Disabling DW_apb_i2c'. When + DW_apb_i2c is disabled, the following occurs: - The TX + FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT + register are still active until DW_apb_i2c goes into IDLE + state. If the module is transmitting, it stops as well + as deletes the contents of the transmit buffer after the + current transfer is complete. If the module is receiving, + the DW_apb_i2c stops the current transfer at the end of + the current byte and does not acknowledge the transfer. + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE + parameter set to asynchronous (1), there is a two ic_clk + delay when enabling or disabling the DW_apb_i2c. For a + detailed description on how to disable DW_apb_i2c, refer + to 'Disabling DW_apb_i2c' Reset value: 0x0 */ + __IOM uint32_t ABORT : 1; /*!< When set, the controller initiates the transfer abort. - 0: + ABORT not initiated or ABORT done - 1: ABORT operation + in progress The software can abort the I2C transfer in + master mode by setting this bit. The software can set this + bit only when ENABLE is already set; otherwise, the controller + ignores any write to ABORT bit. The software cannot clear + the ABORT bit once set. In response to an ABORT, the controller + issues a STOP and flushes the Tx FIFO after completing + the current transfer, then sets the TX_ABORT interrupt + after the abort operation. The ABORT bit is cleared automatically + after the abort operation. For a detailed description on + how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + Reset value: 0x0 */ + __IOM uint32_t TX_CMD_BLOCK : 1; /*!< In Master mode: - 1'b1: Blocks the transmission of data on I2C + bus even if Tx FIFO has data to transmit. - 1'b0: The transmission + of data starts on I2C bus automatically, as soon as the + first data is available in the Tx FIFO. Note: To block + the execution of Master commands, set the TX_CMD_BLOCK + bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master + is in Idle state (IC_STATUS[5] == 0). Any further commands + put in the Tx FIFO are not executed until TX_CMD_BLOCK + bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT */ + uint32_t : 29; + } bit; + } IC_ENABLE; + + union { + __IOM uint32_t reg; /*!< I2C Status Register This is a read-only register used to indicate + the current transfer status and FIFO status. The status + register may be read at any time. None of the bits in this + register request an interrupt. When the I2C is disabled + by writing 0 in bit 0 of the IC_ENABLE register: - Bits + 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When + the master or slave state machines goes to idle and ic_en=0: + - Bits 5 and 6 are set to 0 */ + + struct { + __IM uint32_t ACTIVITY : 1; /*!< I2C Activity Status. Reset value: 0x0 */ + __IM uint32_t TFNF : 1; /*!< Transmit FIFO Not Full. Set when the transmit FIFO contains + one or more empty locations, and is cleared when the FIFO + is full. - 0: Transmit FIFO is full - 1: Transmit FIFO + is not full Reset value: 0x1 */ + __IM uint32_t TFE : 1; /*!< Transmit FIFO Completely Empty. When the transmit FIFO is completely + empty, this bit is set. When it contains one or more valid + entries, this bit is cleared. This bit field does not request + an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit + FIFO is empty Reset value: 0x1 */ + __IM uint32_t RFNE : 1; /*!< Receive FIFO Not Empty. This bit is set when the receive FIFO + contains one or more entries; it is cleared when the receive + FIFO is empty. - 0: Receive FIFO is empty - 1: Receive + FIFO is not empty Reset value: 0x0 */ + __IM uint32_t RFF : 1; /*!< Receive FIFO Completely Full. When the receive FIFO is completely + full, this bit is set. When the receive FIFO contains one + or more empty location, this bit is cleared. - 0: Receive + FIFO is not full - 1: Receive FIFO is full Reset value: + 0x0 */ + __IM uint32_t MST_ACTIVITY : 1; /*!< Master FSM Activity Status. When the Master Finite State Machine + (FSM) is not in the IDLE state, this bit is set. - 0: Master + FSM is in IDLE state so the Master part of DW_apb_i2c is + not Active - 1: Master FSM is not in IDLE state so the + Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that + is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY + bits. Reset value: 0x0 */ + __IM uint32_t SLV_ACTIVITY : 1; /*!< Slave FSM Activity Status. When the Slave Finite State Machine + (FSM) is not in the IDLE state, this bit is set. - 0: Slave + FSM is in IDLE state so the Slave part of DW_apb_i2c is + not Active - 1: Slave FSM is not in IDLE state so the Slave + part of DW_apb_i2c is Active Reset value: 0x0 */ + uint32_t : 25; + } bit; + } IC_STATUS; + + union { + __IOM uint32_t reg; /*!< I2C Transmit FIFO Level Register This register contains the + number of valid data entries in the transmit FIFO buffer. + It is cleared whenever: - The I2C is disabled - There is + a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT + register - The slave bulk transmit mode is aborted The + register increments whenever data is placed into the transmit + FIFO and decrements when data is taken from the transmit + FIFO. */ + + struct { + __IM uint32_t TXFLR : 5; /*!< Transmit FIFO Level. Contains the number of valid data entries + in the transmit FIFO. Reset value: 0x0 */ + uint32_t : 27; + } bit; + } IC_TXFLR; + + union { + __IOM uint32_t reg; /*!< I2C Receive FIFO Level Register This register contains the number + of valid data entries in the receive FIFO buffer. It is + cleared whenever: - The I2C is disabled - Whenever there + is a transmit abort caused by any of the events tracked + in IC_TX_ABRT_SOURCE The register increments whenever data + is placed into the receive FIFO and decrements when data + is taken from the receive FIFO. */ + + struct { + __IM uint32_t RXFLR : 5; /*!< Receive FIFO Level. Contains the number of valid data entries + in the receive FIFO. Reset value: 0x0 */ + uint32_t : 27; + } bit; + } IC_RXFLR; + + union { + __IOM uint32_t reg; /*!< I2C SDA Hold Time Length Register The bits [15:0] of this register + are used to control the hold time of SDA during transmit + in both slave and master mode (after SCL goes from HIGH + to LOW). The bits [23:16] of this register are used to + extend the SDA transition (if any) whenever SCL is HIGH + in the receiver in either master or slave mode. Writes + to this register succeed only when IC_ENABLE[0]=0. The + values in this register are in units of ic_clk period. + The value programmed in IC_SDA_TX_HOLD must be greater + than the minimum hold time in each mode (one cycle in master + mode, seven cycles in slave mode) for the value to be implemented. + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) + cannot exceed at any time the duration of the low part + of scl. Therefore the programmed value cannot be larger + than N_SCL_LOW-2, where N_SCL_LOW is the duration of the + low part of the scl period measured in ic_clk cycles. */ + + struct { + __IOM uint32_t IC_SDA_TX_HOLD : 16; /*!< Sets the required SDA hold time in units of ic_clk period, when + DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD[15:0]. */ + __IOM uint32_t IC_SDA_RX_HOLD : 8; /*!< Sets the required SDA hold time in units of ic_clk period, when + DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD[23:16]. */ + uint32_t : 8; + } bit; + } IC_SDA_HOLD; + + union { + __IOM uint32_t reg; /*!< I2C Transmit Abort Source Register This register has 32 bits + that indicate the source of the TX_ABRT bit. Except for + Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT + register or the IC_CLR_INTR register is read. To clear + Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed + first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL + bit must be cleared (IC_TAR[11]), or the GC_OR_START bit + must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT + is fixed, then this bit can be cleared in the same manner + as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT + is not fixed before attempting to clear this bit, Bit 9 + clears for one cycle and is then re-asserted. */ + + struct { + __IM uint32_t ABRT_7B_ADDR_NOACK : 1; /*!< This field indicates that the Master is in 7-bit addressing + mode and the address sent was not acknowledged by any slave. + Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter + or Master-Receiver */ + __IM uint32_t ABRT_10ADDR1_NOACK : 1; /*!< This field indicates that the Master is in 10-bit address mode + and the first 10-bit address byte was not acknowledged + by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter + or Master-Receiver */ + __IM uint32_t ABRT_10ADDR2_NOACK : 1; /*!< This field indicates that the Master is in 10-bit address mode + and that the second address byte of the 10-bit address + was not acknowledged by any slave. Reset value: 0x0 Role + of DW_apb_i2c: Master-Transmitter or Master-Receiver */ + __IM uint32_t ABRT_TXDATA_NOACK : 1; /*!< This field indicates the master-mode only bit. When the master + receives an acknowledgement for the address, but when it + sends data byte(s) following the address, it did not receive + an acknowledge from the remote slave(s). Reset value: 0x0 + Role of DW_apb_i2c: Master-Transmitter */ + __IM uint32_t ABRT_GCALL_NOACK : 1; /*!< This field indicates that DW_apb_i2c in master mode has sent + a General Call and no slave on the bus acknowledged the + General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter */ + __IM uint32_t ABRT_GCALL_READ : 1; /*!< This field indicates that DW_apb_i2c in the master mode has + sent a General Call but the user programmed the byte following + the General Call to be a read from the bus (IC_DATA_CMD[9] + is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter */ + __IM uint32_t ABRT_HS_ACKDET : 1; /*!< This field indicates that the Master is in High Speed mode and + the High Speed Master code was acknowledged (wrong behavior). + Reset value: 0x0 Role of DW_apb_i2c: Master */ + __IM uint32_t ABRT_SBYTE_ACKDET : 1; /*!< This field indicates that the Master has sent a START Byte and + the START Byte was acknowledged (wrong behavior). Reset + value: 0x0 Role of DW_apb_i2c: Master */ + __IM uint32_t ABRT_HS_NORSTRT : 1; /*!< This field indicates that the restart is disabled (IC_RESTART_EN + bit (IC_CON[5]) =0) and the user is trying to use the master + to transfer data in High Speed mode. Reset value: 0x0 Role + of DW_apb_i2c: Master-Transmitter or Master-Receiver */ + __IM uint32_t ABRT_SBYTE_NORSTRT : 1; /*!< To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be + fixed first; restart must be enabled (IC_CON[5]=1), the + SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START + bit must be cleared (IC_TAR[10]). Once the source of the + ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared + in the same manner as other bits in this register. If the + source of the ABRT_SBYTE_NORSTRT is not fixed before attempting + to clear this bit, bit 9 clears for one cycle and then + gets reasserted. When this field is set to 1, the restart + is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the + user is trying to send a START Byte. Reset value: 0x0 Role + of DW_apb_i2c: Master */ + __IM uint32_t ABRT_10B_RD_NORSTRT : 1; /*!< This field indicates that the restart is disabled (IC_RESTART_EN + bit (IC_CON[5]) =0) and the master sends a read command + in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: + Master-Receiver */ + __IM uint32_t ABRT_MASTER_DIS : 1; /*!< This field indicates that the User tries to initiate a Master + operation with the Master mode disabled. Reset value: 0x0 + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver */ + __IM uint32_t ARB_LOST : 1; /*!< This field specifies that the Master has lost arbitration, or + if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter + has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: + Master-Transmitter or Slave-Transmitter */ + __IM uint32_t ABRT_SLVFLUSH_TXFIFO : 1; /*!< This field specifies that the Slave has received a read command + and some data exists in the TX FIFO, so the slave issues + a TX_ABRT interrupt to flush old data in TX FIFO. Reset + value: 0x0 Role of DW_apb_i2c: Slave-Transmitter */ + __IM uint32_t ABRT_SLV_ARBLOST : 1; /*!< This field indicates that a Slave has lost the bus while transmitting + data to a remote master. IC_TX_ABRT_SOURCE[12] is set at + the same time. Note: Even though the slave never 'owns' + the bus, something could go wrong on the bus. This is a + fail safe check. For instance, during a data transmission + at the low-to-high transition of SCL, if what is on the + data bus is not what is supposed to be transmitted, then + DW_apb_i2c no longer own the bus. Reset value: 0x0 Role + of DW_apb_i2c: Slave-Transmitter */ + __IM uint32_t ABRT_SLVRD_INTX : 1; /*!< 1: When the processor side responds to a slave mode request + for data to be transmitted to a remote master and user + writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset + value: 0x0 Role of DW_apb_i2c: Slave-Transmitter */ + __IM uint32_t ABRT_USER_ABRT : 1; /*!< This is a master-mode-only bit. Master has detected the transfer + abort (IC_ENABLE[1]) Reset value: 0x0 Role of DW_apb_i2c: + Master-Transmitter */ + uint32_t : 6; + __IM uint32_t TX_FLUSH_CNT : 9; /*!< This field indicates the number of Tx FIFO Data Commands which + are flushed due to TX_ABRT interrupt. It is cleared whenever + I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter + or Slave-Transmitter */ + } bit; + } IC_TX_ABRT_SOURCE; + + union { + __IOM uint32_t reg; /*!< Generate Slave Data NACK Register The register is used to generate + a NACK for the data part of a transfer when DW_apb_i2c + is acting as a slave-receiver. This register only exists + when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When + this parameter disabled, this register does not exist and + writing to the register's address has no effect. A write + can occur on this register if both of the following conditions + are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - + Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] + is a register read-back location for the internal slv_activity + signal; the user should poll this before writing the ic_slv_data_nack_onl + bit. */ + + struct { + __IOM uint32_t NACK : 1; /*!< Generate NACK. This NACK generation only occurs when DW_apb_i2c + is a slave-receiver. If this register is set to a value + of 1, it can only generate a NACK after a data byte is + received; hence, the data transfer is aborted and the data + received is not pushed to the receive buffer. When the + register is set to a value of 0, it generates NACK/ACK, + depending on normal criteria. - 1: generate NACK after + data byte received - 0: generate NACK/ACK normally Reset + value: 0x0 */ + uint32_t : 31; + } bit; + } IC_SLV_DATA_NACK_ONLY; + + union { + __IOM uint32_t reg; /*!< DMA Control Register The register is used to enable the DMA + Controller interface operation. There is a separate bit + for transmit and receive. This can be programmed regardless + of the state of IC_ENABLE. */ + + struct { + __IOM uint32_t RDMAE : 1; /*!< Receive DMA Enable. This bit enables/disables the receive FIFO + DMA channel. Reset value: 0x0 */ + __IOM uint32_t TDMAE : 1; /*!< Transmit DMA Enable. This bit enables/disables the transmit + FIFO DMA channel. Reset value: 0x0 */ + uint32_t : 30; + } bit; + } IC_DMA_CR; + + union { + __IOM uint32_t reg; /*!< DMA Transmit Data Level Register */ + + struct { + __IOM uint32_t DMATDL : 4; /*!< Transmit Data Level. This bit field controls the level at which + a DMA request is made by the transmit logic. It is equal + to the watermark level; that is, the dma_tx_req signal + is generated when the number of valid data entries in the + transmit FIFO is equal to or below this field value, and + TDMAE = 1. Reset value: 0x0 */ + uint32_t : 28; + } bit; + } IC_DMA_TDLR; + + union { + __IOM uint32_t reg; /*!< I2C Receive Data Level Register */ + + struct { + __IOM uint32_t DMARDL : 4; /*!< Receive Data Level. This bit field controls the level at which + a DMA request is made by the receive logic. The watermark + level = DMARDL+1; that is, dma_rx_req is generated when + the number of valid data entries in the receive FIFO is + equal to or more than this field value + 1, and RDMAE =1. + For instance, when DMARDL is 0, then dma_rx_req is asserted + when 1 or more data entries are present in the receive + FIFO. Reset value: 0x0 */ + uint32_t : 28; + } bit; + } IC_DMA_RDLR; + + union { + __IOM uint32_t reg; /*!< I2C SDA Setup Register This register controls the amount of + time delay (in terms of number of ic_clk clock periods) + introduced in the rising edge of SCL - relative to SDA + changing - when DW_apb_i2c services a read request in a + slave-transmitter operation. The relevant I2C requirement + is tSU:DAT (note 4) as detailed in the I2C Bus Specification. + This register must be programmed with a value equal to + or greater than 2. Writes to this register succeed only + when IC_ENABLE[0] = 0. Note: The length of setup time is + calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], + so if the user requires 10 ic_clk periods of setup time, + they should program a value of 11. The IC_SDA_SETUP register + is only used by the DW_apb_i2c when operating as a slave + transmitter. */ + + struct { + __IOM uint32_t SDA_SETUP : 8; /*!< SDA Setup. It is recommended that if the required delay is 1000ns, + then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should + be programmed to a value of 11. IC_SDA_SETUP must be programmed + with a minimum value of 2. */ + uint32_t : 24; + } bit; + } IC_SDA_SETUP; + + union { + __IOM uint32_t reg; /*!< I2C ACK General Call Register The register controls whether + DW_apb_i2c responds with a ACK or NACK when it receives + an I2C General Call address. This register is applicable + only when the DW_apb_i2c is in slave mode. */ + + struct { + __IOM uint32_t ACK_GEN_CALL : 1; /*!< ACK General Call. When set to 1, DW_apb_i2c responds with a + ACK (by asserting ic_data_oe) when it receives a General + Call. Otherwise, DW_apb_i2c responds with a NACK (by negating + ic_data_oe). */ + uint32_t : 31; + } bit; + } IC_ACK_GENERAL_CALL; + + union { + __IOM uint32_t reg; /*!< I2C Enable Status Register The register is used to report the + DW_apb_i2c hardware status when the IC_ENABLE[0] register + is set from 1 to 0; that is, when DW_apb_i2c is disabled. + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced + to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been + set to 0, bits 2:1 is only be valid as soon as bit 0 is + read as '0'. Note: When IC_ENABLE[0] has been set to 0, + a delay occurs for bit 0 to be read as 0 because disabling + the DW_apb_i2c depends on I2C bus activities. */ + + struct { + __IM uint32_t IC_EN : 1; /*!< ic_en Status. This bit always reflects the value driven on the + output port ic_en. - When read as 1, DW_apb_i2c is deemed + to be in an enabled state. - When read as 0, DW_apb_i2c + is deemed completely inactive. Note: The CPU can safely + read this bit anytime. When this bit is read as 0, the + CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY + (bit 1). Reset value: 0x0 */ + __IM uint32_t SLV_DISABLED_WHILE_BUSY : 1;/*!< Slave Disabled While Busy (Transmit, Receive). This bit indicates + if a potential or active Slave operation has been aborted + due to the setting bit 0 of the IC_ENABLE register from + 1 to 0. This bit is set when the CPU writes a 0 to the + IC_ENABLE register while: (a) DW_apb_i2c is receiving the + address byte of the Slave-Transmitter operation from a + remote master; OR, (b) address and data bytes of the Slave-Receiver + operation from a remote master. When read as 1, DW_apb_i2c + is deemed to have forced a NACK during any part of an I2C + transfer, irrespective of whether the I2C address matches + the slave address set in DW_apb_i2c (IC_SAR register) OR + if the transfer is completed before IC_ENABLE is set to + 0 but has not taken effect. Note: If the remote I2C master + terminates the transfer with a STOP condition before the + DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] + has been set to 0, then this bit will also be set to 1. + When read as 0, DW_apb_i2c is deemed to have been disabled + when there is master activity, or when the I2C bus is idle. + Note: The CPU can safely read this bit when IC_EN (bit + 0) is read as 0. Reset value: 0x0 */ + __IM uint32_t SLV_RX_DATA_LOST : 1; /*!< Slave Received Data Lost. This bit indicates if a Slave-Receiver + operation has been aborted with at least one data byte + received from an I2C transfer due to the setting bit 0 + of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is + deemed to have been actively engaged in an aborted I2C + transfer (with matching address) and the data phase of + the I2C transfer has been entered, even though a data byte + has been responded with a NACK. Note: If the remote I2C + master terminates the transfer with a STOP condition before + the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] + has been set to 0, then this bit is also set to 1. When + read as 0, DW_apb_i2c is deemed to have been disabled without + being actively involved in the data phase of a Slave-Receiver + transfer. Note: The CPU can safely read this bit when IC_EN + (bit 0) is read as 0. Reset value: 0x0 */ + uint32_t : 29; + } bit; + } IC_ENABLE_STATUS; + + union { + __IOM uint32_t reg; /*!< I2C SS, FS or FM+ spike suppression limit This register is used + to store the duration, measured in ic_clk cycles, of the + longest spike that is filtered out by the spike suppression + logic when the component is operating in SS, FS or FM+ + modes. The relevant I2C requirement is tSP (table 4) as + detailed in the I2C Bus Specification. This register must + be programmed with a minimum value of 1. */ + + struct { + __IOM uint32_t IC_FS_SPKLEN : 8; /*!< This register must be set before any I2C bus transaction can + take place to ensure stable operation. This register sets + the duration, measured in ic_clk cycles, of the longest + spike in the SCL or SDA lines that will be filtered out + by the spike suppression logic. This register can be written + only when the I2C interface is disabled which corresponds + to the IC_ENABLE[0] register being set to 0. Writes at + other times have no effect. The minimum valid value is + 1; hardware prevents values less than this being written, + and if attempted results in 1 being set. or more information, + refer to 'Spike Suppression'. */ + uint32_t : 24; + } bit; + } IC_FS_SPKLEN; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< Clear RESTART_DET Interrupt Register */ + + struct { + __IM uint32_t CLR_RESTART_DET : 1; /*!< Read this register to clear the RESTART_DET interrupt (bit 12) + of IC_RAW_INTR_STAT register. Reset value: 0x0 */ + uint32_t : 31; + } bit; + } IC_CLR_RESTART_DET; + __IM uint32_t RESERVED3[18]; + + union { + __IOM uint32_t reg; /*!< Component Parameter Register 1 Note This register is not implemented + and therefore reads as 0. If it was implemented it would + be a constant read-only register that contains encoded + information about the component's parameter settings. Fields + shown below are the settings for those parameters */ + + struct { + __IM uint32_t APB_DATA_WIDTH : 2; /*!< APB data bus width is 32 bits */ + __IM uint32_t MAX_SPEED_MODE : 2; /*!< MAX SPEED MODE = FAST MODE */ + __IM uint32_t HC_COUNT_VALUES : 1; /*!< Programmable count values for each mode. */ + __IM uint32_t INTR_IO : 1; /*!< COMBINED Interrupt outputs */ + __IM uint32_t HAS_DMA : 1; /*!< DMA handshaking signals are enabled */ + __IM uint32_t ADD_ENCODED_PARAMS : 1; /*!< Encoded parameters not visible */ + __IM uint32_t RX_BUFFER_DEPTH : 8; /*!< RX Buffer Depth = 16 */ + __IM uint32_t TX_BUFFER_DEPTH : 8; /*!< TX Buffer Depth = 16 */ + uint32_t : 8; + } bit; + } IC_COMP_PARAM_1; + + union { + __IOM uint32_t reg; /*!< I2C Component Version Register */ + + struct { + __IM uint32_t IC_COMP_VERSION : 32; /*!< IC_COMP_VERSION */ + } bit; + } IC_COMP_VERSION; + + union { + __IOM uint32_t reg; /*!< I2C Component Type Register */ + + struct { + __IM uint32_t IC_COMP_TYPE : 32; /*!< Designware Component Type number = 0x44_57_01_40. This assigned + unique hex value is constant and is derived from the two + ASCII letters 'DW' followed by a 16-bit unsigned number. */ + } bit; + } IC_COMP_TYPE; +} I2C0_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SPI0) + */ + +typedef struct { /*!< SPI0 Structure */ + + union { + __IOM uint32_t reg; /*!< Control register 0, SSPCR0 on page 3-4 */ + + struct { + __IOM uint32_t DSS : 4; /*!< Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, + undefined operation. 0010 Reserved, undefined operation. + 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 + 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit + data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. + 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. */ + __IOM uint32_t FRF : 2; /*!< Frame format: 00 Motorola SPI frame format. 01 TI synchronous + serial frame format. 10 National Microwire frame format. + 11 Reserved, undefined operation. */ + __IOM uint32_t SPO : 1; /*!< SSPCLKOUT polarity, applicable to Motorola SPI frame format + only. See Motorola SPI frame format on page 2-10. */ + __IOM uint32_t SPH : 1; /*!< SSPCLKOUT phase, applicable to Motorola SPI frame format only. + See Motorola SPI frame format on page 2-10. */ + __IOM uint32_t SCR : 8; /*!< Serial clock rate. The value SCR is used to generate the transmit + and receive bit rate of the PrimeCell SSP. The bit rate + is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even + value from 2-254, programmed through the SSPCPSR register + and SCR is a value from 0-255. */ + uint32_t : 16; + } bit; + } SSPCR0; + + union { + __IOM uint32_t reg; /*!< Control register 1, SSPCR1 on page 3-5 */ + + struct { + __IOM uint32_t LBM : 1; /*!< Loop back mode: 0 Normal serial port operation enabled. 1 Output + of transmit serial shifter is connected to input of receive + serial shifter internally. */ + __IOM uint32_t SSE : 1; /*!< Synchronous serial port enable: 0 SSP operation disabled. 1 + SSP operation enabled. */ + __IOM uint32_t MS : 1; /*!< Master or slave mode select. This bit can be modified only when + the PrimeCell SSP is disabled, SSE=0: 0 Device configured + as master, default. 1 Device configured as slave. */ + __IOM uint32_t SOD : 1; /*!< Slave-mode output disable. This bit is relevant only in the + slave mode, MS=1. In multiple-slave systems, it is possible + for an PrimeCell SSP master to broadcast a message to all + slaves in the system while ensuring that only one slave + drives data onto its serial output line. In such systems + the RXD lines from multiple slaves could be tied together. + To operate in such systems, the SOD bit can be set if the + PrimeCell SSP slave is not supposed to drive the SSPTXD + line: 0 SSP can drive the SSPTXD output in slave mode. + 1 SSP must not drive the SSPTXD output in slave mode. */ + uint32_t : 28; + } bit; + } SSPCR1; + + union { + __IOM uint32_t reg; /*!< Data register, SSPDR on page 3-6 */ + + struct { + __IOM uint32_t DATA : 16; /*!< Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. + You must right-justify data when the PrimeCell SSP is programmed + for a data size that is less than 16 bits. Unused bits + at the top are ignored by transmit logic. The receive logic + automatically right-justifies. */ + uint32_t : 16; + } bit; + } SSPDR; + + union { + __IOM uint32_t reg; /*!< Status register, SSPSR on page 3-7 */ + + struct { + __IM uint32_t TFE : 1; /*!< Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit + FIFO is empty. */ + __IM uint32_t TNF : 1; /*!< Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit + FIFO is not full. */ + __IM uint32_t RNE : 1; /*!< Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive + FIFO is not empty. */ + __IM uint32_t RFF : 1; /*!< Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive + FIFO is full. */ + __IM uint32_t BSY : 1; /*!< PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently + transmitting and/or receiving a frame or the transmit FIFO + is not empty. */ + uint32_t : 27; + } bit; + } SSPSR; + + union { + __IOM uint32_t reg; /*!< Clock prescale register, SSPCPSR on page 3-8 */ + + struct { + __IOM uint32_t CPSDVSR : 8; /*!< Clock prescale divisor. Must be an even number from 2-254, depending + on the frequency of SSPCLK. The least significant bit always + returns zero on reads. */ + uint32_t : 24; + } bit; + } SSPCPSR; + + union { + __IOM uint32_t reg; /*!< Interrupt mask set or clear register, SSPIMSC on page 3-9 */ + + struct { + __IOM uint32_t RORIM : 1; /*!< Receive overrun interrupt mask: 0 Receive FIFO written to while + full condition interrupt is masked. 1 Receive FIFO written + to while full condition interrupt is not masked. */ + __IOM uint32_t RTIM : 1; /*!< Receive timeout interrupt mask: 0 Receive FIFO not empty and + no read prior to timeout period interrupt is masked. 1 + Receive FIFO not empty and no read prior to timeout period + interrupt is not masked. */ + __IOM uint32_t RXIM : 1; /*!< Receive FIFO interrupt mask: 0 Receive FIFO half full or less + condition interrupt is masked. 1 Receive FIFO half full + or less condition interrupt is not masked. */ + __IOM uint32_t TXIM : 1; /*!< Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or + less condition interrupt is masked. 1 Transmit FIFO half + empty or less condition interrupt is not masked. */ + uint32_t : 28; + } bit; + } SSPIMSC; + + union { + __IOM uint32_t reg; /*!< Raw interrupt status register, SSPRIS on page 3-10 */ + + struct { + __IM uint32_t RORRIS : 1; /*!< Gives the raw interrupt state, prior to masking, of the SSPRORINTR + interrupt */ + __IM uint32_t RTRIS : 1; /*!< Gives the raw interrupt state, prior to masking, of the SSPRTINTR + interrupt */ + __IM uint32_t RXRIS : 1; /*!< Gives the raw interrupt state, prior to masking, of the SSPRXINTR + interrupt */ + __IM uint32_t TXRIS : 1; /*!< Gives the raw interrupt state, prior to masking, of the SSPTXINTR + interrupt */ + uint32_t : 28; + } bit; + } SSPRIS; + + union { + __IOM uint32_t reg; /*!< Masked interrupt status register, SSPMIS on page 3-11 */ + + struct { + __IM uint32_t RORMIS : 1; /*!< Gives the receive over run masked interrupt status, after masking, + of the SSPRORINTR interrupt */ + __IM uint32_t RTMIS : 1; /*!< Gives the receive timeout masked interrupt state, after masking, + of the SSPRTINTR interrupt */ + __IM uint32_t RXMIS : 1; /*!< Gives the receive FIFO masked interrupt state, after masking, + of the SSPRXINTR interrupt */ + __IM uint32_t TXMIS : 1; /*!< Gives the transmit FIFO masked interrupt state, after masking, + of the SSPTXINTR interrupt */ + uint32_t : 28; + } bit; + } SSPMIS; + + union { + __IOM uint32_t reg; /*!< Interrupt clear register, SSPICR on page 3-11 */ + + struct { + __IOM uint32_t RORIC : 1; /*!< Clears the SSPRORINTR interrupt */ + __IOM uint32_t RTIC : 1; /*!< Clears the SSPRTINTR interrupt */ + uint32_t : 30; + } bit; + } SSPICR; + + union { + __IOM uint32_t reg; /*!< DMA control register, SSPDMACR on page 3-12 */ + + struct { + __IOM uint32_t RXDMAE : 1; /*!< Receive DMA Enable. If this bit is set to 1, DMA for the receive + FIFO is enabled. */ + __IOM uint32_t TXDMAE : 1; /*!< Transmit DMA Enable. If this bit is set to 1, DMA for the transmit + FIFO is enabled. */ + uint32_t : 30; + } bit; + } SSPDMACR; + __IM uint32_t RESERVED[1006]; + + union { + __IOM uint32_t reg; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + + struct { + __IM uint32_t PARTNUMBER0 : 8; /*!< These bits read back as 0x22 */ + uint32_t : 24; + } bit; + } SSPPERIPHID0; + + union { + __IOM uint32_t reg; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + + struct { + __IM uint32_t PARTNUMBER1 : 4; /*!< These bits read back as 0x0 */ + __IM uint32_t DESIGNER0 : 4; /*!< These bits read back as 0x1 */ + uint32_t : 24; + } bit; + } SSPPERIPHID1; + + union { + __IOM uint32_t reg; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + + struct { + __IM uint32_t DESIGNER1 : 4; /*!< These bits read back as 0x4 */ + __IM uint32_t REVISION : 4; /*!< These bits return the peripheral revision */ + uint32_t : 24; + } bit; + } SSPPERIPHID2; + + union { + __IOM uint32_t reg; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + + struct { + __IM uint32_t CONFIGURATION : 8; /*!< These bits read back as 0x00 */ + uint32_t : 24; + } bit; + } SSPPERIPHID3; + + union { + __IOM uint32_t reg; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + + struct { + __IM uint32_t SSPPCELLID0 : 8; /*!< These bits read back as 0x0D */ + uint32_t : 24; + } bit; + } SSPPCELLID0; + + union { + __IOM uint32_t reg; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + + struct { + __IM uint32_t SSPPCELLID1 : 8; /*!< These bits read back as 0xF0 */ + uint32_t : 24; + } bit; + } SSPPCELLID1; + + union { + __IOM uint32_t reg; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + + struct { + __IM uint32_t SSPPCELLID2 : 8; /*!< These bits read back as 0x05 */ + uint32_t : 24; + } bit; + } SSPPCELLID2; + + union { + __IOM uint32_t reg; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + + struct { + __IM uint32_t SSPPCELLID3 : 8; /*!< These bits read back as 0xB1 */ + uint32_t : 24; + } bit; + } SSPPCELLID3; +} SPI0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ PIO0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable IO block (PIO0) + */ + +typedef struct { /*!< PIO0 Structure */ + + union { + __IOM uint32_t reg; /*!< PIO control register */ + + struct { + __IOM uint32_t SM_ENABLE : 4; /*!< Enable/disable each of the four state machines by writing 1/0 + to each of these four bits. When disabled, a state machine + will cease executing instructions, except those written + directly to SMx_INSTR by the system. Multiple bits can + be set/cleared at once to run/halt multiple state machines + simultaneously. */ + __OM uint32_t SM_RESTART : 4; /*!< Write 1 to instantly clear internal SM state which may be otherwise + difficult to access and will affect future execution. Specifically, + the following are cleared: input and output shift counters; + the contents of the input shift register; the delay counter; + the waiting-on-IRQ state; any stalled instruction written + to SMx_INSTR or run by OUT/MOV EXEC; any pin write left + asserted due to OUT_STICKY. The contents of the output + shift register and the X/Y scratch registers are not affected. */ + __OM uint32_t CLKDIV_RESTART : 4; /*!< Restart a state machine's clock divider from an initial phase + of 0. Clock dividers are free-running, so once started, + their output (including fractional jitter) is completely + determined by the integer/fractional divisor configured + in SMx_CLKDIV. This means that, if multiple clock dividers + with the same divisor are restarted simultaneously, by + writing multiple 1 bits to this field, the execution clocks + of those state machines will run in precise lockstep. Note + that setting/clearing SM_ENABLE does not stop the clock + divider from running, so once multiple state machines' + clocks are synchronised, it is safe to disable/reenable + a state machine, whilst keeping the clock dividers in sync. + Note also that CLKDIV_RESTART can be written to whilst + the state machine is running, and this is useful to resynchronise + clock dividers after the divisors (SMx_CLKDIV) have been + changed on-the-fly. */ + uint32_t : 4; + __OM uint32_t PREV_PIO_MASK : 4; /*!< A mask of state machines in the neighbouring lower-numbered + PIO block in the system (or the highest-numbered PIO block + if this is PIO block 0) to which to apply the operations + specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in + the same write. This allows state machines in a neighbouring + PIO block to be started/stopped/clock-synced exactly simultaneously + with a write to this PIO block's CTRL register. Neighbouring + PIO blocks are disconnected (status signals tied to 0 and + control signals ignored) if one block is accessible to + NonSecure code, and one is not. */ + __OM uint32_t NEXT_PIO_MASK : 4; /*!< A mask of state machines in the neighbouring higher-numbered + PIO block in the system (or PIO block 0 if this is the + highest-numbered PIO block) to which to apply the operations + specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, + and NEXTPREV_SM_DISABLE in the same write. This allows + state machines in a neighbouring PIO block to be started/stopped/clock-sy + ced exactly simultaneously with a write to this PIO block's + CTRL register. Note that in a system with two PIOs, NEXT_PIO_MASK + and PREV_PIO_MASK actually indicate the same PIO block. + In this case the effects are applied cumulatively (as though + the masks were OR'd together). Neighbouring PIO blocks + are disconnected (status signals tied to 0 and control + signals ignored) if one block is accessible to NonSecure + code, and one is not. */ + __OM uint32_t NEXTPREV_SM_ENABLE : 1; /*!< Write 1 to enable state machines in neighbouring PIO blocks, + as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the + same write. This is equivalent to setting the corresponding + SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE + and OTHERS_SM_DISABLE are set, the disable takes precedence. */ + __OM uint32_t NEXTPREV_SM_DISABLE : 1; /*!< Write 1 to disable state machines in neighbouring PIO blocks, + as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the + same write. This is equivalent to clearing the corresponding + SM_ENABLE bits in those PIOs' CTRL registers. */ + __OM uint32_t NEXTPREV_CLKDIV_RESTART : 1;/*!< Write 1 to restart the clock dividers of state machines in neighbouring + PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK + in the same write. This is equivalent to writing 1 to the + corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. */ + uint32_t : 5; + } bit; + } CTRL; + + union { + __IOM uint32_t reg; /*!< FIFO status register */ + + struct { + __IM uint32_t RXFULL : 4; /*!< State machine RX FIFO is full */ + uint32_t : 4; + __IM uint32_t RXEMPTY : 4; /*!< State machine RX FIFO is empty */ + uint32_t : 4; + __IM uint32_t TXFULL : 4; /*!< State machine TX FIFO is full */ + uint32_t : 4; + __IM uint32_t TXEMPTY : 4; /*!< State machine TX FIFO is empty */ + uint32_t : 4; + } bit; + } FSTAT; + + union { + __IOM uint32_t reg; /*!< FIFO debug register */ + + struct { + __IOM uint32_t RXSTALL : 4; /*!< State machine has stalled on full RX FIFO during a blocking + PUSH, or an IN with autopush enabled. This flag is also + set when a nonblocking PUSH to a full FIFO took place, + in which case the state machine has dropped data. Write + 1 to clear. */ + uint32_t : 4; + __IOM uint32_t RXUNDER : 4; /*!< RX FIFO underflow (i.e. read-on-empty by the system) has occurred. + Write 1 to clear. Note that read-on-empty does not perturb + the state of the FIFO in any way, but the data returned + by reading from an empty FIFO is undefined, so this flag + generally only becomes set due to some kind of software + error. */ + uint32_t : 4; + __IOM uint32_t TXOVER : 4; /*!< TX FIFO overflow (i.e. write-on-full by the system) has occurred. + Write 1 to clear. Note that write-on-full does not alter + the state or contents of the FIFO in any way, but the data + that the system attempted to write is dropped, so if this + flag is set, your software has quite likely dropped some + data on the floor. */ + uint32_t : 4; + __IOM uint32_t TXSTALL : 4; /*!< State machine has stalled on empty TX FIFO during a blocking + PULL, or an OUT with autopull enabled. Write 1 to clear. */ + uint32_t : 4; + } bit; + } FDEBUG; + + union { + __IOM uint32_t reg; /*!< FIFO levels */ + + struct { + __IM uint32_t TX0 : 4; /*!< TX0 */ + __IM uint32_t RX0 : 4; /*!< RX0 */ + __IM uint32_t TX1 : 4; /*!< TX1 */ + __IM uint32_t RX1 : 4; /*!< RX1 */ + __IM uint32_t TX2 : 4; /*!< TX2 */ + __IM uint32_t RX2 : 4; /*!< RX2 */ + __IM uint32_t TX3 : 4; /*!< TX3 */ + __IM uint32_t RX3 : 4; /*!< RX3 */ + } bit; + } FLEVEL; + + union { + __IOM uint32_t reg; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + + struct { + __OM uint32_t TXF0 : 32; /*!< TXF0 */ + } bit; + } TXF0; + + union { + __IOM uint32_t reg; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + + struct { + __OM uint32_t TXF1 : 32; /*!< TXF1 */ + } bit; + } TXF1; + + union { + __IOM uint32_t reg; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + + struct { + __OM uint32_t TXF2 : 32; /*!< TXF2 */ + } bit; + } TXF2; + + union { + __IOM uint32_t reg; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + + struct { + __OM uint32_t TXF3 : 32; /*!< TXF3 */ + } bit; + } TXF3; + + union { + __IOM uint32_t reg; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + + struct { + __IM uint32_t RXF0 : 32; /*!< RXF0 */ + } bit; + } RXF0; + + union { + __IOM uint32_t reg; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + + struct { + __IM uint32_t RXF1 : 32; /*!< RXF1 */ + } bit; + } RXF1; + + union { + __IOM uint32_t reg; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + + struct { + __IM uint32_t RXF2 : 32; /*!< RXF2 */ + } bit; + } RXF2; + + union { + __IOM uint32_t reg; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + + struct { + __IM uint32_t RXF3 : 32; /*!< RXF3 */ + } bit; + } RXF3; + + union { + __IOM uint32_t reg; /*!< State machine IRQ flags register. Write 1 to clear. There are + eight state machine IRQ flags, which can be set, cleared, + and waited on by the state machines. There's no fixed association + between flags and state machines -- any state machine can + use any flag. Any of the eight flags can be used for timing + synchronisation between state machines, using IRQ and WAIT + instructions. Any combination of the eight flags can also + routed out to either of the two system-level interrupt + requests, alongside FIFO status interrupts -- see e.g. + IRQ0_INTE. */ + + struct { + __IOM uint32_t IRQ : 8; /*!< IRQ */ + uint32_t : 24; + } bit; + } IRQ; + + union { + __IOM uint32_t reg; /*!< Writing a 1 to each of these bits will forcibly assert the corresponding + IRQ. Note this is different to the INTF register: writing + here affects PIO internal state. INTF just asserts the + processor-facing IRQ signal for testing ISRs, and is not + visible to the state machines. */ + + struct { + __OM uint32_t IRQ_FORCE : 8; /*!< IRQ_FORCE */ + uint32_t : 24; + } bit; + } IRQ_FORCE; + + union { + __IOM uint32_t reg; /*!< There is a 2-flipflop synchronizer on each GPIO input, which + protects PIO logic from metastabilities. This increases + input delay, and for fast synchronous IO (e.g. SPI) these + synchronizers may need to be bypassed. Each bit in this + register corresponds to one GPIO. 0 -> input is synchronized + (default) 1 -> synchronizer is bypassed If in doubt, leave + this register as all zeroes. */ + + struct { + __IOM uint32_t INPUT_SYNC_BYPASS : 32; /*!< INPUT_SYNC_BYPASS */ + } bit; + } INPUT_SYNC_BYPASS; + + union { + __IOM uint32_t reg; /*!< Read to sample the pad output values PIO is currently driving + to the GPIOs. On RP2040 there are 30 GPIOs, so the two + most significant bits are hardwired to 0. */ + + struct { + __IM uint32_t DBG_PADOUT : 32; /*!< DBG_PADOUT */ + } bit; + } DBG_PADOUT; + + union { + __IOM uint32_t reg; /*!< Read to sample the pad output enables (direction) PIO is currently + driving to the GPIOs. On RP2040 there are 30 GPIOs, so + the two most significant bits are hardwired to 0. */ + + struct { + __IM uint32_t DBG_PADOE : 32; /*!< DBG_PADOE */ + } bit; + } DBG_PADOE; + + union { + __IOM uint32_t reg; /*!< The PIO hardware has some free parameters that may vary between + chip products. These should be provided in the chip datasheet, + but are also exposed here. */ + + struct { + __IM uint32_t FIFO_DEPTH : 6; /*!< The depth of the state machine TX/RX FIFOs, measured in words. + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + this depth. */ + uint32_t : 2; + __IM uint32_t SM_COUNT : 4; /*!< The number of state machines this PIO instance is equipped with. */ + uint32_t : 4; + __IM uint32_t IMEM_SIZE : 6; /*!< The size of the instruction memory, measured in units of one + instruction */ + uint32_t : 6; + __IM uint32_t VERSION : 4; /*!< Version of the core PIO hardware. */ + } bit; + } DBG_CFGINFO; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 0 */ + + struct { + __OM uint32_t INSTR_MEM0 : 16; /*!< INSTR_MEM0 */ + uint32_t : 16; + } bit; + } INSTR_MEM0; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 1 */ + + struct { + __OM uint32_t INSTR_MEM1 : 16; /*!< INSTR_MEM1 */ + uint32_t : 16; + } bit; + } INSTR_MEM1; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 2 */ + + struct { + __OM uint32_t INSTR_MEM2 : 16; /*!< INSTR_MEM2 */ + uint32_t : 16; + } bit; + } INSTR_MEM2; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 3 */ + + struct { + __OM uint32_t INSTR_MEM3 : 16; /*!< INSTR_MEM3 */ + uint32_t : 16; + } bit; + } INSTR_MEM3; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 4 */ + + struct { + __OM uint32_t INSTR_MEM4 : 16; /*!< INSTR_MEM4 */ + uint32_t : 16; + } bit; + } INSTR_MEM4; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 5 */ + + struct { + __OM uint32_t INSTR_MEM5 : 16; /*!< INSTR_MEM5 */ + uint32_t : 16; + } bit; + } INSTR_MEM5; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 6 */ + + struct { + __OM uint32_t INSTR_MEM6 : 16; /*!< INSTR_MEM6 */ + uint32_t : 16; + } bit; + } INSTR_MEM6; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 7 */ + + struct { + __OM uint32_t INSTR_MEM7 : 16; /*!< INSTR_MEM7 */ + uint32_t : 16; + } bit; + } INSTR_MEM7; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 8 */ + + struct { + __OM uint32_t INSTR_MEM8 : 16; /*!< INSTR_MEM8 */ + uint32_t : 16; + } bit; + } INSTR_MEM8; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 9 */ + + struct { + __OM uint32_t INSTR_MEM9 : 16; /*!< INSTR_MEM9 */ + uint32_t : 16; + } bit; + } INSTR_MEM9; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 10 */ + + struct { + __OM uint32_t INSTR_MEM10 : 16; /*!< INSTR_MEM10 */ + uint32_t : 16; + } bit; + } INSTR_MEM10; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 11 */ + + struct { + __OM uint32_t INSTR_MEM11 : 16; /*!< INSTR_MEM11 */ + uint32_t : 16; + } bit; + } INSTR_MEM11; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 12 */ + + struct { + __OM uint32_t INSTR_MEM12 : 16; /*!< INSTR_MEM12 */ + uint32_t : 16; + } bit; + } INSTR_MEM12; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 13 */ + + struct { + __OM uint32_t INSTR_MEM13 : 16; /*!< INSTR_MEM13 */ + uint32_t : 16; + } bit; + } INSTR_MEM13; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 14 */ + + struct { + __OM uint32_t INSTR_MEM14 : 16; /*!< INSTR_MEM14 */ + uint32_t : 16; + } bit; + } INSTR_MEM14; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 15 */ + + struct { + __OM uint32_t INSTR_MEM15 : 16; /*!< INSTR_MEM15 */ + uint32_t : 16; + } bit; + } INSTR_MEM15; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 16 */ + + struct { + __OM uint32_t INSTR_MEM16 : 16; /*!< INSTR_MEM16 */ + uint32_t : 16; + } bit; + } INSTR_MEM16; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 17 */ + + struct { + __OM uint32_t INSTR_MEM17 : 16; /*!< INSTR_MEM17 */ + uint32_t : 16; + } bit; + } INSTR_MEM17; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 18 */ + + struct { + __OM uint32_t INSTR_MEM18 : 16; /*!< INSTR_MEM18 */ + uint32_t : 16; + } bit; + } INSTR_MEM18; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 19 */ + + struct { + __OM uint32_t INSTR_MEM19 : 16; /*!< INSTR_MEM19 */ + uint32_t : 16; + } bit; + } INSTR_MEM19; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 20 */ + + struct { + __OM uint32_t INSTR_MEM20 : 16; /*!< INSTR_MEM20 */ + uint32_t : 16; + } bit; + } INSTR_MEM20; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 21 */ + + struct { + __OM uint32_t INSTR_MEM21 : 16; /*!< INSTR_MEM21 */ + uint32_t : 16; + } bit; + } INSTR_MEM21; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 22 */ + + struct { + __OM uint32_t INSTR_MEM22 : 16; /*!< INSTR_MEM22 */ + uint32_t : 16; + } bit; + } INSTR_MEM22; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 23 */ + + struct { + __OM uint32_t INSTR_MEM23 : 16; /*!< INSTR_MEM23 */ + uint32_t : 16; + } bit; + } INSTR_MEM23; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 24 */ + + struct { + __OM uint32_t INSTR_MEM24 : 16; /*!< INSTR_MEM24 */ + uint32_t : 16; + } bit; + } INSTR_MEM24; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 25 */ + + struct { + __OM uint32_t INSTR_MEM25 : 16; /*!< INSTR_MEM25 */ + uint32_t : 16; + } bit; + } INSTR_MEM25; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 26 */ + + struct { + __OM uint32_t INSTR_MEM26 : 16; /*!< INSTR_MEM26 */ + uint32_t : 16; + } bit; + } INSTR_MEM26; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 27 */ + + struct { + __OM uint32_t INSTR_MEM27 : 16; /*!< INSTR_MEM27 */ + uint32_t : 16; + } bit; + } INSTR_MEM27; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 28 */ + + struct { + __OM uint32_t INSTR_MEM28 : 16; /*!< INSTR_MEM28 */ + uint32_t : 16; + } bit; + } INSTR_MEM28; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 29 */ + + struct { + __OM uint32_t INSTR_MEM29 : 16; /*!< INSTR_MEM29 */ + uint32_t : 16; + } bit; + } INSTR_MEM29; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 30 */ + + struct { + __OM uint32_t INSTR_MEM30 : 16; /*!< INSTR_MEM30 */ + uint32_t : 16; + } bit; + } INSTR_MEM30; + + union { + __IOM uint32_t reg; /*!< Write-only access to instruction memory location 31 */ + + struct { + __OM uint32_t INSTR_MEM31 : 16; /*!< INSTR_MEM31 */ + uint32_t : 16; + } bit; + } INSTR_MEM31; + + union { + __IOM uint32_t reg; /*!< Clock divisor register for state machine 0 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + + struct { + uint32_t : 8; + __IOM uint32_t FRAC : 8; /*!< Fractional part of clock divisor */ + __IOM uint32_t INT : 16; /*!< Effective frequency is sysclk/(int + frac/256). Value of 0 is + interpreted as 65536. If INT is 0, FRAC must also be 0. */ + } bit; + } SM0_CLKDIV; + + union { + __IOM uint32_t reg; /*!< Execution/behavioural settings for state machine 0 */ + + struct { + __IOM uint32_t STATUS_N : 5; /*!< Comparison level or IRQ index for the MOV x, STATUS instruction. + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N + greater than the current FIFO depth are reserved, and have + undefined behaviour. */ + __IOM uint32_t STATUS_SEL : 2; /*!< Comparison used for the MOV x, STATUS instruction. */ + __IOM uint32_t WRAP_BOTTOM : 5; /*!< After reaching wrap_top, execution is wrapped to this address. */ + __IOM uint32_t WRAP_TOP : 5; /*!< After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is + true, the jump takes priority. */ + __IOM uint32_t OUT_STICKY : 1; /*!< Continuously assert the most recent OUT/SET to the pins */ + __IOM uint32_t INLINE_OUT_EN : 1; /*!< If 1, use a bit of OUT data as an auxiliary write enable When + used in conjunction with OUT_STICKY, writes with an enable + of 0 will deassert the latest pin write. This can create + useful masking/override behaviour due to the priority ordering + of state machine pin writes (SM0 < SM1 < ...) */ + __IOM uint32_t OUT_EN_SEL : 5; /*!< Which data bit to use for inline OUT enable */ + __IOM uint32_t JMP_PIN : 5; /*!< The GPIO number to use as condition for JMP PIN. Unaffected + by input mapping. */ + __IOM uint32_t SIDE_PINDIR : 1; /*!< If 1, side-set data is asserted to pin directions, instead of + pin values */ + __IOM uint32_t SIDE_EN : 1; /*!< If 1, the MSB of the Delay/Side-set instruction field is used + as side-set enable, rather than a side-set data bit. This + allows instructions to perform side-set optionally, rather + than on every instruction, but the maximum possible side-set + width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUN + is inclusive of this enable bit. */ + __IM uint32_t EXEC_STALLED : 1; /*!< If 1, an instruction written to SMx_INSTR is stalled, and latched + by the state machine. Will clear to 0 once this instruction + completes. */ + } bit; + } SM0_EXECCTRL; + + union { + __IOM uint32_t reg; /*!< Control behaviour of the input/output shift registers for state + machine 0 */ + + struct { + __IOM uint32_t IN_COUNT : 5; /*!< Set the number of pins which are not masked to 0 when read by + an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, + an IN_COUNT of 5 means that the 5 LSBs of the IN pin group + are visible (bits 4:0), but the remaining 27 MSBs are masked + to 0. A count of 32 is encoded with a field value of 0, + so the default behaviour is to not perform any masking. + Note this masking is applied in addition to the masking + usually performed by the IN instruction. This is mainly + useful for the MOV x, PINS instruction, which otherwise + has no way of masking pins. */ + uint32_t : 9; + __IOM uint32_t FJOIN_RX_GET : 1; /*!< If 1, disable this state machine's RX FIFO, make its storage + available for random read access by the state machine (using + the `get` instruction) and, unless FJOIN_RX_PUT is also + set, random write access by the processor (through the + RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET + are both set, then the RX FIFO's registers can be randomly + read/written by the state machine, but are completely inaccessible + to the processor. Setting this bit will clear the FJOIN_TX + and FJOIN_RX bits. */ + __IOM uint32_t FJOIN_RX_PUT : 1; /*!< If 1, disable this state machine's RX FIFO, make its storage + available for random write access by the state machine + (using the `put` instruction) and, unless FJOIN_RX_GET + is also set, random read access by the processor (through + the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET + are both set, then the RX FIFO's registers can be randomly + read/written by the state machine, but are completely inaccessible + to the processor. Setting this bit will clear the FJOIN_TX + and FJOIN_RX bits. */ + __IOM uint32_t AUTOPUSH : 1; /*!< Push automatically when the input shift register is filled, + i.e. on an IN instruction which causes the input shift + counter to reach or exceed PUSH_THRESH. */ + __IOM uint32_t AUTOPULL : 1; /*!< Pull automatically when the output shift register is emptied, + i.e. on or following an OUT instruction which causes the + output shift counter to reach or exceed PULL_THRESH. */ + __IOM uint32_t IN_SHIFTDIR : 1; /*!< 1 = shift input shift register to right (data enters from left). + 0 = to left. */ + __IOM uint32_t OUT_SHIFTDIR : 1; /*!< 1 = shift out of output shift register to right. 0 = to left. */ + __IOM uint32_t PUSH_THRESH : 5; /*!< Number of bits shifted into ISR before autopush, or conditional + push (PUSH IFFULL), will take place. Write 0 for value + of 32. */ + __IOM uint32_t PULL_THRESH : 5; /*!< Number of bits shifted out of OSR before autopull, or conditional + pull (PULL IFEMPTY), will take place. Write 0 for value + of 32. */ + __IOM uint32_t FJOIN_TX : 1; /*!< When 1, TX FIFO steals the RX FIFO's storage, and becomes twice + as deep. RX FIFO is disabled as a result (always reads + as both full and empty). FIFOs are flushed when this bit + is changed. */ + __IOM uint32_t FJOIN_RX : 1; /*!< When 1, RX FIFO steals the TX FIFO's storage, and becomes twice + as deep. TX FIFO is disabled as a result (always reads + as both full and empty). FIFOs are flushed when this bit + is changed. */ + } bit; + } SM0_SHIFTCTRL; + + union { + __IOM uint32_t reg; /*!< Current instruction address of state machine 0 */ + + struct { + __IM uint32_t SM0_ADDR : 5; /*!< SM0_ADDR */ + uint32_t : 27; + } bit; + } SM0_ADDR; + + union { + __IOM uint32_t reg; /*!< Read to see the instruction currently addressed by state machine + 0's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + + struct { + __IOM uint32_t SM0_INSTR : 16; /*!< SM0_INSTR */ + uint32_t : 16; + } bit; + } SM0_INSTR; + + union { + __IOM uint32_t reg; /*!< State machine pin control */ + + struct { + __IOM uint32_t OUT_BASE : 5; /*!< The lowest-numbered pin that will be affected by an OUT PINS, + OUT PINDIRS or MOV PINS instruction. The data written to + this pin will always be the least-significant bit of the + OUT or MOV data. */ + __IOM uint32_t SET_BASE : 5; /*!< The lowest-numbered pin that will be affected by a SET PINS + or SET PINDIRS instruction. The data written to this pin + is the least-significant bit of the SET data. */ + __IOM uint32_t SIDESET_BASE : 5; /*!< The lowest-numbered pin that will be affected by a side-set + operation. The MSBs of an instruction's side-set/delay + field (up to 5, determined by SIDESET_COUNT) are used for + side-set data, with the remaining LSBs used for delay. + The least-significant bit of the side-set portion is the + bit written to this pin, with more-significant bits written + to higher-numbered pins. */ + __IOM uint32_t IN_BASE : 5; /*!< The pin which is mapped to the least-significant bit of a state + machine's IN data bus. Higher-numbered pins are mapped + to consecutively more-significant data bits, with a modulo + of 32 applied to pin number. */ + __IOM uint32_t OUT_COUNT : 6; /*!< The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV + PINS instruction. In the range 0 to 32 inclusive. */ + __IOM uint32_t SET_COUNT : 3; /*!< The number of pins asserted by a SET. In the range 0 to 5 inclusive. */ + __IOM uint32_t SIDESET_COUNT : 3; /*!< The number of MSBs of the Delay/Side-set instruction field which + are used for side-set. Inclusive of the enable bit, if + present. Minimum of 0 (all delay bits, no side-set) and + maximum of 5 (all side-set, no delay). */ + } bit; + } SM0_PINCTRL; + + union { + __IOM uint32_t reg; /*!< Clock divisor register for state machine 1 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + + struct { + uint32_t : 8; + __IOM uint32_t FRAC : 8; /*!< Fractional part of clock divisor */ + __IOM uint32_t INT : 16; /*!< Effective frequency is sysclk/(int + frac/256). Value of 0 is + interpreted as 65536. If INT is 0, FRAC must also be 0. */ + } bit; + } SM1_CLKDIV; + + union { + __IOM uint32_t reg; /*!< Execution/behavioural settings for state machine 1 */ + + struct { + __IOM uint32_t STATUS_N : 5; /*!< Comparison level or IRQ index for the MOV x, STATUS instruction. + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N + greater than the current FIFO depth are reserved, and have + undefined behaviour. */ + __IOM uint32_t STATUS_SEL : 2; /*!< Comparison used for the MOV x, STATUS instruction. */ + __IOM uint32_t WRAP_BOTTOM : 5; /*!< After reaching wrap_top, execution is wrapped to this address. */ + __IOM uint32_t WRAP_TOP : 5; /*!< After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is + true, the jump takes priority. */ + __IOM uint32_t OUT_STICKY : 1; /*!< Continuously assert the most recent OUT/SET to the pins */ + __IOM uint32_t INLINE_OUT_EN : 1; /*!< If 1, use a bit of OUT data as an auxiliary write enable When + used in conjunction with OUT_STICKY, writes with an enable + of 0 will deassert the latest pin write. This can create + useful masking/override behaviour due to the priority ordering + of state machine pin writes (SM0 < SM1 < ...) */ + __IOM uint32_t OUT_EN_SEL : 5; /*!< Which data bit to use for inline OUT enable */ + __IOM uint32_t JMP_PIN : 5; /*!< The GPIO number to use as condition for JMP PIN. Unaffected + by input mapping. */ + __IOM uint32_t SIDE_PINDIR : 1; /*!< If 1, side-set data is asserted to pin directions, instead of + pin values */ + __IOM uint32_t SIDE_EN : 1; /*!< If 1, the MSB of the Delay/Side-set instruction field is used + as side-set enable, rather than a side-set data bit. This + allows instructions to perform side-set optionally, rather + than on every instruction, but the maximum possible side-set + width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUN + is inclusive of this enable bit. */ + __IM uint32_t EXEC_STALLED : 1; /*!< If 1, an instruction written to SMx_INSTR is stalled, and latched + by the state machine. Will clear to 0 once this instruction + completes. */ + } bit; + } SM1_EXECCTRL; + + union { + __IOM uint32_t reg; /*!< Control behaviour of the input/output shift registers for state + machine 1 */ + + struct { + __IOM uint32_t IN_COUNT : 5; /*!< Set the number of pins which are not masked to 0 when read by + an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, + an IN_COUNT of 5 means that the 5 LSBs of the IN pin group + are visible (bits 4:0), but the remaining 27 MSBs are masked + to 0. A count of 32 is encoded with a field value of 0, + so the default behaviour is to not perform any masking. + Note this masking is applied in addition to the masking + usually performed by the IN instruction. This is mainly + useful for the MOV x, PINS instruction, which otherwise + has no way of masking pins. */ + uint32_t : 9; + __IOM uint32_t FJOIN_RX_GET : 1; /*!< If 1, disable this state machine's RX FIFO, make its storage + available for random read access by the state machine (using + the `get` instruction) and, unless FJOIN_RX_PUT is also + set, random write access by the processor (through the + RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET + are both set, then the RX FIFO's registers can be randomly + read/written by the state machine, but are completely inaccessible + to the processor. Setting this bit will clear the FJOIN_TX + and FJOIN_RX bits. */ + __IOM uint32_t FJOIN_RX_PUT : 1; /*!< If 1, disable this state machine's RX FIFO, make its storage + available for random write access by the state machine + (using the `put` instruction) and, unless FJOIN_RX_GET + is also set, random read access by the processor (through + the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET + are both set, then the RX FIFO's registers can be randomly + read/written by the state machine, but are completely inaccessible + to the processor. Setting this bit will clear the FJOIN_TX + and FJOIN_RX bits. */ + __IOM uint32_t AUTOPUSH : 1; /*!< Push automatically when the input shift register is filled, + i.e. on an IN instruction which causes the input shift + counter to reach or exceed PUSH_THRESH. */ + __IOM uint32_t AUTOPULL : 1; /*!< Pull automatically when the output shift register is emptied, + i.e. on or following an OUT instruction which causes the + output shift counter to reach or exceed PULL_THRESH. */ + __IOM uint32_t IN_SHIFTDIR : 1; /*!< 1 = shift input shift register to right (data enters from left). + 0 = to left. */ + __IOM uint32_t OUT_SHIFTDIR : 1; /*!< 1 = shift out of output shift register to right. 0 = to left. */ + __IOM uint32_t PUSH_THRESH : 5; /*!< Number of bits shifted into ISR before autopush, or conditional + push (PUSH IFFULL), will take place. Write 0 for value + of 32. */ + __IOM uint32_t PULL_THRESH : 5; /*!< Number of bits shifted out of OSR before autopull, or conditional + pull (PULL IFEMPTY), will take place. Write 0 for value + of 32. */ + __IOM uint32_t FJOIN_TX : 1; /*!< When 1, TX FIFO steals the RX FIFO's storage, and becomes twice + as deep. RX FIFO is disabled as a result (always reads + as both full and empty). FIFOs are flushed when this bit + is changed. */ + __IOM uint32_t FJOIN_RX : 1; /*!< When 1, RX FIFO steals the TX FIFO's storage, and becomes twice + as deep. TX FIFO is disabled as a result (always reads + as both full and empty). FIFOs are flushed when this bit + is changed. */ + } bit; + } SM1_SHIFTCTRL; + + union { + __IOM uint32_t reg; /*!< Current instruction address of state machine 1 */ + + struct { + __IM uint32_t SM1_ADDR : 5; /*!< SM1_ADDR */ + uint32_t : 27; + } bit; + } SM1_ADDR; + + union { + __IOM uint32_t reg; /*!< Read to see the instruction currently addressed by state machine + 1's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + + struct { + __IOM uint32_t SM1_INSTR : 16; /*!< SM1_INSTR */ + uint32_t : 16; + } bit; + } SM1_INSTR; + + union { + __IOM uint32_t reg; /*!< State machine pin control */ + + struct { + __IOM uint32_t OUT_BASE : 5; /*!< The lowest-numbered pin that will be affected by an OUT PINS, + OUT PINDIRS or MOV PINS instruction. The data written to + this pin will always be the least-significant bit of the + OUT or MOV data. */ + __IOM uint32_t SET_BASE : 5; /*!< The lowest-numbered pin that will be affected by a SET PINS + or SET PINDIRS instruction. The data written to this pin + is the least-significant bit of the SET data. */ + __IOM uint32_t SIDESET_BASE : 5; /*!< The lowest-numbered pin that will be affected by a side-set + operation. The MSBs of an instruction's side-set/delay + field (up to 5, determined by SIDESET_COUNT) are used for + side-set data, with the remaining LSBs used for delay. + The least-significant bit of the side-set portion is the + bit written to this pin, with more-significant bits written + to higher-numbered pins. */ + __IOM uint32_t IN_BASE : 5; /*!< The pin which is mapped to the least-significant bit of a state + machine's IN data bus. Higher-numbered pins are mapped + to consecutively more-significant data bits, with a modulo + of 32 applied to pin number. */ + __IOM uint32_t OUT_COUNT : 6; /*!< The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV + PINS instruction. In the range 0 to 32 inclusive. */ + __IOM uint32_t SET_COUNT : 3; /*!< The number of pins asserted by a SET. In the range 0 to 5 inclusive. */ + __IOM uint32_t SIDESET_COUNT : 3; /*!< The number of MSBs of the Delay/Side-set instruction field which + are used for side-set. Inclusive of the enable bit, if + present. Minimum of 0 (all delay bits, no side-set) and + maximum of 5 (all side-set, no delay). */ + } bit; + } SM1_PINCTRL; + + union { + __IOM uint32_t reg; /*!< Clock divisor register for state machine 2 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + + struct { + uint32_t : 8; + __IOM uint32_t FRAC : 8; /*!< Fractional part of clock divisor */ + __IOM uint32_t INT : 16; /*!< Effective frequency is sysclk/(int + frac/256). Value of 0 is + interpreted as 65536. If INT is 0, FRAC must also be 0. */ + } bit; + } SM2_CLKDIV; + + union { + __IOM uint32_t reg; /*!< Execution/behavioural settings for state machine 2 */ + + struct { + __IOM uint32_t STATUS_N : 5; /*!< Comparison level or IRQ index for the MOV x, STATUS instruction. + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N + greater than the current FIFO depth are reserved, and have + undefined behaviour. */ + __IOM uint32_t STATUS_SEL : 2; /*!< Comparison used for the MOV x, STATUS instruction. */ + __IOM uint32_t WRAP_BOTTOM : 5; /*!< After reaching wrap_top, execution is wrapped to this address. */ + __IOM uint32_t WRAP_TOP : 5; /*!< After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is + true, the jump takes priority. */ + __IOM uint32_t OUT_STICKY : 1; /*!< Continuously assert the most recent OUT/SET to the pins */ + __IOM uint32_t INLINE_OUT_EN : 1; /*!< If 1, use a bit of OUT data as an auxiliary write enable When + used in conjunction with OUT_STICKY, writes with an enable + of 0 will deassert the latest pin write. This can create + useful masking/override behaviour due to the priority ordering + of state machine pin writes (SM0 < SM1 < ...) */ + __IOM uint32_t OUT_EN_SEL : 5; /*!< Which data bit to use for inline OUT enable */ + __IOM uint32_t JMP_PIN : 5; /*!< The GPIO number to use as condition for JMP PIN. Unaffected + by input mapping. */ + __IOM uint32_t SIDE_PINDIR : 1; /*!< If 1, side-set data is asserted to pin directions, instead of + pin values */ + __IOM uint32_t SIDE_EN : 1; /*!< If 1, the MSB of the Delay/Side-set instruction field is used + as side-set enable, rather than a side-set data bit. This + allows instructions to perform side-set optionally, rather + than on every instruction, but the maximum possible side-set + width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUN + is inclusive of this enable bit. */ + __IM uint32_t EXEC_STALLED : 1; /*!< If 1, an instruction written to SMx_INSTR is stalled, and latched + by the state machine. Will clear to 0 once this instruction + completes. */ + } bit; + } SM2_EXECCTRL; + + union { + __IOM uint32_t reg; /*!< Control behaviour of the input/output shift registers for state + machine 2 */ + + struct { + __IOM uint32_t IN_COUNT : 5; /*!< Set the number of pins which are not masked to 0 when read by + an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, + an IN_COUNT of 5 means that the 5 LSBs of the IN pin group + are visible (bits 4:0), but the remaining 27 MSBs are masked + to 0. A count of 32 is encoded with a field value of 0, + so the default behaviour is to not perform any masking. + Note this masking is applied in addition to the masking + usually performed by the IN instruction. This is mainly + useful for the MOV x, PINS instruction, which otherwise + has no way of masking pins. */ + uint32_t : 9; + __IOM uint32_t FJOIN_RX_GET : 1; /*!< If 1, disable this state machine's RX FIFO, make its storage + available for random read access by the state machine (using + the `get` instruction) and, unless FJOIN_RX_PUT is also + set, random write access by the processor (through the + RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET + are both set, then the RX FIFO's registers can be randomly + read/written by the state machine, but are completely inaccessible + to the processor. Setting this bit will clear the FJOIN_TX + and FJOIN_RX bits. */ + __IOM uint32_t FJOIN_RX_PUT : 1; /*!< If 1, disable this state machine's RX FIFO, make its storage + available for random write access by the state machine + (using the `put` instruction) and, unless FJOIN_RX_GET + is also set, random read access by the processor (through + the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET + are both set, then the RX FIFO's registers can be randomly + read/written by the state machine, but are completely inaccessible + to the processor. Setting this bit will clear the FJOIN_TX + and FJOIN_RX bits. */ + __IOM uint32_t AUTOPUSH : 1; /*!< Push automatically when the input shift register is filled, + i.e. on an IN instruction which causes the input shift + counter to reach or exceed PUSH_THRESH. */ + __IOM uint32_t AUTOPULL : 1; /*!< Pull automatically when the output shift register is emptied, + i.e. on or following an OUT instruction which causes the + output shift counter to reach or exceed PULL_THRESH. */ + __IOM uint32_t IN_SHIFTDIR : 1; /*!< 1 = shift input shift register to right (data enters from left). + 0 = to left. */ + __IOM uint32_t OUT_SHIFTDIR : 1; /*!< 1 = shift out of output shift register to right. 0 = to left. */ + __IOM uint32_t PUSH_THRESH : 5; /*!< Number of bits shifted into ISR before autopush, or conditional + push (PUSH IFFULL), will take place. Write 0 for value + of 32. */ + __IOM uint32_t PULL_THRESH : 5; /*!< Number of bits shifted out of OSR before autopull, or conditional + pull (PULL IFEMPTY), will take place. Write 0 for value + of 32. */ + __IOM uint32_t FJOIN_TX : 1; /*!< When 1, TX FIFO steals the RX FIFO's storage, and becomes twice + as deep. RX FIFO is disabled as a result (always reads + as both full and empty). FIFOs are flushed when this bit + is changed. */ + __IOM uint32_t FJOIN_RX : 1; /*!< When 1, RX FIFO steals the TX FIFO's storage, and becomes twice + as deep. TX FIFO is disabled as a result (always reads + as both full and empty). FIFOs are flushed when this bit + is changed. */ + } bit; + } SM2_SHIFTCTRL; + + union { + __IOM uint32_t reg; /*!< Current instruction address of state machine 2 */ + + struct { + __IM uint32_t SM2_ADDR : 5; /*!< SM2_ADDR */ + uint32_t : 27; + } bit; + } SM2_ADDR; + + union { + __IOM uint32_t reg; /*!< Read to see the instruction currently addressed by state machine + 2's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + + struct { + __IOM uint32_t SM2_INSTR : 16; /*!< SM2_INSTR */ + uint32_t : 16; + } bit; + } SM2_INSTR; + + union { + __IOM uint32_t reg; /*!< State machine pin control */ + + struct { + __IOM uint32_t OUT_BASE : 5; /*!< The lowest-numbered pin that will be affected by an OUT PINS, + OUT PINDIRS or MOV PINS instruction. The data written to + this pin will always be the least-significant bit of the + OUT or MOV data. */ + __IOM uint32_t SET_BASE : 5; /*!< The lowest-numbered pin that will be affected by a SET PINS + or SET PINDIRS instruction. The data written to this pin + is the least-significant bit of the SET data. */ + __IOM uint32_t SIDESET_BASE : 5; /*!< The lowest-numbered pin that will be affected by a side-set + operation. The MSBs of an instruction's side-set/delay + field (up to 5, determined by SIDESET_COUNT) are used for + side-set data, with the remaining LSBs used for delay. + The least-significant bit of the side-set portion is the + bit written to this pin, with more-significant bits written + to higher-numbered pins. */ + __IOM uint32_t IN_BASE : 5; /*!< The pin which is mapped to the least-significant bit of a state + machine's IN data bus. Higher-numbered pins are mapped + to consecutively more-significant data bits, with a modulo + of 32 applied to pin number. */ + __IOM uint32_t OUT_COUNT : 6; /*!< The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV + PINS instruction. In the range 0 to 32 inclusive. */ + __IOM uint32_t SET_COUNT : 3; /*!< The number of pins asserted by a SET. In the range 0 to 5 inclusive. */ + __IOM uint32_t SIDESET_COUNT : 3; /*!< The number of MSBs of the Delay/Side-set instruction field which + are used for side-set. Inclusive of the enable bit, if + present. Minimum of 0 (all delay bits, no side-set) and + maximum of 5 (all side-set, no delay). */ + } bit; + } SM2_PINCTRL; + + union { + __IOM uint32_t reg; /*!< Clock divisor register for state machine 3 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + + struct { + uint32_t : 8; + __IOM uint32_t FRAC : 8; /*!< Fractional part of clock divisor */ + __IOM uint32_t INT : 16; /*!< Effective frequency is sysclk/(int + frac/256). Value of 0 is + interpreted as 65536. If INT is 0, FRAC must also be 0. */ + } bit; + } SM3_CLKDIV; + + union { + __IOM uint32_t reg; /*!< Execution/behavioural settings for state machine 3 */ + + struct { + __IOM uint32_t STATUS_N : 5; /*!< Comparison level or IRQ index for the MOV x, STATUS instruction. + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N + greater than the current FIFO depth are reserved, and have + undefined behaviour. */ + __IOM uint32_t STATUS_SEL : 2; /*!< Comparison used for the MOV x, STATUS instruction. */ + __IOM uint32_t WRAP_BOTTOM : 5; /*!< After reaching wrap_top, execution is wrapped to this address. */ + __IOM uint32_t WRAP_TOP : 5; /*!< After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is + true, the jump takes priority. */ + __IOM uint32_t OUT_STICKY : 1; /*!< Continuously assert the most recent OUT/SET to the pins */ + __IOM uint32_t INLINE_OUT_EN : 1; /*!< If 1, use a bit of OUT data as an auxiliary write enable When + used in conjunction with OUT_STICKY, writes with an enable + of 0 will deassert the latest pin write. This can create + useful masking/override behaviour due to the priority ordering + of state machine pin writes (SM0 < SM1 < ...) */ + __IOM uint32_t OUT_EN_SEL : 5; /*!< Which data bit to use for inline OUT enable */ + __IOM uint32_t JMP_PIN : 5; /*!< The GPIO number to use as condition for JMP PIN. Unaffected + by input mapping. */ + __IOM uint32_t SIDE_PINDIR : 1; /*!< If 1, side-set data is asserted to pin directions, instead of + pin values */ + __IOM uint32_t SIDE_EN : 1; /*!< If 1, the MSB of the Delay/Side-set instruction field is used + as side-set enable, rather than a side-set data bit. This + allows instructions to perform side-set optionally, rather + than on every instruction, but the maximum possible side-set + width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUN + is inclusive of this enable bit. */ + __IM uint32_t EXEC_STALLED : 1; /*!< If 1, an instruction written to SMx_INSTR is stalled, and latched + by the state machine. Will clear to 0 once this instruction + completes. */ + } bit; + } SM3_EXECCTRL; + + union { + __IOM uint32_t reg; /*!< Control behaviour of the input/output shift registers for state + machine 3 */ + + struct { + __IOM uint32_t IN_COUNT : 5; /*!< Set the number of pins which are not masked to 0 when read by + an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, + an IN_COUNT of 5 means that the 5 LSBs of the IN pin group + are visible (bits 4:0), but the remaining 27 MSBs are masked + to 0. A count of 32 is encoded with a field value of 0, + so the default behaviour is to not perform any masking. + Note this masking is applied in addition to the masking + usually performed by the IN instruction. This is mainly + useful for the MOV x, PINS instruction, which otherwise + has no way of masking pins. */ + uint32_t : 9; + __IOM uint32_t FJOIN_RX_GET : 1; /*!< If 1, disable this state machine's RX FIFO, make its storage + available for random read access by the state machine (using + the `get` instruction) and, unless FJOIN_RX_PUT is also + set, random write access by the processor (through the + RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET + are both set, then the RX FIFO's registers can be randomly + read/written by the state machine, but are completely inaccessible + to the processor. Setting this bit will clear the FJOIN_TX + and FJOIN_RX bits. */ + __IOM uint32_t FJOIN_RX_PUT : 1; /*!< If 1, disable this state machine's RX FIFO, make its storage + available for random write access by the state machine + (using the `put` instruction) and, unless FJOIN_RX_GET + is also set, random read access by the processor (through + the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET + are both set, then the RX FIFO's registers can be randomly + read/written by the state machine, but are completely inaccessible + to the processor. Setting this bit will clear the FJOIN_TX + and FJOIN_RX bits. */ + __IOM uint32_t AUTOPUSH : 1; /*!< Push automatically when the input shift register is filled, + i.e. on an IN instruction which causes the input shift + counter to reach or exceed PUSH_THRESH. */ + __IOM uint32_t AUTOPULL : 1; /*!< Pull automatically when the output shift register is emptied, + i.e. on or following an OUT instruction which causes the + output shift counter to reach or exceed PULL_THRESH. */ + __IOM uint32_t IN_SHIFTDIR : 1; /*!< 1 = shift input shift register to right (data enters from left). + 0 = to left. */ + __IOM uint32_t OUT_SHIFTDIR : 1; /*!< 1 = shift out of output shift register to right. 0 = to left. */ + __IOM uint32_t PUSH_THRESH : 5; /*!< Number of bits shifted into ISR before autopush, or conditional + push (PUSH IFFULL), will take place. Write 0 for value + of 32. */ + __IOM uint32_t PULL_THRESH : 5; /*!< Number of bits shifted out of OSR before autopull, or conditional + pull (PULL IFEMPTY), will take place. Write 0 for value + of 32. */ + __IOM uint32_t FJOIN_TX : 1; /*!< When 1, TX FIFO steals the RX FIFO's storage, and becomes twice + as deep. RX FIFO is disabled as a result (always reads + as both full and empty). FIFOs are flushed when this bit + is changed. */ + __IOM uint32_t FJOIN_RX : 1; /*!< When 1, RX FIFO steals the TX FIFO's storage, and becomes twice + as deep. TX FIFO is disabled as a result (always reads + as both full and empty). FIFOs are flushed when this bit + is changed. */ + } bit; + } SM3_SHIFTCTRL; + + union { + __IOM uint32_t reg; /*!< Current instruction address of state machine 3 */ + + struct { + __IM uint32_t SM3_ADDR : 5; /*!< SM3_ADDR */ + uint32_t : 27; + } bit; + } SM3_ADDR; + + union { + __IOM uint32_t reg; /*!< Read to see the instruction currently addressed by state machine + 3's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + + struct { + __IOM uint32_t SM3_INSTR : 16; /*!< SM3_INSTR */ + uint32_t : 16; + } bit; + } SM3_INSTR; + + union { + __IOM uint32_t reg; /*!< State machine pin control */ + + struct { + __IOM uint32_t OUT_BASE : 5; /*!< The lowest-numbered pin that will be affected by an OUT PINS, + OUT PINDIRS or MOV PINS instruction. The data written to + this pin will always be the least-significant bit of the + OUT or MOV data. */ + __IOM uint32_t SET_BASE : 5; /*!< The lowest-numbered pin that will be affected by a SET PINS + or SET PINDIRS instruction. The data written to this pin + is the least-significant bit of the SET data. */ + __IOM uint32_t SIDESET_BASE : 5; /*!< The lowest-numbered pin that will be affected by a side-set + operation. The MSBs of an instruction's side-set/delay + field (up to 5, determined by SIDESET_COUNT) are used for + side-set data, with the remaining LSBs used for delay. + The least-significant bit of the side-set portion is the + bit written to this pin, with more-significant bits written + to higher-numbered pins. */ + __IOM uint32_t IN_BASE : 5; /*!< The pin which is mapped to the least-significant bit of a state + machine's IN data bus. Higher-numbered pins are mapped + to consecutively more-significant data bits, with a modulo + of 32 applied to pin number. */ + __IOM uint32_t OUT_COUNT : 6; /*!< The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV + PINS instruction. In the range 0 to 32 inclusive. */ + __IOM uint32_t SET_COUNT : 3; /*!< The number of pins asserted by a SET. In the range 0 to 5 inclusive. */ + __IOM uint32_t SIDESET_COUNT : 3; /*!< The number of MSBs of the Delay/Side-set instruction field which + are used for side-set. Inclusive of the enable bit, if + present. Minimum of 0 (all delay bits, no side-set) and + maximum of 5 (all side-set, no delay). */ + } bit; + } SM3_PINCTRL; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF0_PUTGET0 : 32; /*!< RXF0_PUTGET0 */ + } bit; + } RXF0_PUTGET0; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF0_PUTGET1 : 32; /*!< RXF0_PUTGET1 */ + } bit; + } RXF0_PUTGET1; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF0_PUTGET2 : 32; /*!< RXF0_PUTGET2 */ + } bit; + } RXF0_PUTGET2; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF0_PUTGET3 : 32; /*!< RXF0_PUTGET3 */ + } bit; + } RXF0_PUTGET3; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF1_PUTGET0 : 32; /*!< RXF1_PUTGET0 */ + } bit; + } RXF1_PUTGET0; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF1_PUTGET1 : 32; /*!< RXF1_PUTGET1 */ + } bit; + } RXF1_PUTGET1; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF1_PUTGET2 : 32; /*!< RXF1_PUTGET2 */ + } bit; + } RXF1_PUTGET2; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF1_PUTGET3 : 32; /*!< RXF1_PUTGET3 */ + } bit; + } RXF1_PUTGET3; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF2_PUTGET0 : 32; /*!< RXF2_PUTGET0 */ + } bit; + } RXF2_PUTGET0; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF2_PUTGET1 : 32; /*!< RXF2_PUTGET1 */ + } bit; + } RXF2_PUTGET1; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF2_PUTGET2 : 32; /*!< RXF2_PUTGET2 */ + } bit; + } RXF2_PUTGET2; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF2_PUTGET3 : 32; /*!< RXF2_PUTGET3 */ + } bit; + } RXF2_PUTGET3; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF3_PUTGET0 : 32; /*!< RXF3_PUTGET0 */ + } bit; + } RXF3_PUTGET0; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF3_PUTGET1 : 32; /*!< RXF3_PUTGET1 */ + } bit; + } RXF3_PUTGET1; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF3_PUTGET2 : 32; /*!< RXF3_PUTGET2 */ + } bit; + } RXF3_PUTGET2; + + union { + __IOM uint32_t reg; /*!< Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + + struct { + __IOM uint32_t RXF3_PUTGET3 : 32; /*!< RXF3_PUTGET3 */ + } bit; + } RXF3_PUTGET3; + + union { + __IOM uint32_t reg; /*!< Relocate GPIO 0 (from PIO's point of view) in the system GPIO + numbering, to access more than 32 GPIOs from PIO. Only + the values 0 and 16 are supported (only bit 4 is writable). */ + + struct { + uint32_t : 4; + __IOM uint32_t GPIOBASE : 1; /*!< GPIOBASE */ + uint32_t : 27; + } bit; + } GPIOBASE; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t SM0_RXNEMPTY : 1; /*!< SM0_RXNEMPTY */ + __IM uint32_t SM1_RXNEMPTY : 1; /*!< SM1_RXNEMPTY */ + __IM uint32_t SM2_RXNEMPTY : 1; /*!< SM2_RXNEMPTY */ + __IM uint32_t SM3_RXNEMPTY : 1; /*!< SM3_RXNEMPTY */ + __IM uint32_t SM0_TXNFULL : 1; /*!< SM0_TXNFULL */ + __IM uint32_t SM1_TXNFULL : 1; /*!< SM1_TXNFULL */ + __IM uint32_t SM2_TXNFULL : 1; /*!< SM2_TXNFULL */ + __IM uint32_t SM3_TXNFULL : 1; /*!< SM3_TXNFULL */ + __IM uint32_t SM0 : 1; /*!< SM0 */ + __IM uint32_t SM1 : 1; /*!< SM1 */ + __IM uint32_t SM2 : 1; /*!< SM2 */ + __IM uint32_t SM3 : 1; /*!< SM3 */ + __IM uint32_t SM4 : 1; /*!< SM4 */ + __IM uint32_t SM5 : 1; /*!< SM5 */ + __IM uint32_t SM6 : 1; /*!< SM6 */ + __IM uint32_t SM7 : 1; /*!< SM7 */ + uint32_t : 16; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for irq0 */ + + struct { + __IOM uint32_t SM0_RXNEMPTY : 1; /*!< SM0_RXNEMPTY */ + __IOM uint32_t SM1_RXNEMPTY : 1; /*!< SM1_RXNEMPTY */ + __IOM uint32_t SM2_RXNEMPTY : 1; /*!< SM2_RXNEMPTY */ + __IOM uint32_t SM3_RXNEMPTY : 1; /*!< SM3_RXNEMPTY */ + __IOM uint32_t SM0_TXNFULL : 1; /*!< SM0_TXNFULL */ + __IOM uint32_t SM1_TXNFULL : 1; /*!< SM1_TXNFULL */ + __IOM uint32_t SM2_TXNFULL : 1; /*!< SM2_TXNFULL */ + __IOM uint32_t SM3_TXNFULL : 1; /*!< SM3_TXNFULL */ + __IOM uint32_t SM0 : 1; /*!< SM0 */ + __IOM uint32_t SM1 : 1; /*!< SM1 */ + __IOM uint32_t SM2 : 1; /*!< SM2 */ + __IOM uint32_t SM3 : 1; /*!< SM3 */ + __IOM uint32_t SM4 : 1; /*!< SM4 */ + __IOM uint32_t SM5 : 1; /*!< SM5 */ + __IOM uint32_t SM6 : 1; /*!< SM6 */ + __IOM uint32_t SM7 : 1; /*!< SM7 */ + uint32_t : 16; + } bit; + } IRQ0_INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for irq0 */ + + struct { + __IOM uint32_t SM0_RXNEMPTY : 1; /*!< SM0_RXNEMPTY */ + __IOM uint32_t SM1_RXNEMPTY : 1; /*!< SM1_RXNEMPTY */ + __IOM uint32_t SM2_RXNEMPTY : 1; /*!< SM2_RXNEMPTY */ + __IOM uint32_t SM3_RXNEMPTY : 1; /*!< SM3_RXNEMPTY */ + __IOM uint32_t SM0_TXNFULL : 1; /*!< SM0_TXNFULL */ + __IOM uint32_t SM1_TXNFULL : 1; /*!< SM1_TXNFULL */ + __IOM uint32_t SM2_TXNFULL : 1; /*!< SM2_TXNFULL */ + __IOM uint32_t SM3_TXNFULL : 1; /*!< SM3_TXNFULL */ + __IOM uint32_t SM0 : 1; /*!< SM0 */ + __IOM uint32_t SM1 : 1; /*!< SM1 */ + __IOM uint32_t SM2 : 1; /*!< SM2 */ + __IOM uint32_t SM3 : 1; /*!< SM3 */ + __IOM uint32_t SM4 : 1; /*!< SM4 */ + __IOM uint32_t SM5 : 1; /*!< SM5 */ + __IOM uint32_t SM6 : 1; /*!< SM6 */ + __IOM uint32_t SM7 : 1; /*!< SM7 */ + uint32_t : 16; + } bit; + } IRQ0_INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for irq0 */ + + struct { + __IM uint32_t SM0_RXNEMPTY : 1; /*!< SM0_RXNEMPTY */ + __IM uint32_t SM1_RXNEMPTY : 1; /*!< SM1_RXNEMPTY */ + __IM uint32_t SM2_RXNEMPTY : 1; /*!< SM2_RXNEMPTY */ + __IM uint32_t SM3_RXNEMPTY : 1; /*!< SM3_RXNEMPTY */ + __IM uint32_t SM0_TXNFULL : 1; /*!< SM0_TXNFULL */ + __IM uint32_t SM1_TXNFULL : 1; /*!< SM1_TXNFULL */ + __IM uint32_t SM2_TXNFULL : 1; /*!< SM2_TXNFULL */ + __IM uint32_t SM3_TXNFULL : 1; /*!< SM3_TXNFULL */ + __IM uint32_t SM0 : 1; /*!< SM0 */ + __IM uint32_t SM1 : 1; /*!< SM1 */ + __IM uint32_t SM2 : 1; /*!< SM2 */ + __IM uint32_t SM3 : 1; /*!< SM3 */ + __IM uint32_t SM4 : 1; /*!< SM4 */ + __IM uint32_t SM5 : 1; /*!< SM5 */ + __IM uint32_t SM6 : 1; /*!< SM6 */ + __IM uint32_t SM7 : 1; /*!< SM7 */ + uint32_t : 16; + } bit; + } IRQ0_INTS; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable for irq1 */ + + struct { + __IOM uint32_t SM0_RXNEMPTY : 1; /*!< SM0_RXNEMPTY */ + __IOM uint32_t SM1_RXNEMPTY : 1; /*!< SM1_RXNEMPTY */ + __IOM uint32_t SM2_RXNEMPTY : 1; /*!< SM2_RXNEMPTY */ + __IOM uint32_t SM3_RXNEMPTY : 1; /*!< SM3_RXNEMPTY */ + __IOM uint32_t SM0_TXNFULL : 1; /*!< SM0_TXNFULL */ + __IOM uint32_t SM1_TXNFULL : 1; /*!< SM1_TXNFULL */ + __IOM uint32_t SM2_TXNFULL : 1; /*!< SM2_TXNFULL */ + __IOM uint32_t SM3_TXNFULL : 1; /*!< SM3_TXNFULL */ + __IOM uint32_t SM0 : 1; /*!< SM0 */ + __IOM uint32_t SM1 : 1; /*!< SM1 */ + __IOM uint32_t SM2 : 1; /*!< SM2 */ + __IOM uint32_t SM3 : 1; /*!< SM3 */ + __IOM uint32_t SM4 : 1; /*!< SM4 */ + __IOM uint32_t SM5 : 1; /*!< SM5 */ + __IOM uint32_t SM6 : 1; /*!< SM6 */ + __IOM uint32_t SM7 : 1; /*!< SM7 */ + uint32_t : 16; + } bit; + } IRQ1_INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force for irq1 */ + + struct { + __IOM uint32_t SM0_RXNEMPTY : 1; /*!< SM0_RXNEMPTY */ + __IOM uint32_t SM1_RXNEMPTY : 1; /*!< SM1_RXNEMPTY */ + __IOM uint32_t SM2_RXNEMPTY : 1; /*!< SM2_RXNEMPTY */ + __IOM uint32_t SM3_RXNEMPTY : 1; /*!< SM3_RXNEMPTY */ + __IOM uint32_t SM0_TXNFULL : 1; /*!< SM0_TXNFULL */ + __IOM uint32_t SM1_TXNFULL : 1; /*!< SM1_TXNFULL */ + __IOM uint32_t SM2_TXNFULL : 1; /*!< SM2_TXNFULL */ + __IOM uint32_t SM3_TXNFULL : 1; /*!< SM3_TXNFULL */ + __IOM uint32_t SM0 : 1; /*!< SM0 */ + __IOM uint32_t SM1 : 1; /*!< SM1 */ + __IOM uint32_t SM2 : 1; /*!< SM2 */ + __IOM uint32_t SM3 : 1; /*!< SM3 */ + __IOM uint32_t SM4 : 1; /*!< SM4 */ + __IOM uint32_t SM5 : 1; /*!< SM5 */ + __IOM uint32_t SM6 : 1; /*!< SM6 */ + __IOM uint32_t SM7 : 1; /*!< SM7 */ + uint32_t : 16; + } bit; + } IRQ1_INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing for irq1 */ + + struct { + __IM uint32_t SM0_RXNEMPTY : 1; /*!< SM0_RXNEMPTY */ + __IM uint32_t SM1_RXNEMPTY : 1; /*!< SM1_RXNEMPTY */ + __IM uint32_t SM2_RXNEMPTY : 1; /*!< SM2_RXNEMPTY */ + __IM uint32_t SM3_RXNEMPTY : 1; /*!< SM3_RXNEMPTY */ + __IM uint32_t SM0_TXNFULL : 1; /*!< SM0_TXNFULL */ + __IM uint32_t SM1_TXNFULL : 1; /*!< SM1_TXNFULL */ + __IM uint32_t SM2_TXNFULL : 1; /*!< SM2_TXNFULL */ + __IM uint32_t SM3_TXNFULL : 1; /*!< SM3_TXNFULL */ + __IM uint32_t SM0 : 1; /*!< SM0 */ + __IM uint32_t SM1 : 1; /*!< SM1 */ + __IM uint32_t SM2 : 1; /*!< SM2 */ + __IM uint32_t SM3 : 1; /*!< SM3 */ + __IM uint32_t SM4 : 1; /*!< SM4 */ + __IM uint32_t SM5 : 1; /*!< SM5 */ + __IM uint32_t SM6 : 1; /*!< SM6 */ + __IM uint32_t SM7 : 1; /*!< SM7 */ + uint32_t : 16; + } bit; + } IRQ1_INTS; +} PIO0_Type; /*!< Size = 392 (0x188) */ + + + +/* =========================================================================================================================== */ +/* ================ BUSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for busfabric control signals and performance counters (BUSCTRL) + */ + +typedef struct { /*!< BUSCTRL Structure */ + + union { + __IOM uint32_t reg; /*!< Set the priority of each master for bus arbitration. */ + + struct { + __IOM uint32_t PROC0 : 1; /*!< 0 - low priority, 1 - high priority */ + uint32_t : 3; + __IOM uint32_t PROC1 : 1; /*!< 0 - low priority, 1 - high priority */ + uint32_t : 3; + __IOM uint32_t DMA_R : 1; /*!< 0 - low priority, 1 - high priority */ + uint32_t : 3; + __IOM uint32_t DMA_W : 1; /*!< 0 - low priority, 1 - high priority */ + uint32_t : 19; + } bit; + } BUS_PRIORITY; + + union { + __IOM uint32_t reg; /*!< Bus priority acknowledge */ + + struct { + __IM uint32_t BUS_PRIORITY_ACK : 1; /*!< Goes to 1 once all arbiters have registered the new global priority + levels. Arbiters update their local priority when servicing + a new nonsequential access. In normal circumstances this + will happen almost immediately. */ + uint32_t : 31; + } bit; + } BUS_PRIORITY_ACK; + + union { + __IOM uint32_t reg; /*!< Enable the performance counters. If 0, the performance counters + do not increment. This can be used to precisely start/stop + event sampling around the profiled section of code. The + performance counters are initially disabled, to save energy. */ + + struct { + __IOM uint32_t PERFCTR_EN : 1; /*!< PERFCTR_EN */ + uint32_t : 31; + } bit; + } PERFCTR_EN; + + union { + __IOM uint32_t reg; /*!< Bus fabric performance counter 0 */ + + struct { + __IOM uint32_t PERFCTR0 : 24; /*!< Busfabric saturating performance counter 0 Count some event + signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using + PERFSEL0 */ + uint32_t : 8; + } bit; + } PERFCTR0; + + union { + __IOM uint32_t reg; /*!< Bus fabric performance event select for PERFCTR0 */ + + struct { + __IOM uint32_t PERFSEL0 : 7; /*!< Select an event for PERFCTR0. For each downstream port of the + main crossbar, four events are available: ACCESS, an access + took place; ACCESS_CONTESTED, an access took place that + previously stalled due to contention from other masters; + STALL_DOWNSTREAM, count cycles where any master stalled + due to a stall on the downstream bus; STALL_UPSTREAM, count + cycles where any master stalled for any reason, including + contention from other masters. */ + uint32_t : 25; + } bit; + } PERFSEL0; + + union { + __IOM uint32_t reg; /*!< Bus fabric performance counter 1 */ + + struct { + __IOM uint32_t PERFCTR1 : 24; /*!< Busfabric saturating performance counter 1 Count some event + signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using + PERFSEL1 */ + uint32_t : 8; + } bit; + } PERFCTR1; + + union { + __IOM uint32_t reg; /*!< Bus fabric performance event select for PERFCTR1 */ + + struct { + __IOM uint32_t PERFSEL1 : 7; /*!< Select an event for PERFCTR1. For each downstream port of the + main crossbar, four events are available: ACCESS, an access + took place; ACCESS_CONTESTED, an access took place that + previously stalled due to contention from other masters; + STALL_DOWNSTREAM, count cycles where any master stalled + due to a stall on the downstream bus; STALL_UPSTREAM, count + cycles where any master stalled for any reason, including + contention from other masters. */ + uint32_t : 25; + } bit; + } PERFSEL1; + + union { + __IOM uint32_t reg; /*!< Bus fabric performance counter 2 */ + + struct { + __IOM uint32_t PERFCTR2 : 24; /*!< Busfabric saturating performance counter 2 Count some event + signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using + PERFSEL2 */ + uint32_t : 8; + } bit; + } PERFCTR2; + + union { + __IOM uint32_t reg; /*!< Bus fabric performance event select for PERFCTR2 */ + + struct { + __IOM uint32_t PERFSEL2 : 7; /*!< Select an event for PERFCTR2. For each downstream port of the + main crossbar, four events are available: ACCESS, an access + took place; ACCESS_CONTESTED, an access took place that + previously stalled due to contention from other masters; + STALL_DOWNSTREAM, count cycles where any master stalled + due to a stall on the downstream bus; STALL_UPSTREAM, count + cycles where any master stalled for any reason, including + contention from other masters. */ + uint32_t : 25; + } bit; + } PERFSEL2; + + union { + __IOM uint32_t reg; /*!< Bus fabric performance counter 3 */ + + struct { + __IOM uint32_t PERFCTR3 : 24; /*!< Busfabric saturating performance counter 3 Count some event + signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using + PERFSEL3 */ + uint32_t : 8; + } bit; + } PERFCTR3; + + union { + __IOM uint32_t reg; /*!< Bus fabric performance event select for PERFCTR3 */ + + struct { + __IOM uint32_t PERFSEL3 : 7; /*!< Select an event for PERFCTR3. For each downstream port of the + main crossbar, four events are available: ACCESS, an access + took place; ACCESS_CONTESTED, an access took place that + previously stalled due to contention from other masters; + STALL_DOWNSTREAM, count cycles where any master stalled + due to a stall on the downstream bus; STALL_UPSTREAM, count + cycles where any master stalled for any reason, including + contention from other masters. */ + uint32_t : 25; + } bit; + } PERFSEL3; +} BUSCTRL_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. (SIO) + */ + +typedef struct { /*!< SIO Structure */ + + union { + __IOM uint32_t reg; /*!< Processor core identifier */ + + struct { + __IM uint32_t CPUID : 32; /*!< Value is 0 when read from processor core 0, and 1 when read + from processor core 1. */ + } bit; + } CPUID; + + union { + __IOM uint32_t reg; /*!< Input value for GPIO0...31. In the Non-secure SIO, Secure-only + GPIOs (as per ACCESSCTRL) appear as zero. */ + + struct { + __IM uint32_t GPIO_IN : 32; /*!< GPIO_IN */ + } bit; + } GPIO_IN; + + union { + __IOM uint32_t reg; /*!< Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure + SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. */ + + struct { + __IM uint32_t GPIO : 16; /*!< Input value on GPIO32...47 */ + uint32_t : 8; + __IM uint32_t USB_DP : 1; /*!< Input value on USB D+ pin */ + __IM uint32_t USB_DM : 1; /*!< Input value on USB D- pin */ + __IM uint32_t QSPI_SCK : 1; /*!< Input value on QSPI SCK pin */ + __IM uint32_t QSPI_CSN : 1; /*!< Input value on QSPI CSn pin */ + __IM uint32_t QSPI_SD : 4; /*!< Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins */ + } bit; + } GPIO_HI_IN; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< GPIO0...31 output value */ + + struct { + __IOM uint32_t GPIO_OUT : 32; /*!< Set output level (1/0 -> high/low) for GPIO0...31. Reading back + gives the last value written, NOT the input value from + the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously + (or to a SET/CLR/XOR alias), the result is as though the + write from core 0 took place first, and the write from + core 1 was then applied to that intermediate result. In + the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) + ignore writes, and their output status reads back as zero. + This is also true for SET/CLR/XOR aliases of this register. */ + } bit; + } GPIO_OUT; + + union { + __IOM uint32_t reg; /*!< Output value for GPIO32...47, QSPI IOs and USB pins. Write to + set output level (1/0 -> high/low). Reading back gives + the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_HI_OUT simultaneously + (or to a SET/CLR/XOR alias), the result is as though the + write from core 0 took place first, and the write from + core 1 was then applied to that intermediate result. In + the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) + ignore writes, and their output status reads back as zero. + This is also true for SET/CLR/XOR aliases of this register. */ + + struct { + __IOM uint32_t GPIO : 16; /*!< Output value for GPIO32...47 */ + uint32_t : 8; + __IOM uint32_t USB_DP : 1; /*!< Output value for USB D+ pin */ + __IOM uint32_t USB_DM : 1; /*!< Output value for USB D- pin */ + __IOM uint32_t QSPI_SCK : 1; /*!< Output value for QSPI SCK pin */ + __IOM uint32_t QSPI_CSN : 1; /*!< Output value for QSPI CSn pin */ + __IOM uint32_t QSPI_SD : 4; /*!< Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins */ + } bit; + } GPIO_HI_OUT; + + union { + __IOM uint32_t reg; /*!< GPIO0...31 output value set */ + + struct { + __OM uint32_t GPIO_OUT_SET : 32; /*!< Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` */ + } bit; + } GPIO_OUT_SET; + + union { + __IOM uint32_t reg; /*!< Output value set for GPIO32..47, QSPI IOs and USB pins. Perform + an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= + wdata` */ + + struct { + __OM uint32_t GPIO : 16; /*!< GPIO */ + uint32_t : 8; + __OM uint32_t USB_DP : 1; /*!< USB_DP */ + __OM uint32_t USB_DM : 1; /*!< USB_DM */ + __OM uint32_t QSPI_SCK : 1; /*!< QSPI_SCK */ + __OM uint32_t QSPI_CSN : 1; /*!< QSPI_CSN */ + __OM uint32_t QSPI_SD : 4; /*!< QSPI_SD */ + } bit; + } GPIO_HI_OUT_SET; + + union { + __IOM uint32_t reg; /*!< GPIO0...31 output value clear */ + + struct { + __OM uint32_t GPIO_OUT_CLR : 32; /*!< Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` */ + } bit; + } GPIO_OUT_CLR; + + union { + __IOM uint32_t reg; /*!< Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform + an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= + ~wdata` */ + + struct { + __OM uint32_t GPIO : 16; /*!< GPIO */ + uint32_t : 8; + __OM uint32_t USB_DP : 1; /*!< USB_DP */ + __OM uint32_t USB_DM : 1; /*!< USB_DM */ + __OM uint32_t QSPI_SCK : 1; /*!< QSPI_SCK */ + __OM uint32_t QSPI_CSN : 1; /*!< QSPI_CSN */ + __OM uint32_t QSPI_SD : 4; /*!< QSPI_SD */ + } bit; + } GPIO_HI_OUT_CLR; + + union { + __IOM uint32_t reg; /*!< GPIO0...31 output value XOR */ + + struct { + __OM uint32_t GPIO_OUT_XOR : 32; /*!< Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= + wdata` */ + } bit; + } GPIO_OUT_XOR; + + union { + __IOM uint32_t reg; /*!< Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform + an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT + ^= wdata` */ + + struct { + __OM uint32_t GPIO : 16; /*!< GPIO */ + uint32_t : 8; + __OM uint32_t USB_DP : 1; /*!< USB_DP */ + __OM uint32_t USB_DM : 1; /*!< USB_DM */ + __OM uint32_t QSPI_SCK : 1; /*!< QSPI_SCK */ + __OM uint32_t QSPI_CSN : 1; /*!< QSPI_CSN */ + __OM uint32_t QSPI_SD : 4; /*!< QSPI_SD */ + } bit; + } GPIO_HI_OUT_XOR; + + union { + __IOM uint32_t reg; /*!< GPIO0...31 output enable */ + + struct { + __IOM uint32_t GPIO_OE : 32; /*!< Set output enable (1/0 -> output/input) for GPIO0...31. Reading + back gives the last value written. If core 0 and core 1 + both write to GPIO_OE simultaneously (or to a SET/CLR/XOR + alias), the result is as though the write from core 0 took + place first, and the write from core 1 was then applied + to that intermediate result. In the Non-secure SIO, Secure-only + GPIOs (as per ACCESSCTRL) ignore writes, and their output + status reads back as zero. This is also true for SET/CLR/XOR + aliases of this register. */ + } bit; + } GPIO_OE; + + union { + __IOM uint32_t reg; /*!< Output enable value for GPIO32...47, QSPI IOs and USB pins. + Write output enable (1/0 -> output/input). Reading back + gives the last value written. If core 0 and core 1 both + write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR + alias), the result is as though the write from core 0 took + place first, and the write from core 1 was then applied + to that intermediate result. In the Non-secure SIO, Secure-only + GPIOs (as per ACCESSCTRL) ignore writes, and their output + status reads back as zero. This is also true for SET/CLR/XOR + aliases of this register. */ + + struct { + __IOM uint32_t GPIO : 16; /*!< Output enable value for GPIO32...47 */ + uint32_t : 8; + __IOM uint32_t USB_DP : 1; /*!< Output enable value for USB D+ pin */ + __IOM uint32_t USB_DM : 1; /*!< Output enable value for USB D- pin */ + __IOM uint32_t QSPI_SCK : 1; /*!< Output enable value for QSPI SCK pin */ + __IOM uint32_t QSPI_CSN : 1; /*!< Output enable value for QSPI CSn pin */ + __IOM uint32_t QSPI_SD : 4; /*!< Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and + SD3 pins */ + } bit; + } GPIO_HI_OE; + + union { + __IOM uint32_t reg; /*!< GPIO0...31 output enable set */ + + struct { + __OM uint32_t GPIO_OE_SET : 32; /*!< Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` */ + } bit; + } GPIO_OE_SET; + + union { + __IOM uint32_t reg; /*!< Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform + an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` */ + + struct { + __OM uint32_t GPIO : 16; /*!< GPIO */ + uint32_t : 8; + __OM uint32_t USB_DP : 1; /*!< USB_DP */ + __OM uint32_t USB_DM : 1; /*!< USB_DM */ + __OM uint32_t QSPI_SCK : 1; /*!< QSPI_SCK */ + __OM uint32_t QSPI_CSN : 1; /*!< QSPI_CSN */ + __OM uint32_t QSPI_SD : 4; /*!< QSPI_SD */ + } bit; + } GPIO_HI_OE_SET; + + union { + __IOM uint32_t reg; /*!< GPIO0...31 output enable clear */ + + struct { + __OM uint32_t GPIO_OE_CLR : 32; /*!< Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` */ + } bit; + } GPIO_OE_CLR; + + union { + __IOM uint32_t reg; /*!< Output enable clear for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE + &= ~wdata` */ + + struct { + __OM uint32_t GPIO : 16; /*!< GPIO */ + uint32_t : 8; + __OM uint32_t USB_DP : 1; /*!< USB_DP */ + __OM uint32_t USB_DM : 1; /*!< USB_DM */ + __OM uint32_t QSPI_SCK : 1; /*!< QSPI_SCK */ + __OM uint32_t QSPI_CSN : 1; /*!< QSPI_CSN */ + __OM uint32_t QSPI_SD : 4; /*!< QSPI_SD */ + } bit; + } GPIO_HI_OE_CLR; + + union { + __IOM uint32_t reg; /*!< GPIO0...31 output enable XOR */ + + struct { + __OM uint32_t GPIO_OE_XOR : 32; /*!< Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` */ + } bit; + } GPIO_OE_XOR; + + union { + __IOM uint32_t reg; /*!< Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform + an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= + wdata` */ + + struct { + __OM uint32_t GPIO : 16; /*!< GPIO */ + uint32_t : 8; + __OM uint32_t USB_DP : 1; /*!< USB_DP */ + __OM uint32_t USB_DM : 1; /*!< USB_DM */ + __OM uint32_t QSPI_SCK : 1; /*!< QSPI_SCK */ + __OM uint32_t QSPI_CSN : 1; /*!< QSPI_CSN */ + __OM uint32_t QSPI_SD : 4; /*!< QSPI_SD */ + } bit; + } GPIO_HI_OE_XOR; + + union { + __IOM uint32_t reg; /*!< Status register for inter-core FIFOs (mailboxes). There is one + FIFO in the core 0 -> core 1 direction, and one core 1 + -> core 0. Both are 32 bits wide and 8 words deep. Core + 0 can see the read side of the 1->0 FIFO (RX), and the + write side of 0->1 FIFO (TX). Core 1 can see the read side + of the 0->1 FIFO (RX), and the write side of 1->0 FIFO + (TX). The SIO IRQ for each core is the logical OR of the + VLD, WOF and ROE fields of its FIFO_ST register. */ + + struct { + __IM uint32_t VLD : 1; /*!< Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD + is valid) */ + __IM uint32_t RDY : 1; /*!< Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR + is ready for more data) */ + __IOM uint32_t WOF : 1; /*!< Sticky flag indicating the TX FIFO was written when full. This + write was ignored by the FIFO. */ + __IOM uint32_t ROE : 1; /*!< Sticky flag indicating the RX FIFO was read when empty. This + read was ignored by the FIFO. */ + uint32_t : 28; + } bit; + } FIFO_ST; + + union { + __IOM uint32_t reg; /*!< Write access to this core's TX FIFO */ + + struct { + __OM uint32_t FIFO_WR : 32; /*!< FIFO_WR */ + } bit; + } FIFO_WR; + + union { + __IOM uint32_t reg; /*!< Read access to this core's RX FIFO */ + + struct { + __IM uint32_t FIFO_RD : 32; /*!< FIFO_RD */ + } bit; + } FIFO_RD; + + union { + __IOM uint32_t reg; /*!< Spinlock state A bitmap containing the state of all 32 spinlocks + (1=locked). Mainly intended for debugging. */ + + struct { + __IM uint32_t SPINLOCK_ST : 32; /*!< SPINLOCK_ST */ + } bit; + } SPINLOCK_ST; + __IM uint32_t RESERVED1[8]; + + union { + __IOM uint32_t reg; /*!< Read/write access to accumulator 0 */ + + struct { + __IOM uint32_t INTERP0_ACCUM0 : 32; /*!< INTERP0_ACCUM0 */ + } bit; + } INTERP0_ACCUM0; + + union { + __IOM uint32_t reg; /*!< Read/write access to accumulator 1 */ + + struct { + __IOM uint32_t INTERP0_ACCUM1 : 32; /*!< INTERP0_ACCUM1 */ + } bit; + } INTERP0_ACCUM1; + + union { + __IOM uint32_t reg; /*!< Read/write access to BASE0 register. */ + + struct { + __IOM uint32_t INTERP0_BASE0 : 32; /*!< INTERP0_BASE0 */ + } bit; + } INTERP0_BASE0; + + union { + __IOM uint32_t reg; /*!< Read/write access to BASE1 register. */ + + struct { + __IOM uint32_t INTERP0_BASE1 : 32; /*!< INTERP0_BASE1 */ + } bit; + } INTERP0_BASE1; + + union { + __IOM uint32_t reg; /*!< Read/write access to BASE2 register. */ + + struct { + __IOM uint32_t INTERP0_BASE2 : 32; /*!< INTERP0_BASE2 */ + } bit; + } INTERP0_BASE2; + + union { + __IOM uint32_t reg; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + + struct { + __IM uint32_t INTERP0_POP_LANE0 : 32; /*!< INTERP0_POP_LANE0 */ + } bit; + } INTERP0_POP_LANE0; + + union { + __IOM uint32_t reg; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + + struct { + __IM uint32_t INTERP0_POP_LANE1 : 32; /*!< INTERP0_POP_LANE1 */ + } bit; + } INTERP0_POP_LANE1; + + union { + __IOM uint32_t reg; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + + struct { + __IM uint32_t INTERP0_POP_FULL : 32; /*!< INTERP0_POP_FULL */ + } bit; + } INTERP0_POP_FULL; + + union { + __IOM uint32_t reg; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + + struct { + __IM uint32_t INTERP0_PEEK_LANE0 : 32; /*!< INTERP0_PEEK_LANE0 */ + } bit; + } INTERP0_PEEK_LANE0; + + union { + __IOM uint32_t reg; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + + struct { + __IM uint32_t INTERP0_PEEK_LANE1 : 32; /*!< INTERP0_PEEK_LANE1 */ + } bit; + } INTERP0_PEEK_LANE1; + + union { + __IOM uint32_t reg; /*!< Read FULL result, without altering any internal state (PEEK). */ + + struct { + __IM uint32_t INTERP0_PEEK_FULL : 32; /*!< INTERP0_PEEK_FULL */ + } bit; + } INTERP0_PEEK_FULL; + + union { + __IOM uint32_t reg; /*!< Control register for lane 0 */ + + struct { + __IOM uint32_t SHIFT : 5; /*!< Right-rotate applied to accumulator before masking. By appropriately + configuring the masks, left and right shifts can be synthesised. */ + __IOM uint32_t MASK_LSB : 5; /*!< The least-significant bit allowed to pass by the mask (inclusive) */ + __IOM uint32_t MASK_MSB : 5; /*!< The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out */ + __IOM uint32_t SIGNED : 1; /*!< If SIGNED is set, the shifted and masked accumulator value is + sign-extended to 32 bits before adding to BASE0, and LANE0 + PEEK/POP appear extended to 32 bits when read by processor. */ + __IOM uint32_t CROSS_INPUT : 1; /*!< If 1, feed the opposite lane's accumulator into this lane's + shift + mask hardware. Takes effect even if ADD_RAW is + set (the CROSS_INPUT mux is before the shift+mask bypass) */ + __IOM uint32_t CROSS_RESULT : 1; /*!< If 1, feed the opposite lane's result into this lane's accumulator + on POP. */ + __IOM uint32_t ADD_RAW : 1; /*!< If 1, mask + shift is bypassed for LANE0 result. This does not + affect FULL result. */ + __IOM uint32_t FORCE_MSB : 2; /*!< ORed into bits 29:28 of the lane result presented to the processor + on the bus. No effect on the internal 32-bit datapath. + Handy for using a lane to generate sequence of pointers + into flash or SRAM. */ + __IOM uint32_t BLEND : 1; /*!< Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 + and BASE1, controlled by the 8 LSBs of lane 1 shift and + mask value (a fractional number between 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the + 8 LSBs of lane 1 shift+mask value) - FULL result does not + have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is + signed or unsigned. */ + uint32_t : 1; + __IM uint32_t OVERF0 : 1; /*!< Indicates if any masked-off MSBs in ACCUM0 are set. */ + __IM uint32_t OVERF1 : 1; /*!< Indicates if any masked-off MSBs in ACCUM1 are set. */ + __IM uint32_t OVERF : 1; /*!< Set if either OVERF0 or OVERF1 is set. */ + uint32_t : 6; + } bit; + } INTERP0_CTRL_LANE0; + + union { + __IOM uint32_t reg; /*!< Control register for lane 1 */ + + struct { + __IOM uint32_t SHIFT : 5; /*!< Right-rotate applied to accumulator before masking. By appropriately + configuring the masks, left and right shifts can be synthesised. */ + __IOM uint32_t MASK_LSB : 5; /*!< The least-significant bit allowed to pass by the mask (inclusive) */ + __IOM uint32_t MASK_MSB : 5; /*!< The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out */ + __IOM uint32_t SIGNED : 1; /*!< If SIGNED is set, the shifted and masked accumulator value is + sign-extended to 32 bits before adding to BASE1, and LANE1 + PEEK/POP appear extended to 32 bits when read by processor. */ + __IOM uint32_t CROSS_INPUT : 1; /*!< If 1, feed the opposite lane's accumulator into this lane's + shift + mask hardware. Takes effect even if ADD_RAW is + set (the CROSS_INPUT mux is before the shift+mask bypass) */ + __IOM uint32_t CROSS_RESULT : 1; /*!< If 1, feed the opposite lane's result into this lane's accumulator + on POP. */ + __IOM uint32_t ADD_RAW : 1; /*!< If 1, mask + shift is bypassed for LANE1 result. This does not + affect FULL result. */ + __IOM uint32_t FORCE_MSB : 2; /*!< ORed into bits 29:28 of the lane result presented to the processor + on the bus. No effect on the internal 32-bit datapath. + Handy for using a lane to generate sequence of pointers + into flash or SRAM. */ + uint32_t : 11; + } bit; + } INTERP0_CTRL_LANE1; + + union { + __IOM uint32_t reg; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + + struct { + __IOM uint32_t INTERP0_ACCUM0_ADD : 24; /*!< INTERP0_ACCUM0_ADD */ + uint32_t : 8; + } bit; + } INTERP0_ACCUM0_ADD; + + union { + __IOM uint32_t reg; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + + struct { + __IOM uint32_t INTERP0_ACCUM1_ADD : 24; /*!< INTERP0_ACCUM1_ADD */ + uint32_t : 8; + } bit; + } INTERP0_ACCUM1_ADD; + + union { + __IOM uint32_t reg; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + + struct { + __OM uint32_t INTERP0_BASE_1AND0 : 32; /*!< INTERP0_BASE_1AND0 */ + } bit; + } INTERP0_BASE_1AND0; + + union { + __IOM uint32_t reg; /*!< Read/write access to accumulator 0 */ + + struct { + __IOM uint32_t INTERP1_ACCUM0 : 32; /*!< INTERP1_ACCUM0 */ + } bit; + } INTERP1_ACCUM0; + + union { + __IOM uint32_t reg; /*!< Read/write access to accumulator 1 */ + + struct { + __IOM uint32_t INTERP1_ACCUM1 : 32; /*!< INTERP1_ACCUM1 */ + } bit; + } INTERP1_ACCUM1; + + union { + __IOM uint32_t reg; /*!< Read/write access to BASE0 register. */ + + struct { + __IOM uint32_t INTERP1_BASE0 : 32; /*!< INTERP1_BASE0 */ + } bit; + } INTERP1_BASE0; + + union { + __IOM uint32_t reg; /*!< Read/write access to BASE1 register. */ + + struct { + __IOM uint32_t INTERP1_BASE1 : 32; /*!< INTERP1_BASE1 */ + } bit; + } INTERP1_BASE1; + + union { + __IOM uint32_t reg; /*!< Read/write access to BASE2 register. */ + + struct { + __IOM uint32_t INTERP1_BASE2 : 32; /*!< INTERP1_BASE2 */ + } bit; + } INTERP1_BASE2; + + union { + __IOM uint32_t reg; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + + struct { + __IM uint32_t INTERP1_POP_LANE0 : 32; /*!< INTERP1_POP_LANE0 */ + } bit; + } INTERP1_POP_LANE0; + + union { + __IOM uint32_t reg; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + + struct { + __IM uint32_t INTERP1_POP_LANE1 : 32; /*!< INTERP1_POP_LANE1 */ + } bit; + } INTERP1_POP_LANE1; + + union { + __IOM uint32_t reg; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + + struct { + __IM uint32_t INTERP1_POP_FULL : 32; /*!< INTERP1_POP_FULL */ + } bit; + } INTERP1_POP_FULL; + + union { + __IOM uint32_t reg; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + + struct { + __IM uint32_t INTERP1_PEEK_LANE0 : 32; /*!< INTERP1_PEEK_LANE0 */ + } bit; + } INTERP1_PEEK_LANE0; + + union { + __IOM uint32_t reg; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + + struct { + __IM uint32_t INTERP1_PEEK_LANE1 : 32; /*!< INTERP1_PEEK_LANE1 */ + } bit; + } INTERP1_PEEK_LANE1; + + union { + __IOM uint32_t reg; /*!< Read FULL result, without altering any internal state (PEEK). */ + + struct { + __IM uint32_t INTERP1_PEEK_FULL : 32; /*!< INTERP1_PEEK_FULL */ + } bit; + } INTERP1_PEEK_FULL; + + union { + __IOM uint32_t reg; /*!< Control register for lane 0 */ + + struct { + __IOM uint32_t SHIFT : 5; /*!< Right-rotate applied to accumulator before masking. By appropriately + configuring the masks, left and right shifts can be synthesised. */ + __IOM uint32_t MASK_LSB : 5; /*!< The least-significant bit allowed to pass by the mask (inclusive) */ + __IOM uint32_t MASK_MSB : 5; /*!< The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out */ + __IOM uint32_t SIGNED : 1; /*!< If SIGNED is set, the shifted and masked accumulator value is + sign-extended to 32 bits before adding to BASE0, and LANE0 + PEEK/POP appear extended to 32 bits when read by processor. */ + __IOM uint32_t CROSS_INPUT : 1; /*!< If 1, feed the opposite lane's accumulator into this lane's + shift + mask hardware. Takes effect even if ADD_RAW is + set (the CROSS_INPUT mux is before the shift+mask bypass) */ + __IOM uint32_t CROSS_RESULT : 1; /*!< If 1, feed the opposite lane's result into this lane's accumulator + on POP. */ + __IOM uint32_t ADD_RAW : 1; /*!< If 1, mask + shift is bypassed for LANE0 result. This does not + affect FULL result. */ + __IOM uint32_t FORCE_MSB : 2; /*!< ORed into bits 29:28 of the lane result presented to the processor + on the bus. No effect on the internal 32-bit datapath. + Handy for using a lane to generate sequence of pointers + into flash or SRAM. */ + uint32_t : 1; + __IOM uint32_t CLAMP : 1; /*!< Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by + a lower bound of BASE0 and an upper bound of BASE1. - Signedness + of these comparisons is determined by LANE0_CTRL_SIGNED */ + __IM uint32_t OVERF0 : 1; /*!< Indicates if any masked-off MSBs in ACCUM0 are set. */ + __IM uint32_t OVERF1 : 1; /*!< Indicates if any masked-off MSBs in ACCUM1 are set. */ + __IM uint32_t OVERF : 1; /*!< Set if either OVERF0 or OVERF1 is set. */ + uint32_t : 6; + } bit; + } INTERP1_CTRL_LANE0; + + union { + __IOM uint32_t reg; /*!< Control register for lane 1 */ + + struct { + __IOM uint32_t SHIFT : 5; /*!< Right-rotate applied to accumulator before masking. By appropriately + configuring the masks, left and right shifts can be synthesised. */ + __IOM uint32_t MASK_LSB : 5; /*!< The least-significant bit allowed to pass by the mask (inclusive) */ + __IOM uint32_t MASK_MSB : 5; /*!< The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out */ + __IOM uint32_t SIGNED : 1; /*!< If SIGNED is set, the shifted and masked accumulator value is + sign-extended to 32 bits before adding to BASE1, and LANE1 + PEEK/POP appear extended to 32 bits when read by processor. */ + __IOM uint32_t CROSS_INPUT : 1; /*!< If 1, feed the opposite lane's accumulator into this lane's + shift + mask hardware. Takes effect even if ADD_RAW is + set (the CROSS_INPUT mux is before the shift+mask bypass) */ + __IOM uint32_t CROSS_RESULT : 1; /*!< If 1, feed the opposite lane's result into this lane's accumulator + on POP. */ + __IOM uint32_t ADD_RAW : 1; /*!< If 1, mask + shift is bypassed for LANE1 result. This does not + affect FULL result. */ + __IOM uint32_t FORCE_MSB : 2; /*!< ORed into bits 29:28 of the lane result presented to the processor + on the bus. No effect on the internal 32-bit datapath. + Handy for using a lane to generate sequence of pointers + into flash or SRAM. */ + uint32_t : 11; + } bit; + } INTERP1_CTRL_LANE1; + + union { + __IOM uint32_t reg; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + + struct { + __IOM uint32_t INTERP1_ACCUM0_ADD : 24; /*!< INTERP1_ACCUM0_ADD */ + uint32_t : 8; + } bit; + } INTERP1_ACCUM0_ADD; + + union { + __IOM uint32_t reg; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + + struct { + __IOM uint32_t INTERP1_ACCUM1_ADD : 24; /*!< INTERP1_ACCUM1_ADD */ + uint32_t : 8; + } bit; + } INTERP1_ACCUM1_ADD; + + union { + __IOM uint32_t reg; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + + struct { + __OM uint32_t INTERP1_BASE_1AND0 : 32; /*!< INTERP1_BASE_1AND0 */ + } bit; + } INTERP1_BASE_1AND0; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK0 : 32; /*!< SPINLOCK0 */ + } bit; + } SPINLOCK0; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK1 : 32; /*!< SPINLOCK1 */ + } bit; + } SPINLOCK1; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK2 : 32; /*!< SPINLOCK2 */ + } bit; + } SPINLOCK2; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK3 : 32; /*!< SPINLOCK3 */ + } bit; + } SPINLOCK3; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK4 : 32; /*!< SPINLOCK4 */ + } bit; + } SPINLOCK4; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK5 : 32; /*!< SPINLOCK5 */ + } bit; + } SPINLOCK5; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK6 : 32; /*!< SPINLOCK6 */ + } bit; + } SPINLOCK6; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK7 : 32; /*!< SPINLOCK7 */ + } bit; + } SPINLOCK7; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK8 : 32; /*!< SPINLOCK8 */ + } bit; + } SPINLOCK8; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK9 : 32; /*!< SPINLOCK9 */ + } bit; + } SPINLOCK9; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK10 : 32; /*!< SPINLOCK10 */ + } bit; + } SPINLOCK10; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK11 : 32; /*!< SPINLOCK11 */ + } bit; + } SPINLOCK11; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK12 : 32; /*!< SPINLOCK12 */ + } bit; + } SPINLOCK12; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK13 : 32; /*!< SPINLOCK13 */ + } bit; + } SPINLOCK13; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK14 : 32; /*!< SPINLOCK14 */ + } bit; + } SPINLOCK14; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK15 : 32; /*!< SPINLOCK15 */ + } bit; + } SPINLOCK15; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK16 : 32; /*!< SPINLOCK16 */ + } bit; + } SPINLOCK16; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK17 : 32; /*!< SPINLOCK17 */ + } bit; + } SPINLOCK17; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK18 : 32; /*!< SPINLOCK18 */ + } bit; + } SPINLOCK18; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK19 : 32; /*!< SPINLOCK19 */ + } bit; + } SPINLOCK19; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK20 : 32; /*!< SPINLOCK20 */ + } bit; + } SPINLOCK20; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK21 : 32; /*!< SPINLOCK21 */ + } bit; + } SPINLOCK21; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK22 : 32; /*!< SPINLOCK22 */ + } bit; + } SPINLOCK22; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK23 : 32; /*!< SPINLOCK23 */ + } bit; + } SPINLOCK23; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK24 : 32; /*!< SPINLOCK24 */ + } bit; + } SPINLOCK24; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK25 : 32; /*!< SPINLOCK25 */ + } bit; + } SPINLOCK25; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK26 : 32; /*!< SPINLOCK26 */ + } bit; + } SPINLOCK26; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK27 : 32; /*!< SPINLOCK27 */ + } bit; + } SPINLOCK27; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK28 : 32; /*!< SPINLOCK28 */ + } bit; + } SPINLOCK28; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK29 : 32; /*!< SPINLOCK29 */ + } bit; + } SPINLOCK29; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK30 : 32; /*!< SPINLOCK30 */ + } bit; + } SPINLOCK30; + + union { + __IOM uint32_t reg; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + + struct { + __IOM uint32_t SPINLOCK31 : 32; /*!< SPINLOCK31 */ + } bit; + } SPINLOCK31; + + union { + __IOM uint32_t reg; /*!< Trigger a doorbell interrupt on the opposite core. Write 1 to + a bit to set the corresponding bit in DOORBELL_IN on the + opposite core. This raises the opposite core's doorbell + interrupt. Read to get the status of the doorbells currently + asserted on the opposite core. This is equivalent to that + core reading its own DOORBELL_IN status. */ + + struct { + __IOM uint32_t DOORBELL_OUT_SET : 8; /*!< DOORBELL_OUT_SET */ + uint32_t : 24; + } bit; + } DOORBELL_OUT_SET; + + union { + __IOM uint32_t reg; /*!< Clear doorbells which have been posted to the opposite core. + This register is intended for debugging and initialisation + purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears + the corresponding bit in DOORBELL_IN on the opposite core. + Clearing all bits will cause that core's doorbell interrupt + to deassert. Since the usual order of events is for software + to send events using DOORBELL_OUT_SET, and acknowledge + incoming events by writing to DOORBELL_IN_CLR, this register + should be used with caution to avoid race conditions. Reading + returns the status of the doorbells currently asserted + on the other core, i.e. is equivalent to that core reading + its own DOORBELL_IN status. */ + + struct { + __IOM uint32_t DOORBELL_OUT_CLR : 8; /*!< DOORBELL_OUT_CLR */ + uint32_t : 24; + } bit; + } DOORBELL_OUT_CLR; + + union { + __IOM uint32_t reg; /*!< Write 1s to trigger doorbell interrupts on this core. Read to + get status of doorbells currently asserted on this core. */ + + struct { + __IOM uint32_t DOORBELL_IN_SET : 8; /*!< DOORBELL_IN_SET */ + uint32_t : 24; + } bit; + } DOORBELL_IN_SET; + + union { + __IOM uint32_t reg; /*!< Check and acknowledge doorbells posted to this core. This core's + doorbell interrupt is asserted when any bit in this register + is 1. Write 1 to each bit to clear that bit. The doorbell + interrupt deasserts once all bits are cleared. Read to + get status of doorbells currently asserted on this core. */ + + struct { + __IOM uint32_t DOORBELL_IN_CLR : 8; /*!< DOORBELL_IN_CLR */ + uint32_t : 24; + } bit; + } DOORBELL_IN_CLR; + + union { + __IOM uint32_t reg; /*!< Detach certain core-local peripherals from Secure SIO, and attach + them to Non-secure SIO, so that Non-secure software can + use them. Attempting to access one of these peripherals + from the Secure SIO when it is attached to the Non-secure + SIO, or vice versa, will generate a bus error. This register + is per-core, and is only present on the Secure SIO. Most + SIO hardware is duplicated across the Secure and Non-secure + SIO, so is not listed in this register. */ + + struct { + __IOM uint32_t INTERP0 : 1; /*!< If 1, detach interpolator 0 (of this core) from the Secure SIO, + and attach to the Non-secure SIO. */ + __IOM uint32_t INTERP1 : 1; /*!< If 1, detach interpolator 1 (of this core) from the Secure SIO, + and attach to the Non-secure SIO. */ + uint32_t : 3; + __IOM uint32_t TMDS : 1; /*!< IF 1, detach TMDS encoder (of this core) from the Secure SIO, + and attach to the Non-secure SIO. */ + uint32_t : 26; + } bit; + } PERI_NONSEC; + __IM uint32_t RESERVED2[3]; + + union { + __IOM uint32_t reg; /*!< Control the assertion of the standard software interrupt (MIP.MSIP) + on the RISC-V cores. Unlike the RISC-V timer, this interrupt + is not routed to a normal system-level interrupt line, + so can not be used by the Arm cores. It is safe for both + cores to write to this register on the same cycle. The + set/clear effect is accumulated across both cores, and + then applied. If a flag is both set and cleared on the + same cycle, only the set takes effect. */ + + struct { + __IOM uint32_t CORE0_SET : 1; /*!< Write 1 to atomically set the core 0 software interrupt flag. + Read to get the status of this flag. */ + __IOM uint32_t CORE1_SET : 1; /*!< Write 1 to atomically set the core 1 software interrupt flag. + Read to get the status of this flag. */ + uint32_t : 6; + __IOM uint32_t CORE0_CLR : 1; /*!< Write 1 to atomically clear the core 0 software interrupt flag. + Read to get the status of this flag. */ + __IOM uint32_t CORE1_CLR : 1; /*!< Write 1 to atomically clear the core 1 software interrupt flag. + Read to get the status of this flag. */ + uint32_t : 22; + } bit; + } RISCV_SOFTIRQ; + + union { + __IOM uint32_t reg; /*!< Control register for the RISC-V 64-bit Machine-mode timer. This + timer is only present in the Secure SIO, so is only accessible + to an Arm core in Secure mode or a RISC-V core in Machine + mode. Note whilst this timer follows the RISC-V privileged + specification, it is equally usable by the Arm cores. The + interrupts are routed to normal system-level interrupt + lines as well as to the MIP.MTIP inputs on the RISC-V cores. */ + + struct { + __IOM uint32_t EN : 1; /*!< Timer enable bit. When 0, the timer will not increment automatically. */ + __IOM uint32_t FULLSPEED : 1; /*!< If 1, increment the timer every cycle (i.e. run directly from + the system clock), rather than incrementing on the system-level + timer tick input. */ + __IOM uint32_t DBGPAUSE_CORE0 : 1; /*!< If 1, the timer pauses when core 0 is in the debug halt state. */ + __IOM uint32_t DBGPAUSE_CORE1 : 1; /*!< If 1, the timer pauses when core 1 is in the debug halt state. */ + uint32_t : 28; + } bit; + } MTIME_CTRL; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t reg; /*!< Read/write access to the high half of RISC-V Machine-mode timer. + This register is shared between both cores. If both cores + write on the same cycle, core 1 takes precedence. */ + + struct { + __IOM uint32_t MTIME : 32; /*!< MTIME */ + } bit; + } MTIME; + + union { + __IOM uint32_t reg; /*!< Read/write access to the high half of RISC-V Machine-mode timer. + This register is shared between both cores. If both cores + write on the same cycle, core 1 takes precedence. */ + + struct { + __IOM uint32_t MTIMEH : 32; /*!< MTIMEH */ + } bit; + } MTIMEH; + + union { + __IOM uint32_t reg; /*!< Low half of RISC-V Machine-mode timer comparator. This register + is core-local, i.e., each core gets a copy of this register, + with the comparison result routed to its own interrupt + line. The timer interrupt is asserted whenever MTIME is + greater than or equal to MTIMECMP. This comparison is unsigned, + and performed on the full 64-bit values. */ + + struct { + __IOM uint32_t MTIMECMP : 32; /*!< MTIMECMP */ + } bit; + } MTIMECMP; + + union { + __IOM uint32_t reg; /*!< High half of RISC-V Machine-mode timer comparator. This register + is core-local. The timer interrupt is asserted whenever + MTIME is greater than or equal to MTIMECMP. This comparison + is unsigned, and performed on the full 64-bit values. */ + + struct { + __IOM uint32_t MTIMECMPH : 32; /*!< MTIMECMPH */ + } bit; + } MTIMECMPH; + + union { + __IOM uint32_t reg; /*!< Control register for TMDS encoder. */ + + struct { + __IOM uint32_t L0_ROT : 4; /*!< Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, + in order to get the MSB of the lane 0 (blue) colour data + aligned with the MSB of the 8-bit encoder input. For example, + for RGB565 (red most significant), blue is bits 4:0, so + should be right-rotated by 13 to align with bits 7:3 of + the encoder input. */ + __IOM uint32_t L1_ROT : 4; /*!< Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, + in order to get the MSB of the lane 1 (green) colour data + aligned with the MSB of the 8-bit encoder input. For example, + for RGB565, green is bits 10:5, so should be right-rotated + by 3 bits to align with bits 7:2 of the encoder input. */ + __IOM uint32_t L2_ROT : 4; /*!< Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, + in order to get the MSB of the lane 2 (red) colour data + aligned with the MSB of the 8-bit encoder input. For example, + for RGB565 (red most significant), red is bits 15:11, so + should be right-rotated by 8 bits to align with bits 7:3 + of the encoder input. */ + __IOM uint32_t L0_NBITS : 3; /*!< Number of valid colour MSBs for lane 0 (1-8 bits, encoded as + 0 through 7). Remaining LSBs are masked to 0 after the + rotate. */ + __IOM uint32_t L1_NBITS : 3; /*!< Number of valid colour MSBs for lane 1 (1-8 bits, encoded as + 0 through 7). Remaining LSBs are masked to 0 after the + rotate. */ + __IOM uint32_t L2_NBITS : 3; /*!< Number of valid colour MSBs for lane 2 (1-8 bits, encoded as + 0 through 7). Remaining LSBs are masked to 0 after the + rotate. */ + uint32_t : 2; + __IOM uint32_t INTERLEAVE : 1; /*!< Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. + When interleaving is disabled, each of the 3 symbols appears + as a contiguous 10-bit field, with lane 0 being the least-significant + and starting at bit 0 of the register. When interleaving + is enabled, the symbols are packed into 5 chunks of 3 lanes + times 2 bits (30 bits total). Each chunk contains two bits + of a TMDS symbol per lane, with lane 0 being the least + significant. */ + __IOM uint32_t PIX_SHIFT : 3; /*!< Shift applied to the colour data register with each read of + a POP alias register. Reading from the POP_SINGLE register, + or reading from the POP_DOUBLE register with PIX2_NOSHIFT + set (for pixel doubling), shifts by the indicated amount. + Reading from a POP_DOUBLE register when PIX2_NOSHIFT is + clear will shift by double the indicated amount. (Shift + by 32 means no shift.) */ + __IOM uint32_t PIX2_NOSHIFT : 1; /*!< When encoding two pixels's worth of symbols in one cycle (a + read of a PEEK/POP_DOUBLE register), the second encoder + sees a shifted version of the colour data register. This + control disables that shift, so that both encoder layers + see the same pixel data. This is used for pixel doubling. */ + __OM uint32_t CLEAR_BALANCE : 1; /*!< Clear the running DC balance state of the TMDS encoders. This + bit should be written once at the beginning of each scanline. */ + uint32_t : 3; + } bit; + } TMDS_CTRL; + + union { + __IOM uint32_t reg; /*!< Write-only access to the TMDS colour data register. */ + + struct { + __OM uint32_t TMDS_WDATA : 32; /*!< TMDS_WDATA */ + } bit; + } TMDS_WDATA; + + union { + __IOM uint32_t reg; /*!< Get the encoding of one pixel's worth of colour data, packed + into a 32-bit value (3x10-bit symbols). The PEEK alias + does not shift the colour register when read, but still + advances the running DC balance state of each encoder. + This is useful for pixel doubling. */ + + struct { + __IM uint32_t TMDS_PEEK_SINGLE : 32; /*!< TMDS_PEEK_SINGLE */ + } bit; + } TMDS_PEEK_SINGLE; + + union { + __IOM uint32_t reg; /*!< Get the encoding of one pixel's worth of colour data, packed + into a 32-bit value. The packing is 5 chunks of 3 lanes + times 2 bits (30 bits total). Each chunk contains two bits + of a TMDS symbol per lane. This format is intended for + shifting out with the HSTX peripheral on RP2350. The POP + alias shifts the colour register when read, as well as + advancing the running DC balance state of each encoder. */ + + struct { + __IM uint32_t TMDS_POP_SINGLE : 32; /*!< TMDS_POP_SINGLE */ + } bit; + } TMDS_POP_SINGLE; + + union { + __IOM uint32_t reg; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The PEEK alias does not shift the colour register + when read, but still advances the lane 0 DC balance state. + This is useful if all 3 lanes' worth of encode are to be + read at once, rather than processing the entire scanline + for one lane before moving to the next lane. */ + + struct { + __IM uint32_t TMDS_PEEK_DOUBLE_L0 : 32; /*!< TMDS_PEEK_DOUBLE_L0 */ + } bit; + } TMDS_PEEK_DOUBLE_L0; + + union { + __IOM uint32_t reg; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The POP alias shifts the colour register when read, + according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ + + struct { + __IM uint32_t TMDS_POP_DOUBLE_L0 : 32; /*!< TMDS_POP_DOUBLE_L0 */ + } bit; + } TMDS_POP_DOUBLE_L0; + + union { + __IOM uint32_t reg; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The PEEK alias does not shift the colour register + when read, but still advances the lane 1 DC balance state. + This is useful if all 3 lanes' worth of encode are to be + read at once, rather than processing the entire scanline + for one lane before moving to the next lane. */ + + struct { + __IM uint32_t TMDS_PEEK_DOUBLE_L1 : 32; /*!< TMDS_PEEK_DOUBLE_L1 */ + } bit; + } TMDS_PEEK_DOUBLE_L1; + + union { + __IOM uint32_t reg; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The POP alias shifts the colour register when read, + according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ + + struct { + __IM uint32_t TMDS_POP_DOUBLE_L1 : 32; /*!< TMDS_POP_DOUBLE_L1 */ + } bit; + } TMDS_POP_DOUBLE_L1; + + union { + __IOM uint32_t reg; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The PEEK alias does not shift the colour register + when read, but still advances the lane 2 DC balance state. + This is useful if all 3 lanes' worth of encode are to be + read at once, rather than processing the entire scanline + for one lane before moving to the next lane. */ + + struct { + __IM uint32_t TMDS_PEEK_DOUBLE_L2 : 32; /*!< TMDS_PEEK_DOUBLE_L2 */ + } bit; + } TMDS_PEEK_DOUBLE_L2; + + union { + __IOM uint32_t reg; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The POP alias shifts the colour register when read, + according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ + + struct { + __IM uint32_t TMDS_POP_DOUBLE_L2 : 32; /*!< TMDS_POP_DOUBLE_L2 */ + } bit; + } TMDS_POP_DOUBLE_L2; +} SIO_Type; /*!< Size = 488 (0x1e8) */ + + + +/* =========================================================================================================================== */ +/* ================ BOOTRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Additional registers mapped adjacent to the bootram, for use by the bootrom. (BOOTRAM) + */ + +typedef struct { /*!< BOOTRAM Structure */ + __IM uint32_t RESERVED[512]; + + union { + __IOM uint32_t reg; /*!< This registers always ORs writes into its current contents. + Once a bit is set, it can only be cleared by a reset. */ + + struct { + __IOM uint32_t WRITE_ONCE0 : 32; /*!< WRITE_ONCE0 */ + } bit; + } WRITE_ONCE0; + + union { + __IOM uint32_t reg; /*!< This registers always ORs writes into its current contents. + Once a bit is set, it can only be cleared by a reset. */ + + struct { + __IOM uint32_t WRITE_ONCE1 : 32; /*!< WRITE_ONCE1 */ + } bit; + } WRITE_ONCE1; + + union { + __IOM uint32_t reg; /*!< Bootlock status register. 1=unclaimed, 0=claimed. These locks + function identically to the SIO spinlocks, but are reserved + for bootrom use. */ + + struct { + __IOM uint32_t BOOTLOCK_STAT : 8; /*!< BOOTLOCK_STAT */ + uint32_t : 24; + } bit; + } BOOTLOCK_STAT; + + union { + __IOM uint32_t reg; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + + struct { + __IOM uint32_t BOOTLOCK0 : 32; /*!< BOOTLOCK0 */ + } bit; + } BOOTLOCK0; + + union { + __IOM uint32_t reg; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + + struct { + __IOM uint32_t BOOTLOCK1 : 32; /*!< BOOTLOCK1 */ + } bit; + } BOOTLOCK1; + + union { + __IOM uint32_t reg; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + + struct { + __IOM uint32_t BOOTLOCK2 : 32; /*!< BOOTLOCK2 */ + } bit; + } BOOTLOCK2; + + union { + __IOM uint32_t reg; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + + struct { + __IOM uint32_t BOOTLOCK3 : 32; /*!< BOOTLOCK3 */ + } bit; + } BOOTLOCK3; + + union { + __IOM uint32_t reg; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + + struct { + __IOM uint32_t BOOTLOCK4 : 32; /*!< BOOTLOCK4 */ + } bit; + } BOOTLOCK4; + + union { + __IOM uint32_t reg; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + + struct { + __IOM uint32_t BOOTLOCK5 : 32; /*!< BOOTLOCK5 */ + } bit; + } BOOTLOCK5; + + union { + __IOM uint32_t reg; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + + struct { + __IOM uint32_t BOOTLOCK6 : 32; /*!< BOOTLOCK6 */ + } bit; + } BOOTLOCK6; + + union { + __IOM uint32_t reg; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + + struct { + __IOM uint32_t BOOTLOCK7 : 32; /*!< BOOTLOCK7 */ + } bit; + } BOOTLOCK7; +} BOOTRAM_Type; /*!< Size = 2092 (0x82c) */ + + + +/* =========================================================================================================================== */ +/* ================ CORESIGHT_TRACE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Coresight block - RP specific registers (CORESIGHT_TRACE) + */ + +typedef struct { /*!< CORESIGHT_TRACE Structure */ + + union { + __IOM uint32_t reg; /*!< Control and status register */ + + struct { + __IOM uint32_t TRACE_CAPTURE_FIFO_FLUSH : 1;/*!< Set to 1 to continuously hold the trace FIFO in a flushed state + and prevent overflow. Before clearing this flag, configure + and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO + register. Clear this flag to begin sampling trace data, + and set once again once the trace capture buffer is full. + You must configure the TPIU in order to generate trace + packets to be captured, as well as components like the + ETM further upstream to generate the event stream propagated + to the TPIU. */ + __IOM uint32_t TRACE_CAPTURE_FIFO_OVERFLOW : 1;/*!< This status flag is set high when trace data has been dropped + due to the FIFO being full at the point trace data was + sampled. Write 1 to acknowledge and clear the bit. */ + uint32_t : 30; + } bit; + } CTRL_STATUS; + + union { + __IOM uint32_t reg; /*!< FIFO for trace data captured from the TPIU */ + + struct { + __IM uint32_t RDATA : 32; /*!< Read from an 8 x 32-bit FIFO containing trace data captured + from the TPIU. Hardware pushes to the FIFO on rising edges + of clk_sys, when either of the following is true: * TPIU + TRACECTL output is low (normal trace data) * TPIU TRACETCL + output is high, and TPIU TRACEDATA0 and TRACEDATA1 are + both low (trigger packet) These conditions are in accordance + with Arm Coresight Architecture Spec v3.0 section D3.3.3: + Decoding requirements for Trace Capture Devices The data + captured into the FIFO is the full 32-bit TRACEDATA bus + output by the TPIU. Note that the TPIU is a DDR output + at half of clk_sys, therefore this interface can capture + the full 32-bit TPIU DDR output bandwidth as it samples + once per active edge of the TPIU output clock. */ + } bit; + } TRACE_CAPTURE_FIFO; +} CORESIGHT_TRACE_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB FS/LS controller device registers (USB) + */ + +typedef struct { /*!< USB Structure */ + + union { + __IOM uint32_t reg; /*!< Device address and endpoint control */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< In device mode, the address that the device should respond to. + Set in response to a SET_ADDR setup packet from the host. + In host mode set to the address of the device to communicate + with. */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Device endpoint to send data to. Only valid for HOST mode. */ + uint32_t : 12; + } bit; + } ADDR_ENDP; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 1. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP1; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 2. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP2; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 3. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP3; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 4. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP4; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 5. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP5; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 6. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP6; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 7. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP7; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 8. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP8; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 9. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP9; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 10. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP10; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 11. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP11; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 12. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP12; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 13. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP13; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 14. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP14; + + union { + __IOM uint32_t reg; /*!< Interrupt endpoint 15. Only valid for HOST mode. */ + + struct { + __IOM uint32_t ADDRESS : 7; /*!< Device address */ + uint32_t : 9; + __IOM uint32_t ENDPOINT : 4; /*!< Endpoint number of the interrupt endpoint */ + uint32_t : 5; + __IOM uint32_t INTEP_DIR : 1; /*!< Direction of the interrupt endpoint. In=0, Out=1 */ + __IOM uint32_t INTEP_PREAMBLE : 1; /*!< Interrupt EP requires preamble (is a low speed device on a full + speed hub) */ + uint32_t : 5; + } bit; + } ADDR_ENDP15; + + union { + __IOM uint32_t reg; /*!< Main control register */ + + struct { + __IOM uint32_t CONTROLLER_EN : 1; /*!< Enable controller */ + __IOM uint32_t HOST_NDEVICE : 1; /*!< Device mode = 0, Host mode = 1 */ + __IOM uint32_t PHY_ISO : 1; /*!< Isolates USB phy after controller power-up Remove isolation + once software has configured the controller Not isolated + = 0, Isolated = 1 */ + uint32_t : 28; + __IOM uint32_t SIM_TIMING : 1; /*!< Reduced timings for simulation */ + } bit; + } MAIN_CTRL; + + union { + __IOM uint32_t reg; /*!< Set the SOF (Start of Frame) frame number in the host controller. + The SOF packet is sent every 1ms and the host will increment + the frame number by 1 each time. */ + + struct { + __OM uint32_t COUNT : 11; /*!< COUNT */ + uint32_t : 21; + } bit; + } SOF_WR; + + union { + __IOM uint32_t reg; /*!< Read the last SOF (Start of Frame) frame number seen. In device + mode the last SOF received from the host. In host mode + the last SOF sent by the host. */ + + struct { + __IM uint32_t COUNT : 11; /*!< COUNT */ + uint32_t : 21; + } bit; + } SOF_RD; + + union { + __IOM uint32_t reg; /*!< SIE control register */ + + struct { + __OM uint32_t START_TRANS : 1; /*!< Host: Start transaction */ + __IOM uint32_t SEND_SETUP : 1; /*!< Host: Send Setup packet */ + __IOM uint32_t SEND_DATA : 1; /*!< Host: Send transaction (OUT from host) */ + __IOM uint32_t RECEIVE_DATA : 1; /*!< Host: Receive transaction (IN to host) */ + __OM uint32_t STOP_TRANS : 1; /*!< Host: Stop transaction */ + uint32_t : 1; + __IOM uint32_t PREAMBLE_EN : 1; /*!< Host: Preable enable for LS device on FS hub */ + uint32_t : 1; + __IOM uint32_t SOF_SYNC : 1; /*!< Host: Delay packet(s) until after SOF */ + __IOM uint32_t SOF_EN : 1; /*!< Host: Enable SOF generation (for full speed bus) */ + __IOM uint32_t KEEP_ALIVE_EN : 1; /*!< Host: Enable keep alive packet (for low speed bus) */ + __IOM uint32_t VBUS_EN : 1; /*!< Host: Enable VBUS */ + __OM uint32_t RESUME : 1; /*!< Device: Remote wakeup. Device can initiate its own resume after + suspend. */ + __OM uint32_t RESET_BUS : 1; /*!< Host: Reset bus */ + uint32_t : 1; + __IOM uint32_t PULLDOWN_EN : 1; /*!< Host: Enable pull down resistors */ + __IOM uint32_t PULLUP_EN : 1; /*!< Device: Enable pull up resistor */ + __IOM uint32_t RPU_OPT : 1; /*!< Device: Pull-up strength (0=1K2, 1=2k3) */ + __IOM uint32_t TRANSCEIVER_PD : 1; /*!< Power down bus transceiver */ + __IOM uint32_t EP0_STOP_ON_SHORT_PACKET : 1;/*!< Device: Stop EP0 on a short packet. */ + uint32_t : 4; + __IOM uint32_t DIRECT_DM : 1; /*!< Direct control of DM */ + __IOM uint32_t DIRECT_DP : 1; /*!< Direct control of DP */ + __IOM uint32_t DIRECT_EN : 1; /*!< Direct bus drive enable */ + __IOM uint32_t EP0_INT_NAK : 1; /*!< Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK */ + __IOM uint32_t EP0_INT_2BUF : 1; /*!< Device: Set bit in BUFF_STATUS for every 2 buffers completed + on EP0 */ + __IOM uint32_t EP0_INT_1BUF : 1; /*!< Device: Set bit in BUFF_STATUS for every buffer completed on + EP0 */ + __IOM uint32_t EP0_DOUBLE_BUF : 1; /*!< Device: EP0 single buffered = 0, double buffered = 1 */ + __IOM uint32_t EP0_INT_STALL : 1; /*!< Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL */ + } bit; + } SIE_CTRL; + + union { + __IOM uint32_t reg; /*!< SIE status register */ + + struct { + __IM uint32_t VBUS_DETECTED : 1; /*!< Device: VBUS Detected */ + uint32_t : 1; + __IM uint32_t LINE_STATE : 2; /*!< USB bus line state */ + __IOM uint32_t SUSPENDED : 1; /*!< Bus in suspended state. Valid for device. Device will go into + suspend if neither Keep Alive / SOF frames are enabled. */ + uint32_t : 3; + __IM uint32_t SPEED : 2; /*!< Host: device speed. Disconnected = 00, LS = 01, FS = 10 */ + __IM uint32_t VBUS_OVER_CURR : 1; /*!< VBUS over current detected */ + __IOM uint32_t RESUME : 1; /*!< Host: Device has initiated a remote resume. Device: host has + initiated a resume. */ + __IOM uint32_t RX_SHORT_PACKET : 1; /*!< Device or Host has received a short packet. This is when the + data received is less than configured in the buffer control + register. Device: If using double buffered mode on device + the buffer select will not be toggled after writing status + back to the buffer control register. This is to prevent + any further transactions on that endpoint until the user + has reset the buffer control registers. Host: the current + transfer will be stopped early. */ + uint32_t : 3; + __IM uint32_t CONNECTED : 1; /*!< Device: connected */ + __IOM uint32_t SETUP_REC : 1; /*!< Device: Setup packet received */ + __IOM uint32_t TRANS_COMPLETE : 1; /*!< Transaction complete. Raised by device if: * An IN or OUT packet + is sent with the `LAST_BUFF` bit set in the buffer control + register Raised by host if: * A setup packet is sent when + no data in or data out transaction follows * An IN packet + is received and the `LAST_BUFF` bit is set in the buffer + control register * An IN packet is received with zero length + * An OUT packet is sent and the `LAST_BUFF` bit is set */ + __IOM uint32_t BUS_RESET : 1; /*!< Device: bus reset received */ + uint32_t : 3; + __IOM uint32_t ENDPOINT_ERROR : 1; /*!< An endpoint has encountered an error. Read the ep_rx_error and + ep_tx_error registers to find out which endpoint had an + error. */ + __IOM uint32_t CRC_ERROR : 1; /*!< CRC Error. Raised by the Serial RX engine. */ + __IOM uint32_t BIT_STUFF_ERROR : 1; /*!< Bit Stuff Error. Raised by the Serial RX engine. */ + __IOM uint32_t RX_OVERFLOW : 1; /*!< RX overflow is raised by the Serial RX engine if the incoming + data is too fast. */ + __IOM uint32_t RX_TIMEOUT : 1; /*!< RX timeout is raised by both the host and device if an ACK is + not received in the maximum time specified by the USB spec. */ + __IOM uint32_t NAK_REC : 1; /*!< Host: NAK received */ + __IOM uint32_t STALL_REC : 1; /*!< Host: STALL received */ + __IOM uint32_t ACK_REC : 1; /*!< ACK received. Raised by both host and device. */ + __IOM uint32_t DATA_SEQ_ERROR : 1; /*!< Data Sequence Error. The device can raise a sequence error in + the following conditions: * A SETUP packet is received + followed by a DATA1 packet (data phase should always be + DATA0) * An OUT packet is received from the host but doesn't + match the data pid in the buffer control register read + from DPSRAM The host can raise a data sequence error in + the following conditions: * An IN packet from the device + has the wrong data PID */ + } bit; + } SIE_STATUS; + + union { + __IOM uint32_t reg; /*!< interrupt endpoint control register */ + + struct { + uint32_t : 1; + __IOM uint32_t INT_EP_ACTIVE : 15; /*!< Host: Enable interrupt endpoint 1 -> 15 */ + uint32_t : 16; + } bit; + } INT_EP_CTRL; + + union { + __IOM uint32_t reg; /*!< Buffer status register. A bit set here indicates that a buffer + has completed on the endpoint (if the buffer interrupt + is enabled). It is possible for 2 buffers to be completed, + so clearing the buffer status bit may instantly re set + it on the next clock cycle. */ + + struct { + __IOM uint32_t EP0_IN : 1; /*!< EP0_IN */ + __IOM uint32_t EP0_OUT : 1; /*!< EP0_OUT */ + __IOM uint32_t EP1_IN : 1; /*!< EP1_IN */ + __IOM uint32_t EP1_OUT : 1; /*!< EP1_OUT */ + __IOM uint32_t EP2_IN : 1; /*!< EP2_IN */ + __IOM uint32_t EP2_OUT : 1; /*!< EP2_OUT */ + __IOM uint32_t EP3_IN : 1; /*!< EP3_IN */ + __IOM uint32_t EP3_OUT : 1; /*!< EP3_OUT */ + __IOM uint32_t EP4_IN : 1; /*!< EP4_IN */ + __IOM uint32_t EP4_OUT : 1; /*!< EP4_OUT */ + __IOM uint32_t EP5_IN : 1; /*!< EP5_IN */ + __IOM uint32_t EP5_OUT : 1; /*!< EP5_OUT */ + __IOM uint32_t EP6_IN : 1; /*!< EP6_IN */ + __IOM uint32_t EP6_OUT : 1; /*!< EP6_OUT */ + __IOM uint32_t EP7_IN : 1; /*!< EP7_IN */ + __IOM uint32_t EP7_OUT : 1; /*!< EP7_OUT */ + __IOM uint32_t EP8_IN : 1; /*!< EP8_IN */ + __IOM uint32_t EP8_OUT : 1; /*!< EP8_OUT */ + __IOM uint32_t EP9_IN : 1; /*!< EP9_IN */ + __IOM uint32_t EP9_OUT : 1; /*!< EP9_OUT */ + __IOM uint32_t EP10_IN : 1; /*!< EP10_IN */ + __IOM uint32_t EP10_OUT : 1; /*!< EP10_OUT */ + __IOM uint32_t EP11_IN : 1; /*!< EP11_IN */ + __IOM uint32_t EP11_OUT : 1; /*!< EP11_OUT */ + __IOM uint32_t EP12_IN : 1; /*!< EP12_IN */ + __IOM uint32_t EP12_OUT : 1; /*!< EP12_OUT */ + __IOM uint32_t EP13_IN : 1; /*!< EP13_IN */ + __IOM uint32_t EP13_OUT : 1; /*!< EP13_OUT */ + __IOM uint32_t EP14_IN : 1; /*!< EP14_IN */ + __IOM uint32_t EP14_OUT : 1; /*!< EP14_OUT */ + __IOM uint32_t EP15_IN : 1; /*!< EP15_IN */ + __IOM uint32_t EP15_OUT : 1; /*!< EP15_OUT */ + } bit; + } BUFF_STATUS; + + union { + __IOM uint32_t reg; /*!< Which of the double buffers should be handled. Only valid if + using an interrupt per buffer (i.e. not per 2 buffers). + Not valid for host interrupt endpoint polling because they + are only single buffered. */ + + struct { + __IM uint32_t EP0_IN : 1; /*!< EP0_IN */ + __IM uint32_t EP0_OUT : 1; /*!< EP0_OUT */ + __IM uint32_t EP1_IN : 1; /*!< EP1_IN */ + __IM uint32_t EP1_OUT : 1; /*!< EP1_OUT */ + __IM uint32_t EP2_IN : 1; /*!< EP2_IN */ + __IM uint32_t EP2_OUT : 1; /*!< EP2_OUT */ + __IM uint32_t EP3_IN : 1; /*!< EP3_IN */ + __IM uint32_t EP3_OUT : 1; /*!< EP3_OUT */ + __IM uint32_t EP4_IN : 1; /*!< EP4_IN */ + __IM uint32_t EP4_OUT : 1; /*!< EP4_OUT */ + __IM uint32_t EP5_IN : 1; /*!< EP5_IN */ + __IM uint32_t EP5_OUT : 1; /*!< EP5_OUT */ + __IM uint32_t EP6_IN : 1; /*!< EP6_IN */ + __IM uint32_t EP6_OUT : 1; /*!< EP6_OUT */ + __IM uint32_t EP7_IN : 1; /*!< EP7_IN */ + __IM uint32_t EP7_OUT : 1; /*!< EP7_OUT */ + __IM uint32_t EP8_IN : 1; /*!< EP8_IN */ + __IM uint32_t EP8_OUT : 1; /*!< EP8_OUT */ + __IM uint32_t EP9_IN : 1; /*!< EP9_IN */ + __IM uint32_t EP9_OUT : 1; /*!< EP9_OUT */ + __IM uint32_t EP10_IN : 1; /*!< EP10_IN */ + __IM uint32_t EP10_OUT : 1; /*!< EP10_OUT */ + __IM uint32_t EP11_IN : 1; /*!< EP11_IN */ + __IM uint32_t EP11_OUT : 1; /*!< EP11_OUT */ + __IM uint32_t EP12_IN : 1; /*!< EP12_IN */ + __IM uint32_t EP12_OUT : 1; /*!< EP12_OUT */ + __IM uint32_t EP13_IN : 1; /*!< EP13_IN */ + __IM uint32_t EP13_OUT : 1; /*!< EP13_OUT */ + __IM uint32_t EP14_IN : 1; /*!< EP14_IN */ + __IM uint32_t EP14_OUT : 1; /*!< EP14_OUT */ + __IM uint32_t EP15_IN : 1; /*!< EP15_IN */ + __IM uint32_t EP15_OUT : 1; /*!< EP15_OUT */ + } bit; + } BUFF_CPU_SHOULD_HANDLE; + + union { + __IOM uint32_t reg; /*!< Device only: Can be set to ignore the buffer control register + for this endpoint in case you would like to revoke a buffer. + A NAK will be sent for every access to the endpoint until + this bit is cleared. A corresponding bit in `EP_ABORT_DONE` + is set when it is safe to modify the buffer control register. */ + + struct { + __IOM uint32_t EP0_IN : 1; /*!< EP0_IN */ + __IOM uint32_t EP0_OUT : 1; /*!< EP0_OUT */ + __IOM uint32_t EP1_IN : 1; /*!< EP1_IN */ + __IOM uint32_t EP1_OUT : 1; /*!< EP1_OUT */ + __IOM uint32_t EP2_IN : 1; /*!< EP2_IN */ + __IOM uint32_t EP2_OUT : 1; /*!< EP2_OUT */ + __IOM uint32_t EP3_IN : 1; /*!< EP3_IN */ + __IOM uint32_t EP3_OUT : 1; /*!< EP3_OUT */ + __IOM uint32_t EP4_IN : 1; /*!< EP4_IN */ + __IOM uint32_t EP4_OUT : 1; /*!< EP4_OUT */ + __IOM uint32_t EP5_IN : 1; /*!< EP5_IN */ + __IOM uint32_t EP5_OUT : 1; /*!< EP5_OUT */ + __IOM uint32_t EP6_IN : 1; /*!< EP6_IN */ + __IOM uint32_t EP6_OUT : 1; /*!< EP6_OUT */ + __IOM uint32_t EP7_IN : 1; /*!< EP7_IN */ + __IOM uint32_t EP7_OUT : 1; /*!< EP7_OUT */ + __IOM uint32_t EP8_IN : 1; /*!< EP8_IN */ + __IOM uint32_t EP8_OUT : 1; /*!< EP8_OUT */ + __IOM uint32_t EP9_IN : 1; /*!< EP9_IN */ + __IOM uint32_t EP9_OUT : 1; /*!< EP9_OUT */ + __IOM uint32_t EP10_IN : 1; /*!< EP10_IN */ + __IOM uint32_t EP10_OUT : 1; /*!< EP10_OUT */ + __IOM uint32_t EP11_IN : 1; /*!< EP11_IN */ + __IOM uint32_t EP11_OUT : 1; /*!< EP11_OUT */ + __IOM uint32_t EP12_IN : 1; /*!< EP12_IN */ + __IOM uint32_t EP12_OUT : 1; /*!< EP12_OUT */ + __IOM uint32_t EP13_IN : 1; /*!< EP13_IN */ + __IOM uint32_t EP13_OUT : 1; /*!< EP13_OUT */ + __IOM uint32_t EP14_IN : 1; /*!< EP14_IN */ + __IOM uint32_t EP14_OUT : 1; /*!< EP14_OUT */ + __IOM uint32_t EP15_IN : 1; /*!< EP15_IN */ + __IOM uint32_t EP15_OUT : 1; /*!< EP15_OUT */ + } bit; + } EP_ABORT; + + union { + __IOM uint32_t reg; /*!< Device only: Used in conjunction with `EP_ABORT`. Set once an + endpoint is idle so the programmer knows it is safe to + modify the buffer control register. */ + + struct { + __IOM uint32_t EP0_IN : 1; /*!< EP0_IN */ + __IOM uint32_t EP0_OUT : 1; /*!< EP0_OUT */ + __IOM uint32_t EP1_IN : 1; /*!< EP1_IN */ + __IOM uint32_t EP1_OUT : 1; /*!< EP1_OUT */ + __IOM uint32_t EP2_IN : 1; /*!< EP2_IN */ + __IOM uint32_t EP2_OUT : 1; /*!< EP2_OUT */ + __IOM uint32_t EP3_IN : 1; /*!< EP3_IN */ + __IOM uint32_t EP3_OUT : 1; /*!< EP3_OUT */ + __IOM uint32_t EP4_IN : 1; /*!< EP4_IN */ + __IOM uint32_t EP4_OUT : 1; /*!< EP4_OUT */ + __IOM uint32_t EP5_IN : 1; /*!< EP5_IN */ + __IOM uint32_t EP5_OUT : 1; /*!< EP5_OUT */ + __IOM uint32_t EP6_IN : 1; /*!< EP6_IN */ + __IOM uint32_t EP6_OUT : 1; /*!< EP6_OUT */ + __IOM uint32_t EP7_IN : 1; /*!< EP7_IN */ + __IOM uint32_t EP7_OUT : 1; /*!< EP7_OUT */ + __IOM uint32_t EP8_IN : 1; /*!< EP8_IN */ + __IOM uint32_t EP8_OUT : 1; /*!< EP8_OUT */ + __IOM uint32_t EP9_IN : 1; /*!< EP9_IN */ + __IOM uint32_t EP9_OUT : 1; /*!< EP9_OUT */ + __IOM uint32_t EP10_IN : 1; /*!< EP10_IN */ + __IOM uint32_t EP10_OUT : 1; /*!< EP10_OUT */ + __IOM uint32_t EP11_IN : 1; /*!< EP11_IN */ + __IOM uint32_t EP11_OUT : 1; /*!< EP11_OUT */ + __IOM uint32_t EP12_IN : 1; /*!< EP12_IN */ + __IOM uint32_t EP12_OUT : 1; /*!< EP12_OUT */ + __IOM uint32_t EP13_IN : 1; /*!< EP13_IN */ + __IOM uint32_t EP13_OUT : 1; /*!< EP13_OUT */ + __IOM uint32_t EP14_IN : 1; /*!< EP14_IN */ + __IOM uint32_t EP14_OUT : 1; /*!< EP14_OUT */ + __IOM uint32_t EP15_IN : 1; /*!< EP15_IN */ + __IOM uint32_t EP15_OUT : 1; /*!< EP15_OUT */ + } bit; + } EP_ABORT_DONE; + + union { + __IOM uint32_t reg; /*!< Device: this bit must be set in conjunction with the `STALL` + bit in the buffer control register to send a STALL on EP0. + The device controller clears these bits when a SETUP packet + is received because the USB spec requires that a STALL + condition is cleared when a SETUP packet is received. */ + + struct { + __IOM uint32_t EP0_IN : 1; /*!< EP0_IN */ + __IOM uint32_t EP0_OUT : 1; /*!< EP0_OUT */ + uint32_t : 30; + } bit; + } EP_STALL_ARM; + + union { + __IOM uint32_t reg; /*!< Used by the host controller. Sets the wait time in microseconds + before trying again if the device replies with a NAK. */ + + struct { + __IOM uint32_t DELAY_LS : 10; /*!< NAK polling interval for a low speed device */ + __IM uint32_t RETRY_COUNT_LO : 6; /*!< Bits 5:0 of nak_retry_count */ + __IOM uint32_t DELAY_FS : 10; /*!< NAK polling interval for a full speed device */ + __IOM uint32_t STOP_EPX_ON_NAK : 1; /*!< Stop polling epx when a nak is received */ + __IOM uint32_t EPX_STOPPED_ON_NAK : 1; /*!< EPX polling has stopped because a nak was received */ + __IM uint32_t RETRY_COUNT_HI : 4; /*!< Bits 9:6 of nak_retry count */ + } bit; + } NAK_POLL; + + union { + __IOM uint32_t reg; /*!< Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` + bits are set. For EP0 this comes from `SIE_CTRL`. For all + other endpoints it comes from the endpoint control register. */ + + struct { + __IOM uint32_t EP0_IN : 1; /*!< EP0_IN */ + __IOM uint32_t EP0_OUT : 1; /*!< EP0_OUT */ + __IOM uint32_t EP1_IN : 1; /*!< EP1_IN */ + __IOM uint32_t EP1_OUT : 1; /*!< EP1_OUT */ + __IOM uint32_t EP2_IN : 1; /*!< EP2_IN */ + __IOM uint32_t EP2_OUT : 1; /*!< EP2_OUT */ + __IOM uint32_t EP3_IN : 1; /*!< EP3_IN */ + __IOM uint32_t EP3_OUT : 1; /*!< EP3_OUT */ + __IOM uint32_t EP4_IN : 1; /*!< EP4_IN */ + __IOM uint32_t EP4_OUT : 1; /*!< EP4_OUT */ + __IOM uint32_t EP5_IN : 1; /*!< EP5_IN */ + __IOM uint32_t EP5_OUT : 1; /*!< EP5_OUT */ + __IOM uint32_t EP6_IN : 1; /*!< EP6_IN */ + __IOM uint32_t EP6_OUT : 1; /*!< EP6_OUT */ + __IOM uint32_t EP7_IN : 1; /*!< EP7_IN */ + __IOM uint32_t EP7_OUT : 1; /*!< EP7_OUT */ + __IOM uint32_t EP8_IN : 1; /*!< EP8_IN */ + __IOM uint32_t EP8_OUT : 1; /*!< EP8_OUT */ + __IOM uint32_t EP9_IN : 1; /*!< EP9_IN */ + __IOM uint32_t EP9_OUT : 1; /*!< EP9_OUT */ + __IOM uint32_t EP10_IN : 1; /*!< EP10_IN */ + __IOM uint32_t EP10_OUT : 1; /*!< EP10_OUT */ + __IOM uint32_t EP11_IN : 1; /*!< EP11_IN */ + __IOM uint32_t EP11_OUT : 1; /*!< EP11_OUT */ + __IOM uint32_t EP12_IN : 1; /*!< EP12_IN */ + __IOM uint32_t EP12_OUT : 1; /*!< EP12_OUT */ + __IOM uint32_t EP13_IN : 1; /*!< EP13_IN */ + __IOM uint32_t EP13_OUT : 1; /*!< EP13_OUT */ + __IOM uint32_t EP14_IN : 1; /*!< EP14_IN */ + __IOM uint32_t EP14_OUT : 1; /*!< EP14_OUT */ + __IOM uint32_t EP15_IN : 1; /*!< EP15_IN */ + __IOM uint32_t EP15_OUT : 1; /*!< EP15_OUT */ + } bit; + } EP_STATUS_STALL_NAK; + + union { + __IOM uint32_t reg; /*!< Where to connect the USB controller. Should be to_phy by default. */ + + struct { + __IOM uint32_t TO_PHY : 1; /*!< TO_PHY */ + __IOM uint32_t TO_EXTPHY : 1; /*!< TO_EXTPHY */ + __IOM uint32_t TO_DIGITAL_PAD : 1; /*!< TO_DIGITAL_PAD */ + __IOM uint32_t SOFTCON : 1; /*!< SOFTCON */ + __IOM uint32_t USBPHY_AS_GPIO : 1; /*!< Use the usb DP and DM pins as GPIO pins instead of connecting + them to the USB controller. */ + uint32_t : 26; + __IOM uint32_t SWAP_DPDM : 1; /*!< Swap the USB PHY DP and DM pins and all related controls and + flip receive differential data. Can be used to switch USB + DP/DP on the PCB. This is done at a low level so overrides + all other controls. */ + } bit; + } USB_MUXING; + + union { + __IOM uint32_t reg; /*!< Overrides for the power signals in the event that the VBUS signals + are not hooked up to GPIO. Set the value of the override + and then the override enable to switch over to the override + value. */ + + struct { + __IOM uint32_t VBUS_EN : 1; /*!< VBUS_EN */ + __IOM uint32_t VBUS_EN_OVERRIDE_EN : 1; /*!< VBUS_EN_OVERRIDE_EN */ + __IOM uint32_t VBUS_DETECT : 1; /*!< VBUS_DETECT */ + __IOM uint32_t VBUS_DETECT_OVERRIDE_EN : 1;/*!< VBUS_DETECT_OVERRIDE_EN */ + __IOM uint32_t OVERCURR_DETECT : 1; /*!< OVERCURR_DETECT */ + __IOM uint32_t OVERCURR_DETECT_EN : 1; /*!< OVERCURR_DETECT_EN */ + uint32_t : 26; + } bit; + } USB_PWR; + + union { + __IOM uint32_t reg; /*!< This register allows for direct control of the USB phy. Use + in conjunction with usbphy_direct_override register to + enable each override bit. */ + + struct { + __IOM uint32_t DP_PULLUP_HISEL : 1; /*!< Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - + Pull = Rpu1 + Rpu2 */ + __IOM uint32_t DP_PULLUP_EN : 1; /*!< DP pull up enable */ + __IOM uint32_t DP_PULLDN_EN : 1; /*!< DP pull down enable */ + uint32_t : 1; + __IOM uint32_t DM_PULLUP_HISEL : 1; /*!< Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - + Pull = Rpu1 + Rpu2 */ + __IOM uint32_t DM_PULLUP_EN : 1; /*!< DM pull up enable */ + __IOM uint32_t DM_PULLDN_EN : 1; /*!< DM pull down enable */ + uint32_t : 1; + __IOM uint32_t TX_DP_OE : 1; /*!< Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 + - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, + OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving */ + __IOM uint32_t TX_DM_OE : 1; /*!< Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, + OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving */ + __IOM uint32_t TX_DP : 1; /*!< Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 + to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, + Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP */ + __IOM uint32_t TX_DM : 1; /*!< Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM + only. TX_DM_OE=1 to enable drive. DPM=TX_DM */ + __IOM uint32_t RX_PD : 1; /*!< RX power down override (if override enable is set). 1 = powered + down. */ + __IOM uint32_t TX_PD : 1; /*!< TX power down override (if override enable is set). 1 = powered + down. */ + __IOM uint32_t TX_FSSLEW : 1; /*!< TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew + rate */ + __IOM uint32_t TX_DIFFMODE : 1; /*!< TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential + drive mode (TX_DM, TX_DM_OE ignored) */ + __IM uint32_t RX_DD : 1; /*!< Differential RX */ + __IM uint32_t RX_DP : 1; /*!< DPP pin state */ + __IM uint32_t RX_DM : 1; /*!< DPM pin state */ + __IM uint32_t DP_OVCN : 1; /*!< DP overcurrent */ + __IM uint32_t DM_OVCN : 1; /*!< DM overcurrent */ + __IM uint32_t DP_OVV : 1; /*!< DP over voltage */ + __IM uint32_t DM_OVV : 1; /*!< DM over voltage */ + __IOM uint32_t RX_DD_OVERRIDE : 1; /*!< Override rx_dd value into controller */ + __IOM uint32_t RX_DP_OVERRIDE : 1; /*!< Override rx_dp value into controller */ + __IOM uint32_t RX_DM_OVERRIDE : 1; /*!< Override rx_dm value into controller */ + uint32_t : 6; + } bit; + } USBPHY_DIRECT; + + union { + __IOM uint32_t reg; /*!< Override enable for each control in usbphy_direct */ + + struct { + __IOM uint32_t DP_PULLUP_HISEL_OVERRIDE_EN : 1;/*!< DP_PULLUP_HISEL_OVERRIDE_EN */ + __IOM uint32_t DM_PULLUP_HISEL_OVERRIDE_EN : 1;/*!< DM_PULLUP_HISEL_OVERRIDE_EN */ + __IOM uint32_t DP_PULLUP_EN_OVERRIDE_EN : 1;/*!< DP_PULLUP_EN_OVERRIDE_EN */ + __IOM uint32_t DP_PULLDN_EN_OVERRIDE_EN : 1;/*!< DP_PULLDN_EN_OVERRIDE_EN */ + __IOM uint32_t DM_PULLDN_EN_OVERRIDE_EN : 1;/*!< DM_PULLDN_EN_OVERRIDE_EN */ + __IOM uint32_t TX_DP_OE_OVERRIDE_EN : 1; /*!< TX_DP_OE_OVERRIDE_EN */ + __IOM uint32_t TX_DM_OE_OVERRIDE_EN : 1; /*!< TX_DM_OE_OVERRIDE_EN */ + __IOM uint32_t TX_DP_OVERRIDE_EN : 1; /*!< TX_DP_OVERRIDE_EN */ + __IOM uint32_t TX_DM_OVERRIDE_EN : 1; /*!< TX_DM_OVERRIDE_EN */ + __IOM uint32_t RX_PD_OVERRIDE_EN : 1; /*!< RX_PD_OVERRIDE_EN */ + __IOM uint32_t TX_PD_OVERRIDE_EN : 1; /*!< TX_PD_OVERRIDE_EN */ + __IOM uint32_t TX_FSSLEW_OVERRIDE_EN : 1; /*!< TX_FSSLEW_OVERRIDE_EN */ + __IOM uint32_t DM_PULLUP_OVERRIDE_EN : 1; /*!< DM_PULLUP_OVERRIDE_EN */ + uint32_t : 2; + __IOM uint32_t TX_DIFFMODE_OVERRIDE_EN : 1;/*!< TX_DIFFMODE_OVERRIDE_EN */ + __IOM uint32_t RX_DD_OVERRIDE_EN : 1; /*!< RX_DD_OVERRIDE_EN */ + __IOM uint32_t RX_DP_OVERRIDE_EN : 1; /*!< RX_DP_OVERRIDE_EN */ + __IOM uint32_t RX_DM_OVERRIDE_EN : 1; /*!< RX_DM_OVERRIDE_EN */ + uint32_t : 13; + } bit; + } USBPHY_DIRECT_OVERRIDE; + + union { + __IOM uint32_t reg; /*!< Used to adjust trim values of USB phy pull down resistors. */ + + struct { + __IOM uint32_t DP_PULLDN_TRIM : 5; /*!< Value to drive to USB PHY DP pulldown resistor trim control + Experimental data suggests that the reset value will work, + but this register allows adjustment if required */ + uint32_t : 3; + __IOM uint32_t DM_PULLDN_TRIM : 5; /*!< Value to drive to USB PHY DM pulldown resistor trim control + Experimental data suggests that the reset value will work, + but this register allows adjustment if required */ + uint32_t : 19; + } bit; + } USBPHY_TRIM; + + union { + __IOM uint32_t reg; /*!< Used for debug only. */ + + struct { + __IOM uint32_t RCV_DELAY : 1; /*!< Device - register the received data to account for hub bit dribble + before EOP. Only affects certain hubs. */ + __IOM uint32_t LINESTATE_DELAY : 1; /*!< Device/Host - add an extra 1-bit debounce of linestate sampling. */ + __IOM uint32_t MULTI_HUB_FIX : 1; /*!< Host - increase inter-packet and turnaround timeouts to accommodate + worst-case hub delays. */ + __IOM uint32_t DEV_BUFF_CONTROL_DOUBLE_READ_FIX : 1;/*!< Device - the controller FSM performs two reads of the buffer + status memory address to avoid sampling metastable data. + An enabled buffer is only used if both reads match. */ + __IOM uint32_t SIE_RX_BITSTUFF_FIX : 1; /*!< RX - when a bitstuff error is signalled by rx_dasm, unconditionally + terminate RX decode to avoid a hang during certain packet + phases. */ + __IOM uint32_t SIE_RX_CHATTER_SE0_FIX : 1;/*!< RX - when recovering from line chatter or bitstuff errors, treat + SE0 as the end of chatter as well as 8 consecutive idle + bits. */ + __IOM uint32_t DEV_RX_ERR_QUIESCE : 1; /*!< Device - suppress repeated errors until the device FSM is next + in the process of decoding an inbound packet. */ + __IOM uint32_t DEV_LS_WAKE_FIX : 1; /*!< Device - exit suspend on any non-idle signalling, not qualified + with a 1ms timer */ + __IOM uint32_t SPARE_FIX : 4; /*!< SPARE_FIX */ + uint32_t : 20; + } bit; + } LINESTATE_TUNING; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t HOST_CONN_DIS : 1; /*!< Host: raised when a device is connected or disconnected (i.e. + when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */ + __IM uint32_t HOST_RESUME : 1; /*!< Host: raised when a device wakes up the host. Cleared by writing + to SIE_STATUS.RESUME */ + __IM uint32_t HOST_SOF : 1; /*!< Host: raised every time the host sends a SOF (Start of Frame). + Cleared by reading SOF_RD */ + __IM uint32_t TRANS_COMPLETE : 1; /*!< Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by + writing to this bit. */ + __IM uint32_t BUFF_STATUS : 1; /*!< Raised when any bit in BUFF_STATUS is set. Clear by clearing + all bits in BUFF_STATUS. */ + __IM uint32_t ERROR_DATA_SEQ : 1; /*!< Source: SIE_STATUS.DATA_SEQ_ERROR */ + __IM uint32_t ERROR_RX_TIMEOUT : 1; /*!< Source: SIE_STATUS.RX_TIMEOUT */ + __IM uint32_t ERROR_RX_OVERFLOW : 1; /*!< Source: SIE_STATUS.RX_OVERFLOW */ + __IM uint32_t ERROR_BIT_STUFF : 1; /*!< Source: SIE_STATUS.BIT_STUFF_ERROR */ + __IM uint32_t ERROR_CRC : 1; /*!< Source: SIE_STATUS.CRC_ERROR */ + __IM uint32_t STALL : 1; /*!< Source: SIE_STATUS.STALL_REC */ + __IM uint32_t VBUS_DETECT : 1; /*!< Source: SIE_STATUS.VBUS_DETECTED */ + __IM uint32_t BUS_RESET : 1; /*!< Source: SIE_STATUS.BUS_RESET */ + __IM uint32_t DEV_CONN_DIS : 1; /*!< Set when the device connection state changes. Cleared by writing + to SIE_STATUS.CONNECTED */ + __IM uint32_t DEV_SUSPEND : 1; /*!< Set when the device suspend state changes. Cleared by writing + to SIE_STATUS.SUSPENDED */ + __IM uint32_t DEV_RESUME_FROM_HOST : 1; /*!< Set when the device receives a resume from the host. Cleared + by writing to SIE_STATUS.RESUME */ + __IM uint32_t SETUP_REQ : 1; /*!< Device. Source: SIE_STATUS.SETUP_REC */ + __IM uint32_t DEV_SOF : 1; /*!< Set every time the device receives a SOF (Start of Frame) packet. + Cleared by reading SOF_RD */ + __IM uint32_t ABORT_DONE : 1; /*!< Raised when any bit in ABORT_DONE is set. Clear by clearing + all bits in ABORT_DONE. */ + __IM uint32_t EP_STALL_NAK : 1; /*!< Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by + clearing all bits in EP_STATUS_STALL_NAK. */ + __IM uint32_t RX_SHORT_PACKET : 1; /*!< Source: SIE_STATUS.RX_SHORT_PACKET */ + __IM uint32_t ENDPOINT_ERROR : 1; /*!< Source: SIE_STATUS.ENDPOINT_ERROR */ + __IM uint32_t DEV_SM_WATCHDOG_FIRED : 1; /*!< Source: DEV_SM_WATCHDOG.FIRED */ + __IM uint32_t EPX_STOPPED_ON_NAK : 1; /*!< Source: NAK_POLL.EPX_STOPPED_ON_NAK */ + uint32_t : 8; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable */ + + struct { + __IOM uint32_t HOST_CONN_DIS : 1; /*!< Host: raised when a device is connected or disconnected (i.e. + when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */ + __IOM uint32_t HOST_RESUME : 1; /*!< Host: raised when a device wakes up the host. Cleared by writing + to SIE_STATUS.RESUME */ + __IOM uint32_t HOST_SOF : 1; /*!< Host: raised every time the host sends a SOF (Start of Frame). + Cleared by reading SOF_RD */ + __IOM uint32_t TRANS_COMPLETE : 1; /*!< Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by + writing to this bit. */ + __IOM uint32_t BUFF_STATUS : 1; /*!< Raised when any bit in BUFF_STATUS is set. Clear by clearing + all bits in BUFF_STATUS. */ + __IOM uint32_t ERROR_DATA_SEQ : 1; /*!< Source: SIE_STATUS.DATA_SEQ_ERROR */ + __IOM uint32_t ERROR_RX_TIMEOUT : 1; /*!< Source: SIE_STATUS.RX_TIMEOUT */ + __IOM uint32_t ERROR_RX_OVERFLOW : 1; /*!< Source: SIE_STATUS.RX_OVERFLOW */ + __IOM uint32_t ERROR_BIT_STUFF : 1; /*!< Source: SIE_STATUS.BIT_STUFF_ERROR */ + __IOM uint32_t ERROR_CRC : 1; /*!< Source: SIE_STATUS.CRC_ERROR */ + __IOM uint32_t STALL : 1; /*!< Source: SIE_STATUS.STALL_REC */ + __IOM uint32_t VBUS_DETECT : 1; /*!< Source: SIE_STATUS.VBUS_DETECTED */ + __IOM uint32_t BUS_RESET : 1; /*!< Source: SIE_STATUS.BUS_RESET */ + __IOM uint32_t DEV_CONN_DIS : 1; /*!< Set when the device connection state changes. Cleared by writing + to SIE_STATUS.CONNECTED */ + __IOM uint32_t DEV_SUSPEND : 1; /*!< Set when the device suspend state changes. Cleared by writing + to SIE_STATUS.SUSPENDED */ + __IOM uint32_t DEV_RESUME_FROM_HOST : 1; /*!< Set when the device receives a resume from the host. Cleared + by writing to SIE_STATUS.RESUME */ + __IOM uint32_t SETUP_REQ : 1; /*!< Device. Source: SIE_STATUS.SETUP_REC */ + __IOM uint32_t DEV_SOF : 1; /*!< Set every time the device receives a SOF (Start of Frame) packet. + Cleared by reading SOF_RD */ + __IOM uint32_t ABORT_DONE : 1; /*!< Raised when any bit in ABORT_DONE is set. Clear by clearing + all bits in ABORT_DONE. */ + __IOM uint32_t EP_STALL_NAK : 1; /*!< Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by + clearing all bits in EP_STATUS_STALL_NAK. */ + __IOM uint32_t RX_SHORT_PACKET : 1; /*!< Source: SIE_STATUS.RX_SHORT_PACKET */ + __IOM uint32_t ENDPOINT_ERROR : 1; /*!< Source: SIE_STATUS.ENDPOINT_ERROR */ + __IOM uint32_t DEV_SM_WATCHDOG_FIRED : 1; /*!< Source: DEV_SM_WATCHDOG.FIRED */ + __IOM uint32_t EPX_STOPPED_ON_NAK : 1; /*!< Source: NAK_POLL.EPX_STOPPED_ON_NAK */ + uint32_t : 8; + } bit; + } INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force */ + + struct { + __IOM uint32_t HOST_CONN_DIS : 1; /*!< Host: raised when a device is connected or disconnected (i.e. + when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */ + __IOM uint32_t HOST_RESUME : 1; /*!< Host: raised when a device wakes up the host. Cleared by writing + to SIE_STATUS.RESUME */ + __IOM uint32_t HOST_SOF : 1; /*!< Host: raised every time the host sends a SOF (Start of Frame). + Cleared by reading SOF_RD */ + __IOM uint32_t TRANS_COMPLETE : 1; /*!< Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by + writing to this bit. */ + __IOM uint32_t BUFF_STATUS : 1; /*!< Raised when any bit in BUFF_STATUS is set. Clear by clearing + all bits in BUFF_STATUS. */ + __IOM uint32_t ERROR_DATA_SEQ : 1; /*!< Source: SIE_STATUS.DATA_SEQ_ERROR */ + __IOM uint32_t ERROR_RX_TIMEOUT : 1; /*!< Source: SIE_STATUS.RX_TIMEOUT */ + __IOM uint32_t ERROR_RX_OVERFLOW : 1; /*!< Source: SIE_STATUS.RX_OVERFLOW */ + __IOM uint32_t ERROR_BIT_STUFF : 1; /*!< Source: SIE_STATUS.BIT_STUFF_ERROR */ + __IOM uint32_t ERROR_CRC : 1; /*!< Source: SIE_STATUS.CRC_ERROR */ + __IOM uint32_t STALL : 1; /*!< Source: SIE_STATUS.STALL_REC */ + __IOM uint32_t VBUS_DETECT : 1; /*!< Source: SIE_STATUS.VBUS_DETECTED */ + __IOM uint32_t BUS_RESET : 1; /*!< Source: SIE_STATUS.BUS_RESET */ + __IOM uint32_t DEV_CONN_DIS : 1; /*!< Set when the device connection state changes. Cleared by writing + to SIE_STATUS.CONNECTED */ + __IOM uint32_t DEV_SUSPEND : 1; /*!< Set when the device suspend state changes. Cleared by writing + to SIE_STATUS.SUSPENDED */ + __IOM uint32_t DEV_RESUME_FROM_HOST : 1; /*!< Set when the device receives a resume from the host. Cleared + by writing to SIE_STATUS.RESUME */ + __IOM uint32_t SETUP_REQ : 1; /*!< Device. Source: SIE_STATUS.SETUP_REC */ + __IOM uint32_t DEV_SOF : 1; /*!< Set every time the device receives a SOF (Start of Frame) packet. + Cleared by reading SOF_RD */ + __IOM uint32_t ABORT_DONE : 1; /*!< Raised when any bit in ABORT_DONE is set. Clear by clearing + all bits in ABORT_DONE. */ + __IOM uint32_t EP_STALL_NAK : 1; /*!< Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by + clearing all bits in EP_STATUS_STALL_NAK. */ + __IOM uint32_t RX_SHORT_PACKET : 1; /*!< Source: SIE_STATUS.RX_SHORT_PACKET */ + __IOM uint32_t ENDPOINT_ERROR : 1; /*!< Source: SIE_STATUS.ENDPOINT_ERROR */ + __IOM uint32_t DEV_SM_WATCHDOG_FIRED : 1; /*!< Source: DEV_SM_WATCHDOG.FIRED */ + __IOM uint32_t EPX_STOPPED_ON_NAK : 1; /*!< Source: NAK_POLL.EPX_STOPPED_ON_NAK */ + uint32_t : 8; + } bit; + } INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing */ + + struct { + __IM uint32_t HOST_CONN_DIS : 1; /*!< Host: raised when a device is connected or disconnected (i.e. + when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */ + __IM uint32_t HOST_RESUME : 1; /*!< Host: raised when a device wakes up the host. Cleared by writing + to SIE_STATUS.RESUME */ + __IM uint32_t HOST_SOF : 1; /*!< Host: raised every time the host sends a SOF (Start of Frame). + Cleared by reading SOF_RD */ + __IM uint32_t TRANS_COMPLETE : 1; /*!< Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by + writing to this bit. */ + __IM uint32_t BUFF_STATUS : 1; /*!< Raised when any bit in BUFF_STATUS is set. Clear by clearing + all bits in BUFF_STATUS. */ + __IM uint32_t ERROR_DATA_SEQ : 1; /*!< Source: SIE_STATUS.DATA_SEQ_ERROR */ + __IM uint32_t ERROR_RX_TIMEOUT : 1; /*!< Source: SIE_STATUS.RX_TIMEOUT */ + __IM uint32_t ERROR_RX_OVERFLOW : 1; /*!< Source: SIE_STATUS.RX_OVERFLOW */ + __IM uint32_t ERROR_BIT_STUFF : 1; /*!< Source: SIE_STATUS.BIT_STUFF_ERROR */ + __IM uint32_t ERROR_CRC : 1; /*!< Source: SIE_STATUS.CRC_ERROR */ + __IM uint32_t STALL : 1; /*!< Source: SIE_STATUS.STALL_REC */ + __IM uint32_t VBUS_DETECT : 1; /*!< Source: SIE_STATUS.VBUS_DETECTED */ + __IM uint32_t BUS_RESET : 1; /*!< Source: SIE_STATUS.BUS_RESET */ + __IM uint32_t DEV_CONN_DIS : 1; /*!< Set when the device connection state changes. Cleared by writing + to SIE_STATUS.CONNECTED */ + __IM uint32_t DEV_SUSPEND : 1; /*!< Set when the device suspend state changes. Cleared by writing + to SIE_STATUS.SUSPENDED */ + __IM uint32_t DEV_RESUME_FROM_HOST : 1; /*!< Set when the device receives a resume from the host. Cleared + by writing to SIE_STATUS.RESUME */ + __IM uint32_t SETUP_REQ : 1; /*!< Device. Source: SIE_STATUS.SETUP_REC */ + __IM uint32_t DEV_SOF : 1; /*!< Set every time the device receives a SOF (Start of Frame) packet. + Cleared by reading SOF_RD */ + __IM uint32_t ABORT_DONE : 1; /*!< Raised when any bit in ABORT_DONE is set. Clear by clearing + all bits in ABORT_DONE. */ + __IM uint32_t EP_STALL_NAK : 1; /*!< Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by + clearing all bits in EP_STATUS_STALL_NAK. */ + __IM uint32_t RX_SHORT_PACKET : 1; /*!< Source: SIE_STATUS.RX_SHORT_PACKET */ + __IM uint32_t ENDPOINT_ERROR : 1; /*!< Source: SIE_STATUS.ENDPOINT_ERROR */ + __IM uint32_t DEV_SM_WATCHDOG_FIRED : 1; /*!< Source: DEV_SM_WATCHDOG.FIRED */ + __IM uint32_t EPX_STOPPED_ON_NAK : 1; /*!< Source: NAK_POLL.EPX_STOPPED_ON_NAK */ + uint32_t : 8; + } bit; + } INTS; + __IM uint32_t RESERVED[25]; + + union { + __IOM uint32_t reg; /*!< Device only. Raw value of free-running PHY clock counter @48MHz. + Used to calculate time between SOF events. */ + + struct { + __IM uint32_t SOF_TIMESTAMP_RAW : 21; /*!< SOF_TIMESTAMP_RAW */ + uint32_t : 11; + } bit; + } SOF_TIMESTAMP_RAW; + + union { + __IOM uint32_t reg; /*!< Device only. Value of free-running PHY clock counter @48MHz + when last SOF event occurred. */ + + struct { + __IM uint32_t SOF_TIMESTAMP_LAST : 21; /*!< SOF_TIMESTAMP_LAST */ + uint32_t : 11; + } bit; + } SOF_TIMESTAMP_LAST; + + union { + __IOM uint32_t reg; /*!< SM_STATE */ + + struct { + __IM uint32_t STATE : 5; /*!< STATE */ + __IM uint32_t BC_STATE : 3; /*!< BC_STATE */ + __IM uint32_t RX_DASM : 4; /*!< RX_DASM */ + uint32_t : 20; + } bit; + } SM_STATE; + + union { + __IOM uint32_t reg; /*!< TX error count for each endpoint. Write to each field to reset + the counter to 0. */ + + struct { + __IOM uint32_t EP0 : 2; /*!< EP0 */ + __IOM uint32_t EP1 : 2; /*!< EP1 */ + __IOM uint32_t EP2 : 2; /*!< EP2 */ + __IOM uint32_t EP3 : 2; /*!< EP3 */ + __IOM uint32_t EP4 : 2; /*!< EP4 */ + __IOM uint32_t EP5 : 2; /*!< EP5 */ + __IOM uint32_t EP6 : 2; /*!< EP6 */ + __IOM uint32_t EP7 : 2; /*!< EP7 */ + __IOM uint32_t EP8 : 2; /*!< EP8 */ + __IOM uint32_t EP9 : 2; /*!< EP9 */ + __IOM uint32_t EP10 : 2; /*!< EP10 */ + __IOM uint32_t EP11 : 2; /*!< EP11 */ + __IOM uint32_t EP12 : 2; /*!< EP12 */ + __IOM uint32_t EP13 : 2; /*!< EP13 */ + __IOM uint32_t EP14 : 2; /*!< EP14 */ + __IOM uint32_t EP15 : 2; /*!< EP15 */ + } bit; + } EP_TX_ERROR; + + union { + __IOM uint32_t reg; /*!< RX error count for each endpoint. Write to each field to reset + the counter to 0. */ + + struct { + __IOM uint32_t EP0_TRANSACTION : 1; /*!< EP0_TRANSACTION */ + __IOM uint32_t EP0_SEQ : 1; /*!< EP0_SEQ */ + __IOM uint32_t EP1_TRANSACTION : 1; /*!< EP1_TRANSACTION */ + __IOM uint32_t EP1_SEQ : 1; /*!< EP1_SEQ */ + __IOM uint32_t EP2_TRANSACTION : 1; /*!< EP2_TRANSACTION */ + __IOM uint32_t EP2_SEQ : 1; /*!< EP2_SEQ */ + __IOM uint32_t EP3_TRANSACTION : 1; /*!< EP3_TRANSACTION */ + __IOM uint32_t EP3_SEQ : 1; /*!< EP3_SEQ */ + __IOM uint32_t EP4_TRANSACTION : 1; /*!< EP4_TRANSACTION */ + __IOM uint32_t EP4_SEQ : 1; /*!< EP4_SEQ */ + __IOM uint32_t EP5_TRANSACTION : 1; /*!< EP5_TRANSACTION */ + __IOM uint32_t EP5_SEQ : 1; /*!< EP5_SEQ */ + __IOM uint32_t EP6_TRANSACTION : 1; /*!< EP6_TRANSACTION */ + __IOM uint32_t EP6_SEQ : 1; /*!< EP6_SEQ */ + __IOM uint32_t EP7_TRANSACTION : 1; /*!< EP7_TRANSACTION */ + __IOM uint32_t EP7_SEQ : 1; /*!< EP7_SEQ */ + __IOM uint32_t EP8_TRANSACTION : 1; /*!< EP8_TRANSACTION */ + __IOM uint32_t EP8_SEQ : 1; /*!< EP8_SEQ */ + __IOM uint32_t EP9_TRANSACTION : 1; /*!< EP9_TRANSACTION */ + __IOM uint32_t EP9_SEQ : 1; /*!< EP9_SEQ */ + __IOM uint32_t EP10_TRANSACTION : 1; /*!< EP10_TRANSACTION */ + __IOM uint32_t EP10_SEQ : 1; /*!< EP10_SEQ */ + __IOM uint32_t EP11_TRANSACTION : 1; /*!< EP11_TRANSACTION */ + __IOM uint32_t EP11_SEQ : 1; /*!< EP11_SEQ */ + __IOM uint32_t EP12_TRANSACTION : 1; /*!< EP12_TRANSACTION */ + __IOM uint32_t EP12_SEQ : 1; /*!< EP12_SEQ */ + __IOM uint32_t EP13_TRANSACTION : 1; /*!< EP13_TRANSACTION */ + __IOM uint32_t EP13_SEQ : 1; /*!< EP13_SEQ */ + __IOM uint32_t EP14_TRANSACTION : 1; /*!< EP14_TRANSACTION */ + __IOM uint32_t EP14_SEQ : 1; /*!< EP14_SEQ */ + __IOM uint32_t EP15_TRANSACTION : 1; /*!< EP15_TRANSACTION */ + __IOM uint32_t EP15_SEQ : 1; /*!< EP15_SEQ */ + } bit; + } EP_RX_ERROR; + + union { + __IOM uint32_t reg; /*!< Watchdog that forces the device state machine to idle and raises + an interrupt if the device stays in a state that isn't + idle for the configured limit. The counter is reset on + every state transition. Set limit while enable is low and + then set the enable. */ + + struct { + __IOM uint32_t LIMIT : 18; /*!< LIMIT */ + __IOM uint32_t ENABLE : 1; /*!< ENABLE */ + __IOM uint32_t RESET : 1; /*!< Set to 1 to forcibly reset the device state machine on watchdog + expiry */ + __IOM uint32_t FIRED : 1; /*!< FIRED */ + uint32_t : 11; + } bit; + } DEV_SM_WATCHDOG; +} USB_Type; /*!< Size = 280 (0x118) */ + + + +/* =========================================================================================================================== */ +/* ================ TRNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ARM TrustZone RNG register block (TRNG) + */ + +typedef struct { /*!< TRNG Structure */ + __IM uint32_t RESERVED[64]; + + union { + __IOM uint32_t reg; /*!< Interrupt masking. */ + + struct { + __IOM uint32_t EHR_VALID_INT_MASK : 1; /*!< 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR + for an explanation on this interrupt. */ + __IOM uint32_t AUTOCORR_ERR_INT_MASK : 1; /*!< 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR + for an explanation on this interrupt. */ + __IOM uint32_t CRNGT_ERR_INT_MASK : 1; /*!< 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR + for an explanation on this interrupt. */ + __IOM uint32_t VN_ERR_INT_MASK : 1; /*!< 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR + for an explanation on this interrupt. */ + uint32_t : 28; + } bit; + } RNG_IMR; + + union { + __IOM uint32_t reg; /*!< RNG status register. If corresponding RNG_IMR bit is unmasked, + an interrupt will be generated. */ + + struct { + __IM uint32_t EHR_VALID : 1; /*!< 1'b1 indicates that 192 bits have been collected in the RNG, + and are ready to be read. */ + __IM uint32_t AUTOCORR_ERR : 1; /*!< 1'b1 indicates Autocorrelation test failed four times in a row. + When set, RNG cease from functioning until next reset. */ + __IM uint32_t CRNGT_ERR : 1; /*!< 1'b1 indicates CRNGT in the RNG test failed. Failure occurs + when two consecutive blocks of 16 collected bits are equal. */ + __IM uint32_t VN_ERR : 1; /*!< 1'b1 indicates Von Neuman error. Error in von Neuman occurs + if 32 consecutive collected bits are identical, ZERO or + ONE. */ + uint32_t : 28; + } bit; + } RNG_ISR; + + union { + __IOM uint32_t reg; /*!< Interrupt/status bit clear Register. */ + + struct { + __IOM uint32_t EHR_VALID : 1; /*!< Write 1'b1 - clear corresponding bit in RNG_ISR. */ + __IOM uint32_t AUTOCORR_ERR : 1; /*!< Cannot be cleared by SW! Only RNG reset clears this bit. */ + __IOM uint32_t CRNGT_ERR : 1; /*!< Write 1'b1 - clear corresponding bit in RNG_ISR. */ + __IOM uint32_t VN_ERR : 1; /*!< Write 1'b1 - clear corresponding bit in RNG_ISR. */ + uint32_t : 28; + } bit; + } RNG_ICR; + + union { + __IOM uint32_t reg; /*!< Selecting the inverter-chain length. */ + + struct { + __IOM uint32_t RND_SRC_SEL : 2; /*!< Selects the number of inverters (out of four possible selections) + in the ring oscillator (the entropy source). */ + uint32_t : 30; + } bit; + } TRNG_CONFIG; + + union { + __IOM uint32_t reg; /*!< 192 bit collection indication. */ + + struct { + __IM uint32_t EHR_VALID : 1; /*!< 1'b1 indicates that collection of bits in the RNG is completed, + and data can be read from EHR_DATA register. */ + uint32_t : 31; + } bit; + } TRNG_VALID; + + union { + __IOM uint32_t reg; /*!< RNG collected bits. */ + + struct { + __IM uint32_t EHR_DATA0 : 32; /*!< Bits [31:0] of Entropy Holding Register (EHR) - RNG output register */ + } bit; + } EHR_DATA0; + + union { + __IOM uint32_t reg; /*!< RNG collected bits. */ + + struct { + __IM uint32_t EHR_DATA1 : 32; /*!< Bits [63:32] of Entropy Holding Register (EHR) - RNG output + register */ + } bit; + } EHR_DATA1; + + union { + __IOM uint32_t reg; /*!< RNG collected bits. */ + + struct { + __IM uint32_t EHR_DATA2 : 32; /*!< Bits [95:64] of Entropy Holding Register (EHR) - RNG output + register */ + } bit; + } EHR_DATA2; + + union { + __IOM uint32_t reg; /*!< RNG collected bits. */ + + struct { + __IM uint32_t EHR_DATA3 : 32; /*!< Bits [127:96] of Entropy Holding Register (EHR) - RNG output + register */ + } bit; + } EHR_DATA3; + + union { + __IOM uint32_t reg; /*!< RNG collected bits. */ + + struct { + __IM uint32_t EHR_DATA4 : 32; /*!< Bits [159:128] of Entropy Holding Register (EHR) - RNG output + register */ + } bit; + } EHR_DATA4; + + union { + __IOM uint32_t reg; /*!< RNG collected bits. */ + + struct { + __IM uint32_t EHR_DATA5 : 32; /*!< Bits [191:160] of Entropy Holding Register (EHR) - RNG output + register */ + } bit; + } EHR_DATA5; + + union { + __IOM uint32_t reg; /*!< Enable signal for the random source. */ + + struct { + __IOM uint32_t RND_SRC_EN : 1; /*!< * 1'b1 - entropy source is enabled. *1'b0 - entropy source is + disabled */ + uint32_t : 31; + } bit; + } RND_SOURCE_ENABLE; + + union { + __IOM uint32_t reg; /*!< Counts clocks between sampling of random bit. */ + + struct { + __IOM uint32_t SAMPLE_CNTR1 : 32; /*!< Sets the number of rng_clk cycles between two consecutive ring + oscillator samples. Note! If the Von-Neuman is bypassed, + the minimum value for sample counter must not be less then + decimal seventeen */ + } bit; + } SAMPLE_CNT1; + + union { + __IOM uint32_t reg; /*!< Statistic about Autocorrelation test activations. */ + + struct { + __IOM uint32_t AUTOCORR_TRYS : 14; /*!< Count each time an autocorrelation test starts. Any write to + the register reset the counter. Stop collecting statistic + if one of the counters reached the limit. */ + __IOM uint32_t AUTOCORR_FAILS : 8; /*!< Count each time an autocorrelation test fails. Any write to + the register reset the counter. Stop collecting statistic + if one of the counters reached the limit. */ + uint32_t : 10; + } bit; + } AUTOCORR_STATISTIC; + + union { + __IOM uint32_t reg; /*!< Debug register. */ + + struct { + uint32_t : 1; + __IOM uint32_t VNC_BYPASS : 1; /*!< When set, the Von-Neuman balancer is bypassed (including the + 32 consecutive bits test). */ + __IOM uint32_t TRNG_CRNGT_BYPASS : 1; /*!< When set, the CRNGT test in the RNG is bypassed. */ + __IOM uint32_t AUTO_CORRELATE_BYPASS : 1; /*!< When set, the autocorrelation test in the TRNG module is bypassed. */ + uint32_t : 28; + } bit; + } TRNG_DEBUG_CONTROL; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< Generate internal SW reset within the RNG block. */ + + struct { + __IOM uint32_t TRNG_SW_RESET : 1; /*!< Writing 1'b1 to this register causes an internal RNG reset. */ + uint32_t : 31; + } bit; + } TRNG_SW_RESET; + __IM uint32_t RESERVED2[28]; + + union { + __IOM uint32_t reg; /*!< Enable the RNG debug mode */ + + struct { + __IOM uint32_t RNG_DEBUG_EN : 1; /*!< * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled */ + uint32_t : 31; + } bit; + } RNG_DEBUG_EN_INPUT; + + union { + __IOM uint32_t reg; /*!< RNG Busy indication. */ + + struct { + __IM uint32_t TRNG_BUSY : 1; /*!< Reflects rng_busy status. */ + uint32_t : 31; + } bit; + } TRNG_BUSY; + + union { + __IOM uint32_t reg; /*!< Reset the counter of collected bits in the RNG. */ + + struct { + __IOM uint32_t RST_BITS_COUNTER : 1; /*!< Writing any value to this address will reset the bits counter + and RNG valid registers. RND_SORCE_ENABLE register must + be unset in order for the reset to take place. */ + uint32_t : 31; + } bit; + } RST_BITS_COUNTER; + + union { + __IOM uint32_t reg; /*!< Displays the version settings of the TRNG. */ + + struct { + __IM uint32_t EHR_WIDTH_192 : 1; /*!< * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR */ + __IM uint32_t CRNGT_EXISTS : 1; /*!< * 1'b1 - Exists. *1'b0 - Does not exist */ + __IM uint32_t AUTOCORR_EXISTS : 1; /*!< * 1'b1 - Exists. *1'b0 - Does not exist */ + __IM uint32_t TRNG_TESTS_BYPASS_EN : 1; /*!< * 1'b1 - Exists. *1'b0 - Does not exist */ + __IM uint32_t PRNG_EXISTS : 1; /*!< * 1'b1 - Exists. *1'b0 - Does not exist */ + __IM uint32_t KAT_EXISTS : 1; /*!< * 1'b1 - Exists. *1'b0 - Does not exist */ + __IM uint32_t RESEEDING_EXISTS : 1; /*!< * 1'b1 - Exists. *1'b0 - Does not exist */ + __IM uint32_t RNG_USE_5_SBOXES : 1; /*!< * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES */ + uint32_t : 24; + } bit; + } RNG_VERSION; + __IM uint32_t RESERVED3[7]; + + union { + __IOM uint32_t reg; /*!< Collected BIST results. */ + + struct { + __IM uint32_t ROSC_CNTR_VAL : 22; /*!< Reflects the results of RNG BIST counter. */ + uint32_t : 10; + } bit; + } RNG_BIST_CNTR_0; + + union { + __IOM uint32_t reg; /*!< Collected BIST results. */ + + struct { + __IM uint32_t ROSC_CNTR_VAL : 22; /*!< Reflects the results of RNG BIST counter. */ + uint32_t : 10; + } bit; + } RNG_BIST_CNTR_1; + + union { + __IOM uint32_t reg; /*!< Collected BIST results. */ + + struct { + __IM uint32_t ROSC_CNTR_VAL : 22; /*!< Reflects the results of RNG BIST counter. */ + uint32_t : 10; + } bit; + } RNG_BIST_CNTR_2; +} TRNG_Type; /*!< Size = 492 (0x1ec) */ + + + +/* =========================================================================================================================== */ +/* ================ GLITCH_DETECTOR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Glitch detector controls (GLITCH_DETECTOR) + */ + +typedef struct { /*!< GLITCH_DETECTOR Structure */ + + union { + __IOM uint32_t reg; /*!< Forcibly arm the glitch detectors, if they are not already armed + by OTP. When armed, any individual detector trigger will + cause a restart of the switched core power domain's power-on + reset state machine. Glitch detector triggers are recorded + accumulatively in TRIG_STATUS. If the system is reset by + a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. + This register is Secure read/write only. */ + + struct { + __IOM uint32_t ARM : 16; /*!< ARM */ + uint32_t : 16; + } bit; + } ARM; + + union { + __IOM uint32_t reg; /*!< DISARM */ + + struct { + __IOM uint32_t DISARM : 16; /*!< Forcibly disarm the glitch detectors, if they are armed by OTP. + Ignored if ARM is YES. This register is Secure read/write + only. */ + uint32_t : 16; + } bit; + } DISARM; + + union { + __IOM uint32_t reg; /*!< Adjust the sensitivity of glitch detectors to values other than + their OTP-provided defaults. This register is Secure read/write + only. */ + + struct { + __IOM uint32_t DET0 : 2; /*!< Set sensitivity for detector 0. Higher values are more sensitive. */ + __IOM uint32_t DET1 : 2; /*!< Set sensitivity for detector 1. Higher values are more sensitive. */ + __IOM uint32_t DET2 : 2; /*!< Set sensitivity for detector 2. Higher values are more sensitive. */ + __IOM uint32_t DET3 : 2; /*!< Set sensitivity for detector 3. Higher values are more sensitive. */ + __IOM uint32_t DET0_INV : 2; /*!< Must be the inverse of DET0, else the default value is used. */ + __IOM uint32_t DET1_INV : 2; /*!< Must be the inverse of DET1, else the default value is used. */ + __IOM uint32_t DET2_INV : 2; /*!< Must be the inverse of DET2, else the default value is used. */ + __IOM uint32_t DET3_INV : 2; /*!< Must be the inverse of DET3, else the default value is used. */ + uint32_t : 8; + __IOM uint32_t DEFAULT : 8; /*!< DEFAULT */ + } bit; + } SENSITIVITY; + + union { + __IOM uint32_t reg; /*!< LOCK */ + + struct { + __IOM uint32_t LOCK : 8; /*!< Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY + and LOCK. This register is Secure read/write only. */ + uint32_t : 24; + } bit; + } LOCK; + + union { + __IOM uint32_t reg; /*!< Set when a detector output triggers. Write-1-clear. (May immediately + return high if the detector remains in a failed state. + Detectors can only be cleared by a full reset of the switched + core power domain.) This register is Secure read/write + only. */ + + struct { + __IOM uint32_t DET0 : 1; /*!< DET0 */ + __IOM uint32_t DET1 : 1; /*!< DET1 */ + __IOM uint32_t DET2 : 1; /*!< DET2 */ + __IOM uint32_t DET3 : 1; /*!< DET3 */ + uint32_t : 28; + } bit; + } TRIG_STATUS; + + union { + __IOM uint32_t reg; /*!< Simulate the firing of one or more detectors. Writing ones to + this register will set the matching bits in STATUS_TRIG. + If the glitch detectors are currently armed, writing ones + will also immediately reset the switched core power domain, + and set the reset reason latches in POWMAN_CHIP_RESET to + indicate a glitch detector resets. This register is Secure + read/write only. */ + + struct { + __OM uint32_t TRIG_FORCE : 4; /*!< TRIG_FORCE */ + uint32_t : 28; + } bit; + } TRIG_FORCE; +} GLITCH_DETECTOR_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ OTP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SNPS OTP control IF (SBPI and RPi wrapper control) (OTP) + */ + +typedef struct { /*!< OTP Structure */ + + union { + __IOM uint32_t reg; /*!< Software lock register for page 0. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK0; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 1. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK1; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 2. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK2; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 3. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK3; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 4. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK4; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 5. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK5; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 6. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK6; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 7. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK7; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 8. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK8; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 9. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK9; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 10. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK10; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 11. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK11; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 12. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK12; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 13. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK13; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 14. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK14; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 15. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK15; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 16. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK16; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 17. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK17; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 18. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK18; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 19. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK19; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 20. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK20; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 21. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK21; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 22. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK22; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 23. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK23; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 24. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK24; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 25. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK25; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 26. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK26; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 27. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK27; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 28. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK28; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 29. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK29; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 30. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK30; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 31. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK31; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 32. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK32; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 33. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK33; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 34. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK34; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 35. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK35; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 36. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK36; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 37. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK37; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 38. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK38; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 39. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK39; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 40. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK40; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 41. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK41; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 42. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK42; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 43. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK43; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 44. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK44; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 45. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK45; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 46. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK46; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 47. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK47; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 48. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK48; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 49. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK49; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 50. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK50; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 51. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK51; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 52. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK52; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 53. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK53; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 54. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK54; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 55. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK55; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 56. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK56; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 57. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK57; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 58. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK58; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 59. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK59; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 60. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK60; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 61. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK61; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 62. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK62; + + union { + __IOM uint32_t reg; /*!< Software lock register for page 63. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + + struct { + __IOM uint32_t SEC : 2; /*!< Secure lock status. Writes are OR'd with the current value. + This field is read-only to Non-secure code. */ + __IOM uint32_t NSEC : 2; /*!< Non-secure lock status. Writes are OR'd with the current value. */ + uint32_t : 28; + } bit; + } SW_LOCK63; + + union { + __IOM uint32_t reg; /*!< Dispatch instructions to the SBPI interface, used for programming + the OTP fuses. */ + + struct { + __IOM uint32_t SHORT_WDATA : 8; /*!< wdata to be used only when payload_size_m1=0 */ + __IOM uint32_t CMD : 8; /*!< CMD */ + __IOM uint32_t TARGET : 8; /*!< Instruction target, it can be PMC (0x3a) or DAP (0x02) */ + __IOM uint32_t PAYLOAD_SIZE_M1 : 4; /*!< Instruction payload size in bytes minus 1 */ + __IOM uint32_t HAS_PAYLOAD : 1; /*!< Instruction has payload (data to be written or to be read) */ + __IOM uint32_t IS_WR : 1; /*!< Payload type is write */ + __OM uint32_t EXEC : 1; /*!< Execute instruction */ + uint32_t : 1; + } bit; + } SBPI_INSTR; + + union { + __IOM uint32_t reg; /*!< SBPI write payload bytes 3..0 */ + + struct { + __IOM uint32_t SBPI_WDATA_0 : 32; /*!< SBPI_WDATA_0 */ + } bit; + } SBPI_WDATA_0; + + union { + __IOM uint32_t reg; /*!< SBPI write payload bytes 7..4 */ + + struct { + __IOM uint32_t SBPI_WDATA_1 : 32; /*!< SBPI_WDATA_1 */ + } bit; + } SBPI_WDATA_1; + + union { + __IOM uint32_t reg; /*!< SBPI write payload bytes 11..8 */ + + struct { + __IOM uint32_t SBPI_WDATA_2 : 32; /*!< SBPI_WDATA_2 */ + } bit; + } SBPI_WDATA_2; + + union { + __IOM uint32_t reg; /*!< SBPI write payload bytes 15..12 */ + + struct { + __IOM uint32_t SBPI_WDATA_3 : 32; /*!< SBPI_WDATA_3 */ + } bit; + } SBPI_WDATA_3; + + union { + __IOM uint32_t reg; /*!< Read payload bytes 3..0. Once read, the data in the register + will automatically clear to 0. */ + + struct { + __IM uint32_t SBPI_RDATA_0 : 32; /*!< SBPI_RDATA_0 */ + } bit; + } SBPI_RDATA_0; + + union { + __IOM uint32_t reg; /*!< Read payload bytes 7..4. Once read, the data in the register + will automatically clear to 0. */ + + struct { + __IM uint32_t SBPI_RDATA_1 : 32; /*!< SBPI_RDATA_1 */ + } bit; + } SBPI_RDATA_1; + + union { + __IOM uint32_t reg; /*!< Read payload bytes 11..8. Once read, the data in the register + will automatically clear to 0. */ + + struct { + __IM uint32_t SBPI_RDATA_2 : 32; /*!< SBPI_RDATA_2 */ + } bit; + } SBPI_RDATA_2; + + union { + __IOM uint32_t reg; /*!< Read payload bytes 15..12. Once read, the data in the register + will automatically clear to 0. */ + + struct { + __IM uint32_t SBPI_RDATA_3 : 32; /*!< SBPI_RDATA_3 */ + } bit; + } SBPI_RDATA_3; + + union { + __IOM uint32_t reg; /*!< SBPI_STATUS */ + + struct { + __IOM uint32_t RDATA_VLD : 1; /*!< Read command has returned data */ + uint32_t : 3; + __IOM uint32_t INSTR_DONE : 1; /*!< Last instruction done */ + uint32_t : 3; + __IOM uint32_t INSTR_MISS : 1; /*!< Last instruction missed (dropped), as the previous has not finished + running */ + uint32_t : 3; + __IM uint32_t FLAG : 1; /*!< SBPI flag */ + uint32_t : 3; + __IM uint32_t MISO : 8; /*!< SBPI MISO (master in - slave out): response from SBPI */ + uint32_t : 8; + } bit; + } SBPI_STATUS; + + union { + __IOM uint32_t reg; /*!< Controls for APB data read interface (USER interface) */ + + struct { + __IOM uint32_t DCTRL : 1; /*!< 1 enables USER interface; 0 disables USER interface (enables + SBPI). This bit must be cleared before performing any SBPI + access, such as when programming the OTP. The APB data + read interface (USER interface) will be inaccessible during + this time, and will return a bus error if any read is attempted. */ + uint32_t : 3; + __IOM uint32_t PD : 1; /*!< Power-down; 1 disables current reference. Must be 0 to read + data from the OTP. */ + uint32_t : 27; + } bit; + } USR; + + union { + __IOM uint32_t reg; /*!< Debug for OTP power-on state machine */ + + struct { + __IM uint32_t PSM_DONE : 1; /*!< PSM done status flag */ + __IM uint32_t BOOT_DONE : 1; /*!< PSM boot done status flag */ + __IOM uint32_t ROSC_UP_SEEN : 1; /*!< Ring oscillator was seen up and running */ + __IM uint32_t ROSC_UP : 1; /*!< Ring oscillator is up and running */ + __IM uint32_t PSM_STATE : 4; /*!< Monitor the PSM FSM's state */ + uint32_t : 4; + __IM uint32_t CUSTOMER_RMA_FLAG : 1; /*!< The chip is in RMA mode */ + uint32_t : 19; + } bit; + } DBG; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< During BIST, count address locations that have at least one + leaky bit */ + + struct { + __IM uint32_t CNT : 13; /*!< Number of locations that have at least one leaky bit. Note: + This count is true only if the BIST was initiated without + the fix option. */ + uint32_t : 3; + __IOM uint32_t CNT_MAX : 12; /*!< The cnt_fail flag will be set if the number of leaky locations + exceeds this number */ + __IOM uint32_t CNT_ENA : 1; /*!< Enable the counter before the BIST function is initiated */ + __OM uint32_t CNT_CLR : 1; /*!< Clear counter before use */ + __IM uint32_t CNT_FAIL : 1; /*!< Flag if the count of address locations with at least one leaky + bit exceeds cnt_max */ + uint32_t : 1; + } bit; + } BIST; + + union { + __IOM uint32_t reg; /*!< Word 0 (bits 31..0) of the key. Write only, read returns 0x0 */ + + struct { + __OM uint32_t CRT_KEY_W0 : 32; /*!< CRT_KEY_W0 */ + } bit; + } CRT_KEY_W0; + + union { + __IOM uint32_t reg; /*!< Word 1 (bits 63..32) of the key. Write only, read returns 0x0 */ + + struct { + __OM uint32_t CRT_KEY_W1 : 32; /*!< CRT_KEY_W1 */ + } bit; + } CRT_KEY_W1; + + union { + __IOM uint32_t reg; /*!< Word 2 (bits 95..64) of the key. Write only, read returns 0x0 */ + + struct { + __OM uint32_t CRT_KEY_W2 : 32; /*!< CRT_KEY_W2 */ + } bit; + } CRT_KEY_W2; + + union { + __IOM uint32_t reg; /*!< Word 3 (bits 127..96) of the key. Write only, read returns 0x0 */ + + struct { + __OM uint32_t CRT_KEY_W3 : 32; /*!< CRT_KEY_W3 */ + } bit; + } CRT_KEY_W3; + + union { + __IOM uint32_t reg; /*!< Quickly check values of critical flags read during boot up */ + + struct { + __IM uint32_t SECURE_BOOT_ENABLE : 1; /*!< SECURE_BOOT_ENABLE */ + __IM uint32_t SECURE_DEBUG_DISABLE : 1; /*!< SECURE_DEBUG_DISABLE */ + __IM uint32_t DEBUG_DISABLE : 1; /*!< DEBUG_DISABLE */ + __IM uint32_t DEFAULT_ARCHSEL : 1; /*!< DEFAULT_ARCHSEL */ + __IM uint32_t GLITCH_DETECTOR_ENABLE : 1;/*!< GLITCH_DETECTOR_ENABLE */ + __IM uint32_t GLITCH_DETECTOR_SENS : 2; /*!< GLITCH_DETECTOR_SENS */ + uint32_t : 9; + __IM uint32_t ARM_DISABLE : 1; /*!< ARM_DISABLE */ + __IM uint32_t RISCV_DISABLE : 1; /*!< RISCV_DISABLE */ + uint32_t : 14; + } bit; + } CRITICAL; + + union { + __IOM uint32_t reg; /*!< Which keys were valid (enrolled) at boot time */ + + struct { + __IM uint32_t KEY_VALID : 8; /*!< KEY_VALID */ + uint32_t : 24; + } bit; + } KEY_VALID; + + union { + __IOM uint32_t reg; /*!< Enable a debug feature that has been disabled. Debug features + are disabled if one of the relevant critical boot flags + is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), + OR if a debug key is marked valid in OTP, and the matching + key value has not been supplied over SWD. Specifically: + - The DEBUG_DISABLE flag disables all debug features. This + can be fully overridden by setting all bits of this register. + - The SECURE_DEBUG_DISABLE flag disables secure processor + debug. This can be fully overridden by setting the PROC0_SECURE + and PROC1_SECURE bits of this register. - If a single debug + key has been registered, and no matching key value has + been supplied over SWD, then all debug features are disabled. + This can be fully overridden by setting all bits of this + register. - If both debug keys have been registered, and + the Non-secure key's value (key 6) has been supplied over + SWD, secure processor debug is disabled. This can be fully + overridden by setting the PROC0_SECURE and PROC1_SECURE + bits of this register. - If both debug keys have been registered, + and the Secure key's value (key 5) has been supplied over + SWD, then no debug features are disabled by the key mechanism. + However, note that in this case debug features may still + be disabled by the critical boot flags. */ + + struct { + __IOM uint32_t PROC0 : 1; /*!< Enable core 0's Mem-AP if it is currently disabled. The Mem-AP + is disabled by default if either of the debug disable critical + flags is set, or if at least one debug key has been enrolled + and the least secure of these enrolled key values has not + been provided over SWD. Note also that core Mem-APs are + unconditionally disabled when a core is switched to RISC-V + mode (by setting the ARCHSEL bit and performing a warm + reset of the core). */ + __IOM uint32_t PROC0_SECURE : 1; /*!< Permit core 0's Mem-AP to generate Secure accesses, assuming + it is enabled at all. Also enable secure debug of core + 0 (SPIDEN and SPNIDEN). Secure debug of core 0 is disabled + by default if the secure debug disable critical flag is + set, or if at least one debug key has been enrolled and + the most secure of these enrolled key values not yet provided + over SWD. Note also that core Mem-APs are unconditionally + disabled when a core is switched to RISC-V mode (by setting + the ARCHSEL bit and performing a warm reset of the core). */ + __IOM uint32_t PROC1 : 1; /*!< Enable core 1's Mem-AP if it is currently disabled. The Mem-AP + is disabled by default if either of the debug disable critical + flags is set, or if at least one debug key has been enrolled + and the least secure of these enrolled key values has not + been provided over SWD. */ + __IOM uint32_t PROC1_SECURE : 1; /*!< Permit core 1's Mem-AP to generate Secure accesses, assuming + it is enabled at all. Also enable secure debug of core + 1 (SPIDEN and SPNIDEN). Secure debug of core 1 is disabled + by default if the secure debug disable critical flag is + set, or if at least one debug key has been enrolled and + the most secure of these enrolled key values not yet provided + over SWD. */ + uint32_t : 4; + __IOM uint32_t MISC : 1; /*!< Enable other debug components. Specifically, the CTI, and the + APB-AP used to access the RISC-V Debug Module. These components + are disabled by default if either of the debug disable + critical flags is set, or if at least one debug key has + been enrolled and the least secure of these enrolled key + values has not been provided over SWD. */ + uint32_t : 23; + } bit; + } DEBUGEN; + + union { + __IOM uint32_t reg; /*!< Write 1s to lock corresponding bits in DEBUGEN. This register + is reset by the processor cold reset. */ + + struct { + __IOM uint32_t PROC0 : 1; /*!< Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once + set. */ + __IOM uint32_t PROC0_SECURE : 1; /*!< Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared + once set. */ + __IOM uint32_t PROC1 : 1; /*!< Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once + set. */ + __IOM uint32_t PROC1_SECURE : 1; /*!< Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared + once set. */ + uint32_t : 4; + __IOM uint32_t MISC : 1; /*!< Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once + set. */ + uint32_t : 23; + } bit; + } DEBUGEN_LOCK; + + union { + __IOM uint32_t reg; /*!< Architecture select (Arm/RISC-V). The default and allowable + values of this register are constrained by the critical + boot flags. This register is reset by the earliest reset + in the switched core power domain (before a processor cold + reset). Cores sample their architecture select signal on + a warm reset. The source of the warm reset could be the + system power-up state machine, the watchdog timer, Arm + SYSRESETREQ or from RISC-V hartresetreq. Note that when + an Arm core is deselected, its cold reset domain is also + held in reset, since in particular the SYSRESETREQ bit + becomes inaccessible once the core is deselected. Note + also the RISC-V cores do not have a cold reset domain, + since their corresponding controls are located in the Debug + Module. */ + + struct { + __IOM uint32_t CORE0 : 1; /*!< Select architecture for core 0. */ + __IOM uint32_t CORE1 : 1; /*!< Select architecture for core 1. */ + uint32_t : 30; + } bit; + } ARCHSEL; + + union { + __IOM uint32_t reg; /*!< Get the current architecture select state of each core. Cores + sample the current value of the ARCHSEL register when their + warm reset is released, at which point the corresponding + bit in this register will also update. */ + + struct { + __IM uint32_t CORE0 : 1; /*!< Current architecture for core 0. Updated on processor warm reset. */ + __IM uint32_t CORE1 : 1; /*!< Current architecture for core 0. Updated on processor warm reset. */ + uint32_t : 30; + } bit; + } ARCHSEL_STATUS; + + union { + __IOM uint32_t reg; /*!< Tell the bootrom to ignore scratch register boot vectors (both + power manager and watchdog) on the next power up. If an + early boot stage has soft-locked some OTP pages in order + to protect their contents from later stages, there is a + risk that Secure code running at a later stage can unlock + the pages by performing a watchdog reset that resets the + OTP. This register can be used to ensure that the bootloader + runs as normal on the next power up, preventing Secure + code at a later stage from accessing OTP in its unlocked + state. Should be used in conjunction with the power manager + BOOTDIS register. */ + + struct { + __IOM uint32_t NOW : 1; /*!< When the core is powered down, the current value of BOOTDIS_NEXT + is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + The bootrom checks this flag before reading the boot scratch + registers. If it is set, the bootrom clears it, and ignores + the BOOT registers. This prevents Secure software from + diverting the boot path before a bootloader has had the + chance to soft lock OTP pages containing sensitive data. */ + __IOM uint32_t NEXT : 1; /*!< This flag always ORs writes into its current contents. It can + be set but not cleared by software. The BOOTDIS_NEXT bit + is OR'd into the BOOTDIS_NOW bit when the core is powered + down. Simultaneously, the BOOTDIS_NEXT bit is cleared. + Setting this bit means that the boot scratch registers + will be ignored following the next core power down. This + flag should be set by an early boot stage that has soft-locked + OTP pages, to prevent later stages from unlocking it via + watchdog reset. */ + uint32_t : 30; + } bit; + } BOOTDIS; + + union { + __IOM uint32_t reg; /*!< Raw Interrupts */ + + struct { + __IM uint32_t SBPI_FLAG_N : 1; /*!< SBPI_FLAG_N */ + __IOM uint32_t SBPI_WR_FAIL : 1; /*!< SBPI_WR_FAIL */ + __IOM uint32_t APB_DCTRL_FAIL : 1; /*!< APB_DCTRL_FAIL */ + __IOM uint32_t APB_RD_SEC_FAIL : 1; /*!< APB_RD_SEC_FAIL */ + __IOM uint32_t APB_RD_NSEC_FAIL : 1; /*!< APB_RD_NSEC_FAIL */ + uint32_t : 27; + } bit; + } INTR; + + union { + __IOM uint32_t reg; /*!< Interrupt Enable */ + + struct { + __IOM uint32_t SBPI_FLAG_N : 1; /*!< SBPI_FLAG_N */ + __IOM uint32_t SBPI_WR_FAIL : 1; /*!< SBPI_WR_FAIL */ + __IOM uint32_t APB_DCTRL_FAIL : 1; /*!< APB_DCTRL_FAIL */ + __IOM uint32_t APB_RD_SEC_FAIL : 1; /*!< APB_RD_SEC_FAIL */ + __IOM uint32_t APB_RD_NSEC_FAIL : 1; /*!< APB_RD_NSEC_FAIL */ + uint32_t : 27; + } bit; + } INTE; + + union { + __IOM uint32_t reg; /*!< Interrupt Force */ + + struct { + __IOM uint32_t SBPI_FLAG_N : 1; /*!< SBPI_FLAG_N */ + __IOM uint32_t SBPI_WR_FAIL : 1; /*!< SBPI_WR_FAIL */ + __IOM uint32_t APB_DCTRL_FAIL : 1; /*!< APB_DCTRL_FAIL */ + __IOM uint32_t APB_RD_SEC_FAIL : 1; /*!< APB_RD_SEC_FAIL */ + __IOM uint32_t APB_RD_NSEC_FAIL : 1; /*!< APB_RD_NSEC_FAIL */ + uint32_t : 27; + } bit; + } INTF; + + union { + __IOM uint32_t reg; /*!< Interrupt status after masking & forcing */ + + struct { + __IM uint32_t SBPI_FLAG_N : 1; /*!< SBPI_FLAG_N */ + __IM uint32_t SBPI_WR_FAIL : 1; /*!< SBPI_WR_FAIL */ + __IM uint32_t APB_DCTRL_FAIL : 1; /*!< APB_DCTRL_FAIL */ + __IM uint32_t APB_RD_SEC_FAIL : 1; /*!< APB_RD_SEC_FAIL */ + __IM uint32_t APB_RD_NSEC_FAIL : 1; /*!< APB_RD_NSEC_FAIL */ + uint32_t : 27; + } bit; + } INTS; +} OTP_Type; /*!< Size = 372 (0x174) */ + + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Predefined OTP data layout for RP2350 (OTP_DATA) + */ + +typedef struct { /*!< OTP_DATA Structure */ + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain + a 64-bit random identifier for this chip, which can be + read from the USB bootloader PICOBOOT interface or from + the get_sys_info ROM API. The number of random bits makes + the occurrence of twins exceedingly unlikely: for example, + a fleet of a hundred million devices has a 99.97% probability + of no twinned IDs. This is estimated to be lower than the + occurrence of process errors in the assignment of sequential + random IDs, and for practical purposes CHIPID may be treated + as unique. */ + + struct { + __IM uint16_t CHIPID0 : 16; /*!< CHIPID0 */ + } bit; + } CHIPID0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of public device ID (ECC) */ + + struct { + __IM uint16_t CHIPID1 : 16; /*!< CHIPID1 */ + } bit; + } CHIPID1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of public device ID (ECC) */ + + struct { + __IM uint16_t CHIPID2 : 16; /*!< CHIPID2 */ + } bit; + } CHIPID2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of public device ID (ECC) */ + + struct { + __IM uint16_t CHIPID3 : 16; /*!< CHIPID3 */ + } bit; + } CHIPID3; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 + rows form a 128-bit random number generated during device + test. This ID is not exposed through the USB PICOBOOT GET_INFO + command or the ROM `get_sys_info()` API. However note that + the USB PICOBOOT OTP access point can read the entirety + of page 0, so this value is not meaningfully private unless + the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO + T_IFC flag in BOOT_FLAGS0. */ + + struct { + __IM uint16_t RANDID0 : 16; /*!< RANDID0 */ + } bit; + } RANDID0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of private per-device random number (ECC) */ + + struct { + __IM uint16_t RANDID1 : 16; /*!< RANDID1 */ + } bit; + } RANDID1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of private per-device random number (ECC) */ + + struct { + __IM uint16_t RANDID2 : 16; /*!< RANDID2 */ + } bit; + } RANDID2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of private per-device random number (ECC) */ + + struct { + __IM uint16_t RANDID3 : 16; /*!< RANDID3 */ + } bit; + } RANDID3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of private per-device random number (ECC) */ + + struct { + __IM uint16_t RANDID4 : 16; /*!< RANDID4 */ + } bit; + } RANDID4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of private per-device random number (ECC) */ + + struct { + __IM uint16_t RANDID5 : 16; /*!< RANDID5 */ + } bit; + } RANDID5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of private per-device random number (ECC) */ + + struct { + __IM uint16_t RANDID6 : 16; /*!< RANDID6 */ + } bit; + } RANDID6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of private per-device random number (ECC) */ + + struct { + __IM uint16_t RANDID7 : 16; /*!< RANDID7 */ + } bit; + } RANDID7; + __IM uint16_t RESERVED[4]; + + union { + __IOM uint16_t reg; /*!< Ring oscillator frequency in kHz, measured during manufacturing + (ECC) This is measured at 1.1 V, at room temperature, with + the ROSC configuration registers in their reset state. */ + + struct { + __IM uint16_t ROSC_CALIB : 16; /*!< ROSC_CALIB */ + } bit; + } ROSC_CALIB; + + union { + __IOM uint16_t reg; /*!< Low-power oscillator frequency in Hz, measured during manufacturing + (ECC) This is measured at 1.1V, at room temperature, with + the LPOSC trim register in its reset state. */ + + struct { + __IM uint16_t LPOSC_CALIB : 16; /*!< LPOSC_CALIB */ + } bit; + } LPOSC_CALIB; + __IM uint16_t RESERVED1[6]; + + union { + __IOM uint16_t reg; /*!< The number of main user GPIOs (bank 0). Should read 48 in the + QFN80 package, and 30 in the QFN60 package. (ECC) */ + + struct { + __IM uint16_t NUM_GPIOS : 8; /*!< NUM_GPIOS */ + uint16_t : 8; + } bit; + } NUM_GPIOS; + __IM uint16_t RESERVED2[29]; + + union { + __IOM uint16_t reg; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial + 0x4c11db7, input reflected, output reflected, seed all-ones, + final XOR all-ones) (ECC) */ + + struct { + __IM uint16_t INFO_CRC0 : 16; /*!< INFO_CRC0 */ + } bit; + } INFO_CRC0; + + union { + __IOM uint16_t reg; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ + + struct { + __IM uint16_t INFO_CRC1 : 16; /*!< INFO_CRC1 */ + } bit; + } INFO_CRC1; + __IM uint16_t RESERVED3[28]; + + union { + __IOM uint16_t reg; /*!< Stores information about external flash device(s). (ECC) Assumed + to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ + + struct { + __IM uint16_t CS1_GPIO : 6; /*!< Indicate a GPIO number to be used for the secondary flash chip + select (CS1), which selects the external QSPI device mapped + at system addresses 0x11000000 through 0x11ffffff. There + is no such configuration for CS0, as the primary chip select + has a dedicated pin. On RP2350 the permissible GPIO numbers + are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE + is nonzero, the bootrom will automatically configure this + GPIO as a second chip select upon entering the flash boot + path, or entering any other path that may use the QSPI + flash interface, such as BOOTSEL mode (nsboot). */ + uint16_t : 1; + __IM uint16_t D8H_ERASE_SUPPORTED : 1; /*!< If true, all attached devices are assumed to support (or ignore, + in the case of PSRAM) a block erase command with a command + prefix of D8h, an erase size of 64 kiB, and a 24-bit address. + Almost all 25-series flash devices support this command. + If set, the bootrom will use the D8h erase command where + it is able, to accelerate bulk erase operations. This makes + flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE + is not set, this field defaults to false. */ + __IM uint16_t CS0_SIZE : 4; /*!< The size of the flash/PSRAM device on chip select 0 (addressable + at 0x10000000 through 0x10ffffff). A value of zero is decoded + as a size of zero (no device). Nonzero values are decoded + as 4kiB << CS0_SIZE. For example, four megabytes is encoded + with a CS0_SIZE value of 10, and 16 megabytes is encoded + with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE + is not set, a default of 12 (16 MiB) is used. */ + __IM uint16_t CS1_SIZE : 4; /*!< The size of the flash/PSRAM device on chip select 1 (addressable + at 0x11000000 through 0x11ffffff). A value of zero is decoded + as a size of zero (no device). Nonzero values are decoded + as 4kiB << CS1_SIZE. For example, four megabytes is encoded + with a CS1_SIZE value of 10, and 16 megabytes is encoded + with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE + is not set, a default of zero is used. */ + } bit; + } FLASH_DEVINFO; + + union { + __IOM uint16_t reg; /*!< Gap between partition table slot 0 and slot 1 at the start of + flash (the default size is 4096 bytes) (ECC) Enabled by + the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, + the size is 4096 * (value + 1) */ + + struct { + __IM uint16_t FLASH_PARTITION_SLOT_SIZE : 16;/*!< FLASH_PARTITION_SLOT_SIZE */ + } bit; + } FLASH_PARTITION_SLOT_SIZE; + + union { + __IOM uint16_t reg; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ + + struct { + __IM uint16_t PIN : 6; /*!< GPIO index to use for bootloader activity LED. */ + uint16_t : 2; + __IM uint16_t ACTIVELOW : 1; /*!< LED is active-low. (Default: active-high.) */ + uint16_t : 7; + } bit; + } BOOTSEL_LED_CFG; + + union { + __IOM uint16_t reg; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should + be configured to produce an exact 48 MHz based on the crystal + oscillator frequency. User mode software may also use this + value to calculate the expected crystal frequency based + on an assumed 48 MHz PLL output. If no configuration is + given, the crystal is assumed to be 12 MHz. The PLL frequency + can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) + x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal + frequency can be calculated as: XOSC frequency = 48 MHz + x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the + +1 on REFDIV is because the value stored in this OTP location + is the actual divisor value minus one.) Used if and only + if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. + That bit should be set only after this row and BOOTSEL_XOSC_CFG + are both correctly programmed. */ + + struct { + __IM uint16_t FBDIV : 9; /*!< PLL feedback divisor, in the range 16..320 inclusive. */ + __IM uint16_t POSTDIV1 : 3; /*!< PLL post-divide 1 divisor, in the range 1..7 inclusive. */ + __IM uint16_t POSTDIV2 : 3; /*!< PLL post-divide 2 divisor, in the range 1..7 inclusive. */ + __IM uint16_t REFDIV : 1; /*!< PLL reference divisor, minus one. Programming a value of 0 means + a reference divisor of 1. Programming a value of 1 means + a reference divisor of 2 (for exceptionally fast XIN inputs) */ + } bit; + } BOOTSEL_PLL_CFG; + + union { + __IOM uint16_t reg; /*!< Non-default crystal oscillator configuration for the USB bootloader. + (ECC) These values may also be used by user code configuring + the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL + _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set + only after this row and BOOTSEL_PLL_CFG are both correctly + programmed. */ + + struct { + __IM uint16_t STARTUP : 14; /*!< Value of the XOSC_STARTUP register */ + __IM uint16_t RANGE : 2; /*!< Value of the XOSC_CTRL_FREQ_RANGE register. */ + } bit; + } BOOTSEL_XOSC_CFG; + __IM uint16_t RESERVED4[3]; + + union { + __IOM uint16_t reg; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) + The table has 16 rows, each of which are also ECC and marked + valid by the corresponding valid bit in USB_BOOT_FLAGS + (ECC). The entries are either _VALUEs where the 16 bit + value is used as is, or _STRDEFs which acts as a pointers + to a string value. The value stored in a _STRDEF is two + separate bytes: The low seven bits of the first (LSB) byte + indicates the number of characters in the string, and the + top bit of the first (LSB) byte if set to indicate that + each character in the string is two bytes (Unicode) versus + one byte if unset. The second (MSB) byte represents the + location of the string data, and is encoded as the number + of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of + the start of the string is USB_WHITE_LABEL_ADDR value + + msb_byte. In each case, the corresponding valid bit enables + replacing the default value for the corresponding item + provided by the boot rom. Note that Unicode _STRDEFs are + only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST + DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values + will be ignored if specified for other fields, and non-unicode + values for these three items will be converted to Unicode + characters by setting the upper 8 bits to zero. Note that + if the USB_WHITE_LABEL structure or the corresponding strings + are not readable by BOOTSEL mode based on OTP permissions, + or if alignment requirements are not met, then the corresponding + default values are used. The index values indicate where + each field is located (row USB_WHITE_LABEL_ADDR value + + index): */ + + struct { + __IM uint16_t USB_WHITE_LABEL_ADDR : 16; /*!< USB_WHITE_LABEL_ADDR */ + } bit; + } USB_WHITE_LABEL_ADDR; + __IM uint16_t RESERVED5; + + union { + __IOM uint16_t reg; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, + the bootrom will load from this location into SRAM and + then directly enter the loaded image. Note that the image + must be signed if SECURE_BOOT_ENABLE is set. The image + itself is assumed to be ECC-protected. This must be an + even number. Equivalently, the OTP boot image must start + at a word-aligned location in the ECC read data address + window. */ + + struct { + __IM uint16_t OTPBOOT_SRC : 16; /*!< OTPBOOT_SRC */ + } bit; + } OTPBOOT_SRC; + + union { + __IOM uint16_t reg; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must + be even. The total image size must be a multiple of 4 bytes + (32 bits). */ + + struct { + __IM uint16_t OTPBOOT_LEN : 16; /*!< OTPBOOT_LEN */ + } bit; + } OTPBOOT_LEN; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + + struct { + __IM uint16_t OTPBOOT_DST0 : 16; /*!< OTPBOOT_DST0 */ + } bit; + } OTPBOOT_DST0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + + struct { + __IM uint16_t OTPBOOT_DST1 : 16; /*!< OTPBOOT_DST1 */ + } bit; + } OTPBOOT_DST1; + __IM uint16_t RESERVED6[30]; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_0 : 16; /*!< BOOTKEY0_0 */ + } bit; + } BOOTKEY0_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_1 : 16; /*!< BOOTKEY0_1 */ + } bit; + } BOOTKEY0_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_2 : 16; /*!< BOOTKEY0_2 */ + } bit; + } BOOTKEY0_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_3 : 16; /*!< BOOTKEY0_3 */ + } bit; + } BOOTKEY0_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_4 : 16; /*!< BOOTKEY0_4 */ + } bit; + } BOOTKEY0_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_5 : 16; /*!< BOOTKEY0_5 */ + } bit; + } BOOTKEY0_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_6 : 16; /*!< BOOTKEY0_6 */ + } bit; + } BOOTKEY0_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_7 : 16; /*!< BOOTKEY0_7 */ + } bit; + } BOOTKEY0_7; + + union { + __IOM uint16_t reg; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_8 : 16; /*!< BOOTKEY0_8 */ + } bit; + } BOOTKEY0_8; + + union { + __IOM uint16_t reg; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_9 : 16; /*!< BOOTKEY0_9 */ + } bit; + } BOOTKEY0_9; + + union { + __IOM uint16_t reg; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_10 : 16; /*!< BOOTKEY0_10 */ + } bit; + } BOOTKEY0_10; + + union { + __IOM uint16_t reg; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_11 : 16; /*!< BOOTKEY0_11 */ + } bit; + } BOOTKEY0_11; + + union { + __IOM uint16_t reg; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_12 : 16; /*!< BOOTKEY0_12 */ + } bit; + } BOOTKEY0_12; + + union { + __IOM uint16_t reg; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_13 : 16; /*!< BOOTKEY0_13 */ + } bit; + } BOOTKEY0_13; + + union { + __IOM uint16_t reg; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_14 : 16; /*!< BOOTKEY0_14 */ + } bit; + } BOOTKEY0_14; + + union { + __IOM uint16_t reg; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint16_t BOOTKEY0_15 : 16; /*!< BOOTKEY0_15 */ + } bit; + } BOOTKEY0_15; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_0 : 16; /*!< BOOTKEY1_0 */ + } bit; + } BOOTKEY1_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_1 : 16; /*!< BOOTKEY1_1 */ + } bit; + } BOOTKEY1_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_2 : 16; /*!< BOOTKEY1_2 */ + } bit; + } BOOTKEY1_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_3 : 16; /*!< BOOTKEY1_3 */ + } bit; + } BOOTKEY1_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_4 : 16; /*!< BOOTKEY1_4 */ + } bit; + } BOOTKEY1_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_5 : 16; /*!< BOOTKEY1_5 */ + } bit; + } BOOTKEY1_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_6 : 16; /*!< BOOTKEY1_6 */ + } bit; + } BOOTKEY1_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_7 : 16; /*!< BOOTKEY1_7 */ + } bit; + } BOOTKEY1_7; + + union { + __IOM uint16_t reg; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_8 : 16; /*!< BOOTKEY1_8 */ + } bit; + } BOOTKEY1_8; + + union { + __IOM uint16_t reg; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_9 : 16; /*!< BOOTKEY1_9 */ + } bit; + } BOOTKEY1_9; + + union { + __IOM uint16_t reg; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_10 : 16; /*!< BOOTKEY1_10 */ + } bit; + } BOOTKEY1_10; + + union { + __IOM uint16_t reg; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_11 : 16; /*!< BOOTKEY1_11 */ + } bit; + } BOOTKEY1_11; + + union { + __IOM uint16_t reg; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_12 : 16; /*!< BOOTKEY1_12 */ + } bit; + } BOOTKEY1_12; + + union { + __IOM uint16_t reg; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_13 : 16; /*!< BOOTKEY1_13 */ + } bit; + } BOOTKEY1_13; + + union { + __IOM uint16_t reg; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_14 : 16; /*!< BOOTKEY1_14 */ + } bit; + } BOOTKEY1_14; + + union { + __IOM uint16_t reg; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint16_t BOOTKEY1_15 : 16; /*!< BOOTKEY1_15 */ + } bit; + } BOOTKEY1_15; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_0 : 16; /*!< BOOTKEY2_0 */ + } bit; + } BOOTKEY2_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_1 : 16; /*!< BOOTKEY2_1 */ + } bit; + } BOOTKEY2_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_2 : 16; /*!< BOOTKEY2_2 */ + } bit; + } BOOTKEY2_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_3 : 16; /*!< BOOTKEY2_3 */ + } bit; + } BOOTKEY2_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_4 : 16; /*!< BOOTKEY2_4 */ + } bit; + } BOOTKEY2_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_5 : 16; /*!< BOOTKEY2_5 */ + } bit; + } BOOTKEY2_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_6 : 16; /*!< BOOTKEY2_6 */ + } bit; + } BOOTKEY2_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_7 : 16; /*!< BOOTKEY2_7 */ + } bit; + } BOOTKEY2_7; + + union { + __IOM uint16_t reg; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_8 : 16; /*!< BOOTKEY2_8 */ + } bit; + } BOOTKEY2_8; + + union { + __IOM uint16_t reg; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_9 : 16; /*!< BOOTKEY2_9 */ + } bit; + } BOOTKEY2_9; + + union { + __IOM uint16_t reg; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_10 : 16; /*!< BOOTKEY2_10 */ + } bit; + } BOOTKEY2_10; + + union { + __IOM uint16_t reg; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_11 : 16; /*!< BOOTKEY2_11 */ + } bit; + } BOOTKEY2_11; + + union { + __IOM uint16_t reg; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_12 : 16; /*!< BOOTKEY2_12 */ + } bit; + } BOOTKEY2_12; + + union { + __IOM uint16_t reg; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_13 : 16; /*!< BOOTKEY2_13 */ + } bit; + } BOOTKEY2_13; + + union { + __IOM uint16_t reg; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_14 : 16; /*!< BOOTKEY2_14 */ + } bit; + } BOOTKEY2_14; + + union { + __IOM uint16_t reg; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint16_t BOOTKEY2_15 : 16; /*!< BOOTKEY2_15 */ + } bit; + } BOOTKEY2_15; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_0 : 16; /*!< BOOTKEY3_0 */ + } bit; + } BOOTKEY3_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_1 : 16; /*!< BOOTKEY3_1 */ + } bit; + } BOOTKEY3_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_2 : 16; /*!< BOOTKEY3_2 */ + } bit; + } BOOTKEY3_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_3 : 16; /*!< BOOTKEY3_3 */ + } bit; + } BOOTKEY3_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_4 : 16; /*!< BOOTKEY3_4 */ + } bit; + } BOOTKEY3_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_5 : 16; /*!< BOOTKEY3_5 */ + } bit; + } BOOTKEY3_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_6 : 16; /*!< BOOTKEY3_6 */ + } bit; + } BOOTKEY3_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_7 : 16; /*!< BOOTKEY3_7 */ + } bit; + } BOOTKEY3_7; + + union { + __IOM uint16_t reg; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_8 : 16; /*!< BOOTKEY3_8 */ + } bit; + } BOOTKEY3_8; + + union { + __IOM uint16_t reg; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_9 : 16; /*!< BOOTKEY3_9 */ + } bit; + } BOOTKEY3_9; + + union { + __IOM uint16_t reg; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_10 : 16; /*!< BOOTKEY3_10 */ + } bit; + } BOOTKEY3_10; + + union { + __IOM uint16_t reg; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_11 : 16; /*!< BOOTKEY3_11 */ + } bit; + } BOOTKEY3_11; + + union { + __IOM uint16_t reg; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_12 : 16; /*!< BOOTKEY3_12 */ + } bit; + } BOOTKEY3_12; + + union { + __IOM uint16_t reg; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_13 : 16; /*!< BOOTKEY3_13 */ + } bit; + } BOOTKEY3_13; + + union { + __IOM uint16_t reg; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_14 : 16; /*!< BOOTKEY3_14 */ + } bit; + } BOOTKEY3_14; + + union { + __IOM uint16_t reg; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint16_t BOOTKEY3_15 : 16; /*!< BOOTKEY3_15 */ + } bit; + } BOOTKEY3_15; + __IM uint16_t RESERVED7[3720]; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of OTP access key 1 (ECC) */ + + struct { + __IM uint16_t KEY1_0 : 16; /*!< KEY1_0 */ + } bit; + } KEY1_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of OTP access key 1 (ECC) */ + + struct { + __IM uint16_t KEY1_1 : 16; /*!< KEY1_1 */ + } bit; + } KEY1_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of OTP access key 1 (ECC) */ + + struct { + __IM uint16_t KEY1_2 : 16; /*!< KEY1_2 */ + } bit; + } KEY1_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of OTP access key 1 (ECC) */ + + struct { + __IM uint16_t KEY1_3 : 16; /*!< KEY1_3 */ + } bit; + } KEY1_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of OTP access key 1 (ECC) */ + + struct { + __IM uint16_t KEY1_4 : 16; /*!< KEY1_4 */ + } bit; + } KEY1_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of OTP access key 1 (ECC) */ + + struct { + __IM uint16_t KEY1_5 : 16; /*!< KEY1_5 */ + } bit; + } KEY1_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of OTP access key 1 (ECC) */ + + struct { + __IM uint16_t KEY1_6 : 16; /*!< KEY1_6 */ + } bit; + } KEY1_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of OTP access key 1 (ECC) */ + + struct { + __IM uint16_t KEY1_7 : 16; /*!< KEY1_7 */ + } bit; + } KEY1_7; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of OTP access key 2 (ECC) */ + + struct { + __IM uint16_t KEY2_0 : 16; /*!< KEY2_0 */ + } bit; + } KEY2_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of OTP access key 2 (ECC) */ + + struct { + __IM uint16_t KEY2_1 : 16; /*!< KEY2_1 */ + } bit; + } KEY2_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of OTP access key 2 (ECC) */ + + struct { + __IM uint16_t KEY2_2 : 16; /*!< KEY2_2 */ + } bit; + } KEY2_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of OTP access key 2 (ECC) */ + + struct { + __IM uint16_t KEY2_3 : 16; /*!< KEY2_3 */ + } bit; + } KEY2_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of OTP access key 2 (ECC) */ + + struct { + __IM uint16_t KEY2_4 : 16; /*!< KEY2_4 */ + } bit; + } KEY2_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of OTP access key 2 (ECC) */ + + struct { + __IM uint16_t KEY2_5 : 16; /*!< KEY2_5 */ + } bit; + } KEY2_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of OTP access key 2 (ECC) */ + + struct { + __IM uint16_t KEY2_6 : 16; /*!< KEY2_6 */ + } bit; + } KEY2_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of OTP access key 2 (ECC) */ + + struct { + __IM uint16_t KEY2_7 : 16; /*!< KEY2_7 */ + } bit; + } KEY2_7; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of OTP access key 3 (ECC) */ + + struct { + __IM uint16_t KEY3_0 : 16; /*!< KEY3_0 */ + } bit; + } KEY3_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of OTP access key 3 (ECC) */ + + struct { + __IM uint16_t KEY3_1 : 16; /*!< KEY3_1 */ + } bit; + } KEY3_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of OTP access key 3 (ECC) */ + + struct { + __IM uint16_t KEY3_2 : 16; /*!< KEY3_2 */ + } bit; + } KEY3_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of OTP access key 3 (ECC) */ + + struct { + __IM uint16_t KEY3_3 : 16; /*!< KEY3_3 */ + } bit; + } KEY3_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of OTP access key 3 (ECC) */ + + struct { + __IM uint16_t KEY3_4 : 16; /*!< KEY3_4 */ + } bit; + } KEY3_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of OTP access key 3 (ECC) */ + + struct { + __IM uint16_t KEY3_5 : 16; /*!< KEY3_5 */ + } bit; + } KEY3_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of OTP access key 3 (ECC) */ + + struct { + __IM uint16_t KEY3_6 : 16; /*!< KEY3_6 */ + } bit; + } KEY3_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of OTP access key 3 (ECC) */ + + struct { + __IM uint16_t KEY3_7 : 16; /*!< KEY3_7 */ + } bit; + } KEY3_7; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of OTP access key 4 (ECC) */ + + struct { + __IM uint16_t KEY4_0 : 16; /*!< KEY4_0 */ + } bit; + } KEY4_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of OTP access key 4 (ECC) */ + + struct { + __IM uint16_t KEY4_1 : 16; /*!< KEY4_1 */ + } bit; + } KEY4_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of OTP access key 4 (ECC) */ + + struct { + __IM uint16_t KEY4_2 : 16; /*!< KEY4_2 */ + } bit; + } KEY4_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of OTP access key 4 (ECC) */ + + struct { + __IM uint16_t KEY4_3 : 16; /*!< KEY4_3 */ + } bit; + } KEY4_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of OTP access key 4 (ECC) */ + + struct { + __IM uint16_t KEY4_4 : 16; /*!< KEY4_4 */ + } bit; + } KEY4_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of OTP access key 4 (ECC) */ + + struct { + __IM uint16_t KEY4_5 : 16; /*!< KEY4_5 */ + } bit; + } KEY4_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of OTP access key 4 (ECC) */ + + struct { + __IM uint16_t KEY4_6 : 16; /*!< KEY4_6 */ + } bit; + } KEY4_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of OTP access key 4 (ECC) */ + + struct { + __IM uint16_t KEY4_7 : 16; /*!< KEY4_7 */ + } bit; + } KEY4_7; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of OTP access key 5 (ECC) */ + + struct { + __IM uint16_t KEY5_0 : 16; /*!< KEY5_0 */ + } bit; + } KEY5_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of OTP access key 5 (ECC) */ + + struct { + __IM uint16_t KEY5_1 : 16; /*!< KEY5_1 */ + } bit; + } KEY5_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of OTP access key 5 (ECC) */ + + struct { + __IM uint16_t KEY5_2 : 16; /*!< KEY5_2 */ + } bit; + } KEY5_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of OTP access key 5 (ECC) */ + + struct { + __IM uint16_t KEY5_3 : 16; /*!< KEY5_3 */ + } bit; + } KEY5_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of OTP access key 5 (ECC) */ + + struct { + __IM uint16_t KEY5_4 : 16; /*!< KEY5_4 */ + } bit; + } KEY5_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of OTP access key 5 (ECC) */ + + struct { + __IM uint16_t KEY5_5 : 16; /*!< KEY5_5 */ + } bit; + } KEY5_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of OTP access key 5 (ECC) */ + + struct { + __IM uint16_t KEY5_6 : 16; /*!< KEY5_6 */ + } bit; + } KEY5_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of OTP access key 5 (ECC) */ + + struct { + __IM uint16_t KEY5_7 : 16; /*!< KEY5_7 */ + } bit; + } KEY5_7; + + union { + __IOM uint16_t reg; /*!< Bits 15:0 of OTP access key 6 (ECC) */ + + struct { + __IM uint16_t KEY6_0 : 16; /*!< KEY6_0 */ + } bit; + } KEY6_0; + + union { + __IOM uint16_t reg; /*!< Bits 31:16 of OTP access key 6 (ECC) */ + + struct { + __IM uint16_t KEY6_1 : 16; /*!< KEY6_1 */ + } bit; + } KEY6_1; + + union { + __IOM uint16_t reg; /*!< Bits 47:32 of OTP access key 6 (ECC) */ + + struct { + __IM uint16_t KEY6_2 : 16; /*!< KEY6_2 */ + } bit; + } KEY6_2; + + union { + __IOM uint16_t reg; /*!< Bits 63:48 of OTP access key 6 (ECC) */ + + struct { + __IM uint16_t KEY6_3 : 16; /*!< KEY6_3 */ + } bit; + } KEY6_3; + + union { + __IOM uint16_t reg; /*!< Bits 79:64 of OTP access key 6 (ECC) */ + + struct { + __IM uint16_t KEY6_4 : 16; /*!< KEY6_4 */ + } bit; + } KEY6_4; + + union { + __IOM uint16_t reg; /*!< Bits 95:80 of OTP access key 6 (ECC) */ + + struct { + __IM uint16_t KEY6_5 : 16; /*!< KEY6_5 */ + } bit; + } KEY6_5; + + union { + __IOM uint16_t reg; /*!< Bits 111:96 of OTP access key 6 (ECC) */ + + struct { + __IM uint16_t KEY6_6 : 16; /*!< KEY6_6 */ + } bit; + } KEY6_6; + + union { + __IOM uint16_t reg; /*!< Bits 127:112 of OTP access key 6 (ECC) */ + + struct { + __IM uint16_t KEY6_7 : 16; /*!< KEY6_7 */ + } bit; + } KEY6_7; +} OTP_DATA_Type; /*!< Size = 7920 (0x1ef0) */ + + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA_RAW ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Predefined OTP data layout for RP2350 (OTP_DATA_RAW) + */ + +typedef struct { /*!< OTP_DATA_RAW Structure */ + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain + a 64-bit random identifier for this chip, which can be + read from the USB bootloader PICOBOOT interface or from + the get_sys_info ROM API. The number of random bits makes + the occurrence of twins exceedingly unlikely: for example, + a fleet of a hundred million devices has a 99.97% probability + of no twinned IDs. This is estimated to be lower than the + occurrence of process errors in the assignment of sequential + random IDs, and for practical purposes CHIPID may be treated + as unique. */ + + struct { + __IM uint32_t CHIPID0 : 16; /*!< CHIPID0 */ + uint32_t : 16; + } bit; + } CHIPID0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of public device ID (ECC) */ + + struct { + __IM uint32_t CHIPID1 : 16; /*!< CHIPID1 */ + uint32_t : 16; + } bit; + } CHIPID1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of public device ID (ECC) */ + + struct { + __IM uint32_t CHIPID2 : 16; /*!< CHIPID2 */ + uint32_t : 16; + } bit; + } CHIPID2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of public device ID (ECC) */ + + struct { + __IM uint32_t CHIPID3 : 16; /*!< CHIPID3 */ + uint32_t : 16; + } bit; + } CHIPID3; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 + rows form a 128-bit random number generated during device + test. This ID is not exposed through the USB PICOBOOT GET_INFO + command or the ROM `get_sys_info()` API. However note that + the USB PICOBOOT OTP access point can read the entirety + of page 0, so this value is not meaningfully private unless + the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO + T_IFC flag in BOOT_FLAGS0. */ + + struct { + __IM uint32_t RANDID0 : 16; /*!< RANDID0 */ + uint32_t : 16; + } bit; + } RANDID0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of private per-device random number (ECC) */ + + struct { + __IM uint32_t RANDID1 : 16; /*!< RANDID1 */ + uint32_t : 16; + } bit; + } RANDID1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of private per-device random number (ECC) */ + + struct { + __IM uint32_t RANDID2 : 16; /*!< RANDID2 */ + uint32_t : 16; + } bit; + } RANDID2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of private per-device random number (ECC) */ + + struct { + __IM uint32_t RANDID3 : 16; /*!< RANDID3 */ + uint32_t : 16; + } bit; + } RANDID3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of private per-device random number (ECC) */ + + struct { + __IM uint32_t RANDID4 : 16; /*!< RANDID4 */ + uint32_t : 16; + } bit; + } RANDID4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of private per-device random number (ECC) */ + + struct { + __IM uint32_t RANDID5 : 16; /*!< RANDID5 */ + uint32_t : 16; + } bit; + } RANDID5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of private per-device random number (ECC) */ + + struct { + __IM uint32_t RANDID6 : 16; /*!< RANDID6 */ + uint32_t : 16; + } bit; + } RANDID6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of private per-device random number (ECC) */ + + struct { + __IM uint32_t RANDID7 : 16; /*!< RANDID7 */ + uint32_t : 16; + } bit; + } RANDID7; + __IM uint32_t RESERVED[4]; + + union { + __IOM uint32_t reg; /*!< Ring oscillator frequency in kHz, measured during manufacturing + (ECC) This is measured at 1.1 V, at room temperature, with + the ROSC configuration registers in their reset state. */ + + struct { + __IM uint32_t ROSC_CALIB : 16; /*!< ROSC_CALIB */ + uint32_t : 16; + } bit; + } ROSC_CALIB; + + union { + __IOM uint32_t reg; /*!< Low-power oscillator frequency in Hz, measured during manufacturing + (ECC) This is measured at 1.1V, at room temperature, with + the LPOSC trim register in its reset state. */ + + struct { + __IM uint32_t LPOSC_CALIB : 16; /*!< LPOSC_CALIB */ + uint32_t : 16; + } bit; + } LPOSC_CALIB; + __IM uint32_t RESERVED1[6]; + + union { + __IOM uint32_t reg; /*!< The number of main user GPIOs (bank 0). Should read 48 in the + QFN80 package, and 30 in the QFN60 package. (ECC) */ + + struct { + __IM uint32_t NUM_GPIOS : 8; /*!< NUM_GPIOS */ + uint32_t : 24; + } bit; + } NUM_GPIOS; + __IM uint32_t RESERVED2[29]; + + union { + __IOM uint32_t reg; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial + 0x4c11db7, input reflected, output reflected, seed all-ones, + final XOR all-ones) (ECC) */ + + struct { + __IM uint32_t INFO_CRC0 : 16; /*!< INFO_CRC0 */ + uint32_t : 16; + } bit; + } INFO_CRC0; + + union { + __IOM uint32_t reg; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ + + struct { + __IM uint32_t INFO_CRC1 : 16; /*!< INFO_CRC1 */ + uint32_t : 16; + } bit; + } INFO_CRC1; + + union { + __IOM uint32_t reg; /*!< Page 0 critical boot flags (RBIT-8) */ + + struct { + __IM uint32_t ARM_DISABLE : 1; /*!< Permanently disable ARM processors (Cortex-M33) */ + __IM uint32_t RISCV_DISABLE : 1; /*!< Permanently disable RISC-V processors (Hazard3) */ + uint32_t : 30; + } bit; + } CRIT0; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT0 */ + + struct { + __IM uint32_t CRIT0_R1 : 24; /*!< CRIT0_R1 */ + uint32_t : 8; + } bit; + } CRIT0_R1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT0 */ + + struct { + __IM uint32_t CRIT0_R2 : 24; /*!< CRIT0_R2 */ + uint32_t : 8; + } bit; + } CRIT0_R2; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT0 */ + + struct { + __IM uint32_t CRIT0_R3 : 24; /*!< CRIT0_R3 */ + uint32_t : 8; + } bit; + } CRIT0_R3; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT0 */ + + struct { + __IM uint32_t CRIT0_R4 : 24; /*!< CRIT0_R4 */ + uint32_t : 8; + } bit; + } CRIT0_R4; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT0 */ + + struct { + __IM uint32_t CRIT0_R5 : 24; /*!< CRIT0_R5 */ + uint32_t : 8; + } bit; + } CRIT0_R5; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT0 */ + + struct { + __IM uint32_t CRIT0_R6 : 24; /*!< CRIT0_R6 */ + uint32_t : 8; + } bit; + } CRIT0_R6; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT0 */ + + struct { + __IM uint32_t CRIT0_R7 : 24; /*!< CRIT0_R7 */ + uint32_t : 8; + } bit; + } CRIT0_R7; + + union { + __IOM uint32_t reg; /*!< Page 1 critical boot flags (RBIT-8) */ + + struct { + __IM uint32_t SECURE_BOOT_ENABLE : 1; /*!< Enable boot signature enforcement, and permanently disable the + RISC-V cores. */ + __IM uint32_t SECURE_DEBUG_DISABLE : 1; /*!< Disable Secure debug access */ + __IM uint32_t DEBUG_DISABLE : 1; /*!< Disable all debug access */ + __IM uint32_t BOOT_ARCH : 1; /*!< Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if + ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. */ + __IM uint32_t GLITCH_DETECTOR_ENABLE : 1;/*!< Arm the glitch detectors to reset the system if an abnormal + clock/power event is observed. */ + __IM uint32_t GLITCH_DETECTOR_SENS : 2; /*!< Increase the sensitivity of the glitch detectors from their + default. */ + uint32_t : 25; + } bit; + } CRIT1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT1 */ + + struct { + __IM uint32_t CRIT1_R1 : 24; /*!< CRIT1_R1 */ + uint32_t : 8; + } bit; + } CRIT1_R1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT1 */ + + struct { + __IM uint32_t CRIT1_R2 : 24; /*!< CRIT1_R2 */ + uint32_t : 8; + } bit; + } CRIT1_R2; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT1 */ + + struct { + __IM uint32_t CRIT1_R3 : 24; /*!< CRIT1_R3 */ + uint32_t : 8; + } bit; + } CRIT1_R3; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT1 */ + + struct { + __IM uint32_t CRIT1_R4 : 24; /*!< CRIT1_R4 */ + uint32_t : 8; + } bit; + } CRIT1_R4; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT1 */ + + struct { + __IM uint32_t CRIT1_R5 : 24; /*!< CRIT1_R5 */ + uint32_t : 8; + } bit; + } CRIT1_R5; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT1 */ + + struct { + __IM uint32_t CRIT1_R6 : 24; /*!< CRIT1_R6 */ + uint32_t : 8; + } bit; + } CRIT1_R6; + + union { + __IOM uint32_t reg; /*!< Redundant copy of CRIT1 */ + + struct { + __IM uint32_t CRIT1_R7 : 24; /*!< CRIT1_R7 */ + uint32_t : 8; + } bit; + } CRIT1_R7; + + union { + __IOM uint32_t reg; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + always supersede enables. Enables are provided where there + are other configurations in OTP that must be valid. (RBIT-3) */ + + struct { + __IM uint32_t DISABLE_BOOTSEL_EXEC2 : 1; /*!< DISABLE_BOOTSEL_EXEC2 */ + __IM uint32_t ENABLE_BOOTSEL_LED : 1; /*!< Enable bootloader activity LED. If set, bootsel_led_cfg is assumed + to be valid */ + __IM uint32_t ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG : 1;/*!< Enable loading of the non-default XOSC and PLL configuration + before entering BOOTSEL mode. Ensure that BOOTSEL_XOSC_CFG + and BOOTSEL_PLL_CFG are correctly programmed before setting + this bit. If this bit is set, user software may use the + contents of BOOTSEL_PLL_CFG to calculated the expected + XOSC frequency based on the fixed USB boot frequency of + 48 MHz. */ + __IM uint32_t FLASH_IO_VOLTAGE_1V8 : 1; /*!< If 1, configure the QSPI pads for 1.8 V operation when accessing + flash for the first time from the bootrom, using the VOLTAGE_SELECT + register for the QSPI pads bank. This slightly improves + the input timing of the pads at low voltages, but does + not affect their output characteristics. If 0, leave VOLTAGE_SELECT + in its reset state (suitable for operation at and above + 2.5 V) */ + __IM uint32_t FAST_SIGCHECK_ROSC_DIV : 1;/*!< Enable quartering of ROSC divisor during signature check, to + reduce secure boot time */ + __IM uint32_t FLASH_DEVINFO_ENABLE : 1; /*!< Mark FLASH_DEVINFO as containing valid, ECC'd data which describes + external flash devices. */ + __IM uint32_t OVERRIDE_FLASH_PARTITION_SLOT_SIZE : 1;/*!< Override the limit for default flash metadata scanning. The + value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure + FLASH_PARTITION_SLOT_SIZE is valid before setting this + bit */ + __IM uint32_t SINGLE_FLASH_BINARY : 1; /*!< Restrict flash boot path to use of a single binary at the start + of flash */ + __IM uint32_t DISABLE_AUTO_SWITCH_ARCH : 1;/*!< Disable auto-switch of CPU architecture on boot when the (only) + binary to be booted is for the other Arm/RISC-V architecture + and both architectures are enabled */ + __IM uint32_t SECURE_PARTITION_TABLE : 1;/*!< Require a partition table to be signed */ + __IM uint32_t HASHED_PARTITION_TABLE : 1;/*!< Require a partition table to be hashed (if not signed) */ + __IM uint32_t ROLLBACK_REQUIRED : 1; /*!< Require binaries to have a rollback version. Set automatically + the first time a binary with a rollback version is booted. */ + __IM uint32_t DISABLE_FLASH_BOOT : 1; /*!< DISABLE_FLASH_BOOT */ + __IM uint32_t DISABLE_OTP_BOOT : 1; /*!< Takes precedence over ENABLE_OTP_BOOT. */ + __IM uint32_t ENABLE_OTP_BOOT : 1; /*!< Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN + will be loaded, starting from OTPBOOT_SRC, into the SRAM + location specified by OTPBOOT_DST1 and OTPBOOT_DST0. The + loaded program image is stored with ECC, 16 bits per row, + and must contain a valid IMAGE_DEF. Do not set this bit + without first programming an image into OTP and configuring + OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. + Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers + of OTP rows. Equivalently, the image must be a multiple + of 32 bits in size, and must start at a 32-bit-aligned + address in the ECC read data address window. */ + __IM uint32_t DISABLE_POWER_SCRATCH : 1; /*!< DISABLE_POWER_SCRATCH */ + __IM uint32_t DISABLE_WATCHDOG_SCRATCH : 1;/*!< DISABLE_WATCHDOG_SCRATCH */ + __IM uint32_t DISABLE_BOOTSEL_USB_MSD_IFC : 1;/*!< DISABLE_BOOTSEL_USB_MSD_IFC */ + __IM uint32_t DISABLE_BOOTSEL_USB_PICOBOOT_IFC : 1;/*!< DISABLE_BOOTSEL_USB_PICOBOOT_IFC */ + __IM uint32_t DISABLE_BOOTSEL_UART_BOOT : 1;/*!< DISABLE_BOOTSEL_UART_BOOT */ + __IM uint32_t DISABLE_XIP_ACCESS_ON_SRAM_ENTRY : 1;/*!< Disable all access to XIP after entering an SRAM binary. Note + that this will cause bootrom APIs that access XIP to fail, + including APIs that interact with the partition table. */ + __IM uint32_t DISABLE_SRAM_WINDOW_BOOT : 1;/*!< DISABLE_SRAM_WINDOW_BOOT */ + uint32_t : 10; + } bit; + } BOOT_FLAGS0; + + union { + __IOM uint32_t reg; /*!< Redundant copy of BOOT_FLAGS0 */ + + struct { + __IM uint32_t BOOT_FLAGS0_R1 : 24; /*!< BOOT_FLAGS0_R1 */ + uint32_t : 8; + } bit; + } BOOT_FLAGS0_R1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of BOOT_FLAGS0 */ + + struct { + __IM uint32_t BOOT_FLAGS0_R2 : 24; /*!< BOOT_FLAGS0_R2 */ + uint32_t : 8; + } bit; + } BOOT_FLAGS0_R2; + + union { + __IOM uint32_t reg; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + always supersede enables. Enables are provided where there + are other configurations in OTP that must be valid. (RBIT-3) */ + + struct { + __IM uint32_t KEY_VALID : 4; /*!< Mark each of the possible boot keys as valid. The bootrom will + check signatures against all valid boot keys, and ignore + invalid boot keys. Each bit in this field corresponds to + one of the four 256-bit boot key hashes that may be stored + in page 2 of the OTP. A KEY_VALID bit is ignored if the + corresponding KEY_INVALID bit is set. Boot keys are considered + valid only when KEY_VALID is set and KEY_INVALID is clear. + Do not mark a boot key as KEY_VALID if it does not contain + a valid SHA-256 hash of your secp256k1 public key. Verify + keys after programming, before setting the KEY_VALID bits + -- a boot key with uncorrectable ECC faults will render + your device unbootable if secure boot is enabled. Do not + enable secure boot without first installing a valid key. + This will render your device unbootable. */ + uint32_t : 4; + __IM uint32_t KEY_INVALID : 4; /*!< Mark a boot key as invalid, or prevent it from ever becoming + valid. The bootrom will ignore any boot key marked as invalid + during secure boot signature checks. Each bit in this field + corresponds to one of the four 256-bit boot key hashes + that may be stored in page 2 of the OTP. When provisioning + boot keys, it's recommended to mark any boot key slots + you don't intend to use as KEY_INVALID, so that spurious + keys can not be installed at a later time. */ + uint32_t : 4; + __IM uint32_t DOUBLE_TAP_DELAY : 3; /*!< Adjust how long to wait for a second reset when double tap BOOTSEL + mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, + and each unit of this field adds an additional 50 milliseconds. + For example, settings this field to its maximum value of + 7 will cause the chip to wait for 400 milliseconds at boot + to check for a second reset which requests entry to BOOTSEL + mode. 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate + value. */ + __IM uint32_t DOUBLE_TAP : 1; /*!< Enable entering BOOTSEL mode via double-tap of the RUN/RSTn + pin. Adds a significant delay to boot time, as configured + by DOUBLE_TAP_DELAY. This functions by waiting at startup + (i.e. following a reset) to see if a second reset is applied + soon afterward. The second reset is detected by the bootrom + with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which + is not reset by the external reset pin, and the bootrom + enters BOOTSEL mode (NSBOOT) to await further instruction + over USB or UART. */ + uint32_t : 12; + } bit; + } BOOT_FLAGS1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of BOOT_FLAGS1 */ + + struct { + __IM uint32_t BOOT_FLAGS1_R1 : 24; /*!< BOOT_FLAGS1_R1 */ + uint32_t : 8; + } bit; + } BOOT_FLAGS1_R1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of BOOT_FLAGS1 */ + + struct { + __IM uint32_t BOOT_FLAGS1_R2 : 24; /*!< BOOT_FLAGS1_R2 */ + uint32_t : 8; + } bit; + } BOOT_FLAGS1_R2; + + union { + __IOM uint32_t reg; /*!< Default boot version thermometer counter, bits 23:0 (RBIT-3) */ + + struct { + __IM uint32_t DEFAULT_BOOT_VERSION0 : 24;/*!< DEFAULT_BOOT_VERSION0 */ + uint32_t : 8; + } bit; + } DEFAULT_BOOT_VERSION0; + + union { + __IOM uint32_t reg; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ + + struct { + __IM uint32_t DEFAULT_BOOT_VERSION0_R1 : 24;/*!< DEFAULT_BOOT_VERSION0_R1 */ + uint32_t : 8; + } bit; + } DEFAULT_BOOT_VERSION0_R1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ + + struct { + __IM uint32_t DEFAULT_BOOT_VERSION0_R2 : 24;/*!< DEFAULT_BOOT_VERSION0_R2 */ + uint32_t : 8; + } bit; + } DEFAULT_BOOT_VERSION0_R2; + + union { + __IOM uint32_t reg; /*!< Default boot version thermometer counter, bits 47:24 (RBIT-3) */ + + struct { + __IM uint32_t DEFAULT_BOOT_VERSION1 : 24;/*!< DEFAULT_BOOT_VERSION1 */ + uint32_t : 8; + } bit; + } DEFAULT_BOOT_VERSION1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ + + struct { + __IM uint32_t DEFAULT_BOOT_VERSION1_R1 : 24;/*!< DEFAULT_BOOT_VERSION1_R1 */ + uint32_t : 8; + } bit; + } DEFAULT_BOOT_VERSION1_R1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ + + struct { + __IM uint32_t DEFAULT_BOOT_VERSION1_R2 : 24;/*!< DEFAULT_BOOT_VERSION1_R2 */ + uint32_t : 8; + } bit; + } DEFAULT_BOOT_VERSION1_R2; + + union { + __IOM uint32_t reg; /*!< Stores information about external flash device(s). (ECC) Assumed + to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ + + struct { + __IM uint32_t CS1_GPIO : 6; /*!< Indicate a GPIO number to be used for the secondary flash chip + select (CS1), which selects the external QSPI device mapped + at system addresses 0x11000000 through 0x11ffffff. There + is no such configuration for CS0, as the primary chip select + has a dedicated pin. On RP2350 the permissible GPIO numbers + are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE + is nonzero, the bootrom will automatically configure this + GPIO as a second chip select upon entering the flash boot + path, or entering any other path that may use the QSPI + flash interface, such as BOOTSEL mode (nsboot). */ + uint32_t : 1; + __IM uint32_t D8H_ERASE_SUPPORTED : 1; /*!< If true, all attached devices are assumed to support (or ignore, + in the case of PSRAM) a block erase command with a command + prefix of D8h, an erase size of 64 kiB, and a 24-bit address. + Almost all 25-series flash devices support this command. + If set, the bootrom will use the D8h erase command where + it is able, to accelerate bulk erase operations. This makes + flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE + is not set, this field defaults to false. */ + __IM uint32_t CS0_SIZE : 4; /*!< The size of the flash/PSRAM device on chip select 0 (addressable + at 0x10000000 through 0x10ffffff). A value of zero is decoded + as a size of zero (no device). Nonzero values are decoded + as 4kiB << CS0_SIZE. For example, four megabytes is encoded + with a CS0_SIZE value of 10, and 16 megabytes is encoded + with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE + is not set, a default of 12 (16 MiB) is used. */ + __IM uint32_t CS1_SIZE : 4; /*!< The size of the flash/PSRAM device on chip select 1 (addressable + at 0x11000000 through 0x11ffffff). A value of zero is decoded + as a size of zero (no device). Nonzero values are decoded + as 4kiB << CS1_SIZE. For example, four megabytes is encoded + with a CS1_SIZE value of 10, and 16 megabytes is encoded + with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE + is not set, a default of zero is used. */ + uint32_t : 16; + } bit; + } FLASH_DEVINFO; + + union { + __IOM uint32_t reg; /*!< Gap between partition table slot 0 and slot 1 at the start of + flash (the default size is 4096 bytes) (ECC) Enabled by + the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, + the size is 4096 * (value + 1) */ + + struct { + __IM uint32_t FLASH_PARTITION_SLOT_SIZE : 16;/*!< FLASH_PARTITION_SLOT_SIZE */ + uint32_t : 16; + } bit; + } FLASH_PARTITION_SLOT_SIZE; + + union { + __IOM uint32_t reg; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ + + struct { + __IM uint32_t PIN : 6; /*!< GPIO index to use for bootloader activity LED. */ + uint32_t : 2; + __IM uint32_t ACTIVELOW : 1; /*!< LED is active-low. (Default: active-high.) */ + uint32_t : 23; + } bit; + } BOOTSEL_LED_CFG; + + union { + __IOM uint32_t reg; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should + be configured to produce an exact 48 MHz based on the crystal + oscillator frequency. User mode software may also use this + value to calculate the expected crystal frequency based + on an assumed 48 MHz PLL output. If no configuration is + given, the crystal is assumed to be 12 MHz. The PLL frequency + can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) + x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal + frequency can be calculated as: XOSC frequency = 48 MHz + x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the + +1 on REFDIV is because the value stored in this OTP location + is the actual divisor value minus one.) Used if and only + if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. + That bit should be set only after this row and BOOTSEL_XOSC_CFG + are both correctly programmed. */ + + struct { + __IM uint32_t FBDIV : 9; /*!< PLL feedback divisor, in the range 16..320 inclusive. */ + __IM uint32_t POSTDIV1 : 3; /*!< PLL post-divide 1 divisor, in the range 1..7 inclusive. */ + __IM uint32_t POSTDIV2 : 3; /*!< PLL post-divide 2 divisor, in the range 1..7 inclusive. */ + __IM uint32_t REFDIV : 1; /*!< PLL reference divisor, minus one. Programming a value of 0 means + a reference divisor of 1. Programming a value of 1 means + a reference divisor of 2 (for exceptionally fast XIN inputs) */ + uint32_t : 16; + } bit; + } BOOTSEL_PLL_CFG; + + union { + __IOM uint32_t reg; /*!< Non-default crystal oscillator configuration for the USB bootloader. + (ECC) These values may also be used by user code configuring + the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL + _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set + only after this row and BOOTSEL_PLL_CFG are both correctly + programmed. */ + + struct { + __IM uint32_t STARTUP : 14; /*!< Value of the XOSC_STARTUP register */ + __IM uint32_t RANGE : 2; /*!< Value of the XOSC_CTRL_FREQ_RANGE register. */ + uint32_t : 16; + } bit; + } BOOTSEL_XOSC_CFG; + + union { + __IOM uint32_t reg; /*!< USB boot specific feature flags (RBIT-3) */ + + struct { + __IM uint32_t WL_USB_DEVICE_VID_VALUE_VALID : 1;/*!< valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL + struct (index 0) */ + __IM uint32_t WL_USB_DEVICE_PID_VALUE_VALID : 1;/*!< valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL + struct (index 1) */ + __IM uint32_t WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID : 1;/*!< valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL + struct (index 2) */ + __IM uint32_t WL_USB_DEVICE_LANG_ID_VALUE_VALID : 1;/*!< valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL + struct (index 3) */ + __IM uint32_t WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID : 1;/*!< valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL + struct (index 4) */ + __IM uint32_t WL_USB_DEVICE_PRODUCT_STRDEF_VALID : 1;/*!< valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL + struct (index 5) */ + __IM uint32_t WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID : 1;/*!< valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the + USB_WHITE_LABEL struct (index 6) */ + __IM uint32_t WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID : 1;/*!< valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry + of the USB_WHITE_LABEL struct (index 7) */ + __IM uint32_t WL_VOLUME_LABEL_STRDEF_VALID : 1;/*!< valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL + struct (index 8) */ + __IM uint32_t WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID : 1;/*!< valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL + struct (index 9) */ + __IM uint32_t WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID : 1;/*!< valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL + struct (index 10) */ + __IM uint32_t WL_SCSI_INQUIRY_VERSION_STRDEF_VALID : 1;/*!< valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL + struct (index 11) */ + __IM uint32_t WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID : 1;/*!< valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL + struct (index 12) */ + __IM uint32_t WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID : 1;/*!< valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL + struct (index 13) */ + __IM uint32_t WL_INFO_UF2_TXT_MODEL_STRDEF_VALID : 1;/*!< valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL + struct (index 14) */ + __IM uint32_t WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID : 1;/*!< valid flag for the USB_WHITE_LABEL_ADDR field */ + uint32_t : 6; + __IM uint32_t WHITE_LABEL_ADDR_VALID : 1;/*!< valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL + struct (index 15) */ + __IM uint32_t DP_DM_SWAP : 1; /*!< Swap DM/DP during USB boot, to support board layouts with mirrored + USB routing (deliberate or accidental). */ + uint32_t : 8; + } bit; + } USB_BOOT_FLAGS; + + union { + __IOM uint32_t reg; /*!< Redundant copy of USB_BOOT_FLAGS */ + + struct { + __IM uint32_t USB_BOOT_FLAGS_R1 : 24; /*!< USB_BOOT_FLAGS_R1 */ + uint32_t : 8; + } bit; + } USB_BOOT_FLAGS_R1; + + union { + __IOM uint32_t reg; /*!< Redundant copy of USB_BOOT_FLAGS */ + + struct { + __IM uint32_t USB_BOOT_FLAGS_R2 : 24; /*!< USB_BOOT_FLAGS_R2 */ + uint32_t : 8; + } bit; + } USB_BOOT_FLAGS_R2; + + union { + __IOM uint32_t reg; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) + The table has 16 rows, each of which are also ECC and marked + valid by the corresponding valid bit in USB_BOOT_FLAGS + (ECC). The entries are either _VALUEs where the 16 bit + value is used as is, or _STRDEFs which acts as a pointers + to a string value. The value stored in a _STRDEF is two + separate bytes: The low seven bits of the first (LSB) byte + indicates the number of characters in the string, and the + top bit of the first (LSB) byte if set to indicate that + each character in the string is two bytes (Unicode) versus + one byte if unset. The second (MSB) byte represents the + location of the string data, and is encoded as the number + of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of + the start of the string is USB_WHITE_LABEL_ADDR value + + msb_byte. In each case, the corresponding valid bit enables + replacing the default value for the corresponding item + provided by the boot rom. Note that Unicode _STRDEFs are + only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST + DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values + will be ignored if specified for other fields, and non-unicode + values for these three items will be converted to Unicode + characters by setting the upper 8 bits to zero. Note that + if the USB_WHITE_LABEL structure or the corresponding strings + are not readable by BOOTSEL mode based on OTP permissions, + or if alignment requirements are not met, then the corresponding + default values are used. The index values indicate where + each field is located (row USB_WHITE_LABEL_ADDR value + + index): */ + + struct { + __IM uint32_t USB_WHITE_LABEL_ADDR : 16; /*!< USB_WHITE_LABEL_ADDR */ + uint32_t : 16; + } bit; + } USB_WHITE_LABEL_ADDR; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t reg; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, + the bootrom will load from this location into SRAM and + then directly enter the loaded image. Note that the image + must be signed if SECURE_BOOT_ENABLE is set. The image + itself is assumed to be ECC-protected. This must be an + even number. Equivalently, the OTP boot image must start + at a word-aligned location in the ECC read data address + window. */ + + struct { + __IM uint32_t OTPBOOT_SRC : 16; /*!< OTPBOOT_SRC */ + uint32_t : 16; + } bit; + } OTPBOOT_SRC; + + union { + __IOM uint32_t reg; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must + be even. The total image size must be a multiple of 4 bytes + (32 bits). */ + + struct { + __IM uint32_t OTPBOOT_LEN : 16; /*!< OTPBOOT_LEN */ + uint32_t : 16; + } bit; + } OTPBOOT_LEN; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + + struct { + __IM uint32_t OTPBOOT_DST0 : 16; /*!< OTPBOOT_DST0 */ + uint32_t : 16; + } bit; + } OTPBOOT_DST0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + + struct { + __IM uint32_t OTPBOOT_DST1 : 16; /*!< OTPBOOT_DST1 */ + uint32_t : 16; + } bit; + } OTPBOOT_DST1; + __IM uint32_t RESERVED4[30]; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_0 : 16; /*!< BOOTKEY0_0 */ + uint32_t : 16; + } bit; + } BOOTKEY0_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_1 : 16; /*!< BOOTKEY0_1 */ + uint32_t : 16; + } bit; + } BOOTKEY0_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_2 : 16; /*!< BOOTKEY0_2 */ + uint32_t : 16; + } bit; + } BOOTKEY0_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_3 : 16; /*!< BOOTKEY0_3 */ + uint32_t : 16; + } bit; + } BOOTKEY0_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_4 : 16; /*!< BOOTKEY0_4 */ + uint32_t : 16; + } bit; + } BOOTKEY0_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_5 : 16; /*!< BOOTKEY0_5 */ + uint32_t : 16; + } bit; + } BOOTKEY0_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_6 : 16; /*!< BOOTKEY0_6 */ + uint32_t : 16; + } bit; + } BOOTKEY0_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_7 : 16; /*!< BOOTKEY0_7 */ + uint32_t : 16; + } bit; + } BOOTKEY0_7; + + union { + __IOM uint32_t reg; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_8 : 16; /*!< BOOTKEY0_8 */ + uint32_t : 16; + } bit; + } BOOTKEY0_8; + + union { + __IOM uint32_t reg; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_9 : 16; /*!< BOOTKEY0_9 */ + uint32_t : 16; + } bit; + } BOOTKEY0_9; + + union { + __IOM uint32_t reg; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_10 : 16; /*!< BOOTKEY0_10 */ + uint32_t : 16; + } bit; + } BOOTKEY0_10; + + union { + __IOM uint32_t reg; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_11 : 16; /*!< BOOTKEY0_11 */ + uint32_t : 16; + } bit; + } BOOTKEY0_11; + + union { + __IOM uint32_t reg; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_12 : 16; /*!< BOOTKEY0_12 */ + uint32_t : 16; + } bit; + } BOOTKEY0_12; + + union { + __IOM uint32_t reg; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_13 : 16; /*!< BOOTKEY0_13 */ + uint32_t : 16; + } bit; + } BOOTKEY0_13; + + union { + __IOM uint32_t reg; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_14 : 16; /*!< BOOTKEY0_14 */ + uint32_t : 16; + } bit; + } BOOTKEY0_14; + + union { + __IOM uint32_t reg; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ + + struct { + __IM uint32_t BOOTKEY0_15 : 16; /*!< BOOTKEY0_15 */ + uint32_t : 16; + } bit; + } BOOTKEY0_15; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_0 : 16; /*!< BOOTKEY1_0 */ + uint32_t : 16; + } bit; + } BOOTKEY1_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_1 : 16; /*!< BOOTKEY1_1 */ + uint32_t : 16; + } bit; + } BOOTKEY1_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_2 : 16; /*!< BOOTKEY1_2 */ + uint32_t : 16; + } bit; + } BOOTKEY1_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_3 : 16; /*!< BOOTKEY1_3 */ + uint32_t : 16; + } bit; + } BOOTKEY1_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_4 : 16; /*!< BOOTKEY1_4 */ + uint32_t : 16; + } bit; + } BOOTKEY1_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_5 : 16; /*!< BOOTKEY1_5 */ + uint32_t : 16; + } bit; + } BOOTKEY1_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_6 : 16; /*!< BOOTKEY1_6 */ + uint32_t : 16; + } bit; + } BOOTKEY1_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_7 : 16; /*!< BOOTKEY1_7 */ + uint32_t : 16; + } bit; + } BOOTKEY1_7; + + union { + __IOM uint32_t reg; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_8 : 16; /*!< BOOTKEY1_8 */ + uint32_t : 16; + } bit; + } BOOTKEY1_8; + + union { + __IOM uint32_t reg; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_9 : 16; /*!< BOOTKEY1_9 */ + uint32_t : 16; + } bit; + } BOOTKEY1_9; + + union { + __IOM uint32_t reg; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_10 : 16; /*!< BOOTKEY1_10 */ + uint32_t : 16; + } bit; + } BOOTKEY1_10; + + union { + __IOM uint32_t reg; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_11 : 16; /*!< BOOTKEY1_11 */ + uint32_t : 16; + } bit; + } BOOTKEY1_11; + + union { + __IOM uint32_t reg; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_12 : 16; /*!< BOOTKEY1_12 */ + uint32_t : 16; + } bit; + } BOOTKEY1_12; + + union { + __IOM uint32_t reg; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_13 : 16; /*!< BOOTKEY1_13 */ + uint32_t : 16; + } bit; + } BOOTKEY1_13; + + union { + __IOM uint32_t reg; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_14 : 16; /*!< BOOTKEY1_14 */ + uint32_t : 16; + } bit; + } BOOTKEY1_14; + + union { + __IOM uint32_t reg; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ + + struct { + __IM uint32_t BOOTKEY1_15 : 16; /*!< BOOTKEY1_15 */ + uint32_t : 16; + } bit; + } BOOTKEY1_15; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_0 : 16; /*!< BOOTKEY2_0 */ + uint32_t : 16; + } bit; + } BOOTKEY2_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_1 : 16; /*!< BOOTKEY2_1 */ + uint32_t : 16; + } bit; + } BOOTKEY2_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_2 : 16; /*!< BOOTKEY2_2 */ + uint32_t : 16; + } bit; + } BOOTKEY2_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_3 : 16; /*!< BOOTKEY2_3 */ + uint32_t : 16; + } bit; + } BOOTKEY2_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_4 : 16; /*!< BOOTKEY2_4 */ + uint32_t : 16; + } bit; + } BOOTKEY2_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_5 : 16; /*!< BOOTKEY2_5 */ + uint32_t : 16; + } bit; + } BOOTKEY2_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_6 : 16; /*!< BOOTKEY2_6 */ + uint32_t : 16; + } bit; + } BOOTKEY2_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_7 : 16; /*!< BOOTKEY2_7 */ + uint32_t : 16; + } bit; + } BOOTKEY2_7; + + union { + __IOM uint32_t reg; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_8 : 16; /*!< BOOTKEY2_8 */ + uint32_t : 16; + } bit; + } BOOTKEY2_8; + + union { + __IOM uint32_t reg; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_9 : 16; /*!< BOOTKEY2_9 */ + uint32_t : 16; + } bit; + } BOOTKEY2_9; + + union { + __IOM uint32_t reg; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_10 : 16; /*!< BOOTKEY2_10 */ + uint32_t : 16; + } bit; + } BOOTKEY2_10; + + union { + __IOM uint32_t reg; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_11 : 16; /*!< BOOTKEY2_11 */ + uint32_t : 16; + } bit; + } BOOTKEY2_11; + + union { + __IOM uint32_t reg; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_12 : 16; /*!< BOOTKEY2_12 */ + uint32_t : 16; + } bit; + } BOOTKEY2_12; + + union { + __IOM uint32_t reg; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_13 : 16; /*!< BOOTKEY2_13 */ + uint32_t : 16; + } bit; + } BOOTKEY2_13; + + union { + __IOM uint32_t reg; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_14 : 16; /*!< BOOTKEY2_14 */ + uint32_t : 16; + } bit; + } BOOTKEY2_14; + + union { + __IOM uint32_t reg; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ + + struct { + __IM uint32_t BOOTKEY2_15 : 16; /*!< BOOTKEY2_15 */ + uint32_t : 16; + } bit; + } BOOTKEY2_15; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_0 : 16; /*!< BOOTKEY3_0 */ + uint32_t : 16; + } bit; + } BOOTKEY3_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_1 : 16; /*!< BOOTKEY3_1 */ + uint32_t : 16; + } bit; + } BOOTKEY3_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_2 : 16; /*!< BOOTKEY3_2 */ + uint32_t : 16; + } bit; + } BOOTKEY3_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_3 : 16; /*!< BOOTKEY3_3 */ + uint32_t : 16; + } bit; + } BOOTKEY3_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_4 : 16; /*!< BOOTKEY3_4 */ + uint32_t : 16; + } bit; + } BOOTKEY3_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_5 : 16; /*!< BOOTKEY3_5 */ + uint32_t : 16; + } bit; + } BOOTKEY3_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_6 : 16; /*!< BOOTKEY3_6 */ + uint32_t : 16; + } bit; + } BOOTKEY3_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_7 : 16; /*!< BOOTKEY3_7 */ + uint32_t : 16; + } bit; + } BOOTKEY3_7; + + union { + __IOM uint32_t reg; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_8 : 16; /*!< BOOTKEY3_8 */ + uint32_t : 16; + } bit; + } BOOTKEY3_8; + + union { + __IOM uint32_t reg; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_9 : 16; /*!< BOOTKEY3_9 */ + uint32_t : 16; + } bit; + } BOOTKEY3_9; + + union { + __IOM uint32_t reg; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_10 : 16; /*!< BOOTKEY3_10 */ + uint32_t : 16; + } bit; + } BOOTKEY3_10; + + union { + __IOM uint32_t reg; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_11 : 16; /*!< BOOTKEY3_11 */ + uint32_t : 16; + } bit; + } BOOTKEY3_11; + + union { + __IOM uint32_t reg; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_12 : 16; /*!< BOOTKEY3_12 */ + uint32_t : 16; + } bit; + } BOOTKEY3_12; + + union { + __IOM uint32_t reg; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_13 : 16; /*!< BOOTKEY3_13 */ + uint32_t : 16; + } bit; + } BOOTKEY3_13; + + union { + __IOM uint32_t reg; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_14 : 16; /*!< BOOTKEY3_14 */ + uint32_t : 16; + } bit; + } BOOTKEY3_14; + + union { + __IOM uint32_t reg; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ + + struct { + __IM uint32_t BOOTKEY3_15 : 16; /*!< BOOTKEY3_15 */ + uint32_t : 16; + } bit; + } BOOTKEY3_15; + __IM uint32_t RESERVED5[3720]; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of OTP access key 1 (ECC) */ + + struct { + __IM uint32_t KEY1_0 : 16; /*!< KEY1_0 */ + uint32_t : 16; + } bit; + } KEY1_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of OTP access key 1 (ECC) */ + + struct { + __IM uint32_t KEY1_1 : 16; /*!< KEY1_1 */ + uint32_t : 16; + } bit; + } KEY1_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of OTP access key 1 (ECC) */ + + struct { + __IM uint32_t KEY1_2 : 16; /*!< KEY1_2 */ + uint32_t : 16; + } bit; + } KEY1_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of OTP access key 1 (ECC) */ + + struct { + __IM uint32_t KEY1_3 : 16; /*!< KEY1_3 */ + uint32_t : 16; + } bit; + } KEY1_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of OTP access key 1 (ECC) */ + + struct { + __IM uint32_t KEY1_4 : 16; /*!< KEY1_4 */ + uint32_t : 16; + } bit; + } KEY1_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of OTP access key 1 (ECC) */ + + struct { + __IM uint32_t KEY1_5 : 16; /*!< KEY1_5 */ + uint32_t : 16; + } bit; + } KEY1_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of OTP access key 1 (ECC) */ + + struct { + __IM uint32_t KEY1_6 : 16; /*!< KEY1_6 */ + uint32_t : 16; + } bit; + } KEY1_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of OTP access key 1 (ECC) */ + + struct { + __IM uint32_t KEY1_7 : 16; /*!< KEY1_7 */ + uint32_t : 16; + } bit; + } KEY1_7; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of OTP access key 2 (ECC) */ + + struct { + __IM uint32_t KEY2_0 : 16; /*!< KEY2_0 */ + uint32_t : 16; + } bit; + } KEY2_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of OTP access key 2 (ECC) */ + + struct { + __IM uint32_t KEY2_1 : 16; /*!< KEY2_1 */ + uint32_t : 16; + } bit; + } KEY2_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of OTP access key 2 (ECC) */ + + struct { + __IM uint32_t KEY2_2 : 16; /*!< KEY2_2 */ + uint32_t : 16; + } bit; + } KEY2_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of OTP access key 2 (ECC) */ + + struct { + __IM uint32_t KEY2_3 : 16; /*!< KEY2_3 */ + uint32_t : 16; + } bit; + } KEY2_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of OTP access key 2 (ECC) */ + + struct { + __IM uint32_t KEY2_4 : 16; /*!< KEY2_4 */ + uint32_t : 16; + } bit; + } KEY2_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of OTP access key 2 (ECC) */ + + struct { + __IM uint32_t KEY2_5 : 16; /*!< KEY2_5 */ + uint32_t : 16; + } bit; + } KEY2_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of OTP access key 2 (ECC) */ + + struct { + __IM uint32_t KEY2_6 : 16; /*!< KEY2_6 */ + uint32_t : 16; + } bit; + } KEY2_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of OTP access key 2 (ECC) */ + + struct { + __IM uint32_t KEY2_7 : 16; /*!< KEY2_7 */ + uint32_t : 16; + } bit; + } KEY2_7; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of OTP access key 3 (ECC) */ + + struct { + __IM uint32_t KEY3_0 : 16; /*!< KEY3_0 */ + uint32_t : 16; + } bit; + } KEY3_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of OTP access key 3 (ECC) */ + + struct { + __IM uint32_t KEY3_1 : 16; /*!< KEY3_1 */ + uint32_t : 16; + } bit; + } KEY3_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of OTP access key 3 (ECC) */ + + struct { + __IM uint32_t KEY3_2 : 16; /*!< KEY3_2 */ + uint32_t : 16; + } bit; + } KEY3_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of OTP access key 3 (ECC) */ + + struct { + __IM uint32_t KEY3_3 : 16; /*!< KEY3_3 */ + uint32_t : 16; + } bit; + } KEY3_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of OTP access key 3 (ECC) */ + + struct { + __IM uint32_t KEY3_4 : 16; /*!< KEY3_4 */ + uint32_t : 16; + } bit; + } KEY3_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of OTP access key 3 (ECC) */ + + struct { + __IM uint32_t KEY3_5 : 16; /*!< KEY3_5 */ + uint32_t : 16; + } bit; + } KEY3_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of OTP access key 3 (ECC) */ + + struct { + __IM uint32_t KEY3_6 : 16; /*!< KEY3_6 */ + uint32_t : 16; + } bit; + } KEY3_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of OTP access key 3 (ECC) */ + + struct { + __IM uint32_t KEY3_7 : 16; /*!< KEY3_7 */ + uint32_t : 16; + } bit; + } KEY3_7; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of OTP access key 4 (ECC) */ + + struct { + __IM uint32_t KEY4_0 : 16; /*!< KEY4_0 */ + uint32_t : 16; + } bit; + } KEY4_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of OTP access key 4 (ECC) */ + + struct { + __IM uint32_t KEY4_1 : 16; /*!< KEY4_1 */ + uint32_t : 16; + } bit; + } KEY4_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of OTP access key 4 (ECC) */ + + struct { + __IM uint32_t KEY4_2 : 16; /*!< KEY4_2 */ + uint32_t : 16; + } bit; + } KEY4_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of OTP access key 4 (ECC) */ + + struct { + __IM uint32_t KEY4_3 : 16; /*!< KEY4_3 */ + uint32_t : 16; + } bit; + } KEY4_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of OTP access key 4 (ECC) */ + + struct { + __IM uint32_t KEY4_4 : 16; /*!< KEY4_4 */ + uint32_t : 16; + } bit; + } KEY4_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of OTP access key 4 (ECC) */ + + struct { + __IM uint32_t KEY4_5 : 16; /*!< KEY4_5 */ + uint32_t : 16; + } bit; + } KEY4_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of OTP access key 4 (ECC) */ + + struct { + __IM uint32_t KEY4_6 : 16; /*!< KEY4_6 */ + uint32_t : 16; + } bit; + } KEY4_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of OTP access key 4 (ECC) */ + + struct { + __IM uint32_t KEY4_7 : 16; /*!< KEY4_7 */ + uint32_t : 16; + } bit; + } KEY4_7; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of OTP access key 5 (ECC) */ + + struct { + __IM uint32_t KEY5_0 : 16; /*!< KEY5_0 */ + uint32_t : 16; + } bit; + } KEY5_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of OTP access key 5 (ECC) */ + + struct { + __IM uint32_t KEY5_1 : 16; /*!< KEY5_1 */ + uint32_t : 16; + } bit; + } KEY5_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of OTP access key 5 (ECC) */ + + struct { + __IM uint32_t KEY5_2 : 16; /*!< KEY5_2 */ + uint32_t : 16; + } bit; + } KEY5_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of OTP access key 5 (ECC) */ + + struct { + __IM uint32_t KEY5_3 : 16; /*!< KEY5_3 */ + uint32_t : 16; + } bit; + } KEY5_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of OTP access key 5 (ECC) */ + + struct { + __IM uint32_t KEY5_4 : 16; /*!< KEY5_4 */ + uint32_t : 16; + } bit; + } KEY5_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of OTP access key 5 (ECC) */ + + struct { + __IM uint32_t KEY5_5 : 16; /*!< KEY5_5 */ + uint32_t : 16; + } bit; + } KEY5_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of OTP access key 5 (ECC) */ + + struct { + __IM uint32_t KEY5_6 : 16; /*!< KEY5_6 */ + uint32_t : 16; + } bit; + } KEY5_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of OTP access key 5 (ECC) */ + + struct { + __IM uint32_t KEY5_7 : 16; /*!< KEY5_7 */ + uint32_t : 16; + } bit; + } KEY5_7; + + union { + __IOM uint32_t reg; /*!< Bits 15:0 of OTP access key 6 (ECC) */ + + struct { + __IM uint32_t KEY6_0 : 16; /*!< KEY6_0 */ + uint32_t : 16; + } bit; + } KEY6_0; + + union { + __IOM uint32_t reg; /*!< Bits 31:16 of OTP access key 6 (ECC) */ + + struct { + __IM uint32_t KEY6_1 : 16; /*!< KEY6_1 */ + uint32_t : 16; + } bit; + } KEY6_1; + + union { + __IOM uint32_t reg; /*!< Bits 47:32 of OTP access key 6 (ECC) */ + + struct { + __IM uint32_t KEY6_2 : 16; /*!< KEY6_2 */ + uint32_t : 16; + } bit; + } KEY6_2; + + union { + __IOM uint32_t reg; /*!< Bits 63:48 of OTP access key 6 (ECC) */ + + struct { + __IM uint32_t KEY6_3 : 16; /*!< KEY6_3 */ + uint32_t : 16; + } bit; + } KEY6_3; + + union { + __IOM uint32_t reg; /*!< Bits 79:64 of OTP access key 6 (ECC) */ + + struct { + __IM uint32_t KEY6_4 : 16; /*!< KEY6_4 */ + uint32_t : 16; + } bit; + } KEY6_4; + + union { + __IOM uint32_t reg; /*!< Bits 95:80 of OTP access key 6 (ECC) */ + + struct { + __IM uint32_t KEY6_5 : 16; /*!< KEY6_5 */ + uint32_t : 16; + } bit; + } KEY6_5; + + union { + __IOM uint32_t reg; /*!< Bits 111:96 of OTP access key 6 (ECC) */ + + struct { + __IM uint32_t KEY6_6 : 16; /*!< KEY6_6 */ + uint32_t : 16; + } bit; + } KEY6_6; + + union { + __IOM uint32_t reg; /*!< Bits 127:112 of OTP access key 6 (ECC) */ + + struct { + __IM uint32_t KEY6_7 : 16; /*!< KEY6_7 */ + uint32_t : 16; + } bit; + } KEY6_7; + __IM uint32_t RESERVED6; + + union { + __IOM uint32_t reg; /*!< Valid flag for key 1. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + + struct { + __IM uint32_t VALID : 1; /*!< VALID */ + uint32_t : 7; + __IM uint32_t VALID_R1 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 7; + __IM uint32_t VALID_R2 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 15; + } bit; + } KEY1_VALID; + + union { + __IOM uint32_t reg; /*!< Valid flag for key 2. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + + struct { + __IM uint32_t VALID : 1; /*!< VALID */ + uint32_t : 7; + __IM uint32_t VALID_R1 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 7; + __IM uint32_t VALID_R2 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 15; + } bit; + } KEY2_VALID; + + union { + __IOM uint32_t reg; /*!< Valid flag for key 3. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + + struct { + __IM uint32_t VALID : 1; /*!< VALID */ + uint32_t : 7; + __IM uint32_t VALID_R1 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 7; + __IM uint32_t VALID_R2 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 15; + } bit; + } KEY3_VALID; + + union { + __IOM uint32_t reg; /*!< Valid flag for key 4. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + + struct { + __IM uint32_t VALID : 1; /*!< VALID */ + uint32_t : 7; + __IM uint32_t VALID_R1 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 7; + __IM uint32_t VALID_R2 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 15; + } bit; + } KEY4_VALID; + + union { + __IOM uint32_t reg; /*!< Valid flag for key 5. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + + struct { + __IM uint32_t VALID : 1; /*!< VALID */ + uint32_t : 7; + __IM uint32_t VALID_R1 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 7; + __IM uint32_t VALID_R2 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 15; + } bit; + } KEY5_VALID; + + union { + __IOM uint32_t reg; /*!< Valid flag for key 6. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + + struct { + __IM uint32_t VALID : 1; /*!< VALID */ + uint32_t : 7; + __IM uint32_t VALID_R1 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 7; + __IM uint32_t VALID_R2 : 1; /*!< Redundant copy of VALID, with 3-way majority vote */ + uint32_t : 15; + } bit; + } KEY6_VALID; + __IM uint32_t RESERVED7; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE0_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE0_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE1_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE1_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE2_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE2_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE3_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE3_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE4_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE4_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE5_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE5_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE6_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE6_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE7_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE7_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE8_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE8_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE9_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE9_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE10_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE10_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE11_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE11_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE12_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE12_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE13_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE13_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE14_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE14_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE15_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE15_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE16_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE16_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE17_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE17_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE18_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE18_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE19_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE19_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE20_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE20_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE21_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE21_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE22_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE22_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE23_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE23_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE24_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE24_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE25_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE25_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE26_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE26_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE27_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE27_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE28_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE28_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE29_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE29_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE30_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE30_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE31_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE31_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE32_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE32_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE33_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE33_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE34_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE34_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE35_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE35_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE36_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE36_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE37_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE37_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE38_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE38_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE39_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE39_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE40_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE40_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE41_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE41_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE42_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE42_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE43_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE43_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE44_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE44_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE45_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE45_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE46_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE46_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE47_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE47_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE48_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE48_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE49_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE49_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE50_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE50_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE51_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE51_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE52_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE52_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE53_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE53_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE54_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE54_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE55_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE55_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE56_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE56_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE57_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE57_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE58_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE58_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE59_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE59_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE60_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE60_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE61_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE61_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + uint32_t : 1; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE62_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE62_LOCK1; + + union { + __IOM uint32_t reg; /*!< Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t KEY_W : 3; /*!< Index 1-6 of a hardware key which must be entered to grant write + access, or 0 if no such key is required. */ + __IM uint32_t KEY_R : 3; /*!< Index 1-6 of a hardware key which must be entered to grant read + access, or 0 if no such key is required. */ + __IM uint32_t NO_KEY_STATE : 1; /*!< State when at least one key is registered for this page and + no matching key has been entered. */ + __IM uint32_t RMA : 1; /*!< Decommission for RMA of a suspected faulty device. This re-enables + the factory test JTAG interface, and makes pages 3 through + 61 of the OTP permanently inaccessible. */ + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE63_LOCK0; + + union { + __IOM uint32_t reg; /*!< Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + + struct { + __IM uint32_t LOCK_S : 2; /*!< Lock state for Secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. */ + __IM uint32_t LOCK_NS : 2; /*!< Lock state for Non-secure accesses to this page. Thermometer-coded, + so lock state can be advanced permanently from any state + to any less-permissive state by programming OTP. Software + can also advance the lock state temporarily (until next + OTP reset) using the SW_LOCKx registers. Note that READ_WRITE + and READ_ONLY are equivalent in hardware, as the SBPI programming + interface is not accessible to Non-secure software. However, + Secure software may check these bits to apply write permissions + to a Non-secure OTP programming API. */ + __IM uint32_t LOCK_BL : 2; /*!< Dummy lock bits reserved for bootloaders (including the RP2350 + USB bootloader) to store their own OTP access permissions. + No hardware effect, and no corresponding SW_LOCKx registers. */ + uint32_t : 2; + __IM uint32_t R1 : 8; /*!< Redundant copy of bits 7:0 */ + __IM uint32_t R2 : 8; /*!< Redundant copy of bits 7:0 */ + uint32_t : 8; + } bit; + } PAGE63_LOCK1; +} OTP_DATA_RAW_Type; /*!< Size = 16384 (0x4000) */ + + + +/* =========================================================================================================================== */ +/* ================ TBMAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief For managing simulation testbenches (TBMAN) + */ + +typedef struct { /*!< TBMAN Structure */ + + union { + __IOM uint32_t reg; /*!< Indicates the type of platform in use */ + + struct { + __IM uint32_t ASIC : 1; /*!< Indicates the platform is an ASIC */ + __IM uint32_t FPGA : 1; /*!< Indicates the platform is an FPGA */ + __IM uint32_t HDLSIM : 1; /*!< Indicates the platform is a simulation */ + uint32_t : 29; + } bit; + } PLATFORM; +} TBMAN_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ USB_DPRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DPRAM layout for USB device. (USB_DPRAM) + */ + +typedef struct { /*!< USB_DPRAM Structure */ + + union { + __IOM uint32_t reg; /*!< Bytes 0-3 of the SETUP packet from the host. */ + + struct { + __IOM uint32_t BMREQUESTTYPE : 8; /*!< BMREQUESTTYPE */ + __IOM uint32_t BREQUEST : 8; /*!< BREQUEST */ + __IOM uint32_t WVALUE : 16; /*!< WVALUE */ + } bit; + } SETUP_PACKET_LOW; + + union { + __IOM uint32_t reg; /*!< Bytes 4-7 of the setup packet from the host. */ + + struct { + __IOM uint32_t WINDEX : 16; /*!< WINDEX */ + __IOM uint32_t WLENGTH : 16; /*!< WLENGTH */ + } bit; + } SETUP_PACKET_HIGH; + + union { + __IOM uint32_t reg; /*!< EP1_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP1_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP1_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP1_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP2_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP2_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP2_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP2_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP3_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP3_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP3_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP3_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP4_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP4_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP4_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP4_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP5_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP5_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP5_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP5_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP6_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP6_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP6_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP6_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP7_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP7_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP7_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP7_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP8_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP8_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP8_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP8_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP9_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP9_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP9_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP9_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP10_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP10_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP10_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP10_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP11_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP11_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP11_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP11_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP12_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP12_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP12_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP12_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP13_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP13_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP13_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP13_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP14_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP14_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP14_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP14_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP15_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP15_IN_CONTROL; + + union { + __IOM uint32_t reg; /*!< EP15_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< Trigger an interrupt if a NAK is sent. Intended for debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< Trigger an interrupt if a STALL is sent. Intended for debug + only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< Trigger an interrupt each time both buffers are done. Only valid + in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< Enable this endpoint. The device will not reply to any packets + for this endpoint if this bit is not set. */ + } bit; + } EP15_OUT_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP0_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP0_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP1_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP1_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP2_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP2_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP3_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP3_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP4_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP4_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP5_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP5_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP6_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP6_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP7_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP7_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP8_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP8_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP9_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP9_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP10_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP10_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP11_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP11_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP12_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP12_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP13_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP13_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP14_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP14_OUT_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP15_IN_BUFFER_CONTROL; + + union { + __IOM uint32_t reg; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< Buffer 0 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< Buffer 0 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< Buffer 1 is available. This bit is set to indicate the buffer + can be used by the controller. The controller clears the + available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< The number of bytes buffer 1 is offset from buffer 0 in Isochronous + mode. Only valid in double buffered mode for an Isochronous + endpoint. For a non Isochronous endpoint the offset is + always 64 bytes. */ + __IOM uint32_t PID_1 : 1; /*!< The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< Buffer 1 is full. For an IN transfer (TX to the host) the bit + is set to indicate the data is valid. For an OUT transfer + (RX from the host) this bit should be left as a 0. The + host will set it when it has filled the buffer with data. */ + } bit; + } EP15_OUT_BUFFER_CONTROL; +} USB_DPRAM_Type; /*!< Size = 256 (0x100) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define RESETS_BASE 0x40020000UL +#define PSM_BASE 0x40018000UL +#define CLOCKS_BASE 0x40010000UL +#define TICKS_BASE 0x40108000UL +#define PADS_BANK0_BASE 0x40038000UL +#define PADS_QSPI_BASE 0x40040000UL +#define IO_QSPI_BASE 0x40030000UL +#define IO_BANK0_BASE 0x40028000UL +#define SYSINFO_BASE 0x40000000UL +#define SHA256_BASE 0x400F8000UL +#define HSTX_FIFO_BASE 0x50600000UL +#define HSTX_CTRL_BASE 0x400C0000UL +#define EPPB_BASE 0xE0080000UL +#define PPB_BASE 0xE0000000UL +#define PPB_NS_BASE 0xE0020000UL +#define QMI_BASE 0x400D0000UL +#define XIP_CTRL_BASE 0x400C8000UL +#define XIP_AUX_BASE 0x50500000UL +#define SYSCFG_BASE 0x40008000UL +#define XOSC_BASE 0x40048000UL +#define PLL_SYS_BASE 0x40050000UL +#define PLL_USB_BASE 0x40058000UL +#define ACCESSCTRL_BASE 0x40060000UL +#define UART0_BASE 0x40070000UL +#define UART1_BASE 0x40078000UL +#define ROSC_BASE 0x400E8000UL +#define POWMAN_BASE 0x40100000UL +#define WATCHDOG_BASE 0x400D8000UL +#define DMA_BASE 0x50000000UL +#define TIMER0_BASE 0x400B0000UL +#define TIMER1_BASE 0x400B8000UL +#define PWM_BASE 0x400A8000UL +#define ADC_BASE 0x400A0000UL +#define I2C0_BASE 0x40090000UL +#define I2C1_BASE 0x40098000UL +#define SPI0_BASE 0x40080000UL +#define SPI1_BASE 0x40088000UL +#define PIO0_BASE 0x50200000UL +#define PIO1_BASE 0x50300000UL +#define PIO2_BASE 0x50400000UL +#define BUSCTRL_BASE 0x40068000UL +#define SIO_BASE 0xD0000000UL +#define SIO_NS_BASE 0xD0020000UL +#define BOOTRAM_BASE 0x400E0000UL +#define CORESIGHT_TRACE_BASE 0x50700000UL +#define USB_BASE 0x50110000UL +#define TRNG_BASE 0x400F0000UL +#define GLITCH_DETECTOR_BASE 0x40158000UL +#define OTP_BASE 0x40120000UL +#define OTP_DATA_BASE 0x40130000UL +#define OTP_DATA_RAW_BASE 0x40134000UL +#define TBMAN_BASE 0x40160000UL +#define USB_DPRAM_BASE 0x50100000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define HW_PER_RESETS ((RESETS_Type*) RESETS_BASE) +#define HW_PER_PSM ((PSM_Type*) PSM_BASE) +#define HW_PER_CLOCKS ((CLOCKS_Type*) CLOCKS_BASE) +#define HW_PER_TICKS ((TICKS_Type*) TICKS_BASE) +#define HW_PER_PADS_BANK0 ((PADS_BANK0_Type*) PADS_BANK0_BASE) +#define HW_PER_PADS_QSPI ((PADS_QSPI_Type*) PADS_QSPI_BASE) +#define HW_PER_IO_QSPI ((IO_QSPI_Type*) IO_QSPI_BASE) +#define HW_PER_IO_BANK0 ((IO_BANK0_Type*) IO_BANK0_BASE) +#define HW_PER_SYSINFO ((SYSINFO_Type*) SYSINFO_BASE) +#define HW_PER_SHA256 ((SHA256_Type*) SHA256_BASE) +#define HW_PER_HSTX_FIFO ((HSTX_FIFO_Type*) HSTX_FIFO_BASE) +#define HW_PER_HSTX_CTRL ((HSTX_CTRL_Type*) HSTX_CTRL_BASE) +#define HW_PER_EPPB ((EPPB_Type*) EPPB_BASE) +#define HW_PER_PPB ((PPB_Type*) PPB_BASE) +#define HW_PER_PPB_NS ((PPB_Type*) PPB_NS_BASE) +#define HW_PER_QMI ((QMI_Type*) QMI_BASE) +#define HW_PER_XIP_CTRL ((XIP_CTRL_Type*) XIP_CTRL_BASE) +#define HW_PER_XIP_AUX ((XIP_AUX_Type*) XIP_AUX_BASE) +#define HW_PER_SYSCFG ((SYSCFG_Type*) SYSCFG_BASE) +#define HW_PER_XOSC ((XOSC_Type*) XOSC_BASE) +#define HW_PER_PLL_SYS ((PLL_SYS_Type*) PLL_SYS_BASE) +#define HW_PER_PLL_USB ((PLL_SYS_Type*) PLL_USB_BASE) +#define HW_PER_ACCESSCTRL ((ACCESSCTRL_Type*) ACCESSCTRL_BASE) +#define HW_PER_UART0 ((UART0_Type*) UART0_BASE) +#define HW_PER_UART1 ((UART0_Type*) UART1_BASE) +#define HW_PER_ROSC ((ROSC_Type*) ROSC_BASE) +#define HW_PER_POWMAN ((POWMAN_Type*) POWMAN_BASE) +#define HW_PER_WATCHDOG ((WATCHDOG_Type*) WATCHDOG_BASE) +#define HW_PER_DMA ((DMA_Type*) DMA_BASE) +#define HW_PER_TIMER0 ((TIMER0_Type*) TIMER0_BASE) +#define HW_PER_TIMER1 ((TIMER0_Type*) TIMER1_BASE) +#define HW_PER_PWM ((PWM_Type*) PWM_BASE) +#define HW_PER_ADC ((ADC_Type*) ADC_BASE) +#define HW_PER_I2C0 ((I2C0_Type*) I2C0_BASE) +#define HW_PER_I2C1 ((I2C0_Type*) I2C1_BASE) +#define HW_PER_SPI0 ((SPI0_Type*) SPI0_BASE) +#define HW_PER_SPI1 ((SPI0_Type*) SPI1_BASE) +#define HW_PER_PIO0 ((PIO0_Type*) PIO0_BASE) +#define HW_PER_PIO1 ((PIO0_Type*) PIO1_BASE) +#define HW_PER_PIO2 ((PIO0_Type*) PIO2_BASE) +#define HW_PER_BUSCTRL ((BUSCTRL_Type*) BUSCTRL_BASE) +#define HW_PER_SIO ((SIO_Type*) SIO_BASE) +#define HW_PER_SIO_NS ((SIO_Type*) SIO_NS_BASE) +#define HW_PER_BOOTRAM ((BOOTRAM_Type*) BOOTRAM_BASE) +#define HW_PER_CORESIGHT_TRACE ((CORESIGHT_TRACE_Type*) CORESIGHT_TRACE_BASE) +#define HW_PER_USB ((USB_Type*) USB_BASE) +#define HW_PER_TRNG ((TRNG_Type*) TRNG_BASE) +#define HW_PER_GLITCH_DETECTOR ((GLITCH_DETECTOR_Type*) GLITCH_DETECTOR_BASE) +#define HW_PER_OTP ((OTP_Type*) OTP_BASE) +#define HW_PER_OTP_DATA ((OTP_DATA_Type*) OTP_DATA_BASE) +#define HW_PER_OTP_DATA_RAW ((OTP_DATA_RAW_Type*) OTP_DATA_RAW_BASE) +#define HW_PER_TBMAN ((TBMAN_Type*) TBMAN_BASE) +#define HW_PER_USB_DPRAM ((USB_DPRAM_Type*) USB_DPRAM_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ RESETS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RESET ========================================================= */ +#define RESETS_RESET_USBCTRL_Pos (28UL) /*!< USBCTRL (Bit 28) */ +#define RESETS_RESET_USBCTRL_Msk (0x10000000UL) /*!< USBCTRL (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_UART1_Pos (27UL) /*!< UART1 (Bit 27) */ +#define RESETS_RESET_UART1_Msk (0x8000000UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_UART0_Pos (26UL) /*!< UART0 (Bit 26) */ +#define RESETS_RESET_UART0_Msk (0x4000000UL) /*!< UART0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_TRNG_Pos (25UL) /*!< TRNG (Bit 25) */ +#define RESETS_RESET_TRNG_Msk (0x2000000UL) /*!< TRNG (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_TIMER1_Pos (24UL) /*!< TIMER1 (Bit 24) */ +#define RESETS_RESET_TIMER1_Msk (0x1000000UL) /*!< TIMER1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_TIMER0_Pos (23UL) /*!< TIMER0 (Bit 23) */ +#define RESETS_RESET_TIMER0_Msk (0x800000UL) /*!< TIMER0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_TBMAN_Pos (22UL) /*!< TBMAN (Bit 22) */ +#define RESETS_RESET_TBMAN_Msk (0x400000UL) /*!< TBMAN (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_SYSINFO_Pos (21UL) /*!< SYSINFO (Bit 21) */ +#define RESETS_RESET_SYSINFO_Msk (0x200000UL) /*!< SYSINFO (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_SYSCFG_Pos (20UL) /*!< SYSCFG (Bit 20) */ +#define RESETS_RESET_SYSCFG_Msk (0x100000UL) /*!< SYSCFG (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_SPI1_Pos (19UL) /*!< SPI1 (Bit 19) */ +#define RESETS_RESET_SPI1_Msk (0x80000UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_SPI0_Pos (18UL) /*!< SPI0 (Bit 18) */ +#define RESETS_RESET_SPI0_Msk (0x40000UL) /*!< SPI0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_SHA256_Pos (17UL) /*!< SHA256 (Bit 17) */ +#define RESETS_RESET_SHA256_Msk (0x20000UL) /*!< SHA256 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_PWM_Pos (16UL) /*!< PWM (Bit 16) */ +#define RESETS_RESET_PWM_Msk (0x10000UL) /*!< PWM (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_PLL_USB_Pos (15UL) /*!< PLL_USB (Bit 15) */ +#define RESETS_RESET_PLL_USB_Msk (0x8000UL) /*!< PLL_USB (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_PLL_SYS_Pos (14UL) /*!< PLL_SYS (Bit 14) */ +#define RESETS_RESET_PLL_SYS_Msk (0x4000UL) /*!< PLL_SYS (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_PIO2_Pos (13UL) /*!< PIO2 (Bit 13) */ +#define RESETS_RESET_PIO2_Msk (0x2000UL) /*!< PIO2 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_PIO1_Pos (12UL) /*!< PIO1 (Bit 12) */ +#define RESETS_RESET_PIO1_Msk (0x1000UL) /*!< PIO1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_PIO0_Pos (11UL) /*!< PIO0 (Bit 11) */ +#define RESETS_RESET_PIO0_Msk (0x800UL) /*!< PIO0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_PADS_QSPI_Pos (10UL) /*!< PADS_QSPI (Bit 10) */ +#define RESETS_RESET_PADS_QSPI_Msk (0x400UL) /*!< PADS_QSPI (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_PADS_BANK0_Pos (9UL) /*!< PADS_BANK0 (Bit 9) */ +#define RESETS_RESET_PADS_BANK0_Msk (0x200UL) /*!< PADS_BANK0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_JTAG_Pos (8UL) /*!< JTAG (Bit 8) */ +#define RESETS_RESET_JTAG_Msk (0x100UL) /*!< JTAG (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_IO_QSPI_Pos (7UL) /*!< IO_QSPI (Bit 7) */ +#define RESETS_RESET_IO_QSPI_Msk (0x80UL) /*!< IO_QSPI (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_IO_BANK0_Pos (6UL) /*!< IO_BANK0 (Bit 6) */ +#define RESETS_RESET_IO_BANK0_Msk (0x40UL) /*!< IO_BANK0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_I2C1_Pos (5UL) /*!< I2C1 (Bit 5) */ +#define RESETS_RESET_I2C1_Msk (0x20UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_I2C0_Pos (4UL) /*!< I2C0 (Bit 4) */ +#define RESETS_RESET_I2C0_Msk (0x10UL) /*!< I2C0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_HSTX_Pos (3UL) /*!< HSTX (Bit 3) */ +#define RESETS_RESET_HSTX_Msk (0x8UL) /*!< HSTX (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DMA_Pos (2UL) /*!< DMA (Bit 2) */ +#define RESETS_RESET_DMA_Msk (0x4UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_BUSCTRL_Pos (1UL) /*!< BUSCTRL (Bit 1) */ +#define RESETS_RESET_BUSCTRL_Msk (0x2UL) /*!< BUSCTRL (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_ADC_Pos (0UL) /*!< ADC (Bit 0) */ +#define RESETS_RESET_ADC_Msk (0x1UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ========================================================= WDSEL ========================================================= */ +#define RESETS_WDSEL_USBCTRL_Pos (28UL) /*!< USBCTRL (Bit 28) */ +#define RESETS_WDSEL_USBCTRL_Msk (0x10000000UL) /*!< USBCTRL (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_UART1_Pos (27UL) /*!< UART1 (Bit 27) */ +#define RESETS_WDSEL_UART1_Msk (0x8000000UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_UART0_Pos (26UL) /*!< UART0 (Bit 26) */ +#define RESETS_WDSEL_UART0_Msk (0x4000000UL) /*!< UART0 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_TRNG_Pos (25UL) /*!< TRNG (Bit 25) */ +#define RESETS_WDSEL_TRNG_Msk (0x2000000UL) /*!< TRNG (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_TIMER1_Pos (24UL) /*!< TIMER1 (Bit 24) */ +#define RESETS_WDSEL_TIMER1_Msk (0x1000000UL) /*!< TIMER1 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_TIMER0_Pos (23UL) /*!< TIMER0 (Bit 23) */ +#define RESETS_WDSEL_TIMER0_Msk (0x800000UL) /*!< TIMER0 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_TBMAN_Pos (22UL) /*!< TBMAN (Bit 22) */ +#define RESETS_WDSEL_TBMAN_Msk (0x400000UL) /*!< TBMAN (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_SYSINFO_Pos (21UL) /*!< SYSINFO (Bit 21) */ +#define RESETS_WDSEL_SYSINFO_Msk (0x200000UL) /*!< SYSINFO (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_SYSCFG_Pos (20UL) /*!< SYSCFG (Bit 20) */ +#define RESETS_WDSEL_SYSCFG_Msk (0x100000UL) /*!< SYSCFG (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_SPI1_Pos (19UL) /*!< SPI1 (Bit 19) */ +#define RESETS_WDSEL_SPI1_Msk (0x80000UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_SPI0_Pos (18UL) /*!< SPI0 (Bit 18) */ +#define RESETS_WDSEL_SPI0_Msk (0x40000UL) /*!< SPI0 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_SHA256_Pos (17UL) /*!< SHA256 (Bit 17) */ +#define RESETS_WDSEL_SHA256_Msk (0x20000UL) /*!< SHA256 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_PWM_Pos (16UL) /*!< PWM (Bit 16) */ +#define RESETS_WDSEL_PWM_Msk (0x10000UL) /*!< PWM (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_PLL_USB_Pos (15UL) /*!< PLL_USB (Bit 15) */ +#define RESETS_WDSEL_PLL_USB_Msk (0x8000UL) /*!< PLL_USB (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_PLL_SYS_Pos (14UL) /*!< PLL_SYS (Bit 14) */ +#define RESETS_WDSEL_PLL_SYS_Msk (0x4000UL) /*!< PLL_SYS (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_PIO2_Pos (13UL) /*!< PIO2 (Bit 13) */ +#define RESETS_WDSEL_PIO2_Msk (0x2000UL) /*!< PIO2 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_PIO1_Pos (12UL) /*!< PIO1 (Bit 12) */ +#define RESETS_WDSEL_PIO1_Msk (0x1000UL) /*!< PIO1 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_PIO0_Pos (11UL) /*!< PIO0 (Bit 11) */ +#define RESETS_WDSEL_PIO0_Msk (0x800UL) /*!< PIO0 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_PADS_QSPI_Pos (10UL) /*!< PADS_QSPI (Bit 10) */ +#define RESETS_WDSEL_PADS_QSPI_Msk (0x400UL) /*!< PADS_QSPI (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_PADS_BANK0_Pos (9UL) /*!< PADS_BANK0 (Bit 9) */ +#define RESETS_WDSEL_PADS_BANK0_Msk (0x200UL) /*!< PADS_BANK0 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_JTAG_Pos (8UL) /*!< JTAG (Bit 8) */ +#define RESETS_WDSEL_JTAG_Msk (0x100UL) /*!< JTAG (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_IO_QSPI_Pos (7UL) /*!< IO_QSPI (Bit 7) */ +#define RESETS_WDSEL_IO_QSPI_Msk (0x80UL) /*!< IO_QSPI (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_IO_BANK0_Pos (6UL) /*!< IO_BANK0 (Bit 6) */ +#define RESETS_WDSEL_IO_BANK0_Msk (0x40UL) /*!< IO_BANK0 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_I2C1_Pos (5UL) /*!< I2C1 (Bit 5) */ +#define RESETS_WDSEL_I2C1_Msk (0x20UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_I2C0_Pos (4UL) /*!< I2C0 (Bit 4) */ +#define RESETS_WDSEL_I2C0_Msk (0x10UL) /*!< I2C0 (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_HSTX_Pos (3UL) /*!< HSTX (Bit 3) */ +#define RESETS_WDSEL_HSTX_Msk (0x8UL) /*!< HSTX (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_DMA_Pos (2UL) /*!< DMA (Bit 2) */ +#define RESETS_WDSEL_DMA_Msk (0x4UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_BUSCTRL_Pos (1UL) /*!< BUSCTRL (Bit 1) */ +#define RESETS_WDSEL_BUSCTRL_Msk (0x2UL) /*!< BUSCTRL (Bitfield-Mask: 0x01) */ +#define RESETS_WDSEL_ADC_Pos (0UL) /*!< ADC (Bit 0) */ +#define RESETS_WDSEL_ADC_Msk (0x1UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ====================================================== RESET_DONE ======================================================= */ +#define RESETS_RESET_DONE_USBCTRL_Pos (28UL) /*!< USBCTRL (Bit 28) */ +#define RESETS_RESET_DONE_USBCTRL_Msk (0x10000000UL) /*!< USBCTRL (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_UART1_Pos (27UL) /*!< UART1 (Bit 27) */ +#define RESETS_RESET_DONE_UART1_Msk (0x8000000UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_UART0_Pos (26UL) /*!< UART0 (Bit 26) */ +#define RESETS_RESET_DONE_UART0_Msk (0x4000000UL) /*!< UART0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_TRNG_Pos (25UL) /*!< TRNG (Bit 25) */ +#define RESETS_RESET_DONE_TRNG_Msk (0x2000000UL) /*!< TRNG (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_TIMER1_Pos (24UL) /*!< TIMER1 (Bit 24) */ +#define RESETS_RESET_DONE_TIMER1_Msk (0x1000000UL) /*!< TIMER1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_TIMER0_Pos (23UL) /*!< TIMER0 (Bit 23) */ +#define RESETS_RESET_DONE_TIMER0_Msk (0x800000UL) /*!< TIMER0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_TBMAN_Pos (22UL) /*!< TBMAN (Bit 22) */ +#define RESETS_RESET_DONE_TBMAN_Msk (0x400000UL) /*!< TBMAN (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_SYSINFO_Pos (21UL) /*!< SYSINFO (Bit 21) */ +#define RESETS_RESET_DONE_SYSINFO_Msk (0x200000UL) /*!< SYSINFO (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_SYSCFG_Pos (20UL) /*!< SYSCFG (Bit 20) */ +#define RESETS_RESET_DONE_SYSCFG_Msk (0x100000UL) /*!< SYSCFG (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_SPI1_Pos (19UL) /*!< SPI1 (Bit 19) */ +#define RESETS_RESET_DONE_SPI1_Msk (0x80000UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_SPI0_Pos (18UL) /*!< SPI0 (Bit 18) */ +#define RESETS_RESET_DONE_SPI0_Msk (0x40000UL) /*!< SPI0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_SHA256_Pos (17UL) /*!< SHA256 (Bit 17) */ +#define RESETS_RESET_DONE_SHA256_Msk (0x20000UL) /*!< SHA256 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_PWM_Pos (16UL) /*!< PWM (Bit 16) */ +#define RESETS_RESET_DONE_PWM_Msk (0x10000UL) /*!< PWM (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_PLL_USB_Pos (15UL) /*!< PLL_USB (Bit 15) */ +#define RESETS_RESET_DONE_PLL_USB_Msk (0x8000UL) /*!< PLL_USB (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_PLL_SYS_Pos (14UL) /*!< PLL_SYS (Bit 14) */ +#define RESETS_RESET_DONE_PLL_SYS_Msk (0x4000UL) /*!< PLL_SYS (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_PIO2_Pos (13UL) /*!< PIO2 (Bit 13) */ +#define RESETS_RESET_DONE_PIO2_Msk (0x2000UL) /*!< PIO2 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_PIO1_Pos (12UL) /*!< PIO1 (Bit 12) */ +#define RESETS_RESET_DONE_PIO1_Msk (0x1000UL) /*!< PIO1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_PIO0_Pos (11UL) /*!< PIO0 (Bit 11) */ +#define RESETS_RESET_DONE_PIO0_Msk (0x800UL) /*!< PIO0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_PADS_QSPI_Pos (10UL) /*!< PADS_QSPI (Bit 10) */ +#define RESETS_RESET_DONE_PADS_QSPI_Msk (0x400UL) /*!< PADS_QSPI (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_PADS_BANK0_Pos (9UL) /*!< PADS_BANK0 (Bit 9) */ +#define RESETS_RESET_DONE_PADS_BANK0_Msk (0x200UL) /*!< PADS_BANK0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_JTAG_Pos (8UL) /*!< JTAG (Bit 8) */ +#define RESETS_RESET_DONE_JTAG_Msk (0x100UL) /*!< JTAG (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_IO_QSPI_Pos (7UL) /*!< IO_QSPI (Bit 7) */ +#define RESETS_RESET_DONE_IO_QSPI_Msk (0x80UL) /*!< IO_QSPI (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_IO_BANK0_Pos (6UL) /*!< IO_BANK0 (Bit 6) */ +#define RESETS_RESET_DONE_IO_BANK0_Msk (0x40UL) /*!< IO_BANK0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_I2C1_Pos (5UL) /*!< I2C1 (Bit 5) */ +#define RESETS_RESET_DONE_I2C1_Msk (0x20UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_I2C0_Pos (4UL) /*!< I2C0 (Bit 4) */ +#define RESETS_RESET_DONE_I2C0_Msk (0x10UL) /*!< I2C0 (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_HSTX_Pos (3UL) /*!< HSTX (Bit 3) */ +#define RESETS_RESET_DONE_HSTX_Msk (0x8UL) /*!< HSTX (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_DMA_Pos (2UL) /*!< DMA (Bit 2) */ +#define RESETS_RESET_DONE_DMA_Msk (0x4UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_BUSCTRL_Pos (1UL) /*!< BUSCTRL (Bit 1) */ +#define RESETS_RESET_DONE_BUSCTRL_Msk (0x2UL) /*!< BUSCTRL (Bitfield-Mask: 0x01) */ +#define RESETS_RESET_DONE_ADC_Pos (0UL) /*!< ADC (Bit 0) */ +#define RESETS_RESET_DONE_ADC_Msk (0x1UL) /*!< ADC (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ PSM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FRCE_ON ======================================================== */ +#define PSM_FRCE_ON_PROC1_Pos (24UL) /*!< PROC1 (Bit 24) */ +#define PSM_FRCE_ON_PROC1_Msk (0x1000000UL) /*!< PROC1 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_PROC0_Pos (23UL) /*!< PROC0 (Bit 23) */ +#define PSM_FRCE_ON_PROC0_Msk (0x800000UL) /*!< PROC0 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_ACCESSCTRL_Pos (22UL) /*!< ACCESSCTRL (Bit 22) */ +#define PSM_FRCE_ON_ACCESSCTRL_Msk (0x400000UL) /*!< ACCESSCTRL (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SIO_Pos (21UL) /*!< SIO (Bit 21) */ +#define PSM_FRCE_ON_SIO_Msk (0x200000UL) /*!< SIO (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_XIP_Pos (20UL) /*!< XIP (Bit 20) */ +#define PSM_FRCE_ON_XIP_Msk (0x100000UL) /*!< XIP (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM9_Pos (19UL) /*!< SRAM9 (Bit 19) */ +#define PSM_FRCE_ON_SRAM9_Msk (0x80000UL) /*!< SRAM9 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM8_Pos (18UL) /*!< SRAM8 (Bit 18) */ +#define PSM_FRCE_ON_SRAM8_Msk (0x40000UL) /*!< SRAM8 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM7_Pos (17UL) /*!< SRAM7 (Bit 17) */ +#define PSM_FRCE_ON_SRAM7_Msk (0x20000UL) /*!< SRAM7 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM6_Pos (16UL) /*!< SRAM6 (Bit 16) */ +#define PSM_FRCE_ON_SRAM6_Msk (0x10000UL) /*!< SRAM6 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM5_Pos (15UL) /*!< SRAM5 (Bit 15) */ +#define PSM_FRCE_ON_SRAM5_Msk (0x8000UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM4_Pos (14UL) /*!< SRAM4 (Bit 14) */ +#define PSM_FRCE_ON_SRAM4_Msk (0x4000UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM3_Pos (13UL) /*!< SRAM3 (Bit 13) */ +#define PSM_FRCE_ON_SRAM3_Msk (0x2000UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM2_Pos (12UL) /*!< SRAM2 (Bit 12) */ +#define PSM_FRCE_ON_SRAM2_Msk (0x1000UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM1_Pos (11UL) /*!< SRAM1 (Bit 11) */ +#define PSM_FRCE_ON_SRAM1_Msk (0x800UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_SRAM0_Pos (10UL) /*!< SRAM0 (Bit 10) */ +#define PSM_FRCE_ON_SRAM0_Msk (0x400UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_BOOTRAM_Pos (9UL) /*!< BOOTRAM (Bit 9) */ +#define PSM_FRCE_ON_BOOTRAM_Msk (0x200UL) /*!< BOOTRAM (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_ROM_Pos (8UL) /*!< ROM (Bit 8) */ +#define PSM_FRCE_ON_ROM_Msk (0x100UL) /*!< ROM (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_BUSFABRIC_Pos (7UL) /*!< BUSFABRIC (Bit 7) */ +#define PSM_FRCE_ON_BUSFABRIC_Msk (0x80UL) /*!< BUSFABRIC (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_PSM_READY_Pos (6UL) /*!< PSM_READY (Bit 6) */ +#define PSM_FRCE_ON_PSM_READY_Msk (0x40UL) /*!< PSM_READY (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_CLOCKS_Pos (5UL) /*!< CLOCKS (Bit 5) */ +#define PSM_FRCE_ON_CLOCKS_Msk (0x20UL) /*!< CLOCKS (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_RESETS_Pos (4UL) /*!< RESETS (Bit 4) */ +#define PSM_FRCE_ON_RESETS_Msk (0x10UL) /*!< RESETS (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_XOSC_Pos (3UL) /*!< XOSC (Bit 3) */ +#define PSM_FRCE_ON_XOSC_Msk (0x8UL) /*!< XOSC (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_ROSC_Pos (2UL) /*!< ROSC (Bit 2) */ +#define PSM_FRCE_ON_ROSC_Msk (0x4UL) /*!< ROSC (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_OTP_Pos (1UL) /*!< OTP (Bit 1) */ +#define PSM_FRCE_ON_OTP_Msk (0x2UL) /*!< OTP (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_ON_PROC_COLD_Pos (0UL) /*!< PROC_COLD (Bit 0) */ +#define PSM_FRCE_ON_PROC_COLD_Msk (0x1UL) /*!< PROC_COLD (Bitfield-Mask: 0x01) */ +/* ======================================================= FRCE_OFF ======================================================== */ +#define PSM_FRCE_OFF_PROC1_Pos (24UL) /*!< PROC1 (Bit 24) */ +#define PSM_FRCE_OFF_PROC1_Msk (0x1000000UL) /*!< PROC1 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_PROC0_Pos (23UL) /*!< PROC0 (Bit 23) */ +#define PSM_FRCE_OFF_PROC0_Msk (0x800000UL) /*!< PROC0 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_ACCESSCTRL_Pos (22UL) /*!< ACCESSCTRL (Bit 22) */ +#define PSM_FRCE_OFF_ACCESSCTRL_Msk (0x400000UL) /*!< ACCESSCTRL (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SIO_Pos (21UL) /*!< SIO (Bit 21) */ +#define PSM_FRCE_OFF_SIO_Msk (0x200000UL) /*!< SIO (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_XIP_Pos (20UL) /*!< XIP (Bit 20) */ +#define PSM_FRCE_OFF_XIP_Msk (0x100000UL) /*!< XIP (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM9_Pos (19UL) /*!< SRAM9 (Bit 19) */ +#define PSM_FRCE_OFF_SRAM9_Msk (0x80000UL) /*!< SRAM9 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM8_Pos (18UL) /*!< SRAM8 (Bit 18) */ +#define PSM_FRCE_OFF_SRAM8_Msk (0x40000UL) /*!< SRAM8 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM7_Pos (17UL) /*!< SRAM7 (Bit 17) */ +#define PSM_FRCE_OFF_SRAM7_Msk (0x20000UL) /*!< SRAM7 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM6_Pos (16UL) /*!< SRAM6 (Bit 16) */ +#define PSM_FRCE_OFF_SRAM6_Msk (0x10000UL) /*!< SRAM6 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM5_Pos (15UL) /*!< SRAM5 (Bit 15) */ +#define PSM_FRCE_OFF_SRAM5_Msk (0x8000UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM4_Pos (14UL) /*!< SRAM4 (Bit 14) */ +#define PSM_FRCE_OFF_SRAM4_Msk (0x4000UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM3_Pos (13UL) /*!< SRAM3 (Bit 13) */ +#define PSM_FRCE_OFF_SRAM3_Msk (0x2000UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM2_Pos (12UL) /*!< SRAM2 (Bit 12) */ +#define PSM_FRCE_OFF_SRAM2_Msk (0x1000UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM1_Pos (11UL) /*!< SRAM1 (Bit 11) */ +#define PSM_FRCE_OFF_SRAM1_Msk (0x800UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_SRAM0_Pos (10UL) /*!< SRAM0 (Bit 10) */ +#define PSM_FRCE_OFF_SRAM0_Msk (0x400UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_BOOTRAM_Pos (9UL) /*!< BOOTRAM (Bit 9) */ +#define PSM_FRCE_OFF_BOOTRAM_Msk (0x200UL) /*!< BOOTRAM (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_ROM_Pos (8UL) /*!< ROM (Bit 8) */ +#define PSM_FRCE_OFF_ROM_Msk (0x100UL) /*!< ROM (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_BUSFABRIC_Pos (7UL) /*!< BUSFABRIC (Bit 7) */ +#define PSM_FRCE_OFF_BUSFABRIC_Msk (0x80UL) /*!< BUSFABRIC (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_PSM_READY_Pos (6UL) /*!< PSM_READY (Bit 6) */ +#define PSM_FRCE_OFF_PSM_READY_Msk (0x40UL) /*!< PSM_READY (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_CLOCKS_Pos (5UL) /*!< CLOCKS (Bit 5) */ +#define PSM_FRCE_OFF_CLOCKS_Msk (0x20UL) /*!< CLOCKS (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_RESETS_Pos (4UL) /*!< RESETS (Bit 4) */ +#define PSM_FRCE_OFF_RESETS_Msk (0x10UL) /*!< RESETS (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_XOSC_Pos (3UL) /*!< XOSC (Bit 3) */ +#define PSM_FRCE_OFF_XOSC_Msk (0x8UL) /*!< XOSC (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_ROSC_Pos (2UL) /*!< ROSC (Bit 2) */ +#define PSM_FRCE_OFF_ROSC_Msk (0x4UL) /*!< ROSC (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_OTP_Pos (1UL) /*!< OTP (Bit 1) */ +#define PSM_FRCE_OFF_OTP_Msk (0x2UL) /*!< OTP (Bitfield-Mask: 0x01) */ +#define PSM_FRCE_OFF_PROC_COLD_Pos (0UL) /*!< PROC_COLD (Bit 0) */ +#define PSM_FRCE_OFF_PROC_COLD_Msk (0x1UL) /*!< PROC_COLD (Bitfield-Mask: 0x01) */ +/* ========================================================= WDSEL ========================================================= */ +#define PSM_WDSEL_PROC1_Pos (24UL) /*!< PROC1 (Bit 24) */ +#define PSM_WDSEL_PROC1_Msk (0x1000000UL) /*!< PROC1 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_PROC0_Pos (23UL) /*!< PROC0 (Bit 23) */ +#define PSM_WDSEL_PROC0_Msk (0x800000UL) /*!< PROC0 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_ACCESSCTRL_Pos (22UL) /*!< ACCESSCTRL (Bit 22) */ +#define PSM_WDSEL_ACCESSCTRL_Msk (0x400000UL) /*!< ACCESSCTRL (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SIO_Pos (21UL) /*!< SIO (Bit 21) */ +#define PSM_WDSEL_SIO_Msk (0x200000UL) /*!< SIO (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_XIP_Pos (20UL) /*!< XIP (Bit 20) */ +#define PSM_WDSEL_XIP_Msk (0x100000UL) /*!< XIP (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM9_Pos (19UL) /*!< SRAM9 (Bit 19) */ +#define PSM_WDSEL_SRAM9_Msk (0x80000UL) /*!< SRAM9 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM8_Pos (18UL) /*!< SRAM8 (Bit 18) */ +#define PSM_WDSEL_SRAM8_Msk (0x40000UL) /*!< SRAM8 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM7_Pos (17UL) /*!< SRAM7 (Bit 17) */ +#define PSM_WDSEL_SRAM7_Msk (0x20000UL) /*!< SRAM7 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM6_Pos (16UL) /*!< SRAM6 (Bit 16) */ +#define PSM_WDSEL_SRAM6_Msk (0x10000UL) /*!< SRAM6 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM5_Pos (15UL) /*!< SRAM5 (Bit 15) */ +#define PSM_WDSEL_SRAM5_Msk (0x8000UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM4_Pos (14UL) /*!< SRAM4 (Bit 14) */ +#define PSM_WDSEL_SRAM4_Msk (0x4000UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM3_Pos (13UL) /*!< SRAM3 (Bit 13) */ +#define PSM_WDSEL_SRAM3_Msk (0x2000UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM2_Pos (12UL) /*!< SRAM2 (Bit 12) */ +#define PSM_WDSEL_SRAM2_Msk (0x1000UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM1_Pos (11UL) /*!< SRAM1 (Bit 11) */ +#define PSM_WDSEL_SRAM1_Msk (0x800UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_SRAM0_Pos (10UL) /*!< SRAM0 (Bit 10) */ +#define PSM_WDSEL_SRAM0_Msk (0x400UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_BOOTRAM_Pos (9UL) /*!< BOOTRAM (Bit 9) */ +#define PSM_WDSEL_BOOTRAM_Msk (0x200UL) /*!< BOOTRAM (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_ROM_Pos (8UL) /*!< ROM (Bit 8) */ +#define PSM_WDSEL_ROM_Msk (0x100UL) /*!< ROM (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_BUSFABRIC_Pos (7UL) /*!< BUSFABRIC (Bit 7) */ +#define PSM_WDSEL_BUSFABRIC_Msk (0x80UL) /*!< BUSFABRIC (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_PSM_READY_Pos (6UL) /*!< PSM_READY (Bit 6) */ +#define PSM_WDSEL_PSM_READY_Msk (0x40UL) /*!< PSM_READY (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_CLOCKS_Pos (5UL) /*!< CLOCKS (Bit 5) */ +#define PSM_WDSEL_CLOCKS_Msk (0x20UL) /*!< CLOCKS (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_RESETS_Pos (4UL) /*!< RESETS (Bit 4) */ +#define PSM_WDSEL_RESETS_Msk (0x10UL) /*!< RESETS (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_XOSC_Pos (3UL) /*!< XOSC (Bit 3) */ +#define PSM_WDSEL_XOSC_Msk (0x8UL) /*!< XOSC (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_ROSC_Pos (2UL) /*!< ROSC (Bit 2) */ +#define PSM_WDSEL_ROSC_Msk (0x4UL) /*!< ROSC (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_OTP_Pos (1UL) /*!< OTP (Bit 1) */ +#define PSM_WDSEL_OTP_Msk (0x2UL) /*!< OTP (Bitfield-Mask: 0x01) */ +#define PSM_WDSEL_PROC_COLD_Pos (0UL) /*!< PROC_COLD (Bit 0) */ +#define PSM_WDSEL_PROC_COLD_Msk (0x1UL) /*!< PROC_COLD (Bitfield-Mask: 0x01) */ +/* ========================================================= DONE ========================================================== */ +#define PSM_DONE_PROC1_Pos (24UL) /*!< PROC1 (Bit 24) */ +#define PSM_DONE_PROC1_Msk (0x1000000UL) /*!< PROC1 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_PROC0_Pos (23UL) /*!< PROC0 (Bit 23) */ +#define PSM_DONE_PROC0_Msk (0x800000UL) /*!< PROC0 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_ACCESSCTRL_Pos (22UL) /*!< ACCESSCTRL (Bit 22) */ +#define PSM_DONE_ACCESSCTRL_Msk (0x400000UL) /*!< ACCESSCTRL (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SIO_Pos (21UL) /*!< SIO (Bit 21) */ +#define PSM_DONE_SIO_Msk (0x200000UL) /*!< SIO (Bitfield-Mask: 0x01) */ +#define PSM_DONE_XIP_Pos (20UL) /*!< XIP (Bit 20) */ +#define PSM_DONE_XIP_Msk (0x100000UL) /*!< XIP (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM9_Pos (19UL) /*!< SRAM9 (Bit 19) */ +#define PSM_DONE_SRAM9_Msk (0x80000UL) /*!< SRAM9 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM8_Pos (18UL) /*!< SRAM8 (Bit 18) */ +#define PSM_DONE_SRAM8_Msk (0x40000UL) /*!< SRAM8 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM7_Pos (17UL) /*!< SRAM7 (Bit 17) */ +#define PSM_DONE_SRAM7_Msk (0x20000UL) /*!< SRAM7 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM6_Pos (16UL) /*!< SRAM6 (Bit 16) */ +#define PSM_DONE_SRAM6_Msk (0x10000UL) /*!< SRAM6 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM5_Pos (15UL) /*!< SRAM5 (Bit 15) */ +#define PSM_DONE_SRAM5_Msk (0x8000UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM4_Pos (14UL) /*!< SRAM4 (Bit 14) */ +#define PSM_DONE_SRAM4_Msk (0x4000UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM3_Pos (13UL) /*!< SRAM3 (Bit 13) */ +#define PSM_DONE_SRAM3_Msk (0x2000UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM2_Pos (12UL) /*!< SRAM2 (Bit 12) */ +#define PSM_DONE_SRAM2_Msk (0x1000UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM1_Pos (11UL) /*!< SRAM1 (Bit 11) */ +#define PSM_DONE_SRAM1_Msk (0x800UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_SRAM0_Pos (10UL) /*!< SRAM0 (Bit 10) */ +#define PSM_DONE_SRAM0_Msk (0x400UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */ +#define PSM_DONE_BOOTRAM_Pos (9UL) /*!< BOOTRAM (Bit 9) */ +#define PSM_DONE_BOOTRAM_Msk (0x200UL) /*!< BOOTRAM (Bitfield-Mask: 0x01) */ +#define PSM_DONE_ROM_Pos (8UL) /*!< ROM (Bit 8) */ +#define PSM_DONE_ROM_Msk (0x100UL) /*!< ROM (Bitfield-Mask: 0x01) */ +#define PSM_DONE_BUSFABRIC_Pos (7UL) /*!< BUSFABRIC (Bit 7) */ +#define PSM_DONE_BUSFABRIC_Msk (0x80UL) /*!< BUSFABRIC (Bitfield-Mask: 0x01) */ +#define PSM_DONE_PSM_READY_Pos (6UL) /*!< PSM_READY (Bit 6) */ +#define PSM_DONE_PSM_READY_Msk (0x40UL) /*!< PSM_READY (Bitfield-Mask: 0x01) */ +#define PSM_DONE_CLOCKS_Pos (5UL) /*!< CLOCKS (Bit 5) */ +#define PSM_DONE_CLOCKS_Msk (0x20UL) /*!< CLOCKS (Bitfield-Mask: 0x01) */ +#define PSM_DONE_RESETS_Pos (4UL) /*!< RESETS (Bit 4) */ +#define PSM_DONE_RESETS_Msk (0x10UL) /*!< RESETS (Bitfield-Mask: 0x01) */ +#define PSM_DONE_XOSC_Pos (3UL) /*!< XOSC (Bit 3) */ +#define PSM_DONE_XOSC_Msk (0x8UL) /*!< XOSC (Bitfield-Mask: 0x01) */ +#define PSM_DONE_ROSC_Pos (2UL) /*!< ROSC (Bit 2) */ +#define PSM_DONE_ROSC_Msk (0x4UL) /*!< ROSC (Bitfield-Mask: 0x01) */ +#define PSM_DONE_OTP_Pos (1UL) /*!< OTP (Bit 1) */ +#define PSM_DONE_OTP_Msk (0x2UL) /*!< OTP (Bitfield-Mask: 0x01) */ +#define PSM_DONE_PROC_COLD_Pos (0UL) /*!< PROC_COLD (Bit 0) */ +#define PSM_DONE_PROC_COLD_Msk (0x1UL) /*!< PROC_COLD (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CLOCKS ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== CLK_GPOUT0_CTRL ==================================================== */ +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_Pos (28UL) /*!< ENABLED (Bit 28) */ +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_Msk (0x10000000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */ +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */ +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_Pos (12UL) /*!< DC50 (Bit 12) */ +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_Msk (0x1000UL) /*!< DC50 (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */ +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Msk (0x1e0UL) /*!< AUXSRC (Bitfield-Mask: 0x0f) */ +/* ==================================================== CLK_GPOUT0_DIV ===================================================== */ +#define CLOCKS_CLK_GPOUT0_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_GPOUT0_DIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_Msk (0xffffUL) /*!< FRAC (Bitfield-Mask: 0xffff) */ +/* ================================================== CLK_GPOUT0_SELECTED ================================================== */ +#define CLOCKS_CLK_GPOUT0_SELECTED_CLK_GPOUT0_SELECTED_Pos (0UL) /*!< CLK_GPOUT0_SELECTED (Bit 0) */ +#define CLOCKS_CLK_GPOUT0_SELECTED_CLK_GPOUT0_SELECTED_Msk (0x1UL) /*!< CLK_GPOUT0_SELECTED (Bitfield-Mask: 0x01) */ +/* ==================================================== CLK_GPOUT1_CTRL ==================================================== */ +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_Pos (28UL) /*!< ENABLED (Bit 28) */ +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_Msk (0x10000000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */ +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */ +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_Pos (12UL) /*!< DC50 (Bit 12) */ +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_Msk (0x1000UL) /*!< DC50 (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */ +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Msk (0x1e0UL) /*!< AUXSRC (Bitfield-Mask: 0x0f) */ +/* ==================================================== CLK_GPOUT1_DIV ===================================================== */ +#define CLOCKS_CLK_GPOUT1_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_GPOUT1_DIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_Msk (0xffffUL) /*!< FRAC (Bitfield-Mask: 0xffff) */ +/* ================================================== CLK_GPOUT1_SELECTED ================================================== */ +#define CLOCKS_CLK_GPOUT1_SELECTED_CLK_GPOUT1_SELECTED_Pos (0UL) /*!< CLK_GPOUT1_SELECTED (Bit 0) */ +#define CLOCKS_CLK_GPOUT1_SELECTED_CLK_GPOUT1_SELECTED_Msk (0x1UL) /*!< CLK_GPOUT1_SELECTED (Bitfield-Mask: 0x01) */ +/* ==================================================== CLK_GPOUT2_CTRL ==================================================== */ +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_Pos (28UL) /*!< ENABLED (Bit 28) */ +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_Msk (0x10000000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */ +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */ +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_Pos (12UL) /*!< DC50 (Bit 12) */ +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_Msk (0x1000UL) /*!< DC50 (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */ +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Msk (0x1e0UL) /*!< AUXSRC (Bitfield-Mask: 0x0f) */ +/* ==================================================== CLK_GPOUT2_DIV ===================================================== */ +#define CLOCKS_CLK_GPOUT2_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_GPOUT2_DIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_Msk (0xffffUL) /*!< FRAC (Bitfield-Mask: 0xffff) */ +/* ================================================== CLK_GPOUT2_SELECTED ================================================== */ +#define CLOCKS_CLK_GPOUT2_SELECTED_CLK_GPOUT2_SELECTED_Pos (0UL) /*!< CLK_GPOUT2_SELECTED (Bit 0) */ +#define CLOCKS_CLK_GPOUT2_SELECTED_CLK_GPOUT2_SELECTED_Msk (0x1UL) /*!< CLK_GPOUT2_SELECTED (Bitfield-Mask: 0x01) */ +/* ==================================================== CLK_GPOUT3_CTRL ==================================================== */ +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_Pos (28UL) /*!< ENABLED (Bit 28) */ +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_Msk (0x10000000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */ +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */ +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_Pos (12UL) /*!< DC50 (Bit 12) */ +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_Msk (0x1000UL) /*!< DC50 (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */ +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Msk (0x1e0UL) /*!< AUXSRC (Bitfield-Mask: 0x0f) */ +/* ==================================================== CLK_GPOUT3_DIV ===================================================== */ +#define CLOCKS_CLK_GPOUT3_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_GPOUT3_DIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_Msk (0xffffUL) /*!< FRAC (Bitfield-Mask: 0xffff) */ +/* ================================================== CLK_GPOUT3_SELECTED ================================================== */ +#define CLOCKS_CLK_GPOUT3_SELECTED_CLK_GPOUT3_SELECTED_Pos (0UL) /*!< CLK_GPOUT3_SELECTED (Bit 0) */ +#define CLOCKS_CLK_GPOUT3_SELECTED_CLK_GPOUT3_SELECTED_Msk (0x1UL) /*!< CLK_GPOUT3_SELECTED (Bitfield-Mask: 0x01) */ +/* ===================================================== CLK_REF_CTRL ====================================================== */ +#define CLOCKS_CLK_REF_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_REF_CTRL_AUXSRC_Msk (0x60UL) /*!< AUXSRC (Bitfield-Mask: 0x03) */ +#define CLOCKS_CLK_REF_CTRL_SRC_Pos (0UL) /*!< SRC (Bit 0) */ +#define CLOCKS_CLK_REF_CTRL_SRC_Msk (0x3UL) /*!< SRC (Bitfield-Mask: 0x03) */ +/* ====================================================== CLK_REF_DIV ====================================================== */ +#define CLOCKS_CLK_REF_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_REF_DIV_INT_Msk (0xff0000UL) /*!< INT (Bitfield-Mask: 0xff) */ +/* =================================================== CLK_REF_SELECTED ==================================================== */ +#define CLOCKS_CLK_REF_SELECTED_CLK_REF_SELECTED_Pos (0UL) /*!< CLK_REF_SELECTED (Bit 0) */ +#define CLOCKS_CLK_REF_SELECTED_CLK_REF_SELECTED_Msk (0xfUL) /*!< CLK_REF_SELECTED (Bitfield-Mask: 0x0f) */ +/* ===================================================== CLK_SYS_CTRL ====================================================== */ +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */ +#define CLOCKS_CLK_SYS_CTRL_SRC_Pos (0UL) /*!< SRC (Bit 0) */ +#define CLOCKS_CLK_SYS_CTRL_SRC_Msk (0x1UL) /*!< SRC (Bitfield-Mask: 0x01) */ +/* ====================================================== CLK_SYS_DIV ====================================================== */ +#define CLOCKS_CLK_SYS_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_SYS_DIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define CLOCKS_CLK_SYS_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define CLOCKS_CLK_SYS_DIV_FRAC_Msk (0xffffUL) /*!< FRAC (Bitfield-Mask: 0xffff) */ +/* =================================================== CLK_SYS_SELECTED ==================================================== */ +#define CLOCKS_CLK_SYS_SELECTED_CLK_SYS_SELECTED_Pos (0UL) /*!< CLK_SYS_SELECTED (Bit 0) */ +#define CLOCKS_CLK_SYS_SELECTED_CLK_SYS_SELECTED_Msk (0x3UL) /*!< CLK_SYS_SELECTED (Bitfield-Mask: 0x03) */ +/* ===================================================== CLK_PERI_CTRL ===================================================== */ +#define CLOCKS_CLK_PERI_CTRL_ENABLED_Pos (28UL) /*!< ENABLED (Bit 28) */ +#define CLOCKS_CLK_PERI_CTRL_ENABLED_Msk (0x10000000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_PERI_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ +#define CLOCKS_CLK_PERI_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_PERI_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */ +#define CLOCKS_CLK_PERI_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */ +/* ===================================================== CLK_PERI_DIV ====================================================== */ +#define CLOCKS_CLK_PERI_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_PERI_DIV_INT_Msk (0x30000UL) /*!< INT (Bitfield-Mask: 0x03) */ +/* =================================================== CLK_PERI_SELECTED =================================================== */ +#define CLOCKS_CLK_PERI_SELECTED_CLK_PERI_SELECTED_Pos (0UL) /*!< CLK_PERI_SELECTED (Bit 0) */ +#define CLOCKS_CLK_PERI_SELECTED_CLK_PERI_SELECTED_Msk (0x1UL) /*!< CLK_PERI_SELECTED (Bitfield-Mask: 0x01) */ +/* ===================================================== CLK_HSTX_CTRL ===================================================== */ +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_Pos (28UL) /*!< ENABLED (Bit 28) */ +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_Msk (0x10000000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */ +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_HSTX_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */ +#define CLOCKS_CLK_HSTX_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_HSTX_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */ +#define CLOCKS_CLK_HSTX_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */ +/* ===================================================== CLK_HSTX_DIV ====================================================== */ +#define CLOCKS_CLK_HSTX_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_HSTX_DIV_INT_Msk (0x30000UL) /*!< INT (Bitfield-Mask: 0x03) */ +/* =================================================== CLK_HSTX_SELECTED =================================================== */ +#define CLOCKS_CLK_HSTX_SELECTED_CLK_HSTX_SELECTED_Pos (0UL) /*!< CLK_HSTX_SELECTED (Bit 0) */ +#define CLOCKS_CLK_HSTX_SELECTED_CLK_HSTX_SELECTED_Msk (0x1UL) /*!< CLK_HSTX_SELECTED (Bitfield-Mask: 0x01) */ +/* ===================================================== CLK_USB_CTRL ====================================================== */ +#define CLOCKS_CLK_USB_CTRL_ENABLED_Pos (28UL) /*!< ENABLED (Bit 28) */ +#define CLOCKS_CLK_USB_CTRL_ENABLED_Msk (0x10000000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_USB_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */ +#define CLOCKS_CLK_USB_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_USB_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */ +#define CLOCKS_CLK_USB_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +#define CLOCKS_CLK_USB_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ +#define CLOCKS_CLK_USB_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_USB_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */ +#define CLOCKS_CLK_USB_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_USB_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_USB_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */ +/* ====================================================== CLK_USB_DIV ====================================================== */ +#define CLOCKS_CLK_USB_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_USB_DIV_INT_Msk (0xf0000UL) /*!< INT (Bitfield-Mask: 0x0f) */ +/* =================================================== CLK_USB_SELECTED ==================================================== */ +#define CLOCKS_CLK_USB_SELECTED_CLK_USB_SELECTED_Pos (0UL) /*!< CLK_USB_SELECTED (Bit 0) */ +#define CLOCKS_CLK_USB_SELECTED_CLK_USB_SELECTED_Msk (0x1UL) /*!< CLK_USB_SELECTED (Bitfield-Mask: 0x01) */ +/* ===================================================== CLK_ADC_CTRL ====================================================== */ +#define CLOCKS_CLK_ADC_CTRL_ENABLED_Pos (28UL) /*!< ENABLED (Bit 28) */ +#define CLOCKS_CLK_ADC_CTRL_ENABLED_Msk (0x10000000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_ADC_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */ +#define CLOCKS_CLK_ADC_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_ADC_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */ +#define CLOCKS_CLK_ADC_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +#define CLOCKS_CLK_ADC_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ +#define CLOCKS_CLK_ADC_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_ADC_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */ +#define CLOCKS_CLK_ADC_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */ +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */ +/* ====================================================== CLK_ADC_DIV ====================================================== */ +#define CLOCKS_CLK_ADC_DIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define CLOCKS_CLK_ADC_DIV_INT_Msk (0xf0000UL) /*!< INT (Bitfield-Mask: 0x0f) */ +/* =================================================== CLK_ADC_SELECTED ==================================================== */ +#define CLOCKS_CLK_ADC_SELECTED_CLK_ADC_SELECTED_Pos (0UL) /*!< CLK_ADC_SELECTED (Bit 0) */ +#define CLOCKS_CLK_ADC_SELECTED_CLK_ADC_SELECTED_Msk (0x1UL) /*!< CLK_ADC_SELECTED (Bitfield-Mask: 0x01) */ +/* =================================================== DFTCLK_XOSC_CTRL ==================================================== */ +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_Pos (0UL) /*!< SRC (Bit 0) */ +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_Msk (0x3UL) /*!< SRC (Bitfield-Mask: 0x03) */ +/* =================================================== DFTCLK_ROSC_CTRL ==================================================== */ +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_Pos (0UL) /*!< SRC (Bit 0) */ +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_Msk (0x3UL) /*!< SRC (Bitfield-Mask: 0x03) */ +/* =================================================== DFTCLK_LPOSC_CTRL =================================================== */ +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_Pos (0UL) /*!< SRC (Bit 0) */ +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_Msk (0x3UL) /*!< SRC (Bitfield-Mask: 0x03) */ +/* ================================================== CLK_SYS_RESUS_CTRL =================================================== */ +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_Pos (16UL) /*!< CLEAR (Bit 16) */ +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_Msk (0x10000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_Pos (12UL) /*!< FRCE (Bit 12) */ +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_Msk (0x1000UL) /*!< FRCE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_Pos (8UL) /*!< ENABLE (Bit 8) */ +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_Msk (0x100UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_Pos (0UL) /*!< TIMEOUT (Bit 0) */ +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_Msk (0xffUL) /*!< TIMEOUT (Bitfield-Mask: 0xff) */ +/* ================================================= CLK_SYS_RESUS_STATUS ================================================== */ +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_Pos (0UL) /*!< RESUSSED (Bit 0) */ +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_Msk (0x1UL) /*!< RESUSSED (Bitfield-Mask: 0x01) */ +/* ====================================================== FC0_REF_KHZ ====================================================== */ +#define CLOCKS_FC0_REF_KHZ_FC0_REF_KHZ_Pos (0UL) /*!< FC0_REF_KHZ (Bit 0) */ +#define CLOCKS_FC0_REF_KHZ_FC0_REF_KHZ_Msk (0xfffffUL) /*!< FC0_REF_KHZ (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FC0_MIN_KHZ ====================================================== */ +#define CLOCKS_FC0_MIN_KHZ_FC0_MIN_KHZ_Pos (0UL) /*!< FC0_MIN_KHZ (Bit 0) */ +#define CLOCKS_FC0_MIN_KHZ_FC0_MIN_KHZ_Msk (0x1ffffffUL) /*!< FC0_MIN_KHZ (Bitfield-Mask: 0x1ffffff) */ +/* ====================================================== FC0_MAX_KHZ ====================================================== */ +#define CLOCKS_FC0_MAX_KHZ_FC0_MAX_KHZ_Pos (0UL) /*!< FC0_MAX_KHZ (Bit 0) */ +#define CLOCKS_FC0_MAX_KHZ_FC0_MAX_KHZ_Msk (0x1ffffffUL) /*!< FC0_MAX_KHZ (Bitfield-Mask: 0x1ffffff) */ +/* ======================================================= FC0_DELAY ======================================================= */ +#define CLOCKS_FC0_DELAY_FC0_DELAY_Pos (0UL) /*!< FC0_DELAY (Bit 0) */ +#define CLOCKS_FC0_DELAY_FC0_DELAY_Msk (0x7UL) /*!< FC0_DELAY (Bitfield-Mask: 0x07) */ +/* ===================================================== FC0_INTERVAL ====================================================== */ +#define CLOCKS_FC0_INTERVAL_FC0_INTERVAL_Pos (0UL) /*!< FC0_INTERVAL (Bit 0) */ +#define CLOCKS_FC0_INTERVAL_FC0_INTERVAL_Msk (0xfUL) /*!< FC0_INTERVAL (Bitfield-Mask: 0x0f) */ +/* ======================================================== FC0_SRC ======================================================== */ +#define CLOCKS_FC0_SRC_FC0_SRC_Pos (0UL) /*!< FC0_SRC (Bit 0) */ +#define CLOCKS_FC0_SRC_FC0_SRC_Msk (0xffUL) /*!< FC0_SRC (Bitfield-Mask: 0xff) */ +/* ====================================================== FC0_STATUS ======================================================= */ +#define CLOCKS_FC0_STATUS_DIED_Pos (28UL) /*!< DIED (Bit 28) */ +#define CLOCKS_FC0_STATUS_DIED_Msk (0x10000000UL) /*!< DIED (Bitfield-Mask: 0x01) */ +#define CLOCKS_FC0_STATUS_FAST_Pos (24UL) /*!< FAST (Bit 24) */ +#define CLOCKS_FC0_STATUS_FAST_Msk (0x1000000UL) /*!< FAST (Bitfield-Mask: 0x01) */ +#define CLOCKS_FC0_STATUS_SLOW_Pos (20UL) /*!< SLOW (Bit 20) */ +#define CLOCKS_FC0_STATUS_SLOW_Msk (0x100000UL) /*!< SLOW (Bitfield-Mask: 0x01) */ +#define CLOCKS_FC0_STATUS_FAIL_Pos (16UL) /*!< FAIL (Bit 16) */ +#define CLOCKS_FC0_STATUS_FAIL_Msk (0x10000UL) /*!< FAIL (Bitfield-Mask: 0x01) */ +#define CLOCKS_FC0_STATUS_WAITING_Pos (12UL) /*!< WAITING (Bit 12) */ +#define CLOCKS_FC0_STATUS_WAITING_Msk (0x1000UL) /*!< WAITING (Bitfield-Mask: 0x01) */ +#define CLOCKS_FC0_STATUS_RUNNING_Pos (8UL) /*!< RUNNING (Bit 8) */ +#define CLOCKS_FC0_STATUS_RUNNING_Msk (0x100UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ +#define CLOCKS_FC0_STATUS_DONE_Pos (4UL) /*!< DONE (Bit 4) */ +#define CLOCKS_FC0_STATUS_DONE_Msk (0x10UL) /*!< DONE (Bitfield-Mask: 0x01) */ +#define CLOCKS_FC0_STATUS_PASS_Pos (0UL) /*!< PASS (Bit 0) */ +#define CLOCKS_FC0_STATUS_PASS_Msk (0x1UL) /*!< PASS (Bitfield-Mask: 0x01) */ +/* ====================================================== FC0_RESULT ======================================================= */ +#define CLOCKS_FC0_RESULT_KHZ_Pos (5UL) /*!< KHZ (Bit 5) */ +#define CLOCKS_FC0_RESULT_KHZ_Msk (0x3fffffe0UL) /*!< KHZ (Bitfield-Mask: 0x1ffffff) */ +#define CLOCKS_FC0_RESULT_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define CLOCKS_FC0_RESULT_FRAC_Msk (0x1fUL) /*!< FRAC (Bitfield-Mask: 0x1f) */ +/* ======================================================= WAKE_EN0 ======================================================== */ +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_Pos (31UL) /*!< CLK_SYS_SIO (Bit 31) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_Msk (0x80000000UL) /*!< CLK_SYS_SIO (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_Pos (30UL) /*!< CLK_SYS_SHA256 (Bit 30) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_Msk (0x40000000UL) /*!< CLK_SYS_SHA256 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_Pos (29UL) /*!< CLK_SYS_PSM (Bit 29) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_Msk (0x20000000UL) /*!< CLK_SYS_PSM (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_Pos (28UL) /*!< CLK_SYS_ROSC (Bit 28) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_Msk (0x10000000UL) /*!< CLK_SYS_ROSC (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_Pos (27UL) /*!< CLK_SYS_ROM (Bit 27) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_Msk (0x8000000UL) /*!< CLK_SYS_ROM (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_Pos (26UL) /*!< CLK_SYS_RESETS (Bit 26) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_Msk (0x4000000UL) /*!< CLK_SYS_RESETS (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_Pos (25UL) /*!< CLK_SYS_PWM (Bit 25) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_Msk (0x2000000UL) /*!< CLK_SYS_PWM (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_Pos (24UL) /*!< CLK_SYS_POWMAN (Bit 24) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_Msk (0x1000000UL) /*!< CLK_SYS_POWMAN (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_Pos (23UL) /*!< CLK_REF_POWMAN (Bit 23) */ +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_Msk (0x800000UL) /*!< CLK_REF_POWMAN (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_Pos (22UL) /*!< CLK_SYS_PLL_USB (Bit 22) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_Msk (0x400000UL) /*!< CLK_SYS_PLL_USB (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_Pos (21UL) /*!< CLK_SYS_PLL_SYS (Bit 21) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_Msk (0x200000UL) /*!< CLK_SYS_PLL_SYS (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_Pos (20UL) /*!< CLK_SYS_PIO2 (Bit 20) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_Msk (0x100000UL) /*!< CLK_SYS_PIO2 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_Pos (19UL) /*!< CLK_SYS_PIO1 (Bit 19) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_Msk (0x80000UL) /*!< CLK_SYS_PIO1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_Pos (18UL) /*!< CLK_SYS_PIO0 (Bit 18) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_Msk (0x40000UL) /*!< CLK_SYS_PIO0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_Pos (17UL) /*!< CLK_SYS_PADS (Bit 17) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_Msk (0x20000UL) /*!< CLK_SYS_PADS (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_Pos (16UL) /*!< CLK_SYS_OTP (Bit 16) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_Msk (0x10000UL) /*!< CLK_SYS_OTP (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_Pos (15UL) /*!< CLK_REF_OTP (Bit 15) */ +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_Msk (0x8000UL) /*!< CLK_REF_OTP (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_Pos (14UL) /*!< CLK_SYS_JTAG (Bit 14) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_Msk (0x4000UL) /*!< CLK_SYS_JTAG (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_Pos (13UL) /*!< CLK_SYS_IO (Bit 13) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_Msk (0x2000UL) /*!< CLK_SYS_IO (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_Pos (12UL) /*!< CLK_SYS_I2C1 (Bit 12) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_Msk (0x1000UL) /*!< CLK_SYS_I2C1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_Pos (11UL) /*!< CLK_SYS_I2C0 (Bit 11) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_Msk (0x800UL) /*!< CLK_SYS_I2C0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_Pos (10UL) /*!< CLK_SYS_HSTX (Bit 10) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_Msk (0x400UL) /*!< CLK_SYS_HSTX (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_HSTX_Pos (9UL) /*!< CLK_HSTX (Bit 9) */ +#define CLOCKS_WAKE_EN0_CLK_HSTX_Msk (0x200UL) /*!< CLK_HSTX (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_Pos (8UL) /*!< CLK_SYS_GLITCH_DETECTOR (Bit 8) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_Msk (0x100UL) /*!< CLK_SYS_GLITCH_DETECTOR (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_Pos (7UL) /*!< CLK_SYS_DMA (Bit 7) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_Msk (0x80UL) /*!< CLK_SYS_DMA (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_Pos (6UL) /*!< CLK_SYS_BUSFABRIC (Bit 6) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_Msk (0x40UL) /*!< CLK_SYS_BUSFABRIC (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_Pos (5UL) /*!< CLK_SYS_BUSCTRL (Bit 5) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_Msk (0x20UL) /*!< CLK_SYS_BUSCTRL (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_Pos (4UL) /*!< CLK_SYS_BOOTRAM (Bit 4) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_Msk (0x10UL) /*!< CLK_SYS_BOOTRAM (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_Pos (3UL) /*!< CLK_SYS_ADC (Bit 3) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_Msk (0x8UL) /*!< CLK_SYS_ADC (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_ADC_Pos (2UL) /*!< CLK_ADC (Bit 2) */ +#define CLOCKS_WAKE_EN0_CLK_ADC_Msk (0x4UL) /*!< CLK_ADC (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_Pos (1UL) /*!< CLK_SYS_ACCESSCTRL (Bit 1) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_Msk (0x2UL) /*!< CLK_SYS_ACCESSCTRL (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_Pos (0UL) /*!< CLK_SYS_CLOCKS (Bit 0) */ +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_Msk (0x1UL) /*!< CLK_SYS_CLOCKS (Bitfield-Mask: 0x01) */ +/* ======================================================= WAKE_EN1 ======================================================== */ +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_Pos (30UL) /*!< CLK_SYS_XOSC (Bit 30) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_Msk (0x40000000UL) /*!< CLK_SYS_XOSC (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_Pos (29UL) /*!< CLK_SYS_XIP (Bit 29) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_Msk (0x20000000UL) /*!< CLK_SYS_XIP (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_Pos (28UL) /*!< CLK_SYS_WATCHDOG (Bit 28) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_Msk (0x10000000UL) /*!< CLK_SYS_WATCHDOG (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_USB_Pos (27UL) /*!< CLK_USB (Bit 27) */ +#define CLOCKS_WAKE_EN1_CLK_USB_Msk (0x8000000UL) /*!< CLK_USB (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_Pos (26UL) /*!< CLK_SYS_USBCTRL (Bit 26) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_Msk (0x4000000UL) /*!< CLK_SYS_USBCTRL (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_Pos (25UL) /*!< CLK_SYS_UART1 (Bit 25) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_Msk (0x2000000UL) /*!< CLK_SYS_UART1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_Pos (24UL) /*!< CLK_PERI_UART1 (Bit 24) */ +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_Msk (0x1000000UL) /*!< CLK_PERI_UART1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_Pos (23UL) /*!< CLK_SYS_UART0 (Bit 23) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_Msk (0x800000UL) /*!< CLK_SYS_UART0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_Pos (22UL) /*!< CLK_PERI_UART0 (Bit 22) */ +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_Msk (0x400000UL) /*!< CLK_PERI_UART0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_Pos (21UL) /*!< CLK_SYS_TRNG (Bit 21) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_Msk (0x200000UL) /*!< CLK_SYS_TRNG (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_Pos (20UL) /*!< CLK_SYS_TIMER1 (Bit 20) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_Msk (0x100000UL) /*!< CLK_SYS_TIMER1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_Pos (19UL) /*!< CLK_SYS_TIMER0 (Bit 19) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_Msk (0x80000UL) /*!< CLK_SYS_TIMER0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_Pos (18UL) /*!< CLK_SYS_TICKS (Bit 18) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_Msk (0x40000UL) /*!< CLK_SYS_TICKS (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_Pos (17UL) /*!< CLK_REF_TICKS (Bit 17) */ +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_Msk (0x20000UL) /*!< CLK_REF_TICKS (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_Pos (16UL) /*!< CLK_SYS_TBMAN (Bit 16) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_Msk (0x10000UL) /*!< CLK_SYS_TBMAN (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_Pos (15UL) /*!< CLK_SYS_SYSINFO (Bit 15) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_Msk (0x8000UL) /*!< CLK_SYS_SYSINFO (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_Pos (14UL) /*!< CLK_SYS_SYSCFG (Bit 14) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_Msk (0x4000UL) /*!< CLK_SYS_SYSCFG (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_Pos (13UL) /*!< CLK_SYS_SRAM9 (Bit 13) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_Msk (0x2000UL) /*!< CLK_SYS_SRAM9 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_Pos (12UL) /*!< CLK_SYS_SRAM8 (Bit 12) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_Msk (0x1000UL) /*!< CLK_SYS_SRAM8 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_Pos (11UL) /*!< CLK_SYS_SRAM7 (Bit 11) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_Msk (0x800UL) /*!< CLK_SYS_SRAM7 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_Pos (10UL) /*!< CLK_SYS_SRAM6 (Bit 10) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_Msk (0x400UL) /*!< CLK_SYS_SRAM6 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_Pos (9UL) /*!< CLK_SYS_SRAM5 (Bit 9) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_Msk (0x200UL) /*!< CLK_SYS_SRAM5 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_Pos (8UL) /*!< CLK_SYS_SRAM4 (Bit 8) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_Msk (0x100UL) /*!< CLK_SYS_SRAM4 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_Pos (7UL) /*!< CLK_SYS_SRAM3 (Bit 7) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_Msk (0x80UL) /*!< CLK_SYS_SRAM3 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_Pos (6UL) /*!< CLK_SYS_SRAM2 (Bit 6) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_Msk (0x40UL) /*!< CLK_SYS_SRAM2 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_Pos (5UL) /*!< CLK_SYS_SRAM1 (Bit 5) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_Msk (0x20UL) /*!< CLK_SYS_SRAM1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_Pos (4UL) /*!< CLK_SYS_SRAM0 (Bit 4) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_Msk (0x10UL) /*!< CLK_SYS_SRAM0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_Pos (3UL) /*!< CLK_SYS_SPI1 (Bit 3) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_Msk (0x8UL) /*!< CLK_SYS_SPI1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_Pos (2UL) /*!< CLK_PERI_SPI1 (Bit 2) */ +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_Msk (0x4UL) /*!< CLK_PERI_SPI1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_Pos (1UL) /*!< CLK_SYS_SPI0 (Bit 1) */ +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_Msk (0x2UL) /*!< CLK_SYS_SPI0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_Pos (0UL) /*!< CLK_PERI_SPI0 (Bit 0) */ +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_Msk (0x1UL) /*!< CLK_PERI_SPI0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SLEEP_EN0 ======================================================= */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_Pos (31UL) /*!< CLK_SYS_SIO (Bit 31) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_Msk (0x80000000UL) /*!< CLK_SYS_SIO (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_Pos (30UL) /*!< CLK_SYS_SHA256 (Bit 30) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_Msk (0x40000000UL) /*!< CLK_SYS_SHA256 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_Pos (29UL) /*!< CLK_SYS_PSM (Bit 29) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_Msk (0x20000000UL) /*!< CLK_SYS_PSM (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_Pos (28UL) /*!< CLK_SYS_ROSC (Bit 28) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_Msk (0x10000000UL) /*!< CLK_SYS_ROSC (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_Pos (27UL) /*!< CLK_SYS_ROM (Bit 27) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_Msk (0x8000000UL) /*!< CLK_SYS_ROM (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_Pos (26UL) /*!< CLK_SYS_RESETS (Bit 26) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_Msk (0x4000000UL) /*!< CLK_SYS_RESETS (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_Pos (25UL) /*!< CLK_SYS_PWM (Bit 25) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_Msk (0x2000000UL) /*!< CLK_SYS_PWM (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_Pos (24UL) /*!< CLK_SYS_POWMAN (Bit 24) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_Msk (0x1000000UL) /*!< CLK_SYS_POWMAN (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_Pos (23UL) /*!< CLK_REF_POWMAN (Bit 23) */ +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_Msk (0x800000UL) /*!< CLK_REF_POWMAN (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_Pos (22UL) /*!< CLK_SYS_PLL_USB (Bit 22) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_Msk (0x400000UL) /*!< CLK_SYS_PLL_USB (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_Pos (21UL) /*!< CLK_SYS_PLL_SYS (Bit 21) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_Msk (0x200000UL) /*!< CLK_SYS_PLL_SYS (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_Pos (20UL) /*!< CLK_SYS_PIO2 (Bit 20) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_Msk (0x100000UL) /*!< CLK_SYS_PIO2 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_Pos (19UL) /*!< CLK_SYS_PIO1 (Bit 19) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_Msk (0x80000UL) /*!< CLK_SYS_PIO1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_Pos (18UL) /*!< CLK_SYS_PIO0 (Bit 18) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_Msk (0x40000UL) /*!< CLK_SYS_PIO0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_Pos (17UL) /*!< CLK_SYS_PADS (Bit 17) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_Msk (0x20000UL) /*!< CLK_SYS_PADS (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_Pos (16UL) /*!< CLK_SYS_OTP (Bit 16) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_Msk (0x10000UL) /*!< CLK_SYS_OTP (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_Pos (15UL) /*!< CLK_REF_OTP (Bit 15) */ +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_Msk (0x8000UL) /*!< CLK_REF_OTP (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_Pos (14UL) /*!< CLK_SYS_JTAG (Bit 14) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_Msk (0x4000UL) /*!< CLK_SYS_JTAG (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_Pos (13UL) /*!< CLK_SYS_IO (Bit 13) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_Msk (0x2000UL) /*!< CLK_SYS_IO (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_Pos (12UL) /*!< CLK_SYS_I2C1 (Bit 12) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_Msk (0x1000UL) /*!< CLK_SYS_I2C1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_Pos (11UL) /*!< CLK_SYS_I2C0 (Bit 11) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_Msk (0x800UL) /*!< CLK_SYS_I2C0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_Pos (10UL) /*!< CLK_SYS_HSTX (Bit 10) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_Msk (0x400UL) /*!< CLK_SYS_HSTX (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_HSTX_Pos (9UL) /*!< CLK_HSTX (Bit 9) */ +#define CLOCKS_SLEEP_EN0_CLK_HSTX_Msk (0x200UL) /*!< CLK_HSTX (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_Pos (8UL) /*!< CLK_SYS_GLITCH_DETECTOR (Bit 8) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_Msk (0x100UL) /*!< CLK_SYS_GLITCH_DETECTOR (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_Pos (7UL) /*!< CLK_SYS_DMA (Bit 7) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_Msk (0x80UL) /*!< CLK_SYS_DMA (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_Pos (6UL) /*!< CLK_SYS_BUSFABRIC (Bit 6) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_Msk (0x40UL) /*!< CLK_SYS_BUSFABRIC (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_Pos (5UL) /*!< CLK_SYS_BUSCTRL (Bit 5) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_Msk (0x20UL) /*!< CLK_SYS_BUSCTRL (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_Pos (4UL) /*!< CLK_SYS_BOOTRAM (Bit 4) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_Msk (0x10UL) /*!< CLK_SYS_BOOTRAM (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_Pos (3UL) /*!< CLK_SYS_ADC (Bit 3) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_Msk (0x8UL) /*!< CLK_SYS_ADC (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_ADC_Pos (2UL) /*!< CLK_ADC (Bit 2) */ +#define CLOCKS_SLEEP_EN0_CLK_ADC_Msk (0x4UL) /*!< CLK_ADC (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_Pos (1UL) /*!< CLK_SYS_ACCESSCTRL (Bit 1) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_Msk (0x2UL) /*!< CLK_SYS_ACCESSCTRL (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_Pos (0UL) /*!< CLK_SYS_CLOCKS (Bit 0) */ +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_Msk (0x1UL) /*!< CLK_SYS_CLOCKS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLEEP_EN1 ======================================================= */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_Pos (30UL) /*!< CLK_SYS_XOSC (Bit 30) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_Msk (0x40000000UL) /*!< CLK_SYS_XOSC (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_Pos (29UL) /*!< CLK_SYS_XIP (Bit 29) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_Msk (0x20000000UL) /*!< CLK_SYS_XIP (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_Pos (28UL) /*!< CLK_SYS_WATCHDOG (Bit 28) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_Msk (0x10000000UL) /*!< CLK_SYS_WATCHDOG (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_USB_Pos (27UL) /*!< CLK_USB (Bit 27) */ +#define CLOCKS_SLEEP_EN1_CLK_USB_Msk (0x8000000UL) /*!< CLK_USB (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_Pos (26UL) /*!< CLK_SYS_USBCTRL (Bit 26) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_Msk (0x4000000UL) /*!< CLK_SYS_USBCTRL (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_Pos (25UL) /*!< CLK_SYS_UART1 (Bit 25) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_Msk (0x2000000UL) /*!< CLK_SYS_UART1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_Pos (24UL) /*!< CLK_PERI_UART1 (Bit 24) */ +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_Msk (0x1000000UL) /*!< CLK_PERI_UART1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_Pos (23UL) /*!< CLK_SYS_UART0 (Bit 23) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_Msk (0x800000UL) /*!< CLK_SYS_UART0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_Pos (22UL) /*!< CLK_PERI_UART0 (Bit 22) */ +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_Msk (0x400000UL) /*!< CLK_PERI_UART0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_Pos (21UL) /*!< CLK_SYS_TRNG (Bit 21) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_Msk (0x200000UL) /*!< CLK_SYS_TRNG (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_Pos (20UL) /*!< CLK_SYS_TIMER1 (Bit 20) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_Msk (0x100000UL) /*!< CLK_SYS_TIMER1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_Pos (19UL) /*!< CLK_SYS_TIMER0 (Bit 19) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_Msk (0x80000UL) /*!< CLK_SYS_TIMER0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_Pos (18UL) /*!< CLK_SYS_TICKS (Bit 18) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_Msk (0x40000UL) /*!< CLK_SYS_TICKS (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_Pos (17UL) /*!< CLK_REF_TICKS (Bit 17) */ +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_Msk (0x20000UL) /*!< CLK_REF_TICKS (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_Pos (16UL) /*!< CLK_SYS_TBMAN (Bit 16) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_Msk (0x10000UL) /*!< CLK_SYS_TBMAN (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_Pos (15UL) /*!< CLK_SYS_SYSINFO (Bit 15) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_Msk (0x8000UL) /*!< CLK_SYS_SYSINFO (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_Pos (14UL) /*!< CLK_SYS_SYSCFG (Bit 14) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_Msk (0x4000UL) /*!< CLK_SYS_SYSCFG (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_Pos (13UL) /*!< CLK_SYS_SRAM9 (Bit 13) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_Msk (0x2000UL) /*!< CLK_SYS_SRAM9 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_Pos (12UL) /*!< CLK_SYS_SRAM8 (Bit 12) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_Msk (0x1000UL) /*!< CLK_SYS_SRAM8 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_Pos (11UL) /*!< CLK_SYS_SRAM7 (Bit 11) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_Msk (0x800UL) /*!< CLK_SYS_SRAM7 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_Pos (10UL) /*!< CLK_SYS_SRAM6 (Bit 10) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_Msk (0x400UL) /*!< CLK_SYS_SRAM6 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_Pos (9UL) /*!< CLK_SYS_SRAM5 (Bit 9) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_Msk (0x200UL) /*!< CLK_SYS_SRAM5 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_Pos (8UL) /*!< CLK_SYS_SRAM4 (Bit 8) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_Msk (0x100UL) /*!< CLK_SYS_SRAM4 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_Pos (7UL) /*!< CLK_SYS_SRAM3 (Bit 7) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_Msk (0x80UL) /*!< CLK_SYS_SRAM3 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_Pos (6UL) /*!< CLK_SYS_SRAM2 (Bit 6) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_Msk (0x40UL) /*!< CLK_SYS_SRAM2 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_Pos (5UL) /*!< CLK_SYS_SRAM1 (Bit 5) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_Msk (0x20UL) /*!< CLK_SYS_SRAM1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_Pos (4UL) /*!< CLK_SYS_SRAM0 (Bit 4) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_Msk (0x10UL) /*!< CLK_SYS_SRAM0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_Pos (3UL) /*!< CLK_SYS_SPI1 (Bit 3) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_Msk (0x8UL) /*!< CLK_SYS_SPI1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_Pos (2UL) /*!< CLK_PERI_SPI1 (Bit 2) */ +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_Msk (0x4UL) /*!< CLK_PERI_SPI1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_Pos (1UL) /*!< CLK_SYS_SPI0 (Bit 1) */ +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_Msk (0x2UL) /*!< CLK_SYS_SPI0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_Pos (0UL) /*!< CLK_PERI_SPI0 (Bit 0) */ +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_Msk (0x1UL) /*!< CLK_PERI_SPI0 (Bitfield-Mask: 0x01) */ +/* ======================================================= ENABLED0 ======================================================== */ +#define CLOCKS_ENABLED0_CLK_SYS_SIO_Pos (31UL) /*!< CLK_SYS_SIO (Bit 31) */ +#define CLOCKS_ENABLED0_CLK_SYS_SIO_Msk (0x80000000UL) /*!< CLK_SYS_SIO (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_Pos (30UL) /*!< CLK_SYS_SHA256 (Bit 30) */ +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_Msk (0x40000000UL) /*!< CLK_SYS_SHA256 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_PSM_Pos (29UL) /*!< CLK_SYS_PSM (Bit 29) */ +#define CLOCKS_ENABLED0_CLK_SYS_PSM_Msk (0x20000000UL) /*!< CLK_SYS_PSM (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_Pos (28UL) /*!< CLK_SYS_ROSC (Bit 28) */ +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_Msk (0x10000000UL) /*!< CLK_SYS_ROSC (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_ROM_Pos (27UL) /*!< CLK_SYS_ROM (Bit 27) */ +#define CLOCKS_ENABLED0_CLK_SYS_ROM_Msk (0x8000000UL) /*!< CLK_SYS_ROM (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_Pos (26UL) /*!< CLK_SYS_RESETS (Bit 26) */ +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_Msk (0x4000000UL) /*!< CLK_SYS_RESETS (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_PWM_Pos (25UL) /*!< CLK_SYS_PWM (Bit 25) */ +#define CLOCKS_ENABLED0_CLK_SYS_PWM_Msk (0x2000000UL) /*!< CLK_SYS_PWM (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_Pos (24UL) /*!< CLK_SYS_POWMAN (Bit 24) */ +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_Msk (0x1000000UL) /*!< CLK_SYS_POWMAN (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_Pos (23UL) /*!< CLK_REF_POWMAN (Bit 23) */ +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_Msk (0x800000UL) /*!< CLK_REF_POWMAN (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_Pos (22UL) /*!< CLK_SYS_PLL_USB (Bit 22) */ +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_Msk (0x400000UL) /*!< CLK_SYS_PLL_USB (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_Pos (21UL) /*!< CLK_SYS_PLL_SYS (Bit 21) */ +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_Msk (0x200000UL) /*!< CLK_SYS_PLL_SYS (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_Pos (20UL) /*!< CLK_SYS_PIO2 (Bit 20) */ +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_Msk (0x100000UL) /*!< CLK_SYS_PIO2 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_Pos (19UL) /*!< CLK_SYS_PIO1 (Bit 19) */ +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_Msk (0x80000UL) /*!< CLK_SYS_PIO1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_Pos (18UL) /*!< CLK_SYS_PIO0 (Bit 18) */ +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_Msk (0x40000UL) /*!< CLK_SYS_PIO0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_PADS_Pos (17UL) /*!< CLK_SYS_PADS (Bit 17) */ +#define CLOCKS_ENABLED0_CLK_SYS_PADS_Msk (0x20000UL) /*!< CLK_SYS_PADS (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_OTP_Pos (16UL) /*!< CLK_SYS_OTP (Bit 16) */ +#define CLOCKS_ENABLED0_CLK_SYS_OTP_Msk (0x10000UL) /*!< CLK_SYS_OTP (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_REF_OTP_Pos (15UL) /*!< CLK_REF_OTP (Bit 15) */ +#define CLOCKS_ENABLED0_CLK_REF_OTP_Msk (0x8000UL) /*!< CLK_REF_OTP (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_Pos (14UL) /*!< CLK_SYS_JTAG (Bit 14) */ +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_Msk (0x4000UL) /*!< CLK_SYS_JTAG (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_IO_Pos (13UL) /*!< CLK_SYS_IO (Bit 13) */ +#define CLOCKS_ENABLED0_CLK_SYS_IO_Msk (0x2000UL) /*!< CLK_SYS_IO (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_Pos (12UL) /*!< CLK_SYS_I2C1 (Bit 12) */ +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_Msk (0x1000UL) /*!< CLK_SYS_I2C1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_Pos (11UL) /*!< CLK_SYS_I2C0 (Bit 11) */ +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_Msk (0x800UL) /*!< CLK_SYS_I2C0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_Pos (10UL) /*!< CLK_SYS_HSTX (Bit 10) */ +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_Msk (0x400UL) /*!< CLK_SYS_HSTX (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_HSTX_Pos (9UL) /*!< CLK_HSTX (Bit 9) */ +#define CLOCKS_ENABLED0_CLK_HSTX_Msk (0x200UL) /*!< CLK_HSTX (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_Pos (8UL) /*!< CLK_SYS_GLITCH_DETECTOR (Bit 8) */ +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_Msk (0x100UL) /*!< CLK_SYS_GLITCH_DETECTOR (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_DMA_Pos (7UL) /*!< CLK_SYS_DMA (Bit 7) */ +#define CLOCKS_ENABLED0_CLK_SYS_DMA_Msk (0x80UL) /*!< CLK_SYS_DMA (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_Pos (6UL) /*!< CLK_SYS_BUSFABRIC (Bit 6) */ +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_Msk (0x40UL) /*!< CLK_SYS_BUSFABRIC (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_Pos (5UL) /*!< CLK_SYS_BUSCTRL (Bit 5) */ +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_Msk (0x20UL) /*!< CLK_SYS_BUSCTRL (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_Pos (4UL) /*!< CLK_SYS_BOOTRAM (Bit 4) */ +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_Msk (0x10UL) /*!< CLK_SYS_BOOTRAM (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_ADC_Pos (3UL) /*!< CLK_SYS_ADC (Bit 3) */ +#define CLOCKS_ENABLED0_CLK_SYS_ADC_Msk (0x8UL) /*!< CLK_SYS_ADC (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_ADC_Pos (2UL) /*!< CLK_ADC (Bit 2) */ +#define CLOCKS_ENABLED0_CLK_ADC_Msk (0x4UL) /*!< CLK_ADC (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_Pos (1UL) /*!< CLK_SYS_ACCESSCTRL (Bit 1) */ +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_Msk (0x2UL) /*!< CLK_SYS_ACCESSCTRL (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_Pos (0UL) /*!< CLK_SYS_CLOCKS (Bit 0) */ +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_Msk (0x1UL) /*!< CLK_SYS_CLOCKS (Bitfield-Mask: 0x01) */ +/* ======================================================= ENABLED1 ======================================================== */ +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_Pos (30UL) /*!< CLK_SYS_XOSC (Bit 30) */ +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_Msk (0x40000000UL) /*!< CLK_SYS_XOSC (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_XIP_Pos (29UL) /*!< CLK_SYS_XIP (Bit 29) */ +#define CLOCKS_ENABLED1_CLK_SYS_XIP_Msk (0x20000000UL) /*!< CLK_SYS_XIP (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_Pos (28UL) /*!< CLK_SYS_WATCHDOG (Bit 28) */ +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_Msk (0x10000000UL) /*!< CLK_SYS_WATCHDOG (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_USB_Pos (27UL) /*!< CLK_USB (Bit 27) */ +#define CLOCKS_ENABLED1_CLK_USB_Msk (0x8000000UL) /*!< CLK_USB (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_Pos (26UL) /*!< CLK_SYS_USBCTRL (Bit 26) */ +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_Msk (0x4000000UL) /*!< CLK_SYS_USBCTRL (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_UART1_Pos (25UL) /*!< CLK_SYS_UART1 (Bit 25) */ +#define CLOCKS_ENABLED1_CLK_SYS_UART1_Msk (0x2000000UL) /*!< CLK_SYS_UART1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_PERI_UART1_Pos (24UL) /*!< CLK_PERI_UART1 (Bit 24) */ +#define CLOCKS_ENABLED1_CLK_PERI_UART1_Msk (0x1000000UL) /*!< CLK_PERI_UART1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_UART0_Pos (23UL) /*!< CLK_SYS_UART0 (Bit 23) */ +#define CLOCKS_ENABLED1_CLK_SYS_UART0_Msk (0x800000UL) /*!< CLK_SYS_UART0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_PERI_UART0_Pos (22UL) /*!< CLK_PERI_UART0 (Bit 22) */ +#define CLOCKS_ENABLED1_CLK_PERI_UART0_Msk (0x400000UL) /*!< CLK_PERI_UART0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_Pos (21UL) /*!< CLK_SYS_TRNG (Bit 21) */ +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_Msk (0x200000UL) /*!< CLK_SYS_TRNG (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_Pos (20UL) /*!< CLK_SYS_TIMER1 (Bit 20) */ +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_Msk (0x100000UL) /*!< CLK_SYS_TIMER1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_Pos (19UL) /*!< CLK_SYS_TIMER0 (Bit 19) */ +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_Msk (0x80000UL) /*!< CLK_SYS_TIMER0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_Pos (18UL) /*!< CLK_SYS_TICKS (Bit 18) */ +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_Msk (0x40000UL) /*!< CLK_SYS_TICKS (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_REF_TICKS_Pos (17UL) /*!< CLK_REF_TICKS (Bit 17) */ +#define CLOCKS_ENABLED1_CLK_REF_TICKS_Msk (0x20000UL) /*!< CLK_REF_TICKS (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_Pos (16UL) /*!< CLK_SYS_TBMAN (Bit 16) */ +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_Msk (0x10000UL) /*!< CLK_SYS_TBMAN (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_Pos (15UL) /*!< CLK_SYS_SYSINFO (Bit 15) */ +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_Msk (0x8000UL) /*!< CLK_SYS_SYSINFO (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_Pos (14UL) /*!< CLK_SYS_SYSCFG (Bit 14) */ +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_Msk (0x4000UL) /*!< CLK_SYS_SYSCFG (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_Pos (13UL) /*!< CLK_SYS_SRAM9 (Bit 13) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_Msk (0x2000UL) /*!< CLK_SYS_SRAM9 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_Pos (12UL) /*!< CLK_SYS_SRAM8 (Bit 12) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_Msk (0x1000UL) /*!< CLK_SYS_SRAM8 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_Pos (11UL) /*!< CLK_SYS_SRAM7 (Bit 11) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_Msk (0x800UL) /*!< CLK_SYS_SRAM7 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_Pos (10UL) /*!< CLK_SYS_SRAM6 (Bit 10) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_Msk (0x400UL) /*!< CLK_SYS_SRAM6 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_Pos (9UL) /*!< CLK_SYS_SRAM5 (Bit 9) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_Msk (0x200UL) /*!< CLK_SYS_SRAM5 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_Pos (8UL) /*!< CLK_SYS_SRAM4 (Bit 8) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_Msk (0x100UL) /*!< CLK_SYS_SRAM4 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_Pos (7UL) /*!< CLK_SYS_SRAM3 (Bit 7) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_Msk (0x80UL) /*!< CLK_SYS_SRAM3 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_Pos (6UL) /*!< CLK_SYS_SRAM2 (Bit 6) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_Msk (0x40UL) /*!< CLK_SYS_SRAM2 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_Pos (5UL) /*!< CLK_SYS_SRAM1 (Bit 5) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_Msk (0x20UL) /*!< CLK_SYS_SRAM1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_Pos (4UL) /*!< CLK_SYS_SRAM0 (Bit 4) */ +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_Msk (0x10UL) /*!< CLK_SYS_SRAM0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_Pos (3UL) /*!< CLK_SYS_SPI1 (Bit 3) */ +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_Msk (0x8UL) /*!< CLK_SYS_SPI1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_Pos (2UL) /*!< CLK_PERI_SPI1 (Bit 2) */ +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_Msk (0x4UL) /*!< CLK_PERI_SPI1 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_Pos (1UL) /*!< CLK_SYS_SPI0 (Bit 1) */ +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_Msk (0x2UL) /*!< CLK_SYS_SPI0 (Bitfield-Mask: 0x01) */ +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_Pos (0UL) /*!< CLK_PERI_SPI0 (Bit 0) */ +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_Msk (0x1UL) /*!< CLK_PERI_SPI0 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR ========================================================== */ +#define CLOCKS_INTR_CLK_SYS_RESUS_Pos (0UL) /*!< CLK_SYS_RESUS (Bit 0) */ +#define CLOCKS_INTR_CLK_SYS_RESUS_Msk (0x1UL) /*!< CLK_SYS_RESUS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ +#define CLOCKS_INTE_CLK_SYS_RESUS_Pos (0UL) /*!< CLK_SYS_RESUS (Bit 0) */ +#define CLOCKS_INTE_CLK_SYS_RESUS_Msk (0x1UL) /*!< CLK_SYS_RESUS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define CLOCKS_INTF_CLK_SYS_RESUS_Pos (0UL) /*!< CLK_SYS_RESUS (Bit 0) */ +#define CLOCKS_INTF_CLK_SYS_RESUS_Msk (0x1UL) /*!< CLK_SYS_RESUS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ +#define CLOCKS_INTS_CLK_SYS_RESUS_Pos (0UL) /*!< CLK_SYS_RESUS (Bit 0) */ +#define CLOCKS_INTS_CLK_SYS_RESUS_Msk (0x1UL) /*!< CLK_SYS_RESUS (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ TICKS ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== PROC0_CTRL ======================================================= */ +#define TICKS_PROC0_CTRL_RUNNING_Pos (1UL) /*!< RUNNING (Bit 1) */ +#define TICKS_PROC0_CTRL_RUNNING_Msk (0x2UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ +#define TICKS_PROC0_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define TICKS_PROC0_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ===================================================== PROC0_CYCLES ====================================================== */ +#define TICKS_PROC0_CYCLES_PROC0_CYCLES_Pos (0UL) /*!< PROC0_CYCLES (Bit 0) */ +#define TICKS_PROC0_CYCLES_PROC0_CYCLES_Msk (0x1ffUL) /*!< PROC0_CYCLES (Bitfield-Mask: 0x1ff) */ +/* ====================================================== PROC0_COUNT ====================================================== */ +#define TICKS_PROC0_COUNT_PROC0_COUNT_Pos (0UL) /*!< PROC0_COUNT (Bit 0) */ +#define TICKS_PROC0_COUNT_PROC0_COUNT_Msk (0x1ffUL) /*!< PROC0_COUNT (Bitfield-Mask: 0x1ff) */ +/* ====================================================== PROC1_CTRL ======================================================= */ +#define TICKS_PROC1_CTRL_RUNNING_Pos (1UL) /*!< RUNNING (Bit 1) */ +#define TICKS_PROC1_CTRL_RUNNING_Msk (0x2UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ +#define TICKS_PROC1_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define TICKS_PROC1_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ===================================================== PROC1_CYCLES ====================================================== */ +#define TICKS_PROC1_CYCLES_PROC1_CYCLES_Pos (0UL) /*!< PROC1_CYCLES (Bit 0) */ +#define TICKS_PROC1_CYCLES_PROC1_CYCLES_Msk (0x1ffUL) /*!< PROC1_CYCLES (Bitfield-Mask: 0x1ff) */ +/* ====================================================== PROC1_COUNT ====================================================== */ +#define TICKS_PROC1_COUNT_PROC1_COUNT_Pos (0UL) /*!< PROC1_COUNT (Bit 0) */ +#define TICKS_PROC1_COUNT_PROC1_COUNT_Msk (0x1ffUL) /*!< PROC1_COUNT (Bitfield-Mask: 0x1ff) */ +/* ====================================================== TIMER0_CTRL ====================================================== */ +#define TICKS_TIMER0_CTRL_RUNNING_Pos (1UL) /*!< RUNNING (Bit 1) */ +#define TICKS_TIMER0_CTRL_RUNNING_Msk (0x2UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ +#define TICKS_TIMER0_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define TICKS_TIMER0_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ===================================================== TIMER0_CYCLES ===================================================== */ +#define TICKS_TIMER0_CYCLES_TIMER0_CYCLES_Pos (0UL) /*!< TIMER0_CYCLES (Bit 0) */ +#define TICKS_TIMER0_CYCLES_TIMER0_CYCLES_Msk (0x1ffUL) /*!< TIMER0_CYCLES (Bitfield-Mask: 0x1ff) */ +/* ===================================================== TIMER0_COUNT ====================================================== */ +#define TICKS_TIMER0_COUNT_TIMER0_COUNT_Pos (0UL) /*!< TIMER0_COUNT (Bit 0) */ +#define TICKS_TIMER0_COUNT_TIMER0_COUNT_Msk (0x1ffUL) /*!< TIMER0_COUNT (Bitfield-Mask: 0x1ff) */ +/* ====================================================== TIMER1_CTRL ====================================================== */ +#define TICKS_TIMER1_CTRL_RUNNING_Pos (1UL) /*!< RUNNING (Bit 1) */ +#define TICKS_TIMER1_CTRL_RUNNING_Msk (0x2UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ +#define TICKS_TIMER1_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define TICKS_TIMER1_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ===================================================== TIMER1_CYCLES ===================================================== */ +#define TICKS_TIMER1_CYCLES_TIMER1_CYCLES_Pos (0UL) /*!< TIMER1_CYCLES (Bit 0) */ +#define TICKS_TIMER1_CYCLES_TIMER1_CYCLES_Msk (0x1ffUL) /*!< TIMER1_CYCLES (Bitfield-Mask: 0x1ff) */ +/* ===================================================== TIMER1_COUNT ====================================================== */ +#define TICKS_TIMER1_COUNT_TIMER1_COUNT_Pos (0UL) /*!< TIMER1_COUNT (Bit 0) */ +#define TICKS_TIMER1_COUNT_TIMER1_COUNT_Msk (0x1ffUL) /*!< TIMER1_COUNT (Bitfield-Mask: 0x1ff) */ +/* ===================================================== WATCHDOG_CTRL ===================================================== */ +#define TICKS_WATCHDOG_CTRL_RUNNING_Pos (1UL) /*!< RUNNING (Bit 1) */ +#define TICKS_WATCHDOG_CTRL_RUNNING_Msk (0x2UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ +#define TICKS_WATCHDOG_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define TICKS_WATCHDOG_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== WATCHDOG_CYCLES ==================================================== */ +#define TICKS_WATCHDOG_CYCLES_WATCHDOG_CYCLES_Pos (0UL) /*!< WATCHDOG_CYCLES (Bit 0) */ +#define TICKS_WATCHDOG_CYCLES_WATCHDOG_CYCLES_Msk (0x1ffUL) /*!< WATCHDOG_CYCLES (Bitfield-Mask: 0x1ff) */ +/* ==================================================== WATCHDOG_COUNT ===================================================== */ +#define TICKS_WATCHDOG_COUNT_WATCHDOG_COUNT_Pos (0UL) /*!< WATCHDOG_COUNT (Bit 0) */ +#define TICKS_WATCHDOG_COUNT_WATCHDOG_COUNT_Msk (0x1ffUL) /*!< WATCHDOG_COUNT (Bitfield-Mask: 0x1ff) */ +/* ====================================================== RISCV_CTRL ======================================================= */ +#define TICKS_RISCV_CTRL_RUNNING_Pos (1UL) /*!< RUNNING (Bit 1) */ +#define TICKS_RISCV_CTRL_RUNNING_Msk (0x2UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ +#define TICKS_RISCV_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define TICKS_RISCV_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ===================================================== RISCV_CYCLES ====================================================== */ +#define TICKS_RISCV_CYCLES_RISCV_CYCLES_Pos (0UL) /*!< RISCV_CYCLES (Bit 0) */ +#define TICKS_RISCV_CYCLES_RISCV_CYCLES_Msk (0x1ffUL) /*!< RISCV_CYCLES (Bitfield-Mask: 0x1ff) */ +/* ====================================================== RISCV_COUNT ====================================================== */ +#define TICKS_RISCV_COUNT_RISCV_COUNT_Pos (0UL) /*!< RISCV_COUNT (Bit 0) */ +#define TICKS_RISCV_COUNT_RISCV_COUNT_Msk (0x1ffUL) /*!< RISCV_COUNT (Bitfield-Mask: 0x1ff) */ + + +/* =========================================================================================================================== */ +/* ================ PADS_BANK0 ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== VOLTAGE_SELECT ===================================================== */ +#define PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_Pos (0UL) /*!< VOLTAGE_SELECT (Bit 0) */ +#define PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_Msk (0x1UL) /*!< VOLTAGE_SELECT (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO0 ========================================================= */ +#define PADS_BANK0_GPIO0_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO0_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO0_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO0_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO0_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO0_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO0_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO0_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO0_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO0_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO0_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO0_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO0_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO0_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO0_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO0_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO1 ========================================================= */ +#define PADS_BANK0_GPIO1_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO1_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO1_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO1_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO1_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO1_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO1_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO1_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO1_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO1_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO1_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO1_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO1_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO1_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO1_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO1_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO2 ========================================================= */ +#define PADS_BANK0_GPIO2_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO2_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO2_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO2_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO2_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO2_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO2_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO2_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO2_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO2_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO2_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO2_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO2_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO2_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO2_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO2_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO3 ========================================================= */ +#define PADS_BANK0_GPIO3_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO3_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO3_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO3_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO3_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO3_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO3_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO3_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO3_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO3_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO3_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO3_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO3_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO3_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO3_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO3_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO4 ========================================================= */ +#define PADS_BANK0_GPIO4_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO4_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO4_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO4_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO4_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO4_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO4_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO4_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO4_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO4_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO4_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO4_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO4_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO4_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO4_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO4_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO5 ========================================================= */ +#define PADS_BANK0_GPIO5_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO5_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO5_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO5_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO5_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO5_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO5_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO5_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO5_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO5_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO5_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO5_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO5_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO5_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO5_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO5_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO6 ========================================================= */ +#define PADS_BANK0_GPIO6_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO6_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO6_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO6_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO6_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO6_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO6_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO6_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO6_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO6_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO6_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO6_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO6_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO6_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO6_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO6_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO7 ========================================================= */ +#define PADS_BANK0_GPIO7_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO7_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO7_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO7_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO7_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO7_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO7_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO7_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO7_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO7_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO7_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO7_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO7_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO7_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO7_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO7_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO8 ========================================================= */ +#define PADS_BANK0_GPIO8_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO8_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO8_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO8_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO8_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO8_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO8_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO8_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO8_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO8_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO8_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO8_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO8_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO8_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO8_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO8_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= GPIO9 ========================================================= */ +#define PADS_BANK0_GPIO9_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO9_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO9_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO9_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO9_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO9_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO9_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO9_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO9_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO9_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO9_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO9_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO9_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO9_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO9_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO9_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO10 ========================================================= */ +#define PADS_BANK0_GPIO10_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO10_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO10_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO10_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO10_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO10_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO10_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO10_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO10_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO10_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO10_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO10_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO10_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO10_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO10_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO10_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO11 ========================================================= */ +#define PADS_BANK0_GPIO11_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO11_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO11_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO11_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO11_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO11_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO11_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO11_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO11_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO11_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO11_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO11_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO11_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO11_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO11_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO11_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO12 ========================================================= */ +#define PADS_BANK0_GPIO12_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO12_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO12_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO12_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO12_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO12_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO12_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO12_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO12_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO12_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO12_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO12_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO12_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO12_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO12_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO12_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO13 ========================================================= */ +#define PADS_BANK0_GPIO13_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO13_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO13_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO13_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO13_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO13_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO13_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO13_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO13_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO13_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO13_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO13_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO13_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO13_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO13_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO13_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO14 ========================================================= */ +#define PADS_BANK0_GPIO14_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO14_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO14_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO14_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO14_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO14_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO14_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO14_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO14_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO14_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO14_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO14_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO14_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO14_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO14_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO14_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO15 ========================================================= */ +#define PADS_BANK0_GPIO15_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO15_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO15_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO15_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO15_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO15_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO15_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO15_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO15_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO15_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO15_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO15_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO15_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO15_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO15_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO15_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO16 ========================================================= */ +#define PADS_BANK0_GPIO16_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO16_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO16_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO16_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO16_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO16_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO16_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO16_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO16_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO16_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO16_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO16_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO16_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO16_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO16_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO16_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO17 ========================================================= */ +#define PADS_BANK0_GPIO17_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO17_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO17_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO17_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO17_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO17_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO17_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO17_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO17_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO17_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO17_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO17_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO17_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO17_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO17_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO17_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO18 ========================================================= */ +#define PADS_BANK0_GPIO18_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO18_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO18_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO18_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO18_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO18_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO18_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO18_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO18_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO18_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO18_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO18_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO18_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO18_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO18_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO18_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO19 ========================================================= */ +#define PADS_BANK0_GPIO19_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO19_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO19_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO19_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO19_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO19_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO19_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO19_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO19_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO19_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO19_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO19_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO19_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO19_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO19_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO19_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO20 ========================================================= */ +#define PADS_BANK0_GPIO20_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO20_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO20_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO20_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO20_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO20_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO20_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO20_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO20_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO20_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO20_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO20_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO20_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO20_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO20_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO20_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO21 ========================================================= */ +#define PADS_BANK0_GPIO21_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO21_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO21_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO21_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO21_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO21_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO21_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO21_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO21_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO21_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO21_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO21_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO21_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO21_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO21_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO21_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO22 ========================================================= */ +#define PADS_BANK0_GPIO22_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO22_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO22_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO22_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO22_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO22_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO22_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO22_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO22_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO22_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO22_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO22_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO22_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO22_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO22_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO22_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO23 ========================================================= */ +#define PADS_BANK0_GPIO23_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO23_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO23_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO23_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO23_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO23_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO23_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO23_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO23_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO23_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO23_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO23_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO23_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO23_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO23_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO23_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO24 ========================================================= */ +#define PADS_BANK0_GPIO24_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO24_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO24_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO24_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO24_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO24_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO24_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO24_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO24_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO24_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO24_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO24_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO24_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO24_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO24_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO24_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO25 ========================================================= */ +#define PADS_BANK0_GPIO25_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO25_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO25_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO25_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO25_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO25_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO25_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO25_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO25_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO25_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO25_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO25_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO25_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO25_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO25_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO25_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO26 ========================================================= */ +#define PADS_BANK0_GPIO26_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO26_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO26_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO26_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO26_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO26_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO26_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO26_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO26_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO26_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO26_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO26_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO26_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO26_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO26_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO26_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO27 ========================================================= */ +#define PADS_BANK0_GPIO27_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO27_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO27_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO27_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO27_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO27_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO27_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO27_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO27_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO27_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO27_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO27_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO27_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO27_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO27_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO27_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO28 ========================================================= */ +#define PADS_BANK0_GPIO28_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO28_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO28_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO28_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO28_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO28_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO28_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO28_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO28_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO28_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO28_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO28_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO28_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO28_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO28_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO28_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO29 ========================================================= */ +#define PADS_BANK0_GPIO29_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO29_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO29_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO29_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO29_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO29_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO29_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO29_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO29_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO29_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO29_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO29_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO29_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO29_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO29_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO29_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO30 ========================================================= */ +#define PADS_BANK0_GPIO30_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO30_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO30_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO30_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO30_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO30_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO30_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO30_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO30_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO30_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO30_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO30_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO30_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO30_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO30_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO30_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO31 ========================================================= */ +#define PADS_BANK0_GPIO31_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO31_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO31_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO31_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO31_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO31_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO31_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO31_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO31_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO31_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO31_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO31_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO31_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO31_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO31_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO31_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO32 ========================================================= */ +#define PADS_BANK0_GPIO32_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO32_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO32_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO32_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO32_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO32_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO32_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO32_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO32_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO32_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO32_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO32_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO32_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO32_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO32_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO32_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO33 ========================================================= */ +#define PADS_BANK0_GPIO33_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO33_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO33_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO33_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO33_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO33_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO33_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO33_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO33_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO33_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO33_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO33_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO33_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO33_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO33_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO33_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO34 ========================================================= */ +#define PADS_BANK0_GPIO34_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO34_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO34_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO34_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO34_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO34_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO34_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO34_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO34_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO34_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO34_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO34_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO34_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO34_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO34_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO34_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO35 ========================================================= */ +#define PADS_BANK0_GPIO35_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO35_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO35_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO35_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO35_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO35_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO35_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO35_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO35_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO35_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO35_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO35_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO35_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO35_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO35_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO35_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO36 ========================================================= */ +#define PADS_BANK0_GPIO36_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO36_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO36_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO36_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO36_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO36_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO36_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO36_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO36_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO36_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO36_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO36_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO36_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO36_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO36_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO36_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO37 ========================================================= */ +#define PADS_BANK0_GPIO37_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO37_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO37_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO37_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO37_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO37_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO37_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO37_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO37_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO37_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO37_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO37_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO37_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO37_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO37_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO37_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO38 ========================================================= */ +#define PADS_BANK0_GPIO38_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO38_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO38_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO38_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO38_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO38_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO38_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO38_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO38_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO38_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO38_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO38_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO38_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO38_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO38_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO38_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO39 ========================================================= */ +#define PADS_BANK0_GPIO39_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO39_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO39_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO39_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO39_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO39_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO39_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO39_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO39_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO39_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO39_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO39_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO39_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO39_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO39_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO39_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO40 ========================================================= */ +#define PADS_BANK0_GPIO40_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO40_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO40_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO40_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO40_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO40_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO40_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO40_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO40_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO40_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO40_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO40_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO40_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO40_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO40_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO40_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO41 ========================================================= */ +#define PADS_BANK0_GPIO41_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO41_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO41_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO41_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO41_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO41_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO41_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO41_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO41_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO41_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO41_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO41_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO41_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO41_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO41_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO41_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO42 ========================================================= */ +#define PADS_BANK0_GPIO42_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO42_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO42_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO42_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO42_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO42_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO42_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO42_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO42_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO42_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO42_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO42_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO42_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO42_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO42_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO42_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO43 ========================================================= */ +#define PADS_BANK0_GPIO43_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO43_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO43_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO43_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO43_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO43_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO43_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO43_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO43_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO43_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO43_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO43_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO43_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO43_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO43_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO43_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO44 ========================================================= */ +#define PADS_BANK0_GPIO44_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO44_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO44_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO44_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO44_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO44_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO44_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO44_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO44_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO44_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO44_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO44_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO44_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO44_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO44_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO44_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO45 ========================================================= */ +#define PADS_BANK0_GPIO45_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO45_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO45_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO45_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO45_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO45_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO45_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO45_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO45_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO45_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO45_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO45_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO45_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO45_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO45_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO45_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO46 ========================================================= */ +#define PADS_BANK0_GPIO46_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO46_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO46_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO46_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO46_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO46_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO46_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO46_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO46_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO46_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO46_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO46_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO46_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO46_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO46_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO46_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ======================================================== GPIO47 ========================================================= */ +#define PADS_BANK0_GPIO47_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_GPIO47_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO47_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_GPIO47_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO47_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_GPIO47_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO47_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_GPIO47_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_GPIO47_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_GPIO47_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO47_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_GPIO47_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO47_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_GPIO47_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_GPIO47_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_GPIO47_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================= SWCLK ========================================================= */ +#define PADS_BANK0_SWCLK_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_SWCLK_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWCLK_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_SWCLK_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWCLK_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_SWCLK_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWCLK_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_SWCLK_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_SWCLK_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_SWCLK_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWCLK_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_SWCLK_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWCLK_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_SWCLK_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWCLK_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_SWCLK_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ========================================================== SWD ========================================================== */ +#define PADS_BANK0_SWD_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_BANK0_SWD_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWD_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_BANK0_SWD_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWD_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_BANK0_SWD_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWD_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_BANK0_SWD_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_BANK0_SWD_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_BANK0_SWD_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWD_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_BANK0_SWD_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWD_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_BANK0_SWD_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_BANK0_SWD_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_BANK0_SWD_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ PADS_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== VOLTAGE_SELECT ===================================================== */ +#define PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_Pos (0UL) /*!< VOLTAGE_SELECT (Bit 0) */ +#define PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_Msk (0x1UL) /*!< VOLTAGE_SELECT (Bitfield-Mask: 0x01) */ +/* ==================================================== GPIO_QSPI_SCLK ===================================================== */ +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ===================================================== GPIO_QSPI_SD0 ===================================================== */ +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD0_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_QSPI_GPIO_QSPI_SD0_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD0_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_QSPI_GPIO_QSPI_SD0_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ===================================================== GPIO_QSPI_SD1 ===================================================== */ +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD1_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_QSPI_GPIO_QSPI_SD1_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD1_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_QSPI_GPIO_QSPI_SD1_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ===================================================== GPIO_QSPI_SD2 ===================================================== */ +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD2_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_QSPI_GPIO_QSPI_SD2_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD2_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_QSPI_GPIO_QSPI_SD2_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ===================================================== GPIO_QSPI_SD3 ===================================================== */ +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD3_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_QSPI_GPIO_QSPI_SD3_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD3_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_QSPI_GPIO_QSPI_SD3_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ +/* ===================================================== GPIO_QSPI_SS ====================================================== */ +#define PADS_QSPI_GPIO_QSPI_SS_ISO_Pos (8UL) /*!< ISO (Bit 8) */ +#define PADS_QSPI_GPIO_QSPI_SS_ISO_Msk (0x100UL) /*!< ISO (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SS_OD_Pos (7UL) /*!< OD (Bit 7) */ +#define PADS_QSPI_GPIO_QSPI_SS_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SS_IE_Pos (6UL) /*!< IE (Bit 6) */ +#define PADS_QSPI_GPIO_QSPI_SS_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */ +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */ +#define PADS_QSPI_GPIO_QSPI_SS_PUE_Pos (3UL) /*!< PUE (Bit 3) */ +#define PADS_QSPI_GPIO_QSPI_SS_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SS_PDE_Pos (2UL) /*!< PDE (Bit 2) */ +#define PADS_QSPI_GPIO_QSPI_SS_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */ +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */ +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */ +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IO_QSPI ================ */ +/* =========================================================================================================================== */ + +/* =================================================== USBPHY_DP_STATUS ==================================================== */ +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ==================================================== USBPHY_DP_CTRL ===================================================== */ +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* =================================================== USBPHY_DM_STATUS ==================================================== */ +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ==================================================== USBPHY_DM_CTRL ===================================================== */ +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ================================================= GPIO_QSPI_SCLK_STATUS ================================================= */ +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ================================================== GPIO_QSPI_SCLK_CTRL ================================================== */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ================================================== GPIO_QSPI_SS_STATUS ================================================== */ +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* =================================================== GPIO_QSPI_SS_CTRL =================================================== */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ================================================= GPIO_QSPI_SD0_STATUS ================================================== */ +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ================================================== GPIO_QSPI_SD0_CTRL =================================================== */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ================================================= GPIO_QSPI_SD1_STATUS ================================================== */ +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ================================================== GPIO_QSPI_SD1_CTRL =================================================== */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ================================================= GPIO_QSPI_SD2_STATUS ================================================== */ +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ================================================== GPIO_QSPI_SD2_CTRL =================================================== */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ================================================= GPIO_QSPI_SD3_STATUS ================================================== */ +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ================================================== GPIO_QSPI_SD3_CTRL =================================================== */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ================================================ IRQSUMMARY_PROC0_SECURE ================================================ */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_Pos (7UL) /*!< GPIO_QSPI_SD3 (Bit 7) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_Msk (0x80UL) /*!< GPIO_QSPI_SD3 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_Pos (6UL) /*!< GPIO_QSPI_SD2 (Bit 6) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_Msk (0x40UL) /*!< GPIO_QSPI_SD2 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_Pos (5UL) /*!< GPIO_QSPI_SD1 (Bit 5) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_Msk (0x20UL) /*!< GPIO_QSPI_SD1 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_Pos (4UL) /*!< GPIO_QSPI_SD0 (Bit 4) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_Msk (0x10UL) /*!< GPIO_QSPI_SD0 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_Pos (3UL) /*!< GPIO_QSPI_SS (Bit 3) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_Msk (0x8UL) /*!< GPIO_QSPI_SS (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_Pos (2UL) /*!< GPIO_QSPI_SCLK (Bit 2) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_Msk (0x4UL) /*!< GPIO_QSPI_SCLK (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_Pos (1UL) /*!< USBPHY_DM (Bit 1) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_Msk (0x2UL) /*!< USBPHY_DM (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_Pos (0UL) /*!< USBPHY_DP (Bit 0) */ +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_Msk (0x1UL) /*!< USBPHY_DP (Bitfield-Mask: 0x01) */ +/* ============================================== IRQSUMMARY_PROC0_NONSECURE =============================================== */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_Pos (7UL) /*!< GPIO_QSPI_SD3 (Bit 7) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_Msk (0x80UL) /*!< GPIO_QSPI_SD3 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_Pos (6UL) /*!< GPIO_QSPI_SD2 (Bit 6) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_Msk (0x40UL) /*!< GPIO_QSPI_SD2 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_Pos (5UL) /*!< GPIO_QSPI_SD1 (Bit 5) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_Msk (0x20UL) /*!< GPIO_QSPI_SD1 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_Pos (4UL) /*!< GPIO_QSPI_SD0 (Bit 4) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_Msk (0x10UL) /*!< GPIO_QSPI_SD0 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_Pos (3UL) /*!< GPIO_QSPI_SS (Bit 3) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_Msk (0x8UL) /*!< GPIO_QSPI_SS (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_Pos (2UL) /*!< GPIO_QSPI_SCLK (Bit 2) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_Msk (0x4UL) /*!< GPIO_QSPI_SCLK (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_Pos (1UL) /*!< USBPHY_DM (Bit 1) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_Msk (0x2UL) /*!< USBPHY_DM (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_Pos (0UL) /*!< USBPHY_DP (Bit 0) */ +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_Msk (0x1UL) /*!< USBPHY_DP (Bitfield-Mask: 0x01) */ +/* ================================================ IRQSUMMARY_PROC1_SECURE ================================================ */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_Pos (7UL) /*!< GPIO_QSPI_SD3 (Bit 7) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_Msk (0x80UL) /*!< GPIO_QSPI_SD3 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_Pos (6UL) /*!< GPIO_QSPI_SD2 (Bit 6) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_Msk (0x40UL) /*!< GPIO_QSPI_SD2 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_Pos (5UL) /*!< GPIO_QSPI_SD1 (Bit 5) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_Msk (0x20UL) /*!< GPIO_QSPI_SD1 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_Pos (4UL) /*!< GPIO_QSPI_SD0 (Bit 4) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_Msk (0x10UL) /*!< GPIO_QSPI_SD0 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_Pos (3UL) /*!< GPIO_QSPI_SS (Bit 3) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_Msk (0x8UL) /*!< GPIO_QSPI_SS (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_Pos (2UL) /*!< GPIO_QSPI_SCLK (Bit 2) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_Msk (0x4UL) /*!< GPIO_QSPI_SCLK (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_Pos (1UL) /*!< USBPHY_DM (Bit 1) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_Msk (0x2UL) /*!< USBPHY_DM (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_Pos (0UL) /*!< USBPHY_DP (Bit 0) */ +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_Msk (0x1UL) /*!< USBPHY_DP (Bitfield-Mask: 0x01) */ +/* ============================================== IRQSUMMARY_PROC1_NONSECURE =============================================== */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_Pos (7UL) /*!< GPIO_QSPI_SD3 (Bit 7) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_Msk (0x80UL) /*!< GPIO_QSPI_SD3 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_Pos (6UL) /*!< GPIO_QSPI_SD2 (Bit 6) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_Msk (0x40UL) /*!< GPIO_QSPI_SD2 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_Pos (5UL) /*!< GPIO_QSPI_SD1 (Bit 5) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_Msk (0x20UL) /*!< GPIO_QSPI_SD1 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_Pos (4UL) /*!< GPIO_QSPI_SD0 (Bit 4) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_Msk (0x10UL) /*!< GPIO_QSPI_SD0 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_Pos (3UL) /*!< GPIO_QSPI_SS (Bit 3) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_Msk (0x8UL) /*!< GPIO_QSPI_SS (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_Pos (2UL) /*!< GPIO_QSPI_SCLK (Bit 2) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_Msk (0x4UL) /*!< GPIO_QSPI_SCLK (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_Pos (1UL) /*!< USBPHY_DM (Bit 1) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_Msk (0x2UL) /*!< USBPHY_DM (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_Pos (0UL) /*!< USBPHY_DP (Bit 0) */ +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_Msk (0x1UL) /*!< USBPHY_DP (Bitfield-Mask: 0x01) */ +/* ============================================ IRQSUMMARY_DORMANT_WAKE_SECURE ============================================= */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_Pos (7UL) /*!< GPIO_QSPI_SD3 (Bit 7) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_Msk (0x80UL) /*!< GPIO_QSPI_SD3 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_Pos (6UL) /*!< GPIO_QSPI_SD2 (Bit 6) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_Msk (0x40UL) /*!< GPIO_QSPI_SD2 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_Pos (5UL) /*!< GPIO_QSPI_SD1 (Bit 5) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_Msk (0x20UL) /*!< GPIO_QSPI_SD1 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_Pos (4UL) /*!< GPIO_QSPI_SD0 (Bit 4) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_Msk (0x10UL) /*!< GPIO_QSPI_SD0 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_Pos (3UL) /*!< GPIO_QSPI_SS (Bit 3) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_Msk (0x8UL) /*!< GPIO_QSPI_SS (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_Pos (2UL) /*!< GPIO_QSPI_SCLK (Bit 2) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_Msk (0x4UL) /*!< GPIO_QSPI_SCLK (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_Pos (1UL) /*!< USBPHY_DM (Bit 1) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_Msk (0x2UL) /*!< USBPHY_DM (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_Pos (0UL) /*!< USBPHY_DP (Bit 0) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_Msk (0x1UL) /*!< USBPHY_DP (Bitfield-Mask: 0x01) */ +/* =========================================== IRQSUMMARY_DORMANT_WAKE_NONSECURE =========================================== */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_Pos (7UL) /*!< GPIO_QSPI_SD3 (Bit 7) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_Msk (0x80UL) /*!< GPIO_QSPI_SD3 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_Pos (6UL) /*!< GPIO_QSPI_SD2 (Bit 6) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_Msk (0x40UL) /*!< GPIO_QSPI_SD2 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_Pos (5UL) /*!< GPIO_QSPI_SD1 (Bit 5) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_Msk (0x20UL) /*!< GPIO_QSPI_SD1 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_Pos (4UL) /*!< GPIO_QSPI_SD0 (Bit 4) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_Msk (0x10UL) /*!< GPIO_QSPI_SD0 (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_Pos (3UL) /*!< GPIO_QSPI_SS (Bit 3) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_Msk (0x8UL) /*!< GPIO_QSPI_SS (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_Pos (2UL) /*!< GPIO_QSPI_SCLK (Bit 2) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_Msk (0x4UL) /*!< GPIO_QSPI_SCLK (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_Pos (1UL) /*!< USBPHY_DM (Bit 1) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_Msk (0x2UL) /*!< USBPHY_DM (Bitfield-Mask: 0x01) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_Pos (0UL) /*!< USBPHY_DP (Bit 0) */ +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_Msk (0x1UL) /*!< USBPHY_DP (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR ========================================================== */ +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTE ======================================================= */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTF ======================================================= */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTS ======================================================= */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTE ======================================================= */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTF ======================================================= */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTS ======================================================= */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* =================================================== DORMANT_WAKE_INTE =================================================== */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* =================================================== DORMANT_WAKE_INTF =================================================== */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* =================================================== DORMANT_WAKE_INTS =================================================== */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Pos (31UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 31) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_Pos (30UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 30) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (29UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 29) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Pos (28UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 28) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Pos (27UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 27) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_Pos (26UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 26) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (25UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 25) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Pos (24UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 24) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 23) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 22) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 21) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 20) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 19) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 18) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 17) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 16) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 15) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 14) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 13) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 12) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 11) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 10) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 9) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 8) */ +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_Pos (7UL) /*!< USBPHY_DM_EDGE_HIGH (Bit 7) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_Msk (0x80UL) /*!< USBPHY_DM_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_Pos (6UL) /*!< USBPHY_DM_EDGE_LOW (Bit 6) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_Msk (0x40UL) /*!< USBPHY_DM_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_Pos (5UL) /*!< USBPHY_DM_LEVEL_HIGH (Bit 5) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_Msk (0x20UL) /*!< USBPHY_DM_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_Pos (4UL) /*!< USBPHY_DM_LEVEL_LOW (Bit 4) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_Msk (0x10UL) /*!< USBPHY_DM_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_Pos (3UL) /*!< USBPHY_DP_EDGE_HIGH (Bit 3) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_Msk (0x8UL) /*!< USBPHY_DP_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_Pos (2UL) /*!< USBPHY_DP_EDGE_LOW (Bit 2) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_Msk (0x4UL) /*!< USBPHY_DP_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_Pos (1UL) /*!< USBPHY_DP_LEVEL_HIGH (Bit 1) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_Msk (0x2UL) /*!< USBPHY_DP_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_Pos (0UL) /*!< USBPHY_DP_LEVEL_LOW (Bit 0) */ +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_Msk (0x1UL) /*!< USBPHY_DP_LEVEL_LOW (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IO_BANK0 ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== GPIO0_STATUS ====================================================== */ +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO0_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO0_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO0_CTRL ======================================================= */ +#define IO_BANK0_GPIO0_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO0_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO0_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO0_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO0_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO0_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO0_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO0_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO1_STATUS ====================================================== */ +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO1_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO1_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO1_CTRL ======================================================= */ +#define IO_BANK0_GPIO1_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO1_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO1_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO1_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO1_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO1_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO1_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO1_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO2_STATUS ====================================================== */ +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO2_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO2_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO2_CTRL ======================================================= */ +#define IO_BANK0_GPIO2_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO2_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO2_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO2_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO2_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO2_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO2_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO2_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO3_STATUS ====================================================== */ +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO3_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO3_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO3_CTRL ======================================================= */ +#define IO_BANK0_GPIO3_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO3_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO3_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO3_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO3_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO3_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO3_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO3_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO4_STATUS ====================================================== */ +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO4_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO4_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO4_CTRL ======================================================= */ +#define IO_BANK0_GPIO4_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO4_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO4_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO4_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO4_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO4_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO4_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO4_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO5_STATUS ====================================================== */ +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO5_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO5_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO5_CTRL ======================================================= */ +#define IO_BANK0_GPIO5_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO5_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO5_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO5_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO5_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO5_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO5_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO5_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO6_STATUS ====================================================== */ +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO6_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO6_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO6_CTRL ======================================================= */ +#define IO_BANK0_GPIO6_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO6_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO6_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO6_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO6_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO6_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO6_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO6_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO7_STATUS ====================================================== */ +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO7_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO7_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO7_CTRL ======================================================= */ +#define IO_BANK0_GPIO7_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO7_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO7_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO7_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO7_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO7_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO7_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO7_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO8_STATUS ====================================================== */ +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO8_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO8_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO8_CTRL ======================================================= */ +#define IO_BANK0_GPIO8_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO8_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO8_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO8_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO8_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO8_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO8_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO8_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO9_STATUS ====================================================== */ +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO9_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO9_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO9_CTRL ======================================================= */ +#define IO_BANK0_GPIO9_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO9_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO9_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO9_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO9_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO9_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO9_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO9_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO10_STATUS ===================================================== */ +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO10_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO10_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO10_CTRL ====================================================== */ +#define IO_BANK0_GPIO10_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO10_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO10_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO10_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO10_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO10_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO10_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO10_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO11_STATUS ===================================================== */ +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO11_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO11_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO11_CTRL ====================================================== */ +#define IO_BANK0_GPIO11_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO11_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO11_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO11_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO11_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO11_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO11_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO11_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO12_STATUS ===================================================== */ +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO12_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO12_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO12_CTRL ====================================================== */ +#define IO_BANK0_GPIO12_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO12_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO12_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO12_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO12_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO12_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO12_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO12_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO13_STATUS ===================================================== */ +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO13_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO13_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO13_CTRL ====================================================== */ +#define IO_BANK0_GPIO13_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO13_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO13_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO13_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO13_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO13_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO13_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO13_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO14_STATUS ===================================================== */ +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO14_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO14_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO14_CTRL ====================================================== */ +#define IO_BANK0_GPIO14_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO14_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO14_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO14_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO14_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO14_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO14_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO14_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO15_STATUS ===================================================== */ +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO15_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO15_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO15_CTRL ====================================================== */ +#define IO_BANK0_GPIO15_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO15_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO15_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO15_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO15_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO15_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO15_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO15_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO16_STATUS ===================================================== */ +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO16_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO16_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO16_CTRL ====================================================== */ +#define IO_BANK0_GPIO16_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO16_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO16_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO16_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO16_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO16_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO16_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO16_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO17_STATUS ===================================================== */ +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO17_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO17_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO17_CTRL ====================================================== */ +#define IO_BANK0_GPIO17_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO17_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO17_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO17_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO17_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO17_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO17_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO17_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO18_STATUS ===================================================== */ +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO18_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO18_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO18_CTRL ====================================================== */ +#define IO_BANK0_GPIO18_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO18_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO18_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO18_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO18_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO18_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO18_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO18_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO19_STATUS ===================================================== */ +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO19_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO19_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO19_CTRL ====================================================== */ +#define IO_BANK0_GPIO19_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO19_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO19_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO19_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO19_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO19_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO19_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO19_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO20_STATUS ===================================================== */ +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO20_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO20_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO20_CTRL ====================================================== */ +#define IO_BANK0_GPIO20_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO20_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO20_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO20_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO20_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO20_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO20_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO20_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO21_STATUS ===================================================== */ +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO21_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO21_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO21_CTRL ====================================================== */ +#define IO_BANK0_GPIO21_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO21_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO21_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO21_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO21_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO21_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO21_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO21_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO22_STATUS ===================================================== */ +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO22_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO22_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO22_CTRL ====================================================== */ +#define IO_BANK0_GPIO22_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO22_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO22_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO22_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO22_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO22_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO22_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO22_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO23_STATUS ===================================================== */ +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO23_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO23_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO23_CTRL ====================================================== */ +#define IO_BANK0_GPIO23_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO23_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO23_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO23_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO23_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO23_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO23_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO23_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO24_STATUS ===================================================== */ +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO24_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO24_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO24_CTRL ====================================================== */ +#define IO_BANK0_GPIO24_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO24_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO24_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO24_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO24_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO24_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO24_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO24_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO25_STATUS ===================================================== */ +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO25_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO25_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO25_CTRL ====================================================== */ +#define IO_BANK0_GPIO25_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO25_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO25_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO25_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO25_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO25_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO25_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO25_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO26_STATUS ===================================================== */ +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO26_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO26_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO26_CTRL ====================================================== */ +#define IO_BANK0_GPIO26_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO26_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO26_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO26_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO26_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO26_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO26_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO26_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO27_STATUS ===================================================== */ +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO27_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO27_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO27_CTRL ====================================================== */ +#define IO_BANK0_GPIO27_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO27_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO27_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO27_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO27_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO27_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO27_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO27_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO28_STATUS ===================================================== */ +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO28_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO28_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO28_CTRL ====================================================== */ +#define IO_BANK0_GPIO28_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO28_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO28_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO28_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO28_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO28_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO28_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO28_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO29_STATUS ===================================================== */ +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO29_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO29_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO29_CTRL ====================================================== */ +#define IO_BANK0_GPIO29_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO29_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO29_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO29_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO29_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO29_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO29_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO29_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO30_STATUS ===================================================== */ +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO30_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO30_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO30_CTRL ====================================================== */ +#define IO_BANK0_GPIO30_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO30_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO30_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO30_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO30_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO30_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO30_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO30_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO31_STATUS ===================================================== */ +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO31_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO31_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO31_CTRL ====================================================== */ +#define IO_BANK0_GPIO31_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO31_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO31_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO31_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO31_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO31_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO31_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO31_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO32_STATUS ===================================================== */ +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO32_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO32_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO32_CTRL ====================================================== */ +#define IO_BANK0_GPIO32_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO32_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO32_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO32_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO32_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO32_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO32_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO32_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO33_STATUS ===================================================== */ +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO33_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO33_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO33_CTRL ====================================================== */ +#define IO_BANK0_GPIO33_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO33_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO33_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO33_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO33_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO33_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO33_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO33_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO34_STATUS ===================================================== */ +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO34_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO34_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO34_CTRL ====================================================== */ +#define IO_BANK0_GPIO34_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO34_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO34_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO34_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO34_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO34_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO34_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO34_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO35_STATUS ===================================================== */ +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO35_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO35_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO35_CTRL ====================================================== */ +#define IO_BANK0_GPIO35_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO35_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO35_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO35_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO35_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO35_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO35_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO35_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO36_STATUS ===================================================== */ +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO36_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO36_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO36_CTRL ====================================================== */ +#define IO_BANK0_GPIO36_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO36_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO36_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO36_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO36_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO36_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO36_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO36_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO37_STATUS ===================================================== */ +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO37_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO37_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO37_CTRL ====================================================== */ +#define IO_BANK0_GPIO37_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO37_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO37_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO37_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO37_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO37_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO37_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO37_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO38_STATUS ===================================================== */ +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO38_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO38_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO38_CTRL ====================================================== */ +#define IO_BANK0_GPIO38_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO38_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO38_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO38_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO38_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO38_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO38_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO38_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO39_STATUS ===================================================== */ +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO39_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO39_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO39_CTRL ====================================================== */ +#define IO_BANK0_GPIO39_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO39_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO39_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO39_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO39_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO39_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO39_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO39_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO40_STATUS ===================================================== */ +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO40_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO40_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO40_CTRL ====================================================== */ +#define IO_BANK0_GPIO40_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO40_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO40_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO40_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO40_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO40_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO40_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO40_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO41_STATUS ===================================================== */ +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO41_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO41_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO41_CTRL ====================================================== */ +#define IO_BANK0_GPIO41_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO41_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO41_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO41_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO41_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO41_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO41_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO41_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO42_STATUS ===================================================== */ +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO42_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO42_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO42_CTRL ====================================================== */ +#define IO_BANK0_GPIO42_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO42_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO42_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO42_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO42_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO42_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO42_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO42_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO43_STATUS ===================================================== */ +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO43_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO43_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO43_CTRL ====================================================== */ +#define IO_BANK0_GPIO43_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO43_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO43_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO43_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO43_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO43_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO43_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO43_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO44_STATUS ===================================================== */ +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO44_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO44_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO44_CTRL ====================================================== */ +#define IO_BANK0_GPIO44_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO44_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO44_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO44_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO44_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO44_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO44_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO44_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO45_STATUS ===================================================== */ +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO45_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO45_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO45_CTRL ====================================================== */ +#define IO_BANK0_GPIO45_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO45_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO45_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO45_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO45_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO45_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO45_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO45_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO46_STATUS ===================================================== */ +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO46_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO46_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO46_CTRL ====================================================== */ +#define IO_BANK0_GPIO46_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO46_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO46_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO46_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO46_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO46_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO46_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO46_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== GPIO47_STATUS ===================================================== */ +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */ +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */ +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO47_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */ +#define IO_BANK0_GPIO47_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */ +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */ +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO47_CTRL ====================================================== */ +#define IO_BANK0_GPIO47_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */ +#define IO_BANK0_GPIO47_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO47_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */ +#define IO_BANK0_GPIO47_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO47_CTRL_OEOVER_Pos (14UL) /*!< OEOVER (Bit 14) */ +#define IO_BANK0_GPIO47_CTRL_OEOVER_Msk (0xc000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO47_CTRL_OUTOVER_Pos (12UL) /*!< OUTOVER (Bit 12) */ +#define IO_BANK0_GPIO47_CTRL_OUTOVER_Msk (0x3000UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */ +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */ +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */ +/* =============================================== IRQSUMMARY_PROC0_SECURE0 ================================================ */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* =============================================== IRQSUMMARY_PROC0_SECURE1 ================================================ */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ============================================== IRQSUMMARY_PROC0_NONSECURE0 ============================================== */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ============================================== IRQSUMMARY_PROC0_NONSECURE1 ============================================== */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* =============================================== IRQSUMMARY_PROC1_SECURE0 ================================================ */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* =============================================== IRQSUMMARY_PROC1_SECURE1 ================================================ */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ============================================== IRQSUMMARY_PROC1_NONSECURE0 ============================================== */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ============================================== IRQSUMMARY_PROC1_NONSECURE1 ============================================== */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ============================================ IRQSUMMARY_DORMANT_WAKE_SECURE0 ============================================ */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ============================================ IRQSUMMARY_DORMANT_WAKE_SECURE1 ============================================ */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ========================================== IRQSUMMARY_DORMANT_WAKE_NONSECURE0 =========================================== */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ========================================== IRQSUMMARY_DORMANT_WAKE_NONSECURE1 =========================================== */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR0 ========================================================= */ +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR1 ========================================================= */ +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR2 ========================================================= */ +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR3 ========================================================= */ +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR4 ========================================================= */ +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR5 ========================================================= */ +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTE0 ====================================================== */ +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTE1 ====================================================== */ +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTE2 ====================================================== */ +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTE3 ====================================================== */ +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTE4 ====================================================== */ +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTE5 ====================================================== */ +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTF0 ====================================================== */ +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTF1 ====================================================== */ +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTF2 ====================================================== */ +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTF3 ====================================================== */ +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTF4 ====================================================== */ +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTF5 ====================================================== */ +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTS0 ====================================================== */ +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTS1 ====================================================== */ +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTS2 ====================================================== */ +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTS3 ====================================================== */ +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTS4 ====================================================== */ +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC0_INTS5 ====================================================== */ +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTE0 ====================================================== */ +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTE1 ====================================================== */ +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTE2 ====================================================== */ +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTE3 ====================================================== */ +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTE4 ====================================================== */ +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTE5 ====================================================== */ +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTF0 ====================================================== */ +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTF1 ====================================================== */ +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTF2 ====================================================== */ +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTF3 ====================================================== */ +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTF4 ====================================================== */ +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTF5 ====================================================== */ +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTS0 ====================================================== */ +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTS1 ====================================================== */ +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTS2 ====================================================== */ +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTS3 ====================================================== */ +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTS4 ====================================================== */ +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ====================================================== PROC1_INTS5 ====================================================== */ +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTE0 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTE1 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTE2 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTE3 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTE4 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTE5 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTF0 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTF1 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTF2 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTF3 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTF4 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTF5 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTS0 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTS1 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTS2 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTS3 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_Pos (31UL) /*!< GPIO31_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO31_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_Pos (30UL) /*!< GPIO31_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO31_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_Pos (29UL) /*!< GPIO31_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO31_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_Pos (28UL) /*!< GPIO31_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO31_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_Pos (27UL) /*!< GPIO30_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO30_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_Pos (26UL) /*!< GPIO30_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO30_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_Pos (25UL) /*!< GPIO30_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO30_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_Pos (24UL) /*!< GPIO30_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO30_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTS4 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_Pos (31UL) /*!< GPIO39_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO39_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_Pos (30UL) /*!< GPIO39_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO39_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_Pos (29UL) /*!< GPIO39_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO39_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_Pos (28UL) /*!< GPIO39_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO39_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_Pos (27UL) /*!< GPIO38_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO38_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_Pos (26UL) /*!< GPIO38_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO38_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_Pos (25UL) /*!< GPIO38_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO38_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_Pos (24UL) /*!< GPIO38_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO38_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_Pos (23UL) /*!< GPIO37_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO37_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_Pos (22UL) /*!< GPIO37_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_Msk (0x400000UL) /*!< GPIO37_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_Pos (21UL) /*!< GPIO37_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO37_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_Pos (20UL) /*!< GPIO37_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO37_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_Pos (19UL) /*!< GPIO36_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO36_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_Pos (18UL) /*!< GPIO36_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_Msk (0x40000UL) /*!< GPIO36_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_Pos (17UL) /*!< GPIO36_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO36_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_Pos (16UL) /*!< GPIO36_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO36_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_Pos (15UL) /*!< GPIO35_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO35_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_Pos (14UL) /*!< GPIO35_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_Msk (0x4000UL) /*!< GPIO35_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_Pos (13UL) /*!< GPIO35_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO35_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_Pos (12UL) /*!< GPIO35_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO35_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_Pos (11UL) /*!< GPIO34_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_Msk (0x800UL) /*!< GPIO34_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_Pos (10UL) /*!< GPIO34_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_Msk (0x400UL) /*!< GPIO34_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_Pos (9UL) /*!< GPIO34_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO34_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_Pos (8UL) /*!< GPIO34_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_Msk (0x100UL) /*!< GPIO34_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_Pos (7UL) /*!< GPIO33_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_Msk (0x80UL) /*!< GPIO33_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_Pos (6UL) /*!< GPIO33_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_Msk (0x40UL) /*!< GPIO33_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_Pos (5UL) /*!< GPIO33_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO33_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_Pos (4UL) /*!< GPIO33_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_Msk (0x10UL) /*!< GPIO33_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_Pos (3UL) /*!< GPIO32_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_Msk (0x8UL) /*!< GPIO32_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_Pos (2UL) /*!< GPIO32_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_Msk (0x4UL) /*!< GPIO32_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_Pos (1UL) /*!< GPIO32_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO32_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_Pos (0UL) /*!< GPIO32_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_Msk (0x1UL) /*!< GPIO32_LEVEL_LOW (Bitfield-Mask: 0x01) */ +/* ================================================== DORMANT_WAKE_INTS5 =================================================== */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_Pos (31UL) /*!< GPIO47_EDGE_HIGH (Bit 31) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO47_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_Pos (30UL) /*!< GPIO47_EDGE_LOW (Bit 30) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO47_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_Pos (29UL) /*!< GPIO47_LEVEL_HIGH (Bit 29) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO47_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_Pos (28UL) /*!< GPIO47_LEVEL_LOW (Bit 28) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO47_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_Pos (27UL) /*!< GPIO46_EDGE_HIGH (Bit 27) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO46_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_Pos (26UL) /*!< GPIO46_EDGE_LOW (Bit 26) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO46_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_Pos (25UL) /*!< GPIO46_LEVEL_HIGH (Bit 25) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO46_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_Pos (24UL) /*!< GPIO46_LEVEL_LOW (Bit 24) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO46_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_Pos (23UL) /*!< GPIO45_EDGE_HIGH (Bit 23) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO45_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_Pos (22UL) /*!< GPIO45_EDGE_LOW (Bit 22) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_Msk (0x400000UL) /*!< GPIO45_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_Pos (21UL) /*!< GPIO45_LEVEL_HIGH (Bit 21) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO45_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_Pos (20UL) /*!< GPIO45_LEVEL_LOW (Bit 20) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO45_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_Pos (19UL) /*!< GPIO44_EDGE_HIGH (Bit 19) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO44_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_Pos (18UL) /*!< GPIO44_EDGE_LOW (Bit 18) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_Msk (0x40000UL) /*!< GPIO44_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_Pos (17UL) /*!< GPIO44_LEVEL_HIGH (Bit 17) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO44_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_Pos (16UL) /*!< GPIO44_LEVEL_LOW (Bit 16) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO44_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_Pos (15UL) /*!< GPIO43_EDGE_HIGH (Bit 15) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO43_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_Pos (14UL) /*!< GPIO43_EDGE_LOW (Bit 14) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_Msk (0x4000UL) /*!< GPIO43_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_Pos (13UL) /*!< GPIO43_LEVEL_HIGH (Bit 13) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO43_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_Pos (12UL) /*!< GPIO43_LEVEL_LOW (Bit 12) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO43_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_Pos (11UL) /*!< GPIO42_EDGE_HIGH (Bit 11) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_Msk (0x800UL) /*!< GPIO42_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_Pos (10UL) /*!< GPIO42_EDGE_LOW (Bit 10) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_Msk (0x400UL) /*!< GPIO42_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_Pos (9UL) /*!< GPIO42_LEVEL_HIGH (Bit 9) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO42_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_Pos (8UL) /*!< GPIO42_LEVEL_LOW (Bit 8) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_Msk (0x100UL) /*!< GPIO42_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_Pos (7UL) /*!< GPIO41_EDGE_HIGH (Bit 7) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_Msk (0x80UL) /*!< GPIO41_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_Pos (6UL) /*!< GPIO41_EDGE_LOW (Bit 6) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_Msk (0x40UL) /*!< GPIO41_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_Pos (5UL) /*!< GPIO41_LEVEL_HIGH (Bit 5) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO41_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_Pos (4UL) /*!< GPIO41_LEVEL_LOW (Bit 4) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_Msk (0x10UL) /*!< GPIO41_LEVEL_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_Pos (3UL) /*!< GPIO40_EDGE_HIGH (Bit 3) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_Msk (0x8UL) /*!< GPIO40_EDGE_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_Pos (2UL) /*!< GPIO40_EDGE_LOW (Bit 2) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_Msk (0x4UL) /*!< GPIO40_EDGE_LOW (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_Pos (1UL) /*!< GPIO40_LEVEL_HIGH (Bit 1) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO40_LEVEL_HIGH (Bitfield-Mask: 0x01) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_Pos (0UL) /*!< GPIO40_LEVEL_LOW (Bit 0) */ +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_Msk (0x1UL) /*!< GPIO40_LEVEL_LOW (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SYSINFO ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIP_ID ======================================================== */ +#define SYSINFO_CHIP_ID_REVISION_Pos (28UL) /*!< REVISION (Bit 28) */ +#define SYSINFO_CHIP_ID_REVISION_Msk (0xf0000000UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define SYSINFO_CHIP_ID_PART_Pos (12UL) /*!< PART (Bit 12) */ +#define SYSINFO_CHIP_ID_PART_Msk (0xffff000UL) /*!< PART (Bitfield-Mask: 0xffff) */ +#define SYSINFO_CHIP_ID_MANUFACTURER_Pos (1UL) /*!< MANUFACTURER (Bit 1) */ +#define SYSINFO_CHIP_ID_MANUFACTURER_Msk (0xffeUL) /*!< MANUFACTURER (Bitfield-Mask: 0x7ff) */ +#define SYSINFO_CHIP_ID_STOP_BIT_Pos (0UL) /*!< STOP_BIT (Bit 0) */ +#define SYSINFO_CHIP_ID_STOP_BIT_Msk (0x1UL) /*!< STOP_BIT (Bitfield-Mask: 0x01) */ +/* ====================================================== PACKAGE_SEL ====================================================== */ +#define SYSINFO_PACKAGE_SEL_PACKAGE_SEL_Pos (0UL) /*!< PACKAGE_SEL (Bit 0) */ +#define SYSINFO_PACKAGE_SEL_PACKAGE_SEL_Msk (0x1UL) /*!< PACKAGE_SEL (Bitfield-Mask: 0x01) */ +/* ======================================================= PLATFORM ======================================================== */ +#define SYSINFO_PLATFORM_GATESIM_Pos (4UL) /*!< GATESIM (Bit 4) */ +#define SYSINFO_PLATFORM_GATESIM_Msk (0x10UL) /*!< GATESIM (Bitfield-Mask: 0x01) */ +#define SYSINFO_PLATFORM_BATCHSIM_Pos (3UL) /*!< BATCHSIM (Bit 3) */ +#define SYSINFO_PLATFORM_BATCHSIM_Msk (0x8UL) /*!< BATCHSIM (Bitfield-Mask: 0x01) */ +#define SYSINFO_PLATFORM_HDLSIM_Pos (2UL) /*!< HDLSIM (Bit 2) */ +#define SYSINFO_PLATFORM_HDLSIM_Msk (0x4UL) /*!< HDLSIM (Bitfield-Mask: 0x01) */ +#define SYSINFO_PLATFORM_ASIC_Pos (1UL) /*!< ASIC (Bit 1) */ +#define SYSINFO_PLATFORM_ASIC_Msk (0x2UL) /*!< ASIC (Bitfield-Mask: 0x01) */ +#define SYSINFO_PLATFORM_FPGA_Pos (0UL) /*!< FPGA (Bit 0) */ +#define SYSINFO_PLATFORM_FPGA_Msk (0x1UL) /*!< FPGA (Bitfield-Mask: 0x01) */ +/* ===================================================== GITREF_RP2350 ===================================================== */ +#define SYSINFO_GITREF_RP2350_GITREF_RP2350_Pos (0UL) /*!< GITREF_RP2350 (Bit 0) */ +#define SYSINFO_GITREF_RP2350_GITREF_RP2350_Msk (0xffffffffUL) /*!< GITREF_RP2350 (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ SHA256 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define SHA256_CSR_BSWAP_Pos (12UL) /*!< BSWAP (Bit 12) */ +#define SHA256_CSR_BSWAP_Msk (0x1000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define SHA256_CSR_DMA_SIZE_Pos (8UL) /*!< DMA_SIZE (Bit 8) */ +#define SHA256_CSR_DMA_SIZE_Msk (0x300UL) /*!< DMA_SIZE (Bitfield-Mask: 0x03) */ +#define SHA256_CSR_ERR_WDATA_NOT_RDY_Pos (4UL) /*!< ERR_WDATA_NOT_RDY (Bit 4) */ +#define SHA256_CSR_ERR_WDATA_NOT_RDY_Msk (0x10UL) /*!< ERR_WDATA_NOT_RDY (Bitfield-Mask: 0x01) */ +#define SHA256_CSR_SUM_VLD_Pos (2UL) /*!< SUM_VLD (Bit 2) */ +#define SHA256_CSR_SUM_VLD_Msk (0x4UL) /*!< SUM_VLD (Bitfield-Mask: 0x01) */ +#define SHA256_CSR_WDATA_RDY_Pos (1UL) /*!< WDATA_RDY (Bit 1) */ +#define SHA256_CSR_WDATA_RDY_Msk (0x2UL) /*!< WDATA_RDY (Bitfield-Mask: 0x01) */ +#define SHA256_CSR_START_Pos (0UL) /*!< START (Bit 0) */ +#define SHA256_CSR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= WDATA ========================================================= */ +#define SHA256_WDATA_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ +#define SHA256_WDATA_WDATA_Msk (0xffffffffUL) /*!< WDATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SUM0 ========================================================== */ +#define SHA256_SUM0_SUM0_Pos (0UL) /*!< SUM0 (Bit 0) */ +#define SHA256_SUM0_SUM0_Msk (0xffffffffUL) /*!< SUM0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SUM1 ========================================================== */ +#define SHA256_SUM1_SUM1_Pos (0UL) /*!< SUM1 (Bit 0) */ +#define SHA256_SUM1_SUM1_Msk (0xffffffffUL) /*!< SUM1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SUM2 ========================================================== */ +#define SHA256_SUM2_SUM2_Pos (0UL) /*!< SUM2 (Bit 0) */ +#define SHA256_SUM2_SUM2_Msk (0xffffffffUL) /*!< SUM2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SUM3 ========================================================== */ +#define SHA256_SUM3_SUM3_Pos (0UL) /*!< SUM3 (Bit 0) */ +#define SHA256_SUM3_SUM3_Msk (0xffffffffUL) /*!< SUM3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SUM4 ========================================================== */ +#define SHA256_SUM4_SUM4_Pos (0UL) /*!< SUM4 (Bit 0) */ +#define SHA256_SUM4_SUM4_Msk (0xffffffffUL) /*!< SUM4 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SUM5 ========================================================== */ +#define SHA256_SUM5_SUM5_Pos (0UL) /*!< SUM5 (Bit 0) */ +#define SHA256_SUM5_SUM5_Msk (0xffffffffUL) /*!< SUM5 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SUM6 ========================================================== */ +#define SHA256_SUM6_SUM6_Pos (0UL) /*!< SUM6 (Bit 0) */ +#define SHA256_SUM6_SUM6_Msk (0xffffffffUL) /*!< SUM6 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SUM7 ========================================================== */ +#define SHA256_SUM7_SUM7_Pos (0UL) /*!< SUM7 (Bit 0) */ +#define SHA256_SUM7_SUM7_Msk (0xffffffffUL) /*!< SUM7 (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ HSTX_FIFO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ +#define HSTX_FIFO_STAT_WOF_Pos (10UL) /*!< WOF (Bit 10) */ +#define HSTX_FIFO_STAT_WOF_Msk (0x400UL) /*!< WOF (Bitfield-Mask: 0x01) */ +#define HSTX_FIFO_STAT_EMPTY_Pos (9UL) /*!< EMPTY (Bit 9) */ +#define HSTX_FIFO_STAT_EMPTY_Msk (0x200UL) /*!< EMPTY (Bitfield-Mask: 0x01) */ +#define HSTX_FIFO_STAT_FULL_Pos (8UL) /*!< FULL (Bit 8) */ +#define HSTX_FIFO_STAT_FULL_Msk (0x100UL) /*!< FULL (Bitfield-Mask: 0x01) */ +#define HSTX_FIFO_STAT_LEVEL_Pos (0UL) /*!< LEVEL (Bit 0) */ +#define HSTX_FIFO_STAT_LEVEL_Msk (0xffUL) /*!< LEVEL (Bitfield-Mask: 0xff) */ +/* ========================================================= FIFO ========================================================== */ +#define HSTX_FIFO_FIFO_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define HSTX_FIFO_FIFO_FIFO_Msk (0xffffffffUL) /*!< FIFO (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ HSTX_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define HSTX_CTRL_CSR_CLKDIV_Pos (28UL) /*!< CLKDIV (Bit 28) */ +#define HSTX_CTRL_CSR_CLKDIV_Msk (0xf0000000UL) /*!< CLKDIV (Bitfield-Mask: 0x0f) */ +#define HSTX_CTRL_CSR_CLKPHASE_Pos (24UL) /*!< CLKPHASE (Bit 24) */ +#define HSTX_CTRL_CSR_CLKPHASE_Msk (0xf000000UL) /*!< CLKPHASE (Bitfield-Mask: 0x0f) */ +#define HSTX_CTRL_CSR_N_SHIFTS_Pos (16UL) /*!< N_SHIFTS (Bit 16) */ +#define HSTX_CTRL_CSR_N_SHIFTS_Msk (0x1f0000UL) /*!< N_SHIFTS (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_CSR_SHIFT_Pos (8UL) /*!< SHIFT (Bit 8) */ +#define HSTX_CTRL_CSR_SHIFT_Msk (0x1f00UL) /*!< SHIFT (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_CSR_COUPLED_SEL_Pos (5UL) /*!< COUPLED_SEL (Bit 5) */ +#define HSTX_CTRL_CSR_COUPLED_SEL_Msk (0x60UL) /*!< COUPLED_SEL (Bitfield-Mask: 0x03) */ +#define HSTX_CTRL_CSR_COUPLED_MODE_Pos (4UL) /*!< COUPLED_MODE (Bit 4) */ +#define HSTX_CTRL_CSR_COUPLED_MODE_Msk (0x10UL) /*!< COUPLED_MODE (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_CSR_EXPAND_EN_Pos (1UL) /*!< EXPAND_EN (Bit 1) */ +#define HSTX_CTRL_CSR_EXPAND_EN_Msk (0x2UL) /*!< EXPAND_EN (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define HSTX_CTRL_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= BIT0 ========================================================== */ +#define HSTX_CTRL_BIT0_CLK_Pos (17UL) /*!< CLK (Bit 17) */ +#define HSTX_CTRL_BIT0_CLK_Msk (0x20000UL) /*!< CLK (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT0_INV_Pos (16UL) /*!< INV (Bit 16) */ +#define HSTX_CTRL_BIT0_INV_Msk (0x10000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT0_SEL_N_Pos (8UL) /*!< SEL_N (Bit 8) */ +#define HSTX_CTRL_BIT0_SEL_N_Msk (0x1f00UL) /*!< SEL_N (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_BIT0_SEL_P_Pos (0UL) /*!< SEL_P (Bit 0) */ +#define HSTX_CTRL_BIT0_SEL_P_Msk (0x1fUL) /*!< SEL_P (Bitfield-Mask: 0x1f) */ +/* ========================================================= BIT1 ========================================================== */ +#define HSTX_CTRL_BIT1_CLK_Pos (17UL) /*!< CLK (Bit 17) */ +#define HSTX_CTRL_BIT1_CLK_Msk (0x20000UL) /*!< CLK (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT1_INV_Pos (16UL) /*!< INV (Bit 16) */ +#define HSTX_CTRL_BIT1_INV_Msk (0x10000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT1_SEL_N_Pos (8UL) /*!< SEL_N (Bit 8) */ +#define HSTX_CTRL_BIT1_SEL_N_Msk (0x1f00UL) /*!< SEL_N (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_BIT1_SEL_P_Pos (0UL) /*!< SEL_P (Bit 0) */ +#define HSTX_CTRL_BIT1_SEL_P_Msk (0x1fUL) /*!< SEL_P (Bitfield-Mask: 0x1f) */ +/* ========================================================= BIT2 ========================================================== */ +#define HSTX_CTRL_BIT2_CLK_Pos (17UL) /*!< CLK (Bit 17) */ +#define HSTX_CTRL_BIT2_CLK_Msk (0x20000UL) /*!< CLK (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT2_INV_Pos (16UL) /*!< INV (Bit 16) */ +#define HSTX_CTRL_BIT2_INV_Msk (0x10000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT2_SEL_N_Pos (8UL) /*!< SEL_N (Bit 8) */ +#define HSTX_CTRL_BIT2_SEL_N_Msk (0x1f00UL) /*!< SEL_N (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_BIT2_SEL_P_Pos (0UL) /*!< SEL_P (Bit 0) */ +#define HSTX_CTRL_BIT2_SEL_P_Msk (0x1fUL) /*!< SEL_P (Bitfield-Mask: 0x1f) */ +/* ========================================================= BIT3 ========================================================== */ +#define HSTX_CTRL_BIT3_CLK_Pos (17UL) /*!< CLK (Bit 17) */ +#define HSTX_CTRL_BIT3_CLK_Msk (0x20000UL) /*!< CLK (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT3_INV_Pos (16UL) /*!< INV (Bit 16) */ +#define HSTX_CTRL_BIT3_INV_Msk (0x10000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT3_SEL_N_Pos (8UL) /*!< SEL_N (Bit 8) */ +#define HSTX_CTRL_BIT3_SEL_N_Msk (0x1f00UL) /*!< SEL_N (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_BIT3_SEL_P_Pos (0UL) /*!< SEL_P (Bit 0) */ +#define HSTX_CTRL_BIT3_SEL_P_Msk (0x1fUL) /*!< SEL_P (Bitfield-Mask: 0x1f) */ +/* ========================================================= BIT4 ========================================================== */ +#define HSTX_CTRL_BIT4_CLK_Pos (17UL) /*!< CLK (Bit 17) */ +#define HSTX_CTRL_BIT4_CLK_Msk (0x20000UL) /*!< CLK (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT4_INV_Pos (16UL) /*!< INV (Bit 16) */ +#define HSTX_CTRL_BIT4_INV_Msk (0x10000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT4_SEL_N_Pos (8UL) /*!< SEL_N (Bit 8) */ +#define HSTX_CTRL_BIT4_SEL_N_Msk (0x1f00UL) /*!< SEL_N (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_BIT4_SEL_P_Pos (0UL) /*!< SEL_P (Bit 0) */ +#define HSTX_CTRL_BIT4_SEL_P_Msk (0x1fUL) /*!< SEL_P (Bitfield-Mask: 0x1f) */ +/* ========================================================= BIT5 ========================================================== */ +#define HSTX_CTRL_BIT5_CLK_Pos (17UL) /*!< CLK (Bit 17) */ +#define HSTX_CTRL_BIT5_CLK_Msk (0x20000UL) /*!< CLK (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT5_INV_Pos (16UL) /*!< INV (Bit 16) */ +#define HSTX_CTRL_BIT5_INV_Msk (0x10000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT5_SEL_N_Pos (8UL) /*!< SEL_N (Bit 8) */ +#define HSTX_CTRL_BIT5_SEL_N_Msk (0x1f00UL) /*!< SEL_N (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_BIT5_SEL_P_Pos (0UL) /*!< SEL_P (Bit 0) */ +#define HSTX_CTRL_BIT5_SEL_P_Msk (0x1fUL) /*!< SEL_P (Bitfield-Mask: 0x1f) */ +/* ========================================================= BIT6 ========================================================== */ +#define HSTX_CTRL_BIT6_CLK_Pos (17UL) /*!< CLK (Bit 17) */ +#define HSTX_CTRL_BIT6_CLK_Msk (0x20000UL) /*!< CLK (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT6_INV_Pos (16UL) /*!< INV (Bit 16) */ +#define HSTX_CTRL_BIT6_INV_Msk (0x10000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT6_SEL_N_Pos (8UL) /*!< SEL_N (Bit 8) */ +#define HSTX_CTRL_BIT6_SEL_N_Msk (0x1f00UL) /*!< SEL_N (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_BIT6_SEL_P_Pos (0UL) /*!< SEL_P (Bit 0) */ +#define HSTX_CTRL_BIT6_SEL_P_Msk (0x1fUL) /*!< SEL_P (Bitfield-Mask: 0x1f) */ +/* ========================================================= BIT7 ========================================================== */ +#define HSTX_CTRL_BIT7_CLK_Pos (17UL) /*!< CLK (Bit 17) */ +#define HSTX_CTRL_BIT7_CLK_Msk (0x20000UL) /*!< CLK (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT7_INV_Pos (16UL) /*!< INV (Bit 16) */ +#define HSTX_CTRL_BIT7_INV_Msk (0x10000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define HSTX_CTRL_BIT7_SEL_N_Pos (8UL) /*!< SEL_N (Bit 8) */ +#define HSTX_CTRL_BIT7_SEL_N_Msk (0x1f00UL) /*!< SEL_N (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_BIT7_SEL_P_Pos (0UL) /*!< SEL_P (Bit 0) */ +#define HSTX_CTRL_BIT7_SEL_P_Msk (0x1fUL) /*!< SEL_P (Bitfield-Mask: 0x1f) */ +/* ===================================================== EXPAND_SHIFT ====================================================== */ +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_Pos (24UL) /*!< ENC_N_SHIFTS (Bit 24) */ +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_Msk (0x1f000000UL) /*!< ENC_N_SHIFTS (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_Pos (16UL) /*!< ENC_SHIFT (Bit 16) */ +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_Msk (0x1f0000UL) /*!< ENC_SHIFT (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_Pos (8UL) /*!< RAW_N_SHIFTS (Bit 8) */ +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_Msk (0x1f00UL) /*!< RAW_N_SHIFTS (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_Pos (0UL) /*!< RAW_SHIFT (Bit 0) */ +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_Msk (0x1fUL) /*!< RAW_SHIFT (Bitfield-Mask: 0x1f) */ +/* ====================================================== EXPAND_TMDS ====================================================== */ +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_Pos (21UL) /*!< L2_NBITS (Bit 21) */ +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_Msk (0xe00000UL) /*!< L2_NBITS (Bitfield-Mask: 0x07) */ +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_Pos (16UL) /*!< L2_ROT (Bit 16) */ +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_Msk (0x1f0000UL) /*!< L2_ROT (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_Pos (13UL) /*!< L1_NBITS (Bit 13) */ +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_Msk (0xe000UL) /*!< L1_NBITS (Bitfield-Mask: 0x07) */ +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_Pos (8UL) /*!< L1_ROT (Bit 8) */ +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_Msk (0x1f00UL) /*!< L1_ROT (Bitfield-Mask: 0x1f) */ +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_Pos (5UL) /*!< L0_NBITS (Bit 5) */ +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_Msk (0xe0UL) /*!< L0_NBITS (Bitfield-Mask: 0x07) */ +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_Pos (0UL) /*!< L0_ROT (Bit 0) */ +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_Msk (0x1fUL) /*!< L0_ROT (Bitfield-Mask: 0x1f) */ + + +/* =========================================================================================================================== */ +/* ================ EPPB ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= NMI_MASK0 ======================================================= */ +#define EPPB_NMI_MASK0_NMI_MASK0_Pos (0UL) /*!< NMI_MASK0 (Bit 0) */ +#define EPPB_NMI_MASK0_NMI_MASK0_Msk (0xffffffffUL) /*!< NMI_MASK0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= NMI_MASK1 ======================================================= */ +#define EPPB_NMI_MASK1_NMI_MASK1_Pos (0UL) /*!< NMI_MASK1 (Bit 0) */ +#define EPPB_NMI_MASK1_NMI_MASK1_Msk (0xfffffUL) /*!< NMI_MASK1 (Bitfield-Mask: 0xfffff) */ +/* ======================================================= SLEEPCTRL ======================================================= */ +#define EPPB_SLEEPCTRL_WICENACK_Pos (2UL) /*!< WICENACK (Bit 2) */ +#define EPPB_SLEEPCTRL_WICENACK_Msk (0x4UL) /*!< WICENACK (Bitfield-Mask: 0x01) */ +#define EPPB_SLEEPCTRL_WICENREQ_Pos (1UL) /*!< WICENREQ (Bit 1) */ +#define EPPB_SLEEPCTRL_WICENREQ_Msk (0x2UL) /*!< WICENREQ (Bitfield-Mask: 0x01) */ +#define EPPB_SLEEPCTRL_LIGHT_SLEEP_Pos (0UL) /*!< LIGHT_SLEEP (Bit 0) */ +#define EPPB_SLEEPCTRL_LIGHT_SLEEP_Msk (0x1UL) /*!< LIGHT_SLEEP (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ PPB ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ITM_STIM0 ======================================================= */ +#define PPB_ITM_STIM0_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM0_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_STIM1 ======================================================= */ +#define PPB_ITM_STIM1_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM1_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_STIM2 ======================================================= */ +#define PPB_ITM_STIM2_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM2_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_STIM3 ======================================================= */ +#define PPB_ITM_STIM3_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM3_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_STIM4 ======================================================= */ +#define PPB_ITM_STIM4_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM4_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_STIM5 ======================================================= */ +#define PPB_ITM_STIM5_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM5_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_STIM6 ======================================================= */ +#define PPB_ITM_STIM6_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM6_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_STIM7 ======================================================= */ +#define PPB_ITM_STIM7_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM7_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_STIM8 ======================================================= */ +#define PPB_ITM_STIM8_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM8_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_STIM9 ======================================================= */ +#define PPB_ITM_STIM9_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM9_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM10 ======================================================= */ +#define PPB_ITM_STIM10_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM10_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM11 ======================================================= */ +#define PPB_ITM_STIM11_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM11_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM12 ======================================================= */ +#define PPB_ITM_STIM12_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM12_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM13 ======================================================= */ +#define PPB_ITM_STIM13_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM13_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM14 ======================================================= */ +#define PPB_ITM_STIM14_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM14_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM15 ======================================================= */ +#define PPB_ITM_STIM15_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM15_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM16 ======================================================= */ +#define PPB_ITM_STIM16_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM16_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM17 ======================================================= */ +#define PPB_ITM_STIM17_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM17_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM18 ======================================================= */ +#define PPB_ITM_STIM18_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM18_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM19 ======================================================= */ +#define PPB_ITM_STIM19_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM19_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM20 ======================================================= */ +#define PPB_ITM_STIM20_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM20_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM21 ======================================================= */ +#define PPB_ITM_STIM21_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM21_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM22 ======================================================= */ +#define PPB_ITM_STIM22_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM22_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM23 ======================================================= */ +#define PPB_ITM_STIM23_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM23_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM24 ======================================================= */ +#define PPB_ITM_STIM24_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM24_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM25 ======================================================= */ +#define PPB_ITM_STIM25_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM25_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM26 ======================================================= */ +#define PPB_ITM_STIM26_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM26_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM27 ======================================================= */ +#define PPB_ITM_STIM27_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM27_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM28 ======================================================= */ +#define PPB_ITM_STIM28_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM28_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM29 ======================================================= */ +#define PPB_ITM_STIM29_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM29_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM30 ======================================================= */ +#define PPB_ITM_STIM30_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM30_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ITM_STIM31 ======================================================= */ +#define PPB_ITM_STIM31_STIMULUS_Pos (0UL) /*!< STIMULUS (Bit 0) */ +#define PPB_ITM_STIM31_STIMULUS_Msk (0xffffffffUL) /*!< STIMULUS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_TER0 ======================================================== */ +#define PPB_ITM_TER0_STIMENA_Pos (0UL) /*!< STIMENA (Bit 0) */ +#define PPB_ITM_TER0_STIMENA_Msk (0xffffffffUL) /*!< STIMENA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ITM_TPR ======================================================== */ +#define PPB_ITM_TPR_PRIVMASK_Pos (0UL) /*!< PRIVMASK (Bit 0) */ +#define PPB_ITM_TPR_PRIVMASK_Msk (0xfUL) /*!< PRIVMASK (Bitfield-Mask: 0x0f) */ +/* ======================================================== ITM_TCR ======================================================== */ +#define PPB_ITM_TCR_BUSY_Pos (23UL) /*!< BUSY (Bit 23) */ +#define PPB_ITM_TCR_BUSY_Msk (0x800000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define PPB_ITM_TCR_TRACEBUSID_Pos (16UL) /*!< TRACEBUSID (Bit 16) */ +#define PPB_ITM_TCR_TRACEBUSID_Msk (0x7f0000UL) /*!< TRACEBUSID (Bitfield-Mask: 0x7f) */ +#define PPB_ITM_TCR_GTSFREQ_Pos (10UL) /*!< GTSFREQ (Bit 10) */ +#define PPB_ITM_TCR_GTSFREQ_Msk (0xc00UL) /*!< GTSFREQ (Bitfield-Mask: 0x03) */ +#define PPB_ITM_TCR_TSPRESCALE_Pos (8UL) /*!< TSPRESCALE (Bit 8) */ +#define PPB_ITM_TCR_TSPRESCALE_Msk (0x300UL) /*!< TSPRESCALE (Bitfield-Mask: 0x03) */ +#define PPB_ITM_TCR_STALLENA_Pos (5UL) /*!< STALLENA (Bit 5) */ +#define PPB_ITM_TCR_STALLENA_Msk (0x20UL) /*!< STALLENA (Bitfield-Mask: 0x01) */ +#define PPB_ITM_TCR_SWOENA_Pos (4UL) /*!< SWOENA (Bit 4) */ +#define PPB_ITM_TCR_SWOENA_Msk (0x10UL) /*!< SWOENA (Bitfield-Mask: 0x01) */ +#define PPB_ITM_TCR_TXENA_Pos (3UL) /*!< TXENA (Bit 3) */ +#define PPB_ITM_TCR_TXENA_Msk (0x8UL) /*!< TXENA (Bitfield-Mask: 0x01) */ +#define PPB_ITM_TCR_SYNCENA_Pos (2UL) /*!< SYNCENA (Bit 2) */ +#define PPB_ITM_TCR_SYNCENA_Msk (0x4UL) /*!< SYNCENA (Bitfield-Mask: 0x01) */ +#define PPB_ITM_TCR_TSENA_Pos (1UL) /*!< TSENA (Bit 1) */ +#define PPB_ITM_TCR_TSENA_Msk (0x2UL) /*!< TSENA (Bitfield-Mask: 0x01) */ +#define PPB_ITM_TCR_ITMENA_Pos (0UL) /*!< ITMENA (Bit 0) */ +#define PPB_ITM_TCR_ITMENA_Msk (0x1UL) /*!< ITMENA (Bitfield-Mask: 0x01) */ +/* ====================================================== INT_ATREADY ====================================================== */ +#define PPB_INT_ATREADY_AFVALID_Pos (1UL) /*!< AFVALID (Bit 1) */ +#define PPB_INT_ATREADY_AFVALID_Msk (0x2UL) /*!< AFVALID (Bitfield-Mask: 0x01) */ +#define PPB_INT_ATREADY_ATREADY_Pos (0UL) /*!< ATREADY (Bit 0) */ +#define PPB_INT_ATREADY_ATREADY_Msk (0x1UL) /*!< ATREADY (Bitfield-Mask: 0x01) */ +/* ====================================================== INT_ATVALID ====================================================== */ +#define PPB_INT_ATVALID_AFREADY_Pos (1UL) /*!< AFREADY (Bit 1) */ +#define PPB_INT_ATVALID_AFREADY_Msk (0x2UL) /*!< AFREADY (Bitfield-Mask: 0x01) */ +#define PPB_INT_ATVALID_ATREADY_Pos (0UL) /*!< ATREADY (Bit 0) */ +#define PPB_INT_ATVALID_ATREADY_Msk (0x1UL) /*!< ATREADY (Bitfield-Mask: 0x01) */ +/* ====================================================== ITM_ITCTRL ======================================================= */ +#define PPB_ITM_ITCTRL_IME_Pos (0UL) /*!< IME (Bit 0) */ +#define PPB_ITM_ITCTRL_IME_Msk (0x1UL) /*!< IME (Bitfield-Mask: 0x01) */ +/* ====================================================== ITM_DEVARCH ====================================================== */ +#define PPB_ITM_DEVARCH_ARCHITECT_Pos (21UL) /*!< ARCHITECT (Bit 21) */ +#define PPB_ITM_DEVARCH_ARCHITECT_Msk (0xffe00000UL) /*!< ARCHITECT (Bitfield-Mask: 0x7ff) */ +#define PPB_ITM_DEVARCH_PRESENT_Pos (20UL) /*!< PRESENT (Bit 20) */ +#define PPB_ITM_DEVARCH_PRESENT_Msk (0x100000UL) /*!< PRESENT (Bitfield-Mask: 0x01) */ +#define PPB_ITM_DEVARCH_REVISION_Pos (16UL) /*!< REVISION (Bit 16) */ +#define PPB_ITM_DEVARCH_REVISION_Msk (0xf0000UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_ITM_DEVARCH_ARCHVER_Pos (12UL) /*!< ARCHVER (Bit 12) */ +#define PPB_ITM_DEVARCH_ARCHVER_Msk (0xf000UL) /*!< ARCHVER (Bitfield-Mask: 0x0f) */ +#define PPB_ITM_DEVARCH_ARCHPART_Pos (0UL) /*!< ARCHPART (Bit 0) */ +#define PPB_ITM_DEVARCH_ARCHPART_Msk (0xfffUL) /*!< ARCHPART (Bitfield-Mask: 0xfff) */ +/* ====================================================== ITM_DEVTYPE ====================================================== */ +#define PPB_ITM_DEVTYPE_SUB_Pos (4UL) /*!< SUB (Bit 4) */ +#define PPB_ITM_DEVTYPE_SUB_Msk (0xf0UL) /*!< SUB (Bitfield-Mask: 0x0f) */ +#define PPB_ITM_DEVTYPE_MAJOR_Pos (0UL) /*!< MAJOR (Bit 0) */ +#define PPB_ITM_DEVTYPE_MAJOR_Msk (0xfUL) /*!< MAJOR (Bitfield-Mask: 0x0f) */ +/* ======================================================= ITM_PIDR4 ======================================================= */ +#define PPB_ITM_PIDR4_SIZE_Pos (4UL) /*!< SIZE (Bit 4) */ +#define PPB_ITM_PIDR4_SIZE_Msk (0xf0UL) /*!< SIZE (Bitfield-Mask: 0x0f) */ +#define PPB_ITM_PIDR4_DES_2_Pos (0UL) /*!< DES_2 (Bit 0) */ +#define PPB_ITM_PIDR4_DES_2_Msk (0xfUL) /*!< DES_2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ITM_PIDR5 ======================================================= */ +#define PPB_ITM_PIDR5_ITM_PIDR5_Pos (0UL) /*!< ITM_PIDR5 (Bit 0) */ +#define PPB_ITM_PIDR5_ITM_PIDR5_Msk (0xffffffffUL) /*!< ITM_PIDR5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_PIDR6 ======================================================= */ +#define PPB_ITM_PIDR6_ITM_PIDR6_Pos (0UL) /*!< ITM_PIDR6 (Bit 0) */ +#define PPB_ITM_PIDR6_ITM_PIDR6_Msk (0xffffffffUL) /*!< ITM_PIDR6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_PIDR7 ======================================================= */ +#define PPB_ITM_PIDR7_ITM_PIDR7_Pos (0UL) /*!< ITM_PIDR7 (Bit 0) */ +#define PPB_ITM_PIDR7_ITM_PIDR7_Msk (0xffffffffUL) /*!< ITM_PIDR7 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ITM_PIDR0 ======================================================= */ +#define PPB_ITM_PIDR0_PART_0_Pos (0UL) /*!< PART_0 (Bit 0) */ +#define PPB_ITM_PIDR0_PART_0_Msk (0xffUL) /*!< PART_0 (Bitfield-Mask: 0xff) */ +/* ======================================================= ITM_PIDR1 ======================================================= */ +#define PPB_ITM_PIDR1_DES_0_Pos (4UL) /*!< DES_0 (Bit 4) */ +#define PPB_ITM_PIDR1_DES_0_Msk (0xf0UL) /*!< DES_0 (Bitfield-Mask: 0x0f) */ +#define PPB_ITM_PIDR1_PART_1_Pos (0UL) /*!< PART_1 (Bit 0) */ +#define PPB_ITM_PIDR1_PART_1_Msk (0xfUL) /*!< PART_1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ITM_PIDR2 ======================================================= */ +#define PPB_ITM_PIDR2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */ +#define PPB_ITM_PIDR2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_ITM_PIDR2_JEDEC_Pos (3UL) /*!< JEDEC (Bit 3) */ +#define PPB_ITM_PIDR2_JEDEC_Msk (0x8UL) /*!< JEDEC (Bitfield-Mask: 0x01) */ +#define PPB_ITM_PIDR2_DES_1_Pos (0UL) /*!< DES_1 (Bit 0) */ +#define PPB_ITM_PIDR2_DES_1_Msk (0x7UL) /*!< DES_1 (Bitfield-Mask: 0x07) */ +/* ======================================================= ITM_PIDR3 ======================================================= */ +#define PPB_ITM_PIDR3_REVAND_Pos (4UL) /*!< REVAND (Bit 4) */ +#define PPB_ITM_PIDR3_REVAND_Msk (0xf0UL) /*!< REVAND (Bitfield-Mask: 0x0f) */ +#define PPB_ITM_PIDR3_CMOD_Pos (0UL) /*!< CMOD (Bit 0) */ +#define PPB_ITM_PIDR3_CMOD_Msk (0xfUL) /*!< CMOD (Bitfield-Mask: 0x0f) */ +/* ======================================================= ITM_CIDR0 ======================================================= */ +#define PPB_ITM_CIDR0_PRMBL_0_Pos (0UL) /*!< PRMBL_0 (Bit 0) */ +#define PPB_ITM_CIDR0_PRMBL_0_Msk (0xffUL) /*!< PRMBL_0 (Bitfield-Mask: 0xff) */ +/* ======================================================= ITM_CIDR1 ======================================================= */ +#define PPB_ITM_CIDR1_CLASS_Pos (4UL) /*!< CLASS (Bit 4) */ +#define PPB_ITM_CIDR1_CLASS_Msk (0xf0UL) /*!< CLASS (Bitfield-Mask: 0x0f) */ +#define PPB_ITM_CIDR1_PRMBL_1_Pos (0UL) /*!< PRMBL_1 (Bit 0) */ +#define PPB_ITM_CIDR1_PRMBL_1_Msk (0xfUL) /*!< PRMBL_1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ITM_CIDR2 ======================================================= */ +#define PPB_ITM_CIDR2_PRMBL_2_Pos (0UL) /*!< PRMBL_2 (Bit 0) */ +#define PPB_ITM_CIDR2_PRMBL_2_Msk (0xffUL) /*!< PRMBL_2 (Bitfield-Mask: 0xff) */ +/* ======================================================= ITM_CIDR3 ======================================================= */ +#define PPB_ITM_CIDR3_PRMBL_3_Pos (0UL) /*!< PRMBL_3 (Bit 0) */ +#define PPB_ITM_CIDR3_PRMBL_3_Msk (0xffUL) /*!< PRMBL_3 (Bitfield-Mask: 0xff) */ +/* ======================================================= DWT_CTRL ======================================================== */ +#define PPB_DWT_CTRL_NUMCOMP_Pos (28UL) /*!< NUMCOMP (Bit 28) */ +#define PPB_DWT_CTRL_NUMCOMP_Msk (0xf0000000UL) /*!< NUMCOMP (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_CTRL_NOTRCPKT_Pos (27UL) /*!< NOTRCPKT (Bit 27) */ +#define PPB_DWT_CTRL_NOTRCPKT_Msk (0x8000000UL) /*!< NOTRCPKT (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_NOEXTTRIG_Pos (26UL) /*!< NOEXTTRIG (Bit 26) */ +#define PPB_DWT_CTRL_NOEXTTRIG_Msk (0x4000000UL) /*!< NOEXTTRIG (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_NOCYCCNT_Pos (25UL) /*!< NOCYCCNT (Bit 25) */ +#define PPB_DWT_CTRL_NOCYCCNT_Msk (0x2000000UL) /*!< NOCYCCNT (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_NOPRFCNT_Pos (24UL) /*!< NOPRFCNT (Bit 24) */ +#define PPB_DWT_CTRL_NOPRFCNT_Msk (0x1000000UL) /*!< NOPRFCNT (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_CYCDISS_Pos (23UL) /*!< CYCDISS (Bit 23) */ +#define PPB_DWT_CTRL_CYCDISS_Msk (0x800000UL) /*!< CYCDISS (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_CYCEVTENA_Pos (22UL) /*!< CYCEVTENA (Bit 22) */ +#define PPB_DWT_CTRL_CYCEVTENA_Msk (0x400000UL) /*!< CYCEVTENA (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_FOLDEVTENA_Pos (21UL) /*!< FOLDEVTENA (Bit 21) */ +#define PPB_DWT_CTRL_FOLDEVTENA_Msk (0x200000UL) /*!< FOLDEVTENA (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_LSUEVTENA_Pos (20UL) /*!< LSUEVTENA (Bit 20) */ +#define PPB_DWT_CTRL_LSUEVTENA_Msk (0x100000UL) /*!< LSUEVTENA (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_SLEEPEVTENA_Pos (19UL) /*!< SLEEPEVTENA (Bit 19) */ +#define PPB_DWT_CTRL_SLEEPEVTENA_Msk (0x80000UL) /*!< SLEEPEVTENA (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_EXCEVTENA_Pos (18UL) /*!< EXCEVTENA (Bit 18) */ +#define PPB_DWT_CTRL_EXCEVTENA_Msk (0x40000UL) /*!< EXCEVTENA (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_CPIEVTENA_Pos (17UL) /*!< CPIEVTENA (Bit 17) */ +#define PPB_DWT_CTRL_CPIEVTENA_Msk (0x20000UL) /*!< CPIEVTENA (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_EXTTRCENA_Pos (16UL) /*!< EXTTRCENA (Bit 16) */ +#define PPB_DWT_CTRL_EXTTRCENA_Msk (0x10000UL) /*!< EXTTRCENA (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_PCSAMPLENA_Pos (12UL) /*!< PCSAMPLENA (Bit 12) */ +#define PPB_DWT_CTRL_PCSAMPLENA_Msk (0x1000UL) /*!< PCSAMPLENA (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_SYNCTAP_Pos (10UL) /*!< SYNCTAP (Bit 10) */ +#define PPB_DWT_CTRL_SYNCTAP_Msk (0xc00UL) /*!< SYNCTAP (Bitfield-Mask: 0x03) */ +#define PPB_DWT_CTRL_CYCTAP_Pos (9UL) /*!< CYCTAP (Bit 9) */ +#define PPB_DWT_CTRL_CYCTAP_Msk (0x200UL) /*!< CYCTAP (Bitfield-Mask: 0x01) */ +#define PPB_DWT_CTRL_POSTINIT_Pos (5UL) /*!< POSTINIT (Bit 5) */ +#define PPB_DWT_CTRL_POSTINIT_Msk (0x1e0UL) /*!< POSTINIT (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_CTRL_POSTPRESET_Pos (1UL) /*!< POSTPRESET (Bit 1) */ +#define PPB_DWT_CTRL_POSTPRESET_Msk (0x1eUL) /*!< POSTPRESET (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_CTRL_CYCCNTENA_Pos (0UL) /*!< CYCCNTENA (Bit 0) */ +#define PPB_DWT_CTRL_CYCCNTENA_Msk (0x1UL) /*!< CYCCNTENA (Bitfield-Mask: 0x01) */ +/* ====================================================== DWT_CYCCNT ======================================================= */ +#define PPB_DWT_CYCCNT_CYCCNT_Pos (0UL) /*!< CYCCNT (Bit 0) */ +#define PPB_DWT_CYCCNT_CYCCNT_Msk (0xffffffffUL) /*!< CYCCNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DWT_EXCCNT ======================================================= */ +#define PPB_DWT_EXCCNT_EXCCNT_Pos (0UL) /*!< EXCCNT (Bit 0) */ +#define PPB_DWT_EXCCNT_EXCCNT_Msk (0xffUL) /*!< EXCCNT (Bitfield-Mask: 0xff) */ +/* ====================================================== DWT_LSUCNT ======================================================= */ +#define PPB_DWT_LSUCNT_LSUCNT_Pos (0UL) /*!< LSUCNT (Bit 0) */ +#define PPB_DWT_LSUCNT_LSUCNT_Msk (0xffUL) /*!< LSUCNT (Bitfield-Mask: 0xff) */ +/* ====================================================== DWT_FOLDCNT ====================================================== */ +#define PPB_DWT_FOLDCNT_FOLDCNT_Pos (0UL) /*!< FOLDCNT (Bit 0) */ +#define PPB_DWT_FOLDCNT_FOLDCNT_Msk (0xffUL) /*!< FOLDCNT (Bitfield-Mask: 0xff) */ +/* ======================================================= DWT_COMP0 ======================================================= */ +#define PPB_DWT_COMP0_DWT_COMP0_Pos (0UL) /*!< DWT_COMP0 (Bit 0) */ +#define PPB_DWT_COMP0_DWT_COMP0_Msk (0xffffffffUL) /*!< DWT_COMP0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DWT_FUNCTION0 ===================================================== */ +#define PPB_DWT_FUNCTION0_ID_Pos (27UL) /*!< ID (Bit 27) */ +#define PPB_DWT_FUNCTION0_ID_Msk (0xf8000000UL) /*!< ID (Bitfield-Mask: 0x1f) */ +#define PPB_DWT_FUNCTION0_MATCHED_Pos (24UL) /*!< MATCHED (Bit 24) */ +#define PPB_DWT_FUNCTION0_MATCHED_Msk (0x1000000UL) /*!< MATCHED (Bitfield-Mask: 0x01) */ +#define PPB_DWT_FUNCTION0_DATAVSIZE_Pos (10UL) /*!< DATAVSIZE (Bit 10) */ +#define PPB_DWT_FUNCTION0_DATAVSIZE_Msk (0xc00UL) /*!< DATAVSIZE (Bitfield-Mask: 0x03) */ +#define PPB_DWT_FUNCTION0_ACTION_Pos (4UL) /*!< ACTION (Bit 4) */ +#define PPB_DWT_FUNCTION0_ACTION_Msk (0x30UL) /*!< ACTION (Bitfield-Mask: 0x03) */ +#define PPB_DWT_FUNCTION0_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PPB_DWT_FUNCTION0_MATCH_Msk (0xfUL) /*!< MATCH (Bitfield-Mask: 0x0f) */ +/* ======================================================= DWT_COMP1 ======================================================= */ +#define PPB_DWT_COMP1_DWT_COMP1_Pos (0UL) /*!< DWT_COMP1 (Bit 0) */ +#define PPB_DWT_COMP1_DWT_COMP1_Msk (0xffffffffUL) /*!< DWT_COMP1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DWT_FUNCTION1 ===================================================== */ +#define PPB_DWT_FUNCTION1_ID_Pos (27UL) /*!< ID (Bit 27) */ +#define PPB_DWT_FUNCTION1_ID_Msk (0xf8000000UL) /*!< ID (Bitfield-Mask: 0x1f) */ +#define PPB_DWT_FUNCTION1_MATCHED_Pos (24UL) /*!< MATCHED (Bit 24) */ +#define PPB_DWT_FUNCTION1_MATCHED_Msk (0x1000000UL) /*!< MATCHED (Bitfield-Mask: 0x01) */ +#define PPB_DWT_FUNCTION1_DATAVSIZE_Pos (10UL) /*!< DATAVSIZE (Bit 10) */ +#define PPB_DWT_FUNCTION1_DATAVSIZE_Msk (0xc00UL) /*!< DATAVSIZE (Bitfield-Mask: 0x03) */ +#define PPB_DWT_FUNCTION1_ACTION_Pos (4UL) /*!< ACTION (Bit 4) */ +#define PPB_DWT_FUNCTION1_ACTION_Msk (0x30UL) /*!< ACTION (Bitfield-Mask: 0x03) */ +#define PPB_DWT_FUNCTION1_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PPB_DWT_FUNCTION1_MATCH_Msk (0xfUL) /*!< MATCH (Bitfield-Mask: 0x0f) */ +/* ======================================================= DWT_COMP2 ======================================================= */ +#define PPB_DWT_COMP2_DWT_COMP2_Pos (0UL) /*!< DWT_COMP2 (Bit 0) */ +#define PPB_DWT_COMP2_DWT_COMP2_Msk (0xffffffffUL) /*!< DWT_COMP2 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DWT_FUNCTION2 ===================================================== */ +#define PPB_DWT_FUNCTION2_ID_Pos (27UL) /*!< ID (Bit 27) */ +#define PPB_DWT_FUNCTION2_ID_Msk (0xf8000000UL) /*!< ID (Bitfield-Mask: 0x1f) */ +#define PPB_DWT_FUNCTION2_MATCHED_Pos (24UL) /*!< MATCHED (Bit 24) */ +#define PPB_DWT_FUNCTION2_MATCHED_Msk (0x1000000UL) /*!< MATCHED (Bitfield-Mask: 0x01) */ +#define PPB_DWT_FUNCTION2_DATAVSIZE_Pos (10UL) /*!< DATAVSIZE (Bit 10) */ +#define PPB_DWT_FUNCTION2_DATAVSIZE_Msk (0xc00UL) /*!< DATAVSIZE (Bitfield-Mask: 0x03) */ +#define PPB_DWT_FUNCTION2_ACTION_Pos (4UL) /*!< ACTION (Bit 4) */ +#define PPB_DWT_FUNCTION2_ACTION_Msk (0x30UL) /*!< ACTION (Bitfield-Mask: 0x03) */ +#define PPB_DWT_FUNCTION2_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PPB_DWT_FUNCTION2_MATCH_Msk (0xfUL) /*!< MATCH (Bitfield-Mask: 0x0f) */ +/* ======================================================= DWT_COMP3 ======================================================= */ +#define PPB_DWT_COMP3_DWT_COMP3_Pos (0UL) /*!< DWT_COMP3 (Bit 0) */ +#define PPB_DWT_COMP3_DWT_COMP3_Msk (0xffffffffUL) /*!< DWT_COMP3 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DWT_FUNCTION3 ===================================================== */ +#define PPB_DWT_FUNCTION3_ID_Pos (27UL) /*!< ID (Bit 27) */ +#define PPB_DWT_FUNCTION3_ID_Msk (0xf8000000UL) /*!< ID (Bitfield-Mask: 0x1f) */ +#define PPB_DWT_FUNCTION3_MATCHED_Pos (24UL) /*!< MATCHED (Bit 24) */ +#define PPB_DWT_FUNCTION3_MATCHED_Msk (0x1000000UL) /*!< MATCHED (Bitfield-Mask: 0x01) */ +#define PPB_DWT_FUNCTION3_DATAVSIZE_Pos (10UL) /*!< DATAVSIZE (Bit 10) */ +#define PPB_DWT_FUNCTION3_DATAVSIZE_Msk (0xc00UL) /*!< DATAVSIZE (Bitfield-Mask: 0x03) */ +#define PPB_DWT_FUNCTION3_ACTION_Pos (4UL) /*!< ACTION (Bit 4) */ +#define PPB_DWT_FUNCTION3_ACTION_Msk (0x30UL) /*!< ACTION (Bitfield-Mask: 0x03) */ +#define PPB_DWT_FUNCTION3_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PPB_DWT_FUNCTION3_MATCH_Msk (0xfUL) /*!< MATCH (Bitfield-Mask: 0x0f) */ +/* ====================================================== DWT_DEVARCH ====================================================== */ +#define PPB_DWT_DEVARCH_ARCHITECT_Pos (21UL) /*!< ARCHITECT (Bit 21) */ +#define PPB_DWT_DEVARCH_ARCHITECT_Msk (0xffe00000UL) /*!< ARCHITECT (Bitfield-Mask: 0x7ff) */ +#define PPB_DWT_DEVARCH_PRESENT_Pos (20UL) /*!< PRESENT (Bit 20) */ +#define PPB_DWT_DEVARCH_PRESENT_Msk (0x100000UL) /*!< PRESENT (Bitfield-Mask: 0x01) */ +#define PPB_DWT_DEVARCH_REVISION_Pos (16UL) /*!< REVISION (Bit 16) */ +#define PPB_DWT_DEVARCH_REVISION_Msk (0xf0000UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_DEVARCH_ARCHVER_Pos (12UL) /*!< ARCHVER (Bit 12) */ +#define PPB_DWT_DEVARCH_ARCHVER_Msk (0xf000UL) /*!< ARCHVER (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_DEVARCH_ARCHPART_Pos (0UL) /*!< ARCHPART (Bit 0) */ +#define PPB_DWT_DEVARCH_ARCHPART_Msk (0xfffUL) /*!< ARCHPART (Bitfield-Mask: 0xfff) */ +/* ====================================================== DWT_DEVTYPE ====================================================== */ +#define PPB_DWT_DEVTYPE_SUB_Pos (4UL) /*!< SUB (Bit 4) */ +#define PPB_DWT_DEVTYPE_SUB_Msk (0xf0UL) /*!< SUB (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_DEVTYPE_MAJOR_Pos (0UL) /*!< MAJOR (Bit 0) */ +#define PPB_DWT_DEVTYPE_MAJOR_Msk (0xfUL) /*!< MAJOR (Bitfield-Mask: 0x0f) */ +/* ======================================================= DWT_PIDR4 ======================================================= */ +#define PPB_DWT_PIDR4_SIZE_Pos (4UL) /*!< SIZE (Bit 4) */ +#define PPB_DWT_PIDR4_SIZE_Msk (0xf0UL) /*!< SIZE (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_PIDR4_DES_2_Pos (0UL) /*!< DES_2 (Bit 0) */ +#define PPB_DWT_PIDR4_DES_2_Msk (0xfUL) /*!< DES_2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= DWT_PIDR5 ======================================================= */ +#define PPB_DWT_PIDR5_DWT_PIDR5_Pos (0UL) /*!< DWT_PIDR5 (Bit 0) */ +#define PPB_DWT_PIDR5_DWT_PIDR5_Msk (0xffffffffUL) /*!< DWT_PIDR5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DWT_PIDR6 ======================================================= */ +#define PPB_DWT_PIDR6_DWT_PIDR6_Pos (0UL) /*!< DWT_PIDR6 (Bit 0) */ +#define PPB_DWT_PIDR6_DWT_PIDR6_Msk (0xffffffffUL) /*!< DWT_PIDR6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DWT_PIDR7 ======================================================= */ +#define PPB_DWT_PIDR7_DWT_PIDR7_Pos (0UL) /*!< DWT_PIDR7 (Bit 0) */ +#define PPB_DWT_PIDR7_DWT_PIDR7_Msk (0xffffffffUL) /*!< DWT_PIDR7 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DWT_PIDR0 ======================================================= */ +#define PPB_DWT_PIDR0_PART_0_Pos (0UL) /*!< PART_0 (Bit 0) */ +#define PPB_DWT_PIDR0_PART_0_Msk (0xffUL) /*!< PART_0 (Bitfield-Mask: 0xff) */ +/* ======================================================= DWT_PIDR1 ======================================================= */ +#define PPB_DWT_PIDR1_DES_0_Pos (4UL) /*!< DES_0 (Bit 4) */ +#define PPB_DWT_PIDR1_DES_0_Msk (0xf0UL) /*!< DES_0 (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_PIDR1_PART_1_Pos (0UL) /*!< PART_1 (Bit 0) */ +#define PPB_DWT_PIDR1_PART_1_Msk (0xfUL) /*!< PART_1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= DWT_PIDR2 ======================================================= */ +#define PPB_DWT_PIDR2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */ +#define PPB_DWT_PIDR2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_PIDR2_JEDEC_Pos (3UL) /*!< JEDEC (Bit 3) */ +#define PPB_DWT_PIDR2_JEDEC_Msk (0x8UL) /*!< JEDEC (Bitfield-Mask: 0x01) */ +#define PPB_DWT_PIDR2_DES_1_Pos (0UL) /*!< DES_1 (Bit 0) */ +#define PPB_DWT_PIDR2_DES_1_Msk (0x7UL) /*!< DES_1 (Bitfield-Mask: 0x07) */ +/* ======================================================= DWT_PIDR3 ======================================================= */ +#define PPB_DWT_PIDR3_REVAND_Pos (4UL) /*!< REVAND (Bit 4) */ +#define PPB_DWT_PIDR3_REVAND_Msk (0xf0UL) /*!< REVAND (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_PIDR3_CMOD_Pos (0UL) /*!< CMOD (Bit 0) */ +#define PPB_DWT_PIDR3_CMOD_Msk (0xfUL) /*!< CMOD (Bitfield-Mask: 0x0f) */ +/* ======================================================= DWT_CIDR0 ======================================================= */ +#define PPB_DWT_CIDR0_PRMBL_0_Pos (0UL) /*!< PRMBL_0 (Bit 0) */ +#define PPB_DWT_CIDR0_PRMBL_0_Msk (0xffUL) /*!< PRMBL_0 (Bitfield-Mask: 0xff) */ +/* ======================================================= DWT_CIDR1 ======================================================= */ +#define PPB_DWT_CIDR1_CLASS_Pos (4UL) /*!< CLASS (Bit 4) */ +#define PPB_DWT_CIDR1_CLASS_Msk (0xf0UL) /*!< CLASS (Bitfield-Mask: 0x0f) */ +#define PPB_DWT_CIDR1_PRMBL_1_Pos (0UL) /*!< PRMBL_1 (Bit 0) */ +#define PPB_DWT_CIDR1_PRMBL_1_Msk (0xfUL) /*!< PRMBL_1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= DWT_CIDR2 ======================================================= */ +#define PPB_DWT_CIDR2_PRMBL_2_Pos (0UL) /*!< PRMBL_2 (Bit 0) */ +#define PPB_DWT_CIDR2_PRMBL_2_Msk (0xffUL) /*!< PRMBL_2 (Bitfield-Mask: 0xff) */ +/* ======================================================= DWT_CIDR3 ======================================================= */ +#define PPB_DWT_CIDR3_PRMBL_3_Pos (0UL) /*!< PRMBL_3 (Bit 0) */ +#define PPB_DWT_CIDR3_PRMBL_3_Msk (0xffUL) /*!< PRMBL_3 (Bitfield-Mask: 0xff) */ +/* ======================================================== FP_CTRL ======================================================== */ +#define PPB_FP_CTRL_REV_Pos (28UL) /*!< REV (Bit 28) */ +#define PPB_FP_CTRL_REV_Msk (0xf0000000UL) /*!< REV (Bitfield-Mask: 0x0f) */ +#define PPB_FP_CTRL_NUM_CODE_14_12__Pos (12UL) /*!< NUM_CODE_14_12_ (Bit 12) */ +#define PPB_FP_CTRL_NUM_CODE_14_12__Msk (0x7000UL) /*!< NUM_CODE_14_12_ (Bitfield-Mask: 0x07) */ +#define PPB_FP_CTRL_NUM_LIT_Pos (8UL) /*!< NUM_LIT (Bit 8) */ +#define PPB_FP_CTRL_NUM_LIT_Msk (0xf00UL) /*!< NUM_LIT (Bitfield-Mask: 0x0f) */ +#define PPB_FP_CTRL_NUM_CODE_7_4__Pos (4UL) /*!< NUM_CODE_7_4_ (Bit 4) */ +#define PPB_FP_CTRL_NUM_CODE_7_4__Msk (0xf0UL) /*!< NUM_CODE_7_4_ (Bitfield-Mask: 0x0f) */ +#define PPB_FP_CTRL_KEY_Pos (1UL) /*!< KEY (Bit 1) */ +#define PPB_FP_CTRL_KEY_Msk (0x2UL) /*!< KEY (Bitfield-Mask: 0x01) */ +#define PPB_FP_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define PPB_FP_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= FP_REMAP ======================================================== */ +#define PPB_FP_REMAP_RMPSPT_Pos (29UL) /*!< RMPSPT (Bit 29) */ +#define PPB_FP_REMAP_RMPSPT_Msk (0x20000000UL) /*!< RMPSPT (Bitfield-Mask: 0x01) */ +#define PPB_FP_REMAP_REMAP_Pos (5UL) /*!< REMAP (Bit 5) */ +#define PPB_FP_REMAP_REMAP_Msk (0x1fffffe0UL) /*!< REMAP (Bitfield-Mask: 0xffffff) */ +/* ======================================================= FP_COMP0 ======================================================== */ +#define PPB_FP_COMP0_BE_Pos (0UL) /*!< BE (Bit 0) */ +#define PPB_FP_COMP0_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================= FP_COMP1 ======================================================== */ +#define PPB_FP_COMP1_BE_Pos (0UL) /*!< BE (Bit 0) */ +#define PPB_FP_COMP1_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================= FP_COMP2 ======================================================== */ +#define PPB_FP_COMP2_BE_Pos (0UL) /*!< BE (Bit 0) */ +#define PPB_FP_COMP2_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================= FP_COMP3 ======================================================== */ +#define PPB_FP_COMP3_BE_Pos (0UL) /*!< BE (Bit 0) */ +#define PPB_FP_COMP3_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================= FP_COMP4 ======================================================== */ +#define PPB_FP_COMP4_BE_Pos (0UL) /*!< BE (Bit 0) */ +#define PPB_FP_COMP4_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================= FP_COMP5 ======================================================== */ +#define PPB_FP_COMP5_BE_Pos (0UL) /*!< BE (Bit 0) */ +#define PPB_FP_COMP5_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================= FP_COMP6 ======================================================== */ +#define PPB_FP_COMP6_BE_Pos (0UL) /*!< BE (Bit 0) */ +#define PPB_FP_COMP6_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================= FP_COMP7 ======================================================== */ +#define PPB_FP_COMP7_BE_Pos (0UL) /*!< BE (Bit 0) */ +#define PPB_FP_COMP7_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ====================================================== FP_DEVARCH ======================================================= */ +#define PPB_FP_DEVARCH_ARCHITECT_Pos (21UL) /*!< ARCHITECT (Bit 21) */ +#define PPB_FP_DEVARCH_ARCHITECT_Msk (0xffe00000UL) /*!< ARCHITECT (Bitfield-Mask: 0x7ff) */ +#define PPB_FP_DEVARCH_PRESENT_Pos (20UL) /*!< PRESENT (Bit 20) */ +#define PPB_FP_DEVARCH_PRESENT_Msk (0x100000UL) /*!< PRESENT (Bitfield-Mask: 0x01) */ +#define PPB_FP_DEVARCH_REVISION_Pos (16UL) /*!< REVISION (Bit 16) */ +#define PPB_FP_DEVARCH_REVISION_Msk (0xf0000UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_FP_DEVARCH_ARCHVER_Pos (12UL) /*!< ARCHVER (Bit 12) */ +#define PPB_FP_DEVARCH_ARCHVER_Msk (0xf000UL) /*!< ARCHVER (Bitfield-Mask: 0x0f) */ +#define PPB_FP_DEVARCH_ARCHPART_Pos (0UL) /*!< ARCHPART (Bit 0) */ +#define PPB_FP_DEVARCH_ARCHPART_Msk (0xfffUL) /*!< ARCHPART (Bitfield-Mask: 0xfff) */ +/* ====================================================== FP_DEVTYPE ======================================================= */ +#define PPB_FP_DEVTYPE_SUB_Pos (4UL) /*!< SUB (Bit 4) */ +#define PPB_FP_DEVTYPE_SUB_Msk (0xf0UL) /*!< SUB (Bitfield-Mask: 0x0f) */ +#define PPB_FP_DEVTYPE_MAJOR_Pos (0UL) /*!< MAJOR (Bit 0) */ +#define PPB_FP_DEVTYPE_MAJOR_Msk (0xfUL) /*!< MAJOR (Bitfield-Mask: 0x0f) */ +/* ======================================================= FP_PIDR4 ======================================================== */ +#define PPB_FP_PIDR4_SIZE_Pos (4UL) /*!< SIZE (Bit 4) */ +#define PPB_FP_PIDR4_SIZE_Msk (0xf0UL) /*!< SIZE (Bitfield-Mask: 0x0f) */ +#define PPB_FP_PIDR4_DES_2_Pos (0UL) /*!< DES_2 (Bit 0) */ +#define PPB_FP_PIDR4_DES_2_Msk (0xfUL) /*!< DES_2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= FP_PIDR5 ======================================================== */ +#define PPB_FP_PIDR5_FP_PIDR5_Pos (0UL) /*!< FP_PIDR5 (Bit 0) */ +#define PPB_FP_PIDR5_FP_PIDR5_Msk (0xffffffffUL) /*!< FP_PIDR5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FP_PIDR6 ======================================================== */ +#define PPB_FP_PIDR6_FP_PIDR6_Pos (0UL) /*!< FP_PIDR6 (Bit 0) */ +#define PPB_FP_PIDR6_FP_PIDR6_Msk (0xffffffffUL) /*!< FP_PIDR6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FP_PIDR7 ======================================================== */ +#define PPB_FP_PIDR7_FP_PIDR7_Pos (0UL) /*!< FP_PIDR7 (Bit 0) */ +#define PPB_FP_PIDR7_FP_PIDR7_Msk (0xffffffffUL) /*!< FP_PIDR7 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FP_PIDR0 ======================================================== */ +#define PPB_FP_PIDR0_PART_0_Pos (0UL) /*!< PART_0 (Bit 0) */ +#define PPB_FP_PIDR0_PART_0_Msk (0xffUL) /*!< PART_0 (Bitfield-Mask: 0xff) */ +/* ======================================================= FP_PIDR1 ======================================================== */ +#define PPB_FP_PIDR1_DES_0_Pos (4UL) /*!< DES_0 (Bit 4) */ +#define PPB_FP_PIDR1_DES_0_Msk (0xf0UL) /*!< DES_0 (Bitfield-Mask: 0x0f) */ +#define PPB_FP_PIDR1_PART_1_Pos (0UL) /*!< PART_1 (Bit 0) */ +#define PPB_FP_PIDR1_PART_1_Msk (0xfUL) /*!< PART_1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= FP_PIDR2 ======================================================== */ +#define PPB_FP_PIDR2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */ +#define PPB_FP_PIDR2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_FP_PIDR2_JEDEC_Pos (3UL) /*!< JEDEC (Bit 3) */ +#define PPB_FP_PIDR2_JEDEC_Msk (0x8UL) /*!< JEDEC (Bitfield-Mask: 0x01) */ +#define PPB_FP_PIDR2_DES_1_Pos (0UL) /*!< DES_1 (Bit 0) */ +#define PPB_FP_PIDR2_DES_1_Msk (0x7UL) /*!< DES_1 (Bitfield-Mask: 0x07) */ +/* ======================================================= FP_PIDR3 ======================================================== */ +#define PPB_FP_PIDR3_REVAND_Pos (4UL) /*!< REVAND (Bit 4) */ +#define PPB_FP_PIDR3_REVAND_Msk (0xf0UL) /*!< REVAND (Bitfield-Mask: 0x0f) */ +#define PPB_FP_PIDR3_CMOD_Pos (0UL) /*!< CMOD (Bit 0) */ +#define PPB_FP_PIDR3_CMOD_Msk (0xfUL) /*!< CMOD (Bitfield-Mask: 0x0f) */ +/* ======================================================= FP_CIDR0 ======================================================== */ +#define PPB_FP_CIDR0_PRMBL_0_Pos (0UL) /*!< PRMBL_0 (Bit 0) */ +#define PPB_FP_CIDR0_PRMBL_0_Msk (0xffUL) /*!< PRMBL_0 (Bitfield-Mask: 0xff) */ +/* ======================================================= FP_CIDR1 ======================================================== */ +#define PPB_FP_CIDR1_CLASS_Pos (4UL) /*!< CLASS (Bit 4) */ +#define PPB_FP_CIDR1_CLASS_Msk (0xf0UL) /*!< CLASS (Bitfield-Mask: 0x0f) */ +#define PPB_FP_CIDR1_PRMBL_1_Pos (0UL) /*!< PRMBL_1 (Bit 0) */ +#define PPB_FP_CIDR1_PRMBL_1_Msk (0xfUL) /*!< PRMBL_1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= FP_CIDR2 ======================================================== */ +#define PPB_FP_CIDR2_PRMBL_2_Pos (0UL) /*!< PRMBL_2 (Bit 0) */ +#define PPB_FP_CIDR2_PRMBL_2_Msk (0xffUL) /*!< PRMBL_2 (Bitfield-Mask: 0xff) */ +/* ======================================================= FP_CIDR3 ======================================================== */ +#define PPB_FP_CIDR3_PRMBL_3_Pos (0UL) /*!< PRMBL_3 (Bit 0) */ +#define PPB_FP_CIDR3_PRMBL_3_Msk (0xffUL) /*!< PRMBL_3 (Bitfield-Mask: 0xff) */ +/* ========================================================= ICTR ========================================================== */ +#define PPB_ICTR_INTLINESNUM_Pos (0UL) /*!< INTLINESNUM (Bit 0) */ +#define PPB_ICTR_INTLINESNUM_Msk (0xfUL) /*!< INTLINESNUM (Bitfield-Mask: 0x0f) */ +/* ========================================================= ACTLR ========================================================= */ +#define PPB_ACTLR_EXTEXCLALL_Pos (29UL) /*!< EXTEXCLALL (Bit 29) */ +#define PPB_ACTLR_EXTEXCLALL_Msk (0x20000000UL) /*!< EXTEXCLALL (Bitfield-Mask: 0x01) */ +#define PPB_ACTLR_DISITMATBFLUSH_Pos (12UL) /*!< DISITMATBFLUSH (Bit 12) */ +#define PPB_ACTLR_DISITMATBFLUSH_Msk (0x1000UL) /*!< DISITMATBFLUSH (Bitfield-Mask: 0x01) */ +#define PPB_ACTLR_FPEXCODIS_Pos (10UL) /*!< FPEXCODIS (Bit 10) */ +#define PPB_ACTLR_FPEXCODIS_Msk (0x400UL) /*!< FPEXCODIS (Bitfield-Mask: 0x01) */ +#define PPB_ACTLR_DISOOFP_Pos (9UL) /*!< DISOOFP (Bit 9) */ +#define PPB_ACTLR_DISOOFP_Msk (0x200UL) /*!< DISOOFP (Bitfield-Mask: 0x01) */ +#define PPB_ACTLR_DISFOLD_Pos (2UL) /*!< DISFOLD (Bit 2) */ +#define PPB_ACTLR_DISFOLD_Msk (0x4UL) /*!< DISFOLD (Bitfield-Mask: 0x01) */ +#define PPB_ACTLR_DISMCYCINT_Pos (0UL) /*!< DISMCYCINT (Bit 0) */ +#define PPB_ACTLR_DISMCYCINT_Msk (0x1UL) /*!< DISMCYCINT (Bitfield-Mask: 0x01) */ +/* ======================================================= SYST_CSR ======================================================== */ +#define PPB_SYST_CSR_COUNTFLAG_Pos (16UL) /*!< COUNTFLAG (Bit 16) */ +#define PPB_SYST_CSR_COUNTFLAG_Msk (0x10000UL) /*!< COUNTFLAG (Bitfield-Mask: 0x01) */ +#define PPB_SYST_CSR_CLKSOURCE_Pos (2UL) /*!< CLKSOURCE (Bit 2) */ +#define PPB_SYST_CSR_CLKSOURCE_Msk (0x4UL) /*!< CLKSOURCE (Bitfield-Mask: 0x01) */ +#define PPB_SYST_CSR_TICKINT_Pos (1UL) /*!< TICKINT (Bit 1) */ +#define PPB_SYST_CSR_TICKINT_Msk (0x2UL) /*!< TICKINT (Bitfield-Mask: 0x01) */ +#define PPB_SYST_CSR_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define PPB_SYST_CSR_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= SYST_RVR ======================================================== */ +#define PPB_SYST_RVR_RELOAD_Pos (0UL) /*!< RELOAD (Bit 0) */ +#define PPB_SYST_RVR_RELOAD_Msk (0xffffffUL) /*!< RELOAD (Bitfield-Mask: 0xffffff) */ +/* ======================================================= SYST_CVR ======================================================== */ +#define PPB_SYST_CVR_CURRENT_Pos (0UL) /*!< CURRENT (Bit 0) */ +#define PPB_SYST_CVR_CURRENT_Msk (0xffffffUL) /*!< CURRENT (Bitfield-Mask: 0xffffff) */ +/* ====================================================== SYST_CALIB ======================================================= */ +#define PPB_SYST_CALIB_NOREF_Pos (31UL) /*!< NOREF (Bit 31) */ +#define PPB_SYST_CALIB_NOREF_Msk (0x80000000UL) /*!< NOREF (Bitfield-Mask: 0x01) */ +#define PPB_SYST_CALIB_SKEW_Pos (30UL) /*!< SKEW (Bit 30) */ +#define PPB_SYST_CALIB_SKEW_Msk (0x40000000UL) /*!< SKEW (Bitfield-Mask: 0x01) */ +#define PPB_SYST_CALIB_TENMS_Pos (0UL) /*!< TENMS (Bit 0) */ +#define PPB_SYST_CALIB_TENMS_Msk (0xffffffUL) /*!< TENMS (Bitfield-Mask: 0xffffff) */ +/* ====================================================== NVIC_ISER0 ======================================================= */ +#define PPB_NVIC_ISER0_SETENA_Pos (0UL) /*!< SETENA (Bit 0) */ +#define PPB_NVIC_ISER0_SETENA_Msk (0xffffffffUL) /*!< SETENA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_ISER1 ======================================================= */ +#define PPB_NVIC_ISER1_SETENA_Pos (0UL) /*!< SETENA (Bit 0) */ +#define PPB_NVIC_ISER1_SETENA_Msk (0xffffffffUL) /*!< SETENA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_ICER0 ======================================================= */ +#define PPB_NVIC_ICER0_CLRENA_Pos (0UL) /*!< CLRENA (Bit 0) */ +#define PPB_NVIC_ICER0_CLRENA_Msk (0xffffffffUL) /*!< CLRENA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_ICER1 ======================================================= */ +#define PPB_NVIC_ICER1_CLRENA_Pos (0UL) /*!< CLRENA (Bit 0) */ +#define PPB_NVIC_ICER1_CLRENA_Msk (0xffffffffUL) /*!< CLRENA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_ISPR0 ======================================================= */ +#define PPB_NVIC_ISPR0_SETPEND_Pos (0UL) /*!< SETPEND (Bit 0) */ +#define PPB_NVIC_ISPR0_SETPEND_Msk (0xffffffffUL) /*!< SETPEND (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_ISPR1 ======================================================= */ +#define PPB_NVIC_ISPR1_SETPEND_Pos (0UL) /*!< SETPEND (Bit 0) */ +#define PPB_NVIC_ISPR1_SETPEND_Msk (0xffffffffUL) /*!< SETPEND (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_ICPR0 ======================================================= */ +#define PPB_NVIC_ICPR0_CLRPEND_Pos (0UL) /*!< CLRPEND (Bit 0) */ +#define PPB_NVIC_ICPR0_CLRPEND_Msk (0xffffffffUL) /*!< CLRPEND (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_ICPR1 ======================================================= */ +#define PPB_NVIC_ICPR1_CLRPEND_Pos (0UL) /*!< CLRPEND (Bit 0) */ +#define PPB_NVIC_ICPR1_CLRPEND_Msk (0xffffffffUL) /*!< CLRPEND (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_IABR0 ======================================================= */ +#define PPB_NVIC_IABR0_ACTIVE_Pos (0UL) /*!< ACTIVE (Bit 0) */ +#define PPB_NVIC_IABR0_ACTIVE_Msk (0xffffffffUL) /*!< ACTIVE (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_IABR1 ======================================================= */ +#define PPB_NVIC_IABR1_ACTIVE_Pos (0UL) /*!< ACTIVE (Bit 0) */ +#define PPB_NVIC_IABR1_ACTIVE_Msk (0xffffffffUL) /*!< ACTIVE (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_ITNS0 ======================================================= */ +#define PPB_NVIC_ITNS0_ITNS_Pos (0UL) /*!< ITNS (Bit 0) */ +#define PPB_NVIC_ITNS0_ITNS_Msk (0xffffffffUL) /*!< ITNS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== NVIC_ITNS1 ======================================================= */ +#define PPB_NVIC_ITNS1_ITNS_Pos (0UL) /*!< ITNS (Bit 0) */ +#define PPB_NVIC_ITNS1_ITNS_Msk (0xffffffffUL) /*!< ITNS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= NVIC_IPR0 ======================================================= */ +#define PPB_NVIC_IPR0_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR0_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR0_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR0_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR0_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR0_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR0_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR0_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= NVIC_IPR1 ======================================================= */ +#define PPB_NVIC_IPR1_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR1_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR1_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR1_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR1_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR1_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR1_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR1_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= NVIC_IPR2 ======================================================= */ +#define PPB_NVIC_IPR2_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR2_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR2_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR2_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR2_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR2_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR2_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR2_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= NVIC_IPR3 ======================================================= */ +#define PPB_NVIC_IPR3_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR3_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR3_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR3_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR3_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR3_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR3_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR3_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= NVIC_IPR4 ======================================================= */ +#define PPB_NVIC_IPR4_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR4_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR4_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR4_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR4_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR4_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR4_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR4_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= NVIC_IPR5 ======================================================= */ +#define PPB_NVIC_IPR5_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR5_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR5_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR5_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR5_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR5_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR5_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR5_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= NVIC_IPR6 ======================================================= */ +#define PPB_NVIC_IPR6_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR6_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR6_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR6_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR6_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR6_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR6_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR6_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= NVIC_IPR7 ======================================================= */ +#define PPB_NVIC_IPR7_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR7_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR7_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR7_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR7_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR7_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR7_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR7_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= NVIC_IPR8 ======================================================= */ +#define PPB_NVIC_IPR8_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR8_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR8_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR8_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR8_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR8_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR8_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR8_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= NVIC_IPR9 ======================================================= */ +#define PPB_NVIC_IPR9_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR9_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR9_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR9_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR9_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR9_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR9_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR9_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ====================================================== NVIC_IPR10 ======================================================= */ +#define PPB_NVIC_IPR10_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR10_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR10_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR10_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR10_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR10_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR10_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR10_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ====================================================== NVIC_IPR11 ======================================================= */ +#define PPB_NVIC_IPR11_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR11_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR11_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR11_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR11_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR11_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR11_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR11_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ====================================================== NVIC_IPR12 ======================================================= */ +#define PPB_NVIC_IPR12_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR12_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR12_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR12_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR12_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR12_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR12_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR12_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ====================================================== NVIC_IPR13 ======================================================= */ +#define PPB_NVIC_IPR13_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR13_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR13_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR13_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR13_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR13_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR13_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR13_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ====================================================== NVIC_IPR14 ======================================================= */ +#define PPB_NVIC_IPR14_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR14_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR14_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR14_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR14_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR14_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR14_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR14_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ====================================================== NVIC_IPR15 ======================================================= */ +#define PPB_NVIC_IPR15_PRI_N3_Pos (28UL) /*!< PRI_N3 (Bit 28) */ +#define PPB_NVIC_IPR15_PRI_N3_Msk (0xf0000000UL) /*!< PRI_N3 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR15_PRI_N2_Pos (20UL) /*!< PRI_N2 (Bit 20) */ +#define PPB_NVIC_IPR15_PRI_N2_Msk (0xf00000UL) /*!< PRI_N2 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR15_PRI_N1_Pos (12UL) /*!< PRI_N1 (Bit 12) */ +#define PPB_NVIC_IPR15_PRI_N1_Msk (0xf000UL) /*!< PRI_N1 (Bitfield-Mask: 0x0f) */ +#define PPB_NVIC_IPR15_PRI_N0_Pos (4UL) /*!< PRI_N0 (Bit 4) */ +#define PPB_NVIC_IPR15_PRI_N0_Msk (0xf0UL) /*!< PRI_N0 (Bitfield-Mask: 0x0f) */ +/* ========================================================= CPUID ========================================================= */ +#define PPB_CPUID_IMPLEMENTER_Pos (24UL) /*!< IMPLEMENTER (Bit 24) */ +#define PPB_CPUID_IMPLEMENTER_Msk (0xff000000UL) /*!< IMPLEMENTER (Bitfield-Mask: 0xff) */ +#define PPB_CPUID_VARIANT_Pos (20UL) /*!< VARIANT (Bit 20) */ +#define PPB_CPUID_VARIANT_Msk (0xf00000UL) /*!< VARIANT (Bitfield-Mask: 0x0f) */ +#define PPB_CPUID_ARCHITECTURE_Pos (16UL) /*!< ARCHITECTURE (Bit 16) */ +#define PPB_CPUID_ARCHITECTURE_Msk (0xf0000UL) /*!< ARCHITECTURE (Bitfield-Mask: 0x0f) */ +#define PPB_CPUID_PARTNO_Pos (4UL) /*!< PARTNO (Bit 4) */ +#define PPB_CPUID_PARTNO_Msk (0xfff0UL) /*!< PARTNO (Bitfield-Mask: 0xfff) */ +#define PPB_CPUID_REVISION_Pos (0UL) /*!< REVISION (Bit 0) */ +#define PPB_CPUID_REVISION_Msk (0xfUL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +/* ========================================================= ICSR ========================================================== */ +#define PPB_ICSR_PENDNMISET_Pos (31UL) /*!< PENDNMISET (Bit 31) */ +#define PPB_ICSR_PENDNMISET_Msk (0x80000000UL) /*!< PENDNMISET (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_PENDNMICLR_Pos (30UL) /*!< PENDNMICLR (Bit 30) */ +#define PPB_ICSR_PENDNMICLR_Msk (0x40000000UL) /*!< PENDNMICLR (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_PENDSVSET_Pos (28UL) /*!< PENDSVSET (Bit 28) */ +#define PPB_ICSR_PENDSVSET_Msk (0x10000000UL) /*!< PENDSVSET (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_PENDSVCLR_Pos (27UL) /*!< PENDSVCLR (Bit 27) */ +#define PPB_ICSR_PENDSVCLR_Msk (0x8000000UL) /*!< PENDSVCLR (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_PENDSTSET_Pos (26UL) /*!< PENDSTSET (Bit 26) */ +#define PPB_ICSR_PENDSTSET_Msk (0x4000000UL) /*!< PENDSTSET (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_PENDSTCLR_Pos (25UL) /*!< PENDSTCLR (Bit 25) */ +#define PPB_ICSR_PENDSTCLR_Msk (0x2000000UL) /*!< PENDSTCLR (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_STTNS_Pos (24UL) /*!< STTNS (Bit 24) */ +#define PPB_ICSR_STTNS_Msk (0x1000000UL) /*!< STTNS (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_ISRPREEMPT_Pos (23UL) /*!< ISRPREEMPT (Bit 23) */ +#define PPB_ICSR_ISRPREEMPT_Msk (0x800000UL) /*!< ISRPREEMPT (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_ISRPENDING_Pos (22UL) /*!< ISRPENDING (Bit 22) */ +#define PPB_ICSR_ISRPENDING_Msk (0x400000UL) /*!< ISRPENDING (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_VECTPENDING_Pos (12UL) /*!< VECTPENDING (Bit 12) */ +#define PPB_ICSR_VECTPENDING_Msk (0x1ff000UL) /*!< VECTPENDING (Bitfield-Mask: 0x1ff) */ +#define PPB_ICSR_RETTOBASE_Pos (11UL) /*!< RETTOBASE (Bit 11) */ +#define PPB_ICSR_RETTOBASE_Msk (0x800UL) /*!< RETTOBASE (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_VECTACTIVE_Pos (0UL) /*!< VECTACTIVE (Bit 0) */ +#define PPB_ICSR_VECTACTIVE_Msk (0x1ffUL) /*!< VECTACTIVE (Bitfield-Mask: 0x1ff) */ +/* ========================================================= VTOR ========================================================== */ +#define PPB_VTOR_TBLOFF_Pos (7UL) /*!< TBLOFF (Bit 7) */ +#define PPB_VTOR_TBLOFF_Msk (0xffffff80UL) /*!< TBLOFF (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================= AIRCR ========================================================= */ +#define PPB_AIRCR_VECTKEY_Pos (16UL) /*!< VECTKEY (Bit 16) */ +#define PPB_AIRCR_VECTKEY_Msk (0xffff0000UL) /*!< VECTKEY (Bitfield-Mask: 0xffff) */ +#define PPB_AIRCR_ENDIANESS_Pos (15UL) /*!< ENDIANESS (Bit 15) */ +#define PPB_AIRCR_ENDIANESS_Msk (0x8000UL) /*!< ENDIANESS (Bitfield-Mask: 0x01) */ +#define PPB_AIRCR_PRIS_Pos (14UL) /*!< PRIS (Bit 14) */ +#define PPB_AIRCR_PRIS_Msk (0x4000UL) /*!< PRIS (Bitfield-Mask: 0x01) */ +#define PPB_AIRCR_BFHFNMINS_Pos (13UL) /*!< BFHFNMINS (Bit 13) */ +#define PPB_AIRCR_BFHFNMINS_Msk (0x2000UL) /*!< BFHFNMINS (Bitfield-Mask: 0x01) */ +#define PPB_AIRCR_PRIGROUP_Pos (8UL) /*!< PRIGROUP (Bit 8) */ +#define PPB_AIRCR_PRIGROUP_Msk (0x700UL) /*!< PRIGROUP (Bitfield-Mask: 0x07) */ +#define PPB_AIRCR_SYSRESETREQS_Pos (3UL) /*!< SYSRESETREQS (Bit 3) */ +#define PPB_AIRCR_SYSRESETREQS_Msk (0x8UL) /*!< SYSRESETREQS (Bitfield-Mask: 0x01) */ +#define PPB_AIRCR_SYSRESETREQ_Pos (2UL) /*!< SYSRESETREQ (Bit 2) */ +#define PPB_AIRCR_SYSRESETREQ_Msk (0x4UL) /*!< SYSRESETREQ (Bitfield-Mask: 0x01) */ +#define PPB_AIRCR_VECTCLRACTIVE_Pos (1UL) /*!< VECTCLRACTIVE (Bit 1) */ +#define PPB_AIRCR_VECTCLRACTIVE_Msk (0x2UL) /*!< VECTCLRACTIVE (Bitfield-Mask: 0x01) */ +/* ========================================================== SCR ========================================================== */ +#define PPB_SCR_SEVONPEND_Pos (4UL) /*!< SEVONPEND (Bit 4) */ +#define PPB_SCR_SEVONPEND_Msk (0x10UL) /*!< SEVONPEND (Bitfield-Mask: 0x01) */ +#define PPB_SCR_SLEEPDEEPS_Pos (3UL) /*!< SLEEPDEEPS (Bit 3) */ +#define PPB_SCR_SLEEPDEEPS_Msk (0x8UL) /*!< SLEEPDEEPS (Bitfield-Mask: 0x01) */ +#define PPB_SCR_SLEEPDEEP_Pos (2UL) /*!< SLEEPDEEP (Bit 2) */ +#define PPB_SCR_SLEEPDEEP_Msk (0x4UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */ +#define PPB_SCR_SLEEPONEXIT_Pos (1UL) /*!< SLEEPONEXIT (Bit 1) */ +#define PPB_SCR_SLEEPONEXIT_Msk (0x2UL) /*!< SLEEPONEXIT (Bitfield-Mask: 0x01) */ +/* ========================================================== CCR ========================================================== */ +#define PPB_CCR_BP_Pos (18UL) /*!< BP (Bit 18) */ +#define PPB_CCR_BP_Msk (0x40000UL) /*!< BP (Bitfield-Mask: 0x01) */ +#define PPB_CCR_IC_Pos (17UL) /*!< IC (Bit 17) */ +#define PPB_CCR_IC_Msk (0x20000UL) /*!< IC (Bitfield-Mask: 0x01) */ +#define PPB_CCR_DC_Pos (16UL) /*!< DC (Bit 16) */ +#define PPB_CCR_DC_Msk (0x10000UL) /*!< DC (Bitfield-Mask: 0x01) */ +#define PPB_CCR_STKOFHFNMIGN_Pos (10UL) /*!< STKOFHFNMIGN (Bit 10) */ +#define PPB_CCR_STKOFHFNMIGN_Msk (0x400UL) /*!< STKOFHFNMIGN (Bitfield-Mask: 0x01) */ +#define PPB_CCR_RES1_Pos (9UL) /*!< RES1 (Bit 9) */ +#define PPB_CCR_RES1_Msk (0x200UL) /*!< RES1 (Bitfield-Mask: 0x01) */ +#define PPB_CCR_BFHFNMIGN_Pos (8UL) /*!< BFHFNMIGN (Bit 8) */ +#define PPB_CCR_BFHFNMIGN_Msk (0x100UL) /*!< BFHFNMIGN (Bitfield-Mask: 0x01) */ +#define PPB_CCR_DIV_0_TRP_Pos (4UL) /*!< DIV_0_TRP (Bit 4) */ +#define PPB_CCR_DIV_0_TRP_Msk (0x10UL) /*!< DIV_0_TRP (Bitfield-Mask: 0x01) */ +#define PPB_CCR_UNALIGN_TRP_Pos (3UL) /*!< UNALIGN_TRP (Bit 3) */ +#define PPB_CCR_UNALIGN_TRP_Msk (0x8UL) /*!< UNALIGN_TRP (Bitfield-Mask: 0x01) */ +#define PPB_CCR_USERSETMPEND_Pos (1UL) /*!< USERSETMPEND (Bit 1) */ +#define PPB_CCR_USERSETMPEND_Msk (0x2UL) /*!< USERSETMPEND (Bitfield-Mask: 0x01) */ +#define PPB_CCR_RES1_1_Pos (0UL) /*!< RES1_1 (Bit 0) */ +#define PPB_CCR_RES1_1_Msk (0x1UL) /*!< RES1_1 (Bitfield-Mask: 0x01) */ +/* ========================================================= SHPR1 ========================================================= */ +#define PPB_SHPR1_PRI_7_3_Pos (29UL) /*!< PRI_7_3 (Bit 29) */ +#define PPB_SHPR1_PRI_7_3_Msk (0xe0000000UL) /*!< PRI_7_3 (Bitfield-Mask: 0x07) */ +#define PPB_SHPR1_PRI_6_3_Pos (21UL) /*!< PRI_6_3 (Bit 21) */ +#define PPB_SHPR1_PRI_6_3_Msk (0xe00000UL) /*!< PRI_6_3 (Bitfield-Mask: 0x07) */ +#define PPB_SHPR1_PRI_5_3_Pos (13UL) /*!< PRI_5_3 (Bit 13) */ +#define PPB_SHPR1_PRI_5_3_Msk (0xe000UL) /*!< PRI_5_3 (Bitfield-Mask: 0x07) */ +#define PPB_SHPR1_PRI_4_3_Pos (5UL) /*!< PRI_4_3 (Bit 5) */ +#define PPB_SHPR1_PRI_4_3_Msk (0xe0UL) /*!< PRI_4_3 (Bitfield-Mask: 0x07) */ +/* ========================================================= SHPR2 ========================================================= */ +#define PPB_SHPR2_PRI_11_3_Pos (29UL) /*!< PRI_11_3 (Bit 29) */ +#define PPB_SHPR2_PRI_11_3_Msk (0xe0000000UL) /*!< PRI_11_3 (Bitfield-Mask: 0x07) */ +#define PPB_SHPR2_PRI_10_Pos (16UL) /*!< PRI_10 (Bit 16) */ +#define PPB_SHPR2_PRI_10_Msk (0xff0000UL) /*!< PRI_10 (Bitfield-Mask: 0xff) */ +#define PPB_SHPR2_PRI_9_Pos (8UL) /*!< PRI_9 (Bit 8) */ +#define PPB_SHPR2_PRI_9_Msk (0xff00UL) /*!< PRI_9 (Bitfield-Mask: 0xff) */ +#define PPB_SHPR2_PRI_8_Pos (0UL) /*!< PRI_8 (Bit 0) */ +#define PPB_SHPR2_PRI_8_Msk (0xffUL) /*!< PRI_8 (Bitfield-Mask: 0xff) */ +/* ========================================================= SHPR3 ========================================================= */ +#define PPB_SHPR3_PRI_15_3_Pos (29UL) /*!< PRI_15_3 (Bit 29) */ +#define PPB_SHPR3_PRI_15_3_Msk (0xe0000000UL) /*!< PRI_15_3 (Bitfield-Mask: 0x07) */ +#define PPB_SHPR3_PRI_14_3_Pos (21UL) /*!< PRI_14_3 (Bit 21) */ +#define PPB_SHPR3_PRI_14_3_Msk (0xe00000UL) /*!< PRI_14_3 (Bitfield-Mask: 0x07) */ +#define PPB_SHPR3_PRI_13_Pos (8UL) /*!< PRI_13 (Bit 8) */ +#define PPB_SHPR3_PRI_13_Msk (0xff00UL) /*!< PRI_13 (Bitfield-Mask: 0xff) */ +#define PPB_SHPR3_PRI_12_3_Pos (5UL) /*!< PRI_12_3 (Bit 5) */ +#define PPB_SHPR3_PRI_12_3_Msk (0xe0UL) /*!< PRI_12_3 (Bitfield-Mask: 0x07) */ +/* ========================================================= SHCSR ========================================================= */ +#define PPB_SHCSR_HARDFAULTPENDED_Pos (21UL) /*!< HARDFAULTPENDED (Bit 21) */ +#define PPB_SHCSR_HARDFAULTPENDED_Msk (0x200000UL) /*!< HARDFAULTPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_SECUREFAULTPENDED_Pos (20UL) /*!< SECUREFAULTPENDED (Bit 20) */ +#define PPB_SHCSR_SECUREFAULTPENDED_Msk (0x100000UL) /*!< SECUREFAULTPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_SECUREFAULTENA_Pos (19UL) /*!< SECUREFAULTENA (Bit 19) */ +#define PPB_SHCSR_SECUREFAULTENA_Msk (0x80000UL) /*!< SECUREFAULTENA (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_USGFAULTENA_Pos (18UL) /*!< USGFAULTENA (Bit 18) */ +#define PPB_SHCSR_USGFAULTENA_Msk (0x40000UL) /*!< USGFAULTENA (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_BUSFAULTENA_Pos (17UL) /*!< BUSFAULTENA (Bit 17) */ +#define PPB_SHCSR_BUSFAULTENA_Msk (0x20000UL) /*!< BUSFAULTENA (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_MEMFAULTENA_Pos (16UL) /*!< MEMFAULTENA (Bit 16) */ +#define PPB_SHCSR_MEMFAULTENA_Msk (0x10000UL) /*!< MEMFAULTENA (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_SVCALLPENDED_Pos (15UL) /*!< SVCALLPENDED (Bit 15) */ +#define PPB_SHCSR_SVCALLPENDED_Msk (0x8000UL) /*!< SVCALLPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_BUSFAULTPENDED_Pos (14UL) /*!< BUSFAULTPENDED (Bit 14) */ +#define PPB_SHCSR_BUSFAULTPENDED_Msk (0x4000UL) /*!< BUSFAULTPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_MEMFAULTPENDED_Pos (13UL) /*!< MEMFAULTPENDED (Bit 13) */ +#define PPB_SHCSR_MEMFAULTPENDED_Msk (0x2000UL) /*!< MEMFAULTPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_USGFAULTPENDED_Pos (12UL) /*!< USGFAULTPENDED (Bit 12) */ +#define PPB_SHCSR_USGFAULTPENDED_Msk (0x1000UL) /*!< USGFAULTPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_SYSTICKACT_Pos (11UL) /*!< SYSTICKACT (Bit 11) */ +#define PPB_SHCSR_SYSTICKACT_Msk (0x800UL) /*!< SYSTICKACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_PENDSVACT_Pos (10UL) /*!< PENDSVACT (Bit 10) */ +#define PPB_SHCSR_PENDSVACT_Msk (0x400UL) /*!< PENDSVACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_MONITORACT_Pos (8UL) /*!< MONITORACT (Bit 8) */ +#define PPB_SHCSR_MONITORACT_Msk (0x100UL) /*!< MONITORACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_SVCALLACT_Pos (7UL) /*!< SVCALLACT (Bit 7) */ +#define PPB_SHCSR_SVCALLACT_Msk (0x80UL) /*!< SVCALLACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_NMIACT_Pos (5UL) /*!< NMIACT (Bit 5) */ +#define PPB_SHCSR_NMIACT_Msk (0x20UL) /*!< NMIACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_SECUREFAULTACT_Pos (4UL) /*!< SECUREFAULTACT (Bit 4) */ +#define PPB_SHCSR_SECUREFAULTACT_Msk (0x10UL) /*!< SECUREFAULTACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_USGFAULTACT_Pos (3UL) /*!< USGFAULTACT (Bit 3) */ +#define PPB_SHCSR_USGFAULTACT_Msk (0x8UL) /*!< USGFAULTACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_HARDFAULTACT_Pos (2UL) /*!< HARDFAULTACT (Bit 2) */ +#define PPB_SHCSR_HARDFAULTACT_Msk (0x4UL) /*!< HARDFAULTACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_BUSFAULTACT_Pos (1UL) /*!< BUSFAULTACT (Bit 1) */ +#define PPB_SHCSR_BUSFAULTACT_Msk (0x2UL) /*!< BUSFAULTACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_MEMFAULTACT_Pos (0UL) /*!< MEMFAULTACT (Bit 0) */ +#define PPB_SHCSR_MEMFAULTACT_Msk (0x1UL) /*!< MEMFAULTACT (Bitfield-Mask: 0x01) */ +/* ========================================================= CFSR ========================================================== */ +#define PPB_CFSR_UFSR_DIVBYZERO_Pos (25UL) /*!< UFSR_DIVBYZERO (Bit 25) */ +#define PPB_CFSR_UFSR_DIVBYZERO_Msk (0x2000000UL) /*!< UFSR_DIVBYZERO (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_UFSR_UNALIGNED_Pos (24UL) /*!< UFSR_UNALIGNED (Bit 24) */ +#define PPB_CFSR_UFSR_UNALIGNED_Msk (0x1000000UL) /*!< UFSR_UNALIGNED (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_UFSR_STKOF_Pos (20UL) /*!< UFSR_STKOF (Bit 20) */ +#define PPB_CFSR_UFSR_STKOF_Msk (0x100000UL) /*!< UFSR_STKOF (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_UFSR_NOCP_Pos (19UL) /*!< UFSR_NOCP (Bit 19) */ +#define PPB_CFSR_UFSR_NOCP_Msk (0x80000UL) /*!< UFSR_NOCP (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_UFSR_INVPC_Pos (18UL) /*!< UFSR_INVPC (Bit 18) */ +#define PPB_CFSR_UFSR_INVPC_Msk (0x40000UL) /*!< UFSR_INVPC (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_UFSR_INVSTATE_Pos (17UL) /*!< UFSR_INVSTATE (Bit 17) */ +#define PPB_CFSR_UFSR_INVSTATE_Msk (0x20000UL) /*!< UFSR_INVSTATE (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_UFSR_UNDEFINSTR_Pos (16UL) /*!< UFSR_UNDEFINSTR (Bit 16) */ +#define PPB_CFSR_UFSR_UNDEFINSTR_Msk (0x10000UL) /*!< UFSR_UNDEFINSTR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_BFSR_BFARVALID_Pos (15UL) /*!< BFSR_BFARVALID (Bit 15) */ +#define PPB_CFSR_BFSR_BFARVALID_Msk (0x8000UL) /*!< BFSR_BFARVALID (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_BFSR_LSPERR_Pos (13UL) /*!< BFSR_LSPERR (Bit 13) */ +#define PPB_CFSR_BFSR_LSPERR_Msk (0x2000UL) /*!< BFSR_LSPERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_BFSR_STKERR_Pos (12UL) /*!< BFSR_STKERR (Bit 12) */ +#define PPB_CFSR_BFSR_STKERR_Msk (0x1000UL) /*!< BFSR_STKERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_BFSR_UNSTKERR_Pos (11UL) /*!< BFSR_UNSTKERR (Bit 11) */ +#define PPB_CFSR_BFSR_UNSTKERR_Msk (0x800UL) /*!< BFSR_UNSTKERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_BFSR_IMPRECISERR_Pos (10UL) /*!< BFSR_IMPRECISERR (Bit 10) */ +#define PPB_CFSR_BFSR_IMPRECISERR_Msk (0x400UL) /*!< BFSR_IMPRECISERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_BFSR_PRECISERR_Pos (9UL) /*!< BFSR_PRECISERR (Bit 9) */ +#define PPB_CFSR_BFSR_PRECISERR_Msk (0x200UL) /*!< BFSR_PRECISERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_BFSR_IBUSERR_Pos (8UL) /*!< BFSR_IBUSERR (Bit 8) */ +#define PPB_CFSR_BFSR_IBUSERR_Msk (0x100UL) /*!< BFSR_IBUSERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_MMFSR_Pos (0UL) /*!< MMFSR (Bit 0) */ +#define PPB_CFSR_MMFSR_Msk (0xffUL) /*!< MMFSR (Bitfield-Mask: 0xff) */ +/* ========================================================= HFSR ========================================================== */ +#define PPB_HFSR_DEBUGEVT_Pos (31UL) /*!< DEBUGEVT (Bit 31) */ +#define PPB_HFSR_DEBUGEVT_Msk (0x80000000UL) /*!< DEBUGEVT (Bitfield-Mask: 0x01) */ +#define PPB_HFSR_FORCED_Pos (30UL) /*!< FORCED (Bit 30) */ +#define PPB_HFSR_FORCED_Msk (0x40000000UL) /*!< FORCED (Bitfield-Mask: 0x01) */ +#define PPB_HFSR_VECTTBL_Pos (1UL) /*!< VECTTBL (Bit 1) */ +#define PPB_HFSR_VECTTBL_Msk (0x2UL) /*!< VECTTBL (Bitfield-Mask: 0x01) */ +/* ========================================================= DFSR ========================================================== */ +#define PPB_DFSR_EXTERNAL_Pos (4UL) /*!< EXTERNAL (Bit 4) */ +#define PPB_DFSR_EXTERNAL_Msk (0x10UL) /*!< EXTERNAL (Bitfield-Mask: 0x01) */ +#define PPB_DFSR_VCATCH_Pos (3UL) /*!< VCATCH (Bit 3) */ +#define PPB_DFSR_VCATCH_Msk (0x8UL) /*!< VCATCH (Bitfield-Mask: 0x01) */ +#define PPB_DFSR_DWTTRAP_Pos (2UL) /*!< DWTTRAP (Bit 2) */ +#define PPB_DFSR_DWTTRAP_Msk (0x4UL) /*!< DWTTRAP (Bitfield-Mask: 0x01) */ +#define PPB_DFSR_BKPT_Pos (1UL) /*!< BKPT (Bit 1) */ +#define PPB_DFSR_BKPT_Msk (0x2UL) /*!< BKPT (Bitfield-Mask: 0x01) */ +#define PPB_DFSR_HALTED_Pos (0UL) /*!< HALTED (Bit 0) */ +#define PPB_DFSR_HALTED_Msk (0x1UL) /*!< HALTED (Bitfield-Mask: 0x01) */ +/* ========================================================= MMFAR ========================================================= */ +#define PPB_MMFAR_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define PPB_MMFAR_ADDRESS_Msk (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= BFAR ========================================================== */ +#define PPB_BFAR_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define PPB_BFAR_ADDRESS_Msk (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ID_PFR0 ======================================================== */ +#define PPB_ID_PFR0_STATE1_Pos (4UL) /*!< STATE1 (Bit 4) */ +#define PPB_ID_PFR0_STATE1_Msk (0xf0UL) /*!< STATE1 (Bitfield-Mask: 0x0f) */ +#define PPB_ID_PFR0_STATE0_Pos (0UL) /*!< STATE0 (Bit 0) */ +#define PPB_ID_PFR0_STATE0_Msk (0xfUL) /*!< STATE0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ID_PFR1 ======================================================== */ +#define PPB_ID_PFR1_MPROGMOD_Pos (8UL) /*!< MPROGMOD (Bit 8) */ +#define PPB_ID_PFR1_MPROGMOD_Msk (0xf00UL) /*!< MPROGMOD (Bitfield-Mask: 0x0f) */ +#define PPB_ID_PFR1_SECURITY_Pos (4UL) /*!< SECURITY (Bit 4) */ +#define PPB_ID_PFR1_SECURITY_Msk (0xf0UL) /*!< SECURITY (Bitfield-Mask: 0x0f) */ +/* ======================================================== ID_DFR0 ======================================================== */ +#define PPB_ID_DFR0_MPROFDBG_Pos (20UL) /*!< MPROFDBG (Bit 20) */ +#define PPB_ID_DFR0_MPROFDBG_Msk (0xf00000UL) /*!< MPROFDBG (Bitfield-Mask: 0x0f) */ +/* ======================================================== ID_AFR0 ======================================================== */ +#define PPB_ID_AFR0_IMPDEF3_Pos (12UL) /*!< IMPDEF3 (Bit 12) */ +#define PPB_ID_AFR0_IMPDEF3_Msk (0xf000UL) /*!< IMPDEF3 (Bitfield-Mask: 0x0f) */ +#define PPB_ID_AFR0_IMPDEF2_Pos (8UL) /*!< IMPDEF2 (Bit 8) */ +#define PPB_ID_AFR0_IMPDEF2_Msk (0xf00UL) /*!< IMPDEF2 (Bitfield-Mask: 0x0f) */ +#define PPB_ID_AFR0_IMPDEF1_Pos (4UL) /*!< IMPDEF1 (Bit 4) */ +#define PPB_ID_AFR0_IMPDEF1_Msk (0xf0UL) /*!< IMPDEF1 (Bitfield-Mask: 0x0f) */ +#define PPB_ID_AFR0_IMPDEF0_Pos (0UL) /*!< IMPDEF0 (Bit 0) */ +#define PPB_ID_AFR0_IMPDEF0_Msk (0xfUL) /*!< IMPDEF0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ID_MMFR0 ======================================================== */ +#define PPB_ID_MMFR0_AUXREG_Pos (20UL) /*!< AUXREG (Bit 20) */ +#define PPB_ID_MMFR0_AUXREG_Msk (0xf00000UL) /*!< AUXREG (Bitfield-Mask: 0x0f) */ +#define PPB_ID_MMFR0_TCM_Pos (16UL) /*!< TCM (Bit 16) */ +#define PPB_ID_MMFR0_TCM_Msk (0xf0000UL) /*!< TCM (Bitfield-Mask: 0x0f) */ +#define PPB_ID_MMFR0_SHARELVL_Pos (12UL) /*!< SHARELVL (Bit 12) */ +#define PPB_ID_MMFR0_SHARELVL_Msk (0xf000UL) /*!< SHARELVL (Bitfield-Mask: 0x0f) */ +#define PPB_ID_MMFR0_OUTERSHR_Pos (8UL) /*!< OUTERSHR (Bit 8) */ +#define PPB_ID_MMFR0_OUTERSHR_Msk (0xf00UL) /*!< OUTERSHR (Bitfield-Mask: 0x0f) */ +#define PPB_ID_MMFR0_PMSA_Pos (4UL) /*!< PMSA (Bit 4) */ +#define PPB_ID_MMFR0_PMSA_Msk (0xf0UL) /*!< PMSA (Bitfield-Mask: 0x0f) */ +/* ======================================================= ID_MMFR1 ======================================================== */ +#define PPB_ID_MMFR1_ID_MMFR1_Pos (0UL) /*!< ID_MMFR1 (Bit 0) */ +#define PPB_ID_MMFR1_ID_MMFR1_Msk (0xffffffffUL) /*!< ID_MMFR1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ID_MMFR2 ======================================================== */ +#define PPB_ID_MMFR2_WFISTALL_Pos (24UL) /*!< WFISTALL (Bit 24) */ +#define PPB_ID_MMFR2_WFISTALL_Msk (0xf000000UL) /*!< WFISTALL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ID_MMFR3 ======================================================== */ +#define PPB_ID_MMFR3_BPMAINT_Pos (8UL) /*!< BPMAINT (Bit 8) */ +#define PPB_ID_MMFR3_BPMAINT_Msk (0xf00UL) /*!< BPMAINT (Bitfield-Mask: 0x0f) */ +#define PPB_ID_MMFR3_CMAINTSW_Pos (4UL) /*!< CMAINTSW (Bit 4) */ +#define PPB_ID_MMFR3_CMAINTSW_Msk (0xf0UL) /*!< CMAINTSW (Bitfield-Mask: 0x0f) */ +#define PPB_ID_MMFR3_CMAINTVA_Pos (0UL) /*!< CMAINTVA (Bit 0) */ +#define PPB_ID_MMFR3_CMAINTVA_Msk (0xfUL) /*!< CMAINTVA (Bitfield-Mask: 0x0f) */ +/* ======================================================= ID_ISAR0 ======================================================== */ +#define PPB_ID_ISAR0_DIVIDE_Pos (24UL) /*!< DIVIDE (Bit 24) */ +#define PPB_ID_ISAR0_DIVIDE_Msk (0xf000000UL) /*!< DIVIDE (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR0_DEBUG_Pos (20UL) /*!< DEBUG (Bit 20) */ +#define PPB_ID_ISAR0_DEBUG_Msk (0xf00000UL) /*!< DEBUG (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR0_COPROC_Pos (16UL) /*!< COPROC (Bit 16) */ +#define PPB_ID_ISAR0_COPROC_Msk (0xf0000UL) /*!< COPROC (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR0_CMPBRANCH_Pos (12UL) /*!< CMPBRANCH (Bit 12) */ +#define PPB_ID_ISAR0_CMPBRANCH_Msk (0xf000UL) /*!< CMPBRANCH (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR0_BITFIELD_Pos (8UL) /*!< BITFIELD (Bit 8) */ +#define PPB_ID_ISAR0_BITFIELD_Msk (0xf00UL) /*!< BITFIELD (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR0_BITCOUNT_Pos (4UL) /*!< BITCOUNT (Bit 4) */ +#define PPB_ID_ISAR0_BITCOUNT_Msk (0xf0UL) /*!< BITCOUNT (Bitfield-Mask: 0x0f) */ +/* ======================================================= ID_ISAR1 ======================================================== */ +#define PPB_ID_ISAR1_INTERWORK_Pos (24UL) /*!< INTERWORK (Bit 24) */ +#define PPB_ID_ISAR1_INTERWORK_Msk (0xf000000UL) /*!< INTERWORK (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR1_IMMEDIATE_Pos (20UL) /*!< IMMEDIATE (Bit 20) */ +#define PPB_ID_ISAR1_IMMEDIATE_Msk (0xf00000UL) /*!< IMMEDIATE (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR1_IFTHEN_Pos (16UL) /*!< IFTHEN (Bit 16) */ +#define PPB_ID_ISAR1_IFTHEN_Msk (0xf0000UL) /*!< IFTHEN (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR1_EXTEND_Pos (12UL) /*!< EXTEND (Bit 12) */ +#define PPB_ID_ISAR1_EXTEND_Msk (0xf000UL) /*!< EXTEND (Bitfield-Mask: 0x0f) */ +/* ======================================================= ID_ISAR2 ======================================================== */ +#define PPB_ID_ISAR2_REVERSAL_Pos (28UL) /*!< REVERSAL (Bit 28) */ +#define PPB_ID_ISAR2_REVERSAL_Msk (0xf0000000UL) /*!< REVERSAL (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR2_MULTU_Pos (20UL) /*!< MULTU (Bit 20) */ +#define PPB_ID_ISAR2_MULTU_Msk (0xf00000UL) /*!< MULTU (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR2_MULTS_Pos (16UL) /*!< MULTS (Bit 16) */ +#define PPB_ID_ISAR2_MULTS_Msk (0xf0000UL) /*!< MULTS (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR2_MULT_Pos (12UL) /*!< MULT (Bit 12) */ +#define PPB_ID_ISAR2_MULT_Msk (0xf000UL) /*!< MULT (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR2_MULTIACCESSINT_Pos (8UL) /*!< MULTIACCESSINT (Bit 8) */ +#define PPB_ID_ISAR2_MULTIACCESSINT_Msk (0xf00UL) /*!< MULTIACCESSINT (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR2_MEMHINT_Pos (4UL) /*!< MEMHINT (Bit 4) */ +#define PPB_ID_ISAR2_MEMHINT_Msk (0xf0UL) /*!< MEMHINT (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR2_LOADSTORE_Pos (0UL) /*!< LOADSTORE (Bit 0) */ +#define PPB_ID_ISAR2_LOADSTORE_Msk (0xfUL) /*!< LOADSTORE (Bitfield-Mask: 0x0f) */ +/* ======================================================= ID_ISAR3 ======================================================== */ +#define PPB_ID_ISAR3_TRUENOP_Pos (24UL) /*!< TRUENOP (Bit 24) */ +#define PPB_ID_ISAR3_TRUENOP_Msk (0xf000000UL) /*!< TRUENOP (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR3_T32COPY_Pos (20UL) /*!< T32COPY (Bit 20) */ +#define PPB_ID_ISAR3_T32COPY_Msk (0xf00000UL) /*!< T32COPY (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR3_TABBRANCH_Pos (16UL) /*!< TABBRANCH (Bit 16) */ +#define PPB_ID_ISAR3_TABBRANCH_Msk (0xf0000UL) /*!< TABBRANCH (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR3_SYNCHPRIM_Pos (12UL) /*!< SYNCHPRIM (Bit 12) */ +#define PPB_ID_ISAR3_SYNCHPRIM_Msk (0xf000UL) /*!< SYNCHPRIM (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR3_SVC_Pos (8UL) /*!< SVC (Bit 8) */ +#define PPB_ID_ISAR3_SVC_Msk (0xf00UL) /*!< SVC (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR3_SIMD_Pos (4UL) /*!< SIMD (Bit 4) */ +#define PPB_ID_ISAR3_SIMD_Msk (0xf0UL) /*!< SIMD (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR3_SATURATE_Pos (0UL) /*!< SATURATE (Bit 0) */ +#define PPB_ID_ISAR3_SATURATE_Msk (0xfUL) /*!< SATURATE (Bitfield-Mask: 0x0f) */ +/* ======================================================= ID_ISAR4 ======================================================== */ +#define PPB_ID_ISAR4_PSR_M_Pos (24UL) /*!< PSR_M (Bit 24) */ +#define PPB_ID_ISAR4_PSR_M_Msk (0xf000000UL) /*!< PSR_M (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR4_SYNCPRIM_FRAC_Pos (20UL) /*!< SYNCPRIM_FRAC (Bit 20) */ +#define PPB_ID_ISAR4_SYNCPRIM_FRAC_Msk (0xf00000UL) /*!< SYNCPRIM_FRAC (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR4_BARRIER_Pos (16UL) /*!< BARRIER (Bit 16) */ +#define PPB_ID_ISAR4_BARRIER_Msk (0xf0000UL) /*!< BARRIER (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR4_WRITEBACK_Pos (8UL) /*!< WRITEBACK (Bit 8) */ +#define PPB_ID_ISAR4_WRITEBACK_Msk (0xf00UL) /*!< WRITEBACK (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR4_WITHSHIFTS_Pos (4UL) /*!< WITHSHIFTS (Bit 4) */ +#define PPB_ID_ISAR4_WITHSHIFTS_Msk (0xf0UL) /*!< WITHSHIFTS (Bitfield-Mask: 0x0f) */ +#define PPB_ID_ISAR4_UNPRIV_Pos (0UL) /*!< UNPRIV (Bit 0) */ +#define PPB_ID_ISAR4_UNPRIV_Msk (0xfUL) /*!< UNPRIV (Bitfield-Mask: 0x0f) */ +/* ======================================================= ID_ISAR5 ======================================================== */ +#define PPB_ID_ISAR5_ID_ISAR5_Pos (0UL) /*!< ID_ISAR5 (Bit 0) */ +#define PPB_ID_ISAR5_ID_ISAR5_Msk (0xffffffffUL) /*!< ID_ISAR5 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== CTR ========================================================== */ +#define PPB_CTR_RES1_Pos (31UL) /*!< RES1 (Bit 31) */ +#define PPB_CTR_RES1_Msk (0x80000000UL) /*!< RES1 (Bitfield-Mask: 0x01) */ +#define PPB_CTR_CWG_Pos (24UL) /*!< CWG (Bit 24) */ +#define PPB_CTR_CWG_Msk (0xf000000UL) /*!< CWG (Bitfield-Mask: 0x0f) */ +#define PPB_CTR_ERG_Pos (20UL) /*!< ERG (Bit 20) */ +#define PPB_CTR_ERG_Msk (0xf00000UL) /*!< ERG (Bitfield-Mask: 0x0f) */ +#define PPB_CTR_DMINLINE_Pos (16UL) /*!< DMINLINE (Bit 16) */ +#define PPB_CTR_DMINLINE_Msk (0xf0000UL) /*!< DMINLINE (Bitfield-Mask: 0x0f) */ +#define PPB_CTR_RES1_1_Pos (14UL) /*!< RES1_1 (Bit 14) */ +#define PPB_CTR_RES1_1_Msk (0xc000UL) /*!< RES1_1 (Bitfield-Mask: 0x03) */ +#define PPB_CTR_IMINLINE_Pos (0UL) /*!< IMINLINE (Bit 0) */ +#define PPB_CTR_IMINLINE_Msk (0xfUL) /*!< IMINLINE (Bitfield-Mask: 0x0f) */ +/* ========================================================= CPACR ========================================================= */ +#define PPB_CPACR_CP11_Pos (22UL) /*!< CP11 (Bit 22) */ +#define PPB_CPACR_CP11_Msk (0xc00000UL) /*!< CP11 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP10_Pos (20UL) /*!< CP10 (Bit 20) */ +#define PPB_CPACR_CP10_Msk (0x300000UL) /*!< CP10 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP7_Pos (14UL) /*!< CP7 (Bit 14) */ +#define PPB_CPACR_CP7_Msk (0xc000UL) /*!< CP7 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP6_Pos (12UL) /*!< CP6 (Bit 12) */ +#define PPB_CPACR_CP6_Msk (0x3000UL) /*!< CP6 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP5_Pos (10UL) /*!< CP5 (Bit 10) */ +#define PPB_CPACR_CP5_Msk (0xc00UL) /*!< CP5 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP4_Pos (8UL) /*!< CP4 (Bit 8) */ +#define PPB_CPACR_CP4_Msk (0x300UL) /*!< CP4 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP3_Pos (6UL) /*!< CP3 (Bit 6) */ +#define PPB_CPACR_CP3_Msk (0xc0UL) /*!< CP3 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP2_Pos (4UL) /*!< CP2 (Bit 4) */ +#define PPB_CPACR_CP2_Msk (0x30UL) /*!< CP2 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP1_Pos (2UL) /*!< CP1 (Bit 2) */ +#define PPB_CPACR_CP1_Msk (0xcUL) /*!< CP1 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP0_Pos (0UL) /*!< CP0 (Bit 0) */ +#define PPB_CPACR_CP0_Msk (0x3UL) /*!< CP0 (Bitfield-Mask: 0x03) */ +/* ========================================================= NSACR ========================================================= */ +#define PPB_NSACR_CP11_Pos (11UL) /*!< CP11 (Bit 11) */ +#define PPB_NSACR_CP11_Msk (0x800UL) /*!< CP11 (Bitfield-Mask: 0x01) */ +#define PPB_NSACR_CP10_Pos (10UL) /*!< CP10 (Bit 10) */ +#define PPB_NSACR_CP10_Msk (0x400UL) /*!< CP10 (Bitfield-Mask: 0x01) */ +#define PPB_NSACR_CP7_Pos (7UL) /*!< CP7 (Bit 7) */ +#define PPB_NSACR_CP7_Msk (0x80UL) /*!< CP7 (Bitfield-Mask: 0x01) */ +#define PPB_NSACR_CP6_Pos (6UL) /*!< CP6 (Bit 6) */ +#define PPB_NSACR_CP6_Msk (0x40UL) /*!< CP6 (Bitfield-Mask: 0x01) */ +#define PPB_NSACR_CP5_Pos (5UL) /*!< CP5 (Bit 5) */ +#define PPB_NSACR_CP5_Msk (0x20UL) /*!< CP5 (Bitfield-Mask: 0x01) */ +#define PPB_NSACR_CP4_Pos (4UL) /*!< CP4 (Bit 4) */ +#define PPB_NSACR_CP4_Msk (0x10UL) /*!< CP4 (Bitfield-Mask: 0x01) */ +#define PPB_NSACR_CP3_Pos (3UL) /*!< CP3 (Bit 3) */ +#define PPB_NSACR_CP3_Msk (0x8UL) /*!< CP3 (Bitfield-Mask: 0x01) */ +#define PPB_NSACR_CP2_Pos (2UL) /*!< CP2 (Bit 2) */ +#define PPB_NSACR_CP2_Msk (0x4UL) /*!< CP2 (Bitfield-Mask: 0x01) */ +#define PPB_NSACR_CP1_Pos (1UL) /*!< CP1 (Bit 1) */ +#define PPB_NSACR_CP1_Msk (0x2UL) /*!< CP1 (Bitfield-Mask: 0x01) */ +#define PPB_NSACR_CP0_Pos (0UL) /*!< CP0 (Bit 0) */ +#define PPB_NSACR_CP0_Msk (0x1UL) /*!< CP0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_TYPE ======================================================== */ +#define PPB_MPU_TYPE_DREGION_Pos (8UL) /*!< DREGION (Bit 8) */ +#define PPB_MPU_TYPE_DREGION_Msk (0xff00UL) /*!< DREGION (Bitfield-Mask: 0xff) */ +#define PPB_MPU_TYPE_SEPARATE_Pos (0UL) /*!< SEPARATE (Bit 0) */ +#define PPB_MPU_TYPE_SEPARATE_Msk (0x1UL) /*!< SEPARATE (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_CTRL ======================================================== */ +#define PPB_MPU_CTRL_PRIVDEFENA_Pos (2UL) /*!< PRIVDEFENA (Bit 2) */ +#define PPB_MPU_CTRL_PRIVDEFENA_Msk (0x4UL) /*!< PRIVDEFENA (Bitfield-Mask: 0x01) */ +#define PPB_MPU_CTRL_HFNMIENA_Pos (1UL) /*!< HFNMIENA (Bit 1) */ +#define PPB_MPU_CTRL_HFNMIENA_Msk (0x2UL) /*!< HFNMIENA (Bitfield-Mask: 0x01) */ +#define PPB_MPU_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define PPB_MPU_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== MPU_RNR ======================================================== */ +#define PPB_MPU_RNR_REGION_Pos (0UL) /*!< REGION (Bit 0) */ +#define PPB_MPU_RNR_REGION_Msk (0x7UL) /*!< REGION (Bitfield-Mask: 0x07) */ +/* ======================================================= MPU_RBAR ======================================================== */ +#define PPB_MPU_RBAR_BASE_Pos (5UL) /*!< BASE (Bit 5) */ +#define PPB_MPU_RBAR_BASE_Msk (0xffffffe0UL) /*!< BASE (Bitfield-Mask: 0x7ffffff) */ +#define PPB_MPU_RBAR_SH_Pos (3UL) /*!< SH (Bit 3) */ +#define PPB_MPU_RBAR_SH_Msk (0x18UL) /*!< SH (Bitfield-Mask: 0x03) */ +#define PPB_MPU_RBAR_AP_Pos (1UL) /*!< AP (Bit 1) */ +#define PPB_MPU_RBAR_AP_Msk (0x6UL) /*!< AP (Bitfield-Mask: 0x03) */ +#define PPB_MPU_RBAR_XN_Pos (0UL) /*!< XN (Bit 0) */ +#define PPB_MPU_RBAR_XN_Msk (0x1UL) /*!< XN (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_RLAR ======================================================== */ +#define PPB_MPU_RLAR_LIMIT_Pos (5UL) /*!< LIMIT (Bit 5) */ +#define PPB_MPU_RLAR_LIMIT_Msk (0xffffffe0UL) /*!< LIMIT (Bitfield-Mask: 0x7ffffff) */ +#define PPB_MPU_RLAR_ATTRINDX_Pos (1UL) /*!< ATTRINDX (Bit 1) */ +#define PPB_MPU_RLAR_ATTRINDX_Msk (0xeUL) /*!< ATTRINDX (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RLAR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PPB_MPU_RLAR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ====================================================== MPU_RBAR_A1 ====================================================== */ +#define PPB_MPU_RBAR_A1_BASE_Pos (5UL) /*!< BASE (Bit 5) */ +#define PPB_MPU_RBAR_A1_BASE_Msk (0xffffffe0UL) /*!< BASE (Bitfield-Mask: 0x7ffffff) */ +#define PPB_MPU_RBAR_A1_SH_Pos (3UL) /*!< SH (Bit 3) */ +#define PPB_MPU_RBAR_A1_SH_Msk (0x18UL) /*!< SH (Bitfield-Mask: 0x03) */ +#define PPB_MPU_RBAR_A1_AP_Pos (1UL) /*!< AP (Bit 1) */ +#define PPB_MPU_RBAR_A1_AP_Msk (0x6UL) /*!< AP (Bitfield-Mask: 0x03) */ +#define PPB_MPU_RBAR_A1_XN_Pos (0UL) /*!< XN (Bit 0) */ +#define PPB_MPU_RBAR_A1_XN_Msk (0x1UL) /*!< XN (Bitfield-Mask: 0x01) */ +/* ====================================================== MPU_RLAR_A1 ====================================================== */ +#define PPB_MPU_RLAR_A1_LIMIT_Pos (5UL) /*!< LIMIT (Bit 5) */ +#define PPB_MPU_RLAR_A1_LIMIT_Msk (0xffffffe0UL) /*!< LIMIT (Bitfield-Mask: 0x7ffffff) */ +#define PPB_MPU_RLAR_A1_ATTRINDX_Pos (1UL) /*!< ATTRINDX (Bit 1) */ +#define PPB_MPU_RLAR_A1_ATTRINDX_Msk (0xeUL) /*!< ATTRINDX (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RLAR_A1_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PPB_MPU_RLAR_A1_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ====================================================== MPU_RBAR_A2 ====================================================== */ +#define PPB_MPU_RBAR_A2_BASE_Pos (5UL) /*!< BASE (Bit 5) */ +#define PPB_MPU_RBAR_A2_BASE_Msk (0xffffffe0UL) /*!< BASE (Bitfield-Mask: 0x7ffffff) */ +#define PPB_MPU_RBAR_A2_SH_Pos (3UL) /*!< SH (Bit 3) */ +#define PPB_MPU_RBAR_A2_SH_Msk (0x18UL) /*!< SH (Bitfield-Mask: 0x03) */ +#define PPB_MPU_RBAR_A2_AP_Pos (1UL) /*!< AP (Bit 1) */ +#define PPB_MPU_RBAR_A2_AP_Msk (0x6UL) /*!< AP (Bitfield-Mask: 0x03) */ +#define PPB_MPU_RBAR_A2_XN_Pos (0UL) /*!< XN (Bit 0) */ +#define PPB_MPU_RBAR_A2_XN_Msk (0x1UL) /*!< XN (Bitfield-Mask: 0x01) */ +/* ====================================================== MPU_RLAR_A2 ====================================================== */ +#define PPB_MPU_RLAR_A2_LIMIT_Pos (5UL) /*!< LIMIT (Bit 5) */ +#define PPB_MPU_RLAR_A2_LIMIT_Msk (0xffffffe0UL) /*!< LIMIT (Bitfield-Mask: 0x7ffffff) */ +#define PPB_MPU_RLAR_A2_ATTRINDX_Pos (1UL) /*!< ATTRINDX (Bit 1) */ +#define PPB_MPU_RLAR_A2_ATTRINDX_Msk (0xeUL) /*!< ATTRINDX (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RLAR_A2_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PPB_MPU_RLAR_A2_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ====================================================== MPU_RBAR_A3 ====================================================== */ +#define PPB_MPU_RBAR_A3_BASE_Pos (5UL) /*!< BASE (Bit 5) */ +#define PPB_MPU_RBAR_A3_BASE_Msk (0xffffffe0UL) /*!< BASE (Bitfield-Mask: 0x7ffffff) */ +#define PPB_MPU_RBAR_A3_SH_Pos (3UL) /*!< SH (Bit 3) */ +#define PPB_MPU_RBAR_A3_SH_Msk (0x18UL) /*!< SH (Bitfield-Mask: 0x03) */ +#define PPB_MPU_RBAR_A3_AP_Pos (1UL) /*!< AP (Bit 1) */ +#define PPB_MPU_RBAR_A3_AP_Msk (0x6UL) /*!< AP (Bitfield-Mask: 0x03) */ +#define PPB_MPU_RBAR_A3_XN_Pos (0UL) /*!< XN (Bit 0) */ +#define PPB_MPU_RBAR_A3_XN_Msk (0x1UL) /*!< XN (Bitfield-Mask: 0x01) */ +/* ====================================================== MPU_RLAR_A3 ====================================================== */ +#define PPB_MPU_RLAR_A3_LIMIT_Pos (5UL) /*!< LIMIT (Bit 5) */ +#define PPB_MPU_RLAR_A3_LIMIT_Msk (0xffffffe0UL) /*!< LIMIT (Bitfield-Mask: 0x7ffffff) */ +#define PPB_MPU_RLAR_A3_ATTRINDX_Pos (1UL) /*!< ATTRINDX (Bit 1) */ +#define PPB_MPU_RLAR_A3_ATTRINDX_Msk (0xeUL) /*!< ATTRINDX (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RLAR_A3_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PPB_MPU_RLAR_A3_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_MAIR0 ======================================================= */ +#define PPB_MPU_MAIR0_ATTR3_Pos (24UL) /*!< ATTR3 (Bit 24) */ +#define PPB_MPU_MAIR0_ATTR3_Msk (0xff000000UL) /*!< ATTR3 (Bitfield-Mask: 0xff) */ +#define PPB_MPU_MAIR0_ATTR2_Pos (16UL) /*!< ATTR2 (Bit 16) */ +#define PPB_MPU_MAIR0_ATTR2_Msk (0xff0000UL) /*!< ATTR2 (Bitfield-Mask: 0xff) */ +#define PPB_MPU_MAIR0_ATTR1_Pos (8UL) /*!< ATTR1 (Bit 8) */ +#define PPB_MPU_MAIR0_ATTR1_Msk (0xff00UL) /*!< ATTR1 (Bitfield-Mask: 0xff) */ +#define PPB_MPU_MAIR0_ATTR0_Pos (0UL) /*!< ATTR0 (Bit 0) */ +#define PPB_MPU_MAIR0_ATTR0_Msk (0xffUL) /*!< ATTR0 (Bitfield-Mask: 0xff) */ +/* ======================================================= MPU_MAIR1 ======================================================= */ +#define PPB_MPU_MAIR1_ATTR7_Pos (24UL) /*!< ATTR7 (Bit 24) */ +#define PPB_MPU_MAIR1_ATTR7_Msk (0xff000000UL) /*!< ATTR7 (Bitfield-Mask: 0xff) */ +#define PPB_MPU_MAIR1_ATTR6_Pos (16UL) /*!< ATTR6 (Bit 16) */ +#define PPB_MPU_MAIR1_ATTR6_Msk (0xff0000UL) /*!< ATTR6 (Bitfield-Mask: 0xff) */ +#define PPB_MPU_MAIR1_ATTR5_Pos (8UL) /*!< ATTR5 (Bit 8) */ +#define PPB_MPU_MAIR1_ATTR5_Msk (0xff00UL) /*!< ATTR5 (Bitfield-Mask: 0xff) */ +#define PPB_MPU_MAIR1_ATTR4_Pos (0UL) /*!< ATTR4 (Bit 0) */ +#define PPB_MPU_MAIR1_ATTR4_Msk (0xffUL) /*!< ATTR4 (Bitfield-Mask: 0xff) */ +/* ======================================================= SAU_CTRL ======================================================== */ +#define PPB_SAU_CTRL_ALLNS_Pos (1UL) /*!< ALLNS (Bit 1) */ +#define PPB_SAU_CTRL_ALLNS_Msk (0x2UL) /*!< ALLNS (Bitfield-Mask: 0x01) */ +#define PPB_SAU_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define PPB_SAU_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= SAU_TYPE ======================================================== */ +#define PPB_SAU_TYPE_SREGION_Pos (0UL) /*!< SREGION (Bit 0) */ +#define PPB_SAU_TYPE_SREGION_Msk (0xffUL) /*!< SREGION (Bitfield-Mask: 0xff) */ +/* ======================================================== SAU_RNR ======================================================== */ +#define PPB_SAU_RNR_REGION_Pos (0UL) /*!< REGION (Bit 0) */ +#define PPB_SAU_RNR_REGION_Msk (0xffUL) /*!< REGION (Bitfield-Mask: 0xff) */ +/* ======================================================= SAU_RBAR ======================================================== */ +#define PPB_SAU_RBAR_BADDR_Pos (5UL) /*!< BADDR (Bit 5) */ +#define PPB_SAU_RBAR_BADDR_Msk (0xffffffe0UL) /*!< BADDR (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= SAU_RLAR ======================================================== */ +#define PPB_SAU_RLAR_LADDR_Pos (5UL) /*!< LADDR (Bit 5) */ +#define PPB_SAU_RLAR_LADDR_Msk (0xffffffe0UL) /*!< LADDR (Bitfield-Mask: 0x7ffffff) */ +#define PPB_SAU_RLAR_NSC_Pos (1UL) /*!< NSC (Bit 1) */ +#define PPB_SAU_RLAR_NSC_Msk (0x2UL) /*!< NSC (Bitfield-Mask: 0x01) */ +#define PPB_SAU_RLAR_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define PPB_SAU_RLAR_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= SFSR ========================================================== */ +#define PPB_SFSR_LSERR_Pos (7UL) /*!< LSERR (Bit 7) */ +#define PPB_SFSR_LSERR_Msk (0x80UL) /*!< LSERR (Bitfield-Mask: 0x01) */ +#define PPB_SFSR_SFARVALID_Pos (6UL) /*!< SFARVALID (Bit 6) */ +#define PPB_SFSR_SFARVALID_Msk (0x40UL) /*!< SFARVALID (Bitfield-Mask: 0x01) */ +#define PPB_SFSR_LSPERR_Pos (5UL) /*!< LSPERR (Bit 5) */ +#define PPB_SFSR_LSPERR_Msk (0x20UL) /*!< LSPERR (Bitfield-Mask: 0x01) */ +#define PPB_SFSR_INVTRAN_Pos (4UL) /*!< INVTRAN (Bit 4) */ +#define PPB_SFSR_INVTRAN_Msk (0x10UL) /*!< INVTRAN (Bitfield-Mask: 0x01) */ +#define PPB_SFSR_AUVIOL_Pos (3UL) /*!< AUVIOL (Bit 3) */ +#define PPB_SFSR_AUVIOL_Msk (0x8UL) /*!< AUVIOL (Bitfield-Mask: 0x01) */ +#define PPB_SFSR_INVER_Pos (2UL) /*!< INVER (Bit 2) */ +#define PPB_SFSR_INVER_Msk (0x4UL) /*!< INVER (Bitfield-Mask: 0x01) */ +#define PPB_SFSR_INVIS_Pos (1UL) /*!< INVIS (Bit 1) */ +#define PPB_SFSR_INVIS_Msk (0x2UL) /*!< INVIS (Bitfield-Mask: 0x01) */ +#define PPB_SFSR_INVEP_Pos (0UL) /*!< INVEP (Bit 0) */ +#define PPB_SFSR_INVEP_Msk (0x1UL) /*!< INVEP (Bitfield-Mask: 0x01) */ +/* ========================================================= SFAR ========================================================== */ +#define PPB_SFAR_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define PPB_SFAR_ADDRESS_Msk (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DHCSR ========================================================= */ +#define PPB_DHCSR_S_RESTART_ST_Pos (26UL) /*!< S_RESTART_ST (Bit 26) */ +#define PPB_DHCSR_S_RESTART_ST_Msk (0x4000000UL) /*!< S_RESTART_ST (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_S_RESET_ST_Pos (25UL) /*!< S_RESET_ST (Bit 25) */ +#define PPB_DHCSR_S_RESET_ST_Msk (0x2000000UL) /*!< S_RESET_ST (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_S_RETIRE_ST_Pos (24UL) /*!< S_RETIRE_ST (Bit 24) */ +#define PPB_DHCSR_S_RETIRE_ST_Msk (0x1000000UL) /*!< S_RETIRE_ST (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_S_SDE_Pos (20UL) /*!< S_SDE (Bit 20) */ +#define PPB_DHCSR_S_SDE_Msk (0x100000UL) /*!< S_SDE (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_S_LOCKUP_Pos (19UL) /*!< S_LOCKUP (Bit 19) */ +#define PPB_DHCSR_S_LOCKUP_Msk (0x80000UL) /*!< S_LOCKUP (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_S_SLEEP_Pos (18UL) /*!< S_SLEEP (Bit 18) */ +#define PPB_DHCSR_S_SLEEP_Msk (0x40000UL) /*!< S_SLEEP (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_S_HALT_Pos (17UL) /*!< S_HALT (Bit 17) */ +#define PPB_DHCSR_S_HALT_Msk (0x20000UL) /*!< S_HALT (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_S_REGRDY_Pos (16UL) /*!< S_REGRDY (Bit 16) */ +#define PPB_DHCSR_S_REGRDY_Msk (0x10000UL) /*!< S_REGRDY (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_C_SNAPSTALL_Pos (5UL) /*!< C_SNAPSTALL (Bit 5) */ +#define PPB_DHCSR_C_SNAPSTALL_Msk (0x20UL) /*!< C_SNAPSTALL (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_C_MASKINTS_Pos (3UL) /*!< C_MASKINTS (Bit 3) */ +#define PPB_DHCSR_C_MASKINTS_Msk (0x8UL) /*!< C_MASKINTS (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_C_STEP_Pos (2UL) /*!< C_STEP (Bit 2) */ +#define PPB_DHCSR_C_STEP_Msk (0x4UL) /*!< C_STEP (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_C_HALT_Pos (1UL) /*!< C_HALT (Bit 1) */ +#define PPB_DHCSR_C_HALT_Msk (0x2UL) /*!< C_HALT (Bitfield-Mask: 0x01) */ +#define PPB_DHCSR_C_DEBUGEN_Pos (0UL) /*!< C_DEBUGEN (Bit 0) */ +#define PPB_DHCSR_C_DEBUGEN_Msk (0x1UL) /*!< C_DEBUGEN (Bitfield-Mask: 0x01) */ +/* ========================================================= DCRSR ========================================================= */ +#define PPB_DCRSR_REGWNR_Pos (16UL) /*!< REGWNR (Bit 16) */ +#define PPB_DCRSR_REGWNR_Msk (0x10000UL) /*!< REGWNR (Bitfield-Mask: 0x01) */ +#define PPB_DCRSR_REGSEL_Pos (0UL) /*!< REGSEL (Bit 0) */ +#define PPB_DCRSR_REGSEL_Msk (0x7fUL) /*!< REGSEL (Bitfield-Mask: 0x7f) */ +/* ========================================================= DCRDR ========================================================= */ +#define PPB_DCRDR_DBGTMP_Pos (0UL) /*!< DBGTMP (Bit 0) */ +#define PPB_DCRDR_DBGTMP_Msk (0xffffffffUL) /*!< DBGTMP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DEMCR ========================================================= */ +#define PPB_DEMCR_TRCENA_Pos (24UL) /*!< TRCENA (Bit 24) */ +#define PPB_DEMCR_TRCENA_Msk (0x1000000UL) /*!< TRCENA (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_SDME_Pos (20UL) /*!< SDME (Bit 20) */ +#define PPB_DEMCR_SDME_Msk (0x100000UL) /*!< SDME (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_MON_REQ_Pos (19UL) /*!< MON_REQ (Bit 19) */ +#define PPB_DEMCR_MON_REQ_Msk (0x80000UL) /*!< MON_REQ (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_MON_STEP_Pos (18UL) /*!< MON_STEP (Bit 18) */ +#define PPB_DEMCR_MON_STEP_Msk (0x40000UL) /*!< MON_STEP (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_MON_PEND_Pos (17UL) /*!< MON_PEND (Bit 17) */ +#define PPB_DEMCR_MON_PEND_Msk (0x20000UL) /*!< MON_PEND (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_MON_EN_Pos (16UL) /*!< MON_EN (Bit 16) */ +#define PPB_DEMCR_MON_EN_Msk (0x10000UL) /*!< MON_EN (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_VC_SFERR_Pos (11UL) /*!< VC_SFERR (Bit 11) */ +#define PPB_DEMCR_VC_SFERR_Msk (0x800UL) /*!< VC_SFERR (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_VC_HARDERR_Pos (10UL) /*!< VC_HARDERR (Bit 10) */ +#define PPB_DEMCR_VC_HARDERR_Msk (0x400UL) /*!< VC_HARDERR (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_VC_INTERR_Pos (9UL) /*!< VC_INTERR (Bit 9) */ +#define PPB_DEMCR_VC_INTERR_Msk (0x200UL) /*!< VC_INTERR (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_VC_BUSERR_Pos (8UL) /*!< VC_BUSERR (Bit 8) */ +#define PPB_DEMCR_VC_BUSERR_Msk (0x100UL) /*!< VC_BUSERR (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_VC_STATERR_Pos (7UL) /*!< VC_STATERR (Bit 7) */ +#define PPB_DEMCR_VC_STATERR_Msk (0x80UL) /*!< VC_STATERR (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_VC_CHKERR_Pos (6UL) /*!< VC_CHKERR (Bit 6) */ +#define PPB_DEMCR_VC_CHKERR_Msk (0x40UL) /*!< VC_CHKERR (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_VC_NOCPERR_Pos (5UL) /*!< VC_NOCPERR (Bit 5) */ +#define PPB_DEMCR_VC_NOCPERR_Msk (0x20UL) /*!< VC_NOCPERR (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_VC_MMERR_Pos (4UL) /*!< VC_MMERR (Bit 4) */ +#define PPB_DEMCR_VC_MMERR_Msk (0x10UL) /*!< VC_MMERR (Bitfield-Mask: 0x01) */ +#define PPB_DEMCR_VC_CORERESET_Pos (0UL) /*!< VC_CORERESET (Bit 0) */ +#define PPB_DEMCR_VC_CORERESET_Msk (0x1UL) /*!< VC_CORERESET (Bitfield-Mask: 0x01) */ +/* ========================================================= DSCSR ========================================================= */ +#define PPB_DSCSR_CDSKEY_Pos (17UL) /*!< CDSKEY (Bit 17) */ +#define PPB_DSCSR_CDSKEY_Msk (0x20000UL) /*!< CDSKEY (Bitfield-Mask: 0x01) */ +#define PPB_DSCSR_CDS_Pos (16UL) /*!< CDS (Bit 16) */ +#define PPB_DSCSR_CDS_Msk (0x10000UL) /*!< CDS (Bitfield-Mask: 0x01) */ +#define PPB_DSCSR_SBRSEL_Pos (1UL) /*!< SBRSEL (Bit 1) */ +#define PPB_DSCSR_SBRSEL_Msk (0x2UL) /*!< SBRSEL (Bitfield-Mask: 0x01) */ +#define PPB_DSCSR_SBRSELEN_Pos (0UL) /*!< SBRSELEN (Bit 0) */ +#define PPB_DSCSR_SBRSELEN_Msk (0x1UL) /*!< SBRSELEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STIR ========================================================== */ +#define PPB_STIR_INTID_Pos (0UL) /*!< INTID (Bit 0) */ +#define PPB_STIR_INTID_Msk (0x1ffUL) /*!< INTID (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FPCCR ========================================================= */ +#define PPB_FPCCR_ASPEN_Pos (31UL) /*!< ASPEN (Bit 31) */ +#define PPB_FPCCR_ASPEN_Msk (0x80000000UL) /*!< ASPEN (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_LSPEN_Pos (30UL) /*!< LSPEN (Bit 30) */ +#define PPB_FPCCR_LSPEN_Msk (0x40000000UL) /*!< LSPEN (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_LSPENS_Pos (29UL) /*!< LSPENS (Bit 29) */ +#define PPB_FPCCR_LSPENS_Msk (0x20000000UL) /*!< LSPENS (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_CLRONRET_Pos (28UL) /*!< CLRONRET (Bit 28) */ +#define PPB_FPCCR_CLRONRET_Msk (0x10000000UL) /*!< CLRONRET (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_CLRONRETS_Pos (27UL) /*!< CLRONRETS (Bit 27) */ +#define PPB_FPCCR_CLRONRETS_Msk (0x8000000UL) /*!< CLRONRETS (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_TS_Pos (26UL) /*!< TS (Bit 26) */ +#define PPB_FPCCR_TS_Msk (0x4000000UL) /*!< TS (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_UFRDY_Pos (10UL) /*!< UFRDY (Bit 10) */ +#define PPB_FPCCR_UFRDY_Msk (0x400UL) /*!< UFRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_SPLIMVIOL_Pos (9UL) /*!< SPLIMVIOL (Bit 9) */ +#define PPB_FPCCR_SPLIMVIOL_Msk (0x200UL) /*!< SPLIMVIOL (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_MONRDY_Pos (8UL) /*!< MONRDY (Bit 8) */ +#define PPB_FPCCR_MONRDY_Msk (0x100UL) /*!< MONRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_SFRDY_Pos (7UL) /*!< SFRDY (Bit 7) */ +#define PPB_FPCCR_SFRDY_Msk (0x80UL) /*!< SFRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_BFRDY_Pos (6UL) /*!< BFRDY (Bit 6) */ +#define PPB_FPCCR_BFRDY_Msk (0x40UL) /*!< BFRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_MMRDY_Pos (5UL) /*!< MMRDY (Bit 5) */ +#define PPB_FPCCR_MMRDY_Msk (0x20UL) /*!< MMRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_HFRDY_Pos (4UL) /*!< HFRDY (Bit 4) */ +#define PPB_FPCCR_HFRDY_Msk (0x10UL) /*!< HFRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_THREAD_Pos (3UL) /*!< THREAD (Bit 3) */ +#define PPB_FPCCR_THREAD_Msk (0x8UL) /*!< THREAD (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_S_Pos (2UL) /*!< S (Bit 2) */ +#define PPB_FPCCR_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_USER_Pos (1UL) /*!< USER (Bit 1) */ +#define PPB_FPCCR_USER_Msk (0x2UL) /*!< USER (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_LSPACT_Pos (0UL) /*!< LSPACT (Bit 0) */ +#define PPB_FPCCR_LSPACT_Msk (0x1UL) /*!< LSPACT (Bitfield-Mask: 0x01) */ +/* ========================================================= FPCAR ========================================================= */ +#define PPB_FPCAR_ADDRESS_Pos (3UL) /*!< ADDRESS (Bit 3) */ +#define PPB_FPCAR_ADDRESS_Msk (0xfffffff8UL) /*!< ADDRESS (Bitfield-Mask: 0x1fffffff) */ +/* ======================================================== FPDSCR ========================================================= */ +#define PPB_FPDSCR_AHP_Pos (26UL) /*!< AHP (Bit 26) */ +#define PPB_FPDSCR_AHP_Msk (0x4000000UL) /*!< AHP (Bitfield-Mask: 0x01) */ +#define PPB_FPDSCR_DN_Pos (25UL) /*!< DN (Bit 25) */ +#define PPB_FPDSCR_DN_Msk (0x2000000UL) /*!< DN (Bitfield-Mask: 0x01) */ +#define PPB_FPDSCR_FZ_Pos (24UL) /*!< FZ (Bit 24) */ +#define PPB_FPDSCR_FZ_Msk (0x1000000UL) /*!< FZ (Bitfield-Mask: 0x01) */ +#define PPB_FPDSCR_RMODE_Pos (22UL) /*!< RMODE (Bit 22) */ +#define PPB_FPDSCR_RMODE_Msk (0xc00000UL) /*!< RMODE (Bitfield-Mask: 0x03) */ +/* ========================================================= MVFR0 ========================================================= */ +#define PPB_MVFR0_FPROUND_Pos (28UL) /*!< FPROUND (Bit 28) */ +#define PPB_MVFR0_FPROUND_Msk (0xf0000000UL) /*!< FPROUND (Bitfield-Mask: 0x0f) */ +#define PPB_MVFR0_FPSQRT_Pos (20UL) /*!< FPSQRT (Bit 20) */ +#define PPB_MVFR0_FPSQRT_Msk (0xf00000UL) /*!< FPSQRT (Bitfield-Mask: 0x0f) */ +#define PPB_MVFR0_FPDIVIDE_Pos (16UL) /*!< FPDIVIDE (Bit 16) */ +#define PPB_MVFR0_FPDIVIDE_Msk (0xf0000UL) /*!< FPDIVIDE (Bitfield-Mask: 0x0f) */ +#define PPB_MVFR0_FPDP_Pos (8UL) /*!< FPDP (Bit 8) */ +#define PPB_MVFR0_FPDP_Msk (0xf00UL) /*!< FPDP (Bitfield-Mask: 0x0f) */ +#define PPB_MVFR0_FPSP_Pos (4UL) /*!< FPSP (Bit 4) */ +#define PPB_MVFR0_FPSP_Msk (0xf0UL) /*!< FPSP (Bitfield-Mask: 0x0f) */ +#define PPB_MVFR0_SIMDREG_Pos (0UL) /*!< SIMDREG (Bit 0) */ +#define PPB_MVFR0_SIMDREG_Msk (0xfUL) /*!< SIMDREG (Bitfield-Mask: 0x0f) */ +/* ========================================================= MVFR1 ========================================================= */ +#define PPB_MVFR1_FMAC_Pos (28UL) /*!< FMAC (Bit 28) */ +#define PPB_MVFR1_FMAC_Msk (0xf0000000UL) /*!< FMAC (Bitfield-Mask: 0x0f) */ +#define PPB_MVFR1_FPHP_Pos (24UL) /*!< FPHP (Bit 24) */ +#define PPB_MVFR1_FPHP_Msk (0xf000000UL) /*!< FPHP (Bitfield-Mask: 0x0f) */ +#define PPB_MVFR1_FPDNAN_Pos (4UL) /*!< FPDNAN (Bit 4) */ +#define PPB_MVFR1_FPDNAN_Msk (0xf0UL) /*!< FPDNAN (Bitfield-Mask: 0x0f) */ +#define PPB_MVFR1_FPFTZ_Pos (0UL) /*!< FPFTZ (Bit 0) */ +#define PPB_MVFR1_FPFTZ_Msk (0xfUL) /*!< FPFTZ (Bitfield-Mask: 0x0f) */ +/* ========================================================= MVFR2 ========================================================= */ +#define PPB_MVFR2_FPMISC_Pos (4UL) /*!< FPMISC (Bit 4) */ +#define PPB_MVFR2_FPMISC_Msk (0xf0UL) /*!< FPMISC (Bitfield-Mask: 0x0f) */ +/* ======================================================= DDEVARCH ======================================================== */ +#define PPB_DDEVARCH_ARCHITECT_Pos (21UL) /*!< ARCHITECT (Bit 21) */ +#define PPB_DDEVARCH_ARCHITECT_Msk (0xffe00000UL) /*!< ARCHITECT (Bitfield-Mask: 0x7ff) */ +#define PPB_DDEVARCH_PRESENT_Pos (20UL) /*!< PRESENT (Bit 20) */ +#define PPB_DDEVARCH_PRESENT_Msk (0x100000UL) /*!< PRESENT (Bitfield-Mask: 0x01) */ +#define PPB_DDEVARCH_REVISION_Pos (16UL) /*!< REVISION (Bit 16) */ +#define PPB_DDEVARCH_REVISION_Msk (0xf0000UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_DDEVARCH_ARCHVER_Pos (12UL) /*!< ARCHVER (Bit 12) */ +#define PPB_DDEVARCH_ARCHVER_Msk (0xf000UL) /*!< ARCHVER (Bitfield-Mask: 0x0f) */ +#define PPB_DDEVARCH_ARCHPART_Pos (0UL) /*!< ARCHPART (Bit 0) */ +#define PPB_DDEVARCH_ARCHPART_Msk (0xfffUL) /*!< ARCHPART (Bitfield-Mask: 0xfff) */ +/* ======================================================= DDEVTYPE ======================================================== */ +#define PPB_DDEVTYPE_SUB_Pos (4UL) /*!< SUB (Bit 4) */ +#define PPB_DDEVTYPE_SUB_Msk (0xf0UL) /*!< SUB (Bitfield-Mask: 0x0f) */ +#define PPB_DDEVTYPE_MAJOR_Pos (0UL) /*!< MAJOR (Bit 0) */ +#define PPB_DDEVTYPE_MAJOR_Msk (0xfUL) /*!< MAJOR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPIDR4 ========================================================= */ +#define PPB_DPIDR4_SIZE_Pos (4UL) /*!< SIZE (Bit 4) */ +#define PPB_DPIDR4_SIZE_Msk (0xf0UL) /*!< SIZE (Bitfield-Mask: 0x0f) */ +#define PPB_DPIDR4_DES_2_Pos (0UL) /*!< DES_2 (Bit 0) */ +#define PPB_DPIDR4_DES_2_Msk (0xfUL) /*!< DES_2 (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPIDR5 ========================================================= */ +#define PPB_DPIDR5_DPIDR5_Pos (0UL) /*!< DPIDR5 (Bit 0) */ +#define PPB_DPIDR5_DPIDR5_Msk (0xffffffffUL) /*!< DPIDR5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DPIDR6 ========================================================= */ +#define PPB_DPIDR6_DPIDR6_Pos (0UL) /*!< DPIDR6 (Bit 0) */ +#define PPB_DPIDR6_DPIDR6_Msk (0xffffffffUL) /*!< DPIDR6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DPIDR7 ========================================================= */ +#define PPB_DPIDR7_DPIDR7_Pos (0UL) /*!< DPIDR7 (Bit 0) */ +#define PPB_DPIDR7_DPIDR7_Msk (0xffffffffUL) /*!< DPIDR7 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DPIDR0 ========================================================= */ +#define PPB_DPIDR0_PART_0_Pos (0UL) /*!< PART_0 (Bit 0) */ +#define PPB_DPIDR0_PART_0_Msk (0xffUL) /*!< PART_0 (Bitfield-Mask: 0xff) */ +/* ======================================================== DPIDR1 ========================================================= */ +#define PPB_DPIDR1_DES_0_Pos (4UL) /*!< DES_0 (Bit 4) */ +#define PPB_DPIDR1_DES_0_Msk (0xf0UL) /*!< DES_0 (Bitfield-Mask: 0x0f) */ +#define PPB_DPIDR1_PART_1_Pos (0UL) /*!< PART_1 (Bit 0) */ +#define PPB_DPIDR1_PART_1_Msk (0xfUL) /*!< PART_1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPIDR2 ========================================================= */ +#define PPB_DPIDR2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */ +#define PPB_DPIDR2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_DPIDR2_JEDEC_Pos (3UL) /*!< JEDEC (Bit 3) */ +#define PPB_DPIDR2_JEDEC_Msk (0x8UL) /*!< JEDEC (Bitfield-Mask: 0x01) */ +#define PPB_DPIDR2_DES_1_Pos (0UL) /*!< DES_1 (Bit 0) */ +#define PPB_DPIDR2_DES_1_Msk (0x7UL) /*!< DES_1 (Bitfield-Mask: 0x07) */ +/* ======================================================== DPIDR3 ========================================================= */ +#define PPB_DPIDR3_REVAND_Pos (4UL) /*!< REVAND (Bit 4) */ +#define PPB_DPIDR3_REVAND_Msk (0xf0UL) /*!< REVAND (Bitfield-Mask: 0x0f) */ +#define PPB_DPIDR3_CMOD_Pos (0UL) /*!< CMOD (Bit 0) */ +#define PPB_DPIDR3_CMOD_Msk (0xfUL) /*!< CMOD (Bitfield-Mask: 0x0f) */ +/* ======================================================== DCIDR0 ========================================================= */ +#define PPB_DCIDR0_PRMBL_0_Pos (0UL) /*!< PRMBL_0 (Bit 0) */ +#define PPB_DCIDR0_PRMBL_0_Msk (0xffUL) /*!< PRMBL_0 (Bitfield-Mask: 0xff) */ +/* ======================================================== DCIDR1 ========================================================= */ +#define PPB_DCIDR1_CLASS_Pos (4UL) /*!< CLASS (Bit 4) */ +#define PPB_DCIDR1_CLASS_Msk (0xf0UL) /*!< CLASS (Bitfield-Mask: 0x0f) */ +#define PPB_DCIDR1_PRMBL_1_Pos (0UL) /*!< PRMBL_1 (Bit 0) */ +#define PPB_DCIDR1_PRMBL_1_Msk (0xfUL) /*!< PRMBL_1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== DCIDR2 ========================================================= */ +#define PPB_DCIDR2_PRMBL_2_Pos (0UL) /*!< PRMBL_2 (Bit 0) */ +#define PPB_DCIDR2_PRMBL_2_Msk (0xffUL) /*!< PRMBL_2 (Bitfield-Mask: 0xff) */ +/* ======================================================== DCIDR3 ========================================================= */ +#define PPB_DCIDR3_PRMBL_3_Pos (0UL) /*!< PRMBL_3 (Bit 0) */ +#define PPB_DCIDR3_PRMBL_3_Msk (0xffUL) /*!< PRMBL_3 (Bitfield-Mask: 0xff) */ +/* ====================================================== TRCPRGCTLR ======================================================= */ +#define PPB_TRCPRGCTLR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PPB_TRCPRGCTLR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= TRCSTATR ======================================================== */ +#define PPB_TRCSTATR_PMSTABLE_Pos (1UL) /*!< PMSTABLE (Bit 1) */ +#define PPB_TRCSTATR_PMSTABLE_Msk (0x2UL) /*!< PMSTABLE (Bitfield-Mask: 0x01) */ +#define PPB_TRCSTATR_IDLE_Pos (0UL) /*!< IDLE (Bit 0) */ +#define PPB_TRCSTATR_IDLE_Msk (0x1UL) /*!< IDLE (Bitfield-Mask: 0x01) */ +/* ====================================================== TRCCONFIGR ======================================================= */ +#define PPB_TRCCONFIGR_RS_Pos (12UL) /*!< RS (Bit 12) */ +#define PPB_TRCCONFIGR_RS_Msk (0x1000UL) /*!< RS (Bitfield-Mask: 0x01) */ +#define PPB_TRCCONFIGR_TS_Pos (11UL) /*!< TS (Bit 11) */ +#define PPB_TRCCONFIGR_TS_Msk (0x800UL) /*!< TS (Bitfield-Mask: 0x01) */ +#define PPB_TRCCONFIGR_COND_Pos (5UL) /*!< COND (Bit 5) */ +#define PPB_TRCCONFIGR_COND_Msk (0x7e0UL) /*!< COND (Bitfield-Mask: 0x3f) */ +#define PPB_TRCCONFIGR_CCI_Pos (4UL) /*!< CCI (Bit 4) */ +#define PPB_TRCCONFIGR_CCI_Msk (0x10UL) /*!< CCI (Bitfield-Mask: 0x01) */ +#define PPB_TRCCONFIGR_BB_Pos (3UL) /*!< BB (Bit 3) */ +#define PPB_TRCCONFIGR_BB_Msk (0x8UL) /*!< BB (Bitfield-Mask: 0x01) */ +/* ===================================================== TRCEVENTCTL0R ===================================================== */ +#define PPB_TRCEVENTCTL0R_TYPE1_Pos (15UL) /*!< TYPE1 (Bit 15) */ +#define PPB_TRCEVENTCTL0R_TYPE1_Msk (0x8000UL) /*!< TYPE1 (Bitfield-Mask: 0x01) */ +#define PPB_TRCEVENTCTL0R_SEL1_Pos (8UL) /*!< SEL1 (Bit 8) */ +#define PPB_TRCEVENTCTL0R_SEL1_Msk (0x700UL) /*!< SEL1 (Bitfield-Mask: 0x07) */ +#define PPB_TRCEVENTCTL0R_TYPE0_Pos (7UL) /*!< TYPE0 (Bit 7) */ +#define PPB_TRCEVENTCTL0R_TYPE0_Msk (0x80UL) /*!< TYPE0 (Bitfield-Mask: 0x01) */ +#define PPB_TRCEVENTCTL0R_SEL0_Pos (0UL) /*!< SEL0 (Bit 0) */ +#define PPB_TRCEVENTCTL0R_SEL0_Msk (0x7UL) /*!< SEL0 (Bitfield-Mask: 0x07) */ +/* ===================================================== TRCEVENTCTL1R ===================================================== */ +#define PPB_TRCEVENTCTL1R_LPOVERRIDE_Pos (12UL) /*!< LPOVERRIDE (Bit 12) */ +#define PPB_TRCEVENTCTL1R_LPOVERRIDE_Msk (0x1000UL) /*!< LPOVERRIDE (Bitfield-Mask: 0x01) */ +#define PPB_TRCEVENTCTL1R_ATB_Pos (11UL) /*!< ATB (Bit 11) */ +#define PPB_TRCEVENTCTL1R_ATB_Msk (0x800UL) /*!< ATB (Bitfield-Mask: 0x01) */ +#define PPB_TRCEVENTCTL1R_INSTEN1_Pos (1UL) /*!< INSTEN1 (Bit 1) */ +#define PPB_TRCEVENTCTL1R_INSTEN1_Msk (0x2UL) /*!< INSTEN1 (Bitfield-Mask: 0x01) */ +#define PPB_TRCEVENTCTL1R_INSTEN0_Pos (0UL) /*!< INSTEN0 (Bit 0) */ +#define PPB_TRCEVENTCTL1R_INSTEN0_Msk (0x1UL) /*!< INSTEN0 (Bitfield-Mask: 0x01) */ +/* ===================================================== TRCSTALLCTLR ====================================================== */ +#define PPB_TRCSTALLCTLR_INSTPRIORITY_Pos (10UL) /*!< INSTPRIORITY (Bit 10) */ +#define PPB_TRCSTALLCTLR_INSTPRIORITY_Msk (0x400UL) /*!< INSTPRIORITY (Bitfield-Mask: 0x01) */ +#define PPB_TRCSTALLCTLR_ISTALL_Pos (8UL) /*!< ISTALL (Bit 8) */ +#define PPB_TRCSTALLCTLR_ISTALL_Msk (0x100UL) /*!< ISTALL (Bitfield-Mask: 0x01) */ +#define PPB_TRCSTALLCTLR_LEVEL_Pos (2UL) /*!< LEVEL (Bit 2) */ +#define PPB_TRCSTALLCTLR_LEVEL_Msk (0xcUL) /*!< LEVEL (Bitfield-Mask: 0x03) */ +/* ======================================================= TRCTSCTLR ======================================================= */ +#define PPB_TRCTSCTLR_TYPE0_Pos (7UL) /*!< TYPE0 (Bit 7) */ +#define PPB_TRCTSCTLR_TYPE0_Msk (0x80UL) /*!< TYPE0 (Bitfield-Mask: 0x01) */ +#define PPB_TRCTSCTLR_SEL0_Pos (0UL) /*!< SEL0 (Bit 0) */ +#define PPB_TRCTSCTLR_SEL0_Msk (0x3UL) /*!< SEL0 (Bitfield-Mask: 0x03) */ +/* ======================================================= TRCSYNCPR ======================================================= */ +#define PPB_TRCSYNCPR_PERIOD_Pos (0UL) /*!< PERIOD (Bit 0) */ +#define PPB_TRCSYNCPR_PERIOD_Msk (0x1fUL) /*!< PERIOD (Bitfield-Mask: 0x1f) */ +/* ======================================================= TRCCCCTLR ======================================================= */ +#define PPB_TRCCCCTLR_THRESHOLD_Pos (0UL) /*!< THRESHOLD (Bit 0) */ +#define PPB_TRCCCCTLR_THRESHOLD_Msk (0xfffUL) /*!< THRESHOLD (Bitfield-Mask: 0xfff) */ +/* ======================================================= TRCVICTLR ======================================================= */ +#define PPB_TRCVICTLR_EXLEVEL_S3_Pos (19UL) /*!< EXLEVEL_S3 (Bit 19) */ +#define PPB_TRCVICTLR_EXLEVEL_S3_Msk (0x80000UL) /*!< EXLEVEL_S3 (Bitfield-Mask: 0x01) */ +#define PPB_TRCVICTLR_EXLEVEL_S0_Pos (16UL) /*!< EXLEVEL_S0 (Bit 16) */ +#define PPB_TRCVICTLR_EXLEVEL_S0_Msk (0x10000UL) /*!< EXLEVEL_S0 (Bitfield-Mask: 0x01) */ +#define PPB_TRCVICTLR_TRCERR_Pos (11UL) /*!< TRCERR (Bit 11) */ +#define PPB_TRCVICTLR_TRCERR_Msk (0x800UL) /*!< TRCERR (Bitfield-Mask: 0x01) */ +#define PPB_TRCVICTLR_TRCRESET_Pos (10UL) /*!< TRCRESET (Bit 10) */ +#define PPB_TRCVICTLR_TRCRESET_Msk (0x400UL) /*!< TRCRESET (Bitfield-Mask: 0x01) */ +#define PPB_TRCVICTLR_SSSTATUS_Pos (9UL) /*!< SSSTATUS (Bit 9) */ +#define PPB_TRCVICTLR_SSSTATUS_Msk (0x200UL) /*!< SSSTATUS (Bitfield-Mask: 0x01) */ +#define PPB_TRCVICTLR_TYPE0_Pos (7UL) /*!< TYPE0 (Bit 7) */ +#define PPB_TRCVICTLR_TYPE0_Msk (0x80UL) /*!< TYPE0 (Bitfield-Mask: 0x01) */ +#define PPB_TRCVICTLR_SEL0_Pos (0UL) /*!< SEL0 (Bit 0) */ +#define PPB_TRCVICTLR_SEL0_Msk (0x3UL) /*!< SEL0 (Bitfield-Mask: 0x03) */ +/* ===================================================== TRCCNTRLDVR0 ====================================================== */ +#define PPB_TRCCNTRLDVR0_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define PPB_TRCCNTRLDVR0_VALUE_Msk (0xffffUL) /*!< VALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== TRCIDR8 ======================================================== */ +#define PPB_TRCIDR8_MAXSPEC_Pos (0UL) /*!< MAXSPEC (Bit 0) */ +#define PPB_TRCIDR8_MAXSPEC_Msk (0xffffffffUL) /*!< MAXSPEC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TRCIDR9 ======================================================== */ +#define PPB_TRCIDR9_NUMP0KEY_Pos (0UL) /*!< NUMP0KEY (Bit 0) */ +#define PPB_TRCIDR9_NUMP0KEY_Msk (0xffffffffUL) /*!< NUMP0KEY (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TRCIDR10 ======================================================== */ +#define PPB_TRCIDR10_NUMP1KEY_Pos (0UL) /*!< NUMP1KEY (Bit 0) */ +#define PPB_TRCIDR10_NUMP1KEY_Msk (0xffffffffUL) /*!< NUMP1KEY (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TRCIDR11 ======================================================== */ +#define PPB_TRCIDR11_NUMP1SPC_Pos (0UL) /*!< NUMP1SPC (Bit 0) */ +#define PPB_TRCIDR11_NUMP1SPC_Msk (0xffffffffUL) /*!< NUMP1SPC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TRCIDR12 ======================================================== */ +#define PPB_TRCIDR12_NUMCONDKEY_Pos (0UL) /*!< NUMCONDKEY (Bit 0) */ +#define PPB_TRCIDR12_NUMCONDKEY_Msk (0xffffffffUL) /*!< NUMCONDKEY (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TRCIDR13 ======================================================== */ +#define PPB_TRCIDR13_NUMCONDSPC_Pos (0UL) /*!< NUMCONDSPC (Bit 0) */ +#define PPB_TRCIDR13_NUMCONDSPC_Msk (0xffffffffUL) /*!< NUMCONDSPC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TRCIMSPEC ======================================================= */ +#define PPB_TRCIMSPEC_SUPPORT_Pos (0UL) /*!< SUPPORT (Bit 0) */ +#define PPB_TRCIMSPEC_SUPPORT_Msk (0xfUL) /*!< SUPPORT (Bitfield-Mask: 0x0f) */ +/* ======================================================== TRCIDR0 ======================================================== */ +#define PPB_TRCIDR0_COMMOPT_Pos (29UL) /*!< COMMOPT (Bit 29) */ +#define PPB_TRCIDR0_COMMOPT_Msk (0x20000000UL) /*!< COMMOPT (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR0_TSSIZE_Pos (24UL) /*!< TSSIZE (Bit 24) */ +#define PPB_TRCIDR0_TSSIZE_Msk (0x1f000000UL) /*!< TSSIZE (Bitfield-Mask: 0x1f) */ +#define PPB_TRCIDR0_TRCEXDATA_Pos (17UL) /*!< TRCEXDATA (Bit 17) */ +#define PPB_TRCIDR0_TRCEXDATA_Msk (0x20000UL) /*!< TRCEXDATA (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR0_QSUPP_Pos (15UL) /*!< QSUPP (Bit 15) */ +#define PPB_TRCIDR0_QSUPP_Msk (0x18000UL) /*!< QSUPP (Bitfield-Mask: 0x03) */ +#define PPB_TRCIDR0_QFILT_Pos (14UL) /*!< QFILT (Bit 14) */ +#define PPB_TRCIDR0_QFILT_Msk (0x4000UL) /*!< QFILT (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR0_CONDTYPE_Pos (12UL) /*!< CONDTYPE (Bit 12) */ +#define PPB_TRCIDR0_CONDTYPE_Msk (0x3000UL) /*!< CONDTYPE (Bitfield-Mask: 0x03) */ +#define PPB_TRCIDR0_NUMEVENT_Pos (10UL) /*!< NUMEVENT (Bit 10) */ +#define PPB_TRCIDR0_NUMEVENT_Msk (0xc00UL) /*!< NUMEVENT (Bitfield-Mask: 0x03) */ +#define PPB_TRCIDR0_RETSTACK_Pos (9UL) /*!< RETSTACK (Bit 9) */ +#define PPB_TRCIDR0_RETSTACK_Msk (0x200UL) /*!< RETSTACK (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR0_TRCCCI_Pos (7UL) /*!< TRCCCI (Bit 7) */ +#define PPB_TRCIDR0_TRCCCI_Msk (0x80UL) /*!< TRCCCI (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR0_TRCCOND_Pos (6UL) /*!< TRCCOND (Bit 6) */ +#define PPB_TRCIDR0_TRCCOND_Msk (0x40UL) /*!< TRCCOND (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR0_TRCBB_Pos (5UL) /*!< TRCBB (Bit 5) */ +#define PPB_TRCIDR0_TRCBB_Msk (0x20UL) /*!< TRCBB (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR0_TRCDATA_Pos (3UL) /*!< TRCDATA (Bit 3) */ +#define PPB_TRCIDR0_TRCDATA_Msk (0x18UL) /*!< TRCDATA (Bitfield-Mask: 0x03) */ +#define PPB_TRCIDR0_INSTP0_Pos (1UL) /*!< INSTP0 (Bit 1) */ +#define PPB_TRCIDR0_INSTP0_Msk (0x6UL) /*!< INSTP0 (Bitfield-Mask: 0x03) */ +#define PPB_TRCIDR0_RES1_Pos (0UL) /*!< RES1 (Bit 0) */ +#define PPB_TRCIDR0_RES1_Msk (0x1UL) /*!< RES1 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRCIDR1 ======================================================== */ +#define PPB_TRCIDR1_DESIGNER_Pos (24UL) /*!< DESIGNER (Bit 24) */ +#define PPB_TRCIDR1_DESIGNER_Msk (0xff000000UL) /*!< DESIGNER (Bitfield-Mask: 0xff) */ +#define PPB_TRCIDR1_RES1_Pos (12UL) /*!< RES1 (Bit 12) */ +#define PPB_TRCIDR1_RES1_Msk (0xf000UL) /*!< RES1 (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR1_TRCARCHMAJ_Pos (8UL) /*!< TRCARCHMAJ (Bit 8) */ +#define PPB_TRCIDR1_TRCARCHMAJ_Msk (0xf00UL) /*!< TRCARCHMAJ (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR1_TRCARCHMIN_Pos (4UL) /*!< TRCARCHMIN (Bit 4) */ +#define PPB_TRCIDR1_TRCARCHMIN_Msk (0xf0UL) /*!< TRCARCHMIN (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR1_REVISION_Pos (0UL) /*!< REVISION (Bit 0) */ +#define PPB_TRCIDR1_REVISION_Msk (0xfUL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +/* ======================================================== TRCIDR2 ======================================================== */ +#define PPB_TRCIDR2_CCSIZE_Pos (25UL) /*!< CCSIZE (Bit 25) */ +#define PPB_TRCIDR2_CCSIZE_Msk (0x1e000000UL) /*!< CCSIZE (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR2_DVSIZE_Pos (20UL) /*!< DVSIZE (Bit 20) */ +#define PPB_TRCIDR2_DVSIZE_Msk (0x1f00000UL) /*!< DVSIZE (Bitfield-Mask: 0x1f) */ +#define PPB_TRCIDR2_DASIZE_Pos (15UL) /*!< DASIZE (Bit 15) */ +#define PPB_TRCIDR2_DASIZE_Msk (0xf8000UL) /*!< DASIZE (Bitfield-Mask: 0x1f) */ +#define PPB_TRCIDR2_VMIDSIZE_Pos (10UL) /*!< VMIDSIZE (Bit 10) */ +#define PPB_TRCIDR2_VMIDSIZE_Msk (0x7c00UL) /*!< VMIDSIZE (Bitfield-Mask: 0x1f) */ +#define PPB_TRCIDR2_CIDSIZE_Pos (5UL) /*!< CIDSIZE (Bit 5) */ +#define PPB_TRCIDR2_CIDSIZE_Msk (0x3e0UL) /*!< CIDSIZE (Bitfield-Mask: 0x1f) */ +#define PPB_TRCIDR2_IASIZE_Pos (0UL) /*!< IASIZE (Bit 0) */ +#define PPB_TRCIDR2_IASIZE_Msk (0x1fUL) /*!< IASIZE (Bitfield-Mask: 0x1f) */ +/* ======================================================== TRCIDR3 ======================================================== */ +#define PPB_TRCIDR3_NOOVERFLOW_Pos (31UL) /*!< NOOVERFLOW (Bit 31) */ +#define PPB_TRCIDR3_NOOVERFLOW_Msk (0x80000000UL) /*!< NOOVERFLOW (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR3_NUMPROC_Pos (28UL) /*!< NUMPROC (Bit 28) */ +#define PPB_TRCIDR3_NUMPROC_Msk (0x70000000UL) /*!< NUMPROC (Bitfield-Mask: 0x07) */ +#define PPB_TRCIDR3_SYSSTALL_Pos (27UL) /*!< SYSSTALL (Bit 27) */ +#define PPB_TRCIDR3_SYSSTALL_Msk (0x8000000UL) /*!< SYSSTALL (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR3_STALLCTL_Pos (26UL) /*!< STALLCTL (Bit 26) */ +#define PPB_TRCIDR3_STALLCTL_Msk (0x4000000UL) /*!< STALLCTL (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR3_SYNCPR_Pos (25UL) /*!< SYNCPR (Bit 25) */ +#define PPB_TRCIDR3_SYNCPR_Msk (0x2000000UL) /*!< SYNCPR (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR3_TRCERR_Pos (24UL) /*!< TRCERR (Bit 24) */ +#define PPB_TRCIDR3_TRCERR_Msk (0x1000000UL) /*!< TRCERR (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR3_EXLEVEL_NS_Pos (20UL) /*!< EXLEVEL_NS (Bit 20) */ +#define PPB_TRCIDR3_EXLEVEL_NS_Msk (0xf00000UL) /*!< EXLEVEL_NS (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR3_EXLEVEL_S_Pos (16UL) /*!< EXLEVEL_S (Bit 16) */ +#define PPB_TRCIDR3_EXLEVEL_S_Msk (0xf0000UL) /*!< EXLEVEL_S (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR3_CCITMIN_Pos (0UL) /*!< CCITMIN (Bit 0) */ +#define PPB_TRCIDR3_CCITMIN_Msk (0xfffUL) /*!< CCITMIN (Bitfield-Mask: 0xfff) */ +/* ======================================================== TRCIDR4 ======================================================== */ +#define PPB_TRCIDR4_NUMVMIDC_Pos (28UL) /*!< NUMVMIDC (Bit 28) */ +#define PPB_TRCIDR4_NUMVMIDC_Msk (0xf0000000UL) /*!< NUMVMIDC (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR4_NUMCIDC_Pos (24UL) /*!< NUMCIDC (Bit 24) */ +#define PPB_TRCIDR4_NUMCIDC_Msk (0xf000000UL) /*!< NUMCIDC (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR4_NUMSSCC_Pos (20UL) /*!< NUMSSCC (Bit 20) */ +#define PPB_TRCIDR4_NUMSSCC_Msk (0xf00000UL) /*!< NUMSSCC (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR4_NUMRSPAIR_Pos (16UL) /*!< NUMRSPAIR (Bit 16) */ +#define PPB_TRCIDR4_NUMRSPAIR_Msk (0xf0000UL) /*!< NUMRSPAIR (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR4_NUMPC_Pos (12UL) /*!< NUMPC (Bit 12) */ +#define PPB_TRCIDR4_NUMPC_Msk (0xf000UL) /*!< NUMPC (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR4_SUPPDAC_Pos (8UL) /*!< SUPPDAC (Bit 8) */ +#define PPB_TRCIDR4_SUPPDAC_Msk (0x100UL) /*!< SUPPDAC (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR4_NUMDVC_Pos (4UL) /*!< NUMDVC (Bit 4) */ +#define PPB_TRCIDR4_NUMDVC_Msk (0xf0UL) /*!< NUMDVC (Bitfield-Mask: 0x0f) */ +#define PPB_TRCIDR4_NUMACPAIRS_Pos (0UL) /*!< NUMACPAIRS (Bit 0) */ +#define PPB_TRCIDR4_NUMACPAIRS_Msk (0xfUL) /*!< NUMACPAIRS (Bitfield-Mask: 0x0f) */ +/* ======================================================== TRCIDR5 ======================================================== */ +#define PPB_TRCIDR5_REDFUNCNTR_Pos (31UL) /*!< REDFUNCNTR (Bit 31) */ +#define PPB_TRCIDR5_REDFUNCNTR_Msk (0x80000000UL) /*!< REDFUNCNTR (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR5_NUMCNTR_Pos (28UL) /*!< NUMCNTR (Bit 28) */ +#define PPB_TRCIDR5_NUMCNTR_Msk (0x70000000UL) /*!< NUMCNTR (Bitfield-Mask: 0x07) */ +#define PPB_TRCIDR5_NUMSEQSTATE_Pos (25UL) /*!< NUMSEQSTATE (Bit 25) */ +#define PPB_TRCIDR5_NUMSEQSTATE_Msk (0xe000000UL) /*!< NUMSEQSTATE (Bitfield-Mask: 0x07) */ +#define PPB_TRCIDR5_LPOVERRIDE_Pos (23UL) /*!< LPOVERRIDE (Bit 23) */ +#define PPB_TRCIDR5_LPOVERRIDE_Msk (0x800000UL) /*!< LPOVERRIDE (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR5_ATBTRIG_Pos (22UL) /*!< ATBTRIG (Bit 22) */ +#define PPB_TRCIDR5_ATBTRIG_Msk (0x400000UL) /*!< ATBTRIG (Bitfield-Mask: 0x01) */ +#define PPB_TRCIDR5_TRACEIDSIZE_Pos (16UL) /*!< TRACEIDSIZE (Bit 16) */ +#define PPB_TRCIDR5_TRACEIDSIZE_Msk (0x3f0000UL) /*!< TRACEIDSIZE (Bitfield-Mask: 0x3f) */ +#define PPB_TRCIDR5_NUMEXTINSEL_Pos (9UL) /*!< NUMEXTINSEL (Bit 9) */ +#define PPB_TRCIDR5_NUMEXTINSEL_Msk (0xe00UL) /*!< NUMEXTINSEL (Bitfield-Mask: 0x07) */ +#define PPB_TRCIDR5_NUMEXTIN_Pos (0UL) /*!< NUMEXTIN (Bit 0) */ +#define PPB_TRCIDR5_NUMEXTIN_Msk (0x1ffUL) /*!< NUMEXTIN (Bitfield-Mask: 0x1ff) */ +/* ======================================================== TRCIDR6 ======================================================== */ +#define PPB_TRCIDR6_TRCIDR6_Pos (0UL) /*!< TRCIDR6 (Bit 0) */ +#define PPB_TRCIDR6_TRCIDR6_Msk (0xffffffffUL) /*!< TRCIDR6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TRCIDR7 ======================================================== */ +#define PPB_TRCIDR7_TRCIDR7_Pos (0UL) /*!< TRCIDR7 (Bit 0) */ +#define PPB_TRCIDR7_TRCIDR7_Msk (0xffffffffUL) /*!< TRCIDR7 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TRCRSCTLR2 ======================================================= */ +#define PPB_TRCRSCTLR2_PAIRINV_Pos (21UL) /*!< PAIRINV (Bit 21) */ +#define PPB_TRCRSCTLR2_PAIRINV_Msk (0x200000UL) /*!< PAIRINV (Bitfield-Mask: 0x01) */ +#define PPB_TRCRSCTLR2_INV_Pos (20UL) /*!< INV (Bit 20) */ +#define PPB_TRCRSCTLR2_INV_Msk (0x100000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define PPB_TRCRSCTLR2_GROUP_Pos (16UL) /*!< GROUP (Bit 16) */ +#define PPB_TRCRSCTLR2_GROUP_Msk (0x70000UL) /*!< GROUP (Bitfield-Mask: 0x07) */ +#define PPB_TRCRSCTLR2_SELECT_Pos (0UL) /*!< SELECT (Bit 0) */ +#define PPB_TRCRSCTLR2_SELECT_Msk (0xffUL) /*!< SELECT (Bitfield-Mask: 0xff) */ +/* ====================================================== TRCRSCTLR3 ======================================================= */ +#define PPB_TRCRSCTLR3_PAIRINV_Pos (21UL) /*!< PAIRINV (Bit 21) */ +#define PPB_TRCRSCTLR3_PAIRINV_Msk (0x200000UL) /*!< PAIRINV (Bitfield-Mask: 0x01) */ +#define PPB_TRCRSCTLR3_INV_Pos (20UL) /*!< INV (Bit 20) */ +#define PPB_TRCRSCTLR3_INV_Msk (0x100000UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define PPB_TRCRSCTLR3_GROUP_Pos (16UL) /*!< GROUP (Bit 16) */ +#define PPB_TRCRSCTLR3_GROUP_Msk (0x70000UL) /*!< GROUP (Bitfield-Mask: 0x07) */ +#define PPB_TRCRSCTLR3_SELECT_Pos (0UL) /*!< SELECT (Bit 0) */ +#define PPB_TRCRSCTLR3_SELECT_Msk (0xffUL) /*!< SELECT (Bitfield-Mask: 0xff) */ +/* ======================================================= TRCSSCSR ======================================================== */ +#define PPB_TRCSSCSR_STATUS_Pos (31UL) /*!< STATUS (Bit 31) */ +#define PPB_TRCSSCSR_STATUS_Msk (0x80000000UL) /*!< STATUS (Bitfield-Mask: 0x01) */ +#define PPB_TRCSSCSR_PC_Pos (3UL) /*!< PC (Bit 3) */ +#define PPB_TRCSSCSR_PC_Msk (0x8UL) /*!< PC (Bitfield-Mask: 0x01) */ +#define PPB_TRCSSCSR_DV_Pos (2UL) /*!< DV (Bit 2) */ +#define PPB_TRCSSCSR_DV_Msk (0x4UL) /*!< DV (Bitfield-Mask: 0x01) */ +#define PPB_TRCSSCSR_DA_Pos (1UL) /*!< DA (Bit 1) */ +#define PPB_TRCSSCSR_DA_Msk (0x2UL) /*!< DA (Bitfield-Mask: 0x01) */ +#define PPB_TRCSSCSR_INST_Pos (0UL) /*!< INST (Bit 0) */ +#define PPB_TRCSSCSR_INST_Msk (0x1UL) /*!< INST (Bitfield-Mask: 0x01) */ +/* ====================================================== TRCSSPCICR ======================================================= */ +#define PPB_TRCSSPCICR_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define PPB_TRCSSPCICR_PC_Msk (0xfUL) /*!< PC (Bitfield-Mask: 0x0f) */ +/* ======================================================== TRCPDCR ======================================================== */ +#define PPB_TRCPDCR_PU_Pos (3UL) /*!< PU (Bit 3) */ +#define PPB_TRCPDCR_PU_Msk (0x8UL) /*!< PU (Bitfield-Mask: 0x01) */ +/* ======================================================== TRCPDSR ======================================================== */ +#define PPB_TRCPDSR_OSLK_Pos (5UL) /*!< OSLK (Bit 5) */ +#define PPB_TRCPDSR_OSLK_Msk (0x20UL) /*!< OSLK (Bitfield-Mask: 0x01) */ +#define PPB_TRCPDSR_STICKYPD_Pos (1UL) /*!< STICKYPD (Bit 1) */ +#define PPB_TRCPDSR_STICKYPD_Msk (0x2UL) /*!< STICKYPD (Bitfield-Mask: 0x01) */ +#define PPB_TRCPDSR_POWER_Pos (0UL) /*!< POWER (Bit 0) */ +#define PPB_TRCPDSR_POWER_Msk (0x1UL) /*!< POWER (Bitfield-Mask: 0x01) */ +/* ====================================================== TRCITATBIDR ====================================================== */ +#define PPB_TRCITATBIDR_ID_Pos (0UL) /*!< ID (Bit 0) */ +#define PPB_TRCITATBIDR_ID_Msk (0x7fUL) /*!< ID (Bitfield-Mask: 0x7f) */ +/* ===================================================== TRCITIATBINR ====================================================== */ +#define PPB_TRCITIATBINR_AFVALIDM_Pos (1UL) /*!< AFVALIDM (Bit 1) */ +#define PPB_TRCITIATBINR_AFVALIDM_Msk (0x2UL) /*!< AFVALIDM (Bitfield-Mask: 0x01) */ +#define PPB_TRCITIATBINR_ATREADYM_Pos (0UL) /*!< ATREADYM (Bit 0) */ +#define PPB_TRCITIATBINR_ATREADYM_Msk (0x1UL) /*!< ATREADYM (Bitfield-Mask: 0x01) */ +/* ===================================================== TRCITIATBOUTR ===================================================== */ +#define PPB_TRCITIATBOUTR_AFREADY_Pos (1UL) /*!< AFREADY (Bit 1) */ +#define PPB_TRCITIATBOUTR_AFREADY_Msk (0x2UL) /*!< AFREADY (Bitfield-Mask: 0x01) */ +#define PPB_TRCITIATBOUTR_ATVALID_Pos (0UL) /*!< ATVALID (Bit 0) */ +#define PPB_TRCITIATBOUTR_ATVALID_Msk (0x1UL) /*!< ATVALID (Bitfield-Mask: 0x01) */ +/* ====================================================== TRCCLAIMSET ====================================================== */ +#define PPB_TRCCLAIMSET_SET3_Pos (3UL) /*!< SET3 (Bit 3) */ +#define PPB_TRCCLAIMSET_SET3_Msk (0x8UL) /*!< SET3 (Bitfield-Mask: 0x01) */ +#define PPB_TRCCLAIMSET_SET2_Pos (2UL) /*!< SET2 (Bit 2) */ +#define PPB_TRCCLAIMSET_SET2_Msk (0x4UL) /*!< SET2 (Bitfield-Mask: 0x01) */ +#define PPB_TRCCLAIMSET_SET1_Pos (1UL) /*!< SET1 (Bit 1) */ +#define PPB_TRCCLAIMSET_SET1_Msk (0x2UL) /*!< SET1 (Bitfield-Mask: 0x01) */ +#define PPB_TRCCLAIMSET_SET0_Pos (0UL) /*!< SET0 (Bit 0) */ +#define PPB_TRCCLAIMSET_SET0_Msk (0x1UL) /*!< SET0 (Bitfield-Mask: 0x01) */ +/* ====================================================== TRCCLAIMCLR ====================================================== */ +#define PPB_TRCCLAIMCLR_CLR3_Pos (3UL) /*!< CLR3 (Bit 3) */ +#define PPB_TRCCLAIMCLR_CLR3_Msk (0x8UL) /*!< CLR3 (Bitfield-Mask: 0x01) */ +#define PPB_TRCCLAIMCLR_CLR2_Pos (2UL) /*!< CLR2 (Bit 2) */ +#define PPB_TRCCLAIMCLR_CLR2_Msk (0x4UL) /*!< CLR2 (Bitfield-Mask: 0x01) */ +#define PPB_TRCCLAIMCLR_CLR1_Pos (1UL) /*!< CLR1 (Bit 1) */ +#define PPB_TRCCLAIMCLR_CLR1_Msk (0x2UL) /*!< CLR1 (Bitfield-Mask: 0x01) */ +#define PPB_TRCCLAIMCLR_CLR0_Pos (0UL) /*!< CLR0 (Bit 0) */ +#define PPB_TRCCLAIMCLR_CLR0_Msk (0x1UL) /*!< CLR0 (Bitfield-Mask: 0x01) */ +/* ===================================================== TRCAUTHSTATUS ===================================================== */ +#define PPB_TRCAUTHSTATUS_SNID_Pos (6UL) /*!< SNID (Bit 6) */ +#define PPB_TRCAUTHSTATUS_SNID_Msk (0xc0UL) /*!< SNID (Bitfield-Mask: 0x03) */ +#define PPB_TRCAUTHSTATUS_SID_Pos (4UL) /*!< SID (Bit 4) */ +#define PPB_TRCAUTHSTATUS_SID_Msk (0x30UL) /*!< SID (Bitfield-Mask: 0x03) */ +#define PPB_TRCAUTHSTATUS_NSNID_Pos (2UL) /*!< NSNID (Bit 2) */ +#define PPB_TRCAUTHSTATUS_NSNID_Msk (0xcUL) /*!< NSNID (Bitfield-Mask: 0x03) */ +#define PPB_TRCAUTHSTATUS_NSID_Pos (0UL) /*!< NSID (Bit 0) */ +#define PPB_TRCAUTHSTATUS_NSID_Msk (0x3UL) /*!< NSID (Bitfield-Mask: 0x03) */ +/* ====================================================== TRCDEVARCH ======================================================= */ +#define PPB_TRCDEVARCH_ARCHITECT_Pos (21UL) /*!< ARCHITECT (Bit 21) */ +#define PPB_TRCDEVARCH_ARCHITECT_Msk (0xffe00000UL) /*!< ARCHITECT (Bitfield-Mask: 0x7ff) */ +#define PPB_TRCDEVARCH_PRESENT_Pos (20UL) /*!< PRESENT (Bit 20) */ +#define PPB_TRCDEVARCH_PRESENT_Msk (0x100000UL) /*!< PRESENT (Bitfield-Mask: 0x01) */ +#define PPB_TRCDEVARCH_REVISION_Pos (16UL) /*!< REVISION (Bit 16) */ +#define PPB_TRCDEVARCH_REVISION_Msk (0xf0000UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_TRCDEVARCH_ARCHID_Pos (0UL) /*!< ARCHID (Bit 0) */ +#define PPB_TRCDEVARCH_ARCHID_Msk (0xffffUL) /*!< ARCHID (Bitfield-Mask: 0xffff) */ +/* ======================================================= TRCDEVID ======================================================== */ +#define PPB_TRCDEVID_TRCDEVID_Pos (0UL) /*!< TRCDEVID (Bit 0) */ +#define PPB_TRCDEVID_TRCDEVID_Msk (0xffffffffUL) /*!< TRCDEVID (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TRCDEVTYPE ======================================================= */ +#define PPB_TRCDEVTYPE_SUB_Pos (4UL) /*!< SUB (Bit 4) */ +#define PPB_TRCDEVTYPE_SUB_Msk (0xf0UL) /*!< SUB (Bitfield-Mask: 0x0f) */ +#define PPB_TRCDEVTYPE_MAJOR_Pos (0UL) /*!< MAJOR (Bit 0) */ +#define PPB_TRCDEVTYPE_MAJOR_Msk (0xfUL) /*!< MAJOR (Bitfield-Mask: 0x0f) */ +/* ======================================================= TRCPIDR4 ======================================================== */ +#define PPB_TRCPIDR4_SIZE_Pos (4UL) /*!< SIZE (Bit 4) */ +#define PPB_TRCPIDR4_SIZE_Msk (0xf0UL) /*!< SIZE (Bitfield-Mask: 0x0f) */ +#define PPB_TRCPIDR4_DES_2_Pos (0UL) /*!< DES_2 (Bit 0) */ +#define PPB_TRCPIDR4_DES_2_Msk (0xfUL) /*!< DES_2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= TRCPIDR5 ======================================================== */ +#define PPB_TRCPIDR5_TRCPIDR5_Pos (0UL) /*!< TRCPIDR5 (Bit 0) */ +#define PPB_TRCPIDR5_TRCPIDR5_Msk (0xffffffffUL) /*!< TRCPIDR5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TRCPIDR6 ======================================================== */ +#define PPB_TRCPIDR6_TRCPIDR6_Pos (0UL) /*!< TRCPIDR6 (Bit 0) */ +#define PPB_TRCPIDR6_TRCPIDR6_Msk (0xffffffffUL) /*!< TRCPIDR6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TRCPIDR7 ======================================================== */ +#define PPB_TRCPIDR7_TRCPIDR7_Pos (0UL) /*!< TRCPIDR7 (Bit 0) */ +#define PPB_TRCPIDR7_TRCPIDR7_Msk (0xffffffffUL) /*!< TRCPIDR7 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TRCPIDR0 ======================================================== */ +#define PPB_TRCPIDR0_PART_0_Pos (0UL) /*!< PART_0 (Bit 0) */ +#define PPB_TRCPIDR0_PART_0_Msk (0xffUL) /*!< PART_0 (Bitfield-Mask: 0xff) */ +/* ======================================================= TRCPIDR1 ======================================================== */ +#define PPB_TRCPIDR1_DES_0_Pos (4UL) /*!< DES_0 (Bit 4) */ +#define PPB_TRCPIDR1_DES_0_Msk (0xf0UL) /*!< DES_0 (Bitfield-Mask: 0x0f) */ +#define PPB_TRCPIDR1_PART_0_Pos (0UL) /*!< PART_0 (Bit 0) */ +#define PPB_TRCPIDR1_PART_0_Msk (0xfUL) /*!< PART_0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= TRCPIDR2 ======================================================== */ +#define PPB_TRCPIDR2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */ +#define PPB_TRCPIDR2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_TRCPIDR2_JEDEC_Pos (3UL) /*!< JEDEC (Bit 3) */ +#define PPB_TRCPIDR2_JEDEC_Msk (0x8UL) /*!< JEDEC (Bitfield-Mask: 0x01) */ +#define PPB_TRCPIDR2_DES_0_Pos (0UL) /*!< DES_0 (Bit 0) */ +#define PPB_TRCPIDR2_DES_0_Msk (0x7UL) /*!< DES_0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TRCPIDR3 ======================================================== */ +#define PPB_TRCPIDR3_REVAND_Pos (4UL) /*!< REVAND (Bit 4) */ +#define PPB_TRCPIDR3_REVAND_Msk (0xf0UL) /*!< REVAND (Bitfield-Mask: 0x0f) */ +#define PPB_TRCPIDR3_CMOD_Pos (0UL) /*!< CMOD (Bit 0) */ +#define PPB_TRCPIDR3_CMOD_Msk (0xfUL) /*!< CMOD (Bitfield-Mask: 0x0f) */ +/* ======================================================= TRCCIDR0 ======================================================== */ +#define PPB_TRCCIDR0_PRMBL_0_Pos (0UL) /*!< PRMBL_0 (Bit 0) */ +#define PPB_TRCCIDR0_PRMBL_0_Msk (0xffUL) /*!< PRMBL_0 (Bitfield-Mask: 0xff) */ +/* ======================================================= TRCCIDR1 ======================================================== */ +#define PPB_TRCCIDR1_CLASS_Pos (4UL) /*!< CLASS (Bit 4) */ +#define PPB_TRCCIDR1_CLASS_Msk (0xf0UL) /*!< CLASS (Bitfield-Mask: 0x0f) */ +#define PPB_TRCCIDR1_PRMBL_1_Pos (0UL) /*!< PRMBL_1 (Bit 0) */ +#define PPB_TRCCIDR1_PRMBL_1_Msk (0xfUL) /*!< PRMBL_1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= TRCCIDR2 ======================================================== */ +#define PPB_TRCCIDR2_PRMBL_2_Pos (0UL) /*!< PRMBL_2 (Bit 0) */ +#define PPB_TRCCIDR2_PRMBL_2_Msk (0xffUL) /*!< PRMBL_2 (Bitfield-Mask: 0xff) */ +/* ======================================================= TRCCIDR3 ======================================================== */ +#define PPB_TRCCIDR3_PRMBL_3_Pos (0UL) /*!< PRMBL_3 (Bit 0) */ +#define PPB_TRCCIDR3_PRMBL_3_Msk (0xffUL) /*!< PRMBL_3 (Bitfield-Mask: 0xff) */ +/* ====================================================== CTICONTROL ======================================================= */ +#define PPB_CTICONTROL_GLBEN_Pos (0UL) /*!< GLBEN (Bit 0) */ +#define PPB_CTICONTROL_GLBEN_Msk (0x1UL) /*!< GLBEN (Bitfield-Mask: 0x01) */ +/* ======================================================= CTIINTACK ======================================================= */ +#define PPB_CTIINTACK_INTACK_Pos (0UL) /*!< INTACK (Bit 0) */ +#define PPB_CTIINTACK_INTACK_Msk (0xffUL) /*!< INTACK (Bitfield-Mask: 0xff) */ +/* ======================================================= CTIAPPSET ======================================================= */ +#define PPB_CTIAPPSET_APPSET_Pos (0UL) /*!< APPSET (Bit 0) */ +#define PPB_CTIAPPSET_APPSET_Msk (0xfUL) /*!< APPSET (Bitfield-Mask: 0x0f) */ +/* ====================================================== CTIAPPCLEAR ====================================================== */ +#define PPB_CTIAPPCLEAR_APPCLEAR_Pos (0UL) /*!< APPCLEAR (Bit 0) */ +#define PPB_CTIAPPCLEAR_APPCLEAR_Msk (0xfUL) /*!< APPCLEAR (Bitfield-Mask: 0x0f) */ +/* ====================================================== CTIAPPPULSE ====================================================== */ +#define PPB_CTIAPPPULSE_APPULSE_Pos (0UL) /*!< APPULSE (Bit 0) */ +#define PPB_CTIAPPPULSE_APPULSE_Msk (0xfUL) /*!< APPULSE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIINEN0 ======================================================== */ +#define PPB_CTIINEN0_TRIGINEN_Pos (0UL) /*!< TRIGINEN (Bit 0) */ +#define PPB_CTIINEN0_TRIGINEN_Msk (0xfUL) /*!< TRIGINEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIINEN1 ======================================================== */ +#define PPB_CTIINEN1_TRIGINEN_Pos (0UL) /*!< TRIGINEN (Bit 0) */ +#define PPB_CTIINEN1_TRIGINEN_Msk (0xfUL) /*!< TRIGINEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIINEN2 ======================================================== */ +#define PPB_CTIINEN2_TRIGINEN_Pos (0UL) /*!< TRIGINEN (Bit 0) */ +#define PPB_CTIINEN2_TRIGINEN_Msk (0xfUL) /*!< TRIGINEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIINEN3 ======================================================== */ +#define PPB_CTIINEN3_TRIGINEN_Pos (0UL) /*!< TRIGINEN (Bit 0) */ +#define PPB_CTIINEN3_TRIGINEN_Msk (0xfUL) /*!< TRIGINEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIINEN4 ======================================================== */ +#define PPB_CTIINEN4_TRIGINEN_Pos (0UL) /*!< TRIGINEN (Bit 0) */ +#define PPB_CTIINEN4_TRIGINEN_Msk (0xfUL) /*!< TRIGINEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIINEN5 ======================================================== */ +#define PPB_CTIINEN5_TRIGINEN_Pos (0UL) /*!< TRIGINEN (Bit 0) */ +#define PPB_CTIINEN5_TRIGINEN_Msk (0xfUL) /*!< TRIGINEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIINEN6 ======================================================== */ +#define PPB_CTIINEN6_TRIGINEN_Pos (0UL) /*!< TRIGINEN (Bit 0) */ +#define PPB_CTIINEN6_TRIGINEN_Msk (0xfUL) /*!< TRIGINEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIINEN7 ======================================================== */ +#define PPB_CTIINEN7_TRIGINEN_Pos (0UL) /*!< TRIGINEN (Bit 0) */ +#define PPB_CTIINEN7_TRIGINEN_Msk (0xfUL) /*!< TRIGINEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIOUTEN0 ======================================================= */ +#define PPB_CTIOUTEN0_TRIGOUTEN_Pos (0UL) /*!< TRIGOUTEN (Bit 0) */ +#define PPB_CTIOUTEN0_TRIGOUTEN_Msk (0xfUL) /*!< TRIGOUTEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIOUTEN1 ======================================================= */ +#define PPB_CTIOUTEN1_TRIGOUTEN_Pos (0UL) /*!< TRIGOUTEN (Bit 0) */ +#define PPB_CTIOUTEN1_TRIGOUTEN_Msk (0xfUL) /*!< TRIGOUTEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIOUTEN2 ======================================================= */ +#define PPB_CTIOUTEN2_TRIGOUTEN_Pos (0UL) /*!< TRIGOUTEN (Bit 0) */ +#define PPB_CTIOUTEN2_TRIGOUTEN_Msk (0xfUL) /*!< TRIGOUTEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIOUTEN3 ======================================================= */ +#define PPB_CTIOUTEN3_TRIGOUTEN_Pos (0UL) /*!< TRIGOUTEN (Bit 0) */ +#define PPB_CTIOUTEN3_TRIGOUTEN_Msk (0xfUL) /*!< TRIGOUTEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIOUTEN4 ======================================================= */ +#define PPB_CTIOUTEN4_TRIGOUTEN_Pos (0UL) /*!< TRIGOUTEN (Bit 0) */ +#define PPB_CTIOUTEN4_TRIGOUTEN_Msk (0xfUL) /*!< TRIGOUTEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIOUTEN5 ======================================================= */ +#define PPB_CTIOUTEN5_TRIGOUTEN_Pos (0UL) /*!< TRIGOUTEN (Bit 0) */ +#define PPB_CTIOUTEN5_TRIGOUTEN_Msk (0xfUL) /*!< TRIGOUTEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIOUTEN6 ======================================================= */ +#define PPB_CTIOUTEN6_TRIGOUTEN_Pos (0UL) /*!< TRIGOUTEN (Bit 0) */ +#define PPB_CTIOUTEN6_TRIGOUTEN_Msk (0xfUL) /*!< TRIGOUTEN (Bitfield-Mask: 0x0f) */ +/* ======================================================= CTIOUTEN7 ======================================================= */ +#define PPB_CTIOUTEN7_TRIGOUTEN_Pos (0UL) /*!< TRIGOUTEN (Bit 0) */ +#define PPB_CTIOUTEN7_TRIGOUTEN_Msk (0xfUL) /*!< TRIGOUTEN (Bitfield-Mask: 0x0f) */ +/* ==================================================== CTITRIGINSTATUS ==================================================== */ +#define PPB_CTITRIGINSTATUS_TRIGINSTATUS_Pos (0UL) /*!< TRIGINSTATUS (Bit 0) */ +#define PPB_CTITRIGINSTATUS_TRIGINSTATUS_Msk (0xffUL) /*!< TRIGINSTATUS (Bitfield-Mask: 0xff) */ +/* =================================================== CTITRIGOUTSTATUS ==================================================== */ +#define PPB_CTITRIGOUTSTATUS_TRIGOUTSTATUS_Pos (0UL) /*!< TRIGOUTSTATUS (Bit 0) */ +#define PPB_CTITRIGOUTSTATUS_TRIGOUTSTATUS_Msk (0xffUL) /*!< TRIGOUTSTATUS (Bitfield-Mask: 0xff) */ +/* ===================================================== CTICHINSTATUS ===================================================== */ +#define PPB_CTICHINSTATUS_CTICHOUTSTATUS_Pos (0UL) /*!< CTICHOUTSTATUS (Bit 0) */ +#define PPB_CTICHINSTATUS_CTICHOUTSTATUS_Msk (0xfUL) /*!< CTICHOUTSTATUS (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTIGATE ======================================================== */ +#define PPB_CTIGATE_CTIGATEEN3_Pos (3UL) /*!< CTIGATEEN3 (Bit 3) */ +#define PPB_CTIGATE_CTIGATEEN3_Msk (0x8UL) /*!< CTIGATEEN3 (Bitfield-Mask: 0x01) */ +#define PPB_CTIGATE_CTIGATEEN2_Pos (2UL) /*!< CTIGATEEN2 (Bit 2) */ +#define PPB_CTIGATE_CTIGATEEN2_Msk (0x4UL) /*!< CTIGATEEN2 (Bitfield-Mask: 0x01) */ +#define PPB_CTIGATE_CTIGATEEN1_Pos (1UL) /*!< CTIGATEEN1 (Bit 1) */ +#define PPB_CTIGATE_CTIGATEEN1_Msk (0x2UL) /*!< CTIGATEEN1 (Bitfield-Mask: 0x01) */ +#define PPB_CTIGATE_CTIGATEEN0_Pos (0UL) /*!< CTIGATEEN0 (Bit 0) */ +#define PPB_CTIGATE_CTIGATEEN0_Msk (0x1UL) /*!< CTIGATEEN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ASICCTL ======================================================== */ +#define PPB_ASICCTL_ASICCTL_Pos (0UL) /*!< ASICCTL (Bit 0) */ +#define PPB_ASICCTL_ASICCTL_Msk (0xffffffffUL) /*!< ASICCTL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ITCHOUT ======================================================== */ +#define PPB_ITCHOUT_CTCHOUT_Pos (0UL) /*!< CTCHOUT (Bit 0) */ +#define PPB_ITCHOUT_CTCHOUT_Msk (0xfUL) /*!< CTCHOUT (Bitfield-Mask: 0x0f) */ +/* ======================================================= ITTRIGOUT ======================================================= */ +#define PPB_ITTRIGOUT_CTTRIGOUT_Pos (0UL) /*!< CTTRIGOUT (Bit 0) */ +#define PPB_ITTRIGOUT_CTTRIGOUT_Msk (0xffUL) /*!< CTTRIGOUT (Bitfield-Mask: 0xff) */ +/* ======================================================== ITCHIN ========================================================= */ +#define PPB_ITCHIN_CTCHIN_Pos (0UL) /*!< CTCHIN (Bit 0) */ +#define PPB_ITCHIN_CTCHIN_Msk (0xfUL) /*!< CTCHIN (Bitfield-Mask: 0x0f) */ +/* ======================================================== ITCTRL ========================================================= */ +#define PPB_ITCTRL_IME_Pos (0UL) /*!< IME (Bit 0) */ +#define PPB_ITCTRL_IME_Msk (0x1UL) /*!< IME (Bitfield-Mask: 0x01) */ +/* ======================================================== DEVARCH ======================================================== */ +#define PPB_DEVARCH_ARCHITECT_Pos (21UL) /*!< ARCHITECT (Bit 21) */ +#define PPB_DEVARCH_ARCHITECT_Msk (0xffe00000UL) /*!< ARCHITECT (Bitfield-Mask: 0x7ff) */ +#define PPB_DEVARCH_PRESENT_Pos (20UL) /*!< PRESENT (Bit 20) */ +#define PPB_DEVARCH_PRESENT_Msk (0x100000UL) /*!< PRESENT (Bitfield-Mask: 0x01) */ +#define PPB_DEVARCH_REVISION_Pos (16UL) /*!< REVISION (Bit 16) */ +#define PPB_DEVARCH_REVISION_Msk (0xf0000UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_DEVARCH_ARCHID_Pos (0UL) /*!< ARCHID (Bit 0) */ +#define PPB_DEVARCH_ARCHID_Msk (0xffffUL) /*!< ARCHID (Bitfield-Mask: 0xffff) */ +/* ========================================================= DEVID ========================================================= */ +#define PPB_DEVID_NUMCH_Pos (16UL) /*!< NUMCH (Bit 16) */ +#define PPB_DEVID_NUMCH_Msk (0xf0000UL) /*!< NUMCH (Bitfield-Mask: 0x0f) */ +#define PPB_DEVID_NUMTRIG_Pos (8UL) /*!< NUMTRIG (Bit 8) */ +#define PPB_DEVID_NUMTRIG_Msk (0xff00UL) /*!< NUMTRIG (Bitfield-Mask: 0xff) */ +#define PPB_DEVID_EXTMUXNUM_Pos (0UL) /*!< EXTMUXNUM (Bit 0) */ +#define PPB_DEVID_EXTMUXNUM_Msk (0x1fUL) /*!< EXTMUXNUM (Bitfield-Mask: 0x1f) */ +/* ======================================================== DEVTYPE ======================================================== */ +#define PPB_DEVTYPE_SUB_Pos (4UL) /*!< SUB (Bit 4) */ +#define PPB_DEVTYPE_SUB_Msk (0xf0UL) /*!< SUB (Bitfield-Mask: 0x0f) */ +#define PPB_DEVTYPE_MAJOR_Pos (0UL) /*!< MAJOR (Bit 0) */ +#define PPB_DEVTYPE_MAJOR_Msk (0xfUL) /*!< MAJOR (Bitfield-Mask: 0x0f) */ +/* ========================================================= PIDR4 ========================================================= */ +#define PPB_PIDR4_SIZE_Pos (4UL) /*!< SIZE (Bit 4) */ +#define PPB_PIDR4_SIZE_Msk (0xf0UL) /*!< SIZE (Bitfield-Mask: 0x0f) */ +#define PPB_PIDR4_DES_2_Pos (0UL) /*!< DES_2 (Bit 0) */ +#define PPB_PIDR4_DES_2_Msk (0xfUL) /*!< DES_2 (Bitfield-Mask: 0x0f) */ +/* ========================================================= PIDR5 ========================================================= */ +#define PPB_PIDR5_PIDR5_Pos (0UL) /*!< PIDR5 (Bit 0) */ +#define PPB_PIDR5_PIDR5_Msk (0xffffffffUL) /*!< PIDR5 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PIDR6 ========================================================= */ +#define PPB_PIDR6_PIDR6_Pos (0UL) /*!< PIDR6 (Bit 0) */ +#define PPB_PIDR6_PIDR6_Msk (0xffffffffUL) /*!< PIDR6 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PIDR7 ========================================================= */ +#define PPB_PIDR7_PIDR7_Pos (0UL) /*!< PIDR7 (Bit 0) */ +#define PPB_PIDR7_PIDR7_Msk (0xffffffffUL) /*!< PIDR7 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PIDR0 ========================================================= */ +#define PPB_PIDR0_PART_0_Pos (0UL) /*!< PART_0 (Bit 0) */ +#define PPB_PIDR0_PART_0_Msk (0xffUL) /*!< PART_0 (Bitfield-Mask: 0xff) */ +/* ========================================================= PIDR1 ========================================================= */ +#define PPB_PIDR1_DES_0_Pos (4UL) /*!< DES_0 (Bit 4) */ +#define PPB_PIDR1_DES_0_Msk (0xf0UL) /*!< DES_0 (Bitfield-Mask: 0x0f) */ +#define PPB_PIDR1_PART_1_Pos (0UL) /*!< PART_1 (Bit 0) */ +#define PPB_PIDR1_PART_1_Msk (0xfUL) /*!< PART_1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= PIDR2 ========================================================= */ +#define PPB_PIDR2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */ +#define PPB_PIDR2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define PPB_PIDR2_JEDEC_Pos (3UL) /*!< JEDEC (Bit 3) */ +#define PPB_PIDR2_JEDEC_Msk (0x8UL) /*!< JEDEC (Bitfield-Mask: 0x01) */ +#define PPB_PIDR2_DES_1_Pos (0UL) /*!< DES_1 (Bit 0) */ +#define PPB_PIDR2_DES_1_Msk (0x7UL) /*!< DES_1 (Bitfield-Mask: 0x07) */ +/* ========================================================= PIDR3 ========================================================= */ +#define PPB_PIDR3_REVAND_Pos (4UL) /*!< REVAND (Bit 4) */ +#define PPB_PIDR3_REVAND_Msk (0xf0UL) /*!< REVAND (Bitfield-Mask: 0x0f) */ +#define PPB_PIDR3_CMOD_Pos (0UL) /*!< CMOD (Bit 0) */ +#define PPB_PIDR3_CMOD_Msk (0xfUL) /*!< CMOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= CIDR0 ========================================================= */ +#define PPB_CIDR0_PRMBL_0_Pos (0UL) /*!< PRMBL_0 (Bit 0) */ +#define PPB_CIDR0_PRMBL_0_Msk (0xffUL) /*!< PRMBL_0 (Bitfield-Mask: 0xff) */ +/* ========================================================= CIDR1 ========================================================= */ +#define PPB_CIDR1_CLASS_Pos (4UL) /*!< CLASS (Bit 4) */ +#define PPB_CIDR1_CLASS_Msk (0xf0UL) /*!< CLASS (Bitfield-Mask: 0x0f) */ +#define PPB_CIDR1_PRMBL_1_Pos (0UL) /*!< PRMBL_1 (Bit 0) */ +#define PPB_CIDR1_PRMBL_1_Msk (0xfUL) /*!< PRMBL_1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= CIDR2 ========================================================= */ +#define PPB_CIDR2_PRMBL_2_Pos (0UL) /*!< PRMBL_2 (Bit 0) */ +#define PPB_CIDR2_PRMBL_2_Msk (0xffUL) /*!< PRMBL_2 (Bitfield-Mask: 0xff) */ +/* ========================================================= CIDR3 ========================================================= */ +#define PPB_CIDR3_PRMBL_3_Pos (0UL) /*!< PRMBL_3 (Bit 0) */ +#define PPB_CIDR3_PRMBL_3_Msk (0xffUL) /*!< PRMBL_3 (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ QMI ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== DIRECT_CSR ======================================================= */ +#define QMI_DIRECT_CSR_RXDELAY_Pos (30UL) /*!< RXDELAY (Bit 30) */ +#define QMI_DIRECT_CSR_RXDELAY_Msk (0xc0000000UL) /*!< RXDELAY (Bitfield-Mask: 0x03) */ +#define QMI_DIRECT_CSR_CLKDIV_Pos (22UL) /*!< CLKDIV (Bit 22) */ +#define QMI_DIRECT_CSR_CLKDIV_Msk (0x3fc00000UL) /*!< CLKDIV (Bitfield-Mask: 0xff) */ +#define QMI_DIRECT_CSR_RXLEVEL_Pos (18UL) /*!< RXLEVEL (Bit 18) */ +#define QMI_DIRECT_CSR_RXLEVEL_Msk (0x1c0000UL) /*!< RXLEVEL (Bitfield-Mask: 0x07) */ +#define QMI_DIRECT_CSR_RXFULL_Pos (17UL) /*!< RXFULL (Bit 17) */ +#define QMI_DIRECT_CSR_RXFULL_Msk (0x20000UL) /*!< RXFULL (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_CSR_RXEMPTY_Pos (16UL) /*!< RXEMPTY (Bit 16) */ +#define QMI_DIRECT_CSR_RXEMPTY_Msk (0x10000UL) /*!< RXEMPTY (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_CSR_TXLEVEL_Pos (12UL) /*!< TXLEVEL (Bit 12) */ +#define QMI_DIRECT_CSR_TXLEVEL_Msk (0x7000UL) /*!< TXLEVEL (Bitfield-Mask: 0x07) */ +#define QMI_DIRECT_CSR_TXEMPTY_Pos (11UL) /*!< TXEMPTY (Bit 11) */ +#define QMI_DIRECT_CSR_TXEMPTY_Msk (0x800UL) /*!< TXEMPTY (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_CSR_TXFULL_Pos (10UL) /*!< TXFULL (Bit 10) */ +#define QMI_DIRECT_CSR_TXFULL_Msk (0x400UL) /*!< TXFULL (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_CSR_AUTO_CS1N_Pos (7UL) /*!< AUTO_CS1N (Bit 7) */ +#define QMI_DIRECT_CSR_AUTO_CS1N_Msk (0x80UL) /*!< AUTO_CS1N (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_CSR_AUTO_CS0N_Pos (6UL) /*!< AUTO_CS0N (Bit 6) */ +#define QMI_DIRECT_CSR_AUTO_CS0N_Msk (0x40UL) /*!< AUTO_CS0N (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_CSR_ASSERT_CS1N_Pos (3UL) /*!< ASSERT_CS1N (Bit 3) */ +#define QMI_DIRECT_CSR_ASSERT_CS1N_Msk (0x8UL) /*!< ASSERT_CS1N (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_CSR_ASSERT_CS0N_Pos (2UL) /*!< ASSERT_CS0N (Bit 2) */ +#define QMI_DIRECT_CSR_ASSERT_CS0N_Msk (0x4UL) /*!< ASSERT_CS0N (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_CSR_BUSY_Pos (1UL) /*!< BUSY (Bit 1) */ +#define QMI_DIRECT_CSR_BUSY_Msk (0x2UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define QMI_DIRECT_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= DIRECT_TX ======================================================= */ +#define QMI_DIRECT_TX_NOPUSH_Pos (20UL) /*!< NOPUSH (Bit 20) */ +#define QMI_DIRECT_TX_NOPUSH_Msk (0x100000UL) /*!< NOPUSH (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_TX_OE_Pos (19UL) /*!< OE (Bit 19) */ +#define QMI_DIRECT_TX_OE_Msk (0x80000UL) /*!< OE (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_TX_DWIDTH_Pos (18UL) /*!< DWIDTH (Bit 18) */ +#define QMI_DIRECT_TX_DWIDTH_Msk (0x40000UL) /*!< DWIDTH (Bitfield-Mask: 0x01) */ +#define QMI_DIRECT_TX_IWIDTH_Pos (16UL) /*!< IWIDTH (Bit 16) */ +#define QMI_DIRECT_TX_IWIDTH_Msk (0x30000UL) /*!< IWIDTH (Bitfield-Mask: 0x03) */ +#define QMI_DIRECT_TX_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define QMI_DIRECT_TX_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= DIRECT_RX ======================================================= */ +#define QMI_DIRECT_RX_DIRECT_RX_Pos (0UL) /*!< DIRECT_RX (Bit 0) */ +#define QMI_DIRECT_RX_DIRECT_RX_Msk (0xffffUL) /*!< DIRECT_RX (Bitfield-Mask: 0xffff) */ +/* ======================================================= M0_TIMING ======================================================= */ +#define QMI_M0_TIMING_COOLDOWN_Pos (30UL) /*!< COOLDOWN (Bit 30) */ +#define QMI_M0_TIMING_COOLDOWN_Msk (0xc0000000UL) /*!< COOLDOWN (Bitfield-Mask: 0x03) */ +#define QMI_M0_TIMING_PAGEBREAK_Pos (28UL) /*!< PAGEBREAK (Bit 28) */ +#define QMI_M0_TIMING_PAGEBREAK_Msk (0x30000000UL) /*!< PAGEBREAK (Bitfield-Mask: 0x03) */ +#define QMI_M0_TIMING_SELECT_SETUP_Pos (25UL) /*!< SELECT_SETUP (Bit 25) */ +#define QMI_M0_TIMING_SELECT_SETUP_Msk (0x2000000UL) /*!< SELECT_SETUP (Bitfield-Mask: 0x01) */ +#define QMI_M0_TIMING_SELECT_HOLD_Pos (23UL) /*!< SELECT_HOLD (Bit 23) */ +#define QMI_M0_TIMING_SELECT_HOLD_Msk (0x1800000UL) /*!< SELECT_HOLD (Bitfield-Mask: 0x03) */ +#define QMI_M0_TIMING_MAX_SELECT_Pos (17UL) /*!< MAX_SELECT (Bit 17) */ +#define QMI_M0_TIMING_MAX_SELECT_Msk (0x7e0000UL) /*!< MAX_SELECT (Bitfield-Mask: 0x3f) */ +#define QMI_M0_TIMING_MIN_DESELECT_Pos (12UL) /*!< MIN_DESELECT (Bit 12) */ +#define QMI_M0_TIMING_MIN_DESELECT_Msk (0x1f000UL) /*!< MIN_DESELECT (Bitfield-Mask: 0x1f) */ +#define QMI_M0_TIMING_RXDELAY_Pos (8UL) /*!< RXDELAY (Bit 8) */ +#define QMI_M0_TIMING_RXDELAY_Msk (0x700UL) /*!< RXDELAY (Bitfield-Mask: 0x07) */ +#define QMI_M0_TIMING_CLKDIV_Pos (0UL) /*!< CLKDIV (Bit 0) */ +#define QMI_M0_TIMING_CLKDIV_Msk (0xffUL) /*!< CLKDIV (Bitfield-Mask: 0xff) */ +/* ======================================================== M0_RFMT ======================================================== */ +#define QMI_M0_RFMT_DTR_Pos (28UL) /*!< DTR (Bit 28) */ +#define QMI_M0_RFMT_DTR_Msk (0x10000000UL) /*!< DTR (Bitfield-Mask: 0x01) */ +#define QMI_M0_RFMT_DUMMY_LEN_Pos (16UL) /*!< DUMMY_LEN (Bit 16) */ +#define QMI_M0_RFMT_DUMMY_LEN_Msk (0x70000UL) /*!< DUMMY_LEN (Bitfield-Mask: 0x07) */ +#define QMI_M0_RFMT_SUFFIX_LEN_Pos (14UL) /*!< SUFFIX_LEN (Bit 14) */ +#define QMI_M0_RFMT_SUFFIX_LEN_Msk (0xc000UL) /*!< SUFFIX_LEN (Bitfield-Mask: 0x03) */ +#define QMI_M0_RFMT_PREFIX_LEN_Pos (12UL) /*!< PREFIX_LEN (Bit 12) */ +#define QMI_M0_RFMT_PREFIX_LEN_Msk (0x1000UL) /*!< PREFIX_LEN (Bitfield-Mask: 0x01) */ +#define QMI_M0_RFMT_DATA_WIDTH_Pos (8UL) /*!< DATA_WIDTH (Bit 8) */ +#define QMI_M0_RFMT_DATA_WIDTH_Msk (0x300UL) /*!< DATA_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M0_RFMT_DUMMY_WIDTH_Pos (6UL) /*!< DUMMY_WIDTH (Bit 6) */ +#define QMI_M0_RFMT_DUMMY_WIDTH_Msk (0xc0UL) /*!< DUMMY_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M0_RFMT_SUFFIX_WIDTH_Pos (4UL) /*!< SUFFIX_WIDTH (Bit 4) */ +#define QMI_M0_RFMT_SUFFIX_WIDTH_Msk (0x30UL) /*!< SUFFIX_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M0_RFMT_ADDR_WIDTH_Pos (2UL) /*!< ADDR_WIDTH (Bit 2) */ +#define QMI_M0_RFMT_ADDR_WIDTH_Msk (0xcUL) /*!< ADDR_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M0_RFMT_PREFIX_WIDTH_Pos (0UL) /*!< PREFIX_WIDTH (Bit 0) */ +#define QMI_M0_RFMT_PREFIX_WIDTH_Msk (0x3UL) /*!< PREFIX_WIDTH (Bitfield-Mask: 0x03) */ +/* ======================================================== M0_RCMD ======================================================== */ +#define QMI_M0_RCMD_SUFFIX_Pos (8UL) /*!< SUFFIX (Bit 8) */ +#define QMI_M0_RCMD_SUFFIX_Msk (0xff00UL) /*!< SUFFIX (Bitfield-Mask: 0xff) */ +#define QMI_M0_RCMD_PREFIX_Pos (0UL) /*!< PREFIX (Bit 0) */ +#define QMI_M0_RCMD_PREFIX_Msk (0xffUL) /*!< PREFIX (Bitfield-Mask: 0xff) */ +/* ======================================================== M0_WFMT ======================================================== */ +#define QMI_M0_WFMT_DTR_Pos (28UL) /*!< DTR (Bit 28) */ +#define QMI_M0_WFMT_DTR_Msk (0x10000000UL) /*!< DTR (Bitfield-Mask: 0x01) */ +#define QMI_M0_WFMT_DUMMY_LEN_Pos (16UL) /*!< DUMMY_LEN (Bit 16) */ +#define QMI_M0_WFMT_DUMMY_LEN_Msk (0x70000UL) /*!< DUMMY_LEN (Bitfield-Mask: 0x07) */ +#define QMI_M0_WFMT_SUFFIX_LEN_Pos (14UL) /*!< SUFFIX_LEN (Bit 14) */ +#define QMI_M0_WFMT_SUFFIX_LEN_Msk (0xc000UL) /*!< SUFFIX_LEN (Bitfield-Mask: 0x03) */ +#define QMI_M0_WFMT_PREFIX_LEN_Pos (12UL) /*!< PREFIX_LEN (Bit 12) */ +#define QMI_M0_WFMT_PREFIX_LEN_Msk (0x1000UL) /*!< PREFIX_LEN (Bitfield-Mask: 0x01) */ +#define QMI_M0_WFMT_DATA_WIDTH_Pos (8UL) /*!< DATA_WIDTH (Bit 8) */ +#define QMI_M0_WFMT_DATA_WIDTH_Msk (0x300UL) /*!< DATA_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M0_WFMT_DUMMY_WIDTH_Pos (6UL) /*!< DUMMY_WIDTH (Bit 6) */ +#define QMI_M0_WFMT_DUMMY_WIDTH_Msk (0xc0UL) /*!< DUMMY_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M0_WFMT_SUFFIX_WIDTH_Pos (4UL) /*!< SUFFIX_WIDTH (Bit 4) */ +#define QMI_M0_WFMT_SUFFIX_WIDTH_Msk (0x30UL) /*!< SUFFIX_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M0_WFMT_ADDR_WIDTH_Pos (2UL) /*!< ADDR_WIDTH (Bit 2) */ +#define QMI_M0_WFMT_ADDR_WIDTH_Msk (0xcUL) /*!< ADDR_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M0_WFMT_PREFIX_WIDTH_Pos (0UL) /*!< PREFIX_WIDTH (Bit 0) */ +#define QMI_M0_WFMT_PREFIX_WIDTH_Msk (0x3UL) /*!< PREFIX_WIDTH (Bitfield-Mask: 0x03) */ +/* ======================================================== M0_WCMD ======================================================== */ +#define QMI_M0_WCMD_SUFFIX_Pos (8UL) /*!< SUFFIX (Bit 8) */ +#define QMI_M0_WCMD_SUFFIX_Msk (0xff00UL) /*!< SUFFIX (Bitfield-Mask: 0xff) */ +#define QMI_M0_WCMD_PREFIX_Pos (0UL) /*!< PREFIX (Bit 0) */ +#define QMI_M0_WCMD_PREFIX_Msk (0xffUL) /*!< PREFIX (Bitfield-Mask: 0xff) */ +/* ======================================================= M1_TIMING ======================================================= */ +#define QMI_M1_TIMING_COOLDOWN_Pos (30UL) /*!< COOLDOWN (Bit 30) */ +#define QMI_M1_TIMING_COOLDOWN_Msk (0xc0000000UL) /*!< COOLDOWN (Bitfield-Mask: 0x03) */ +#define QMI_M1_TIMING_PAGEBREAK_Pos (28UL) /*!< PAGEBREAK (Bit 28) */ +#define QMI_M1_TIMING_PAGEBREAK_Msk (0x30000000UL) /*!< PAGEBREAK (Bitfield-Mask: 0x03) */ +#define QMI_M1_TIMING_SELECT_SETUP_Pos (25UL) /*!< SELECT_SETUP (Bit 25) */ +#define QMI_M1_TIMING_SELECT_SETUP_Msk (0x2000000UL) /*!< SELECT_SETUP (Bitfield-Mask: 0x01) */ +#define QMI_M1_TIMING_SELECT_HOLD_Pos (23UL) /*!< SELECT_HOLD (Bit 23) */ +#define QMI_M1_TIMING_SELECT_HOLD_Msk (0x1800000UL) /*!< SELECT_HOLD (Bitfield-Mask: 0x03) */ +#define QMI_M1_TIMING_MAX_SELECT_Pos (17UL) /*!< MAX_SELECT (Bit 17) */ +#define QMI_M1_TIMING_MAX_SELECT_Msk (0x7e0000UL) /*!< MAX_SELECT (Bitfield-Mask: 0x3f) */ +#define QMI_M1_TIMING_MIN_DESELECT_Pos (12UL) /*!< MIN_DESELECT (Bit 12) */ +#define QMI_M1_TIMING_MIN_DESELECT_Msk (0x1f000UL) /*!< MIN_DESELECT (Bitfield-Mask: 0x1f) */ +#define QMI_M1_TIMING_RXDELAY_Pos (8UL) /*!< RXDELAY (Bit 8) */ +#define QMI_M1_TIMING_RXDELAY_Msk (0x700UL) /*!< RXDELAY (Bitfield-Mask: 0x07) */ +#define QMI_M1_TIMING_CLKDIV_Pos (0UL) /*!< CLKDIV (Bit 0) */ +#define QMI_M1_TIMING_CLKDIV_Msk (0xffUL) /*!< CLKDIV (Bitfield-Mask: 0xff) */ +/* ======================================================== M1_RFMT ======================================================== */ +#define QMI_M1_RFMT_DTR_Pos (28UL) /*!< DTR (Bit 28) */ +#define QMI_M1_RFMT_DTR_Msk (0x10000000UL) /*!< DTR (Bitfield-Mask: 0x01) */ +#define QMI_M1_RFMT_DUMMY_LEN_Pos (16UL) /*!< DUMMY_LEN (Bit 16) */ +#define QMI_M1_RFMT_DUMMY_LEN_Msk (0x70000UL) /*!< DUMMY_LEN (Bitfield-Mask: 0x07) */ +#define QMI_M1_RFMT_SUFFIX_LEN_Pos (14UL) /*!< SUFFIX_LEN (Bit 14) */ +#define QMI_M1_RFMT_SUFFIX_LEN_Msk (0xc000UL) /*!< SUFFIX_LEN (Bitfield-Mask: 0x03) */ +#define QMI_M1_RFMT_PREFIX_LEN_Pos (12UL) /*!< PREFIX_LEN (Bit 12) */ +#define QMI_M1_RFMT_PREFIX_LEN_Msk (0x1000UL) /*!< PREFIX_LEN (Bitfield-Mask: 0x01) */ +#define QMI_M1_RFMT_DATA_WIDTH_Pos (8UL) /*!< DATA_WIDTH (Bit 8) */ +#define QMI_M1_RFMT_DATA_WIDTH_Msk (0x300UL) /*!< DATA_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M1_RFMT_DUMMY_WIDTH_Pos (6UL) /*!< DUMMY_WIDTH (Bit 6) */ +#define QMI_M1_RFMT_DUMMY_WIDTH_Msk (0xc0UL) /*!< DUMMY_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M1_RFMT_SUFFIX_WIDTH_Pos (4UL) /*!< SUFFIX_WIDTH (Bit 4) */ +#define QMI_M1_RFMT_SUFFIX_WIDTH_Msk (0x30UL) /*!< SUFFIX_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M1_RFMT_ADDR_WIDTH_Pos (2UL) /*!< ADDR_WIDTH (Bit 2) */ +#define QMI_M1_RFMT_ADDR_WIDTH_Msk (0xcUL) /*!< ADDR_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M1_RFMT_PREFIX_WIDTH_Pos (0UL) /*!< PREFIX_WIDTH (Bit 0) */ +#define QMI_M1_RFMT_PREFIX_WIDTH_Msk (0x3UL) /*!< PREFIX_WIDTH (Bitfield-Mask: 0x03) */ +/* ======================================================== M1_RCMD ======================================================== */ +#define QMI_M1_RCMD_SUFFIX_Pos (8UL) /*!< SUFFIX (Bit 8) */ +#define QMI_M1_RCMD_SUFFIX_Msk (0xff00UL) /*!< SUFFIX (Bitfield-Mask: 0xff) */ +#define QMI_M1_RCMD_PREFIX_Pos (0UL) /*!< PREFIX (Bit 0) */ +#define QMI_M1_RCMD_PREFIX_Msk (0xffUL) /*!< PREFIX (Bitfield-Mask: 0xff) */ +/* ======================================================== M1_WFMT ======================================================== */ +#define QMI_M1_WFMT_DTR_Pos (28UL) /*!< DTR (Bit 28) */ +#define QMI_M1_WFMT_DTR_Msk (0x10000000UL) /*!< DTR (Bitfield-Mask: 0x01) */ +#define QMI_M1_WFMT_DUMMY_LEN_Pos (16UL) /*!< DUMMY_LEN (Bit 16) */ +#define QMI_M1_WFMT_DUMMY_LEN_Msk (0x70000UL) /*!< DUMMY_LEN (Bitfield-Mask: 0x07) */ +#define QMI_M1_WFMT_SUFFIX_LEN_Pos (14UL) /*!< SUFFIX_LEN (Bit 14) */ +#define QMI_M1_WFMT_SUFFIX_LEN_Msk (0xc000UL) /*!< SUFFIX_LEN (Bitfield-Mask: 0x03) */ +#define QMI_M1_WFMT_PREFIX_LEN_Pos (12UL) /*!< PREFIX_LEN (Bit 12) */ +#define QMI_M1_WFMT_PREFIX_LEN_Msk (0x1000UL) /*!< PREFIX_LEN (Bitfield-Mask: 0x01) */ +#define QMI_M1_WFMT_DATA_WIDTH_Pos (8UL) /*!< DATA_WIDTH (Bit 8) */ +#define QMI_M1_WFMT_DATA_WIDTH_Msk (0x300UL) /*!< DATA_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M1_WFMT_DUMMY_WIDTH_Pos (6UL) /*!< DUMMY_WIDTH (Bit 6) */ +#define QMI_M1_WFMT_DUMMY_WIDTH_Msk (0xc0UL) /*!< DUMMY_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M1_WFMT_SUFFIX_WIDTH_Pos (4UL) /*!< SUFFIX_WIDTH (Bit 4) */ +#define QMI_M1_WFMT_SUFFIX_WIDTH_Msk (0x30UL) /*!< SUFFIX_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M1_WFMT_ADDR_WIDTH_Pos (2UL) /*!< ADDR_WIDTH (Bit 2) */ +#define QMI_M1_WFMT_ADDR_WIDTH_Msk (0xcUL) /*!< ADDR_WIDTH (Bitfield-Mask: 0x03) */ +#define QMI_M1_WFMT_PREFIX_WIDTH_Pos (0UL) /*!< PREFIX_WIDTH (Bit 0) */ +#define QMI_M1_WFMT_PREFIX_WIDTH_Msk (0x3UL) /*!< PREFIX_WIDTH (Bitfield-Mask: 0x03) */ +/* ======================================================== M1_WCMD ======================================================== */ +#define QMI_M1_WCMD_SUFFIX_Pos (8UL) /*!< SUFFIX (Bit 8) */ +#define QMI_M1_WCMD_SUFFIX_Msk (0xff00UL) /*!< SUFFIX (Bitfield-Mask: 0xff) */ +#define QMI_M1_WCMD_PREFIX_Pos (0UL) /*!< PREFIX (Bit 0) */ +#define QMI_M1_WCMD_PREFIX_Msk (0xffUL) /*!< PREFIX (Bitfield-Mask: 0xff) */ +/* ======================================================== ATRANS0 ======================================================== */ +#define QMI_ATRANS0_SIZE_Pos (16UL) /*!< SIZE (Bit 16) */ +#define QMI_ATRANS0_SIZE_Msk (0x7ff0000UL) /*!< SIZE (Bitfield-Mask: 0x7ff) */ +#define QMI_ATRANS0_BASE_Pos (0UL) /*!< BASE (Bit 0) */ +#define QMI_ATRANS0_BASE_Msk (0xfffUL) /*!< BASE (Bitfield-Mask: 0xfff) */ +/* ======================================================== ATRANS1 ======================================================== */ +#define QMI_ATRANS1_SIZE_Pos (16UL) /*!< SIZE (Bit 16) */ +#define QMI_ATRANS1_SIZE_Msk (0x7ff0000UL) /*!< SIZE (Bitfield-Mask: 0x7ff) */ +#define QMI_ATRANS1_BASE_Pos (0UL) /*!< BASE (Bit 0) */ +#define QMI_ATRANS1_BASE_Msk (0xfffUL) /*!< BASE (Bitfield-Mask: 0xfff) */ +/* ======================================================== ATRANS2 ======================================================== */ +#define QMI_ATRANS2_SIZE_Pos (16UL) /*!< SIZE (Bit 16) */ +#define QMI_ATRANS2_SIZE_Msk (0x7ff0000UL) /*!< SIZE (Bitfield-Mask: 0x7ff) */ +#define QMI_ATRANS2_BASE_Pos (0UL) /*!< BASE (Bit 0) */ +#define QMI_ATRANS2_BASE_Msk (0xfffUL) /*!< BASE (Bitfield-Mask: 0xfff) */ +/* ======================================================== ATRANS3 ======================================================== */ +#define QMI_ATRANS3_SIZE_Pos (16UL) /*!< SIZE (Bit 16) */ +#define QMI_ATRANS3_SIZE_Msk (0x7ff0000UL) /*!< SIZE (Bitfield-Mask: 0x7ff) */ +#define QMI_ATRANS3_BASE_Pos (0UL) /*!< BASE (Bit 0) */ +#define QMI_ATRANS3_BASE_Msk (0xfffUL) /*!< BASE (Bitfield-Mask: 0xfff) */ +/* ======================================================== ATRANS4 ======================================================== */ +#define QMI_ATRANS4_SIZE_Pos (16UL) /*!< SIZE (Bit 16) */ +#define QMI_ATRANS4_SIZE_Msk (0x7ff0000UL) /*!< SIZE (Bitfield-Mask: 0x7ff) */ +#define QMI_ATRANS4_BASE_Pos (0UL) /*!< BASE (Bit 0) */ +#define QMI_ATRANS4_BASE_Msk (0xfffUL) /*!< BASE (Bitfield-Mask: 0xfff) */ +/* ======================================================== ATRANS5 ======================================================== */ +#define QMI_ATRANS5_SIZE_Pos (16UL) /*!< SIZE (Bit 16) */ +#define QMI_ATRANS5_SIZE_Msk (0x7ff0000UL) /*!< SIZE (Bitfield-Mask: 0x7ff) */ +#define QMI_ATRANS5_BASE_Pos (0UL) /*!< BASE (Bit 0) */ +#define QMI_ATRANS5_BASE_Msk (0xfffUL) /*!< BASE (Bitfield-Mask: 0xfff) */ +/* ======================================================== ATRANS6 ======================================================== */ +#define QMI_ATRANS6_SIZE_Pos (16UL) /*!< SIZE (Bit 16) */ +#define QMI_ATRANS6_SIZE_Msk (0x7ff0000UL) /*!< SIZE (Bitfield-Mask: 0x7ff) */ +#define QMI_ATRANS6_BASE_Pos (0UL) /*!< BASE (Bit 0) */ +#define QMI_ATRANS6_BASE_Msk (0xfffUL) /*!< BASE (Bitfield-Mask: 0xfff) */ +/* ======================================================== ATRANS7 ======================================================== */ +#define QMI_ATRANS7_SIZE_Pos (16UL) /*!< SIZE (Bit 16) */ +#define QMI_ATRANS7_SIZE_Msk (0x7ff0000UL) /*!< SIZE (Bitfield-Mask: 0x7ff) */ +#define QMI_ATRANS7_BASE_Pos (0UL) /*!< BASE (Bit 0) */ +#define QMI_ATRANS7_BASE_Msk (0xfffUL) /*!< BASE (Bitfield-Mask: 0xfff) */ + + +/* =========================================================================================================================== */ +/* ================ XIP_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define XIP_CTRL_CTRL_WRITABLE_M1_Pos (11UL) /*!< WRITABLE_M1 (Bit 11) */ +#define XIP_CTRL_CTRL_WRITABLE_M1_Msk (0x800UL) /*!< WRITABLE_M1 (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_WRITABLE_M0_Pos (10UL) /*!< WRITABLE_M0 (Bit 10) */ +#define XIP_CTRL_CTRL_WRITABLE_M0_Msk (0x400UL) /*!< WRITABLE_M0 (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_SPLIT_WAYS_Pos (9UL) /*!< SPLIT_WAYS (Bit 9) */ +#define XIP_CTRL_CTRL_SPLIT_WAYS_Msk (0x200UL) /*!< SPLIT_WAYS (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_MAINT_NONSEC_Pos (8UL) /*!< MAINT_NONSEC (Bit 8) */ +#define XIP_CTRL_CTRL_MAINT_NONSEC_Msk (0x100UL) /*!< MAINT_NONSEC (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_NO_UNTRANSLATED_NONSEC_Pos (7UL) /*!< NO_UNTRANSLATED_NONSEC (Bit 7) */ +#define XIP_CTRL_CTRL_NO_UNTRANSLATED_NONSEC_Msk (0x80UL) /*!< NO_UNTRANSLATED_NONSEC (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_NO_UNTRANSLATED_SEC_Pos (6UL) /*!< NO_UNTRANSLATED_SEC (Bit 6) */ +#define XIP_CTRL_CTRL_NO_UNTRANSLATED_SEC_Msk (0x40UL) /*!< NO_UNTRANSLATED_SEC (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_NO_UNCACHED_NONSEC_Pos (5UL) /*!< NO_UNCACHED_NONSEC (Bit 5) */ +#define XIP_CTRL_CTRL_NO_UNCACHED_NONSEC_Msk (0x20UL) /*!< NO_UNCACHED_NONSEC (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_NO_UNCACHED_SEC_Pos (4UL) /*!< NO_UNCACHED_SEC (Bit 4) */ +#define XIP_CTRL_CTRL_NO_UNCACHED_SEC_Msk (0x10UL) /*!< NO_UNCACHED_SEC (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_POWER_DOWN_Pos (3UL) /*!< POWER_DOWN (Bit 3) */ +#define XIP_CTRL_CTRL_POWER_DOWN_Msk (0x8UL) /*!< POWER_DOWN (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_EN_NONSECURE_Pos (1UL) /*!< EN_NONSECURE (Bit 1) */ +#define XIP_CTRL_CTRL_EN_NONSECURE_Msk (0x2UL) /*!< EN_NONSECURE (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_CTRL_EN_SECURE_Pos (0UL) /*!< EN_SECURE (Bit 0) */ +#define XIP_CTRL_CTRL_EN_SECURE_Msk (0x1UL) /*!< EN_SECURE (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define XIP_CTRL_STAT_FIFO_FULL_Pos (2UL) /*!< FIFO_FULL (Bit 2) */ +#define XIP_CTRL_STAT_FIFO_FULL_Msk (0x4UL) /*!< FIFO_FULL (Bitfield-Mask: 0x01) */ +#define XIP_CTRL_STAT_FIFO_EMPTY_Pos (1UL) /*!< FIFO_EMPTY (Bit 1) */ +#define XIP_CTRL_STAT_FIFO_EMPTY_Msk (0x2UL) /*!< FIFO_EMPTY (Bitfield-Mask: 0x01) */ +/* ======================================================== CTR_HIT ======================================================== */ +#define XIP_CTRL_CTR_HIT_CTR_HIT_Pos (0UL) /*!< CTR_HIT (Bit 0) */ +#define XIP_CTRL_CTR_HIT_CTR_HIT_Msk (0xffffffffUL) /*!< CTR_HIT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CTR_ACC ======================================================== */ +#define XIP_CTRL_CTR_ACC_CTR_ACC_Pos (0UL) /*!< CTR_ACC (Bit 0) */ +#define XIP_CTRL_CTR_ACC_CTR_ACC_Msk (0xffffffffUL) /*!< CTR_ACC (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== STREAM_ADDR ====================================================== */ +#define XIP_CTRL_STREAM_ADDR_STREAM_ADDR_Pos (2UL) /*!< STREAM_ADDR (Bit 2) */ +#define XIP_CTRL_STREAM_ADDR_STREAM_ADDR_Msk (0xfffffffcUL) /*!< STREAM_ADDR (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== STREAM_CTR ======================================================= */ +#define XIP_CTRL_STREAM_CTR_STREAM_CTR_Pos (0UL) /*!< STREAM_CTR (Bit 0) */ +#define XIP_CTRL_STREAM_CTR_STREAM_CTR_Msk (0x3fffffUL) /*!< STREAM_CTR (Bitfield-Mask: 0x3fffff) */ +/* ====================================================== STREAM_FIFO ====================================================== */ +#define XIP_CTRL_STREAM_FIFO_STREAM_FIFO_Pos (0UL) /*!< STREAM_FIFO (Bit 0) */ +#define XIP_CTRL_STREAM_FIFO_STREAM_FIFO_Msk (0xffffffffUL) /*!< STREAM_FIFO (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ XIP_AUX ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== STREAM ========================================================= */ +#define XIP_AUX_STREAM_STREAM_Pos (0UL) /*!< STREAM (Bit 0) */ +#define XIP_AUX_STREAM_STREAM_Msk (0xffffffffUL) /*!< STREAM (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== QMI_DIRECT_TX ===================================================== */ +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_Pos (20UL) /*!< NOPUSH (Bit 20) */ +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_Msk (0x100000UL) /*!< NOPUSH (Bitfield-Mask: 0x01) */ +#define XIP_AUX_QMI_DIRECT_TX_OE_Pos (19UL) /*!< OE (Bit 19) */ +#define XIP_AUX_QMI_DIRECT_TX_OE_Msk (0x80000UL) /*!< OE (Bitfield-Mask: 0x01) */ +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_Pos (18UL) /*!< DWIDTH (Bit 18) */ +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_Msk (0x40000UL) /*!< DWIDTH (Bitfield-Mask: 0x01) */ +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_Pos (16UL) /*!< IWIDTH (Bit 16) */ +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_Msk (0x30000UL) /*!< IWIDTH (Bitfield-Mask: 0x03) */ +#define XIP_AUX_QMI_DIRECT_TX_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define XIP_AUX_QMI_DIRECT_TX_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ===================================================== QMI_DIRECT_RX ===================================================== */ +#define XIP_AUX_QMI_DIRECT_RX_QMI_DIRECT_RX_Pos (0UL) /*!< QMI_DIRECT_RX (Bit 0) */ +#define XIP_AUX_QMI_DIRECT_RX_QMI_DIRECT_RX_Msk (0xffffUL) /*!< QMI_DIRECT_RX (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== PROC_CONFIG ====================================================== */ +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_Pos (1UL) /*!< PROC1_HALTED (Bit 1) */ +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_Msk (0x2UL) /*!< PROC1_HALTED (Bitfield-Mask: 0x01) */ +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_Pos (0UL) /*!< PROC0_HALTED (Bit 0) */ +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_Msk (0x1UL) /*!< PROC0_HALTED (Bitfield-Mask: 0x01) */ +/* ================================================== PROC_IN_SYNC_BYPASS ================================================== */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_Msk (0xffffffffUL) /*!< GPIO (Bitfield-Mask: 0xffffffff) */ +/* ================================================ PROC_IN_SYNC_BYPASS_HI ================================================= */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ======================================================= DBGFORCE ======================================================== */ +#define SYSCFG_DBGFORCE_ATTACH_Pos (3UL) /*!< ATTACH (Bit 3) */ +#define SYSCFG_DBGFORCE_ATTACH_Msk (0x8UL) /*!< ATTACH (Bitfield-Mask: 0x01) */ +#define SYSCFG_DBGFORCE_SWCLK_Pos (2UL) /*!< SWCLK (Bit 2) */ +#define SYSCFG_DBGFORCE_SWCLK_Msk (0x4UL) /*!< SWCLK (Bitfield-Mask: 0x01) */ +#define SYSCFG_DBGFORCE_SWDI_Pos (1UL) /*!< SWDI (Bit 1) */ +#define SYSCFG_DBGFORCE_SWDI_Msk (0x2UL) /*!< SWDI (Bitfield-Mask: 0x01) */ +#define SYSCFG_DBGFORCE_SWDO_Pos (0UL) /*!< SWDO (Bit 0) */ +#define SYSCFG_DBGFORCE_SWDO_Msk (0x1UL) /*!< SWDO (Bitfield-Mask: 0x01) */ +/* ===================================================== MEMPOWERDOWN ====================================================== */ +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_Pos (12UL) /*!< BOOTRAM (Bit 12) */ +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_Msk (0x1000UL) /*!< BOOTRAM (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_ROM_Pos (11UL) /*!< ROM (Bit 11) */ +#define SYSCFG_MEMPOWERDOWN_ROM_Msk (0x800UL) /*!< ROM (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_USB_Pos (10UL) /*!< USB (Bit 10) */ +#define SYSCFG_MEMPOWERDOWN_USB_Msk (0x400UL) /*!< USB (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM9_Pos (9UL) /*!< SRAM9 (Bit 9) */ +#define SYSCFG_MEMPOWERDOWN_SRAM9_Msk (0x200UL) /*!< SRAM9 (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM8_Pos (8UL) /*!< SRAM8 (Bit 8) */ +#define SYSCFG_MEMPOWERDOWN_SRAM8_Msk (0x100UL) /*!< SRAM8 (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM7_Pos (7UL) /*!< SRAM7 (Bit 7) */ +#define SYSCFG_MEMPOWERDOWN_SRAM7_Msk (0x80UL) /*!< SRAM7 (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM6_Pos (6UL) /*!< SRAM6 (Bit 6) */ +#define SYSCFG_MEMPOWERDOWN_SRAM6_Msk (0x40UL) /*!< SRAM6 (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM5_Pos (5UL) /*!< SRAM5 (Bit 5) */ +#define SYSCFG_MEMPOWERDOWN_SRAM5_Msk (0x20UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM4_Pos (4UL) /*!< SRAM4 (Bit 4) */ +#define SYSCFG_MEMPOWERDOWN_SRAM4_Msk (0x10UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM3_Pos (3UL) /*!< SRAM3 (Bit 3) */ +#define SYSCFG_MEMPOWERDOWN_SRAM3_Msk (0x8UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM2_Pos (2UL) /*!< SRAM2 (Bit 2) */ +#define SYSCFG_MEMPOWERDOWN_SRAM2_Msk (0x4UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM1_Pos (1UL) /*!< SRAM1 (Bit 1) */ +#define SYSCFG_MEMPOWERDOWN_SRAM1_Msk (0x2UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */ +#define SYSCFG_MEMPOWERDOWN_SRAM0_Pos (0UL) /*!< SRAM0 (Bit 0) */ +#define SYSCFG_MEMPOWERDOWN_SRAM0_Msk (0x1UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */ +/* ======================================================== AUXCTRL ======================================================== */ +#define SYSCFG_AUXCTRL_AUXCTRL_Pos (0UL) /*!< AUXCTRL (Bit 0) */ +#define SYSCFG_AUXCTRL_AUXCTRL_Msk (0xffUL) /*!< AUXCTRL (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ XOSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define XOSC_CTRL_ENABLE_Pos (12UL) /*!< ENABLE (Bit 12) */ +#define XOSC_CTRL_ENABLE_Msk (0xfff000UL) /*!< ENABLE (Bitfield-Mask: 0xfff) */ +#define XOSC_CTRL_FREQ_RANGE_Pos (0UL) /*!< FREQ_RANGE (Bit 0) */ +#define XOSC_CTRL_FREQ_RANGE_Msk (0xfffUL) /*!< FREQ_RANGE (Bitfield-Mask: 0xfff) */ +/* ======================================================== STATUS ========================================================= */ +#define XOSC_STATUS_STABLE_Pos (31UL) /*!< STABLE (Bit 31) */ +#define XOSC_STATUS_STABLE_Msk (0x80000000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define XOSC_STATUS_BADWRITE_Pos (24UL) /*!< BADWRITE (Bit 24) */ +#define XOSC_STATUS_BADWRITE_Msk (0x1000000UL) /*!< BADWRITE (Bitfield-Mask: 0x01) */ +#define XOSC_STATUS_ENABLED_Pos (12UL) /*!< ENABLED (Bit 12) */ +#define XOSC_STATUS_ENABLED_Msk (0x1000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +#define XOSC_STATUS_FREQ_RANGE_Pos (0UL) /*!< FREQ_RANGE (Bit 0) */ +#define XOSC_STATUS_FREQ_RANGE_Msk (0x3UL) /*!< FREQ_RANGE (Bitfield-Mask: 0x03) */ +/* ======================================================== DORMANT ======================================================== */ +#define XOSC_DORMANT_DORMANT_Pos (0UL) /*!< DORMANT (Bit 0) */ +#define XOSC_DORMANT_DORMANT_Msk (0xffffffffUL) /*!< DORMANT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== STARTUP ======================================================== */ +#define XOSC_STARTUP_X4_Pos (20UL) /*!< X4 (Bit 20) */ +#define XOSC_STARTUP_X4_Msk (0x100000UL) /*!< X4 (Bitfield-Mask: 0x01) */ +#define XOSC_STARTUP_DELAY_Pos (0UL) /*!< DELAY (Bit 0) */ +#define XOSC_STARTUP_DELAY_Msk (0x3fffUL) /*!< DELAY (Bitfield-Mask: 0x3fff) */ +/* ========================================================= COUNT ========================================================= */ +#define XOSC_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define XOSC_COUNT_COUNT_Msk (0xffffUL) /*!< COUNT (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ PLL_SYS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CS =========================================================== */ +#define PLL_SYS_CS_LOCK_Pos (31UL) /*!< LOCK (Bit 31) */ +#define PLL_SYS_CS_LOCK_Msk (0x80000000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define PLL_SYS_CS_LOCK_N_Pos (30UL) /*!< LOCK_N (Bit 30) */ +#define PLL_SYS_CS_LOCK_N_Msk (0x40000000UL) /*!< LOCK_N (Bitfield-Mask: 0x01) */ +#define PLL_SYS_CS_BYPASS_Pos (8UL) /*!< BYPASS (Bit 8) */ +#define PLL_SYS_CS_BYPASS_Msk (0x100UL) /*!< BYPASS (Bitfield-Mask: 0x01) */ +#define PLL_SYS_CS_REFDIV_Pos (0UL) /*!< REFDIV (Bit 0) */ +#define PLL_SYS_CS_REFDIV_Msk (0x3fUL) /*!< REFDIV (Bitfield-Mask: 0x3f) */ +/* ========================================================== PWR ========================================================== */ +#define PLL_SYS_PWR_VCOPD_Pos (5UL) /*!< VCOPD (Bit 5) */ +#define PLL_SYS_PWR_VCOPD_Msk (0x20UL) /*!< VCOPD (Bitfield-Mask: 0x01) */ +#define PLL_SYS_PWR_POSTDIVPD_Pos (3UL) /*!< POSTDIVPD (Bit 3) */ +#define PLL_SYS_PWR_POSTDIVPD_Msk (0x8UL) /*!< POSTDIVPD (Bitfield-Mask: 0x01) */ +#define PLL_SYS_PWR_DSMPD_Pos (2UL) /*!< DSMPD (Bit 2) */ +#define PLL_SYS_PWR_DSMPD_Msk (0x4UL) /*!< DSMPD (Bitfield-Mask: 0x01) */ +#define PLL_SYS_PWR_PD_Pos (0UL) /*!< PD (Bit 0) */ +#define PLL_SYS_PWR_PD_Msk (0x1UL) /*!< PD (Bitfield-Mask: 0x01) */ +/* ======================================================= FBDIV_INT ======================================================= */ +#define PLL_SYS_FBDIV_INT_FBDIV_INT_Pos (0UL) /*!< FBDIV_INT (Bit 0) */ +#define PLL_SYS_FBDIV_INT_FBDIV_INT_Msk (0xfffUL) /*!< FBDIV_INT (Bitfield-Mask: 0xfff) */ +/* ========================================================= PRIM ========================================================== */ +#define PLL_SYS_PRIM_POSTDIV1_Pos (16UL) /*!< POSTDIV1 (Bit 16) */ +#define PLL_SYS_PRIM_POSTDIV1_Msk (0x70000UL) /*!< POSTDIV1 (Bitfield-Mask: 0x07) */ +#define PLL_SYS_PRIM_POSTDIV2_Pos (12UL) /*!< POSTDIV2 (Bit 12) */ +#define PLL_SYS_PRIM_POSTDIV2_Msk (0x7000UL) /*!< POSTDIV2 (Bitfield-Mask: 0x07) */ +/* ========================================================= INTR ========================================================== */ +#define PLL_SYS_INTR_LOCK_N_STICKY_Pos (0UL) /*!< LOCK_N_STICKY (Bit 0) */ +#define PLL_SYS_INTR_LOCK_N_STICKY_Msk (0x1UL) /*!< LOCK_N_STICKY (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ +#define PLL_SYS_INTE_LOCK_N_STICKY_Pos (0UL) /*!< LOCK_N_STICKY (Bit 0) */ +#define PLL_SYS_INTE_LOCK_N_STICKY_Msk (0x1UL) /*!< LOCK_N_STICKY (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define PLL_SYS_INTF_LOCK_N_STICKY_Pos (0UL) /*!< LOCK_N_STICKY (Bit 0) */ +#define PLL_SYS_INTF_LOCK_N_STICKY_Msk (0x1UL) /*!< LOCK_N_STICKY (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ +#define PLL_SYS_INTS_LOCK_N_STICKY_Pos (0UL) /*!< LOCK_N_STICKY (Bit 0) */ +#define PLL_SYS_INTS_LOCK_N_STICKY_Msk (0x1UL) /*!< LOCK_N_STICKY (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ ACCESSCTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LOCK ========================================================== */ +#define ACCESSCTRL_LOCK_DEBUG_Pos (3UL) /*!< DEBUG (Bit 3) */ +#define ACCESSCTRL_LOCK_DEBUG_Msk (0x8UL) /*!< DEBUG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_LOCK_DMA_Pos (2UL) /*!< DMA (Bit 2) */ +#define ACCESSCTRL_LOCK_DMA_Msk (0x4UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_LOCK_CORE1_Pos (1UL) /*!< CORE1 (Bit 1) */ +#define ACCESSCTRL_LOCK_CORE1_Msk (0x2UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_LOCK_CORE0_Pos (0UL) /*!< CORE0 (Bit 0) */ +#define ACCESSCTRL_LOCK_CORE0_Msk (0x1UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +/* ===================================================== FORCE_CORE_NS ===================================================== */ +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_Pos (1UL) /*!< CORE1 (Bit 1) */ +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_Msk (0x2UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFGRESET ======================================================== */ +#define ACCESSCTRL_CFGRESET_CFGRESET_Pos (0UL) /*!< CFGRESET (Bit 0) */ +#define ACCESSCTRL_CFGRESET_CFGRESET_Msk (0x1UL) /*!< CFGRESET (Bitfield-Mask: 0x01) */ +/* ===================================================== GPIO_NSMASK0 ====================================================== */ +#define ACCESSCTRL_GPIO_NSMASK0_GPIO_NSMASK0_Pos (0UL) /*!< GPIO_NSMASK0 (Bit 0) */ +#define ACCESSCTRL_GPIO_NSMASK0_GPIO_NSMASK0_Msk (0xffffffffUL) /*!< GPIO_NSMASK0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== GPIO_NSMASK1 ====================================================== */ +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ========================================================== ROM ========================================================== */ +#define ACCESSCTRL_ROM_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_ROM_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROM_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_ROM_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROM_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_ROM_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROM_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_ROM_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROM_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_ROM_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROM_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_ROM_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROM_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_ROM_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROM_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_ROM_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================= XIP_MAIN ======================================================== */ +#define ACCESSCTRL_XIP_MAIN_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_XIP_MAIN_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_MAIN_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_XIP_MAIN_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_MAIN_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_XIP_MAIN_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_MAIN_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_XIP_MAIN_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_MAIN_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_XIP_MAIN_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_MAIN_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_XIP_MAIN_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_MAIN_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_XIP_MAIN_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_MAIN_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_XIP_MAIN_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM0 ========================================================= */ +#define ACCESSCTRL_SRAM0_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM0_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM0_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM0_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM0_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM0_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM0_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM0_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM0_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM0_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM0_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM0_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM0_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM0_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM0_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM0_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM1 ========================================================= */ +#define ACCESSCTRL_SRAM1_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM1_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM1_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM1_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM1_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM1_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM1_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM1_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM1_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM1_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM1_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM1_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM1_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM1_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM1_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM1_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM2 ========================================================= */ +#define ACCESSCTRL_SRAM2_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM2_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM2_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM2_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM2_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM2_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM2_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM2_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM2_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM2_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM2_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM2_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM2_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM2_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM2_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM3 ========================================================= */ +#define ACCESSCTRL_SRAM3_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM3_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM3_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM3_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM3_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM3_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM3_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM3_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM3_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM3_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM3_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM3_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM3_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM3_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM3_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM3_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM4 ========================================================= */ +#define ACCESSCTRL_SRAM4_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM4_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM4_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM4_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM4_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM4_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM4_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM4_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM4_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM4_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM4_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM4_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM4_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM4_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM4_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM4_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM5 ========================================================= */ +#define ACCESSCTRL_SRAM5_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM5_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM5_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM5_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM5_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM5_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM5_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM5_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM5_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM5_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM5_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM5_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM5_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM5_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM5_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM5_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM6 ========================================================= */ +#define ACCESSCTRL_SRAM6_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM6_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM6_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM6_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM6_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM6_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM6_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM6_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM6_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM6_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM6_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM6_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM6_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM6_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM6_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM6_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM7 ========================================================= */ +#define ACCESSCTRL_SRAM7_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM7_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM7_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM7_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM7_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM7_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM7_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM7_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM7_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM7_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM7_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM7_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM7_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM7_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM7_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM7_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM8 ========================================================= */ +#define ACCESSCTRL_SRAM8_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM8_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM8_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM8_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM8_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM8_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM8_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM8_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM8_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM8_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM8_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM8_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM8_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM8_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM8_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM8_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SRAM9 ========================================================= */ +#define ACCESSCTRL_SRAM9_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SRAM9_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM9_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SRAM9_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM9_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SRAM9_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM9_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SRAM9_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM9_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SRAM9_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM9_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SRAM9_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM9_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SRAM9_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SRAM9_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SRAM9_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================== DMA ========================================================== */ +#define ACCESSCTRL_DMA_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_DMA_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_DMA_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_DMA_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_DMA_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_DMA_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_DMA_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_DMA_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_DMA_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_DMA_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_DMA_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_DMA_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_DMA_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_DMA_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_DMA_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_DMA_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== USBCTRL ======================================================== */ +#define ACCESSCTRL_USBCTRL_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_USBCTRL_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_USBCTRL_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_USBCTRL_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_USBCTRL_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_USBCTRL_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_USBCTRL_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_USBCTRL_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_USBCTRL_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_USBCTRL_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_USBCTRL_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_USBCTRL_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_USBCTRL_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_USBCTRL_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_USBCTRL_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_USBCTRL_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= PIO0 ========================================================== */ +#define ACCESSCTRL_PIO0_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_PIO0_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO0_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_PIO0_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO0_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_PIO0_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO0_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_PIO0_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO0_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_PIO0_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO0_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_PIO0_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO0_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_PIO0_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO0_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_PIO0_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= PIO1 ========================================================== */ +#define ACCESSCTRL_PIO1_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_PIO1_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO1_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_PIO1_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO1_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_PIO1_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO1_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_PIO1_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO1_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_PIO1_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO1_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_PIO1_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO1_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_PIO1_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO1_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_PIO1_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= PIO2 ========================================================== */ +#define ACCESSCTRL_PIO2_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_PIO2_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO2_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_PIO2_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO2_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_PIO2_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO2_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_PIO2_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO2_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_PIO2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO2_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_PIO2_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO2_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_PIO2_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PIO2_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_PIO2_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ==================================================== CORESIGHT_TRACE ==================================================== */ +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_TRACE_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_CORESIGHT_TRACE_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_TRACE_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_CORESIGHT_TRACE_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* =================================================== CORESIGHT_PERIPH ==================================================== */ +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== SYSINFO ======================================================== */ +#define ACCESSCTRL_SYSINFO_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SYSINFO_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSINFO_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SYSINFO_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSINFO_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SYSINFO_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSINFO_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SYSINFO_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSINFO_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SYSINFO_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSINFO_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SYSINFO_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSINFO_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SYSINFO_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSINFO_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SYSINFO_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== RESETS ========================================================= */ +#define ACCESSCTRL_RESETS_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_RESETS_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RESETS_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_RESETS_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RESETS_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_RESETS_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RESETS_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_RESETS_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RESETS_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_RESETS_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RESETS_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_RESETS_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RESETS_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_RESETS_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RESETS_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_RESETS_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================= IO_BANK0 ======================================================== */ +#define ACCESSCTRL_IO_BANK0_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_IO_BANK0_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK0_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_IO_BANK0_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK0_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_IO_BANK0_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK0_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_IO_BANK0_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK0_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_IO_BANK0_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK0_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_IO_BANK0_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK0_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_IO_BANK0_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK0_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_IO_BANK0_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================= IO_BANK1 ======================================================== */ +#define ACCESSCTRL_IO_BANK1_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_IO_BANK1_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK1_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_IO_BANK1_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK1_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_IO_BANK1_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK1_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_IO_BANK1_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK1_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_IO_BANK1_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK1_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_IO_BANK1_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK1_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_IO_BANK1_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_IO_BANK1_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_IO_BANK1_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ====================================================== PADS_BANK0 ======================================================= */ +#define ACCESSCTRL_PADS_BANK0_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_PADS_BANK0_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_BANK0_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_PADS_BANK0_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_BANK0_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_PADS_BANK0_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_BANK0_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_PADS_BANK0_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_BANK0_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_PADS_BANK0_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_BANK0_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_PADS_BANK0_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_BANK0_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_PADS_BANK0_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_BANK0_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_PADS_BANK0_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================= PADS_QSPI ======================================================= */ +#define ACCESSCTRL_PADS_QSPI_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_PADS_QSPI_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_QSPI_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_PADS_QSPI_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_QSPI_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_PADS_QSPI_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_QSPI_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_PADS_QSPI_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_QSPI_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_PADS_QSPI_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_QSPI_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_PADS_QSPI_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_QSPI_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_PADS_QSPI_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PADS_QSPI_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_PADS_QSPI_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSCTRL ======================================================== */ +#define ACCESSCTRL_BUSCTRL_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_BUSCTRL_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_BUSCTRL_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_BUSCTRL_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_BUSCTRL_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_BUSCTRL_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_BUSCTRL_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_BUSCTRL_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_BUSCTRL_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_BUSCTRL_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_BUSCTRL_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_BUSCTRL_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_BUSCTRL_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_BUSCTRL_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_BUSCTRL_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_BUSCTRL_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= ADC0 ========================================================== */ +#define ACCESSCTRL_ADC0_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_ADC0_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ADC0_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_ADC0_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ADC0_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_ADC0_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ADC0_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_ADC0_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ADC0_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_ADC0_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ADC0_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_ADC0_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ADC0_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_ADC0_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ADC0_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_ADC0_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= HSTX ========================================================== */ +#define ACCESSCTRL_HSTX_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_HSTX_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_HSTX_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_HSTX_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_HSTX_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_HSTX_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_HSTX_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_HSTX_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_HSTX_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_HSTX_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_HSTX_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_HSTX_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_HSTX_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_HSTX_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_HSTX_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_HSTX_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= I2C0 ========================================================== */ +#define ACCESSCTRL_I2C0_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_I2C0_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C0_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_I2C0_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C0_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_I2C0_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C0_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_I2C0_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C0_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_I2C0_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C0_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_I2C0_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C0_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_I2C0_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C0_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_I2C0_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= I2C1 ========================================================== */ +#define ACCESSCTRL_I2C1_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_I2C1_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C1_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_I2C1_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C1_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_I2C1_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C1_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_I2C1_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C1_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_I2C1_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C1_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_I2C1_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C1_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_I2C1_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_I2C1_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_I2C1_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================== PWM ========================================================== */ +#define ACCESSCTRL_PWM_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_PWM_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PWM_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_PWM_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PWM_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_PWM_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PWM_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_PWM_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PWM_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_PWM_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PWM_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_PWM_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PWM_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_PWM_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PWM_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_PWM_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SPI0 ========================================================== */ +#define ACCESSCTRL_SPI0_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SPI0_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI0_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SPI0_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI0_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SPI0_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI0_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SPI0_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI0_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SPI0_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI0_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SPI0_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI0_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SPI0_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI0_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SPI0_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= SPI1 ========================================================== */ +#define ACCESSCTRL_SPI1_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SPI1_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI1_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SPI1_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI1_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SPI1_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI1_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SPI1_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI1_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SPI1_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI1_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SPI1_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI1_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SPI1_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SPI1_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SPI1_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== TIMER0 ========================================================= */ +#define ACCESSCTRL_TIMER0_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_TIMER0_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER0_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_TIMER0_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER0_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_TIMER0_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER0_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_TIMER0_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER0_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_TIMER0_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER0_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_TIMER0_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER0_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_TIMER0_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER0_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_TIMER0_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== TIMER1 ========================================================= */ +#define ACCESSCTRL_TIMER1_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_TIMER1_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER1_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_TIMER1_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER1_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_TIMER1_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER1_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_TIMER1_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER1_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_TIMER1_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER1_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_TIMER1_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER1_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_TIMER1_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TIMER1_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_TIMER1_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= UART0 ========================================================= */ +#define ACCESSCTRL_UART0_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_UART0_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART0_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_UART0_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART0_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_UART0_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART0_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_UART0_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART0_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_UART0_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART0_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_UART0_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART0_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_UART0_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART0_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_UART0_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= UART1 ========================================================= */ +#define ACCESSCTRL_UART1_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_UART1_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART1_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_UART1_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART1_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_UART1_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART1_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_UART1_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART1_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_UART1_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART1_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_UART1_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART1_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_UART1_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_UART1_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_UART1_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================== OTP ========================================================== */ +#define ACCESSCTRL_OTP_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_OTP_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_OTP_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_OTP_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_OTP_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_OTP_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_OTP_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_OTP_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_OTP_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_OTP_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_OTP_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_OTP_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_OTP_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_OTP_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_OTP_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_OTP_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= TBMAN ========================================================= */ +#define ACCESSCTRL_TBMAN_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_TBMAN_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TBMAN_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_TBMAN_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TBMAN_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_TBMAN_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TBMAN_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_TBMAN_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TBMAN_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_TBMAN_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TBMAN_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_TBMAN_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TBMAN_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_TBMAN_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TBMAN_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_TBMAN_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== POWMAN ========================================================= */ +#define ACCESSCTRL_POWMAN_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_POWMAN_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_POWMAN_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_POWMAN_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_POWMAN_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_POWMAN_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_POWMAN_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_POWMAN_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_POWMAN_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_POWMAN_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_POWMAN_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_POWMAN_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_POWMAN_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_POWMAN_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_POWMAN_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_POWMAN_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= TRNG ========================================================== */ +#define ACCESSCTRL_TRNG_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_TRNG_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TRNG_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_TRNG_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TRNG_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_TRNG_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TRNG_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_TRNG_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TRNG_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_TRNG_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TRNG_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_TRNG_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TRNG_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_TRNG_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TRNG_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_TRNG_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== SHA256 ========================================================= */ +#define ACCESSCTRL_SHA256_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SHA256_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SHA256_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SHA256_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SHA256_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SHA256_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SHA256_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SHA256_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SHA256_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SHA256_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SHA256_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SHA256_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SHA256_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SHA256_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SHA256_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SHA256_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== SYSCFG ========================================================= */ +#define ACCESSCTRL_SYSCFG_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_SYSCFG_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSCFG_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_SYSCFG_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSCFG_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_SYSCFG_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSCFG_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_SYSCFG_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSCFG_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_SYSCFG_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSCFG_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_SYSCFG_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSCFG_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_SYSCFG_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_SYSCFG_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_SYSCFG_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== CLOCKS ========================================================= */ +#define ACCESSCTRL_CLOCKS_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_CLOCKS_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CLOCKS_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_CLOCKS_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CLOCKS_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_CLOCKS_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CLOCKS_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_CLOCKS_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CLOCKS_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_CLOCKS_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CLOCKS_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_CLOCKS_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CLOCKS_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_CLOCKS_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_CLOCKS_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_CLOCKS_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= XOSC ========================================================== */ +#define ACCESSCTRL_XOSC_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_XOSC_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XOSC_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_XOSC_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XOSC_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_XOSC_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XOSC_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_XOSC_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XOSC_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_XOSC_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XOSC_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_XOSC_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XOSC_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_XOSC_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XOSC_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_XOSC_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= ROSC ========================================================== */ +#define ACCESSCTRL_ROSC_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_ROSC_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROSC_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_ROSC_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROSC_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_ROSC_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROSC_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_ROSC_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROSC_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_ROSC_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROSC_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_ROSC_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROSC_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_ROSC_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_ROSC_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_ROSC_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL_SYS ======================================================== */ +#define ACCESSCTRL_PLL_SYS_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_PLL_SYS_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_SYS_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_PLL_SYS_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_SYS_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_PLL_SYS_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_SYS_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_PLL_SYS_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_SYS_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_PLL_SYS_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_SYS_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_PLL_SYS_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_SYS_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_PLL_SYS_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_SYS_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_PLL_SYS_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL_USB ======================================================== */ +#define ACCESSCTRL_PLL_USB_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_PLL_USB_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_USB_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_PLL_USB_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_USB_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_PLL_USB_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_USB_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_PLL_USB_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_USB_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_PLL_USB_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_USB_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_PLL_USB_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_USB_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_PLL_USB_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_PLL_USB_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_PLL_USB_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================= TICKS ========================================================= */ +#define ACCESSCTRL_TICKS_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_TICKS_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TICKS_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_TICKS_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TICKS_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_TICKS_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TICKS_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_TICKS_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TICKS_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_TICKS_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TICKS_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_TICKS_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TICKS_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_TICKS_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_TICKS_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_TICKS_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================= WATCHDOG ======================================================== */ +#define ACCESSCTRL_WATCHDOG_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_WATCHDOG_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_WATCHDOG_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_WATCHDOG_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_WATCHDOG_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_WATCHDOG_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_WATCHDOG_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_WATCHDOG_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_WATCHDOG_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_WATCHDOG_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_WATCHDOG_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_WATCHDOG_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_WATCHDOG_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_WATCHDOG_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_WATCHDOG_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_WATCHDOG_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ========================================================== RSM ========================================================== */ +#define ACCESSCTRL_RSM_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_RSM_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RSM_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_RSM_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RSM_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_RSM_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RSM_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_RSM_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RSM_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_RSM_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RSM_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_RSM_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RSM_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_RSM_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_RSM_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_RSM_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================= XIP_CTRL ======================================================== */ +#define ACCESSCTRL_XIP_CTRL_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_XIP_CTRL_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_CTRL_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_XIP_CTRL_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_CTRL_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_XIP_CTRL_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_CTRL_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_XIP_CTRL_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_CTRL_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_XIP_CTRL_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_CTRL_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_XIP_CTRL_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_CTRL_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_XIP_CTRL_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_CTRL_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_XIP_CTRL_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== XIP_QMI ======================================================== */ +#define ACCESSCTRL_XIP_QMI_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_XIP_QMI_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_QMI_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_XIP_QMI_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_QMI_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_XIP_QMI_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_QMI_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_XIP_QMI_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_QMI_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_XIP_QMI_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_QMI_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_XIP_QMI_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_QMI_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_XIP_QMI_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_QMI_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_XIP_QMI_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ +/* ======================================================== XIP_AUX ======================================================== */ +#define ACCESSCTRL_XIP_AUX_DBG_Pos (7UL) /*!< DBG (Bit 7) */ +#define ACCESSCTRL_XIP_AUX_DBG_Msk (0x80UL) /*!< DBG (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_AUX_DMA_Pos (6UL) /*!< DMA (Bit 6) */ +#define ACCESSCTRL_XIP_AUX_DMA_Msk (0x40UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_AUX_CORE1_Pos (5UL) /*!< CORE1 (Bit 5) */ +#define ACCESSCTRL_XIP_AUX_CORE1_Msk (0x20UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_AUX_CORE0_Pos (4UL) /*!< CORE0 (Bit 4) */ +#define ACCESSCTRL_XIP_AUX_CORE0_Msk (0x10UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_AUX_SP_Pos (3UL) /*!< SP (Bit 3) */ +#define ACCESSCTRL_XIP_AUX_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_AUX_SU_Pos (2UL) /*!< SU (Bit 2) */ +#define ACCESSCTRL_XIP_AUX_SU_Msk (0x4UL) /*!< SU (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_AUX_NSP_Pos (1UL) /*!< NSP (Bit 1) */ +#define ACCESSCTRL_XIP_AUX_NSP_Msk (0x2UL) /*!< NSP (Bitfield-Mask: 0x01) */ +#define ACCESSCTRL_XIP_AUX_NSU_Pos (0UL) /*!< NSU (Bit 0) */ +#define ACCESSCTRL_XIP_AUX_NSU_Msk (0x1UL) /*!< NSU (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== UARTDR ========================================================= */ +#define UART0_UARTDR_OE_Pos (11UL) /*!< OE (Bit 11) */ +#define UART0_UARTDR_OE_Msk (0x800UL) /*!< OE (Bitfield-Mask: 0x01) */ +#define UART0_UARTDR_BE_Pos (10UL) /*!< BE (Bit 10) */ +#define UART0_UARTDR_BE_Msk (0x400UL) /*!< BE (Bitfield-Mask: 0x01) */ +#define UART0_UARTDR_PE_Pos (9UL) /*!< PE (Bit 9) */ +#define UART0_UARTDR_PE_Msk (0x200UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART0_UARTDR_FE_Pos (8UL) /*!< FE (Bit 8) */ +#define UART0_UARTDR_FE_Msk (0x100UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UART0_UARTDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define UART0_UARTDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ======================================================== UARTRSR ======================================================== */ +#define UART0_UARTRSR_OE_Pos (3UL) /*!< OE (Bit 3) */ +#define UART0_UARTRSR_OE_Msk (0x8UL) /*!< OE (Bitfield-Mask: 0x01) */ +#define UART0_UARTRSR_BE_Pos (2UL) /*!< BE (Bit 2) */ +#define UART0_UARTRSR_BE_Msk (0x4UL) /*!< BE (Bitfield-Mask: 0x01) */ +#define UART0_UARTRSR_PE_Pos (1UL) /*!< PE (Bit 1) */ +#define UART0_UARTRSR_PE_Msk (0x2UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART0_UARTRSR_FE_Pos (0UL) /*!< FE (Bit 0) */ +#define UART0_UARTRSR_FE_Msk (0x1UL) /*!< FE (Bitfield-Mask: 0x01) */ +/* ======================================================== UARTFR ========================================================= */ +#define UART0_UARTFR_RI_Pos (8UL) /*!< RI (Bit 8) */ +#define UART0_UARTFR_RI_Msk (0x100UL) /*!< RI (Bitfield-Mask: 0x01) */ +#define UART0_UARTFR_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ +#define UART0_UARTFR_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ +#define UART0_UARTFR_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */ +#define UART0_UARTFR_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */ +#define UART0_UARTFR_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */ +#define UART0_UARTFR_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */ +#define UART0_UARTFR_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */ +#define UART0_UARTFR_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */ +#define UART0_UARTFR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */ +#define UART0_UARTFR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define UART0_UARTFR_DCD_Pos (2UL) /*!< DCD (Bit 2) */ +#define UART0_UARTFR_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */ +#define UART0_UARTFR_DSR_Pos (1UL) /*!< DSR (Bit 1) */ +#define UART0_UARTFR_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */ +#define UART0_UARTFR_CTS_Pos (0UL) /*!< CTS (Bit 0) */ +#define UART0_UARTFR_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */ +/* ======================================================= UARTILPR ======================================================== */ +#define UART0_UARTILPR_ILPDVSR_Pos (0UL) /*!< ILPDVSR (Bit 0) */ +#define UART0_UARTILPR_ILPDVSR_Msk (0xffUL) /*!< ILPDVSR (Bitfield-Mask: 0xff) */ +/* ======================================================= UARTIBRD ======================================================== */ +#define UART0_UARTIBRD_BAUD_DIVINT_Pos (0UL) /*!< BAUD_DIVINT (Bit 0) */ +#define UART0_UARTIBRD_BAUD_DIVINT_Msk (0xffffUL) /*!< BAUD_DIVINT (Bitfield-Mask: 0xffff) */ +/* ======================================================= UARTFBRD ======================================================== */ +#define UART0_UARTFBRD_BAUD_DIVFRAC_Pos (0UL) /*!< BAUD_DIVFRAC (Bit 0) */ +#define UART0_UARTFBRD_BAUD_DIVFRAC_Msk (0x3fUL) /*!< BAUD_DIVFRAC (Bitfield-Mask: 0x3f) */ +/* ======================================================= UARTLCR_H ======================================================= */ +#define UART0_UARTLCR_H_SPS_Pos (7UL) /*!< SPS (Bit 7) */ +#define UART0_UARTLCR_H_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */ +#define UART0_UARTLCR_H_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */ +#define UART0_UARTLCR_H_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */ +#define UART0_UARTLCR_H_FEN_Pos (4UL) /*!< FEN (Bit 4) */ +#define UART0_UARTLCR_H_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */ +#define UART0_UARTLCR_H_STP2_Pos (3UL) /*!< STP2 (Bit 3) */ +#define UART0_UARTLCR_H_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */ +#define UART0_UARTLCR_H_EPS_Pos (2UL) /*!< EPS (Bit 2) */ +#define UART0_UARTLCR_H_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */ +#define UART0_UARTLCR_H_PEN_Pos (1UL) /*!< PEN (Bit 1) */ +#define UART0_UARTLCR_H_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */ +#define UART0_UARTLCR_H_BRK_Pos (0UL) /*!< BRK (Bit 0) */ +#define UART0_UARTLCR_H_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */ +/* ======================================================== UARTCR ========================================================= */ +#define UART0_UARTCR_CTSEN_Pos (15UL) /*!< CTSEN (Bit 15) */ +#define UART0_UARTCR_CTSEN_Msk (0x8000UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_RTSEN_Pos (14UL) /*!< RTSEN (Bit 14) */ +#define UART0_UARTCR_RTSEN_Msk (0x4000UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_OUT2_Pos (13UL) /*!< OUT2 (Bit 13) */ +#define UART0_UARTCR_OUT2_Msk (0x2000UL) /*!< OUT2 (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_OUT1_Pos (12UL) /*!< OUT1 (Bit 12) */ +#define UART0_UARTCR_OUT1_Msk (0x1000UL) /*!< OUT1 (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_RTS_Pos (11UL) /*!< RTS (Bit 11) */ +#define UART0_UARTCR_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_DTR_Pos (10UL) /*!< DTR (Bit 10) */ +#define UART0_UARTCR_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_RXE_Pos (9UL) /*!< RXE (Bit 9) */ +#define UART0_UARTCR_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_TXE_Pos (8UL) /*!< TXE (Bit 8) */ +#define UART0_UARTCR_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_LBE_Pos (7UL) /*!< LBE (Bit 7) */ +#define UART0_UARTCR_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_SIRLP_Pos (2UL) /*!< SIRLP (Bit 2) */ +#define UART0_UARTCR_SIRLP_Msk (0x4UL) /*!< SIRLP (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_SIREN_Pos (1UL) /*!< SIREN (Bit 1) */ +#define UART0_UARTCR_SIREN_Msk (0x2UL) /*!< SIREN (Bitfield-Mask: 0x01) */ +#define UART0_UARTCR_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */ +#define UART0_UARTCR_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= UARTIFLS ======================================================== */ +#define UART0_UARTIFLS_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */ +#define UART0_UARTIFLS_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */ +#define UART0_UARTIFLS_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */ +#define UART0_UARTIFLS_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */ +/* ======================================================= UARTIMSC ======================================================== */ +#define UART0_UARTIMSC_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */ +#define UART0_UARTIMSC_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */ +#define UART0_UARTIMSC_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */ +#define UART0_UARTIMSC_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */ +#define UART0_UARTIMSC_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */ +#define UART0_UARTIMSC_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */ +#define UART0_UARTIMSC_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */ +#define UART0_UARTIMSC_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */ +#define UART0_UARTIMSC_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */ +#define UART0_UARTIMSC_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */ +#define UART0_UARTIMSC_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */ +#define UART0_UARTIMSC_RIMIM_Pos (0UL) /*!< RIMIM (Bit 0) */ +#define UART0_UARTIMSC_RIMIM_Msk (0x1UL) /*!< RIMIM (Bitfield-Mask: 0x01) */ +/* ======================================================== UARTRIS ======================================================== */ +#define UART0_UARTRIS_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */ +#define UART0_UARTRIS_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */ +#define UART0_UARTRIS_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */ +#define UART0_UARTRIS_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */ +#define UART0_UARTRIS_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */ +#define UART0_UARTRIS_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */ +#define UART0_UARTRIS_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */ +#define UART0_UARTRIS_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_DSRRMIS_Pos (3UL) /*!< DSRRMIS (Bit 3) */ +#define UART0_UARTRIS_DSRRMIS_Msk (0x8UL) /*!< DSRRMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_DCDRMIS_Pos (2UL) /*!< DCDRMIS (Bit 2) */ +#define UART0_UARTRIS_DCDRMIS_Msk (0x4UL) /*!< DCDRMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_CTSRMIS_Pos (1UL) /*!< CTSRMIS (Bit 1) */ +#define UART0_UARTRIS_CTSRMIS_Msk (0x2UL) /*!< CTSRMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTRIS_RIRMIS_Pos (0UL) /*!< RIRMIS (Bit 0) */ +#define UART0_UARTRIS_RIRMIS_Msk (0x1UL) /*!< RIRMIS (Bitfield-Mask: 0x01) */ +/* ======================================================== UARTMIS ======================================================== */ +#define UART0_UARTMIS_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */ +#define UART0_UARTMIS_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */ +#define UART0_UARTMIS_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */ +#define UART0_UARTMIS_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */ +#define UART0_UARTMIS_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */ +#define UART0_UARTMIS_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */ +#define UART0_UARTMIS_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */ +#define UART0_UARTMIS_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */ +#define UART0_UARTMIS_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */ +#define UART0_UARTMIS_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */ +#define UART0_UARTMIS_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */ +#define UART0_UARTMIS_RIMMIS_Pos (0UL) /*!< RIMMIS (Bit 0) */ +#define UART0_UARTMIS_RIMMIS_Msk (0x1UL) /*!< RIMMIS (Bitfield-Mask: 0x01) */ +/* ======================================================== UARTICR ======================================================== */ +#define UART0_UARTICR_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */ +#define UART0_UARTICR_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */ +#define UART0_UARTICR_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */ +#define UART0_UARTICR_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */ +#define UART0_UARTICR_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */ +#define UART0_UARTICR_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */ +#define UART0_UARTICR_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */ +#define UART0_UARTICR_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */ +#define UART0_UARTICR_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */ +#define UART0_UARTICR_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */ +#define UART0_UARTICR_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */ +#define UART0_UARTICR_RIMIC_Pos (0UL) /*!< RIMIC (Bit 0) */ +#define UART0_UARTICR_RIMIC_Msk (0x1UL) /*!< RIMIC (Bitfield-Mask: 0x01) */ +/* ======================================================= UARTDMACR ======================================================= */ +#define UART0_UARTDMACR_DMAONERR_Pos (2UL) /*!< DMAONERR (Bit 2) */ +#define UART0_UARTDMACR_DMAONERR_Msk (0x4UL) /*!< DMAONERR (Bitfield-Mask: 0x01) */ +#define UART0_UARTDMACR_TXDMAE_Pos (1UL) /*!< TXDMAE (Bit 1) */ +#define UART0_UARTDMACR_TXDMAE_Msk (0x2UL) /*!< TXDMAE (Bitfield-Mask: 0x01) */ +#define UART0_UARTDMACR_RXDMAE_Pos (0UL) /*!< RXDMAE (Bit 0) */ +#define UART0_UARTDMACR_RXDMAE_Msk (0x1UL) /*!< RXDMAE (Bitfield-Mask: 0x01) */ +/* ===================================================== UARTPERIPHID0 ===================================================== */ +#define UART0_UARTPERIPHID0_PARTNUMBER0_Pos (0UL) /*!< PARTNUMBER0 (Bit 0) */ +#define UART0_UARTPERIPHID0_PARTNUMBER0_Msk (0xffUL) /*!< PARTNUMBER0 (Bitfield-Mask: 0xff) */ +/* ===================================================== UARTPERIPHID1 ===================================================== */ +#define UART0_UARTPERIPHID1_DESIGNER0_Pos (4UL) /*!< DESIGNER0 (Bit 4) */ +#define UART0_UARTPERIPHID1_DESIGNER0_Msk (0xf0UL) /*!< DESIGNER0 (Bitfield-Mask: 0x0f) */ +#define UART0_UARTPERIPHID1_PARTNUMBER1_Pos (0UL) /*!< PARTNUMBER1 (Bit 0) */ +#define UART0_UARTPERIPHID1_PARTNUMBER1_Msk (0xfUL) /*!< PARTNUMBER1 (Bitfield-Mask: 0x0f) */ +/* ===================================================== UARTPERIPHID2 ===================================================== */ +#define UART0_UARTPERIPHID2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */ +#define UART0_UARTPERIPHID2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define UART0_UARTPERIPHID2_DESIGNER1_Pos (0UL) /*!< DESIGNER1 (Bit 0) */ +#define UART0_UARTPERIPHID2_DESIGNER1_Msk (0xfUL) /*!< DESIGNER1 (Bitfield-Mask: 0x0f) */ +/* ===================================================== UARTPERIPHID3 ===================================================== */ +#define UART0_UARTPERIPHID3_CONFIGURATION_Pos (0UL) /*!< CONFIGURATION (Bit 0) */ +#define UART0_UARTPERIPHID3_CONFIGURATION_Msk (0xffUL) /*!< CONFIGURATION (Bitfield-Mask: 0xff) */ +/* ===================================================== UARTPCELLID0 ====================================================== */ +#define UART0_UARTPCELLID0_UARTPCELLID0_Pos (0UL) /*!< UARTPCELLID0 (Bit 0) */ +#define UART0_UARTPCELLID0_UARTPCELLID0_Msk (0xffUL) /*!< UARTPCELLID0 (Bitfield-Mask: 0xff) */ +/* ===================================================== UARTPCELLID1 ====================================================== */ +#define UART0_UARTPCELLID1_UARTPCELLID1_Pos (0UL) /*!< UARTPCELLID1 (Bit 0) */ +#define UART0_UARTPCELLID1_UARTPCELLID1_Msk (0xffUL) /*!< UARTPCELLID1 (Bitfield-Mask: 0xff) */ +/* ===================================================== UARTPCELLID2 ====================================================== */ +#define UART0_UARTPCELLID2_UARTPCELLID2_Pos (0UL) /*!< UARTPCELLID2 (Bit 0) */ +#define UART0_UARTPCELLID2_UARTPCELLID2_Msk (0xffUL) /*!< UARTPCELLID2 (Bitfield-Mask: 0xff) */ +/* ===================================================== UARTPCELLID3 ====================================================== */ +#define UART0_UARTPCELLID3_UARTPCELLID3_Pos (0UL) /*!< UARTPCELLID3 (Bit 0) */ +#define UART0_UARTPCELLID3_UARTPCELLID3_Msk (0xffUL) /*!< UARTPCELLID3 (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ ROSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define ROSC_CTRL_ENABLE_Pos (12UL) /*!< ENABLE (Bit 12) */ +#define ROSC_CTRL_ENABLE_Msk (0xfff000UL) /*!< ENABLE (Bitfield-Mask: 0xfff) */ +#define ROSC_CTRL_FREQ_RANGE_Pos (0UL) /*!< FREQ_RANGE (Bit 0) */ +#define ROSC_CTRL_FREQ_RANGE_Msk (0xfffUL) /*!< FREQ_RANGE (Bitfield-Mask: 0xfff) */ +/* ========================================================= FREQA ========================================================= */ +#define ROSC_FREQA_PASSWD_Pos (16UL) /*!< PASSWD (Bit 16) */ +#define ROSC_FREQA_PASSWD_Msk (0xffff0000UL) /*!< PASSWD (Bitfield-Mask: 0xffff) */ +#define ROSC_FREQA_DS3_Pos (12UL) /*!< DS3 (Bit 12) */ +#define ROSC_FREQA_DS3_Msk (0x7000UL) /*!< DS3 (Bitfield-Mask: 0x07) */ +#define ROSC_FREQA_DS2_Pos (8UL) /*!< DS2 (Bit 8) */ +#define ROSC_FREQA_DS2_Msk (0x700UL) /*!< DS2 (Bitfield-Mask: 0x07) */ +#define ROSC_FREQA_DS1_RANDOM_Pos (7UL) /*!< DS1_RANDOM (Bit 7) */ +#define ROSC_FREQA_DS1_RANDOM_Msk (0x80UL) /*!< DS1_RANDOM (Bitfield-Mask: 0x01) */ +#define ROSC_FREQA_DS1_Pos (4UL) /*!< DS1 (Bit 4) */ +#define ROSC_FREQA_DS1_Msk (0x70UL) /*!< DS1 (Bitfield-Mask: 0x07) */ +#define ROSC_FREQA_DS0_RANDOM_Pos (3UL) /*!< DS0_RANDOM (Bit 3) */ +#define ROSC_FREQA_DS0_RANDOM_Msk (0x8UL) /*!< DS0_RANDOM (Bitfield-Mask: 0x01) */ +#define ROSC_FREQA_DS0_Pos (0UL) /*!< DS0 (Bit 0) */ +#define ROSC_FREQA_DS0_Msk (0x7UL) /*!< DS0 (Bitfield-Mask: 0x07) */ +/* ========================================================= FREQB ========================================================= */ +#define ROSC_FREQB_PASSWD_Pos (16UL) /*!< PASSWD (Bit 16) */ +#define ROSC_FREQB_PASSWD_Msk (0xffff0000UL) /*!< PASSWD (Bitfield-Mask: 0xffff) */ +#define ROSC_FREQB_DS7_Pos (12UL) /*!< DS7 (Bit 12) */ +#define ROSC_FREQB_DS7_Msk (0x7000UL) /*!< DS7 (Bitfield-Mask: 0x07) */ +#define ROSC_FREQB_DS6_Pos (8UL) /*!< DS6 (Bit 8) */ +#define ROSC_FREQB_DS6_Msk (0x700UL) /*!< DS6 (Bitfield-Mask: 0x07) */ +#define ROSC_FREQB_DS5_Pos (4UL) /*!< DS5 (Bit 4) */ +#define ROSC_FREQB_DS5_Msk (0x70UL) /*!< DS5 (Bitfield-Mask: 0x07) */ +#define ROSC_FREQB_DS4_Pos (0UL) /*!< DS4 (Bit 0) */ +#define ROSC_FREQB_DS4_Msk (0x7UL) /*!< DS4 (Bitfield-Mask: 0x07) */ +/* ======================================================== RANDOM ========================================================= */ +#define ROSC_RANDOM_SEED_Pos (0UL) /*!< SEED (Bit 0) */ +#define ROSC_RANDOM_SEED_Msk (0xffffffffUL) /*!< SEED (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DORMANT ======================================================== */ +#define ROSC_DORMANT_DORMANT_Pos (0UL) /*!< DORMANT (Bit 0) */ +#define ROSC_DORMANT_DORMANT_Msk (0xffffffffUL) /*!< DORMANT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== DIV ========================================================== */ +#define ROSC_DIV_DIV_Pos (0UL) /*!< DIV (Bit 0) */ +#define ROSC_DIV_DIV_Msk (0xffffUL) /*!< DIV (Bitfield-Mask: 0xffff) */ +/* ========================================================= PHASE ========================================================= */ +#define ROSC_PHASE_PASSWD_Pos (4UL) /*!< PASSWD (Bit 4) */ +#define ROSC_PHASE_PASSWD_Msk (0xff0UL) /*!< PASSWD (Bitfield-Mask: 0xff) */ +#define ROSC_PHASE_ENABLE_Pos (3UL) /*!< ENABLE (Bit 3) */ +#define ROSC_PHASE_ENABLE_Msk (0x8UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define ROSC_PHASE_FLIP_Pos (2UL) /*!< FLIP (Bit 2) */ +#define ROSC_PHASE_FLIP_Msk (0x4UL) /*!< FLIP (Bitfield-Mask: 0x01) */ +#define ROSC_PHASE_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */ +#define ROSC_PHASE_SHIFT_Msk (0x3UL) /*!< SHIFT (Bitfield-Mask: 0x03) */ +/* ======================================================== STATUS ========================================================= */ +#define ROSC_STATUS_STABLE_Pos (31UL) /*!< STABLE (Bit 31) */ +#define ROSC_STATUS_STABLE_Msk (0x80000000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define ROSC_STATUS_BADWRITE_Pos (24UL) /*!< BADWRITE (Bit 24) */ +#define ROSC_STATUS_BADWRITE_Msk (0x1000000UL) /*!< BADWRITE (Bitfield-Mask: 0x01) */ +#define ROSC_STATUS_DIV_RUNNING_Pos (16UL) /*!< DIV_RUNNING (Bit 16) */ +#define ROSC_STATUS_DIV_RUNNING_Msk (0x10000UL) /*!< DIV_RUNNING (Bitfield-Mask: 0x01) */ +#define ROSC_STATUS_ENABLED_Pos (12UL) /*!< ENABLED (Bit 12) */ +#define ROSC_STATUS_ENABLED_Msk (0x1000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */ +/* ======================================================= RANDOMBIT ======================================================= */ +#define ROSC_RANDOMBIT_RANDOMBIT_Pos (0UL) /*!< RANDOMBIT (Bit 0) */ +#define ROSC_RANDOMBIT_RANDOMBIT_Msk (0x1UL) /*!< RANDOMBIT (Bitfield-Mask: 0x01) */ +/* ========================================================= COUNT ========================================================= */ +#define ROSC_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define ROSC_COUNT_COUNT_Msk (0xffffUL) /*!< COUNT (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ POWMAN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= BADPASSWD ======================================================= */ +#define POWMAN_BADPASSWD_BADPASSWD_Pos (0UL) /*!< BADPASSWD (Bit 0) */ +#define POWMAN_BADPASSWD_BADPASSWD_Msk (0x1UL) /*!< BADPASSWD (Bitfield-Mask: 0x01) */ +/* ======================================================= VREG_CTRL ======================================================= */ +#define POWMAN_VREG_CTRL_RST_N_Pos (15UL) /*!< RST_N (Bit 15) */ +#define POWMAN_VREG_CTRL_RST_N_Msk (0x8000UL) /*!< RST_N (Bitfield-Mask: 0x01) */ +#define POWMAN_VREG_CTRL_UNLOCK_Pos (13UL) /*!< UNLOCK (Bit 13) */ +#define POWMAN_VREG_CTRL_UNLOCK_Msk (0x2000UL) /*!< UNLOCK (Bitfield-Mask: 0x01) */ +#define POWMAN_VREG_CTRL_ISOLATE_Pos (12UL) /*!< ISOLATE (Bit 12) */ +#define POWMAN_VREG_CTRL_ISOLATE_Msk (0x1000UL) /*!< ISOLATE (Bitfield-Mask: 0x01) */ +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_Pos (8UL) /*!< DISABLE_VOLTAGE_LIMIT (Bit 8) */ +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_Msk (0x100UL) /*!< DISABLE_VOLTAGE_LIMIT (Bitfield-Mask: 0x01) */ +#define POWMAN_VREG_CTRL_HT_TH_Pos (4UL) /*!< HT_TH (Bit 4) */ +#define POWMAN_VREG_CTRL_HT_TH_Msk (0x70UL) /*!< HT_TH (Bitfield-Mask: 0x07) */ +/* ======================================================= VREG_STS ======================================================== */ +#define POWMAN_VREG_STS_VOUT_OK_Pos (4UL) /*!< VOUT_OK (Bit 4) */ +#define POWMAN_VREG_STS_VOUT_OK_Msk (0x10UL) /*!< VOUT_OK (Bitfield-Mask: 0x01) */ +#define POWMAN_VREG_STS_STARTUP_Pos (0UL) /*!< STARTUP (Bit 0) */ +#define POWMAN_VREG_STS_STARTUP_Msk (0x1UL) /*!< STARTUP (Bitfield-Mask: 0x01) */ +/* ========================================================= VREG ========================================================== */ +#define POWMAN_VREG_UPDATE_IN_PROGRESS_Pos (15UL) /*!< UPDATE_IN_PROGRESS (Bit 15) */ +#define POWMAN_VREG_UPDATE_IN_PROGRESS_Msk (0x8000UL) /*!< UPDATE_IN_PROGRESS (Bitfield-Mask: 0x01) */ +#define POWMAN_VREG_VSEL_Pos (4UL) /*!< VSEL (Bit 4) */ +#define POWMAN_VREG_VSEL_Msk (0x1f0UL) /*!< VSEL (Bitfield-Mask: 0x1f) */ +#define POWMAN_VREG_HIZ_Pos (1UL) /*!< HIZ (Bit 1) */ +#define POWMAN_VREG_HIZ_Msk (0x2UL) /*!< HIZ (Bitfield-Mask: 0x01) */ +/* ===================================================== VREG_LP_ENTRY ===================================================== */ +#define POWMAN_VREG_LP_ENTRY_VSEL_Pos (4UL) /*!< VSEL (Bit 4) */ +#define POWMAN_VREG_LP_ENTRY_VSEL_Msk (0x1f0UL) /*!< VSEL (Bitfield-Mask: 0x1f) */ +#define POWMAN_VREG_LP_ENTRY_MODE_Pos (2UL) /*!< MODE (Bit 2) */ +#define POWMAN_VREG_LP_ENTRY_MODE_Msk (0x4UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define POWMAN_VREG_LP_ENTRY_HIZ_Pos (1UL) /*!< HIZ (Bit 1) */ +#define POWMAN_VREG_LP_ENTRY_HIZ_Msk (0x2UL) /*!< HIZ (Bitfield-Mask: 0x01) */ +/* ===================================================== VREG_LP_EXIT ====================================================== */ +#define POWMAN_VREG_LP_EXIT_VSEL_Pos (4UL) /*!< VSEL (Bit 4) */ +#define POWMAN_VREG_LP_EXIT_VSEL_Msk (0x1f0UL) /*!< VSEL (Bitfield-Mask: 0x1f) */ +#define POWMAN_VREG_LP_EXIT_MODE_Pos (2UL) /*!< MODE (Bit 2) */ +#define POWMAN_VREG_LP_EXIT_MODE_Msk (0x4UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define POWMAN_VREG_LP_EXIT_HIZ_Pos (1UL) /*!< HIZ (Bit 1) */ +#define POWMAN_VREG_LP_EXIT_HIZ_Msk (0x2UL) /*!< HIZ (Bitfield-Mask: 0x01) */ +/* ======================================================= BOD_CTRL ======================================================== */ +#define POWMAN_BOD_CTRL_ISOLATE_Pos (12UL) /*!< ISOLATE (Bit 12) */ +#define POWMAN_BOD_CTRL_ISOLATE_Msk (0x1000UL) /*!< ISOLATE (Bitfield-Mask: 0x01) */ +/* ========================================================== BOD ========================================================== */ +#define POWMAN_BOD_VSEL_Pos (4UL) /*!< VSEL (Bit 4) */ +#define POWMAN_BOD_VSEL_Msk (0x1f0UL) /*!< VSEL (Bitfield-Mask: 0x1f) */ +#define POWMAN_BOD_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define POWMAN_BOD_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== BOD_LP_ENTRY ====================================================== */ +#define POWMAN_BOD_LP_ENTRY_VSEL_Pos (4UL) /*!< VSEL (Bit 4) */ +#define POWMAN_BOD_LP_ENTRY_VSEL_Msk (0x1f0UL) /*!< VSEL (Bitfield-Mask: 0x1f) */ +#define POWMAN_BOD_LP_ENTRY_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define POWMAN_BOD_LP_ENTRY_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ====================================================== BOD_LP_EXIT ====================================================== */ +#define POWMAN_BOD_LP_EXIT_VSEL_Pos (4UL) /*!< VSEL (Bit 4) */ +#define POWMAN_BOD_LP_EXIT_VSEL_Msk (0x1f0UL) /*!< VSEL (Bitfield-Mask: 0x1f) */ +#define POWMAN_BOD_LP_EXIT_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define POWMAN_BOD_LP_EXIT_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOSC ========================================================= */ +#define POWMAN_LPOSC_TRIM_Pos (4UL) /*!< TRIM (Bit 4) */ +#define POWMAN_LPOSC_TRIM_Msk (0x3f0UL) /*!< TRIM (Bitfield-Mask: 0x3f) */ +#define POWMAN_LPOSC_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define POWMAN_LPOSC_MODE_Msk (0x3UL) /*!< MODE (Bitfield-Mask: 0x03) */ +/* ====================================================== CHIP_RESET ======================================================= */ +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_Pos (28UL) /*!< HAD_WATCHDOG_RESET_RSM (Bit 28) */ +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_Msk (0x10000000UL) /*!< HAD_WATCHDOG_RESET_RSM (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_Pos (27UL) /*!< HAD_HZD_SYS_RESET_REQ (Bit 27) */ +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_Msk (0x8000000UL) /*!< HAD_HZD_SYS_RESET_REQ (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_Pos (26UL) /*!< HAD_GLITCH_DETECT (Bit 26) */ +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_Msk (0x4000000UL) /*!< HAD_GLITCH_DETECT (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_Pos (25UL) /*!< HAD_SWCORE_PD (Bit 25) */ +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_Msk (0x2000000UL) /*!< HAD_SWCORE_PD (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_Pos (24UL) /*!< HAD_WATCHDOG_RESET_SWCORE (Bit 24) */ +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_Msk (0x1000000UL) /*!< HAD_WATCHDOG_RESET_SWCORE (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_Pos (23UL) /*!< HAD_WATCHDOG_RESET_POWMAN (Bit 23) */ +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_Msk (0x800000UL) /*!< HAD_WATCHDOG_RESET_POWMAN (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_Pos (22UL) /*!< HAD_WATCHDOG_RESET_POWMAN_ASYNC (Bit 22) */ +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_Msk (0x400000UL) /*!< HAD_WATCHDOG_RESET_POWMAN_ASYNC (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_RESCUE_Pos (21UL) /*!< HAD_RESCUE (Bit 21) */ +#define POWMAN_CHIP_RESET_HAD_RESCUE_Msk (0x200000UL) /*!< HAD_RESCUE (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_Pos (19UL) /*!< HAD_DP_RESET_REQ (Bit 19) */ +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_Msk (0x80000UL) /*!< HAD_DP_RESET_REQ (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_Pos (18UL) /*!< HAD_RUN_LOW (Bit 18) */ +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_Msk (0x40000UL) /*!< HAD_RUN_LOW (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_BOR_Pos (17UL) /*!< HAD_BOR (Bit 17) */ +#define POWMAN_CHIP_RESET_HAD_BOR_Msk (0x20000UL) /*!< HAD_BOR (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_HAD_POR_Pos (16UL) /*!< HAD_POR (Bit 16) */ +#define POWMAN_CHIP_RESET_HAD_POR_Msk (0x10000UL) /*!< HAD_POR (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_RESCUE_FLAG_Pos (4UL) /*!< RESCUE_FLAG (Bit 4) */ +#define POWMAN_CHIP_RESET_RESCUE_FLAG_Msk (0x10UL) /*!< RESCUE_FLAG (Bitfield-Mask: 0x01) */ +#define POWMAN_CHIP_RESET_DOUBLE_TAP_Pos (0UL) /*!< DOUBLE_TAP (Bit 0) */ +#define POWMAN_CHIP_RESET_DOUBLE_TAP_Msk (0x1UL) /*!< DOUBLE_TAP (Bitfield-Mask: 0x01) */ +/* ========================================================= WDSEL ========================================================= */ +#define POWMAN_WDSEL_RESET_RSM_Pos (12UL) /*!< RESET_RSM (Bit 12) */ +#define POWMAN_WDSEL_RESET_RSM_Msk (0x1000UL) /*!< RESET_RSM (Bitfield-Mask: 0x01) */ +#define POWMAN_WDSEL_RESET_SWCORE_Pos (8UL) /*!< RESET_SWCORE (Bit 8) */ +#define POWMAN_WDSEL_RESET_SWCORE_Msk (0x100UL) /*!< RESET_SWCORE (Bitfield-Mask: 0x01) */ +#define POWMAN_WDSEL_RESET_POWMAN_Pos (4UL) /*!< RESET_POWMAN (Bit 4) */ +#define POWMAN_WDSEL_RESET_POWMAN_Msk (0x10UL) /*!< RESET_POWMAN (Bitfield-Mask: 0x01) */ +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_Pos (0UL) /*!< RESET_POWMAN_ASYNC (Bit 0) */ +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_Msk (0x1UL) /*!< RESET_POWMAN_ASYNC (Bitfield-Mask: 0x01) */ +/* ======================================================== SEQ_CFG ======================================================== */ +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_Pos (20UL) /*!< USING_FAST_POWCK (Bit 20) */ +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_Msk (0x100000UL) /*!< USING_FAST_POWCK (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_USING_BOD_LP_Pos (17UL) /*!< USING_BOD_LP (Bit 17) */ +#define POWMAN_SEQ_CFG_USING_BOD_LP_Msk (0x20000UL) /*!< USING_BOD_LP (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_USING_VREG_LP_Pos (16UL) /*!< USING_VREG_LP (Bit 16) */ +#define POWMAN_SEQ_CFG_USING_VREG_LP_Msk (0x10000UL) /*!< USING_VREG_LP (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_Pos (12UL) /*!< USE_FAST_POWCK (Bit 12) */ +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_Msk (0x1000UL) /*!< USE_FAST_POWCK (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_Pos (8UL) /*!< RUN_LPOSC_IN_LP (Bit 8) */ +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_Msk (0x100UL) /*!< RUN_LPOSC_IN_LP (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_USE_BOD_HP_Pos (7UL) /*!< USE_BOD_HP (Bit 7) */ +#define POWMAN_SEQ_CFG_USE_BOD_HP_Msk (0x80UL) /*!< USE_BOD_HP (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_USE_BOD_LP_Pos (6UL) /*!< USE_BOD_LP (Bit 6) */ +#define POWMAN_SEQ_CFG_USE_BOD_LP_Msk (0x40UL) /*!< USE_BOD_LP (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_USE_VREG_HP_Pos (5UL) /*!< USE_VREG_HP (Bit 5) */ +#define POWMAN_SEQ_CFG_USE_VREG_HP_Msk (0x20UL) /*!< USE_VREG_HP (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_USE_VREG_LP_Pos (4UL) /*!< USE_VREG_LP (Bit 4) */ +#define POWMAN_SEQ_CFG_USE_VREG_LP_Msk (0x10UL) /*!< USE_VREG_LP (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_Pos (1UL) /*!< HW_PWRUP_SRAM0 (Bit 1) */ +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_Msk (0x2UL) /*!< HW_PWRUP_SRAM0 (Bitfield-Mask: 0x01) */ +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_Pos (0UL) /*!< HW_PWRUP_SRAM1 (Bit 0) */ +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_Msk (0x1UL) /*!< HW_PWRUP_SRAM1 (Bitfield-Mask: 0x01) */ +/* ========================================================= STATE ========================================================= */ +#define POWMAN_STATE_CHANGING_Pos (13UL) /*!< CHANGING (Bit 13) */ +#define POWMAN_STATE_CHANGING_Msk (0x2000UL) /*!< CHANGING (Bitfield-Mask: 0x01) */ +#define POWMAN_STATE_WAITING_Pos (12UL) /*!< WAITING (Bit 12) */ +#define POWMAN_STATE_WAITING_Msk (0x1000UL) /*!< WAITING (Bitfield-Mask: 0x01) */ +#define POWMAN_STATE_BAD_HW_REQ_Pos (11UL) /*!< BAD_HW_REQ (Bit 11) */ +#define POWMAN_STATE_BAD_HW_REQ_Msk (0x800UL) /*!< BAD_HW_REQ (Bitfield-Mask: 0x01) */ +#define POWMAN_STATE_BAD_SW_REQ_Pos (10UL) /*!< BAD_SW_REQ (Bit 10) */ +#define POWMAN_STATE_BAD_SW_REQ_Msk (0x400UL) /*!< BAD_SW_REQ (Bitfield-Mask: 0x01) */ +#define POWMAN_STATE_PWRUP_WHILE_WAITING_Pos (9UL) /*!< PWRUP_WHILE_WAITING (Bit 9) */ +#define POWMAN_STATE_PWRUP_WHILE_WAITING_Msk (0x200UL) /*!< PWRUP_WHILE_WAITING (Bitfield-Mask: 0x01) */ +#define POWMAN_STATE_REQ_IGNORED_Pos (8UL) /*!< REQ_IGNORED (Bit 8) */ +#define POWMAN_STATE_REQ_IGNORED_Msk (0x100UL) /*!< REQ_IGNORED (Bitfield-Mask: 0x01) */ +#define POWMAN_STATE_REQ_Pos (4UL) /*!< REQ (Bit 4) */ +#define POWMAN_STATE_REQ_Msk (0xf0UL) /*!< REQ (Bitfield-Mask: 0x0f) */ +#define POWMAN_STATE_CURRENT_Pos (0UL) /*!< CURRENT (Bit 0) */ +#define POWMAN_STATE_CURRENT_Msk (0xfUL) /*!< CURRENT (Bitfield-Mask: 0x0f) */ +/* ====================================================== POW_FASTDIV ====================================================== */ +#define POWMAN_POW_FASTDIV_POW_FASTDIV_Pos (0UL) /*!< POW_FASTDIV (Bit 0) */ +#define POWMAN_POW_FASTDIV_POW_FASTDIV_Msk (0x7ffUL) /*!< POW_FASTDIV (Bitfield-Mask: 0x7ff) */ +/* ======================================================= POW_DELAY ======================================================= */ +#define POWMAN_POW_DELAY_SRAM_STEP_Pos (8UL) /*!< SRAM_STEP (Bit 8) */ +#define POWMAN_POW_DELAY_SRAM_STEP_Msk (0xff00UL) /*!< SRAM_STEP (Bitfield-Mask: 0xff) */ +#define POWMAN_POW_DELAY_XIP_STEP_Pos (4UL) /*!< XIP_STEP (Bit 4) */ +#define POWMAN_POW_DELAY_XIP_STEP_Msk (0xf0UL) /*!< XIP_STEP (Bitfield-Mask: 0x0f) */ +#define POWMAN_POW_DELAY_SWCORE_STEP_Pos (0UL) /*!< SWCORE_STEP (Bit 0) */ +#define POWMAN_POW_DELAY_SWCORE_STEP_Msk (0xfUL) /*!< SWCORE_STEP (Bitfield-Mask: 0x0f) */ +/* ======================================================= EXT_CTRL0 ======================================================= */ +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_Pos (14UL) /*!< LP_EXIT_STATE (Bit 14) */ +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_Msk (0x4000UL) /*!< LP_EXIT_STATE (Bitfield-Mask: 0x01) */ +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_Pos (13UL) /*!< LP_ENTRY_STATE (Bit 13) */ +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_Msk (0x2000UL) /*!< LP_ENTRY_STATE (Bitfield-Mask: 0x01) */ +#define POWMAN_EXT_CTRL0_INIT_STATE_Pos (12UL) /*!< INIT_STATE (Bit 12) */ +#define POWMAN_EXT_CTRL0_INIT_STATE_Msk (0x1000UL) /*!< INIT_STATE (Bitfield-Mask: 0x01) */ +#define POWMAN_EXT_CTRL0_INIT_Pos (8UL) /*!< INIT (Bit 8) */ +#define POWMAN_EXT_CTRL0_INIT_Msk (0x100UL) /*!< INIT (Bitfield-Mask: 0x01) */ +#define POWMAN_EXT_CTRL0_GPIO_SELECT_Pos (0UL) /*!< GPIO_SELECT (Bit 0) */ +#define POWMAN_EXT_CTRL0_GPIO_SELECT_Msk (0x3fUL) /*!< GPIO_SELECT (Bitfield-Mask: 0x3f) */ +/* ======================================================= EXT_CTRL1 ======================================================= */ +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_Pos (14UL) /*!< LP_EXIT_STATE (Bit 14) */ +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_Msk (0x4000UL) /*!< LP_EXIT_STATE (Bitfield-Mask: 0x01) */ +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_Pos (13UL) /*!< LP_ENTRY_STATE (Bit 13) */ +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_Msk (0x2000UL) /*!< LP_ENTRY_STATE (Bitfield-Mask: 0x01) */ +#define POWMAN_EXT_CTRL1_INIT_STATE_Pos (12UL) /*!< INIT_STATE (Bit 12) */ +#define POWMAN_EXT_CTRL1_INIT_STATE_Msk (0x1000UL) /*!< INIT_STATE (Bitfield-Mask: 0x01) */ +#define POWMAN_EXT_CTRL1_INIT_Pos (8UL) /*!< INIT (Bit 8) */ +#define POWMAN_EXT_CTRL1_INIT_Msk (0x100UL) /*!< INIT (Bitfield-Mask: 0x01) */ +#define POWMAN_EXT_CTRL1_GPIO_SELECT_Pos (0UL) /*!< GPIO_SELECT (Bit 0) */ +#define POWMAN_EXT_CTRL1_GPIO_SELECT_Msk (0x3fUL) /*!< GPIO_SELECT (Bitfield-Mask: 0x3f) */ +/* ===================================================== EXT_TIME_REF ====================================================== */ +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_Pos (4UL) /*!< DRIVE_LPCK (Bit 4) */ +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_Msk (0x10UL) /*!< DRIVE_LPCK (Bitfield-Mask: 0x01) */ +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_Pos (0UL) /*!< SOURCE_SEL (Bit 0) */ +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_Msk (0x3UL) /*!< SOURCE_SEL (Bitfield-Mask: 0x03) */ +/* ================================================== LPOSC_FREQ_KHZ_INT =================================================== */ +#define POWMAN_LPOSC_FREQ_KHZ_INT_LPOSC_FREQ_KHZ_INT_Pos (0UL) /*!< LPOSC_FREQ_KHZ_INT (Bit 0) */ +#define POWMAN_LPOSC_FREQ_KHZ_INT_LPOSC_FREQ_KHZ_INT_Msk (0x3fUL) /*!< LPOSC_FREQ_KHZ_INT (Bitfield-Mask: 0x3f) */ +/* ================================================== LPOSC_FREQ_KHZ_FRAC ================================================== */ +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_LPOSC_FREQ_KHZ_FRAC_Pos (0UL) /*!< LPOSC_FREQ_KHZ_FRAC (Bit 0) */ +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_LPOSC_FREQ_KHZ_FRAC_Msk (0xffffUL) /*!< LPOSC_FREQ_KHZ_FRAC (Bitfield-Mask: 0xffff) */ +/* =================================================== XOSC_FREQ_KHZ_INT =================================================== */ +#define POWMAN_XOSC_FREQ_KHZ_INT_XOSC_FREQ_KHZ_INT_Pos (0UL) /*!< XOSC_FREQ_KHZ_INT (Bit 0) */ +#define POWMAN_XOSC_FREQ_KHZ_INT_XOSC_FREQ_KHZ_INT_Msk (0xffffUL) /*!< XOSC_FREQ_KHZ_INT (Bitfield-Mask: 0xffff) */ +/* ================================================== XOSC_FREQ_KHZ_FRAC =================================================== */ +#define POWMAN_XOSC_FREQ_KHZ_FRAC_XOSC_FREQ_KHZ_FRAC_Pos (0UL) /*!< XOSC_FREQ_KHZ_FRAC (Bit 0) */ +#define POWMAN_XOSC_FREQ_KHZ_FRAC_XOSC_FREQ_KHZ_FRAC_Msk (0xffffUL) /*!< XOSC_FREQ_KHZ_FRAC (Bitfield-Mask: 0xffff) */ +/* ==================================================== SET_TIME_63TO48 ==================================================== */ +#define POWMAN_SET_TIME_63TO48_SET_TIME_63TO48_Pos (0UL) /*!< SET_TIME_63TO48 (Bit 0) */ +#define POWMAN_SET_TIME_63TO48_SET_TIME_63TO48_Msk (0xffffUL) /*!< SET_TIME_63TO48 (Bitfield-Mask: 0xffff) */ +/* ==================================================== SET_TIME_47TO32 ==================================================== */ +#define POWMAN_SET_TIME_47TO32_SET_TIME_47TO32_Pos (0UL) /*!< SET_TIME_47TO32 (Bit 0) */ +#define POWMAN_SET_TIME_47TO32_SET_TIME_47TO32_Msk (0xffffUL) /*!< SET_TIME_47TO32 (Bitfield-Mask: 0xffff) */ +/* ==================================================== SET_TIME_31TO16 ==================================================== */ +#define POWMAN_SET_TIME_31TO16_SET_TIME_31TO16_Pos (0UL) /*!< SET_TIME_31TO16 (Bit 0) */ +#define POWMAN_SET_TIME_31TO16_SET_TIME_31TO16_Msk (0xffffUL) /*!< SET_TIME_31TO16 (Bitfield-Mask: 0xffff) */ +/* ==================================================== SET_TIME_15TO0 ===================================================== */ +#define POWMAN_SET_TIME_15TO0_SET_TIME_15TO0_Pos (0UL) /*!< SET_TIME_15TO0 (Bit 0) */ +#define POWMAN_SET_TIME_15TO0_SET_TIME_15TO0_Msk (0xffffUL) /*!< SET_TIME_15TO0 (Bitfield-Mask: 0xffff) */ +/* ==================================================== READ_TIME_UPPER ==================================================== */ +#define POWMAN_READ_TIME_UPPER_READ_TIME_UPPER_Pos (0UL) /*!< READ_TIME_UPPER (Bit 0) */ +#define POWMAN_READ_TIME_UPPER_READ_TIME_UPPER_Msk (0xffffffffUL) /*!< READ_TIME_UPPER (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== READ_TIME_LOWER ==================================================== */ +#define POWMAN_READ_TIME_LOWER_READ_TIME_LOWER_Pos (0UL) /*!< READ_TIME_LOWER (Bit 0) */ +#define POWMAN_READ_TIME_LOWER_READ_TIME_LOWER_Msk (0xffffffffUL) /*!< READ_TIME_LOWER (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ALARM_TIME_63TO48 =================================================== */ +#define POWMAN_ALARM_TIME_63TO48_ALARM_TIME_63TO48_Pos (0UL) /*!< ALARM_TIME_63TO48 (Bit 0) */ +#define POWMAN_ALARM_TIME_63TO48_ALARM_TIME_63TO48_Msk (0xffffUL) /*!< ALARM_TIME_63TO48 (Bitfield-Mask: 0xffff) */ +/* =================================================== ALARM_TIME_47TO32 =================================================== */ +#define POWMAN_ALARM_TIME_47TO32_ALARM_TIME_47TO32_Pos (0UL) /*!< ALARM_TIME_47TO32 (Bit 0) */ +#define POWMAN_ALARM_TIME_47TO32_ALARM_TIME_47TO32_Msk (0xffffUL) /*!< ALARM_TIME_47TO32 (Bitfield-Mask: 0xffff) */ +/* =================================================== ALARM_TIME_31TO16 =================================================== */ +#define POWMAN_ALARM_TIME_31TO16_ALARM_TIME_31TO16_Pos (0UL) /*!< ALARM_TIME_31TO16 (Bit 0) */ +#define POWMAN_ALARM_TIME_31TO16_ALARM_TIME_31TO16_Msk (0xffffUL) /*!< ALARM_TIME_31TO16 (Bitfield-Mask: 0xffff) */ +/* =================================================== ALARM_TIME_15TO0 ==================================================== */ +#define POWMAN_ALARM_TIME_15TO0_ALARM_TIME_15TO0_Pos (0UL) /*!< ALARM_TIME_15TO0 (Bit 0) */ +#define POWMAN_ALARM_TIME_15TO0_ALARM_TIME_15TO0_Msk (0xffffUL) /*!< ALARM_TIME_15TO0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= TIMER ========================================================= */ +#define POWMAN_TIMER_USING_GPIO_1HZ_Pos (19UL) /*!< USING_GPIO_1HZ (Bit 19) */ +#define POWMAN_TIMER_USING_GPIO_1HZ_Msk (0x80000UL) /*!< USING_GPIO_1HZ (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_USING_GPIO_1KHZ_Pos (18UL) /*!< USING_GPIO_1KHZ (Bit 18) */ +#define POWMAN_TIMER_USING_GPIO_1KHZ_Msk (0x40000UL) /*!< USING_GPIO_1KHZ (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_USING_LPOSC_Pos (17UL) /*!< USING_LPOSC (Bit 17) */ +#define POWMAN_TIMER_USING_LPOSC_Msk (0x20000UL) /*!< USING_LPOSC (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_USING_XOSC_Pos (16UL) /*!< USING_XOSC (Bit 16) */ +#define POWMAN_TIMER_USING_XOSC_Msk (0x10000UL) /*!< USING_XOSC (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_USE_GPIO_1HZ_Pos (13UL) /*!< USE_GPIO_1HZ (Bit 13) */ +#define POWMAN_TIMER_USE_GPIO_1HZ_Msk (0x2000UL) /*!< USE_GPIO_1HZ (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_USE_GPIO_1KHZ_Pos (10UL) /*!< USE_GPIO_1KHZ (Bit 10) */ +#define POWMAN_TIMER_USE_GPIO_1KHZ_Msk (0x400UL) /*!< USE_GPIO_1KHZ (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_USE_XOSC_Pos (9UL) /*!< USE_XOSC (Bit 9) */ +#define POWMAN_TIMER_USE_XOSC_Msk (0x200UL) /*!< USE_XOSC (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_USE_LPOSC_Pos (8UL) /*!< USE_LPOSC (Bit 8) */ +#define POWMAN_TIMER_USE_LPOSC_Msk (0x100UL) /*!< USE_LPOSC (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_ALARM_Pos (6UL) /*!< ALARM (Bit 6) */ +#define POWMAN_TIMER_ALARM_Msk (0x40UL) /*!< ALARM (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_PWRUP_ON_ALARM_Pos (5UL) /*!< PWRUP_ON_ALARM (Bit 5) */ +#define POWMAN_TIMER_PWRUP_ON_ALARM_Msk (0x20UL) /*!< PWRUP_ON_ALARM (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_ALARM_ENAB_Pos (4UL) /*!< ALARM_ENAB (Bit 4) */ +#define POWMAN_TIMER_ALARM_ENAB_Msk (0x10UL) /*!< ALARM_ENAB (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_CLEAR_Pos (2UL) /*!< CLEAR (Bit 2) */ +#define POWMAN_TIMER_CLEAR_Msk (0x4UL) /*!< CLEAR (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_RUN_Pos (1UL) /*!< RUN (Bit 1) */ +#define POWMAN_TIMER_RUN_Msk (0x2UL) /*!< RUN (Bitfield-Mask: 0x01) */ +#define POWMAN_TIMER_NONSEC_WRITE_Pos (0UL) /*!< NONSEC_WRITE (Bit 0) */ +#define POWMAN_TIMER_NONSEC_WRITE_Msk (0x1UL) /*!< NONSEC_WRITE (Bitfield-Mask: 0x01) */ +/* ======================================================== PWRUP0 ========================================================= */ +#define POWMAN_PWRUP0_RAW_STATUS_Pos (10UL) /*!< RAW_STATUS (Bit 10) */ +#define POWMAN_PWRUP0_RAW_STATUS_Msk (0x400UL) /*!< RAW_STATUS (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP0_STATUS_Pos (9UL) /*!< STATUS (Bit 9) */ +#define POWMAN_PWRUP0_STATUS_Msk (0x200UL) /*!< STATUS (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP0_MODE_Pos (8UL) /*!< MODE (Bit 8) */ +#define POWMAN_PWRUP0_MODE_Msk (0x100UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP0_DIRECTION_Pos (7UL) /*!< DIRECTION (Bit 7) */ +#define POWMAN_PWRUP0_DIRECTION_Msk (0x80UL) /*!< DIRECTION (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP0_ENABLE_Pos (6UL) /*!< ENABLE (Bit 6) */ +#define POWMAN_PWRUP0_ENABLE_Msk (0x40UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP0_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define POWMAN_PWRUP0_SOURCE_Msk (0x3fUL) /*!< SOURCE (Bitfield-Mask: 0x3f) */ +/* ======================================================== PWRUP1 ========================================================= */ +#define POWMAN_PWRUP1_RAW_STATUS_Pos (10UL) /*!< RAW_STATUS (Bit 10) */ +#define POWMAN_PWRUP1_RAW_STATUS_Msk (0x400UL) /*!< RAW_STATUS (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP1_STATUS_Pos (9UL) /*!< STATUS (Bit 9) */ +#define POWMAN_PWRUP1_STATUS_Msk (0x200UL) /*!< STATUS (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP1_MODE_Pos (8UL) /*!< MODE (Bit 8) */ +#define POWMAN_PWRUP1_MODE_Msk (0x100UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP1_DIRECTION_Pos (7UL) /*!< DIRECTION (Bit 7) */ +#define POWMAN_PWRUP1_DIRECTION_Msk (0x80UL) /*!< DIRECTION (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP1_ENABLE_Pos (6UL) /*!< ENABLE (Bit 6) */ +#define POWMAN_PWRUP1_ENABLE_Msk (0x40UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP1_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define POWMAN_PWRUP1_SOURCE_Msk (0x3fUL) /*!< SOURCE (Bitfield-Mask: 0x3f) */ +/* ======================================================== PWRUP2 ========================================================= */ +#define POWMAN_PWRUP2_RAW_STATUS_Pos (10UL) /*!< RAW_STATUS (Bit 10) */ +#define POWMAN_PWRUP2_RAW_STATUS_Msk (0x400UL) /*!< RAW_STATUS (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP2_STATUS_Pos (9UL) /*!< STATUS (Bit 9) */ +#define POWMAN_PWRUP2_STATUS_Msk (0x200UL) /*!< STATUS (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP2_MODE_Pos (8UL) /*!< MODE (Bit 8) */ +#define POWMAN_PWRUP2_MODE_Msk (0x100UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP2_DIRECTION_Pos (7UL) /*!< DIRECTION (Bit 7) */ +#define POWMAN_PWRUP2_DIRECTION_Msk (0x80UL) /*!< DIRECTION (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP2_ENABLE_Pos (6UL) /*!< ENABLE (Bit 6) */ +#define POWMAN_PWRUP2_ENABLE_Msk (0x40UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP2_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define POWMAN_PWRUP2_SOURCE_Msk (0x3fUL) /*!< SOURCE (Bitfield-Mask: 0x3f) */ +/* ======================================================== PWRUP3 ========================================================= */ +#define POWMAN_PWRUP3_RAW_STATUS_Pos (10UL) /*!< RAW_STATUS (Bit 10) */ +#define POWMAN_PWRUP3_RAW_STATUS_Msk (0x400UL) /*!< RAW_STATUS (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP3_STATUS_Pos (9UL) /*!< STATUS (Bit 9) */ +#define POWMAN_PWRUP3_STATUS_Msk (0x200UL) /*!< STATUS (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP3_MODE_Pos (8UL) /*!< MODE (Bit 8) */ +#define POWMAN_PWRUP3_MODE_Msk (0x100UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP3_DIRECTION_Pos (7UL) /*!< DIRECTION (Bit 7) */ +#define POWMAN_PWRUP3_DIRECTION_Msk (0x80UL) /*!< DIRECTION (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP3_ENABLE_Pos (6UL) /*!< ENABLE (Bit 6) */ +#define POWMAN_PWRUP3_ENABLE_Msk (0x40UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define POWMAN_PWRUP3_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define POWMAN_PWRUP3_SOURCE_Msk (0x3fUL) /*!< SOURCE (Bitfield-Mask: 0x3f) */ +/* =================================================== CURRENT_PWRUP_REQ =================================================== */ +#define POWMAN_CURRENT_PWRUP_REQ_CURRENT_PWRUP_REQ_Pos (0UL) /*!< CURRENT_PWRUP_REQ (Bit 0) */ +#define POWMAN_CURRENT_PWRUP_REQ_CURRENT_PWRUP_REQ_Msk (0x7fUL) /*!< CURRENT_PWRUP_REQ (Bitfield-Mask: 0x7f) */ +/* =================================================== LAST_SWCORE_PWRUP =================================================== */ +#define POWMAN_LAST_SWCORE_PWRUP_LAST_SWCORE_PWRUP_Pos (0UL) /*!< LAST_SWCORE_PWRUP (Bit 0) */ +#define POWMAN_LAST_SWCORE_PWRUP_LAST_SWCORE_PWRUP_Msk (0x7fUL) /*!< LAST_SWCORE_PWRUP (Bitfield-Mask: 0x7f) */ +/* ====================================================== DBG_PWRCFG ======================================================= */ +#define POWMAN_DBG_PWRCFG_IGNORE_Pos (0UL) /*!< IGNORE (Bit 0) */ +#define POWMAN_DBG_PWRCFG_IGNORE_Msk (0x1UL) /*!< IGNORE (Bitfield-Mask: 0x01) */ +/* ======================================================== BOOTDIS ======================================================== */ +#define POWMAN_BOOTDIS_NEXT_Pos (1UL) /*!< NEXT (Bit 1) */ +#define POWMAN_BOOTDIS_NEXT_Msk (0x2UL) /*!< NEXT (Bitfield-Mask: 0x01) */ +#define POWMAN_BOOTDIS_NOW_Pos (0UL) /*!< NOW (Bit 0) */ +#define POWMAN_BOOTDIS_NOW_Msk (0x1UL) /*!< NOW (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGCONFIG ======================================================= */ +#define POWMAN_DBGCONFIG_DP_INSTID_Pos (0UL) /*!< DP_INSTID (Bit 0) */ +#define POWMAN_DBGCONFIG_DP_INSTID_Msk (0xfUL) /*!< DP_INSTID (Bitfield-Mask: 0x0f) */ +/* ======================================================= SCRATCH0 ======================================================== */ +#define POWMAN_SCRATCH0_SCRATCH0_Pos (0UL) /*!< SCRATCH0 (Bit 0) */ +#define POWMAN_SCRATCH0_SCRATCH0_Msk (0xffffffffUL) /*!< SCRATCH0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH1 ======================================================== */ +#define POWMAN_SCRATCH1_SCRATCH1_Pos (0UL) /*!< SCRATCH1 (Bit 0) */ +#define POWMAN_SCRATCH1_SCRATCH1_Msk (0xffffffffUL) /*!< SCRATCH1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH2 ======================================================== */ +#define POWMAN_SCRATCH2_SCRATCH2_Pos (0UL) /*!< SCRATCH2 (Bit 0) */ +#define POWMAN_SCRATCH2_SCRATCH2_Msk (0xffffffffUL) /*!< SCRATCH2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH3 ======================================================== */ +#define POWMAN_SCRATCH3_SCRATCH3_Pos (0UL) /*!< SCRATCH3 (Bit 0) */ +#define POWMAN_SCRATCH3_SCRATCH3_Msk (0xffffffffUL) /*!< SCRATCH3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH4 ======================================================== */ +#define POWMAN_SCRATCH4_SCRATCH4_Pos (0UL) /*!< SCRATCH4 (Bit 0) */ +#define POWMAN_SCRATCH4_SCRATCH4_Msk (0xffffffffUL) /*!< SCRATCH4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH5 ======================================================== */ +#define POWMAN_SCRATCH5_SCRATCH5_Pos (0UL) /*!< SCRATCH5 (Bit 0) */ +#define POWMAN_SCRATCH5_SCRATCH5_Msk (0xffffffffUL) /*!< SCRATCH5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH6 ======================================================== */ +#define POWMAN_SCRATCH6_SCRATCH6_Pos (0UL) /*!< SCRATCH6 (Bit 0) */ +#define POWMAN_SCRATCH6_SCRATCH6_Msk (0xffffffffUL) /*!< SCRATCH6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH7 ======================================================== */ +#define POWMAN_SCRATCH7_SCRATCH7_Pos (0UL) /*!< SCRATCH7 (Bit 0) */ +#define POWMAN_SCRATCH7_SCRATCH7_Msk (0xffffffffUL) /*!< SCRATCH7 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= BOOT0 ========================================================= */ +#define POWMAN_BOOT0_BOOT0_Pos (0UL) /*!< BOOT0 (Bit 0) */ +#define POWMAN_BOOT0_BOOT0_Msk (0xffffffffUL) /*!< BOOT0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= BOOT1 ========================================================= */ +#define POWMAN_BOOT1_BOOT1_Pos (0UL) /*!< BOOT1 (Bit 0) */ +#define POWMAN_BOOT1_BOOT1_Msk (0xffffffffUL) /*!< BOOT1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= BOOT2 ========================================================= */ +#define POWMAN_BOOT2_BOOT2_Pos (0UL) /*!< BOOT2 (Bit 0) */ +#define POWMAN_BOOT2_BOOT2_Msk (0xffffffffUL) /*!< BOOT2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= BOOT3 ========================================================= */ +#define POWMAN_BOOT3_BOOT3_Pos (0UL) /*!< BOOT3 (Bit 0) */ +#define POWMAN_BOOT3_BOOT3_Msk (0xffffffffUL) /*!< BOOT3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTR ========================================================== */ +#define POWMAN_INTR_PWRUP_WHILE_WAITING_Pos (3UL) /*!< PWRUP_WHILE_WAITING (Bit 3) */ +#define POWMAN_INTR_PWRUP_WHILE_WAITING_Msk (0x8UL) /*!< PWRUP_WHILE_WAITING (Bitfield-Mask: 0x01) */ +#define POWMAN_INTR_STATE_REQ_IGNORED_Pos (2UL) /*!< STATE_REQ_IGNORED (Bit 2) */ +#define POWMAN_INTR_STATE_REQ_IGNORED_Msk (0x4UL) /*!< STATE_REQ_IGNORED (Bitfield-Mask: 0x01) */ +#define POWMAN_INTR_TIMER_Pos (1UL) /*!< TIMER (Bit 1) */ +#define POWMAN_INTR_TIMER_Msk (0x2UL) /*!< TIMER (Bitfield-Mask: 0x01) */ +#define POWMAN_INTR_VREG_OUTPUT_LOW_Pos (0UL) /*!< VREG_OUTPUT_LOW (Bit 0) */ +#define POWMAN_INTR_VREG_OUTPUT_LOW_Msk (0x1UL) /*!< VREG_OUTPUT_LOW (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ +#define POWMAN_INTE_PWRUP_WHILE_WAITING_Pos (3UL) /*!< PWRUP_WHILE_WAITING (Bit 3) */ +#define POWMAN_INTE_PWRUP_WHILE_WAITING_Msk (0x8UL) /*!< PWRUP_WHILE_WAITING (Bitfield-Mask: 0x01) */ +#define POWMAN_INTE_STATE_REQ_IGNORED_Pos (2UL) /*!< STATE_REQ_IGNORED (Bit 2) */ +#define POWMAN_INTE_STATE_REQ_IGNORED_Msk (0x4UL) /*!< STATE_REQ_IGNORED (Bitfield-Mask: 0x01) */ +#define POWMAN_INTE_TIMER_Pos (1UL) /*!< TIMER (Bit 1) */ +#define POWMAN_INTE_TIMER_Msk (0x2UL) /*!< TIMER (Bitfield-Mask: 0x01) */ +#define POWMAN_INTE_VREG_OUTPUT_LOW_Pos (0UL) /*!< VREG_OUTPUT_LOW (Bit 0) */ +#define POWMAN_INTE_VREG_OUTPUT_LOW_Msk (0x1UL) /*!< VREG_OUTPUT_LOW (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define POWMAN_INTF_PWRUP_WHILE_WAITING_Pos (3UL) /*!< PWRUP_WHILE_WAITING (Bit 3) */ +#define POWMAN_INTF_PWRUP_WHILE_WAITING_Msk (0x8UL) /*!< PWRUP_WHILE_WAITING (Bitfield-Mask: 0x01) */ +#define POWMAN_INTF_STATE_REQ_IGNORED_Pos (2UL) /*!< STATE_REQ_IGNORED (Bit 2) */ +#define POWMAN_INTF_STATE_REQ_IGNORED_Msk (0x4UL) /*!< STATE_REQ_IGNORED (Bitfield-Mask: 0x01) */ +#define POWMAN_INTF_TIMER_Pos (1UL) /*!< TIMER (Bit 1) */ +#define POWMAN_INTF_TIMER_Msk (0x2UL) /*!< TIMER (Bitfield-Mask: 0x01) */ +#define POWMAN_INTF_VREG_OUTPUT_LOW_Pos (0UL) /*!< VREG_OUTPUT_LOW (Bit 0) */ +#define POWMAN_INTF_VREG_OUTPUT_LOW_Msk (0x1UL) /*!< VREG_OUTPUT_LOW (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ +#define POWMAN_INTS_PWRUP_WHILE_WAITING_Pos (3UL) /*!< PWRUP_WHILE_WAITING (Bit 3) */ +#define POWMAN_INTS_PWRUP_WHILE_WAITING_Msk (0x8UL) /*!< PWRUP_WHILE_WAITING (Bitfield-Mask: 0x01) */ +#define POWMAN_INTS_STATE_REQ_IGNORED_Pos (2UL) /*!< STATE_REQ_IGNORED (Bit 2) */ +#define POWMAN_INTS_STATE_REQ_IGNORED_Msk (0x4UL) /*!< STATE_REQ_IGNORED (Bitfield-Mask: 0x01) */ +#define POWMAN_INTS_TIMER_Pos (1UL) /*!< TIMER (Bit 1) */ +#define POWMAN_INTS_TIMER_Msk (0x2UL) /*!< TIMER (Bitfield-Mask: 0x01) */ +#define POWMAN_INTS_VREG_OUTPUT_LOW_Pos (0UL) /*!< VREG_OUTPUT_LOW (Bit 0) */ +#define POWMAN_INTS_VREG_OUTPUT_LOW_Msk (0x1UL) /*!< VREG_OUTPUT_LOW (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ WATCHDOG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define WATCHDOG_CTRL_TRIGGER_Pos (31UL) /*!< TRIGGER (Bit 31) */ +#define WATCHDOG_CTRL_TRIGGER_Msk (0x80000000UL) /*!< TRIGGER (Bitfield-Mask: 0x01) */ +#define WATCHDOG_CTRL_ENABLE_Pos (30UL) /*!< ENABLE (Bit 30) */ +#define WATCHDOG_CTRL_ENABLE_Msk (0x40000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define WATCHDOG_CTRL_PAUSE_DBG1_Pos (26UL) /*!< PAUSE_DBG1 (Bit 26) */ +#define WATCHDOG_CTRL_PAUSE_DBG1_Msk (0x4000000UL) /*!< PAUSE_DBG1 (Bitfield-Mask: 0x01) */ +#define WATCHDOG_CTRL_PAUSE_DBG0_Pos (25UL) /*!< PAUSE_DBG0 (Bit 25) */ +#define WATCHDOG_CTRL_PAUSE_DBG0_Msk (0x2000000UL) /*!< PAUSE_DBG0 (Bitfield-Mask: 0x01) */ +#define WATCHDOG_CTRL_PAUSE_JTAG_Pos (24UL) /*!< PAUSE_JTAG (Bit 24) */ +#define WATCHDOG_CTRL_PAUSE_JTAG_Msk (0x1000000UL) /*!< PAUSE_JTAG (Bitfield-Mask: 0x01) */ +#define WATCHDOG_CTRL_TIME_Pos (0UL) /*!< TIME (Bit 0) */ +#define WATCHDOG_CTRL_TIME_Msk (0xffffffUL) /*!< TIME (Bitfield-Mask: 0xffffff) */ +/* ========================================================= LOAD ========================================================== */ +#define WATCHDOG_LOAD_LOAD_Pos (0UL) /*!< LOAD (Bit 0) */ +#define WATCHDOG_LOAD_LOAD_Msk (0xffffffUL) /*!< LOAD (Bitfield-Mask: 0xffffff) */ +/* ======================================================== REASON ========================================================= */ +#define WATCHDOG_REASON_FORCE_Pos (1UL) /*!< FORCE (Bit 1) */ +#define WATCHDOG_REASON_FORCE_Msk (0x2UL) /*!< FORCE (Bitfield-Mask: 0x01) */ +#define WATCHDOG_REASON_TIMER_Pos (0UL) /*!< TIMER (Bit 0) */ +#define WATCHDOG_REASON_TIMER_Msk (0x1UL) /*!< TIMER (Bitfield-Mask: 0x01) */ +/* ======================================================= SCRATCH0 ======================================================== */ +#define WATCHDOG_SCRATCH0_SCRATCH0_Pos (0UL) /*!< SCRATCH0 (Bit 0) */ +#define WATCHDOG_SCRATCH0_SCRATCH0_Msk (0xffffffffUL) /*!< SCRATCH0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH1 ======================================================== */ +#define WATCHDOG_SCRATCH1_SCRATCH1_Pos (0UL) /*!< SCRATCH1 (Bit 0) */ +#define WATCHDOG_SCRATCH1_SCRATCH1_Msk (0xffffffffUL) /*!< SCRATCH1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH2 ======================================================== */ +#define WATCHDOG_SCRATCH2_SCRATCH2_Pos (0UL) /*!< SCRATCH2 (Bit 0) */ +#define WATCHDOG_SCRATCH2_SCRATCH2_Msk (0xffffffffUL) /*!< SCRATCH2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH3 ======================================================== */ +#define WATCHDOG_SCRATCH3_SCRATCH3_Pos (0UL) /*!< SCRATCH3 (Bit 0) */ +#define WATCHDOG_SCRATCH3_SCRATCH3_Msk (0xffffffffUL) /*!< SCRATCH3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH4 ======================================================== */ +#define WATCHDOG_SCRATCH4_SCRATCH4_Pos (0UL) /*!< SCRATCH4 (Bit 0) */ +#define WATCHDOG_SCRATCH4_SCRATCH4_Msk (0xffffffffUL) /*!< SCRATCH4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH5 ======================================================== */ +#define WATCHDOG_SCRATCH5_SCRATCH5_Pos (0UL) /*!< SCRATCH5 (Bit 0) */ +#define WATCHDOG_SCRATCH5_SCRATCH5_Msk (0xffffffffUL) /*!< SCRATCH5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH6 ======================================================== */ +#define WATCHDOG_SCRATCH6_SCRATCH6_Pos (0UL) /*!< SCRATCH6 (Bit 0) */ +#define WATCHDOG_SCRATCH6_SCRATCH6_Msk (0xffffffffUL) /*!< SCRATCH6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH7 ======================================================== */ +#define WATCHDOG_SCRATCH7_SCRATCH7_Pos (0UL) /*!< SCRATCH7 (Bit 0) */ +#define WATCHDOG_SCRATCH7_SCRATCH7_Msk (0xffffffffUL) /*!< SCRATCH7 (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== CH0_READ_ADDR ===================================================== */ +#define DMA_CH0_READ_ADDR_CH0_READ_ADDR_Pos (0UL) /*!< CH0_READ_ADDR (Bit 0) */ +#define DMA_CH0_READ_ADDR_CH0_READ_ADDR_Msk (0xffffffffUL) /*!< CH0_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH0_WRITE_ADDR ===================================================== */ +#define DMA_CH0_WRITE_ADDR_CH0_WRITE_ADDR_Pos (0UL) /*!< CH0_WRITE_ADDR (Bit 0) */ +#define DMA_CH0_WRITE_ADDR_CH0_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH0_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH0_TRANS_COUNT ==================================================== */ +#define DMA_CH0_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH0_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH0_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH0_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH0_CTRL_TRIG ===================================================== */ +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH0_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH0_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH0_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH0_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH0_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH0_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH0_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH0_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH0_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH0_AL1_CTRL ====================================================== */ +#define DMA_CH0_AL1_CTRL_CH0_AL1_CTRL_Pos (0UL) /*!< CH0_AL1_CTRL (Bit 0) */ +#define DMA_CH0_AL1_CTRL_CH0_AL1_CTRL_Msk (0xffffffffUL) /*!< CH0_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH0_AL1_READ_ADDR =================================================== */ +#define DMA_CH0_AL1_READ_ADDR_CH0_AL1_READ_ADDR_Pos (0UL) /*!< CH0_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH0_AL1_READ_ADDR_CH0_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH0_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH0_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH0_AL1_WRITE_ADDR_CH0_AL1_WRITE_ADDR_Pos (0UL) /*!< CH0_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH0_AL1_WRITE_ADDR_CH0_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH0_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH0_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_CH0_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH0_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_CH0_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH0_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH0_AL2_CTRL ====================================================== */ +#define DMA_CH0_AL2_CTRL_CH0_AL2_CTRL_Pos (0UL) /*!< CH0_AL2_CTRL (Bit 0) */ +#define DMA_CH0_AL2_CTRL_CH0_AL2_CTRL_Msk (0xffffffffUL) /*!< CH0_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH0_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH0_AL2_TRANS_COUNT_CH0_AL2_TRANS_COUNT_Pos (0UL) /*!< CH0_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH0_AL2_TRANS_COUNT_CH0_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH0_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH0_AL2_READ_ADDR =================================================== */ +#define DMA_CH0_AL2_READ_ADDR_CH0_AL2_READ_ADDR_Pos (0UL) /*!< CH0_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH0_AL2_READ_ADDR_CH0_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH0_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH0_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_CH0_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH0_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_CH0_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH0_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH0_AL3_CTRL ====================================================== */ +#define DMA_CH0_AL3_CTRL_CH0_AL3_CTRL_Pos (0UL) /*!< CH0_AL3_CTRL (Bit 0) */ +#define DMA_CH0_AL3_CTRL_CH0_AL3_CTRL_Msk (0xffffffffUL) /*!< CH0_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH0_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH0_AL3_WRITE_ADDR_CH0_AL3_WRITE_ADDR_Pos (0UL) /*!< CH0_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH0_AL3_WRITE_ADDR_CH0_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH0_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH0_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH0_AL3_TRANS_COUNT_CH0_AL3_TRANS_COUNT_Pos (0UL) /*!< CH0_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH0_AL3_TRANS_COUNT_CH0_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH0_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH0_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH0_AL3_READ_ADDR_TRIG_CH0_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH0_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH0_AL3_READ_ADDR_TRIG_CH0_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH0_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH1_READ_ADDR ===================================================== */ +#define DMA_CH1_READ_ADDR_CH1_READ_ADDR_Pos (0UL) /*!< CH1_READ_ADDR (Bit 0) */ +#define DMA_CH1_READ_ADDR_CH1_READ_ADDR_Msk (0xffffffffUL) /*!< CH1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH1_WRITE_ADDR ===================================================== */ +#define DMA_CH1_WRITE_ADDR_CH1_WRITE_ADDR_Pos (0UL) /*!< CH1_WRITE_ADDR (Bit 0) */ +#define DMA_CH1_WRITE_ADDR_CH1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH1_TRANS_COUNT ==================================================== */ +#define DMA_CH1_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH1_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH1_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH1_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH1_CTRL_TRIG ===================================================== */ +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH1_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH1_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH1_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH1_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH1_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH1_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH1_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH1_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH1_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH1_AL1_CTRL ====================================================== */ +#define DMA_CH1_AL1_CTRL_CH1_AL1_CTRL_Pos (0UL) /*!< CH1_AL1_CTRL (Bit 0) */ +#define DMA_CH1_AL1_CTRL_CH1_AL1_CTRL_Msk (0xffffffffUL) /*!< CH1_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH1_AL1_READ_ADDR =================================================== */ +#define DMA_CH1_AL1_READ_ADDR_CH1_AL1_READ_ADDR_Pos (0UL) /*!< CH1_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH1_AL1_READ_ADDR_CH1_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH1_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH1_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH1_AL1_WRITE_ADDR_CH1_AL1_WRITE_ADDR_Pos (0UL) /*!< CH1_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH1_AL1_WRITE_ADDR_CH1_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH1_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH1_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_CH1_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH1_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_CH1_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH1_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH1_AL2_CTRL ====================================================== */ +#define DMA_CH1_AL2_CTRL_CH1_AL2_CTRL_Pos (0UL) /*!< CH1_AL2_CTRL (Bit 0) */ +#define DMA_CH1_AL2_CTRL_CH1_AL2_CTRL_Msk (0xffffffffUL) /*!< CH1_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH1_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH1_AL2_TRANS_COUNT_CH1_AL2_TRANS_COUNT_Pos (0UL) /*!< CH1_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH1_AL2_TRANS_COUNT_CH1_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH1_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH1_AL2_READ_ADDR =================================================== */ +#define DMA_CH1_AL2_READ_ADDR_CH1_AL2_READ_ADDR_Pos (0UL) /*!< CH1_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH1_AL2_READ_ADDR_CH1_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH1_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH1_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_CH1_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH1_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_CH1_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH1_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH1_AL3_CTRL ====================================================== */ +#define DMA_CH1_AL3_CTRL_CH1_AL3_CTRL_Pos (0UL) /*!< CH1_AL3_CTRL (Bit 0) */ +#define DMA_CH1_AL3_CTRL_CH1_AL3_CTRL_Msk (0xffffffffUL) /*!< CH1_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH1_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH1_AL3_WRITE_ADDR_CH1_AL3_WRITE_ADDR_Pos (0UL) /*!< CH1_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH1_AL3_WRITE_ADDR_CH1_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH1_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH1_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH1_AL3_TRANS_COUNT_CH1_AL3_TRANS_COUNT_Pos (0UL) /*!< CH1_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH1_AL3_TRANS_COUNT_CH1_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH1_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH1_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH1_AL3_READ_ADDR_TRIG_CH1_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH1_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH1_AL3_READ_ADDR_TRIG_CH1_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH1_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH2_READ_ADDR ===================================================== */ +#define DMA_CH2_READ_ADDR_CH2_READ_ADDR_Pos (0UL) /*!< CH2_READ_ADDR (Bit 0) */ +#define DMA_CH2_READ_ADDR_CH2_READ_ADDR_Msk (0xffffffffUL) /*!< CH2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH2_WRITE_ADDR ===================================================== */ +#define DMA_CH2_WRITE_ADDR_CH2_WRITE_ADDR_Pos (0UL) /*!< CH2_WRITE_ADDR (Bit 0) */ +#define DMA_CH2_WRITE_ADDR_CH2_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH2_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH2_TRANS_COUNT ==================================================== */ +#define DMA_CH2_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH2_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH2_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH2_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH2_CTRL_TRIG ===================================================== */ +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH2_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH2_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH2_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH2_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH2_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH2_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH2_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH2_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH2_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH2_AL1_CTRL ====================================================== */ +#define DMA_CH2_AL1_CTRL_CH2_AL1_CTRL_Pos (0UL) /*!< CH2_AL1_CTRL (Bit 0) */ +#define DMA_CH2_AL1_CTRL_CH2_AL1_CTRL_Msk (0xffffffffUL) /*!< CH2_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH2_AL1_READ_ADDR =================================================== */ +#define DMA_CH2_AL1_READ_ADDR_CH2_AL1_READ_ADDR_Pos (0UL) /*!< CH2_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH2_AL1_READ_ADDR_CH2_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH2_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH2_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH2_AL1_WRITE_ADDR_CH2_AL1_WRITE_ADDR_Pos (0UL) /*!< CH2_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH2_AL1_WRITE_ADDR_CH2_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH2_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH2_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_CH2_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH2_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_CH2_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH2_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH2_AL2_CTRL ====================================================== */ +#define DMA_CH2_AL2_CTRL_CH2_AL2_CTRL_Pos (0UL) /*!< CH2_AL2_CTRL (Bit 0) */ +#define DMA_CH2_AL2_CTRL_CH2_AL2_CTRL_Msk (0xffffffffUL) /*!< CH2_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH2_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH2_AL2_TRANS_COUNT_CH2_AL2_TRANS_COUNT_Pos (0UL) /*!< CH2_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH2_AL2_TRANS_COUNT_CH2_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH2_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH2_AL2_READ_ADDR =================================================== */ +#define DMA_CH2_AL2_READ_ADDR_CH2_AL2_READ_ADDR_Pos (0UL) /*!< CH2_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH2_AL2_READ_ADDR_CH2_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH2_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH2_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_CH2_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH2_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_CH2_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH2_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH2_AL3_CTRL ====================================================== */ +#define DMA_CH2_AL3_CTRL_CH2_AL3_CTRL_Pos (0UL) /*!< CH2_AL3_CTRL (Bit 0) */ +#define DMA_CH2_AL3_CTRL_CH2_AL3_CTRL_Msk (0xffffffffUL) /*!< CH2_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH2_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH2_AL3_WRITE_ADDR_CH2_AL3_WRITE_ADDR_Pos (0UL) /*!< CH2_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH2_AL3_WRITE_ADDR_CH2_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH2_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH2_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH2_AL3_TRANS_COUNT_CH2_AL3_TRANS_COUNT_Pos (0UL) /*!< CH2_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH2_AL3_TRANS_COUNT_CH2_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH2_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH2_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH2_AL3_READ_ADDR_TRIG_CH2_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH2_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH2_AL3_READ_ADDR_TRIG_CH2_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH2_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH3_READ_ADDR ===================================================== */ +#define DMA_CH3_READ_ADDR_CH3_READ_ADDR_Pos (0UL) /*!< CH3_READ_ADDR (Bit 0) */ +#define DMA_CH3_READ_ADDR_CH3_READ_ADDR_Msk (0xffffffffUL) /*!< CH3_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH3_WRITE_ADDR ===================================================== */ +#define DMA_CH3_WRITE_ADDR_CH3_WRITE_ADDR_Pos (0UL) /*!< CH3_WRITE_ADDR (Bit 0) */ +#define DMA_CH3_WRITE_ADDR_CH3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH3_TRANS_COUNT ==================================================== */ +#define DMA_CH3_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH3_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH3_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH3_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH3_CTRL_TRIG ===================================================== */ +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH3_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH3_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH3_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH3_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH3_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH3_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH3_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH3_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH3_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH3_AL1_CTRL ====================================================== */ +#define DMA_CH3_AL1_CTRL_CH3_AL1_CTRL_Pos (0UL) /*!< CH3_AL1_CTRL (Bit 0) */ +#define DMA_CH3_AL1_CTRL_CH3_AL1_CTRL_Msk (0xffffffffUL) /*!< CH3_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH3_AL1_READ_ADDR =================================================== */ +#define DMA_CH3_AL1_READ_ADDR_CH3_AL1_READ_ADDR_Pos (0UL) /*!< CH3_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH3_AL1_READ_ADDR_CH3_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH3_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH3_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH3_AL1_WRITE_ADDR_CH3_AL1_WRITE_ADDR_Pos (0UL) /*!< CH3_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH3_AL1_WRITE_ADDR_CH3_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH3_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH3_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_CH3_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH3_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_CH3_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH3_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH3_AL2_CTRL ====================================================== */ +#define DMA_CH3_AL2_CTRL_CH3_AL2_CTRL_Pos (0UL) /*!< CH3_AL2_CTRL (Bit 0) */ +#define DMA_CH3_AL2_CTRL_CH3_AL2_CTRL_Msk (0xffffffffUL) /*!< CH3_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH3_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH3_AL2_TRANS_COUNT_CH3_AL2_TRANS_COUNT_Pos (0UL) /*!< CH3_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH3_AL2_TRANS_COUNT_CH3_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH3_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH3_AL2_READ_ADDR =================================================== */ +#define DMA_CH3_AL2_READ_ADDR_CH3_AL2_READ_ADDR_Pos (0UL) /*!< CH3_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH3_AL2_READ_ADDR_CH3_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH3_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH3_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_CH3_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH3_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_CH3_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH3_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH3_AL3_CTRL ====================================================== */ +#define DMA_CH3_AL3_CTRL_CH3_AL3_CTRL_Pos (0UL) /*!< CH3_AL3_CTRL (Bit 0) */ +#define DMA_CH3_AL3_CTRL_CH3_AL3_CTRL_Msk (0xffffffffUL) /*!< CH3_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH3_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH3_AL3_WRITE_ADDR_CH3_AL3_WRITE_ADDR_Pos (0UL) /*!< CH3_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH3_AL3_WRITE_ADDR_CH3_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH3_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH3_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH3_AL3_TRANS_COUNT_CH3_AL3_TRANS_COUNT_Pos (0UL) /*!< CH3_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH3_AL3_TRANS_COUNT_CH3_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH3_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH3_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH3_AL3_READ_ADDR_TRIG_CH3_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH3_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH3_AL3_READ_ADDR_TRIG_CH3_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH3_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH4_READ_ADDR ===================================================== */ +#define DMA_CH4_READ_ADDR_CH4_READ_ADDR_Pos (0UL) /*!< CH4_READ_ADDR (Bit 0) */ +#define DMA_CH4_READ_ADDR_CH4_READ_ADDR_Msk (0xffffffffUL) /*!< CH4_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH4_WRITE_ADDR ===================================================== */ +#define DMA_CH4_WRITE_ADDR_CH4_WRITE_ADDR_Pos (0UL) /*!< CH4_WRITE_ADDR (Bit 0) */ +#define DMA_CH4_WRITE_ADDR_CH4_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH4_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH4_TRANS_COUNT ==================================================== */ +#define DMA_CH4_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH4_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH4_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH4_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH4_CTRL_TRIG ===================================================== */ +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH4_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH4_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH4_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH4_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH4_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH4_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH4_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH4_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH4_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH4_AL1_CTRL ====================================================== */ +#define DMA_CH4_AL1_CTRL_CH4_AL1_CTRL_Pos (0UL) /*!< CH4_AL1_CTRL (Bit 0) */ +#define DMA_CH4_AL1_CTRL_CH4_AL1_CTRL_Msk (0xffffffffUL) /*!< CH4_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH4_AL1_READ_ADDR =================================================== */ +#define DMA_CH4_AL1_READ_ADDR_CH4_AL1_READ_ADDR_Pos (0UL) /*!< CH4_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH4_AL1_READ_ADDR_CH4_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH4_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH4_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH4_AL1_WRITE_ADDR_CH4_AL1_WRITE_ADDR_Pos (0UL) /*!< CH4_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH4_AL1_WRITE_ADDR_CH4_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH4_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH4_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_CH4_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH4_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_CH4_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH4_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH4_AL2_CTRL ====================================================== */ +#define DMA_CH4_AL2_CTRL_CH4_AL2_CTRL_Pos (0UL) /*!< CH4_AL2_CTRL (Bit 0) */ +#define DMA_CH4_AL2_CTRL_CH4_AL2_CTRL_Msk (0xffffffffUL) /*!< CH4_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH4_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH4_AL2_TRANS_COUNT_CH4_AL2_TRANS_COUNT_Pos (0UL) /*!< CH4_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH4_AL2_TRANS_COUNT_CH4_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH4_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH4_AL2_READ_ADDR =================================================== */ +#define DMA_CH4_AL2_READ_ADDR_CH4_AL2_READ_ADDR_Pos (0UL) /*!< CH4_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH4_AL2_READ_ADDR_CH4_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH4_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH4_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_CH4_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH4_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_CH4_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH4_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH4_AL3_CTRL ====================================================== */ +#define DMA_CH4_AL3_CTRL_CH4_AL3_CTRL_Pos (0UL) /*!< CH4_AL3_CTRL (Bit 0) */ +#define DMA_CH4_AL3_CTRL_CH4_AL3_CTRL_Msk (0xffffffffUL) /*!< CH4_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH4_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH4_AL3_WRITE_ADDR_CH4_AL3_WRITE_ADDR_Pos (0UL) /*!< CH4_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH4_AL3_WRITE_ADDR_CH4_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH4_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH4_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH4_AL3_TRANS_COUNT_CH4_AL3_TRANS_COUNT_Pos (0UL) /*!< CH4_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH4_AL3_TRANS_COUNT_CH4_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH4_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH4_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH4_AL3_READ_ADDR_TRIG_CH4_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH4_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH4_AL3_READ_ADDR_TRIG_CH4_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH4_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH5_READ_ADDR ===================================================== */ +#define DMA_CH5_READ_ADDR_CH5_READ_ADDR_Pos (0UL) /*!< CH5_READ_ADDR (Bit 0) */ +#define DMA_CH5_READ_ADDR_CH5_READ_ADDR_Msk (0xffffffffUL) /*!< CH5_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH5_WRITE_ADDR ===================================================== */ +#define DMA_CH5_WRITE_ADDR_CH5_WRITE_ADDR_Pos (0UL) /*!< CH5_WRITE_ADDR (Bit 0) */ +#define DMA_CH5_WRITE_ADDR_CH5_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH5_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH5_TRANS_COUNT ==================================================== */ +#define DMA_CH5_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH5_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH5_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH5_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH5_CTRL_TRIG ===================================================== */ +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH5_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH5_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH5_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH5_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH5_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH5_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH5_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH5_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH5_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH5_AL1_CTRL ====================================================== */ +#define DMA_CH5_AL1_CTRL_CH5_AL1_CTRL_Pos (0UL) /*!< CH5_AL1_CTRL (Bit 0) */ +#define DMA_CH5_AL1_CTRL_CH5_AL1_CTRL_Msk (0xffffffffUL) /*!< CH5_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH5_AL1_READ_ADDR =================================================== */ +#define DMA_CH5_AL1_READ_ADDR_CH5_AL1_READ_ADDR_Pos (0UL) /*!< CH5_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH5_AL1_READ_ADDR_CH5_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH5_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH5_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH5_AL1_WRITE_ADDR_CH5_AL1_WRITE_ADDR_Pos (0UL) /*!< CH5_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH5_AL1_WRITE_ADDR_CH5_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH5_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH5_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_CH5_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH5_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_CH5_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH5_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH5_AL2_CTRL ====================================================== */ +#define DMA_CH5_AL2_CTRL_CH5_AL2_CTRL_Pos (0UL) /*!< CH5_AL2_CTRL (Bit 0) */ +#define DMA_CH5_AL2_CTRL_CH5_AL2_CTRL_Msk (0xffffffffUL) /*!< CH5_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH5_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH5_AL2_TRANS_COUNT_CH5_AL2_TRANS_COUNT_Pos (0UL) /*!< CH5_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH5_AL2_TRANS_COUNT_CH5_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH5_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH5_AL2_READ_ADDR =================================================== */ +#define DMA_CH5_AL2_READ_ADDR_CH5_AL2_READ_ADDR_Pos (0UL) /*!< CH5_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH5_AL2_READ_ADDR_CH5_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH5_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH5_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_CH5_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH5_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_CH5_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH5_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH5_AL3_CTRL ====================================================== */ +#define DMA_CH5_AL3_CTRL_CH5_AL3_CTRL_Pos (0UL) /*!< CH5_AL3_CTRL (Bit 0) */ +#define DMA_CH5_AL3_CTRL_CH5_AL3_CTRL_Msk (0xffffffffUL) /*!< CH5_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH5_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH5_AL3_WRITE_ADDR_CH5_AL3_WRITE_ADDR_Pos (0UL) /*!< CH5_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH5_AL3_WRITE_ADDR_CH5_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH5_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH5_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH5_AL3_TRANS_COUNT_CH5_AL3_TRANS_COUNT_Pos (0UL) /*!< CH5_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH5_AL3_TRANS_COUNT_CH5_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH5_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH5_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH5_AL3_READ_ADDR_TRIG_CH5_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH5_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH5_AL3_READ_ADDR_TRIG_CH5_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH5_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH6_READ_ADDR ===================================================== */ +#define DMA_CH6_READ_ADDR_CH6_READ_ADDR_Pos (0UL) /*!< CH6_READ_ADDR (Bit 0) */ +#define DMA_CH6_READ_ADDR_CH6_READ_ADDR_Msk (0xffffffffUL) /*!< CH6_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH6_WRITE_ADDR ===================================================== */ +#define DMA_CH6_WRITE_ADDR_CH6_WRITE_ADDR_Pos (0UL) /*!< CH6_WRITE_ADDR (Bit 0) */ +#define DMA_CH6_WRITE_ADDR_CH6_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH6_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH6_TRANS_COUNT ==================================================== */ +#define DMA_CH6_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH6_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH6_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH6_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH6_CTRL_TRIG ===================================================== */ +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH6_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH6_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH6_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH6_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH6_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH6_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH6_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH6_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH6_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH6_AL1_CTRL ====================================================== */ +#define DMA_CH6_AL1_CTRL_CH6_AL1_CTRL_Pos (0UL) /*!< CH6_AL1_CTRL (Bit 0) */ +#define DMA_CH6_AL1_CTRL_CH6_AL1_CTRL_Msk (0xffffffffUL) /*!< CH6_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH6_AL1_READ_ADDR =================================================== */ +#define DMA_CH6_AL1_READ_ADDR_CH6_AL1_READ_ADDR_Pos (0UL) /*!< CH6_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH6_AL1_READ_ADDR_CH6_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH6_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH6_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH6_AL1_WRITE_ADDR_CH6_AL1_WRITE_ADDR_Pos (0UL) /*!< CH6_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH6_AL1_WRITE_ADDR_CH6_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH6_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH6_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_CH6_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH6_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_CH6_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH6_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH6_AL2_CTRL ====================================================== */ +#define DMA_CH6_AL2_CTRL_CH6_AL2_CTRL_Pos (0UL) /*!< CH6_AL2_CTRL (Bit 0) */ +#define DMA_CH6_AL2_CTRL_CH6_AL2_CTRL_Msk (0xffffffffUL) /*!< CH6_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH6_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH6_AL2_TRANS_COUNT_CH6_AL2_TRANS_COUNT_Pos (0UL) /*!< CH6_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH6_AL2_TRANS_COUNT_CH6_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH6_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH6_AL2_READ_ADDR =================================================== */ +#define DMA_CH6_AL2_READ_ADDR_CH6_AL2_READ_ADDR_Pos (0UL) /*!< CH6_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH6_AL2_READ_ADDR_CH6_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH6_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH6_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_CH6_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH6_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_CH6_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH6_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH6_AL3_CTRL ====================================================== */ +#define DMA_CH6_AL3_CTRL_CH6_AL3_CTRL_Pos (0UL) /*!< CH6_AL3_CTRL (Bit 0) */ +#define DMA_CH6_AL3_CTRL_CH6_AL3_CTRL_Msk (0xffffffffUL) /*!< CH6_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH6_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH6_AL3_WRITE_ADDR_CH6_AL3_WRITE_ADDR_Pos (0UL) /*!< CH6_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH6_AL3_WRITE_ADDR_CH6_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH6_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH6_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH6_AL3_TRANS_COUNT_CH6_AL3_TRANS_COUNT_Pos (0UL) /*!< CH6_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH6_AL3_TRANS_COUNT_CH6_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH6_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH6_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH6_AL3_READ_ADDR_TRIG_CH6_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH6_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH6_AL3_READ_ADDR_TRIG_CH6_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH6_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH7_READ_ADDR ===================================================== */ +#define DMA_CH7_READ_ADDR_CH7_READ_ADDR_Pos (0UL) /*!< CH7_READ_ADDR (Bit 0) */ +#define DMA_CH7_READ_ADDR_CH7_READ_ADDR_Msk (0xffffffffUL) /*!< CH7_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH7_WRITE_ADDR ===================================================== */ +#define DMA_CH7_WRITE_ADDR_CH7_WRITE_ADDR_Pos (0UL) /*!< CH7_WRITE_ADDR (Bit 0) */ +#define DMA_CH7_WRITE_ADDR_CH7_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH7_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH7_TRANS_COUNT ==================================================== */ +#define DMA_CH7_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH7_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH7_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH7_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH7_CTRL_TRIG ===================================================== */ +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH7_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH7_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH7_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH7_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH7_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH7_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH7_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH7_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH7_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH7_AL1_CTRL ====================================================== */ +#define DMA_CH7_AL1_CTRL_CH7_AL1_CTRL_Pos (0UL) /*!< CH7_AL1_CTRL (Bit 0) */ +#define DMA_CH7_AL1_CTRL_CH7_AL1_CTRL_Msk (0xffffffffUL) /*!< CH7_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH7_AL1_READ_ADDR =================================================== */ +#define DMA_CH7_AL1_READ_ADDR_CH7_AL1_READ_ADDR_Pos (0UL) /*!< CH7_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH7_AL1_READ_ADDR_CH7_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH7_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH7_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH7_AL1_WRITE_ADDR_CH7_AL1_WRITE_ADDR_Pos (0UL) /*!< CH7_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH7_AL1_WRITE_ADDR_CH7_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH7_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH7_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_CH7_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH7_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_CH7_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH7_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH7_AL2_CTRL ====================================================== */ +#define DMA_CH7_AL2_CTRL_CH7_AL2_CTRL_Pos (0UL) /*!< CH7_AL2_CTRL (Bit 0) */ +#define DMA_CH7_AL2_CTRL_CH7_AL2_CTRL_Msk (0xffffffffUL) /*!< CH7_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH7_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH7_AL2_TRANS_COUNT_CH7_AL2_TRANS_COUNT_Pos (0UL) /*!< CH7_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH7_AL2_TRANS_COUNT_CH7_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH7_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH7_AL2_READ_ADDR =================================================== */ +#define DMA_CH7_AL2_READ_ADDR_CH7_AL2_READ_ADDR_Pos (0UL) /*!< CH7_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH7_AL2_READ_ADDR_CH7_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH7_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH7_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_CH7_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH7_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_CH7_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH7_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH7_AL3_CTRL ====================================================== */ +#define DMA_CH7_AL3_CTRL_CH7_AL3_CTRL_Pos (0UL) /*!< CH7_AL3_CTRL (Bit 0) */ +#define DMA_CH7_AL3_CTRL_CH7_AL3_CTRL_Msk (0xffffffffUL) /*!< CH7_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH7_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH7_AL3_WRITE_ADDR_CH7_AL3_WRITE_ADDR_Pos (0UL) /*!< CH7_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH7_AL3_WRITE_ADDR_CH7_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH7_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH7_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH7_AL3_TRANS_COUNT_CH7_AL3_TRANS_COUNT_Pos (0UL) /*!< CH7_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH7_AL3_TRANS_COUNT_CH7_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH7_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH7_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH7_AL3_READ_ADDR_TRIG_CH7_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH7_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH7_AL3_READ_ADDR_TRIG_CH7_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH7_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH8_READ_ADDR ===================================================== */ +#define DMA_CH8_READ_ADDR_CH8_READ_ADDR_Pos (0UL) /*!< CH8_READ_ADDR (Bit 0) */ +#define DMA_CH8_READ_ADDR_CH8_READ_ADDR_Msk (0xffffffffUL) /*!< CH8_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH8_WRITE_ADDR ===================================================== */ +#define DMA_CH8_WRITE_ADDR_CH8_WRITE_ADDR_Pos (0UL) /*!< CH8_WRITE_ADDR (Bit 0) */ +#define DMA_CH8_WRITE_ADDR_CH8_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH8_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH8_TRANS_COUNT ==================================================== */ +#define DMA_CH8_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH8_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH8_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH8_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH8_CTRL_TRIG ===================================================== */ +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH8_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH8_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH8_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH8_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH8_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH8_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH8_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH8_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH8_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH8_AL1_CTRL ====================================================== */ +#define DMA_CH8_AL1_CTRL_CH8_AL1_CTRL_Pos (0UL) /*!< CH8_AL1_CTRL (Bit 0) */ +#define DMA_CH8_AL1_CTRL_CH8_AL1_CTRL_Msk (0xffffffffUL) /*!< CH8_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH8_AL1_READ_ADDR =================================================== */ +#define DMA_CH8_AL1_READ_ADDR_CH8_AL1_READ_ADDR_Pos (0UL) /*!< CH8_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH8_AL1_READ_ADDR_CH8_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH8_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH8_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH8_AL1_WRITE_ADDR_CH8_AL1_WRITE_ADDR_Pos (0UL) /*!< CH8_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH8_AL1_WRITE_ADDR_CH8_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH8_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH8_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_CH8_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH8_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_CH8_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH8_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH8_AL2_CTRL ====================================================== */ +#define DMA_CH8_AL2_CTRL_CH8_AL2_CTRL_Pos (0UL) /*!< CH8_AL2_CTRL (Bit 0) */ +#define DMA_CH8_AL2_CTRL_CH8_AL2_CTRL_Msk (0xffffffffUL) /*!< CH8_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH8_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH8_AL2_TRANS_COUNT_CH8_AL2_TRANS_COUNT_Pos (0UL) /*!< CH8_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH8_AL2_TRANS_COUNT_CH8_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH8_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH8_AL2_READ_ADDR =================================================== */ +#define DMA_CH8_AL2_READ_ADDR_CH8_AL2_READ_ADDR_Pos (0UL) /*!< CH8_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH8_AL2_READ_ADDR_CH8_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH8_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH8_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_CH8_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH8_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_CH8_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH8_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH8_AL3_CTRL ====================================================== */ +#define DMA_CH8_AL3_CTRL_CH8_AL3_CTRL_Pos (0UL) /*!< CH8_AL3_CTRL (Bit 0) */ +#define DMA_CH8_AL3_CTRL_CH8_AL3_CTRL_Msk (0xffffffffUL) /*!< CH8_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH8_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH8_AL3_WRITE_ADDR_CH8_AL3_WRITE_ADDR_Pos (0UL) /*!< CH8_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH8_AL3_WRITE_ADDR_CH8_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH8_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH8_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH8_AL3_TRANS_COUNT_CH8_AL3_TRANS_COUNT_Pos (0UL) /*!< CH8_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH8_AL3_TRANS_COUNT_CH8_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH8_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH8_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH8_AL3_READ_ADDR_TRIG_CH8_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH8_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH8_AL3_READ_ADDR_TRIG_CH8_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH8_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH9_READ_ADDR ===================================================== */ +#define DMA_CH9_READ_ADDR_CH9_READ_ADDR_Pos (0UL) /*!< CH9_READ_ADDR (Bit 0) */ +#define DMA_CH9_READ_ADDR_CH9_READ_ADDR_Msk (0xffffffffUL) /*!< CH9_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH9_WRITE_ADDR ===================================================== */ +#define DMA_CH9_WRITE_ADDR_CH9_WRITE_ADDR_Pos (0UL) /*!< CH9_WRITE_ADDR (Bit 0) */ +#define DMA_CH9_WRITE_ADDR_CH9_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH9_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH9_TRANS_COUNT ==================================================== */ +#define DMA_CH9_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH9_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH9_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH9_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== CH9_CTRL_TRIG ===================================================== */ +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH9_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH9_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH9_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH9_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH9_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH9_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH9_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH9_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH9_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH9_AL1_CTRL ====================================================== */ +#define DMA_CH9_AL1_CTRL_CH9_AL1_CTRL_Pos (0UL) /*!< CH9_AL1_CTRL (Bit 0) */ +#define DMA_CH9_AL1_CTRL_CH9_AL1_CTRL_Msk (0xffffffffUL) /*!< CH9_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH9_AL1_READ_ADDR =================================================== */ +#define DMA_CH9_AL1_READ_ADDR_CH9_AL1_READ_ADDR_Pos (0UL) /*!< CH9_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH9_AL1_READ_ADDR_CH9_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH9_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH9_AL1_WRITE_ADDR =================================================== */ +#define DMA_CH9_AL1_WRITE_ADDR_CH9_AL1_WRITE_ADDR_Pos (0UL) /*!< CH9_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH9_AL1_WRITE_ADDR_CH9_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH9_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH9_AL1_TRANS_COUNT_TRIG ================================================ */ +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_CH9_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH9_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_CH9_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH9_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH9_AL2_CTRL ====================================================== */ +#define DMA_CH9_AL2_CTRL_CH9_AL2_CTRL_Pos (0UL) /*!< CH9_AL2_CTRL (Bit 0) */ +#define DMA_CH9_AL2_CTRL_CH9_AL2_CTRL_Msk (0xffffffffUL) /*!< CH9_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH9_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH9_AL2_TRANS_COUNT_CH9_AL2_TRANS_COUNT_Pos (0UL) /*!< CH9_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH9_AL2_TRANS_COUNT_CH9_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH9_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH9_AL2_READ_ADDR =================================================== */ +#define DMA_CH9_AL2_READ_ADDR_CH9_AL2_READ_ADDR_Pos (0UL) /*!< CH9_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH9_AL2_READ_ADDR_CH9_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH9_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH9_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_CH9_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH9_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_CH9_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH9_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH9_AL3_CTRL ====================================================== */ +#define DMA_CH9_AL3_CTRL_CH9_AL3_CTRL_Pos (0UL) /*!< CH9_AL3_CTRL (Bit 0) */ +#define DMA_CH9_AL3_CTRL_CH9_AL3_CTRL_Msk (0xffffffffUL) /*!< CH9_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH9_AL3_WRITE_ADDR =================================================== */ +#define DMA_CH9_AL3_WRITE_ADDR_CH9_AL3_WRITE_ADDR_Pos (0UL) /*!< CH9_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH9_AL3_WRITE_ADDR_CH9_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH9_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH9_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH9_AL3_TRANS_COUNT_CH9_AL3_TRANS_COUNT_Pos (0UL) /*!< CH9_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH9_AL3_TRANS_COUNT_CH9_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH9_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH9_AL3_READ_ADDR_TRIG ================================================= */ +#define DMA_CH9_AL3_READ_ADDR_TRIG_CH9_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH9_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH9_AL3_READ_ADDR_TRIG_CH9_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH9_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH10_READ_ADDR ===================================================== */ +#define DMA_CH10_READ_ADDR_CH10_READ_ADDR_Pos (0UL) /*!< CH10_READ_ADDR (Bit 0) */ +#define DMA_CH10_READ_ADDR_CH10_READ_ADDR_Msk (0xffffffffUL) /*!< CH10_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH10_WRITE_ADDR ==================================================== */ +#define DMA_CH10_WRITE_ADDR_CH10_WRITE_ADDR_Pos (0UL) /*!< CH10_WRITE_ADDR (Bit 0) */ +#define DMA_CH10_WRITE_ADDR_CH10_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH10_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH10_TRANS_COUNT ==================================================== */ +#define DMA_CH10_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH10_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH10_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH10_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== CH10_CTRL_TRIG ===================================================== */ +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH10_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH10_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH10_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH10_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH10_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH10_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH10_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH10_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH10_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH10_AL1_CTRL ===================================================== */ +#define DMA_CH10_AL1_CTRL_CH10_AL1_CTRL_Pos (0UL) /*!< CH10_AL1_CTRL (Bit 0) */ +#define DMA_CH10_AL1_CTRL_CH10_AL1_CTRL_Msk (0xffffffffUL) /*!< CH10_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH10_AL1_READ_ADDR =================================================== */ +#define DMA_CH10_AL1_READ_ADDR_CH10_AL1_READ_ADDR_Pos (0UL) /*!< CH10_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH10_AL1_READ_ADDR_CH10_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH10_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH10_AL1_WRITE_ADDR ================================================== */ +#define DMA_CH10_AL1_WRITE_ADDR_CH10_AL1_WRITE_ADDR_Pos (0UL) /*!< CH10_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH10_AL1_WRITE_ADDR_CH10_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH10_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH10_AL1_TRANS_COUNT_TRIG =============================================== */ +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_CH10_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH10_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_CH10_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH10_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH10_AL2_CTRL ===================================================== */ +#define DMA_CH10_AL2_CTRL_CH10_AL2_CTRL_Pos (0UL) /*!< CH10_AL2_CTRL (Bit 0) */ +#define DMA_CH10_AL2_CTRL_CH10_AL2_CTRL_Msk (0xffffffffUL) /*!< CH10_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH10_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH10_AL2_TRANS_COUNT_CH10_AL2_TRANS_COUNT_Pos (0UL) /*!< CH10_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH10_AL2_TRANS_COUNT_CH10_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH10_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH10_AL2_READ_ADDR =================================================== */ +#define DMA_CH10_AL2_READ_ADDR_CH10_AL2_READ_ADDR_Pos (0UL) /*!< CH10_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH10_AL2_READ_ADDR_CH10_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH10_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH10_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_CH10_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH10_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_CH10_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH10_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH10_AL3_CTRL ===================================================== */ +#define DMA_CH10_AL3_CTRL_CH10_AL3_CTRL_Pos (0UL) /*!< CH10_AL3_CTRL (Bit 0) */ +#define DMA_CH10_AL3_CTRL_CH10_AL3_CTRL_Msk (0xffffffffUL) /*!< CH10_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH10_AL3_WRITE_ADDR ================================================== */ +#define DMA_CH10_AL3_WRITE_ADDR_CH10_AL3_WRITE_ADDR_Pos (0UL) /*!< CH10_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH10_AL3_WRITE_ADDR_CH10_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH10_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH10_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH10_AL3_TRANS_COUNT_CH10_AL3_TRANS_COUNT_Pos (0UL) /*!< CH10_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH10_AL3_TRANS_COUNT_CH10_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH10_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH10_AL3_READ_ADDR_TRIG ================================================ */ +#define DMA_CH10_AL3_READ_ADDR_TRIG_CH10_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH10_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH10_AL3_READ_ADDR_TRIG_CH10_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH10_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH11_READ_ADDR ===================================================== */ +#define DMA_CH11_READ_ADDR_CH11_READ_ADDR_Pos (0UL) /*!< CH11_READ_ADDR (Bit 0) */ +#define DMA_CH11_READ_ADDR_CH11_READ_ADDR_Msk (0xffffffffUL) /*!< CH11_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH11_WRITE_ADDR ==================================================== */ +#define DMA_CH11_WRITE_ADDR_CH11_WRITE_ADDR_Pos (0UL) /*!< CH11_WRITE_ADDR (Bit 0) */ +#define DMA_CH11_WRITE_ADDR_CH11_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH11_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH11_TRANS_COUNT ==================================================== */ +#define DMA_CH11_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH11_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH11_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH11_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== CH11_CTRL_TRIG ===================================================== */ +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH11_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH11_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH11_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH11_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH11_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH11_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH11_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH11_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH11_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH11_AL1_CTRL ===================================================== */ +#define DMA_CH11_AL1_CTRL_CH11_AL1_CTRL_Pos (0UL) /*!< CH11_AL1_CTRL (Bit 0) */ +#define DMA_CH11_AL1_CTRL_CH11_AL1_CTRL_Msk (0xffffffffUL) /*!< CH11_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH11_AL1_READ_ADDR =================================================== */ +#define DMA_CH11_AL1_READ_ADDR_CH11_AL1_READ_ADDR_Pos (0UL) /*!< CH11_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH11_AL1_READ_ADDR_CH11_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH11_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH11_AL1_WRITE_ADDR ================================================== */ +#define DMA_CH11_AL1_WRITE_ADDR_CH11_AL1_WRITE_ADDR_Pos (0UL) /*!< CH11_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH11_AL1_WRITE_ADDR_CH11_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH11_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH11_AL1_TRANS_COUNT_TRIG =============================================== */ +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_CH11_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH11_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_CH11_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH11_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH11_AL2_CTRL ===================================================== */ +#define DMA_CH11_AL2_CTRL_CH11_AL2_CTRL_Pos (0UL) /*!< CH11_AL2_CTRL (Bit 0) */ +#define DMA_CH11_AL2_CTRL_CH11_AL2_CTRL_Msk (0xffffffffUL) /*!< CH11_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH11_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH11_AL2_TRANS_COUNT_CH11_AL2_TRANS_COUNT_Pos (0UL) /*!< CH11_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH11_AL2_TRANS_COUNT_CH11_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH11_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH11_AL2_READ_ADDR =================================================== */ +#define DMA_CH11_AL2_READ_ADDR_CH11_AL2_READ_ADDR_Pos (0UL) /*!< CH11_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH11_AL2_READ_ADDR_CH11_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH11_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH11_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_CH11_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH11_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_CH11_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH11_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH11_AL3_CTRL ===================================================== */ +#define DMA_CH11_AL3_CTRL_CH11_AL3_CTRL_Pos (0UL) /*!< CH11_AL3_CTRL (Bit 0) */ +#define DMA_CH11_AL3_CTRL_CH11_AL3_CTRL_Msk (0xffffffffUL) /*!< CH11_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH11_AL3_WRITE_ADDR ================================================== */ +#define DMA_CH11_AL3_WRITE_ADDR_CH11_AL3_WRITE_ADDR_Pos (0UL) /*!< CH11_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH11_AL3_WRITE_ADDR_CH11_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH11_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH11_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH11_AL3_TRANS_COUNT_CH11_AL3_TRANS_COUNT_Pos (0UL) /*!< CH11_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH11_AL3_TRANS_COUNT_CH11_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH11_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH11_AL3_READ_ADDR_TRIG ================================================ */ +#define DMA_CH11_AL3_READ_ADDR_TRIG_CH11_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH11_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH11_AL3_READ_ADDR_TRIG_CH11_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH11_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH12_READ_ADDR ===================================================== */ +#define DMA_CH12_READ_ADDR_CH12_READ_ADDR_Pos (0UL) /*!< CH12_READ_ADDR (Bit 0) */ +#define DMA_CH12_READ_ADDR_CH12_READ_ADDR_Msk (0xffffffffUL) /*!< CH12_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH12_WRITE_ADDR ==================================================== */ +#define DMA_CH12_WRITE_ADDR_CH12_WRITE_ADDR_Pos (0UL) /*!< CH12_WRITE_ADDR (Bit 0) */ +#define DMA_CH12_WRITE_ADDR_CH12_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH12_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH12_TRANS_COUNT ==================================================== */ +#define DMA_CH12_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH12_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH12_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH12_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== CH12_CTRL_TRIG ===================================================== */ +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH12_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH12_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH12_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH12_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH12_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH12_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH12_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH12_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH12_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH12_AL1_CTRL ===================================================== */ +#define DMA_CH12_AL1_CTRL_CH12_AL1_CTRL_Pos (0UL) /*!< CH12_AL1_CTRL (Bit 0) */ +#define DMA_CH12_AL1_CTRL_CH12_AL1_CTRL_Msk (0xffffffffUL) /*!< CH12_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH12_AL1_READ_ADDR =================================================== */ +#define DMA_CH12_AL1_READ_ADDR_CH12_AL1_READ_ADDR_Pos (0UL) /*!< CH12_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH12_AL1_READ_ADDR_CH12_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH12_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH12_AL1_WRITE_ADDR ================================================== */ +#define DMA_CH12_AL1_WRITE_ADDR_CH12_AL1_WRITE_ADDR_Pos (0UL) /*!< CH12_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH12_AL1_WRITE_ADDR_CH12_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH12_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH12_AL1_TRANS_COUNT_TRIG =============================================== */ +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_CH12_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH12_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_CH12_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH12_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH12_AL2_CTRL ===================================================== */ +#define DMA_CH12_AL2_CTRL_CH12_AL2_CTRL_Pos (0UL) /*!< CH12_AL2_CTRL (Bit 0) */ +#define DMA_CH12_AL2_CTRL_CH12_AL2_CTRL_Msk (0xffffffffUL) /*!< CH12_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH12_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH12_AL2_TRANS_COUNT_CH12_AL2_TRANS_COUNT_Pos (0UL) /*!< CH12_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH12_AL2_TRANS_COUNT_CH12_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH12_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH12_AL2_READ_ADDR =================================================== */ +#define DMA_CH12_AL2_READ_ADDR_CH12_AL2_READ_ADDR_Pos (0UL) /*!< CH12_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH12_AL2_READ_ADDR_CH12_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH12_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH12_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_CH12_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH12_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_CH12_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH12_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH12_AL3_CTRL ===================================================== */ +#define DMA_CH12_AL3_CTRL_CH12_AL3_CTRL_Pos (0UL) /*!< CH12_AL3_CTRL (Bit 0) */ +#define DMA_CH12_AL3_CTRL_CH12_AL3_CTRL_Msk (0xffffffffUL) /*!< CH12_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH12_AL3_WRITE_ADDR ================================================== */ +#define DMA_CH12_AL3_WRITE_ADDR_CH12_AL3_WRITE_ADDR_Pos (0UL) /*!< CH12_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH12_AL3_WRITE_ADDR_CH12_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH12_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH12_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH12_AL3_TRANS_COUNT_CH12_AL3_TRANS_COUNT_Pos (0UL) /*!< CH12_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH12_AL3_TRANS_COUNT_CH12_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH12_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH12_AL3_READ_ADDR_TRIG ================================================ */ +#define DMA_CH12_AL3_READ_ADDR_TRIG_CH12_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH12_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH12_AL3_READ_ADDR_TRIG_CH12_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH12_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH13_READ_ADDR ===================================================== */ +#define DMA_CH13_READ_ADDR_CH13_READ_ADDR_Pos (0UL) /*!< CH13_READ_ADDR (Bit 0) */ +#define DMA_CH13_READ_ADDR_CH13_READ_ADDR_Msk (0xffffffffUL) /*!< CH13_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH13_WRITE_ADDR ==================================================== */ +#define DMA_CH13_WRITE_ADDR_CH13_WRITE_ADDR_Pos (0UL) /*!< CH13_WRITE_ADDR (Bit 0) */ +#define DMA_CH13_WRITE_ADDR_CH13_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH13_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH13_TRANS_COUNT ==================================================== */ +#define DMA_CH13_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH13_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH13_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH13_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== CH13_CTRL_TRIG ===================================================== */ +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH13_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH13_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH13_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH13_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH13_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH13_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH13_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH13_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH13_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH13_AL1_CTRL ===================================================== */ +#define DMA_CH13_AL1_CTRL_CH13_AL1_CTRL_Pos (0UL) /*!< CH13_AL1_CTRL (Bit 0) */ +#define DMA_CH13_AL1_CTRL_CH13_AL1_CTRL_Msk (0xffffffffUL) /*!< CH13_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH13_AL1_READ_ADDR =================================================== */ +#define DMA_CH13_AL1_READ_ADDR_CH13_AL1_READ_ADDR_Pos (0UL) /*!< CH13_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH13_AL1_READ_ADDR_CH13_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH13_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH13_AL1_WRITE_ADDR ================================================== */ +#define DMA_CH13_AL1_WRITE_ADDR_CH13_AL1_WRITE_ADDR_Pos (0UL) /*!< CH13_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH13_AL1_WRITE_ADDR_CH13_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH13_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH13_AL1_TRANS_COUNT_TRIG =============================================== */ +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_CH13_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH13_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_CH13_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH13_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH13_AL2_CTRL ===================================================== */ +#define DMA_CH13_AL2_CTRL_CH13_AL2_CTRL_Pos (0UL) /*!< CH13_AL2_CTRL (Bit 0) */ +#define DMA_CH13_AL2_CTRL_CH13_AL2_CTRL_Msk (0xffffffffUL) /*!< CH13_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH13_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH13_AL2_TRANS_COUNT_CH13_AL2_TRANS_COUNT_Pos (0UL) /*!< CH13_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH13_AL2_TRANS_COUNT_CH13_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH13_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH13_AL2_READ_ADDR =================================================== */ +#define DMA_CH13_AL2_READ_ADDR_CH13_AL2_READ_ADDR_Pos (0UL) /*!< CH13_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH13_AL2_READ_ADDR_CH13_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH13_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH13_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_CH13_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH13_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_CH13_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH13_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH13_AL3_CTRL ===================================================== */ +#define DMA_CH13_AL3_CTRL_CH13_AL3_CTRL_Pos (0UL) /*!< CH13_AL3_CTRL (Bit 0) */ +#define DMA_CH13_AL3_CTRL_CH13_AL3_CTRL_Msk (0xffffffffUL) /*!< CH13_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH13_AL3_WRITE_ADDR ================================================== */ +#define DMA_CH13_AL3_WRITE_ADDR_CH13_AL3_WRITE_ADDR_Pos (0UL) /*!< CH13_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH13_AL3_WRITE_ADDR_CH13_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH13_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH13_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH13_AL3_TRANS_COUNT_CH13_AL3_TRANS_COUNT_Pos (0UL) /*!< CH13_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH13_AL3_TRANS_COUNT_CH13_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH13_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH13_AL3_READ_ADDR_TRIG ================================================ */ +#define DMA_CH13_AL3_READ_ADDR_TRIG_CH13_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH13_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH13_AL3_READ_ADDR_TRIG_CH13_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH13_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH14_READ_ADDR ===================================================== */ +#define DMA_CH14_READ_ADDR_CH14_READ_ADDR_Pos (0UL) /*!< CH14_READ_ADDR (Bit 0) */ +#define DMA_CH14_READ_ADDR_CH14_READ_ADDR_Msk (0xffffffffUL) /*!< CH14_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH14_WRITE_ADDR ==================================================== */ +#define DMA_CH14_WRITE_ADDR_CH14_WRITE_ADDR_Pos (0UL) /*!< CH14_WRITE_ADDR (Bit 0) */ +#define DMA_CH14_WRITE_ADDR_CH14_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH14_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH14_TRANS_COUNT ==================================================== */ +#define DMA_CH14_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH14_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH14_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH14_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== CH14_CTRL_TRIG ===================================================== */ +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH14_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH14_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH14_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH14_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH14_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH14_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH14_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH14_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH14_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH14_AL1_CTRL ===================================================== */ +#define DMA_CH14_AL1_CTRL_CH14_AL1_CTRL_Pos (0UL) /*!< CH14_AL1_CTRL (Bit 0) */ +#define DMA_CH14_AL1_CTRL_CH14_AL1_CTRL_Msk (0xffffffffUL) /*!< CH14_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH14_AL1_READ_ADDR =================================================== */ +#define DMA_CH14_AL1_READ_ADDR_CH14_AL1_READ_ADDR_Pos (0UL) /*!< CH14_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH14_AL1_READ_ADDR_CH14_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH14_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH14_AL1_WRITE_ADDR ================================================== */ +#define DMA_CH14_AL1_WRITE_ADDR_CH14_AL1_WRITE_ADDR_Pos (0UL) /*!< CH14_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH14_AL1_WRITE_ADDR_CH14_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH14_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH14_AL1_TRANS_COUNT_TRIG =============================================== */ +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_CH14_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH14_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_CH14_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH14_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH14_AL2_CTRL ===================================================== */ +#define DMA_CH14_AL2_CTRL_CH14_AL2_CTRL_Pos (0UL) /*!< CH14_AL2_CTRL (Bit 0) */ +#define DMA_CH14_AL2_CTRL_CH14_AL2_CTRL_Msk (0xffffffffUL) /*!< CH14_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH14_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH14_AL2_TRANS_COUNT_CH14_AL2_TRANS_COUNT_Pos (0UL) /*!< CH14_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH14_AL2_TRANS_COUNT_CH14_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH14_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH14_AL2_READ_ADDR =================================================== */ +#define DMA_CH14_AL2_READ_ADDR_CH14_AL2_READ_ADDR_Pos (0UL) /*!< CH14_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH14_AL2_READ_ADDR_CH14_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH14_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH14_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_CH14_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH14_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_CH14_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH14_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH14_AL3_CTRL ===================================================== */ +#define DMA_CH14_AL3_CTRL_CH14_AL3_CTRL_Pos (0UL) /*!< CH14_AL3_CTRL (Bit 0) */ +#define DMA_CH14_AL3_CTRL_CH14_AL3_CTRL_Msk (0xffffffffUL) /*!< CH14_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH14_AL3_WRITE_ADDR ================================================== */ +#define DMA_CH14_AL3_WRITE_ADDR_CH14_AL3_WRITE_ADDR_Pos (0UL) /*!< CH14_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH14_AL3_WRITE_ADDR_CH14_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH14_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH14_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH14_AL3_TRANS_COUNT_CH14_AL3_TRANS_COUNT_Pos (0UL) /*!< CH14_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH14_AL3_TRANS_COUNT_CH14_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH14_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH14_AL3_READ_ADDR_TRIG ================================================ */ +#define DMA_CH14_AL3_READ_ADDR_TRIG_CH14_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH14_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH14_AL3_READ_ADDR_TRIG_CH14_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH14_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH15_READ_ADDR ===================================================== */ +#define DMA_CH15_READ_ADDR_CH15_READ_ADDR_Pos (0UL) /*!< CH15_READ_ADDR (Bit 0) */ +#define DMA_CH15_READ_ADDR_CH15_READ_ADDR_Msk (0xffffffffUL) /*!< CH15_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH15_WRITE_ADDR ==================================================== */ +#define DMA_CH15_WRITE_ADDR_CH15_WRITE_ADDR_Pos (0UL) /*!< CH15_WRITE_ADDR (Bit 0) */ +#define DMA_CH15_WRITE_ADDR_CH15_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH15_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CH15_TRANS_COUNT ==================================================== */ +#define DMA_CH15_TRANS_COUNT_MODE_Pos (28UL) /*!< MODE (Bit 28) */ +#define DMA_CH15_TRANS_COUNT_MODE_Msk (0xf0000000UL) /*!< MODE (Bitfield-Mask: 0x0f) */ +#define DMA_CH15_TRANS_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define DMA_CH15_TRANS_COUNT_COUNT_Msk (0xfffffffUL) /*!< COUNT (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== CH15_CTRL_TRIG ===================================================== */ +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */ +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */ +#define DMA_CH15_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */ +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_BUSY_Pos (26UL) /*!< BUSY (Bit 26) */ +#define DMA_CH15_CTRL_TRIG_BUSY_Msk (0x4000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_Pos (25UL) /*!< SNIFF_EN (Bit 25) */ +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_Msk (0x2000000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_BSWAP_Pos (24UL) /*!< BSWAP (Bit 24) */ +#define DMA_CH15_CTRL_TRIG_BSWAP_Msk (0x1000000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_Pos (23UL) /*!< IRQ_QUIET (Bit 23) */ +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_Msk (0x800000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_Pos (17UL) /*!< TREQ_SEL (Bit 17) */ +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_Msk (0x7e0000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */ +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_Pos (13UL) /*!< CHAIN_TO (Bit 13) */ +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_Msk (0x1e000UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */ +#define DMA_CH15_CTRL_TRIG_RING_SEL_Pos (12UL) /*!< RING_SEL (Bit 12) */ +#define DMA_CH15_CTRL_TRIG_RING_SEL_Msk (0x1000UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_RING_SIZE_Pos (8UL) /*!< RING_SIZE (Bit 8) */ +#define DMA_CH15_CTRL_TRIG_RING_SIZE_Msk (0xf00UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */ +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_Pos (7UL) /*!< INCR_WRITE_REV (Bit 7) */ +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_Msk (0x80UL) /*!< INCR_WRITE_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_Pos (6UL) /*!< INCR_WRITE (Bit 6) */ +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_Msk (0x40UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_Pos (5UL) /*!< INCR_READ_REV (Bit 5) */ +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_Msk (0x20UL) /*!< INCR_READ_REV (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */ +#define DMA_CH15_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */ +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */ +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */ +#define DMA_CH15_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CH15_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== CH15_AL1_CTRL ===================================================== */ +#define DMA_CH15_AL1_CTRL_CH15_AL1_CTRL_Pos (0UL) /*!< CH15_AL1_CTRL (Bit 0) */ +#define DMA_CH15_AL1_CTRL_CH15_AL1_CTRL_Msk (0xffffffffUL) /*!< CH15_AL1_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH15_AL1_READ_ADDR =================================================== */ +#define DMA_CH15_AL1_READ_ADDR_CH15_AL1_READ_ADDR_Pos (0UL) /*!< CH15_AL1_READ_ADDR (Bit 0) */ +#define DMA_CH15_AL1_READ_ADDR_CH15_AL1_READ_ADDR_Msk (0xffffffffUL) /*!< CH15_AL1_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH15_AL1_WRITE_ADDR ================================================== */ +#define DMA_CH15_AL1_WRITE_ADDR_CH15_AL1_WRITE_ADDR_Pos (0UL) /*!< CH15_AL1_WRITE_ADDR (Bit 0) */ +#define DMA_CH15_AL1_WRITE_ADDR_CH15_AL1_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH15_AL1_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH15_AL1_TRANS_COUNT_TRIG =============================================== */ +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_CH15_AL1_TRANS_COUNT_TRIG_Pos (0UL) /*!< CH15_AL1_TRANS_COUNT_TRIG (Bit 0) */ +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_CH15_AL1_TRANS_COUNT_TRIG_Msk (0xffffffffUL) /*!< CH15_AL1_TRANS_COUNT_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH15_AL2_CTRL ===================================================== */ +#define DMA_CH15_AL2_CTRL_CH15_AL2_CTRL_Pos (0UL) /*!< CH15_AL2_CTRL (Bit 0) */ +#define DMA_CH15_AL2_CTRL_CH15_AL2_CTRL_Msk (0xffffffffUL) /*!< CH15_AL2_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH15_AL2_TRANS_COUNT ================================================== */ +#define DMA_CH15_AL2_TRANS_COUNT_CH15_AL2_TRANS_COUNT_Pos (0UL) /*!< CH15_AL2_TRANS_COUNT (Bit 0) */ +#define DMA_CH15_AL2_TRANS_COUNT_CH15_AL2_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH15_AL2_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH15_AL2_READ_ADDR =================================================== */ +#define DMA_CH15_AL2_READ_ADDR_CH15_AL2_READ_ADDR_Pos (0UL) /*!< CH15_AL2_READ_ADDR (Bit 0) */ +#define DMA_CH15_AL2_READ_ADDR_CH15_AL2_READ_ADDR_Msk (0xffffffffUL) /*!< CH15_AL2_READ_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CH15_AL2_WRITE_ADDR_TRIG ================================================ */ +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_CH15_AL2_WRITE_ADDR_TRIG_Pos (0UL) /*!< CH15_AL2_WRITE_ADDR_TRIG (Bit 0) */ +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_CH15_AL2_WRITE_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH15_AL2_WRITE_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CH15_AL3_CTRL ===================================================== */ +#define DMA_CH15_AL3_CTRL_CH15_AL3_CTRL_Pos (0UL) /*!< CH15_AL3_CTRL (Bit 0) */ +#define DMA_CH15_AL3_CTRL_CH15_AL3_CTRL_Msk (0xffffffffUL) /*!< CH15_AL3_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CH15_AL3_WRITE_ADDR ================================================== */ +#define DMA_CH15_AL3_WRITE_ADDR_CH15_AL3_WRITE_ADDR_Pos (0UL) /*!< CH15_AL3_WRITE_ADDR (Bit 0) */ +#define DMA_CH15_AL3_WRITE_ADDR_CH15_AL3_WRITE_ADDR_Msk (0xffffffffUL) /*!< CH15_AL3_WRITE_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CH15_AL3_TRANS_COUNT ================================================== */ +#define DMA_CH15_AL3_TRANS_COUNT_CH15_AL3_TRANS_COUNT_Pos (0UL) /*!< CH15_AL3_TRANS_COUNT (Bit 0) */ +#define DMA_CH15_AL3_TRANS_COUNT_CH15_AL3_TRANS_COUNT_Msk (0xffffffffUL) /*!< CH15_AL3_TRANS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CH15_AL3_READ_ADDR_TRIG ================================================ */ +#define DMA_CH15_AL3_READ_ADDR_TRIG_CH15_AL3_READ_ADDR_TRIG_Pos (0UL) /*!< CH15_AL3_READ_ADDR_TRIG (Bit 0) */ +#define DMA_CH15_AL3_READ_ADDR_TRIG_CH15_AL3_READ_ADDR_TRIG_Msk (0xffffffffUL) /*!< CH15_AL3_READ_ADDR_TRIG (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTR ========================================================== */ +#define DMA_INTR_INTR_Pos (0UL) /*!< INTR (Bit 0) */ +#define DMA_INTR_INTR_Msk (0xffffUL) /*!< INTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTE0 ========================================================= */ +#define DMA_INTE0_INTE0_Pos (0UL) /*!< INTE0 (Bit 0) */ +#define DMA_INTE0_INTE0_Msk (0xffffUL) /*!< INTE0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTF0 ========================================================= */ +#define DMA_INTF0_INTF0_Pos (0UL) /*!< INTF0 (Bit 0) */ +#define DMA_INTF0_INTF0_Msk (0xffffUL) /*!< INTF0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTS0 ========================================================= */ +#define DMA_INTS0_INTS0_Pos (0UL) /*!< INTS0 (Bit 0) */ +#define DMA_INTS0_INTS0_Msk (0xffffUL) /*!< INTS0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTR1 ========================================================= */ +#define DMA_INTR1_INTR1_Pos (0UL) /*!< INTR1 (Bit 0) */ +#define DMA_INTR1_INTR1_Msk (0xffffUL) /*!< INTR1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTE1 ========================================================= */ +#define DMA_INTE1_INTE1_Pos (0UL) /*!< INTE1 (Bit 0) */ +#define DMA_INTE1_INTE1_Msk (0xffffUL) /*!< INTE1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTF1 ========================================================= */ +#define DMA_INTF1_INTF1_Pos (0UL) /*!< INTF1 (Bit 0) */ +#define DMA_INTF1_INTF1_Msk (0xffffUL) /*!< INTF1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTS1 ========================================================= */ +#define DMA_INTS1_INTS1_Pos (0UL) /*!< INTS1 (Bit 0) */ +#define DMA_INTS1_INTS1_Msk (0xffffUL) /*!< INTS1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTR2 ========================================================= */ +#define DMA_INTR2_INTR2_Pos (0UL) /*!< INTR2 (Bit 0) */ +#define DMA_INTR2_INTR2_Msk (0xffffUL) /*!< INTR2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTE2 ========================================================= */ +#define DMA_INTE2_INTE2_Pos (0UL) /*!< INTE2 (Bit 0) */ +#define DMA_INTE2_INTE2_Msk (0xffffUL) /*!< INTE2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTF2 ========================================================= */ +#define DMA_INTF2_INTF2_Pos (0UL) /*!< INTF2 (Bit 0) */ +#define DMA_INTF2_INTF2_Msk (0xffffUL) /*!< INTF2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTS2 ========================================================= */ +#define DMA_INTS2_INTS2_Pos (0UL) /*!< INTS2 (Bit 0) */ +#define DMA_INTS2_INTS2_Msk (0xffffUL) /*!< INTS2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTR3 ========================================================= */ +#define DMA_INTR3_INTR3_Pos (0UL) /*!< INTR3 (Bit 0) */ +#define DMA_INTR3_INTR3_Msk (0xffffUL) /*!< INTR3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTE3 ========================================================= */ +#define DMA_INTE3_INTE3_Pos (0UL) /*!< INTE3 (Bit 0) */ +#define DMA_INTE3_INTE3_Msk (0xffffUL) /*!< INTE3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTF3 ========================================================= */ +#define DMA_INTF3_INTF3_Pos (0UL) /*!< INTF3 (Bit 0) */ +#define DMA_INTF3_INTF3_Msk (0xffffUL) /*!< INTF3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= INTS3 ========================================================= */ +#define DMA_INTS3_INTS3_Pos (0UL) /*!< INTS3 (Bit 0) */ +#define DMA_INTS3_INTS3_Msk (0xffffUL) /*!< INTS3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== TIMER0 ========================================================= */ +#define DMA_TIMER0_X_Pos (16UL) /*!< X (Bit 16) */ +#define DMA_TIMER0_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ +#define DMA_TIMER0_Y_Pos (0UL) /*!< Y (Bit 0) */ +#define DMA_TIMER0_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ +/* ======================================================== TIMER1 ========================================================= */ +#define DMA_TIMER1_X_Pos (16UL) /*!< X (Bit 16) */ +#define DMA_TIMER1_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ +#define DMA_TIMER1_Y_Pos (0UL) /*!< Y (Bit 0) */ +#define DMA_TIMER1_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ +/* ======================================================== TIMER2 ========================================================= */ +#define DMA_TIMER2_X_Pos (16UL) /*!< X (Bit 16) */ +#define DMA_TIMER2_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ +#define DMA_TIMER2_Y_Pos (0UL) /*!< Y (Bit 0) */ +#define DMA_TIMER2_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ +/* ======================================================== TIMER3 ========================================================= */ +#define DMA_TIMER3_X_Pos (16UL) /*!< X (Bit 16) */ +#define DMA_TIMER3_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ +#define DMA_TIMER3_Y_Pos (0UL) /*!< Y (Bit 0) */ +#define DMA_TIMER3_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ +/* ================================================== MULTI_CHAN_TRIGGER =================================================== */ +#define DMA_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Pos (0UL) /*!< MULTI_CHAN_TRIGGER (Bit 0) */ +#define DMA_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Msk (0xffffUL) /*!< MULTI_CHAN_TRIGGER (Bitfield-Mask: 0xffff) */ +/* ====================================================== SNIFF_CTRL ======================================================= */ +#define DMA_SNIFF_CTRL_OUT_INV_Pos (11UL) /*!< OUT_INV (Bit 11) */ +#define DMA_SNIFF_CTRL_OUT_INV_Msk (0x800UL) /*!< OUT_INV (Bitfield-Mask: 0x01) */ +#define DMA_SNIFF_CTRL_OUT_REV_Pos (10UL) /*!< OUT_REV (Bit 10) */ +#define DMA_SNIFF_CTRL_OUT_REV_Msk (0x400UL) /*!< OUT_REV (Bitfield-Mask: 0x01) */ +#define DMA_SNIFF_CTRL_BSWAP_Pos (9UL) /*!< BSWAP (Bit 9) */ +#define DMA_SNIFF_CTRL_BSWAP_Msk (0x200UL) /*!< BSWAP (Bitfield-Mask: 0x01) */ +#define DMA_SNIFF_CTRL_CALC_Pos (5UL) /*!< CALC (Bit 5) */ +#define DMA_SNIFF_CTRL_CALC_Msk (0x1e0UL) /*!< CALC (Bitfield-Mask: 0x0f) */ +#define DMA_SNIFF_CTRL_DMACH_Pos (1UL) /*!< DMACH (Bit 1) */ +#define DMA_SNIFF_CTRL_DMACH_Msk (0x1eUL) /*!< DMACH (Bitfield-Mask: 0x0f) */ +#define DMA_SNIFF_CTRL_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_SNIFF_CTRL_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ====================================================== SNIFF_DATA ======================================================= */ +#define DMA_SNIFF_DATA_SNIFF_DATA_Pos (0UL) /*!< SNIFF_DATA (Bit 0) */ +#define DMA_SNIFF_DATA_SNIFF_DATA_Msk (0xffffffffUL) /*!< SNIFF_DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FIFO_LEVELS ====================================================== */ +#define DMA_FIFO_LEVELS_RAF_LVL_Pos (16UL) /*!< RAF_LVL (Bit 16) */ +#define DMA_FIFO_LEVELS_RAF_LVL_Msk (0xff0000UL) /*!< RAF_LVL (Bitfield-Mask: 0xff) */ +#define DMA_FIFO_LEVELS_WAF_LVL_Pos (8UL) /*!< WAF_LVL (Bit 8) */ +#define DMA_FIFO_LEVELS_WAF_LVL_Msk (0xff00UL) /*!< WAF_LVL (Bitfield-Mask: 0xff) */ +#define DMA_FIFO_LEVELS_TDF_LVL_Pos (0UL) /*!< TDF_LVL (Bit 0) */ +#define DMA_FIFO_LEVELS_TDF_LVL_Msk (0xffUL) /*!< TDF_LVL (Bitfield-Mask: 0xff) */ +/* ====================================================== CHAN_ABORT ======================================================= */ +#define DMA_CHAN_ABORT_CHAN_ABORT_Pos (0UL) /*!< CHAN_ABORT (Bit 0) */ +#define DMA_CHAN_ABORT_CHAN_ABORT_Msk (0xffffUL) /*!< CHAN_ABORT (Bitfield-Mask: 0xffff) */ +/* ====================================================== N_CHANNELS ======================================================= */ +#define DMA_N_CHANNELS_N_CHANNELS_Pos (0UL) /*!< N_CHANNELS (Bit 0) */ +#define DMA_N_CHANNELS_N_CHANNELS_Msk (0x1fUL) /*!< N_CHANNELS (Bitfield-Mask: 0x1f) */ +/* ====================================================== SECCFG_CH0 ======================================================= */ +#define DMA_SECCFG_CH0_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH0_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH0_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH0_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH0_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH0_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH1 ======================================================= */ +#define DMA_SECCFG_CH1_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH1_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH1_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH1_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH1_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH1_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH2 ======================================================= */ +#define DMA_SECCFG_CH2_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH2_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH2_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH2_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH2_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH2_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH3 ======================================================= */ +#define DMA_SECCFG_CH3_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH3_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH3_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH3_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH3_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH3_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH4 ======================================================= */ +#define DMA_SECCFG_CH4_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH4_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH4_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH4_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH4_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH4_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH5 ======================================================= */ +#define DMA_SECCFG_CH5_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH5_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH5_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH5_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH5_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH5_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH6 ======================================================= */ +#define DMA_SECCFG_CH6_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH6_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH6_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH6_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH6_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH6_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH7 ======================================================= */ +#define DMA_SECCFG_CH7_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH7_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH7_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH7_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH7_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH7_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH8 ======================================================= */ +#define DMA_SECCFG_CH8_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH8_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH8_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH8_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH8_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH8_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH9 ======================================================= */ +#define DMA_SECCFG_CH9_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH9_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH9_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH9_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH9_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH9_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH10 ====================================================== */ +#define DMA_SECCFG_CH10_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH10_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH10_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH10_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH10_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH10_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH11 ====================================================== */ +#define DMA_SECCFG_CH11_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH11_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH11_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH11_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH11_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH11_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH12 ====================================================== */ +#define DMA_SECCFG_CH12_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH12_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH12_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH12_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH12_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH12_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH13 ====================================================== */ +#define DMA_SECCFG_CH13_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH13_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH13_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH13_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH13_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH13_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH14 ====================================================== */ +#define DMA_SECCFG_CH14_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH14_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH14_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH14_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH14_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH14_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_CH15 ====================================================== */ +#define DMA_SECCFG_CH15_LOCK_Pos (2UL) /*!< LOCK (Bit 2) */ +#define DMA_SECCFG_CH15_LOCK_Msk (0x4UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH15_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_CH15_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_CH15_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_CH15_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_IRQ0 ====================================================== */ +#define DMA_SECCFG_IRQ0_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_IRQ0_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_IRQ0_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_IRQ0_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_IRQ1 ====================================================== */ +#define DMA_SECCFG_IRQ1_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_IRQ1_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_IRQ1_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_IRQ1_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_IRQ2 ====================================================== */ +#define DMA_SECCFG_IRQ2_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_IRQ2_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_IRQ2_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_IRQ2_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_IRQ3 ====================================================== */ +#define DMA_SECCFG_IRQ3_S_Pos (1UL) /*!< S (Bit 1) */ +#define DMA_SECCFG_IRQ3_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_IRQ3_P_Pos (0UL) /*!< P (Bit 0) */ +#define DMA_SECCFG_IRQ3_P_Msk (0x1UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ====================================================== SECCFG_MISC ====================================================== */ +#define DMA_SECCFG_MISC_TIMER3_S_Pos (9UL) /*!< TIMER3_S (Bit 9) */ +#define DMA_SECCFG_MISC_TIMER3_S_Msk (0x200UL) /*!< TIMER3_S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_MISC_TIMER3_P_Pos (8UL) /*!< TIMER3_P (Bit 8) */ +#define DMA_SECCFG_MISC_TIMER3_P_Msk (0x100UL) /*!< TIMER3_P (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_MISC_TIMER2_S_Pos (7UL) /*!< TIMER2_S (Bit 7) */ +#define DMA_SECCFG_MISC_TIMER2_S_Msk (0x80UL) /*!< TIMER2_S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_MISC_TIMER2_P_Pos (6UL) /*!< TIMER2_P (Bit 6) */ +#define DMA_SECCFG_MISC_TIMER2_P_Msk (0x40UL) /*!< TIMER2_P (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_MISC_TIMER1_S_Pos (5UL) /*!< TIMER1_S (Bit 5) */ +#define DMA_SECCFG_MISC_TIMER1_S_Msk (0x20UL) /*!< TIMER1_S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_MISC_TIMER1_P_Pos (4UL) /*!< TIMER1_P (Bit 4) */ +#define DMA_SECCFG_MISC_TIMER1_P_Msk (0x10UL) /*!< TIMER1_P (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_MISC_TIMER0_S_Pos (3UL) /*!< TIMER0_S (Bit 3) */ +#define DMA_SECCFG_MISC_TIMER0_S_Msk (0x8UL) /*!< TIMER0_S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_MISC_TIMER0_P_Pos (2UL) /*!< TIMER0_P (Bit 2) */ +#define DMA_SECCFG_MISC_TIMER0_P_Msk (0x4UL) /*!< TIMER0_P (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_MISC_SNIFF_S_Pos (1UL) /*!< SNIFF_S (Bit 1) */ +#define DMA_SECCFG_MISC_SNIFF_S_Msk (0x2UL) /*!< SNIFF_S (Bitfield-Mask: 0x01) */ +#define DMA_SECCFG_MISC_SNIFF_P_Pos (0UL) /*!< SNIFF_P (Bit 0) */ +#define DMA_SECCFG_MISC_SNIFF_P_Msk (0x1UL) /*!< SNIFF_P (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_CTRL ======================================================== */ +#define DMA_MPU_CTRL_NS_HIDE_ADDR_Pos (3UL) /*!< NS_HIDE_ADDR (Bit 3) */ +#define DMA_MPU_CTRL_NS_HIDE_ADDR_Msk (0x8UL) /*!< NS_HIDE_ADDR (Bitfield-Mask: 0x01) */ +#define DMA_MPU_CTRL_S_Pos (2UL) /*!< S (Bit 2) */ +#define DMA_MPU_CTRL_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_MPU_CTRL_P_Pos (1UL) /*!< P (Bit 1) */ +#define DMA_MPU_CTRL_P_Msk (0x2UL) /*!< P (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_BAR0 ======================================================== */ +#define DMA_MPU_BAR0_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_BAR0_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MPU_LAR0 ======================================================== */ +#define DMA_MPU_LAR0_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_LAR0_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +#define DMA_MPU_LAR0_S_Pos (2UL) /*!< S (Bit 2) */ +#define DMA_MPU_LAR0_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR0_P_Pos (1UL) /*!< P (Bit 1) */ +#define DMA_MPU_LAR0_P_Msk (0x2UL) /*!< P (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_MPU_LAR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_BAR1 ======================================================== */ +#define DMA_MPU_BAR1_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_BAR1_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MPU_LAR1 ======================================================== */ +#define DMA_MPU_LAR1_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_LAR1_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +#define DMA_MPU_LAR1_S_Pos (2UL) /*!< S (Bit 2) */ +#define DMA_MPU_LAR1_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR1_P_Pos (1UL) /*!< P (Bit 1) */ +#define DMA_MPU_LAR1_P_Msk (0x2UL) /*!< P (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR1_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_MPU_LAR1_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_BAR2 ======================================================== */ +#define DMA_MPU_BAR2_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_BAR2_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MPU_LAR2 ======================================================== */ +#define DMA_MPU_LAR2_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_LAR2_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +#define DMA_MPU_LAR2_S_Pos (2UL) /*!< S (Bit 2) */ +#define DMA_MPU_LAR2_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR2_P_Pos (1UL) /*!< P (Bit 1) */ +#define DMA_MPU_LAR2_P_Msk (0x2UL) /*!< P (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR2_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_MPU_LAR2_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_BAR3 ======================================================== */ +#define DMA_MPU_BAR3_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_BAR3_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MPU_LAR3 ======================================================== */ +#define DMA_MPU_LAR3_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_LAR3_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +#define DMA_MPU_LAR3_S_Pos (2UL) /*!< S (Bit 2) */ +#define DMA_MPU_LAR3_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR3_P_Pos (1UL) /*!< P (Bit 1) */ +#define DMA_MPU_LAR3_P_Msk (0x2UL) /*!< P (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR3_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_MPU_LAR3_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_BAR4 ======================================================== */ +#define DMA_MPU_BAR4_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_BAR4_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MPU_LAR4 ======================================================== */ +#define DMA_MPU_LAR4_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_LAR4_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +#define DMA_MPU_LAR4_S_Pos (2UL) /*!< S (Bit 2) */ +#define DMA_MPU_LAR4_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR4_P_Pos (1UL) /*!< P (Bit 1) */ +#define DMA_MPU_LAR4_P_Msk (0x2UL) /*!< P (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR4_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_MPU_LAR4_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_BAR5 ======================================================== */ +#define DMA_MPU_BAR5_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_BAR5_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MPU_LAR5 ======================================================== */ +#define DMA_MPU_LAR5_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_LAR5_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +#define DMA_MPU_LAR5_S_Pos (2UL) /*!< S (Bit 2) */ +#define DMA_MPU_LAR5_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR5_P_Pos (1UL) /*!< P (Bit 1) */ +#define DMA_MPU_LAR5_P_Msk (0x2UL) /*!< P (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR5_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_MPU_LAR5_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_BAR6 ======================================================== */ +#define DMA_MPU_BAR6_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_BAR6_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MPU_LAR6 ======================================================== */ +#define DMA_MPU_LAR6_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_LAR6_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +#define DMA_MPU_LAR6_S_Pos (2UL) /*!< S (Bit 2) */ +#define DMA_MPU_LAR6_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR6_P_Pos (1UL) /*!< P (Bit 1) */ +#define DMA_MPU_LAR6_P_Msk (0x2UL) /*!< P (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR6_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_MPU_LAR6_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= MPU_BAR7 ======================================================== */ +#define DMA_MPU_BAR7_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_BAR7_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MPU_LAR7 ======================================================== */ +#define DMA_MPU_LAR7_ADDR_Pos (5UL) /*!< ADDR (Bit 5) */ +#define DMA_MPU_LAR7_ADDR_Msk (0xffffffe0UL) /*!< ADDR (Bitfield-Mask: 0x7ffffff) */ +#define DMA_MPU_LAR7_S_Pos (2UL) /*!< S (Bit 2) */ +#define DMA_MPU_LAR7_S_Msk (0x4UL) /*!< S (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR7_P_Pos (1UL) /*!< P (Bit 1) */ +#define DMA_MPU_LAR7_P_Msk (0x2UL) /*!< P (Bitfield-Mask: 0x01) */ +#define DMA_MPU_LAR7_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_MPU_LAR7_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ==================================================== CH0_DBG_CTDREQ ===================================================== */ +#define DMA_CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Pos (0UL) /*!< CH0_DBG_CTDREQ (Bit 0) */ +#define DMA_CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Msk (0x3fUL) /*!< CH0_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH0_DBG_TCR ====================================================== */ +#define DMA_CH0_DBG_TCR_CH0_DBG_TCR_Pos (0UL) /*!< CH0_DBG_TCR (Bit 0) */ +#define DMA_CH0_DBG_TCR_CH0_DBG_TCR_Msk (0xffffffffUL) /*!< CH0_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH1_DBG_CTDREQ ===================================================== */ +#define DMA_CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Pos (0UL) /*!< CH1_DBG_CTDREQ (Bit 0) */ +#define DMA_CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Msk (0x3fUL) /*!< CH1_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH1_DBG_TCR ====================================================== */ +#define DMA_CH1_DBG_TCR_CH1_DBG_TCR_Pos (0UL) /*!< CH1_DBG_TCR (Bit 0) */ +#define DMA_CH1_DBG_TCR_CH1_DBG_TCR_Msk (0xffffffffUL) /*!< CH1_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH2_DBG_CTDREQ ===================================================== */ +#define DMA_CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Pos (0UL) /*!< CH2_DBG_CTDREQ (Bit 0) */ +#define DMA_CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Msk (0x3fUL) /*!< CH2_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH2_DBG_TCR ====================================================== */ +#define DMA_CH2_DBG_TCR_CH2_DBG_TCR_Pos (0UL) /*!< CH2_DBG_TCR (Bit 0) */ +#define DMA_CH2_DBG_TCR_CH2_DBG_TCR_Msk (0xffffffffUL) /*!< CH2_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH3_DBG_CTDREQ ===================================================== */ +#define DMA_CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Pos (0UL) /*!< CH3_DBG_CTDREQ (Bit 0) */ +#define DMA_CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Msk (0x3fUL) /*!< CH3_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH3_DBG_TCR ====================================================== */ +#define DMA_CH3_DBG_TCR_CH3_DBG_TCR_Pos (0UL) /*!< CH3_DBG_TCR (Bit 0) */ +#define DMA_CH3_DBG_TCR_CH3_DBG_TCR_Msk (0xffffffffUL) /*!< CH3_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH4_DBG_CTDREQ ===================================================== */ +#define DMA_CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Pos (0UL) /*!< CH4_DBG_CTDREQ (Bit 0) */ +#define DMA_CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Msk (0x3fUL) /*!< CH4_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH4_DBG_TCR ====================================================== */ +#define DMA_CH4_DBG_TCR_CH4_DBG_TCR_Pos (0UL) /*!< CH4_DBG_TCR (Bit 0) */ +#define DMA_CH4_DBG_TCR_CH4_DBG_TCR_Msk (0xffffffffUL) /*!< CH4_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH5_DBG_CTDREQ ===================================================== */ +#define DMA_CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Pos (0UL) /*!< CH5_DBG_CTDREQ (Bit 0) */ +#define DMA_CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Msk (0x3fUL) /*!< CH5_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH5_DBG_TCR ====================================================== */ +#define DMA_CH5_DBG_TCR_CH5_DBG_TCR_Pos (0UL) /*!< CH5_DBG_TCR (Bit 0) */ +#define DMA_CH5_DBG_TCR_CH5_DBG_TCR_Msk (0xffffffffUL) /*!< CH5_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH6_DBG_CTDREQ ===================================================== */ +#define DMA_CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Pos (0UL) /*!< CH6_DBG_CTDREQ (Bit 0) */ +#define DMA_CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Msk (0x3fUL) /*!< CH6_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH6_DBG_TCR ====================================================== */ +#define DMA_CH6_DBG_TCR_CH6_DBG_TCR_Pos (0UL) /*!< CH6_DBG_TCR (Bit 0) */ +#define DMA_CH6_DBG_TCR_CH6_DBG_TCR_Msk (0xffffffffUL) /*!< CH6_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH7_DBG_CTDREQ ===================================================== */ +#define DMA_CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Pos (0UL) /*!< CH7_DBG_CTDREQ (Bit 0) */ +#define DMA_CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Msk (0x3fUL) /*!< CH7_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH7_DBG_TCR ====================================================== */ +#define DMA_CH7_DBG_TCR_CH7_DBG_TCR_Pos (0UL) /*!< CH7_DBG_TCR (Bit 0) */ +#define DMA_CH7_DBG_TCR_CH7_DBG_TCR_Msk (0xffffffffUL) /*!< CH7_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH8_DBG_CTDREQ ===================================================== */ +#define DMA_CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Pos (0UL) /*!< CH8_DBG_CTDREQ (Bit 0) */ +#define DMA_CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Msk (0x3fUL) /*!< CH8_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH8_DBG_TCR ====================================================== */ +#define DMA_CH8_DBG_TCR_CH8_DBG_TCR_Pos (0UL) /*!< CH8_DBG_TCR (Bit 0) */ +#define DMA_CH8_DBG_TCR_CH8_DBG_TCR_Msk (0xffffffffUL) /*!< CH8_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH9_DBG_CTDREQ ===================================================== */ +#define DMA_CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Pos (0UL) /*!< CH9_DBG_CTDREQ (Bit 0) */ +#define DMA_CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Msk (0x3fUL) /*!< CH9_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ====================================================== CH9_DBG_TCR ====================================================== */ +#define DMA_CH9_DBG_TCR_CH9_DBG_TCR_Pos (0UL) /*!< CH9_DBG_TCR (Bit 0) */ +#define DMA_CH9_DBG_TCR_CH9_DBG_TCR_Msk (0xffffffffUL) /*!< CH9_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH10_DBG_CTDREQ ==================================================== */ +#define DMA_CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Pos (0UL) /*!< CH10_DBG_CTDREQ (Bit 0) */ +#define DMA_CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Msk (0x3fUL) /*!< CH10_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ===================================================== CH10_DBG_TCR ====================================================== */ +#define DMA_CH10_DBG_TCR_CH10_DBG_TCR_Pos (0UL) /*!< CH10_DBG_TCR (Bit 0) */ +#define DMA_CH10_DBG_TCR_CH10_DBG_TCR_Msk (0xffffffffUL) /*!< CH10_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH11_DBG_CTDREQ ==================================================== */ +#define DMA_CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Pos (0UL) /*!< CH11_DBG_CTDREQ (Bit 0) */ +#define DMA_CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Msk (0x3fUL) /*!< CH11_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ===================================================== CH11_DBG_TCR ====================================================== */ +#define DMA_CH11_DBG_TCR_CH11_DBG_TCR_Pos (0UL) /*!< CH11_DBG_TCR (Bit 0) */ +#define DMA_CH11_DBG_TCR_CH11_DBG_TCR_Msk (0xffffffffUL) /*!< CH11_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH12_DBG_CTDREQ ==================================================== */ +#define DMA_CH12_DBG_CTDREQ_CH12_DBG_CTDREQ_Pos (0UL) /*!< CH12_DBG_CTDREQ (Bit 0) */ +#define DMA_CH12_DBG_CTDREQ_CH12_DBG_CTDREQ_Msk (0x3fUL) /*!< CH12_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ===================================================== CH12_DBG_TCR ====================================================== */ +#define DMA_CH12_DBG_TCR_CH12_DBG_TCR_Pos (0UL) /*!< CH12_DBG_TCR (Bit 0) */ +#define DMA_CH12_DBG_TCR_CH12_DBG_TCR_Msk (0xffffffffUL) /*!< CH12_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH13_DBG_CTDREQ ==================================================== */ +#define DMA_CH13_DBG_CTDREQ_CH13_DBG_CTDREQ_Pos (0UL) /*!< CH13_DBG_CTDREQ (Bit 0) */ +#define DMA_CH13_DBG_CTDREQ_CH13_DBG_CTDREQ_Msk (0x3fUL) /*!< CH13_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ===================================================== CH13_DBG_TCR ====================================================== */ +#define DMA_CH13_DBG_TCR_CH13_DBG_TCR_Pos (0UL) /*!< CH13_DBG_TCR (Bit 0) */ +#define DMA_CH13_DBG_TCR_CH13_DBG_TCR_Msk (0xffffffffUL) /*!< CH13_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH14_DBG_CTDREQ ==================================================== */ +#define DMA_CH14_DBG_CTDREQ_CH14_DBG_CTDREQ_Pos (0UL) /*!< CH14_DBG_CTDREQ (Bit 0) */ +#define DMA_CH14_DBG_CTDREQ_CH14_DBG_CTDREQ_Msk (0x3fUL) /*!< CH14_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ===================================================== CH14_DBG_TCR ====================================================== */ +#define DMA_CH14_DBG_TCR_CH14_DBG_TCR_Pos (0UL) /*!< CH14_DBG_TCR (Bit 0) */ +#define DMA_CH14_DBG_TCR_CH14_DBG_TCR_Msk (0xffffffffUL) /*!< CH14_DBG_TCR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CH15_DBG_CTDREQ ==================================================== */ +#define DMA_CH15_DBG_CTDREQ_CH15_DBG_CTDREQ_Pos (0UL) /*!< CH15_DBG_CTDREQ (Bit 0) */ +#define DMA_CH15_DBG_CTDREQ_CH15_DBG_CTDREQ_Msk (0x3fUL) /*!< CH15_DBG_CTDREQ (Bitfield-Mask: 0x3f) */ +/* ===================================================== CH15_DBG_TCR ====================================================== */ +#define DMA_CH15_DBG_TCR_CH15_DBG_TCR_Pos (0UL) /*!< CH15_DBG_TCR (Bit 0) */ +#define DMA_CH15_DBG_TCR_CH15_DBG_TCR_Msk (0xffffffffUL) /*!< CH15_DBG_TCR (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TIMEHW ========================================================= */ +#define TIMER0_TIMEHW_TIMEHW_Pos (0UL) /*!< TIMEHW (Bit 0) */ +#define TIMER0_TIMEHW_TIMEHW_Msk (0xffffffffUL) /*!< TIMEHW (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TIMELW ========================================================= */ +#define TIMER0_TIMELW_TIMELW_Pos (0UL) /*!< TIMELW (Bit 0) */ +#define TIMER0_TIMELW_TIMELW_Msk (0xffffffffUL) /*!< TIMELW (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TIMEHR ========================================================= */ +#define TIMER0_TIMEHR_TIMEHR_Pos (0UL) /*!< TIMEHR (Bit 0) */ +#define TIMER0_TIMEHR_TIMEHR_Msk (0xffffffffUL) /*!< TIMEHR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TIMELR ========================================================= */ +#define TIMER0_TIMELR_TIMELR_Pos (0UL) /*!< TIMELR (Bit 0) */ +#define TIMER0_TIMELR_TIMELR_Msk (0xffffffffUL) /*!< TIMELR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ALARM0 ========================================================= */ +#define TIMER0_ALARM0_ALARM0_Pos (0UL) /*!< ALARM0 (Bit 0) */ +#define TIMER0_ALARM0_ALARM0_Msk (0xffffffffUL) /*!< ALARM0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ALARM1 ========================================================= */ +#define TIMER0_ALARM1_ALARM1_Pos (0UL) /*!< ALARM1 (Bit 0) */ +#define TIMER0_ALARM1_ALARM1_Msk (0xffffffffUL) /*!< ALARM1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ALARM2 ========================================================= */ +#define TIMER0_ALARM2_ALARM2_Pos (0UL) /*!< ALARM2 (Bit 0) */ +#define TIMER0_ALARM2_ALARM2_Msk (0xffffffffUL) /*!< ALARM2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ALARM3 ========================================================= */ +#define TIMER0_ALARM3_ALARM3_Pos (0UL) /*!< ALARM3 (Bit 0) */ +#define TIMER0_ALARM3_ALARM3_Msk (0xffffffffUL) /*!< ALARM3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ARMED ========================================================= */ +#define TIMER0_ARMED_ARMED_Pos (0UL) /*!< ARMED (Bit 0) */ +#define TIMER0_ARMED_ARMED_Msk (0xfUL) /*!< ARMED (Bitfield-Mask: 0x0f) */ +/* ======================================================= TIMERAWH ======================================================== */ +#define TIMER0_TIMERAWH_TIMERAWH_Pos (0UL) /*!< TIMERAWH (Bit 0) */ +#define TIMER0_TIMERAWH_TIMERAWH_Msk (0xffffffffUL) /*!< TIMERAWH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TIMERAWL ======================================================== */ +#define TIMER0_TIMERAWL_TIMERAWL_Pos (0UL) /*!< TIMERAWL (Bit 0) */ +#define TIMER0_TIMERAWL_TIMERAWL_Msk (0xffffffffUL) /*!< TIMERAWL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DBGPAUSE ======================================================== */ +#define TIMER0_DBGPAUSE_DBG1_Pos (2UL) /*!< DBG1 (Bit 2) */ +#define TIMER0_DBGPAUSE_DBG1_Msk (0x4UL) /*!< DBG1 (Bitfield-Mask: 0x01) */ +#define TIMER0_DBGPAUSE_DBG0_Pos (1UL) /*!< DBG0 (Bit 1) */ +#define TIMER0_DBGPAUSE_DBG0_Msk (0x2UL) /*!< DBG0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PAUSE ========================================================= */ +#define TIMER0_PAUSE_PAUSE_Pos (0UL) /*!< PAUSE (Bit 0) */ +#define TIMER0_PAUSE_PAUSE_Msk (0x1UL) /*!< PAUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== LOCKED ========================================================= */ +#define TIMER0_LOCKED_LOCKED_Pos (0UL) /*!< LOCKED (Bit 0) */ +#define TIMER0_LOCKED_LOCKED_Msk (0x1UL) /*!< LOCKED (Bitfield-Mask: 0x01) */ +/* ======================================================== SOURCE ========================================================= */ +#define TIMER0_SOURCE_CLK_SYS_Pos (0UL) /*!< CLK_SYS (Bit 0) */ +#define TIMER0_SOURCE_CLK_SYS_Msk (0x1UL) /*!< CLK_SYS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR ========================================================== */ +#define TIMER0_INTR_ALARM_3_Pos (3UL) /*!< ALARM_3 (Bit 3) */ +#define TIMER0_INTR_ALARM_3_Msk (0x8UL) /*!< ALARM_3 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTR_ALARM_2_Pos (2UL) /*!< ALARM_2 (Bit 2) */ +#define TIMER0_INTR_ALARM_2_Msk (0x4UL) /*!< ALARM_2 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTR_ALARM_1_Pos (1UL) /*!< ALARM_1 (Bit 1) */ +#define TIMER0_INTR_ALARM_1_Msk (0x2UL) /*!< ALARM_1 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTR_ALARM_0_Pos (0UL) /*!< ALARM_0 (Bit 0) */ +#define TIMER0_INTR_ALARM_0_Msk (0x1UL) /*!< ALARM_0 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ +#define TIMER0_INTE_ALARM_3_Pos (3UL) /*!< ALARM_3 (Bit 3) */ +#define TIMER0_INTE_ALARM_3_Msk (0x8UL) /*!< ALARM_3 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTE_ALARM_2_Pos (2UL) /*!< ALARM_2 (Bit 2) */ +#define TIMER0_INTE_ALARM_2_Msk (0x4UL) /*!< ALARM_2 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTE_ALARM_1_Pos (1UL) /*!< ALARM_1 (Bit 1) */ +#define TIMER0_INTE_ALARM_1_Msk (0x2UL) /*!< ALARM_1 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTE_ALARM_0_Pos (0UL) /*!< ALARM_0 (Bit 0) */ +#define TIMER0_INTE_ALARM_0_Msk (0x1UL) /*!< ALARM_0 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define TIMER0_INTF_ALARM_3_Pos (3UL) /*!< ALARM_3 (Bit 3) */ +#define TIMER0_INTF_ALARM_3_Msk (0x8UL) /*!< ALARM_3 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_ALARM_2_Pos (2UL) /*!< ALARM_2 (Bit 2) */ +#define TIMER0_INTF_ALARM_2_Msk (0x4UL) /*!< ALARM_2 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_ALARM_1_Pos (1UL) /*!< ALARM_1 (Bit 1) */ +#define TIMER0_INTF_ALARM_1_Msk (0x2UL) /*!< ALARM_1 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_ALARM_0_Pos (0UL) /*!< ALARM_0 (Bit 0) */ +#define TIMER0_INTF_ALARM_0_Msk (0x1UL) /*!< ALARM_0 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ +#define TIMER0_INTS_ALARM_3_Pos (3UL) /*!< ALARM_3 (Bit 3) */ +#define TIMER0_INTS_ALARM_3_Msk (0x8UL) /*!< ALARM_3 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTS_ALARM_2_Pos (2UL) /*!< ALARM_2 (Bit 2) */ +#define TIMER0_INTS_ALARM_2_Msk (0x4UL) /*!< ALARM_2 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTS_ALARM_1_Pos (1UL) /*!< ALARM_1 (Bit 1) */ +#define TIMER0_INTS_ALARM_1_Msk (0x2UL) /*!< ALARM_1 (Bitfield-Mask: 0x01) */ +#define TIMER0_INTS_ALARM_0_Pos (0UL) /*!< ALARM_0 (Bit 0) */ +#define TIMER0_INTS_ALARM_0_Msk (0x1UL) /*!< ALARM_0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CH0_CSR ======================================================== */ +#define PWM_CH0_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH0_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH0_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH0_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH0_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH0_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH0_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH0_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH0_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH0_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH0_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH0_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH0_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH0_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH0_DIV ======================================================== */ +#define PWM_CH0_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH0_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH0_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH0_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH0_CTR ======================================================== */ +#define PWM_CH0_CTR_CH0_CTR_Pos (0UL) /*!< CH0_CTR (Bit 0) */ +#define PWM_CH0_CTR_CH0_CTR_Msk (0xffffUL) /*!< CH0_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH0_CC ========================================================= */ +#define PWM_CH0_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH0_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH0_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH0_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH0_TOP ======================================================== */ +#define PWM_CH0_TOP_CH0_TOP_Pos (0UL) /*!< CH0_TOP (Bit 0) */ +#define PWM_CH0_TOP_CH0_TOP_Msk (0xffffUL) /*!< CH0_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH1_CSR ======================================================== */ +#define PWM_CH1_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH1_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH1_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH1_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH1_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH1_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH1_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH1_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH1_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH1_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH1_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH1_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH1_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH1_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH1_DIV ======================================================== */ +#define PWM_CH1_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH1_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH1_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH1_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH1_CTR ======================================================== */ +#define PWM_CH1_CTR_CH1_CTR_Pos (0UL) /*!< CH1_CTR (Bit 0) */ +#define PWM_CH1_CTR_CH1_CTR_Msk (0xffffUL) /*!< CH1_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH1_CC ========================================================= */ +#define PWM_CH1_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH1_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH1_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH1_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH1_TOP ======================================================== */ +#define PWM_CH1_TOP_CH1_TOP_Pos (0UL) /*!< CH1_TOP (Bit 0) */ +#define PWM_CH1_TOP_CH1_TOP_Msk (0xffffUL) /*!< CH1_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH2_CSR ======================================================== */ +#define PWM_CH2_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH2_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH2_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH2_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH2_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH2_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH2_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH2_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH2_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH2_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH2_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH2_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH2_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH2_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH2_DIV ======================================================== */ +#define PWM_CH2_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH2_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH2_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH2_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH2_CTR ======================================================== */ +#define PWM_CH2_CTR_CH2_CTR_Pos (0UL) /*!< CH2_CTR (Bit 0) */ +#define PWM_CH2_CTR_CH2_CTR_Msk (0xffffUL) /*!< CH2_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH2_CC ========================================================= */ +#define PWM_CH2_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH2_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH2_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH2_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH2_TOP ======================================================== */ +#define PWM_CH2_TOP_CH2_TOP_Pos (0UL) /*!< CH2_TOP (Bit 0) */ +#define PWM_CH2_TOP_CH2_TOP_Msk (0xffffUL) /*!< CH2_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH3_CSR ======================================================== */ +#define PWM_CH3_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH3_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH3_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH3_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH3_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH3_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH3_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH3_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH3_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH3_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH3_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH3_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH3_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH3_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH3_DIV ======================================================== */ +#define PWM_CH3_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH3_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH3_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH3_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH3_CTR ======================================================== */ +#define PWM_CH3_CTR_CH3_CTR_Pos (0UL) /*!< CH3_CTR (Bit 0) */ +#define PWM_CH3_CTR_CH3_CTR_Msk (0xffffUL) /*!< CH3_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH3_CC ========================================================= */ +#define PWM_CH3_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH3_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH3_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH3_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH3_TOP ======================================================== */ +#define PWM_CH3_TOP_CH3_TOP_Pos (0UL) /*!< CH3_TOP (Bit 0) */ +#define PWM_CH3_TOP_CH3_TOP_Msk (0xffffUL) /*!< CH3_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH4_CSR ======================================================== */ +#define PWM_CH4_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH4_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH4_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH4_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH4_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH4_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH4_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH4_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH4_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH4_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH4_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH4_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH4_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH4_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH4_DIV ======================================================== */ +#define PWM_CH4_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH4_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH4_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH4_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH4_CTR ======================================================== */ +#define PWM_CH4_CTR_CH4_CTR_Pos (0UL) /*!< CH4_CTR (Bit 0) */ +#define PWM_CH4_CTR_CH4_CTR_Msk (0xffffUL) /*!< CH4_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH4_CC ========================================================= */ +#define PWM_CH4_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH4_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH4_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH4_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH4_TOP ======================================================== */ +#define PWM_CH4_TOP_CH4_TOP_Pos (0UL) /*!< CH4_TOP (Bit 0) */ +#define PWM_CH4_TOP_CH4_TOP_Msk (0xffffUL) /*!< CH4_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH5_CSR ======================================================== */ +#define PWM_CH5_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH5_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH5_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH5_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH5_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH5_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH5_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH5_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH5_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH5_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH5_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH5_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH5_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH5_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH5_DIV ======================================================== */ +#define PWM_CH5_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH5_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH5_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH5_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH5_CTR ======================================================== */ +#define PWM_CH5_CTR_CH5_CTR_Pos (0UL) /*!< CH5_CTR (Bit 0) */ +#define PWM_CH5_CTR_CH5_CTR_Msk (0xffffUL) /*!< CH5_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH5_CC ========================================================= */ +#define PWM_CH5_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH5_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH5_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH5_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH5_TOP ======================================================== */ +#define PWM_CH5_TOP_CH5_TOP_Pos (0UL) /*!< CH5_TOP (Bit 0) */ +#define PWM_CH5_TOP_CH5_TOP_Msk (0xffffUL) /*!< CH5_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH6_CSR ======================================================== */ +#define PWM_CH6_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH6_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH6_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH6_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH6_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH6_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH6_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH6_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH6_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH6_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH6_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH6_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH6_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH6_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH6_DIV ======================================================== */ +#define PWM_CH6_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH6_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH6_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH6_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH6_CTR ======================================================== */ +#define PWM_CH6_CTR_CH6_CTR_Pos (0UL) /*!< CH6_CTR (Bit 0) */ +#define PWM_CH6_CTR_CH6_CTR_Msk (0xffffUL) /*!< CH6_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH6_CC ========================================================= */ +#define PWM_CH6_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH6_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH6_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH6_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH6_TOP ======================================================== */ +#define PWM_CH6_TOP_CH6_TOP_Pos (0UL) /*!< CH6_TOP (Bit 0) */ +#define PWM_CH6_TOP_CH6_TOP_Msk (0xffffUL) /*!< CH6_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH7_CSR ======================================================== */ +#define PWM_CH7_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH7_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH7_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH7_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH7_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH7_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH7_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH7_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH7_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH7_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH7_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH7_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH7_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH7_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH7_DIV ======================================================== */ +#define PWM_CH7_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH7_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH7_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH7_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH7_CTR ======================================================== */ +#define PWM_CH7_CTR_CH7_CTR_Pos (0UL) /*!< CH7_CTR (Bit 0) */ +#define PWM_CH7_CTR_CH7_CTR_Msk (0xffffUL) /*!< CH7_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH7_CC ========================================================= */ +#define PWM_CH7_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH7_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH7_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH7_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH7_TOP ======================================================== */ +#define PWM_CH7_TOP_CH7_TOP_Pos (0UL) /*!< CH7_TOP (Bit 0) */ +#define PWM_CH7_TOP_CH7_TOP_Msk (0xffffUL) /*!< CH7_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH8_CSR ======================================================== */ +#define PWM_CH8_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH8_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH8_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH8_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH8_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH8_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH8_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH8_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH8_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH8_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH8_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH8_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH8_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH8_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH8_DIV ======================================================== */ +#define PWM_CH8_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH8_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH8_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH8_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH8_CTR ======================================================== */ +#define PWM_CH8_CTR_CH8_CTR_Pos (0UL) /*!< CH8_CTR (Bit 0) */ +#define PWM_CH8_CTR_CH8_CTR_Msk (0xffffUL) /*!< CH8_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH8_CC ========================================================= */ +#define PWM_CH8_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH8_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH8_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH8_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH8_TOP ======================================================== */ +#define PWM_CH8_TOP_CH8_TOP_Pos (0UL) /*!< CH8_TOP (Bit 0) */ +#define PWM_CH8_TOP_CH8_TOP_Msk (0xffffUL) /*!< CH8_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH9_CSR ======================================================== */ +#define PWM_CH9_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH9_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH9_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH9_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH9_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH9_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH9_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH9_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH9_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH9_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH9_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH9_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH9_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH9_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== CH9_DIV ======================================================== */ +#define PWM_CH9_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH9_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH9_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH9_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================== CH9_CTR ======================================================== */ +#define PWM_CH9_CTR_CH9_CTR_Pos (0UL) /*!< CH9_CTR (Bit 0) */ +#define PWM_CH9_CTR_CH9_CTR_Msk (0xffffUL) /*!< CH9_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH9_CC ========================================================= */ +#define PWM_CH9_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH9_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH9_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH9_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH9_TOP ======================================================== */ +#define PWM_CH9_TOP_CH9_TOP_Pos (0UL) /*!< CH9_TOP (Bit 0) */ +#define PWM_CH9_TOP_CH9_TOP_Msk (0xffffUL) /*!< CH9_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH10_CSR ======================================================== */ +#define PWM_CH10_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH10_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH10_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH10_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH10_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH10_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH10_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH10_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH10_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH10_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH10_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH10_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH10_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH10_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CH10_DIV ======================================================== */ +#define PWM_CH10_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH10_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH10_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH10_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================= CH10_CTR ======================================================== */ +#define PWM_CH10_CTR_CH10_CTR_Pos (0UL) /*!< CH10_CTR (Bit 0) */ +#define PWM_CH10_CTR_CH10_CTR_Msk (0xffffUL) /*!< CH10_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH10_CC ======================================================== */ +#define PWM_CH10_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH10_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH10_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH10_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH10_TOP ======================================================== */ +#define PWM_CH10_TOP_CH10_TOP_Pos (0UL) /*!< CH10_TOP (Bit 0) */ +#define PWM_CH10_TOP_CH10_TOP_Msk (0xffffUL) /*!< CH10_TOP (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH11_CSR ======================================================== */ +#define PWM_CH11_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */ +#define PWM_CH11_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */ +#define PWM_CH11_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */ +#define PWM_CH11_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */ +#define PWM_CH11_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */ +#define PWM_CH11_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */ +#define PWM_CH11_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */ +#define PWM_CH11_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH11_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */ +#define PWM_CH11_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */ +#define PWM_CH11_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */ +#define PWM_CH11_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */ +#define PWM_CH11_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define PWM_CH11_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CH11_DIV ======================================================== */ +#define PWM_CH11_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */ +#define PWM_CH11_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */ +#define PWM_CH11_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define PWM_CH11_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */ +/* ======================================================= CH11_CTR ======================================================== */ +#define PWM_CH11_CTR_CH11_CTR_Pos (0UL) /*!< CH11_CTR (Bit 0) */ +#define PWM_CH11_CTR_CH11_CTR_Msk (0xffffUL) /*!< CH11_CTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH11_CC ======================================================== */ +#define PWM_CH11_CC_B_Pos (16UL) /*!< B (Bit 16) */ +#define PWM_CH11_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */ +#define PWM_CH11_CC_A_Pos (0UL) /*!< A (Bit 0) */ +#define PWM_CH11_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH11_TOP ======================================================== */ +#define PWM_CH11_TOP_CH11_TOP_Pos (0UL) /*!< CH11_TOP (Bit 0) */ +#define PWM_CH11_TOP_CH11_TOP_Msk (0xffffUL) /*!< CH11_TOP (Bitfield-Mask: 0xffff) */ +/* ========================================================== EN =========================================================== */ +#define PWM_EN_CH11_Pos (11UL) /*!< CH11 (Bit 11) */ +#define PWM_EN_CH11_Msk (0x800UL) /*!< CH11 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH10_Pos (10UL) /*!< CH10 (Bit 10) */ +#define PWM_EN_CH10_Msk (0x400UL) /*!< CH10 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH9_Pos (9UL) /*!< CH9 (Bit 9) */ +#define PWM_EN_CH9_Msk (0x200UL) /*!< CH9 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH8_Pos (8UL) /*!< CH8 (Bit 8) */ +#define PWM_EN_CH8_Msk (0x100UL) /*!< CH8 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH7_Pos (7UL) /*!< CH7 (Bit 7) */ +#define PWM_EN_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH6_Pos (6UL) /*!< CH6 (Bit 6) */ +#define PWM_EN_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH5_Pos (5UL) /*!< CH5 (Bit 5) */ +#define PWM_EN_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH4_Pos (4UL) /*!< CH4 (Bit 4) */ +#define PWM_EN_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH3_Pos (3UL) /*!< CH3 (Bit 3) */ +#define PWM_EN_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH2_Pos (2UL) /*!< CH2 (Bit 2) */ +#define PWM_EN_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH1_Pos (1UL) /*!< CH1 (Bit 1) */ +#define PWM_EN_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */ +#define PWM_EN_CH0_Pos (0UL) /*!< CH0 (Bit 0) */ +#define PWM_EN_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR ========================================================== */ +#define PWM_INTR_CH11_Pos (11UL) /*!< CH11 (Bit 11) */ +#define PWM_INTR_CH11_Msk (0x800UL) /*!< CH11 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH10_Pos (10UL) /*!< CH10 (Bit 10) */ +#define PWM_INTR_CH10_Msk (0x400UL) /*!< CH10 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH9_Pos (9UL) /*!< CH9 (Bit 9) */ +#define PWM_INTR_CH9_Msk (0x200UL) /*!< CH9 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH8_Pos (8UL) /*!< CH8 (Bit 8) */ +#define PWM_INTR_CH8_Msk (0x100UL) /*!< CH8 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH7_Pos (7UL) /*!< CH7 (Bit 7) */ +#define PWM_INTR_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH6_Pos (6UL) /*!< CH6 (Bit 6) */ +#define PWM_INTR_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH5_Pos (5UL) /*!< CH5 (Bit 5) */ +#define PWM_INTR_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH4_Pos (4UL) /*!< CH4 (Bit 4) */ +#define PWM_INTR_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH3_Pos (3UL) /*!< CH3 (Bit 3) */ +#define PWM_INTR_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH2_Pos (2UL) /*!< CH2 (Bit 2) */ +#define PWM_INTR_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH1_Pos (1UL) /*!< CH1 (Bit 1) */ +#define PWM_INTR_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */ +#define PWM_INTR_CH0_Pos (0UL) /*!< CH0 (Bit 0) */ +#define PWM_INTR_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ0_INTE ======================================================= */ +#define PWM_IRQ0_INTE_CH11_Pos (11UL) /*!< CH11 (Bit 11) */ +#define PWM_IRQ0_INTE_CH11_Msk (0x800UL) /*!< CH11 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH10_Pos (10UL) /*!< CH10 (Bit 10) */ +#define PWM_IRQ0_INTE_CH10_Msk (0x400UL) /*!< CH10 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH9_Pos (9UL) /*!< CH9 (Bit 9) */ +#define PWM_IRQ0_INTE_CH9_Msk (0x200UL) /*!< CH9 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH8_Pos (8UL) /*!< CH8 (Bit 8) */ +#define PWM_IRQ0_INTE_CH8_Msk (0x100UL) /*!< CH8 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH7_Pos (7UL) /*!< CH7 (Bit 7) */ +#define PWM_IRQ0_INTE_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH6_Pos (6UL) /*!< CH6 (Bit 6) */ +#define PWM_IRQ0_INTE_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH5_Pos (5UL) /*!< CH5 (Bit 5) */ +#define PWM_IRQ0_INTE_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH4_Pos (4UL) /*!< CH4 (Bit 4) */ +#define PWM_IRQ0_INTE_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH3_Pos (3UL) /*!< CH3 (Bit 3) */ +#define PWM_IRQ0_INTE_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH2_Pos (2UL) /*!< CH2 (Bit 2) */ +#define PWM_IRQ0_INTE_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH1_Pos (1UL) /*!< CH1 (Bit 1) */ +#define PWM_IRQ0_INTE_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTE_CH0_Pos (0UL) /*!< CH0 (Bit 0) */ +#define PWM_IRQ0_INTE_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ0_INTF ======================================================= */ +#define PWM_IRQ0_INTF_CH11_Pos (11UL) /*!< CH11 (Bit 11) */ +#define PWM_IRQ0_INTF_CH11_Msk (0x800UL) /*!< CH11 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH10_Pos (10UL) /*!< CH10 (Bit 10) */ +#define PWM_IRQ0_INTF_CH10_Msk (0x400UL) /*!< CH10 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH9_Pos (9UL) /*!< CH9 (Bit 9) */ +#define PWM_IRQ0_INTF_CH9_Msk (0x200UL) /*!< CH9 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH8_Pos (8UL) /*!< CH8 (Bit 8) */ +#define PWM_IRQ0_INTF_CH8_Msk (0x100UL) /*!< CH8 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH7_Pos (7UL) /*!< CH7 (Bit 7) */ +#define PWM_IRQ0_INTF_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH6_Pos (6UL) /*!< CH6 (Bit 6) */ +#define PWM_IRQ0_INTF_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH5_Pos (5UL) /*!< CH5 (Bit 5) */ +#define PWM_IRQ0_INTF_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH4_Pos (4UL) /*!< CH4 (Bit 4) */ +#define PWM_IRQ0_INTF_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH3_Pos (3UL) /*!< CH3 (Bit 3) */ +#define PWM_IRQ0_INTF_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH2_Pos (2UL) /*!< CH2 (Bit 2) */ +#define PWM_IRQ0_INTF_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH1_Pos (1UL) /*!< CH1 (Bit 1) */ +#define PWM_IRQ0_INTF_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTF_CH0_Pos (0UL) /*!< CH0 (Bit 0) */ +#define PWM_IRQ0_INTF_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ0_INTS ======================================================= */ +#define PWM_IRQ0_INTS_CH11_Pos (11UL) /*!< CH11 (Bit 11) */ +#define PWM_IRQ0_INTS_CH11_Msk (0x800UL) /*!< CH11 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH10_Pos (10UL) /*!< CH10 (Bit 10) */ +#define PWM_IRQ0_INTS_CH10_Msk (0x400UL) /*!< CH10 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH9_Pos (9UL) /*!< CH9 (Bit 9) */ +#define PWM_IRQ0_INTS_CH9_Msk (0x200UL) /*!< CH9 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH8_Pos (8UL) /*!< CH8 (Bit 8) */ +#define PWM_IRQ0_INTS_CH8_Msk (0x100UL) /*!< CH8 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH7_Pos (7UL) /*!< CH7 (Bit 7) */ +#define PWM_IRQ0_INTS_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH6_Pos (6UL) /*!< CH6 (Bit 6) */ +#define PWM_IRQ0_INTS_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH5_Pos (5UL) /*!< CH5 (Bit 5) */ +#define PWM_IRQ0_INTS_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH4_Pos (4UL) /*!< CH4 (Bit 4) */ +#define PWM_IRQ0_INTS_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH3_Pos (3UL) /*!< CH3 (Bit 3) */ +#define PWM_IRQ0_INTS_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH2_Pos (2UL) /*!< CH2 (Bit 2) */ +#define PWM_IRQ0_INTS_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH1_Pos (1UL) /*!< CH1 (Bit 1) */ +#define PWM_IRQ0_INTS_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ0_INTS_CH0_Pos (0UL) /*!< CH0 (Bit 0) */ +#define PWM_IRQ0_INTS_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ1_INTE ======================================================= */ +#define PWM_IRQ1_INTE_CH11_Pos (11UL) /*!< CH11 (Bit 11) */ +#define PWM_IRQ1_INTE_CH11_Msk (0x800UL) /*!< CH11 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH10_Pos (10UL) /*!< CH10 (Bit 10) */ +#define PWM_IRQ1_INTE_CH10_Msk (0x400UL) /*!< CH10 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH9_Pos (9UL) /*!< CH9 (Bit 9) */ +#define PWM_IRQ1_INTE_CH9_Msk (0x200UL) /*!< CH9 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH8_Pos (8UL) /*!< CH8 (Bit 8) */ +#define PWM_IRQ1_INTE_CH8_Msk (0x100UL) /*!< CH8 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH7_Pos (7UL) /*!< CH7 (Bit 7) */ +#define PWM_IRQ1_INTE_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH6_Pos (6UL) /*!< CH6 (Bit 6) */ +#define PWM_IRQ1_INTE_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH5_Pos (5UL) /*!< CH5 (Bit 5) */ +#define PWM_IRQ1_INTE_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH4_Pos (4UL) /*!< CH4 (Bit 4) */ +#define PWM_IRQ1_INTE_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH3_Pos (3UL) /*!< CH3 (Bit 3) */ +#define PWM_IRQ1_INTE_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH2_Pos (2UL) /*!< CH2 (Bit 2) */ +#define PWM_IRQ1_INTE_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH1_Pos (1UL) /*!< CH1 (Bit 1) */ +#define PWM_IRQ1_INTE_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTE_CH0_Pos (0UL) /*!< CH0 (Bit 0) */ +#define PWM_IRQ1_INTE_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ1_INTF ======================================================= */ +#define PWM_IRQ1_INTF_CH11_Pos (11UL) /*!< CH11 (Bit 11) */ +#define PWM_IRQ1_INTF_CH11_Msk (0x800UL) /*!< CH11 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH10_Pos (10UL) /*!< CH10 (Bit 10) */ +#define PWM_IRQ1_INTF_CH10_Msk (0x400UL) /*!< CH10 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH9_Pos (9UL) /*!< CH9 (Bit 9) */ +#define PWM_IRQ1_INTF_CH9_Msk (0x200UL) /*!< CH9 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH8_Pos (8UL) /*!< CH8 (Bit 8) */ +#define PWM_IRQ1_INTF_CH8_Msk (0x100UL) /*!< CH8 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH7_Pos (7UL) /*!< CH7 (Bit 7) */ +#define PWM_IRQ1_INTF_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH6_Pos (6UL) /*!< CH6 (Bit 6) */ +#define PWM_IRQ1_INTF_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH5_Pos (5UL) /*!< CH5 (Bit 5) */ +#define PWM_IRQ1_INTF_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH4_Pos (4UL) /*!< CH4 (Bit 4) */ +#define PWM_IRQ1_INTF_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH3_Pos (3UL) /*!< CH3 (Bit 3) */ +#define PWM_IRQ1_INTF_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH2_Pos (2UL) /*!< CH2 (Bit 2) */ +#define PWM_IRQ1_INTF_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH1_Pos (1UL) /*!< CH1 (Bit 1) */ +#define PWM_IRQ1_INTF_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTF_CH0_Pos (0UL) /*!< CH0 (Bit 0) */ +#define PWM_IRQ1_INTF_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ1_INTS ======================================================= */ +#define PWM_IRQ1_INTS_CH11_Pos (11UL) /*!< CH11 (Bit 11) */ +#define PWM_IRQ1_INTS_CH11_Msk (0x800UL) /*!< CH11 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH10_Pos (10UL) /*!< CH10 (Bit 10) */ +#define PWM_IRQ1_INTS_CH10_Msk (0x400UL) /*!< CH10 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH9_Pos (9UL) /*!< CH9 (Bit 9) */ +#define PWM_IRQ1_INTS_CH9_Msk (0x200UL) /*!< CH9 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH8_Pos (8UL) /*!< CH8 (Bit 8) */ +#define PWM_IRQ1_INTS_CH8_Msk (0x100UL) /*!< CH8 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH7_Pos (7UL) /*!< CH7 (Bit 7) */ +#define PWM_IRQ1_INTS_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH6_Pos (6UL) /*!< CH6 (Bit 6) */ +#define PWM_IRQ1_INTS_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH5_Pos (5UL) /*!< CH5 (Bit 5) */ +#define PWM_IRQ1_INTS_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH4_Pos (4UL) /*!< CH4 (Bit 4) */ +#define PWM_IRQ1_INTS_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH3_Pos (3UL) /*!< CH3 (Bit 3) */ +#define PWM_IRQ1_INTS_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH2_Pos (2UL) /*!< CH2 (Bit 2) */ +#define PWM_IRQ1_INTS_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH1_Pos (1UL) /*!< CH1 (Bit 1) */ +#define PWM_IRQ1_INTS_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */ +#define PWM_IRQ1_INTS_CH0_Pos (0UL) /*!< CH0 (Bit 0) */ +#define PWM_IRQ1_INTS_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CS =========================================================== */ +#define ADC_CS_RROBIN_Pos (16UL) /*!< RROBIN (Bit 16) */ +#define ADC_CS_RROBIN_Msk (0x1ff0000UL) /*!< RROBIN (Bitfield-Mask: 0x1ff) */ +#define ADC_CS_AINSEL_Pos (12UL) /*!< AINSEL (Bit 12) */ +#define ADC_CS_AINSEL_Msk (0xf000UL) /*!< AINSEL (Bitfield-Mask: 0x0f) */ +#define ADC_CS_ERR_STICKY_Pos (10UL) /*!< ERR_STICKY (Bit 10) */ +#define ADC_CS_ERR_STICKY_Msk (0x400UL) /*!< ERR_STICKY (Bitfield-Mask: 0x01) */ +#define ADC_CS_ERR_Pos (9UL) /*!< ERR (Bit 9) */ +#define ADC_CS_ERR_Msk (0x200UL) /*!< ERR (Bitfield-Mask: 0x01) */ +#define ADC_CS_READY_Pos (8UL) /*!< READY (Bit 8) */ +#define ADC_CS_READY_Msk (0x100UL) /*!< READY (Bitfield-Mask: 0x01) */ +#define ADC_CS_START_MANY_Pos (3UL) /*!< START_MANY (Bit 3) */ +#define ADC_CS_START_MANY_Msk (0x8UL) /*!< START_MANY (Bitfield-Mask: 0x01) */ +#define ADC_CS_START_ONCE_Pos (2UL) /*!< START_ONCE (Bit 2) */ +#define ADC_CS_START_ONCE_Msk (0x4UL) /*!< START_ONCE (Bitfield-Mask: 0x01) */ +#define ADC_CS_TS_EN_Pos (1UL) /*!< TS_EN (Bit 1) */ +#define ADC_CS_TS_EN_Msk (0x2UL) /*!< TS_EN (Bitfield-Mask: 0x01) */ +#define ADC_CS_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define ADC_CS_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== RESULT ========================================================= */ +#define ADC_RESULT_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xfff) */ +/* ========================================================== FCS ========================================================== */ +#define ADC_FCS_THRESH_Pos (24UL) /*!< THRESH (Bit 24) */ +#define ADC_FCS_THRESH_Msk (0xf000000UL) /*!< THRESH (Bitfield-Mask: 0x0f) */ +#define ADC_FCS_LEVEL_Pos (16UL) /*!< LEVEL (Bit 16) */ +#define ADC_FCS_LEVEL_Msk (0xf0000UL) /*!< LEVEL (Bitfield-Mask: 0x0f) */ +#define ADC_FCS_OVER_Pos (11UL) /*!< OVER (Bit 11) */ +#define ADC_FCS_OVER_Msk (0x800UL) /*!< OVER (Bitfield-Mask: 0x01) */ +#define ADC_FCS_UNDER_Pos (10UL) /*!< UNDER (Bit 10) */ +#define ADC_FCS_UNDER_Msk (0x400UL) /*!< UNDER (Bitfield-Mask: 0x01) */ +#define ADC_FCS_FULL_Pos (9UL) /*!< FULL (Bit 9) */ +#define ADC_FCS_FULL_Msk (0x200UL) /*!< FULL (Bitfield-Mask: 0x01) */ +#define ADC_FCS_EMPTY_Pos (8UL) /*!< EMPTY (Bit 8) */ +#define ADC_FCS_EMPTY_Msk (0x100UL) /*!< EMPTY (Bitfield-Mask: 0x01) */ +#define ADC_FCS_DREQ_EN_Pos (3UL) /*!< DREQ_EN (Bit 3) */ +#define ADC_FCS_DREQ_EN_Msk (0x8UL) /*!< DREQ_EN (Bitfield-Mask: 0x01) */ +#define ADC_FCS_ERR_Pos (2UL) /*!< ERR (Bit 2) */ +#define ADC_FCS_ERR_Msk (0x4UL) /*!< ERR (Bitfield-Mask: 0x01) */ +#define ADC_FCS_SHIFT_Pos (1UL) /*!< SHIFT (Bit 1) */ +#define ADC_FCS_SHIFT_Msk (0x2UL) /*!< SHIFT (Bitfield-Mask: 0x01) */ +#define ADC_FCS_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define ADC_FCS_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= FIFO ========================================================== */ +#define ADC_FIFO_ERR_Pos (15UL) /*!< ERR (Bit 15) */ +#define ADC_FIFO_ERR_Msk (0x8000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +#define ADC_FIFO_VAL_Pos (0UL) /*!< VAL (Bit 0) */ +#define ADC_FIFO_VAL_Msk (0xfffUL) /*!< VAL (Bitfield-Mask: 0xfff) */ +/* ========================================================== DIV ========================================================== */ +#define ADC_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */ +#define ADC_DIV_INT_Msk (0xffff00UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define ADC_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */ +#define ADC_DIV_FRAC_Msk (0xffUL) /*!< FRAC (Bitfield-Mask: 0xff) */ +/* ========================================================= INTR ========================================================== */ +#define ADC_INTR_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define ADC_INTR_FIFO_Msk (0x1UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ +#define ADC_INTE_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define ADC_INTE_FIFO_Msk (0x1UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define ADC_INTF_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define ADC_INTF_FIFO_Msk (0x1UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ +#define ADC_INTS_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define ADC_INTS_FIFO_Msk (0x1UL) /*!< FIFO (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IC_CON ========================================================= */ +#define I2C0_IC_CON_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL) /*!< STOP_DET_IF_MASTER_ACTIVE (Bit 10) */ +#define I2C0_IC_CON_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_Pos (9UL) /*!< RX_FIFO_FULL_HLD_CTRL (Bit 9) */ +#define I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL) /*!< RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01) */ +#define I2C0_IC_CON_TX_EMPTY_CTRL_Pos (8UL) /*!< TX_EMPTY_CTRL (Bit 8) */ +#define I2C0_IC_CON_TX_EMPTY_CTRL_Msk (0x100UL) /*!< TX_EMPTY_CTRL (Bitfield-Mask: 0x01) */ +#define I2C0_IC_CON_STOP_DET_IFADDRESSED_Pos (7UL) /*!< STOP_DET_IFADDRESSED (Bit 7) */ +#define I2C0_IC_CON_STOP_DET_IFADDRESSED_Msk (0x80UL) /*!< STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01) */ +#define I2C0_IC_CON_IC_SLAVE_DISABLE_Pos (6UL) /*!< IC_SLAVE_DISABLE (Bit 6) */ +#define I2C0_IC_CON_IC_SLAVE_DISABLE_Msk (0x40UL) /*!< IC_SLAVE_DISABLE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_CON_IC_RESTART_EN_Pos (5UL) /*!< IC_RESTART_EN (Bit 5) */ +#define I2C0_IC_CON_IC_RESTART_EN_Msk (0x20UL) /*!< IC_RESTART_EN (Bitfield-Mask: 0x01) */ +#define I2C0_IC_CON_IC_10BITADDR_MASTER_Pos (4UL) /*!< IC_10BITADDR_MASTER (Bit 4) */ +#define I2C0_IC_CON_IC_10BITADDR_MASTER_Msk (0x10UL) /*!< IC_10BITADDR_MASTER (Bitfield-Mask: 0x01) */ +#define I2C0_IC_CON_IC_10BITADDR_SLAVE_Pos (3UL) /*!< IC_10BITADDR_SLAVE (Bit 3) */ +#define I2C0_IC_CON_IC_10BITADDR_SLAVE_Msk (0x8UL) /*!< IC_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_CON_SPEED_Pos (1UL) /*!< SPEED (Bit 1) */ +#define I2C0_IC_CON_SPEED_Msk (0x6UL) /*!< SPEED (Bitfield-Mask: 0x03) */ +#define I2C0_IC_CON_MASTER_MODE_Pos (0UL) /*!< MASTER_MODE (Bit 0) */ +#define I2C0_IC_CON_MASTER_MODE_Msk (0x1UL) /*!< MASTER_MODE (Bitfield-Mask: 0x01) */ +/* ======================================================== IC_TAR ========================================================= */ +#define I2C0_IC_TAR_SPECIAL_Pos (11UL) /*!< SPECIAL (Bit 11) */ +#define I2C0_IC_TAR_SPECIAL_Msk (0x800UL) /*!< SPECIAL (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TAR_GC_OR_START_Pos (10UL) /*!< GC_OR_START (Bit 10) */ +#define I2C0_IC_TAR_GC_OR_START_Msk (0x400UL) /*!< GC_OR_START (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TAR_IC_TAR_Pos (0UL) /*!< IC_TAR (Bit 0) */ +#define I2C0_IC_TAR_IC_TAR_Msk (0x3ffUL) /*!< IC_TAR (Bitfield-Mask: 0x3ff) */ +/* ======================================================== IC_SAR ========================================================= */ +#define I2C0_IC_SAR_IC_SAR_Pos (0UL) /*!< IC_SAR (Bit 0) */ +#define I2C0_IC_SAR_IC_SAR_Msk (0x3ffUL) /*!< IC_SAR (Bitfield-Mask: 0x3ff) */ +/* ====================================================== IC_DATA_CMD ====================================================== */ +#define I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_Pos (11UL) /*!< FIRST_DATA_BYTE (Bit 11) */ +#define I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_Msk (0x800UL) /*!< FIRST_DATA_BYTE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_DATA_CMD_RESTART_Pos (10UL) /*!< RESTART (Bit 10) */ +#define I2C0_IC_DATA_CMD_RESTART_Msk (0x400UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define I2C0_IC_DATA_CMD_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2C0_IC_DATA_CMD_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2C0_IC_DATA_CMD_CMD_Pos (8UL) /*!< CMD (Bit 8) */ +#define I2C0_IC_DATA_CMD_CMD_Msk (0x100UL) /*!< CMD (Bitfield-Mask: 0x01) */ +#define I2C0_IC_DATA_CMD_DAT_Pos (0UL) /*!< DAT (Bit 0) */ +#define I2C0_IC_DATA_CMD_DAT_Msk (0xffUL) /*!< DAT (Bitfield-Mask: 0xff) */ +/* ==================================================== IC_SS_SCL_HCNT ===================================================== */ +#define I2C0_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_Pos (0UL) /*!< IC_SS_SCL_HCNT (Bit 0) */ +#define I2C0_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== IC_SS_SCL_LCNT ===================================================== */ +#define I2C0_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_Pos (0UL) /*!< IC_SS_SCL_LCNT (Bit 0) */ +#define I2C0_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== IC_FS_SCL_HCNT ===================================================== */ +#define I2C0_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_Pos (0UL) /*!< IC_FS_SCL_HCNT (Bit 0) */ +#define I2C0_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== IC_FS_SCL_LCNT ===================================================== */ +#define I2C0_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */ +#define I2C0_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ===================================================== IC_INTR_STAT ====================================================== */ +#define I2C0_IC_INTR_STAT_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */ +#define I2C0_IC_INTR_STAT_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */ +#define I2C0_IC_INTR_STAT_R_GEN_CALL_Msk (0x800UL) /*!< R_GEN_CALL (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_START_DET_Pos (10UL) /*!< R_START_DET (Bit 10) */ +#define I2C0_IC_INTR_STAT_R_START_DET_Msk (0x400UL) /*!< R_START_DET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_STOP_DET_Pos (9UL) /*!< R_STOP_DET (Bit 9) */ +#define I2C0_IC_INTR_STAT_R_STOP_DET_Msk (0x200UL) /*!< R_STOP_DET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_ACTIVITY_Pos (8UL) /*!< R_ACTIVITY (Bit 8) */ +#define I2C0_IC_INTR_STAT_R_ACTIVITY_Msk (0x100UL) /*!< R_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_RX_DONE_Pos (7UL) /*!< R_RX_DONE (Bit 7) */ +#define I2C0_IC_INTR_STAT_R_RX_DONE_Msk (0x80UL) /*!< R_RX_DONE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_TX_ABRT_Pos (6UL) /*!< R_TX_ABRT (Bit 6) */ +#define I2C0_IC_INTR_STAT_R_TX_ABRT_Msk (0x40UL) /*!< R_TX_ABRT (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_RD_REQ_Pos (5UL) /*!< R_RD_REQ (Bit 5) */ +#define I2C0_IC_INTR_STAT_R_RD_REQ_Msk (0x20UL) /*!< R_RD_REQ (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_TX_EMPTY_Pos (4UL) /*!< R_TX_EMPTY (Bit 4) */ +#define I2C0_IC_INTR_STAT_R_TX_EMPTY_Msk (0x10UL) /*!< R_TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_TX_OVER_Pos (3UL) /*!< R_TX_OVER (Bit 3) */ +#define I2C0_IC_INTR_STAT_R_TX_OVER_Msk (0x8UL) /*!< R_TX_OVER (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_RX_FULL_Pos (2UL) /*!< R_RX_FULL (Bit 2) */ +#define I2C0_IC_INTR_STAT_R_RX_FULL_Msk (0x4UL) /*!< R_RX_FULL (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_RX_OVER_Pos (1UL) /*!< R_RX_OVER (Bit 1) */ +#define I2C0_IC_INTR_STAT_R_RX_OVER_Msk (0x2UL) /*!< R_RX_OVER (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_STAT_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */ +#define I2C0_IC_INTR_STAT_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ===================================================== IC_INTR_MASK ====================================================== */ +#define I2C0_IC_INTR_MASK_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */ +#define I2C0_IC_INTR_MASK_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */ +#define I2C0_IC_INTR_MASK_M_GEN_CALL_Msk (0x800UL) /*!< M_GEN_CALL (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_START_DET_Pos (10UL) /*!< M_START_DET (Bit 10) */ +#define I2C0_IC_INTR_MASK_M_START_DET_Msk (0x400UL) /*!< M_START_DET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_STOP_DET_Pos (9UL) /*!< M_STOP_DET (Bit 9) */ +#define I2C0_IC_INTR_MASK_M_STOP_DET_Msk (0x200UL) /*!< M_STOP_DET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_ACTIVITY_Pos (8UL) /*!< M_ACTIVITY (Bit 8) */ +#define I2C0_IC_INTR_MASK_M_ACTIVITY_Msk (0x100UL) /*!< M_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_RX_DONE_Pos (7UL) /*!< M_RX_DONE (Bit 7) */ +#define I2C0_IC_INTR_MASK_M_RX_DONE_Msk (0x80UL) /*!< M_RX_DONE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_TX_ABRT_Pos (6UL) /*!< M_TX_ABRT (Bit 6) */ +#define I2C0_IC_INTR_MASK_M_TX_ABRT_Msk (0x40UL) /*!< M_TX_ABRT (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_RD_REQ_Pos (5UL) /*!< M_RD_REQ (Bit 5) */ +#define I2C0_IC_INTR_MASK_M_RD_REQ_Msk (0x20UL) /*!< M_RD_REQ (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_TX_EMPTY_Pos (4UL) /*!< M_TX_EMPTY (Bit 4) */ +#define I2C0_IC_INTR_MASK_M_TX_EMPTY_Msk (0x10UL) /*!< M_TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_TX_OVER_Pos (3UL) /*!< M_TX_OVER (Bit 3) */ +#define I2C0_IC_INTR_MASK_M_TX_OVER_Msk (0x8UL) /*!< M_TX_OVER (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_RX_FULL_Pos (2UL) /*!< M_RX_FULL (Bit 2) */ +#define I2C0_IC_INTR_MASK_M_RX_FULL_Msk (0x4UL) /*!< M_RX_FULL (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_RX_OVER_Pos (1UL) /*!< M_RX_OVER (Bit 1) */ +#define I2C0_IC_INTR_MASK_M_RX_OVER_Msk (0x2UL) /*!< M_RX_OVER (Bitfield-Mask: 0x01) */ +#define I2C0_IC_INTR_MASK_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */ +#define I2C0_IC_INTR_MASK_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */ +/* =================================================== IC_RAW_INTR_STAT ==================================================== */ +#define I2C0_IC_RAW_INTR_STAT_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */ +#define I2C0_IC_RAW_INTR_STAT_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */ +#define I2C0_IC_RAW_INTR_STAT_GEN_CALL_Msk (0x800UL) /*!< GEN_CALL (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_START_DET_Pos (10UL) /*!< START_DET (Bit 10) */ +#define I2C0_IC_RAW_INTR_STAT_START_DET_Msk (0x400UL) /*!< START_DET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_STOP_DET_Pos (9UL) /*!< STOP_DET (Bit 9) */ +#define I2C0_IC_RAW_INTR_STAT_STOP_DET_Msk (0x200UL) /*!< STOP_DET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_ACTIVITY_Pos (8UL) /*!< ACTIVITY (Bit 8) */ +#define I2C0_IC_RAW_INTR_STAT_ACTIVITY_Msk (0x100UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_RX_DONE_Pos (7UL) /*!< RX_DONE (Bit 7) */ +#define I2C0_IC_RAW_INTR_STAT_RX_DONE_Msk (0x80UL) /*!< RX_DONE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_TX_ABRT_Pos (6UL) /*!< TX_ABRT (Bit 6) */ +#define I2C0_IC_RAW_INTR_STAT_TX_ABRT_Msk (0x40UL) /*!< TX_ABRT (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_RD_REQ_Pos (5UL) /*!< RD_REQ (Bit 5) */ +#define I2C0_IC_RAW_INTR_STAT_RD_REQ_Msk (0x20UL) /*!< RD_REQ (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_TX_EMPTY_Pos (4UL) /*!< TX_EMPTY (Bit 4) */ +#define I2C0_IC_RAW_INTR_STAT_TX_EMPTY_Msk (0x10UL) /*!< TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_TX_OVER_Pos (3UL) /*!< TX_OVER (Bit 3) */ +#define I2C0_IC_RAW_INTR_STAT_TX_OVER_Msk (0x8UL) /*!< TX_OVER (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_RX_FULL_Pos (2UL) /*!< RX_FULL (Bit 2) */ +#define I2C0_IC_RAW_INTR_STAT_RX_FULL_Msk (0x4UL) /*!< RX_FULL (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_RX_OVER_Pos (1UL) /*!< RX_OVER (Bit 1) */ +#define I2C0_IC_RAW_INTR_STAT_RX_OVER_Msk (0x2UL) /*!< RX_OVER (Bitfield-Mask: 0x01) */ +#define I2C0_IC_RAW_INTR_STAT_RX_UNDER_Pos (0UL) /*!< RX_UNDER (Bit 0) */ +#define I2C0_IC_RAW_INTR_STAT_RX_UNDER_Msk (0x1UL) /*!< RX_UNDER (Bitfield-Mask: 0x01) */ +/* ======================================================= IC_RX_TL ======================================================== */ +#define I2C0_IC_RX_TL_RX_TL_Pos (0UL) /*!< RX_TL (Bit 0) */ +#define I2C0_IC_RX_TL_RX_TL_Msk (0xffUL) /*!< RX_TL (Bitfield-Mask: 0xff) */ +/* ======================================================= IC_TX_TL ======================================================== */ +#define I2C0_IC_TX_TL_TX_TL_Pos (0UL) /*!< TX_TL (Bit 0) */ +#define I2C0_IC_TX_TL_TX_TL_Msk (0xffUL) /*!< TX_TL (Bitfield-Mask: 0xff) */ +/* ====================================================== IC_CLR_INTR ====================================================== */ +#define I2C0_IC_CLR_INTR_CLR_INTR_Pos (0UL) /*!< CLR_INTR (Bit 0) */ +#define I2C0_IC_CLR_INTR_CLR_INTR_Msk (0x1UL) /*!< CLR_INTR (Bitfield-Mask: 0x01) */ +/* ==================================================== IC_CLR_RX_UNDER ==================================================== */ +#define I2C0_IC_CLR_RX_UNDER_CLR_RX_UNDER_Pos (0UL) /*!< CLR_RX_UNDER (Bit 0) */ +#define I2C0_IC_CLR_RX_UNDER_CLR_RX_UNDER_Msk (0x1UL) /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ==================================================== IC_CLR_RX_OVER ===================================================== */ +#define I2C0_IC_CLR_RX_OVER_CLR_RX_OVER_Pos (0UL) /*!< CLR_RX_OVER (Bit 0) */ +#define I2C0_IC_CLR_RX_OVER_CLR_RX_OVER_Msk (0x1UL) /*!< CLR_RX_OVER (Bitfield-Mask: 0x01) */ +/* ==================================================== IC_CLR_TX_OVER ===================================================== */ +#define I2C0_IC_CLR_TX_OVER_CLR_TX_OVER_Pos (0UL) /*!< CLR_TX_OVER (Bit 0) */ +#define I2C0_IC_CLR_TX_OVER_CLR_TX_OVER_Msk (0x1UL) /*!< CLR_TX_OVER (Bitfield-Mask: 0x01) */ +/* ===================================================== IC_CLR_RD_REQ ===================================================== */ +#define I2C0_IC_CLR_RD_REQ_CLR_RD_REQ_Pos (0UL) /*!< CLR_RD_REQ (Bit 0) */ +#define I2C0_IC_CLR_RD_REQ_CLR_RD_REQ_Msk (0x1UL) /*!< CLR_RD_REQ (Bitfield-Mask: 0x01) */ +/* ==================================================== IC_CLR_TX_ABRT ===================================================== */ +#define I2C0_IC_CLR_TX_ABRT_CLR_TX_ABRT_Pos (0UL) /*!< CLR_TX_ABRT (Bit 0) */ +#define I2C0_IC_CLR_TX_ABRT_CLR_TX_ABRT_Msk (0x1UL) /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01) */ +/* ==================================================== IC_CLR_RX_DONE ===================================================== */ +#define I2C0_IC_CLR_RX_DONE_CLR_RX_DONE_Pos (0UL) /*!< CLR_RX_DONE (Bit 0) */ +#define I2C0_IC_CLR_RX_DONE_CLR_RX_DONE_Msk (0x1UL) /*!< CLR_RX_DONE (Bitfield-Mask: 0x01) */ +/* ==================================================== IC_CLR_ACTIVITY ==================================================== */ +#define I2C0_IC_CLR_ACTIVITY_CLR_ACTIVITY_Pos (0UL) /*!< CLR_ACTIVITY (Bit 0) */ +#define I2C0_IC_CLR_ACTIVITY_CLR_ACTIVITY_Msk (0x1UL) /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01) */ +/* ==================================================== IC_CLR_STOP_DET ==================================================== */ +#define I2C0_IC_CLR_STOP_DET_CLR_STOP_DET_Pos (0UL) /*!< CLR_STOP_DET (Bit 0) */ +#define I2C0_IC_CLR_STOP_DET_CLR_STOP_DET_Msk (0x1UL) /*!< CLR_STOP_DET (Bitfield-Mask: 0x01) */ +/* =================================================== IC_CLR_START_DET ==================================================== */ +#define I2C0_IC_CLR_START_DET_CLR_START_DET_Pos (0UL) /*!< CLR_START_DET (Bit 0) */ +#define I2C0_IC_CLR_START_DET_CLR_START_DET_Msk (0x1UL) /*!< CLR_START_DET (Bitfield-Mask: 0x01) */ +/* ==================================================== IC_CLR_GEN_CALL ==================================================== */ +#define I2C0_IC_CLR_GEN_CALL_CLR_GEN_CALL_Pos (0UL) /*!< CLR_GEN_CALL (Bit 0) */ +#define I2C0_IC_CLR_GEN_CALL_CLR_GEN_CALL_Msk (0x1UL) /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01) */ +/* ======================================================= IC_ENABLE ======================================================= */ +#define I2C0_IC_ENABLE_TX_CMD_BLOCK_Pos (2UL) /*!< TX_CMD_BLOCK (Bit 2) */ +#define I2C0_IC_ENABLE_TX_CMD_BLOCK_Msk (0x4UL) /*!< TX_CMD_BLOCK (Bitfield-Mask: 0x01) */ +#define I2C0_IC_ENABLE_ABORT_Pos (1UL) /*!< ABORT (Bit 1) */ +#define I2C0_IC_ENABLE_ABORT_Msk (0x2UL) /*!< ABORT (Bitfield-Mask: 0x01) */ +#define I2C0_IC_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define I2C0_IC_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= IC_STATUS ======================================================= */ +#define I2C0_IC_STATUS_SLV_ACTIVITY_Pos (6UL) /*!< SLV_ACTIVITY (Bit 6) */ +#define I2C0_IC_STATUS_SLV_ACTIVITY_Msk (0x40UL) /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C0_IC_STATUS_MST_ACTIVITY_Pos (5UL) /*!< MST_ACTIVITY (Bit 5) */ +#define I2C0_IC_STATUS_MST_ACTIVITY_Msk (0x20UL) /*!< MST_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C0_IC_STATUS_RFF_Pos (4UL) /*!< RFF (Bit 4) */ +#define I2C0_IC_STATUS_RFF_Msk (0x10UL) /*!< RFF (Bitfield-Mask: 0x01) */ +#define I2C0_IC_STATUS_RFNE_Pos (3UL) /*!< RFNE (Bit 3) */ +#define I2C0_IC_STATUS_RFNE_Msk (0x8UL) /*!< RFNE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_STATUS_TFE_Pos (2UL) /*!< TFE (Bit 2) */ +#define I2C0_IC_STATUS_TFE_Msk (0x4UL) /*!< TFE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_STATUS_TFNF_Pos (1UL) /*!< TFNF (Bit 1) */ +#define I2C0_IC_STATUS_TFNF_Msk (0x2UL) /*!< TFNF (Bitfield-Mask: 0x01) */ +#define I2C0_IC_STATUS_ACTIVITY_Pos (0UL) /*!< ACTIVITY (Bit 0) */ +#define I2C0_IC_STATUS_ACTIVITY_Msk (0x1UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */ +/* ======================================================= IC_TXFLR ======================================================== */ +#define I2C0_IC_TXFLR_TXFLR_Pos (0UL) /*!< TXFLR (Bit 0) */ +#define I2C0_IC_TXFLR_TXFLR_Msk (0x1fUL) /*!< TXFLR (Bitfield-Mask: 0x1f) */ +/* ======================================================= IC_RXFLR ======================================================== */ +#define I2C0_IC_RXFLR_RXFLR_Pos (0UL) /*!< RXFLR (Bit 0) */ +#define I2C0_IC_RXFLR_RXFLR_Msk (0x1fUL) /*!< RXFLR (Bitfield-Mask: 0x1f) */ +/* ====================================================== IC_SDA_HOLD ====================================================== */ +#define I2C0_IC_SDA_HOLD_IC_SDA_RX_HOLD_Pos (16UL) /*!< IC_SDA_RX_HOLD (Bit 16) */ +#define I2C0_IC_SDA_HOLD_IC_SDA_RX_HOLD_Msk (0xff0000UL) /*!< IC_SDA_RX_HOLD (Bitfield-Mask: 0xff) */ +#define I2C0_IC_SDA_HOLD_IC_SDA_TX_HOLD_Pos (0UL) /*!< IC_SDA_TX_HOLD (Bit 0) */ +#define I2C0_IC_SDA_HOLD_IC_SDA_TX_HOLD_Msk (0xffffUL) /*!< IC_SDA_TX_HOLD (Bitfield-Mask: 0xffff) */ +/* =================================================== IC_TX_ABRT_SOURCE =================================================== */ +#define I2C0_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_Pos (23UL) /*!< TX_FLUSH_CNT (Bit 23) */ +#define I2C0_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_Msk (0xff800000UL) /*!< TX_FLUSH_CNT (Bitfield-Mask: 0x1ff) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_Pos (16UL) /*!< ABRT_USER_ABRT (Bit 16) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_Msk (0x10000UL) /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_Pos (15UL) /*!< ABRT_SLVRD_INTX (Bit 15) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_Pos (14UL) /*!< ABRT_SLV_ARBLOST (Bit 14) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_Pos (12UL) /*!< ARB_LOST (Bit 12) */ +#define I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_Msk (0x1000UL) /*!< ARB_LOST (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_Pos (11UL) /*!< ABRT_MASTER_DIS (Bit 11) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_Msk (0x800UL) /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< ABRT_10B_RD_NORSTRT (Bit 10) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< ABRT_SBYTE_NORSTRT (Bit 9) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_Pos (8UL) /*!< ABRT_HS_NORSTRT (Bit 8) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< ABRT_SBYTE_ACKDET (Bit 7) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_Pos (6UL) /*!< ABRT_HS_ACKDET (Bit 6) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_Msk (0x40UL) /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_Pos (5UL) /*!< ABRT_GCALL_READ (Bit 5) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_Msk (0x20UL) /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_Pos (4UL) /*!< ABRT_GCALL_NOACK (Bit 4) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_Pos (3UL) /*!< ABRT_TXDATA_NOACK (Bit 3) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< ABRT_10ADDR2_NOACK (Bit 2) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< ABRT_10ADDR1_NOACK (Bit 1) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< ABRT_7B_ADDR_NOACK (Bit 0) */ +#define I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */ +/* ================================================= IC_SLV_DATA_NACK_ONLY ================================================= */ +#define I2C0_IC_SLV_DATA_NACK_ONLY_NACK_Pos (0UL) /*!< NACK (Bit 0) */ +#define I2C0_IC_SLV_DATA_NACK_ONLY_NACK_Msk (0x1UL) /*!< NACK (Bitfield-Mask: 0x01) */ +/* ======================================================= IC_DMA_CR ======================================================= */ +#define I2C0_IC_DMA_CR_TDMAE_Pos (1UL) /*!< TDMAE (Bit 1) */ +#define I2C0_IC_DMA_CR_TDMAE_Msk (0x2UL) /*!< TDMAE (Bitfield-Mask: 0x01) */ +#define I2C0_IC_DMA_CR_RDMAE_Pos (0UL) /*!< RDMAE (Bit 0) */ +#define I2C0_IC_DMA_CR_RDMAE_Msk (0x1UL) /*!< RDMAE (Bitfield-Mask: 0x01) */ +/* ====================================================== IC_DMA_TDLR ====================================================== */ +#define I2C0_IC_DMA_TDLR_DMATDL_Pos (0UL) /*!< DMATDL (Bit 0) */ +#define I2C0_IC_DMA_TDLR_DMATDL_Msk (0xfUL) /*!< DMATDL (Bitfield-Mask: 0x0f) */ +/* ====================================================== IC_DMA_RDLR ====================================================== */ +#define I2C0_IC_DMA_RDLR_DMARDL_Pos (0UL) /*!< DMARDL (Bit 0) */ +#define I2C0_IC_DMA_RDLR_DMARDL_Msk (0xfUL) /*!< DMARDL (Bitfield-Mask: 0x0f) */ +/* ===================================================== IC_SDA_SETUP ====================================================== */ +#define I2C0_IC_SDA_SETUP_SDA_SETUP_Pos (0UL) /*!< SDA_SETUP (Bit 0) */ +#define I2C0_IC_SDA_SETUP_SDA_SETUP_Msk (0xffUL) /*!< SDA_SETUP (Bitfield-Mask: 0xff) */ +/* ================================================== IC_ACK_GENERAL_CALL ================================================== */ +#define I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_Pos (0UL) /*!< ACK_GEN_CALL (Bit 0) */ +#define I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_Msk (0x1UL) /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01) */ +/* =================================================== IC_ENABLE_STATUS ==================================================== */ +#define I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_Pos (2UL) /*!< SLV_RX_DATA_LOST (Bit 2) */ +#define I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */ +#define I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1) */ +#define I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */ +#define I2C0_IC_ENABLE_STATUS_IC_EN_Pos (0UL) /*!< IC_EN (Bit 0) */ +#define I2C0_IC_ENABLE_STATUS_IC_EN_Msk (0x1UL) /*!< IC_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== IC_FS_SPKLEN ====================================================== */ +#define I2C0_IC_FS_SPKLEN_IC_FS_SPKLEN_Pos (0UL) /*!< IC_FS_SPKLEN (Bit 0) */ +#define I2C0_IC_FS_SPKLEN_IC_FS_SPKLEN_Msk (0xffUL) /*!< IC_FS_SPKLEN (Bitfield-Mask: 0xff) */ +/* ================================================== IC_CLR_RESTART_DET =================================================== */ +#define I2C0_IC_CLR_RESTART_DET_CLR_RESTART_DET_Pos (0UL) /*!< CLR_RESTART_DET (Bit 0) */ +#define I2C0_IC_CLR_RESTART_DET_CLR_RESTART_DET_Msk (0x1UL) /*!< CLR_RESTART_DET (Bitfield-Mask: 0x01) */ +/* ==================================================== IC_COMP_PARAM_1 ==================================================== */ +#define I2C0_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_Pos (16UL) /*!< TX_BUFFER_DEPTH (Bit 16) */ +#define I2C0_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_Msk (0xff0000UL) /*!< TX_BUFFER_DEPTH (Bitfield-Mask: 0xff) */ +#define I2C0_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_Pos (8UL) /*!< RX_BUFFER_DEPTH (Bit 8) */ +#define I2C0_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_Msk (0xff00UL) /*!< RX_BUFFER_DEPTH (Bitfield-Mask: 0xff) */ +#define I2C0_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_Pos (7UL) /*!< ADD_ENCODED_PARAMS (Bit 7) */ +#define I2C0_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_Msk (0x80UL) /*!< ADD_ENCODED_PARAMS (Bitfield-Mask: 0x01) */ +#define I2C0_IC_COMP_PARAM_1_HAS_DMA_Pos (6UL) /*!< HAS_DMA (Bit 6) */ +#define I2C0_IC_COMP_PARAM_1_HAS_DMA_Msk (0x40UL) /*!< HAS_DMA (Bitfield-Mask: 0x01) */ +#define I2C0_IC_COMP_PARAM_1_INTR_IO_Pos (5UL) /*!< INTR_IO (Bit 5) */ +#define I2C0_IC_COMP_PARAM_1_INTR_IO_Msk (0x20UL) /*!< INTR_IO (Bitfield-Mask: 0x01) */ +#define I2C0_IC_COMP_PARAM_1_HC_COUNT_VALUES_Pos (4UL) /*!< HC_COUNT_VALUES (Bit 4) */ +#define I2C0_IC_COMP_PARAM_1_HC_COUNT_VALUES_Msk (0x10UL) /*!< HC_COUNT_VALUES (Bitfield-Mask: 0x01) */ +#define I2C0_IC_COMP_PARAM_1_MAX_SPEED_MODE_Pos (2UL) /*!< MAX_SPEED_MODE (Bit 2) */ +#define I2C0_IC_COMP_PARAM_1_MAX_SPEED_MODE_Msk (0xcUL) /*!< MAX_SPEED_MODE (Bitfield-Mask: 0x03) */ +#define I2C0_IC_COMP_PARAM_1_APB_DATA_WIDTH_Pos (0UL) /*!< APB_DATA_WIDTH (Bit 0) */ +#define I2C0_IC_COMP_PARAM_1_APB_DATA_WIDTH_Msk (0x3UL) /*!< APB_DATA_WIDTH (Bitfield-Mask: 0x03) */ +/* ==================================================== IC_COMP_VERSION ==================================================== */ +#define I2C0_IC_COMP_VERSION_IC_COMP_VERSION_Pos (0UL) /*!< IC_COMP_VERSION (Bit 0) */ +#define I2C0_IC_COMP_VERSION_IC_COMP_VERSION_Msk (0xffffffffUL) /*!< IC_COMP_VERSION (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IC_COMP_TYPE ====================================================== */ +#define I2C0_IC_COMP_TYPE_IC_COMP_TYPE_Pos (0UL) /*!< IC_COMP_TYPE (Bit 0) */ +#define I2C0_IC_COMP_TYPE_IC_COMP_TYPE_Msk (0xffffffffUL) /*!< IC_COMP_TYPE (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SSPCR0 ========================================================= */ +#define SPI0_SSPCR0_SCR_Pos (8UL) /*!< SCR (Bit 8) */ +#define SPI0_SSPCR0_SCR_Msk (0xff00UL) /*!< SCR (Bitfield-Mask: 0xff) */ +#define SPI0_SSPCR0_SPH_Pos (7UL) /*!< SPH (Bit 7) */ +#define SPI0_SSPCR0_SPH_Msk (0x80UL) /*!< SPH (Bitfield-Mask: 0x01) */ +#define SPI0_SSPCR0_SPO_Pos (6UL) /*!< SPO (Bit 6) */ +#define SPI0_SSPCR0_SPO_Msk (0x40UL) /*!< SPO (Bitfield-Mask: 0x01) */ +#define SPI0_SSPCR0_FRF_Pos (4UL) /*!< FRF (Bit 4) */ +#define SPI0_SSPCR0_FRF_Msk (0x30UL) /*!< FRF (Bitfield-Mask: 0x03) */ +#define SPI0_SSPCR0_DSS_Pos (0UL) /*!< DSS (Bit 0) */ +#define SPI0_SSPCR0_DSS_Msk (0xfUL) /*!< DSS (Bitfield-Mask: 0x0f) */ +/* ======================================================== SSPCR1 ========================================================= */ +#define SPI0_SSPCR1_SOD_Pos (3UL) /*!< SOD (Bit 3) */ +#define SPI0_SSPCR1_SOD_Msk (0x8UL) /*!< SOD (Bitfield-Mask: 0x01) */ +#define SPI0_SSPCR1_MS_Pos (2UL) /*!< MS (Bit 2) */ +#define SPI0_SSPCR1_MS_Msk (0x4UL) /*!< MS (Bitfield-Mask: 0x01) */ +#define SPI0_SSPCR1_SSE_Pos (1UL) /*!< SSE (Bit 1) */ +#define SPI0_SSPCR1_SSE_Msk (0x2UL) /*!< SSE (Bitfield-Mask: 0x01) */ +#define SPI0_SSPCR1_LBM_Pos (0UL) /*!< LBM (Bit 0) */ +#define SPI0_SSPCR1_LBM_Msk (0x1UL) /*!< LBM (Bitfield-Mask: 0x01) */ +/* ========================================================= SSPDR ========================================================= */ +#define SPI0_SSPDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define SPI0_SSPDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= SSPSR ========================================================= */ +#define SPI0_SSPSR_BSY_Pos (4UL) /*!< BSY (Bit 4) */ +#define SPI0_SSPSR_BSY_Msk (0x10UL) /*!< BSY (Bitfield-Mask: 0x01) */ +#define SPI0_SSPSR_RFF_Pos (3UL) /*!< RFF (Bit 3) */ +#define SPI0_SSPSR_RFF_Msk (0x8UL) /*!< RFF (Bitfield-Mask: 0x01) */ +#define SPI0_SSPSR_RNE_Pos (2UL) /*!< RNE (Bit 2) */ +#define SPI0_SSPSR_RNE_Msk (0x4UL) /*!< RNE (Bitfield-Mask: 0x01) */ +#define SPI0_SSPSR_TNF_Pos (1UL) /*!< TNF (Bit 1) */ +#define SPI0_SSPSR_TNF_Msk (0x2UL) /*!< TNF (Bitfield-Mask: 0x01) */ +#define SPI0_SSPSR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ +#define SPI0_SSPSR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ======================================================== SSPCPSR ======================================================== */ +#define SPI0_SSPCPSR_CPSDVSR_Pos (0UL) /*!< CPSDVSR (Bit 0) */ +#define SPI0_SSPCPSR_CPSDVSR_Msk (0xffUL) /*!< CPSDVSR (Bitfield-Mask: 0xff) */ +/* ======================================================== SSPIMSC ======================================================== */ +#define SPI0_SSPIMSC_TXIM_Pos (3UL) /*!< TXIM (Bit 3) */ +#define SPI0_SSPIMSC_TXIM_Msk (0x8UL) /*!< TXIM (Bitfield-Mask: 0x01) */ +#define SPI0_SSPIMSC_RXIM_Pos (2UL) /*!< RXIM (Bit 2) */ +#define SPI0_SSPIMSC_RXIM_Msk (0x4UL) /*!< RXIM (Bitfield-Mask: 0x01) */ +#define SPI0_SSPIMSC_RTIM_Pos (1UL) /*!< RTIM (Bit 1) */ +#define SPI0_SSPIMSC_RTIM_Msk (0x2UL) /*!< RTIM (Bitfield-Mask: 0x01) */ +#define SPI0_SSPIMSC_RORIM_Pos (0UL) /*!< RORIM (Bit 0) */ +#define SPI0_SSPIMSC_RORIM_Msk (0x1UL) /*!< RORIM (Bitfield-Mask: 0x01) */ +/* ======================================================== SSPRIS ========================================================= */ +#define SPI0_SSPRIS_TXRIS_Pos (3UL) /*!< TXRIS (Bit 3) */ +#define SPI0_SSPRIS_TXRIS_Msk (0x8UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ +#define SPI0_SSPRIS_RXRIS_Pos (2UL) /*!< RXRIS (Bit 2) */ +#define SPI0_SSPRIS_RXRIS_Msk (0x4UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ +#define SPI0_SSPRIS_RTRIS_Pos (1UL) /*!< RTRIS (Bit 1) */ +#define SPI0_SSPRIS_RTRIS_Msk (0x2UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ +#define SPI0_SSPRIS_RORRIS_Pos (0UL) /*!< RORRIS (Bit 0) */ +#define SPI0_SSPRIS_RORRIS_Msk (0x1UL) /*!< RORRIS (Bitfield-Mask: 0x01) */ +/* ======================================================== SSPMIS ========================================================= */ +#define SPI0_SSPMIS_TXMIS_Pos (3UL) /*!< TXMIS (Bit 3) */ +#define SPI0_SSPMIS_TXMIS_Msk (0x8UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ +#define SPI0_SSPMIS_RXMIS_Pos (2UL) /*!< RXMIS (Bit 2) */ +#define SPI0_SSPMIS_RXMIS_Msk (0x4UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ +#define SPI0_SSPMIS_RTMIS_Pos (1UL) /*!< RTMIS (Bit 1) */ +#define SPI0_SSPMIS_RTMIS_Msk (0x2UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ +#define SPI0_SSPMIS_RORMIS_Pos (0UL) /*!< RORMIS (Bit 0) */ +#define SPI0_SSPMIS_RORMIS_Msk (0x1UL) /*!< RORMIS (Bitfield-Mask: 0x01) */ +/* ======================================================== SSPICR ========================================================= */ +#define SPI0_SSPICR_RTIC_Pos (1UL) /*!< RTIC (Bit 1) */ +#define SPI0_SSPICR_RTIC_Msk (0x2UL) /*!< RTIC (Bitfield-Mask: 0x01) */ +#define SPI0_SSPICR_RORIC_Pos (0UL) /*!< RORIC (Bit 0) */ +#define SPI0_SSPICR_RORIC_Msk (0x1UL) /*!< RORIC (Bitfield-Mask: 0x01) */ +/* ======================================================= SSPDMACR ======================================================== */ +#define SPI0_SSPDMACR_TXDMAE_Pos (1UL) /*!< TXDMAE (Bit 1) */ +#define SPI0_SSPDMACR_TXDMAE_Msk (0x2UL) /*!< TXDMAE (Bitfield-Mask: 0x01) */ +#define SPI0_SSPDMACR_RXDMAE_Pos (0UL) /*!< RXDMAE (Bit 0) */ +#define SPI0_SSPDMACR_RXDMAE_Msk (0x1UL) /*!< RXDMAE (Bitfield-Mask: 0x01) */ +/* ===================================================== SSPPERIPHID0 ====================================================== */ +#define SPI0_SSPPERIPHID0_PARTNUMBER0_Pos (0UL) /*!< PARTNUMBER0 (Bit 0) */ +#define SPI0_SSPPERIPHID0_PARTNUMBER0_Msk (0xffUL) /*!< PARTNUMBER0 (Bitfield-Mask: 0xff) */ +/* ===================================================== SSPPERIPHID1 ====================================================== */ +#define SPI0_SSPPERIPHID1_DESIGNER0_Pos (4UL) /*!< DESIGNER0 (Bit 4) */ +#define SPI0_SSPPERIPHID1_DESIGNER0_Msk (0xf0UL) /*!< DESIGNER0 (Bitfield-Mask: 0x0f) */ +#define SPI0_SSPPERIPHID1_PARTNUMBER1_Pos (0UL) /*!< PARTNUMBER1 (Bit 0) */ +#define SPI0_SSPPERIPHID1_PARTNUMBER1_Msk (0xfUL) /*!< PARTNUMBER1 (Bitfield-Mask: 0x0f) */ +/* ===================================================== SSPPERIPHID2 ====================================================== */ +#define SPI0_SSPPERIPHID2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */ +#define SPI0_SSPPERIPHID2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */ +#define SPI0_SSPPERIPHID2_DESIGNER1_Pos (0UL) /*!< DESIGNER1 (Bit 0) */ +#define SPI0_SSPPERIPHID2_DESIGNER1_Msk (0xfUL) /*!< DESIGNER1 (Bitfield-Mask: 0x0f) */ +/* ===================================================== SSPPERIPHID3 ====================================================== */ +#define SPI0_SSPPERIPHID3_CONFIGURATION_Pos (0UL) /*!< CONFIGURATION (Bit 0) */ +#define SPI0_SSPPERIPHID3_CONFIGURATION_Msk (0xffUL) /*!< CONFIGURATION (Bitfield-Mask: 0xff) */ +/* ====================================================== SSPPCELLID0 ====================================================== */ +#define SPI0_SSPPCELLID0_SSPPCELLID0_Pos (0UL) /*!< SSPPCELLID0 (Bit 0) */ +#define SPI0_SSPPCELLID0_SSPPCELLID0_Msk (0xffUL) /*!< SSPPCELLID0 (Bitfield-Mask: 0xff) */ +/* ====================================================== SSPPCELLID1 ====================================================== */ +#define SPI0_SSPPCELLID1_SSPPCELLID1_Pos (0UL) /*!< SSPPCELLID1 (Bit 0) */ +#define SPI0_SSPPCELLID1_SSPPCELLID1_Msk (0xffUL) /*!< SSPPCELLID1 (Bitfield-Mask: 0xff) */ +/* ====================================================== SSPPCELLID2 ====================================================== */ +#define SPI0_SSPPCELLID2_SSPPCELLID2_Pos (0UL) /*!< SSPPCELLID2 (Bit 0) */ +#define SPI0_SSPPCELLID2_SSPPCELLID2_Msk (0xffUL) /*!< SSPPCELLID2 (Bitfield-Mask: 0xff) */ +/* ====================================================== SSPPCELLID3 ====================================================== */ +#define SPI0_SSPPCELLID3_SSPPCELLID3_Pos (0UL) /*!< SSPPCELLID3 (Bit 0) */ +#define SPI0_SSPPCELLID3_SSPPCELLID3_Msk (0xffUL) /*!< SSPPCELLID3 (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ PIO0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define PIO0_CTRL_NEXTPREV_CLKDIV_RESTART_Pos (26UL) /*!< NEXTPREV_CLKDIV_RESTART (Bit 26) */ +#define PIO0_CTRL_NEXTPREV_CLKDIV_RESTART_Msk (0x4000000UL) /*!< NEXTPREV_CLKDIV_RESTART (Bitfield-Mask: 0x01) */ +#define PIO0_CTRL_NEXTPREV_SM_DISABLE_Pos (25UL) /*!< NEXTPREV_SM_DISABLE (Bit 25) */ +#define PIO0_CTRL_NEXTPREV_SM_DISABLE_Msk (0x2000000UL) /*!< NEXTPREV_SM_DISABLE (Bitfield-Mask: 0x01) */ +#define PIO0_CTRL_NEXTPREV_SM_ENABLE_Pos (24UL) /*!< NEXTPREV_SM_ENABLE (Bit 24) */ +#define PIO0_CTRL_NEXTPREV_SM_ENABLE_Msk (0x1000000UL) /*!< NEXTPREV_SM_ENABLE (Bitfield-Mask: 0x01) */ +#define PIO0_CTRL_NEXT_PIO_MASK_Pos (20UL) /*!< NEXT_PIO_MASK (Bit 20) */ +#define PIO0_CTRL_NEXT_PIO_MASK_Msk (0xf00000UL) /*!< NEXT_PIO_MASK (Bitfield-Mask: 0x0f) */ +#define PIO0_CTRL_PREV_PIO_MASK_Pos (16UL) /*!< PREV_PIO_MASK (Bit 16) */ +#define PIO0_CTRL_PREV_PIO_MASK_Msk (0xf0000UL) /*!< PREV_PIO_MASK (Bitfield-Mask: 0x0f) */ +#define PIO0_CTRL_CLKDIV_RESTART_Pos (8UL) /*!< CLKDIV_RESTART (Bit 8) */ +#define PIO0_CTRL_CLKDIV_RESTART_Msk (0xf00UL) /*!< CLKDIV_RESTART (Bitfield-Mask: 0x0f) */ +#define PIO0_CTRL_SM_RESTART_Pos (4UL) /*!< SM_RESTART (Bit 4) */ +#define PIO0_CTRL_SM_RESTART_Msk (0xf0UL) /*!< SM_RESTART (Bitfield-Mask: 0x0f) */ +#define PIO0_CTRL_SM_ENABLE_Pos (0UL) /*!< SM_ENABLE (Bit 0) */ +#define PIO0_CTRL_SM_ENABLE_Msk (0xfUL) /*!< SM_ENABLE (Bitfield-Mask: 0x0f) */ +/* ========================================================= FSTAT ========================================================= */ +#define PIO0_FSTAT_TXEMPTY_Pos (24UL) /*!< TXEMPTY (Bit 24) */ +#define PIO0_FSTAT_TXEMPTY_Msk (0xf000000UL) /*!< TXEMPTY (Bitfield-Mask: 0x0f) */ +#define PIO0_FSTAT_TXFULL_Pos (16UL) /*!< TXFULL (Bit 16) */ +#define PIO0_FSTAT_TXFULL_Msk (0xf0000UL) /*!< TXFULL (Bitfield-Mask: 0x0f) */ +#define PIO0_FSTAT_RXEMPTY_Pos (8UL) /*!< RXEMPTY (Bit 8) */ +#define PIO0_FSTAT_RXEMPTY_Msk (0xf00UL) /*!< RXEMPTY (Bitfield-Mask: 0x0f) */ +#define PIO0_FSTAT_RXFULL_Pos (0UL) /*!< RXFULL (Bit 0) */ +#define PIO0_FSTAT_RXFULL_Msk (0xfUL) /*!< RXFULL (Bitfield-Mask: 0x0f) */ +/* ======================================================== FDEBUG ========================================================= */ +#define PIO0_FDEBUG_TXSTALL_Pos (24UL) /*!< TXSTALL (Bit 24) */ +#define PIO0_FDEBUG_TXSTALL_Msk (0xf000000UL) /*!< TXSTALL (Bitfield-Mask: 0x0f) */ +#define PIO0_FDEBUG_TXOVER_Pos (16UL) /*!< TXOVER (Bit 16) */ +#define PIO0_FDEBUG_TXOVER_Msk (0xf0000UL) /*!< TXOVER (Bitfield-Mask: 0x0f) */ +#define PIO0_FDEBUG_RXUNDER_Pos (8UL) /*!< RXUNDER (Bit 8) */ +#define PIO0_FDEBUG_RXUNDER_Msk (0xf00UL) /*!< RXUNDER (Bitfield-Mask: 0x0f) */ +#define PIO0_FDEBUG_RXSTALL_Pos (0UL) /*!< RXSTALL (Bit 0) */ +#define PIO0_FDEBUG_RXSTALL_Msk (0xfUL) /*!< RXSTALL (Bitfield-Mask: 0x0f) */ +/* ======================================================== FLEVEL ========================================================= */ +#define PIO0_FLEVEL_RX3_Pos (28UL) /*!< RX3 (Bit 28) */ +#define PIO0_FLEVEL_RX3_Msk (0xf0000000UL) /*!< RX3 (Bitfield-Mask: 0x0f) */ +#define PIO0_FLEVEL_TX3_Pos (24UL) /*!< TX3 (Bit 24) */ +#define PIO0_FLEVEL_TX3_Msk (0xf000000UL) /*!< TX3 (Bitfield-Mask: 0x0f) */ +#define PIO0_FLEVEL_RX2_Pos (20UL) /*!< RX2 (Bit 20) */ +#define PIO0_FLEVEL_RX2_Msk (0xf00000UL) /*!< RX2 (Bitfield-Mask: 0x0f) */ +#define PIO0_FLEVEL_TX2_Pos (16UL) /*!< TX2 (Bit 16) */ +#define PIO0_FLEVEL_TX2_Msk (0xf0000UL) /*!< TX2 (Bitfield-Mask: 0x0f) */ +#define PIO0_FLEVEL_RX1_Pos (12UL) /*!< RX1 (Bit 12) */ +#define PIO0_FLEVEL_RX1_Msk (0xf000UL) /*!< RX1 (Bitfield-Mask: 0x0f) */ +#define PIO0_FLEVEL_TX1_Pos (8UL) /*!< TX1 (Bit 8) */ +#define PIO0_FLEVEL_TX1_Msk (0xf00UL) /*!< TX1 (Bitfield-Mask: 0x0f) */ +#define PIO0_FLEVEL_RX0_Pos (4UL) /*!< RX0 (Bit 4) */ +#define PIO0_FLEVEL_RX0_Msk (0xf0UL) /*!< RX0 (Bitfield-Mask: 0x0f) */ +#define PIO0_FLEVEL_TX0_Pos (0UL) /*!< TX0 (Bit 0) */ +#define PIO0_FLEVEL_TX0_Msk (0xfUL) /*!< TX0 (Bitfield-Mask: 0x0f) */ +/* ========================================================= TXF0 ========================================================== */ +#define PIO0_TXF0_TXF0_Pos (0UL) /*!< TXF0 (Bit 0) */ +#define PIO0_TXF0_TXF0_Msk (0xffffffffUL) /*!< TXF0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TXF1 ========================================================== */ +#define PIO0_TXF1_TXF1_Pos (0UL) /*!< TXF1 (Bit 0) */ +#define PIO0_TXF1_TXF1_Msk (0xffffffffUL) /*!< TXF1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TXF2 ========================================================== */ +#define PIO0_TXF2_TXF2_Pos (0UL) /*!< TXF2 (Bit 0) */ +#define PIO0_TXF2_TXF2_Msk (0xffffffffUL) /*!< TXF2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TXF3 ========================================================== */ +#define PIO0_TXF3_TXF3_Pos (0UL) /*!< TXF3 (Bit 0) */ +#define PIO0_TXF3_TXF3_Msk (0xffffffffUL) /*!< TXF3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RXF0 ========================================================== */ +#define PIO0_RXF0_RXF0_Pos (0UL) /*!< RXF0 (Bit 0) */ +#define PIO0_RXF0_RXF0_Msk (0xffffffffUL) /*!< RXF0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RXF1 ========================================================== */ +#define PIO0_RXF1_RXF1_Pos (0UL) /*!< RXF1 (Bit 0) */ +#define PIO0_RXF1_RXF1_Msk (0xffffffffUL) /*!< RXF1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RXF2 ========================================================== */ +#define PIO0_RXF2_RXF2_Pos (0UL) /*!< RXF2 (Bit 0) */ +#define PIO0_RXF2_RXF2_Msk (0xffffffffUL) /*!< RXF2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RXF3 ========================================================== */ +#define PIO0_RXF3_RXF3_Pos (0UL) /*!< RXF3 (Bit 0) */ +#define PIO0_RXF3_RXF3_Msk (0xffffffffUL) /*!< RXF3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== IRQ ========================================================== */ +#define PIO0_IRQ_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ +#define PIO0_IRQ_IRQ_Msk (0xffUL) /*!< IRQ (Bitfield-Mask: 0xff) */ +/* ======================================================= IRQ_FORCE ======================================================= */ +#define PIO0_IRQ_FORCE_IRQ_FORCE_Pos (0UL) /*!< IRQ_FORCE (Bit 0) */ +#define PIO0_IRQ_FORCE_IRQ_FORCE_Msk (0xffUL) /*!< IRQ_FORCE (Bitfield-Mask: 0xff) */ +/* =================================================== INPUT_SYNC_BYPASS =================================================== */ +#define PIO0_INPUT_SYNC_BYPASS_INPUT_SYNC_BYPASS_Pos (0UL) /*!< INPUT_SYNC_BYPASS (Bit 0) */ +#define PIO0_INPUT_SYNC_BYPASS_INPUT_SYNC_BYPASS_Msk (0xffffffffUL) /*!< INPUT_SYNC_BYPASS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DBG_PADOUT ======================================================= */ +#define PIO0_DBG_PADOUT_DBG_PADOUT_Pos (0UL) /*!< DBG_PADOUT (Bit 0) */ +#define PIO0_DBG_PADOUT_DBG_PADOUT_Msk (0xffffffffUL) /*!< DBG_PADOUT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DBG_PADOE ======================================================= */ +#define PIO0_DBG_PADOE_DBG_PADOE_Pos (0UL) /*!< DBG_PADOE (Bit 0) */ +#define PIO0_DBG_PADOE_DBG_PADOE_Msk (0xffffffffUL) /*!< DBG_PADOE (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DBG_CFGINFO ====================================================== */ +#define PIO0_DBG_CFGINFO_VERSION_Pos (28UL) /*!< VERSION (Bit 28) */ +#define PIO0_DBG_CFGINFO_VERSION_Msk (0xf0000000UL) /*!< VERSION (Bitfield-Mask: 0x0f) */ +#define PIO0_DBG_CFGINFO_IMEM_SIZE_Pos (16UL) /*!< IMEM_SIZE (Bit 16) */ +#define PIO0_DBG_CFGINFO_IMEM_SIZE_Msk (0x3f0000UL) /*!< IMEM_SIZE (Bitfield-Mask: 0x3f) */ +#define PIO0_DBG_CFGINFO_SM_COUNT_Pos (8UL) /*!< SM_COUNT (Bit 8) */ +#define PIO0_DBG_CFGINFO_SM_COUNT_Msk (0xf00UL) /*!< SM_COUNT (Bitfield-Mask: 0x0f) */ +#define PIO0_DBG_CFGINFO_FIFO_DEPTH_Pos (0UL) /*!< FIFO_DEPTH (Bit 0) */ +#define PIO0_DBG_CFGINFO_FIFO_DEPTH_Msk (0x3fUL) /*!< FIFO_DEPTH (Bitfield-Mask: 0x3f) */ +/* ====================================================== INSTR_MEM0 ======================================================= */ +#define PIO0_INSTR_MEM0_INSTR_MEM0_Pos (0UL) /*!< INSTR_MEM0 (Bit 0) */ +#define PIO0_INSTR_MEM0_INSTR_MEM0_Msk (0xffffUL) /*!< INSTR_MEM0 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM1 ======================================================= */ +#define PIO0_INSTR_MEM1_INSTR_MEM1_Pos (0UL) /*!< INSTR_MEM1 (Bit 0) */ +#define PIO0_INSTR_MEM1_INSTR_MEM1_Msk (0xffffUL) /*!< INSTR_MEM1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM2 ======================================================= */ +#define PIO0_INSTR_MEM2_INSTR_MEM2_Pos (0UL) /*!< INSTR_MEM2 (Bit 0) */ +#define PIO0_INSTR_MEM2_INSTR_MEM2_Msk (0xffffUL) /*!< INSTR_MEM2 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM3 ======================================================= */ +#define PIO0_INSTR_MEM3_INSTR_MEM3_Pos (0UL) /*!< INSTR_MEM3 (Bit 0) */ +#define PIO0_INSTR_MEM3_INSTR_MEM3_Msk (0xffffUL) /*!< INSTR_MEM3 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM4 ======================================================= */ +#define PIO0_INSTR_MEM4_INSTR_MEM4_Pos (0UL) /*!< INSTR_MEM4 (Bit 0) */ +#define PIO0_INSTR_MEM4_INSTR_MEM4_Msk (0xffffUL) /*!< INSTR_MEM4 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM5 ======================================================= */ +#define PIO0_INSTR_MEM5_INSTR_MEM5_Pos (0UL) /*!< INSTR_MEM5 (Bit 0) */ +#define PIO0_INSTR_MEM5_INSTR_MEM5_Msk (0xffffUL) /*!< INSTR_MEM5 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM6 ======================================================= */ +#define PIO0_INSTR_MEM6_INSTR_MEM6_Pos (0UL) /*!< INSTR_MEM6 (Bit 0) */ +#define PIO0_INSTR_MEM6_INSTR_MEM6_Msk (0xffffUL) /*!< INSTR_MEM6 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM7 ======================================================= */ +#define PIO0_INSTR_MEM7_INSTR_MEM7_Pos (0UL) /*!< INSTR_MEM7 (Bit 0) */ +#define PIO0_INSTR_MEM7_INSTR_MEM7_Msk (0xffffUL) /*!< INSTR_MEM7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM8 ======================================================= */ +#define PIO0_INSTR_MEM8_INSTR_MEM8_Pos (0UL) /*!< INSTR_MEM8 (Bit 0) */ +#define PIO0_INSTR_MEM8_INSTR_MEM8_Msk (0xffffUL) /*!< INSTR_MEM8 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM9 ======================================================= */ +#define PIO0_INSTR_MEM9_INSTR_MEM9_Pos (0UL) /*!< INSTR_MEM9 (Bit 0) */ +#define PIO0_INSTR_MEM9_INSTR_MEM9_Msk (0xffffUL) /*!< INSTR_MEM9 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM10 ====================================================== */ +#define PIO0_INSTR_MEM10_INSTR_MEM10_Pos (0UL) /*!< INSTR_MEM10 (Bit 0) */ +#define PIO0_INSTR_MEM10_INSTR_MEM10_Msk (0xffffUL) /*!< INSTR_MEM10 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM11 ====================================================== */ +#define PIO0_INSTR_MEM11_INSTR_MEM11_Pos (0UL) /*!< INSTR_MEM11 (Bit 0) */ +#define PIO0_INSTR_MEM11_INSTR_MEM11_Msk (0xffffUL) /*!< INSTR_MEM11 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM12 ====================================================== */ +#define PIO0_INSTR_MEM12_INSTR_MEM12_Pos (0UL) /*!< INSTR_MEM12 (Bit 0) */ +#define PIO0_INSTR_MEM12_INSTR_MEM12_Msk (0xffffUL) /*!< INSTR_MEM12 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM13 ====================================================== */ +#define PIO0_INSTR_MEM13_INSTR_MEM13_Pos (0UL) /*!< INSTR_MEM13 (Bit 0) */ +#define PIO0_INSTR_MEM13_INSTR_MEM13_Msk (0xffffUL) /*!< INSTR_MEM13 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM14 ====================================================== */ +#define PIO0_INSTR_MEM14_INSTR_MEM14_Pos (0UL) /*!< INSTR_MEM14 (Bit 0) */ +#define PIO0_INSTR_MEM14_INSTR_MEM14_Msk (0xffffUL) /*!< INSTR_MEM14 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM15 ====================================================== */ +#define PIO0_INSTR_MEM15_INSTR_MEM15_Pos (0UL) /*!< INSTR_MEM15 (Bit 0) */ +#define PIO0_INSTR_MEM15_INSTR_MEM15_Msk (0xffffUL) /*!< INSTR_MEM15 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM16 ====================================================== */ +#define PIO0_INSTR_MEM16_INSTR_MEM16_Pos (0UL) /*!< INSTR_MEM16 (Bit 0) */ +#define PIO0_INSTR_MEM16_INSTR_MEM16_Msk (0xffffUL) /*!< INSTR_MEM16 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM17 ====================================================== */ +#define PIO0_INSTR_MEM17_INSTR_MEM17_Pos (0UL) /*!< INSTR_MEM17 (Bit 0) */ +#define PIO0_INSTR_MEM17_INSTR_MEM17_Msk (0xffffUL) /*!< INSTR_MEM17 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM18 ====================================================== */ +#define PIO0_INSTR_MEM18_INSTR_MEM18_Pos (0UL) /*!< INSTR_MEM18 (Bit 0) */ +#define PIO0_INSTR_MEM18_INSTR_MEM18_Msk (0xffffUL) /*!< INSTR_MEM18 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM19 ====================================================== */ +#define PIO0_INSTR_MEM19_INSTR_MEM19_Pos (0UL) /*!< INSTR_MEM19 (Bit 0) */ +#define PIO0_INSTR_MEM19_INSTR_MEM19_Msk (0xffffUL) /*!< INSTR_MEM19 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM20 ====================================================== */ +#define PIO0_INSTR_MEM20_INSTR_MEM20_Pos (0UL) /*!< INSTR_MEM20 (Bit 0) */ +#define PIO0_INSTR_MEM20_INSTR_MEM20_Msk (0xffffUL) /*!< INSTR_MEM20 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM21 ====================================================== */ +#define PIO0_INSTR_MEM21_INSTR_MEM21_Pos (0UL) /*!< INSTR_MEM21 (Bit 0) */ +#define PIO0_INSTR_MEM21_INSTR_MEM21_Msk (0xffffUL) /*!< INSTR_MEM21 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM22 ====================================================== */ +#define PIO0_INSTR_MEM22_INSTR_MEM22_Pos (0UL) /*!< INSTR_MEM22 (Bit 0) */ +#define PIO0_INSTR_MEM22_INSTR_MEM22_Msk (0xffffUL) /*!< INSTR_MEM22 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM23 ====================================================== */ +#define PIO0_INSTR_MEM23_INSTR_MEM23_Pos (0UL) /*!< INSTR_MEM23 (Bit 0) */ +#define PIO0_INSTR_MEM23_INSTR_MEM23_Msk (0xffffUL) /*!< INSTR_MEM23 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM24 ====================================================== */ +#define PIO0_INSTR_MEM24_INSTR_MEM24_Pos (0UL) /*!< INSTR_MEM24 (Bit 0) */ +#define PIO0_INSTR_MEM24_INSTR_MEM24_Msk (0xffffUL) /*!< INSTR_MEM24 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM25 ====================================================== */ +#define PIO0_INSTR_MEM25_INSTR_MEM25_Pos (0UL) /*!< INSTR_MEM25 (Bit 0) */ +#define PIO0_INSTR_MEM25_INSTR_MEM25_Msk (0xffffUL) /*!< INSTR_MEM25 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM26 ====================================================== */ +#define PIO0_INSTR_MEM26_INSTR_MEM26_Pos (0UL) /*!< INSTR_MEM26 (Bit 0) */ +#define PIO0_INSTR_MEM26_INSTR_MEM26_Msk (0xffffUL) /*!< INSTR_MEM26 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM27 ====================================================== */ +#define PIO0_INSTR_MEM27_INSTR_MEM27_Pos (0UL) /*!< INSTR_MEM27 (Bit 0) */ +#define PIO0_INSTR_MEM27_INSTR_MEM27_Msk (0xffffUL) /*!< INSTR_MEM27 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM28 ====================================================== */ +#define PIO0_INSTR_MEM28_INSTR_MEM28_Pos (0UL) /*!< INSTR_MEM28 (Bit 0) */ +#define PIO0_INSTR_MEM28_INSTR_MEM28_Msk (0xffffUL) /*!< INSTR_MEM28 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM29 ====================================================== */ +#define PIO0_INSTR_MEM29_INSTR_MEM29_Pos (0UL) /*!< INSTR_MEM29 (Bit 0) */ +#define PIO0_INSTR_MEM29_INSTR_MEM29_Msk (0xffffUL) /*!< INSTR_MEM29 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM30 ====================================================== */ +#define PIO0_INSTR_MEM30_INSTR_MEM30_Pos (0UL) /*!< INSTR_MEM30 (Bit 0) */ +#define PIO0_INSTR_MEM30_INSTR_MEM30_Msk (0xffffUL) /*!< INSTR_MEM30 (Bitfield-Mask: 0xffff) */ +/* ====================================================== INSTR_MEM31 ====================================================== */ +#define PIO0_INSTR_MEM31_INSTR_MEM31_Pos (0UL) /*!< INSTR_MEM31 (Bit 0) */ +#define PIO0_INSTR_MEM31_INSTR_MEM31_Msk (0xffffUL) /*!< INSTR_MEM31 (Bitfield-Mask: 0xffff) */ +/* ====================================================== SM0_CLKDIV ======================================================= */ +#define PIO0_SM0_CLKDIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define PIO0_SM0_CLKDIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define PIO0_SM0_CLKDIV_FRAC_Pos (8UL) /*!< FRAC (Bit 8) */ +#define PIO0_SM0_CLKDIV_FRAC_Msk (0xff00UL) /*!< FRAC (Bitfield-Mask: 0xff) */ +/* ===================================================== SM0_EXECCTRL ====================================================== */ +#define PIO0_SM0_EXECCTRL_EXEC_STALLED_Pos (31UL) /*!< EXEC_STALLED (Bit 31) */ +#define PIO0_SM0_EXECCTRL_EXEC_STALLED_Msk (0x80000000UL) /*!< EXEC_STALLED (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_EXECCTRL_SIDE_EN_Pos (30UL) /*!< SIDE_EN (Bit 30) */ +#define PIO0_SM0_EXECCTRL_SIDE_EN_Msk (0x40000000UL) /*!< SIDE_EN (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_EXECCTRL_SIDE_PINDIR_Pos (29UL) /*!< SIDE_PINDIR (Bit 29) */ +#define PIO0_SM0_EXECCTRL_SIDE_PINDIR_Msk (0x20000000UL) /*!< SIDE_PINDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_EXECCTRL_JMP_PIN_Pos (24UL) /*!< JMP_PIN (Bit 24) */ +#define PIO0_SM0_EXECCTRL_JMP_PIN_Msk (0x1f000000UL) /*!< JMP_PIN (Bitfield-Mask: 0x1f) */ +#define PIO0_SM0_EXECCTRL_OUT_EN_SEL_Pos (19UL) /*!< OUT_EN_SEL (Bit 19) */ +#define PIO0_SM0_EXECCTRL_OUT_EN_SEL_Msk (0xf80000UL) /*!< OUT_EN_SEL (Bitfield-Mask: 0x1f) */ +#define PIO0_SM0_EXECCTRL_INLINE_OUT_EN_Pos (18UL) /*!< INLINE_OUT_EN (Bit 18) */ +#define PIO0_SM0_EXECCTRL_INLINE_OUT_EN_Msk (0x40000UL) /*!< INLINE_OUT_EN (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_EXECCTRL_OUT_STICKY_Pos (17UL) /*!< OUT_STICKY (Bit 17) */ +#define PIO0_SM0_EXECCTRL_OUT_STICKY_Msk (0x20000UL) /*!< OUT_STICKY (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_EXECCTRL_WRAP_TOP_Pos (12UL) /*!< WRAP_TOP (Bit 12) */ +#define PIO0_SM0_EXECCTRL_WRAP_TOP_Msk (0x1f000UL) /*!< WRAP_TOP (Bitfield-Mask: 0x1f) */ +#define PIO0_SM0_EXECCTRL_WRAP_BOTTOM_Pos (7UL) /*!< WRAP_BOTTOM (Bit 7) */ +#define PIO0_SM0_EXECCTRL_WRAP_BOTTOM_Msk (0xf80UL) /*!< WRAP_BOTTOM (Bitfield-Mask: 0x1f) */ +#define PIO0_SM0_EXECCTRL_STATUS_SEL_Pos (5UL) /*!< STATUS_SEL (Bit 5) */ +#define PIO0_SM0_EXECCTRL_STATUS_SEL_Msk (0x60UL) /*!< STATUS_SEL (Bitfield-Mask: 0x03) */ +#define PIO0_SM0_EXECCTRL_STATUS_N_Pos (0UL) /*!< STATUS_N (Bit 0) */ +#define PIO0_SM0_EXECCTRL_STATUS_N_Msk (0x1fUL) /*!< STATUS_N (Bitfield-Mask: 0x1f) */ +/* ===================================================== SM0_SHIFTCTRL ===================================================== */ +#define PIO0_SM0_SHIFTCTRL_FJOIN_RX_Pos (31UL) /*!< FJOIN_RX (Bit 31) */ +#define PIO0_SM0_SHIFTCTRL_FJOIN_RX_Msk (0x80000000UL) /*!< FJOIN_RX (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_SHIFTCTRL_FJOIN_TX_Pos (30UL) /*!< FJOIN_TX (Bit 30) */ +#define PIO0_SM0_SHIFTCTRL_FJOIN_TX_Msk (0x40000000UL) /*!< FJOIN_TX (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_SHIFTCTRL_PULL_THRESH_Pos (25UL) /*!< PULL_THRESH (Bit 25) */ +#define PIO0_SM0_SHIFTCTRL_PULL_THRESH_Msk (0x3e000000UL) /*!< PULL_THRESH (Bitfield-Mask: 0x1f) */ +#define PIO0_SM0_SHIFTCTRL_PUSH_THRESH_Pos (20UL) /*!< PUSH_THRESH (Bit 20) */ +#define PIO0_SM0_SHIFTCTRL_PUSH_THRESH_Msk (0x1f00000UL) /*!< PUSH_THRESH (Bitfield-Mask: 0x1f) */ +#define PIO0_SM0_SHIFTCTRL_OUT_SHIFTDIR_Pos (19UL) /*!< OUT_SHIFTDIR (Bit 19) */ +#define PIO0_SM0_SHIFTCTRL_OUT_SHIFTDIR_Msk (0x80000UL) /*!< OUT_SHIFTDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_SHIFTCTRL_IN_SHIFTDIR_Pos (18UL) /*!< IN_SHIFTDIR (Bit 18) */ +#define PIO0_SM0_SHIFTCTRL_IN_SHIFTDIR_Msk (0x40000UL) /*!< IN_SHIFTDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_SHIFTCTRL_AUTOPULL_Pos (17UL) /*!< AUTOPULL (Bit 17) */ +#define PIO0_SM0_SHIFTCTRL_AUTOPULL_Msk (0x20000UL) /*!< AUTOPULL (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_SHIFTCTRL_AUTOPUSH_Pos (16UL) /*!< AUTOPUSH (Bit 16) */ +#define PIO0_SM0_SHIFTCTRL_AUTOPUSH_Msk (0x10000UL) /*!< AUTOPUSH (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_SHIFTCTRL_FJOIN_RX_PUT_Pos (15UL) /*!< FJOIN_RX_PUT (Bit 15) */ +#define PIO0_SM0_SHIFTCTRL_FJOIN_RX_PUT_Msk (0x8000UL) /*!< FJOIN_RX_PUT (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_SHIFTCTRL_FJOIN_RX_GET_Pos (14UL) /*!< FJOIN_RX_GET (Bit 14) */ +#define PIO0_SM0_SHIFTCTRL_FJOIN_RX_GET_Msk (0x4000UL) /*!< FJOIN_RX_GET (Bitfield-Mask: 0x01) */ +#define PIO0_SM0_SHIFTCTRL_IN_COUNT_Pos (0UL) /*!< IN_COUNT (Bit 0) */ +#define PIO0_SM0_SHIFTCTRL_IN_COUNT_Msk (0x1fUL) /*!< IN_COUNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= SM0_ADDR ======================================================== */ +#define PIO0_SM0_ADDR_SM0_ADDR_Pos (0UL) /*!< SM0_ADDR (Bit 0) */ +#define PIO0_SM0_ADDR_SM0_ADDR_Msk (0x1fUL) /*!< SM0_ADDR (Bitfield-Mask: 0x1f) */ +/* ======================================================= SM0_INSTR ======================================================= */ +#define PIO0_SM0_INSTR_SM0_INSTR_Pos (0UL) /*!< SM0_INSTR (Bit 0) */ +#define PIO0_SM0_INSTR_SM0_INSTR_Msk (0xffffUL) /*!< SM0_INSTR (Bitfield-Mask: 0xffff) */ +/* ====================================================== SM0_PINCTRL ====================================================== */ +#define PIO0_SM0_PINCTRL_SIDESET_COUNT_Pos (29UL) /*!< SIDESET_COUNT (Bit 29) */ +#define PIO0_SM0_PINCTRL_SIDESET_COUNT_Msk (0xe0000000UL) /*!< SIDESET_COUNT (Bitfield-Mask: 0x07) */ +#define PIO0_SM0_PINCTRL_SET_COUNT_Pos (26UL) /*!< SET_COUNT (Bit 26) */ +#define PIO0_SM0_PINCTRL_SET_COUNT_Msk (0x1c000000UL) /*!< SET_COUNT (Bitfield-Mask: 0x07) */ +#define PIO0_SM0_PINCTRL_OUT_COUNT_Pos (20UL) /*!< OUT_COUNT (Bit 20) */ +#define PIO0_SM0_PINCTRL_OUT_COUNT_Msk (0x3f00000UL) /*!< OUT_COUNT (Bitfield-Mask: 0x3f) */ +#define PIO0_SM0_PINCTRL_IN_BASE_Pos (15UL) /*!< IN_BASE (Bit 15) */ +#define PIO0_SM0_PINCTRL_IN_BASE_Msk (0xf8000UL) /*!< IN_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM0_PINCTRL_SIDESET_BASE_Pos (10UL) /*!< SIDESET_BASE (Bit 10) */ +#define PIO0_SM0_PINCTRL_SIDESET_BASE_Msk (0x7c00UL) /*!< SIDESET_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM0_PINCTRL_SET_BASE_Pos (5UL) /*!< SET_BASE (Bit 5) */ +#define PIO0_SM0_PINCTRL_SET_BASE_Msk (0x3e0UL) /*!< SET_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM0_PINCTRL_OUT_BASE_Pos (0UL) /*!< OUT_BASE (Bit 0) */ +#define PIO0_SM0_PINCTRL_OUT_BASE_Msk (0x1fUL) /*!< OUT_BASE (Bitfield-Mask: 0x1f) */ +/* ====================================================== SM1_CLKDIV ======================================================= */ +#define PIO0_SM1_CLKDIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define PIO0_SM1_CLKDIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define PIO0_SM1_CLKDIV_FRAC_Pos (8UL) /*!< FRAC (Bit 8) */ +#define PIO0_SM1_CLKDIV_FRAC_Msk (0xff00UL) /*!< FRAC (Bitfield-Mask: 0xff) */ +/* ===================================================== SM1_EXECCTRL ====================================================== */ +#define PIO0_SM1_EXECCTRL_EXEC_STALLED_Pos (31UL) /*!< EXEC_STALLED (Bit 31) */ +#define PIO0_SM1_EXECCTRL_EXEC_STALLED_Msk (0x80000000UL) /*!< EXEC_STALLED (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_EXECCTRL_SIDE_EN_Pos (30UL) /*!< SIDE_EN (Bit 30) */ +#define PIO0_SM1_EXECCTRL_SIDE_EN_Msk (0x40000000UL) /*!< SIDE_EN (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_EXECCTRL_SIDE_PINDIR_Pos (29UL) /*!< SIDE_PINDIR (Bit 29) */ +#define PIO0_SM1_EXECCTRL_SIDE_PINDIR_Msk (0x20000000UL) /*!< SIDE_PINDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_EXECCTRL_JMP_PIN_Pos (24UL) /*!< JMP_PIN (Bit 24) */ +#define PIO0_SM1_EXECCTRL_JMP_PIN_Msk (0x1f000000UL) /*!< JMP_PIN (Bitfield-Mask: 0x1f) */ +#define PIO0_SM1_EXECCTRL_OUT_EN_SEL_Pos (19UL) /*!< OUT_EN_SEL (Bit 19) */ +#define PIO0_SM1_EXECCTRL_OUT_EN_SEL_Msk (0xf80000UL) /*!< OUT_EN_SEL (Bitfield-Mask: 0x1f) */ +#define PIO0_SM1_EXECCTRL_INLINE_OUT_EN_Pos (18UL) /*!< INLINE_OUT_EN (Bit 18) */ +#define PIO0_SM1_EXECCTRL_INLINE_OUT_EN_Msk (0x40000UL) /*!< INLINE_OUT_EN (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_EXECCTRL_OUT_STICKY_Pos (17UL) /*!< OUT_STICKY (Bit 17) */ +#define PIO0_SM1_EXECCTRL_OUT_STICKY_Msk (0x20000UL) /*!< OUT_STICKY (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_EXECCTRL_WRAP_TOP_Pos (12UL) /*!< WRAP_TOP (Bit 12) */ +#define PIO0_SM1_EXECCTRL_WRAP_TOP_Msk (0x1f000UL) /*!< WRAP_TOP (Bitfield-Mask: 0x1f) */ +#define PIO0_SM1_EXECCTRL_WRAP_BOTTOM_Pos (7UL) /*!< WRAP_BOTTOM (Bit 7) */ +#define PIO0_SM1_EXECCTRL_WRAP_BOTTOM_Msk (0xf80UL) /*!< WRAP_BOTTOM (Bitfield-Mask: 0x1f) */ +#define PIO0_SM1_EXECCTRL_STATUS_SEL_Pos (5UL) /*!< STATUS_SEL (Bit 5) */ +#define PIO0_SM1_EXECCTRL_STATUS_SEL_Msk (0x60UL) /*!< STATUS_SEL (Bitfield-Mask: 0x03) */ +#define PIO0_SM1_EXECCTRL_STATUS_N_Pos (0UL) /*!< STATUS_N (Bit 0) */ +#define PIO0_SM1_EXECCTRL_STATUS_N_Msk (0x1fUL) /*!< STATUS_N (Bitfield-Mask: 0x1f) */ +/* ===================================================== SM1_SHIFTCTRL ===================================================== */ +#define PIO0_SM1_SHIFTCTRL_FJOIN_RX_Pos (31UL) /*!< FJOIN_RX (Bit 31) */ +#define PIO0_SM1_SHIFTCTRL_FJOIN_RX_Msk (0x80000000UL) /*!< FJOIN_RX (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_SHIFTCTRL_FJOIN_TX_Pos (30UL) /*!< FJOIN_TX (Bit 30) */ +#define PIO0_SM1_SHIFTCTRL_FJOIN_TX_Msk (0x40000000UL) /*!< FJOIN_TX (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_SHIFTCTRL_PULL_THRESH_Pos (25UL) /*!< PULL_THRESH (Bit 25) */ +#define PIO0_SM1_SHIFTCTRL_PULL_THRESH_Msk (0x3e000000UL) /*!< PULL_THRESH (Bitfield-Mask: 0x1f) */ +#define PIO0_SM1_SHIFTCTRL_PUSH_THRESH_Pos (20UL) /*!< PUSH_THRESH (Bit 20) */ +#define PIO0_SM1_SHIFTCTRL_PUSH_THRESH_Msk (0x1f00000UL) /*!< PUSH_THRESH (Bitfield-Mask: 0x1f) */ +#define PIO0_SM1_SHIFTCTRL_OUT_SHIFTDIR_Pos (19UL) /*!< OUT_SHIFTDIR (Bit 19) */ +#define PIO0_SM1_SHIFTCTRL_OUT_SHIFTDIR_Msk (0x80000UL) /*!< OUT_SHIFTDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_SHIFTCTRL_IN_SHIFTDIR_Pos (18UL) /*!< IN_SHIFTDIR (Bit 18) */ +#define PIO0_SM1_SHIFTCTRL_IN_SHIFTDIR_Msk (0x40000UL) /*!< IN_SHIFTDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_SHIFTCTRL_AUTOPULL_Pos (17UL) /*!< AUTOPULL (Bit 17) */ +#define PIO0_SM1_SHIFTCTRL_AUTOPULL_Msk (0x20000UL) /*!< AUTOPULL (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_SHIFTCTRL_AUTOPUSH_Pos (16UL) /*!< AUTOPUSH (Bit 16) */ +#define PIO0_SM1_SHIFTCTRL_AUTOPUSH_Msk (0x10000UL) /*!< AUTOPUSH (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_SHIFTCTRL_FJOIN_RX_PUT_Pos (15UL) /*!< FJOIN_RX_PUT (Bit 15) */ +#define PIO0_SM1_SHIFTCTRL_FJOIN_RX_PUT_Msk (0x8000UL) /*!< FJOIN_RX_PUT (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_SHIFTCTRL_FJOIN_RX_GET_Pos (14UL) /*!< FJOIN_RX_GET (Bit 14) */ +#define PIO0_SM1_SHIFTCTRL_FJOIN_RX_GET_Msk (0x4000UL) /*!< FJOIN_RX_GET (Bitfield-Mask: 0x01) */ +#define PIO0_SM1_SHIFTCTRL_IN_COUNT_Pos (0UL) /*!< IN_COUNT (Bit 0) */ +#define PIO0_SM1_SHIFTCTRL_IN_COUNT_Msk (0x1fUL) /*!< IN_COUNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= SM1_ADDR ======================================================== */ +#define PIO0_SM1_ADDR_SM1_ADDR_Pos (0UL) /*!< SM1_ADDR (Bit 0) */ +#define PIO0_SM1_ADDR_SM1_ADDR_Msk (0x1fUL) /*!< SM1_ADDR (Bitfield-Mask: 0x1f) */ +/* ======================================================= SM1_INSTR ======================================================= */ +#define PIO0_SM1_INSTR_SM1_INSTR_Pos (0UL) /*!< SM1_INSTR (Bit 0) */ +#define PIO0_SM1_INSTR_SM1_INSTR_Msk (0xffffUL) /*!< SM1_INSTR (Bitfield-Mask: 0xffff) */ +/* ====================================================== SM1_PINCTRL ====================================================== */ +#define PIO0_SM1_PINCTRL_SIDESET_COUNT_Pos (29UL) /*!< SIDESET_COUNT (Bit 29) */ +#define PIO0_SM1_PINCTRL_SIDESET_COUNT_Msk (0xe0000000UL) /*!< SIDESET_COUNT (Bitfield-Mask: 0x07) */ +#define PIO0_SM1_PINCTRL_SET_COUNT_Pos (26UL) /*!< SET_COUNT (Bit 26) */ +#define PIO0_SM1_PINCTRL_SET_COUNT_Msk (0x1c000000UL) /*!< SET_COUNT (Bitfield-Mask: 0x07) */ +#define PIO0_SM1_PINCTRL_OUT_COUNT_Pos (20UL) /*!< OUT_COUNT (Bit 20) */ +#define PIO0_SM1_PINCTRL_OUT_COUNT_Msk (0x3f00000UL) /*!< OUT_COUNT (Bitfield-Mask: 0x3f) */ +#define PIO0_SM1_PINCTRL_IN_BASE_Pos (15UL) /*!< IN_BASE (Bit 15) */ +#define PIO0_SM1_PINCTRL_IN_BASE_Msk (0xf8000UL) /*!< IN_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM1_PINCTRL_SIDESET_BASE_Pos (10UL) /*!< SIDESET_BASE (Bit 10) */ +#define PIO0_SM1_PINCTRL_SIDESET_BASE_Msk (0x7c00UL) /*!< SIDESET_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM1_PINCTRL_SET_BASE_Pos (5UL) /*!< SET_BASE (Bit 5) */ +#define PIO0_SM1_PINCTRL_SET_BASE_Msk (0x3e0UL) /*!< SET_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM1_PINCTRL_OUT_BASE_Pos (0UL) /*!< OUT_BASE (Bit 0) */ +#define PIO0_SM1_PINCTRL_OUT_BASE_Msk (0x1fUL) /*!< OUT_BASE (Bitfield-Mask: 0x1f) */ +/* ====================================================== SM2_CLKDIV ======================================================= */ +#define PIO0_SM2_CLKDIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define PIO0_SM2_CLKDIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define PIO0_SM2_CLKDIV_FRAC_Pos (8UL) /*!< FRAC (Bit 8) */ +#define PIO0_SM2_CLKDIV_FRAC_Msk (0xff00UL) /*!< FRAC (Bitfield-Mask: 0xff) */ +/* ===================================================== SM2_EXECCTRL ====================================================== */ +#define PIO0_SM2_EXECCTRL_EXEC_STALLED_Pos (31UL) /*!< EXEC_STALLED (Bit 31) */ +#define PIO0_SM2_EXECCTRL_EXEC_STALLED_Msk (0x80000000UL) /*!< EXEC_STALLED (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_EXECCTRL_SIDE_EN_Pos (30UL) /*!< SIDE_EN (Bit 30) */ +#define PIO0_SM2_EXECCTRL_SIDE_EN_Msk (0x40000000UL) /*!< SIDE_EN (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_EXECCTRL_SIDE_PINDIR_Pos (29UL) /*!< SIDE_PINDIR (Bit 29) */ +#define PIO0_SM2_EXECCTRL_SIDE_PINDIR_Msk (0x20000000UL) /*!< SIDE_PINDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_EXECCTRL_JMP_PIN_Pos (24UL) /*!< JMP_PIN (Bit 24) */ +#define PIO0_SM2_EXECCTRL_JMP_PIN_Msk (0x1f000000UL) /*!< JMP_PIN (Bitfield-Mask: 0x1f) */ +#define PIO0_SM2_EXECCTRL_OUT_EN_SEL_Pos (19UL) /*!< OUT_EN_SEL (Bit 19) */ +#define PIO0_SM2_EXECCTRL_OUT_EN_SEL_Msk (0xf80000UL) /*!< OUT_EN_SEL (Bitfield-Mask: 0x1f) */ +#define PIO0_SM2_EXECCTRL_INLINE_OUT_EN_Pos (18UL) /*!< INLINE_OUT_EN (Bit 18) */ +#define PIO0_SM2_EXECCTRL_INLINE_OUT_EN_Msk (0x40000UL) /*!< INLINE_OUT_EN (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_EXECCTRL_OUT_STICKY_Pos (17UL) /*!< OUT_STICKY (Bit 17) */ +#define PIO0_SM2_EXECCTRL_OUT_STICKY_Msk (0x20000UL) /*!< OUT_STICKY (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_EXECCTRL_WRAP_TOP_Pos (12UL) /*!< WRAP_TOP (Bit 12) */ +#define PIO0_SM2_EXECCTRL_WRAP_TOP_Msk (0x1f000UL) /*!< WRAP_TOP (Bitfield-Mask: 0x1f) */ +#define PIO0_SM2_EXECCTRL_WRAP_BOTTOM_Pos (7UL) /*!< WRAP_BOTTOM (Bit 7) */ +#define PIO0_SM2_EXECCTRL_WRAP_BOTTOM_Msk (0xf80UL) /*!< WRAP_BOTTOM (Bitfield-Mask: 0x1f) */ +#define PIO0_SM2_EXECCTRL_STATUS_SEL_Pos (5UL) /*!< STATUS_SEL (Bit 5) */ +#define PIO0_SM2_EXECCTRL_STATUS_SEL_Msk (0x60UL) /*!< STATUS_SEL (Bitfield-Mask: 0x03) */ +#define PIO0_SM2_EXECCTRL_STATUS_N_Pos (0UL) /*!< STATUS_N (Bit 0) */ +#define PIO0_SM2_EXECCTRL_STATUS_N_Msk (0x1fUL) /*!< STATUS_N (Bitfield-Mask: 0x1f) */ +/* ===================================================== SM2_SHIFTCTRL ===================================================== */ +#define PIO0_SM2_SHIFTCTRL_FJOIN_RX_Pos (31UL) /*!< FJOIN_RX (Bit 31) */ +#define PIO0_SM2_SHIFTCTRL_FJOIN_RX_Msk (0x80000000UL) /*!< FJOIN_RX (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_SHIFTCTRL_FJOIN_TX_Pos (30UL) /*!< FJOIN_TX (Bit 30) */ +#define PIO0_SM2_SHIFTCTRL_FJOIN_TX_Msk (0x40000000UL) /*!< FJOIN_TX (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_SHIFTCTRL_PULL_THRESH_Pos (25UL) /*!< PULL_THRESH (Bit 25) */ +#define PIO0_SM2_SHIFTCTRL_PULL_THRESH_Msk (0x3e000000UL) /*!< PULL_THRESH (Bitfield-Mask: 0x1f) */ +#define PIO0_SM2_SHIFTCTRL_PUSH_THRESH_Pos (20UL) /*!< PUSH_THRESH (Bit 20) */ +#define PIO0_SM2_SHIFTCTRL_PUSH_THRESH_Msk (0x1f00000UL) /*!< PUSH_THRESH (Bitfield-Mask: 0x1f) */ +#define PIO0_SM2_SHIFTCTRL_OUT_SHIFTDIR_Pos (19UL) /*!< OUT_SHIFTDIR (Bit 19) */ +#define PIO0_SM2_SHIFTCTRL_OUT_SHIFTDIR_Msk (0x80000UL) /*!< OUT_SHIFTDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_SHIFTCTRL_IN_SHIFTDIR_Pos (18UL) /*!< IN_SHIFTDIR (Bit 18) */ +#define PIO0_SM2_SHIFTCTRL_IN_SHIFTDIR_Msk (0x40000UL) /*!< IN_SHIFTDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_SHIFTCTRL_AUTOPULL_Pos (17UL) /*!< AUTOPULL (Bit 17) */ +#define PIO0_SM2_SHIFTCTRL_AUTOPULL_Msk (0x20000UL) /*!< AUTOPULL (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_SHIFTCTRL_AUTOPUSH_Pos (16UL) /*!< AUTOPUSH (Bit 16) */ +#define PIO0_SM2_SHIFTCTRL_AUTOPUSH_Msk (0x10000UL) /*!< AUTOPUSH (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_SHIFTCTRL_FJOIN_RX_PUT_Pos (15UL) /*!< FJOIN_RX_PUT (Bit 15) */ +#define PIO0_SM2_SHIFTCTRL_FJOIN_RX_PUT_Msk (0x8000UL) /*!< FJOIN_RX_PUT (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_SHIFTCTRL_FJOIN_RX_GET_Pos (14UL) /*!< FJOIN_RX_GET (Bit 14) */ +#define PIO0_SM2_SHIFTCTRL_FJOIN_RX_GET_Msk (0x4000UL) /*!< FJOIN_RX_GET (Bitfield-Mask: 0x01) */ +#define PIO0_SM2_SHIFTCTRL_IN_COUNT_Pos (0UL) /*!< IN_COUNT (Bit 0) */ +#define PIO0_SM2_SHIFTCTRL_IN_COUNT_Msk (0x1fUL) /*!< IN_COUNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= SM2_ADDR ======================================================== */ +#define PIO0_SM2_ADDR_SM2_ADDR_Pos (0UL) /*!< SM2_ADDR (Bit 0) */ +#define PIO0_SM2_ADDR_SM2_ADDR_Msk (0x1fUL) /*!< SM2_ADDR (Bitfield-Mask: 0x1f) */ +/* ======================================================= SM2_INSTR ======================================================= */ +#define PIO0_SM2_INSTR_SM2_INSTR_Pos (0UL) /*!< SM2_INSTR (Bit 0) */ +#define PIO0_SM2_INSTR_SM2_INSTR_Msk (0xffffUL) /*!< SM2_INSTR (Bitfield-Mask: 0xffff) */ +/* ====================================================== SM2_PINCTRL ====================================================== */ +#define PIO0_SM2_PINCTRL_SIDESET_COUNT_Pos (29UL) /*!< SIDESET_COUNT (Bit 29) */ +#define PIO0_SM2_PINCTRL_SIDESET_COUNT_Msk (0xe0000000UL) /*!< SIDESET_COUNT (Bitfield-Mask: 0x07) */ +#define PIO0_SM2_PINCTRL_SET_COUNT_Pos (26UL) /*!< SET_COUNT (Bit 26) */ +#define PIO0_SM2_PINCTRL_SET_COUNT_Msk (0x1c000000UL) /*!< SET_COUNT (Bitfield-Mask: 0x07) */ +#define PIO0_SM2_PINCTRL_OUT_COUNT_Pos (20UL) /*!< OUT_COUNT (Bit 20) */ +#define PIO0_SM2_PINCTRL_OUT_COUNT_Msk (0x3f00000UL) /*!< OUT_COUNT (Bitfield-Mask: 0x3f) */ +#define PIO0_SM2_PINCTRL_IN_BASE_Pos (15UL) /*!< IN_BASE (Bit 15) */ +#define PIO0_SM2_PINCTRL_IN_BASE_Msk (0xf8000UL) /*!< IN_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM2_PINCTRL_SIDESET_BASE_Pos (10UL) /*!< SIDESET_BASE (Bit 10) */ +#define PIO0_SM2_PINCTRL_SIDESET_BASE_Msk (0x7c00UL) /*!< SIDESET_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM2_PINCTRL_SET_BASE_Pos (5UL) /*!< SET_BASE (Bit 5) */ +#define PIO0_SM2_PINCTRL_SET_BASE_Msk (0x3e0UL) /*!< SET_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM2_PINCTRL_OUT_BASE_Pos (0UL) /*!< OUT_BASE (Bit 0) */ +#define PIO0_SM2_PINCTRL_OUT_BASE_Msk (0x1fUL) /*!< OUT_BASE (Bitfield-Mask: 0x1f) */ +/* ====================================================== SM3_CLKDIV ======================================================= */ +#define PIO0_SM3_CLKDIV_INT_Pos (16UL) /*!< INT (Bit 16) */ +#define PIO0_SM3_CLKDIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */ +#define PIO0_SM3_CLKDIV_FRAC_Pos (8UL) /*!< FRAC (Bit 8) */ +#define PIO0_SM3_CLKDIV_FRAC_Msk (0xff00UL) /*!< FRAC (Bitfield-Mask: 0xff) */ +/* ===================================================== SM3_EXECCTRL ====================================================== */ +#define PIO0_SM3_EXECCTRL_EXEC_STALLED_Pos (31UL) /*!< EXEC_STALLED (Bit 31) */ +#define PIO0_SM3_EXECCTRL_EXEC_STALLED_Msk (0x80000000UL) /*!< EXEC_STALLED (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_EXECCTRL_SIDE_EN_Pos (30UL) /*!< SIDE_EN (Bit 30) */ +#define PIO0_SM3_EXECCTRL_SIDE_EN_Msk (0x40000000UL) /*!< SIDE_EN (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_EXECCTRL_SIDE_PINDIR_Pos (29UL) /*!< SIDE_PINDIR (Bit 29) */ +#define PIO0_SM3_EXECCTRL_SIDE_PINDIR_Msk (0x20000000UL) /*!< SIDE_PINDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_EXECCTRL_JMP_PIN_Pos (24UL) /*!< JMP_PIN (Bit 24) */ +#define PIO0_SM3_EXECCTRL_JMP_PIN_Msk (0x1f000000UL) /*!< JMP_PIN (Bitfield-Mask: 0x1f) */ +#define PIO0_SM3_EXECCTRL_OUT_EN_SEL_Pos (19UL) /*!< OUT_EN_SEL (Bit 19) */ +#define PIO0_SM3_EXECCTRL_OUT_EN_SEL_Msk (0xf80000UL) /*!< OUT_EN_SEL (Bitfield-Mask: 0x1f) */ +#define PIO0_SM3_EXECCTRL_INLINE_OUT_EN_Pos (18UL) /*!< INLINE_OUT_EN (Bit 18) */ +#define PIO0_SM3_EXECCTRL_INLINE_OUT_EN_Msk (0x40000UL) /*!< INLINE_OUT_EN (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_EXECCTRL_OUT_STICKY_Pos (17UL) /*!< OUT_STICKY (Bit 17) */ +#define PIO0_SM3_EXECCTRL_OUT_STICKY_Msk (0x20000UL) /*!< OUT_STICKY (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_EXECCTRL_WRAP_TOP_Pos (12UL) /*!< WRAP_TOP (Bit 12) */ +#define PIO0_SM3_EXECCTRL_WRAP_TOP_Msk (0x1f000UL) /*!< WRAP_TOP (Bitfield-Mask: 0x1f) */ +#define PIO0_SM3_EXECCTRL_WRAP_BOTTOM_Pos (7UL) /*!< WRAP_BOTTOM (Bit 7) */ +#define PIO0_SM3_EXECCTRL_WRAP_BOTTOM_Msk (0xf80UL) /*!< WRAP_BOTTOM (Bitfield-Mask: 0x1f) */ +#define PIO0_SM3_EXECCTRL_STATUS_SEL_Pos (5UL) /*!< STATUS_SEL (Bit 5) */ +#define PIO0_SM3_EXECCTRL_STATUS_SEL_Msk (0x60UL) /*!< STATUS_SEL (Bitfield-Mask: 0x03) */ +#define PIO0_SM3_EXECCTRL_STATUS_N_Pos (0UL) /*!< STATUS_N (Bit 0) */ +#define PIO0_SM3_EXECCTRL_STATUS_N_Msk (0x1fUL) /*!< STATUS_N (Bitfield-Mask: 0x1f) */ +/* ===================================================== SM3_SHIFTCTRL ===================================================== */ +#define PIO0_SM3_SHIFTCTRL_FJOIN_RX_Pos (31UL) /*!< FJOIN_RX (Bit 31) */ +#define PIO0_SM3_SHIFTCTRL_FJOIN_RX_Msk (0x80000000UL) /*!< FJOIN_RX (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_SHIFTCTRL_FJOIN_TX_Pos (30UL) /*!< FJOIN_TX (Bit 30) */ +#define PIO0_SM3_SHIFTCTRL_FJOIN_TX_Msk (0x40000000UL) /*!< FJOIN_TX (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_SHIFTCTRL_PULL_THRESH_Pos (25UL) /*!< PULL_THRESH (Bit 25) */ +#define PIO0_SM3_SHIFTCTRL_PULL_THRESH_Msk (0x3e000000UL) /*!< PULL_THRESH (Bitfield-Mask: 0x1f) */ +#define PIO0_SM3_SHIFTCTRL_PUSH_THRESH_Pos (20UL) /*!< PUSH_THRESH (Bit 20) */ +#define PIO0_SM3_SHIFTCTRL_PUSH_THRESH_Msk (0x1f00000UL) /*!< PUSH_THRESH (Bitfield-Mask: 0x1f) */ +#define PIO0_SM3_SHIFTCTRL_OUT_SHIFTDIR_Pos (19UL) /*!< OUT_SHIFTDIR (Bit 19) */ +#define PIO0_SM3_SHIFTCTRL_OUT_SHIFTDIR_Msk (0x80000UL) /*!< OUT_SHIFTDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_SHIFTCTRL_IN_SHIFTDIR_Pos (18UL) /*!< IN_SHIFTDIR (Bit 18) */ +#define PIO0_SM3_SHIFTCTRL_IN_SHIFTDIR_Msk (0x40000UL) /*!< IN_SHIFTDIR (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_SHIFTCTRL_AUTOPULL_Pos (17UL) /*!< AUTOPULL (Bit 17) */ +#define PIO0_SM3_SHIFTCTRL_AUTOPULL_Msk (0x20000UL) /*!< AUTOPULL (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_SHIFTCTRL_AUTOPUSH_Pos (16UL) /*!< AUTOPUSH (Bit 16) */ +#define PIO0_SM3_SHIFTCTRL_AUTOPUSH_Msk (0x10000UL) /*!< AUTOPUSH (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_SHIFTCTRL_FJOIN_RX_PUT_Pos (15UL) /*!< FJOIN_RX_PUT (Bit 15) */ +#define PIO0_SM3_SHIFTCTRL_FJOIN_RX_PUT_Msk (0x8000UL) /*!< FJOIN_RX_PUT (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_SHIFTCTRL_FJOIN_RX_GET_Pos (14UL) /*!< FJOIN_RX_GET (Bit 14) */ +#define PIO0_SM3_SHIFTCTRL_FJOIN_RX_GET_Msk (0x4000UL) /*!< FJOIN_RX_GET (Bitfield-Mask: 0x01) */ +#define PIO0_SM3_SHIFTCTRL_IN_COUNT_Pos (0UL) /*!< IN_COUNT (Bit 0) */ +#define PIO0_SM3_SHIFTCTRL_IN_COUNT_Msk (0x1fUL) /*!< IN_COUNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= SM3_ADDR ======================================================== */ +#define PIO0_SM3_ADDR_SM3_ADDR_Pos (0UL) /*!< SM3_ADDR (Bit 0) */ +#define PIO0_SM3_ADDR_SM3_ADDR_Msk (0x1fUL) /*!< SM3_ADDR (Bitfield-Mask: 0x1f) */ +/* ======================================================= SM3_INSTR ======================================================= */ +#define PIO0_SM3_INSTR_SM3_INSTR_Pos (0UL) /*!< SM3_INSTR (Bit 0) */ +#define PIO0_SM3_INSTR_SM3_INSTR_Msk (0xffffUL) /*!< SM3_INSTR (Bitfield-Mask: 0xffff) */ +/* ====================================================== SM3_PINCTRL ====================================================== */ +#define PIO0_SM3_PINCTRL_SIDESET_COUNT_Pos (29UL) /*!< SIDESET_COUNT (Bit 29) */ +#define PIO0_SM3_PINCTRL_SIDESET_COUNT_Msk (0xe0000000UL) /*!< SIDESET_COUNT (Bitfield-Mask: 0x07) */ +#define PIO0_SM3_PINCTRL_SET_COUNT_Pos (26UL) /*!< SET_COUNT (Bit 26) */ +#define PIO0_SM3_PINCTRL_SET_COUNT_Msk (0x1c000000UL) /*!< SET_COUNT (Bitfield-Mask: 0x07) */ +#define PIO0_SM3_PINCTRL_OUT_COUNT_Pos (20UL) /*!< OUT_COUNT (Bit 20) */ +#define PIO0_SM3_PINCTRL_OUT_COUNT_Msk (0x3f00000UL) /*!< OUT_COUNT (Bitfield-Mask: 0x3f) */ +#define PIO0_SM3_PINCTRL_IN_BASE_Pos (15UL) /*!< IN_BASE (Bit 15) */ +#define PIO0_SM3_PINCTRL_IN_BASE_Msk (0xf8000UL) /*!< IN_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM3_PINCTRL_SIDESET_BASE_Pos (10UL) /*!< SIDESET_BASE (Bit 10) */ +#define PIO0_SM3_PINCTRL_SIDESET_BASE_Msk (0x7c00UL) /*!< SIDESET_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM3_PINCTRL_SET_BASE_Pos (5UL) /*!< SET_BASE (Bit 5) */ +#define PIO0_SM3_PINCTRL_SET_BASE_Msk (0x3e0UL) /*!< SET_BASE (Bitfield-Mask: 0x1f) */ +#define PIO0_SM3_PINCTRL_OUT_BASE_Pos (0UL) /*!< OUT_BASE (Bit 0) */ +#define PIO0_SM3_PINCTRL_OUT_BASE_Msk (0x1fUL) /*!< OUT_BASE (Bitfield-Mask: 0x1f) */ +/* ===================================================== RXF0_PUTGET0 ====================================================== */ +#define PIO0_RXF0_PUTGET0_RXF0_PUTGET0_Pos (0UL) /*!< RXF0_PUTGET0 (Bit 0) */ +#define PIO0_RXF0_PUTGET0_RXF0_PUTGET0_Msk (0xffffffffUL) /*!< RXF0_PUTGET0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF0_PUTGET1 ====================================================== */ +#define PIO0_RXF0_PUTGET1_RXF0_PUTGET1_Pos (0UL) /*!< RXF0_PUTGET1 (Bit 0) */ +#define PIO0_RXF0_PUTGET1_RXF0_PUTGET1_Msk (0xffffffffUL) /*!< RXF0_PUTGET1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF0_PUTGET2 ====================================================== */ +#define PIO0_RXF0_PUTGET2_RXF0_PUTGET2_Pos (0UL) /*!< RXF0_PUTGET2 (Bit 0) */ +#define PIO0_RXF0_PUTGET2_RXF0_PUTGET2_Msk (0xffffffffUL) /*!< RXF0_PUTGET2 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF0_PUTGET3 ====================================================== */ +#define PIO0_RXF0_PUTGET3_RXF0_PUTGET3_Pos (0UL) /*!< RXF0_PUTGET3 (Bit 0) */ +#define PIO0_RXF0_PUTGET3_RXF0_PUTGET3_Msk (0xffffffffUL) /*!< RXF0_PUTGET3 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF1_PUTGET0 ====================================================== */ +#define PIO0_RXF1_PUTGET0_RXF1_PUTGET0_Pos (0UL) /*!< RXF1_PUTGET0 (Bit 0) */ +#define PIO0_RXF1_PUTGET0_RXF1_PUTGET0_Msk (0xffffffffUL) /*!< RXF1_PUTGET0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF1_PUTGET1 ====================================================== */ +#define PIO0_RXF1_PUTGET1_RXF1_PUTGET1_Pos (0UL) /*!< RXF1_PUTGET1 (Bit 0) */ +#define PIO0_RXF1_PUTGET1_RXF1_PUTGET1_Msk (0xffffffffUL) /*!< RXF1_PUTGET1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF1_PUTGET2 ====================================================== */ +#define PIO0_RXF1_PUTGET2_RXF1_PUTGET2_Pos (0UL) /*!< RXF1_PUTGET2 (Bit 0) */ +#define PIO0_RXF1_PUTGET2_RXF1_PUTGET2_Msk (0xffffffffUL) /*!< RXF1_PUTGET2 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF1_PUTGET3 ====================================================== */ +#define PIO0_RXF1_PUTGET3_RXF1_PUTGET3_Pos (0UL) /*!< RXF1_PUTGET3 (Bit 0) */ +#define PIO0_RXF1_PUTGET3_RXF1_PUTGET3_Msk (0xffffffffUL) /*!< RXF1_PUTGET3 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF2_PUTGET0 ====================================================== */ +#define PIO0_RXF2_PUTGET0_RXF2_PUTGET0_Pos (0UL) /*!< RXF2_PUTGET0 (Bit 0) */ +#define PIO0_RXF2_PUTGET0_RXF2_PUTGET0_Msk (0xffffffffUL) /*!< RXF2_PUTGET0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF2_PUTGET1 ====================================================== */ +#define PIO0_RXF2_PUTGET1_RXF2_PUTGET1_Pos (0UL) /*!< RXF2_PUTGET1 (Bit 0) */ +#define PIO0_RXF2_PUTGET1_RXF2_PUTGET1_Msk (0xffffffffUL) /*!< RXF2_PUTGET1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF2_PUTGET2 ====================================================== */ +#define PIO0_RXF2_PUTGET2_RXF2_PUTGET2_Pos (0UL) /*!< RXF2_PUTGET2 (Bit 0) */ +#define PIO0_RXF2_PUTGET2_RXF2_PUTGET2_Msk (0xffffffffUL) /*!< RXF2_PUTGET2 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF2_PUTGET3 ====================================================== */ +#define PIO0_RXF2_PUTGET3_RXF2_PUTGET3_Pos (0UL) /*!< RXF2_PUTGET3 (Bit 0) */ +#define PIO0_RXF2_PUTGET3_RXF2_PUTGET3_Msk (0xffffffffUL) /*!< RXF2_PUTGET3 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF3_PUTGET0 ====================================================== */ +#define PIO0_RXF3_PUTGET0_RXF3_PUTGET0_Pos (0UL) /*!< RXF3_PUTGET0 (Bit 0) */ +#define PIO0_RXF3_PUTGET0_RXF3_PUTGET0_Msk (0xffffffffUL) /*!< RXF3_PUTGET0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF3_PUTGET1 ====================================================== */ +#define PIO0_RXF3_PUTGET1_RXF3_PUTGET1_Pos (0UL) /*!< RXF3_PUTGET1 (Bit 0) */ +#define PIO0_RXF3_PUTGET1_RXF3_PUTGET1_Msk (0xffffffffUL) /*!< RXF3_PUTGET1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF3_PUTGET2 ====================================================== */ +#define PIO0_RXF3_PUTGET2_RXF3_PUTGET2_Pos (0UL) /*!< RXF3_PUTGET2 (Bit 0) */ +#define PIO0_RXF3_PUTGET2_RXF3_PUTGET2_Msk (0xffffffffUL) /*!< RXF3_PUTGET2 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RXF3_PUTGET3 ====================================================== */ +#define PIO0_RXF3_PUTGET3_RXF3_PUTGET3_Pos (0UL) /*!< RXF3_PUTGET3 (Bit 0) */ +#define PIO0_RXF3_PUTGET3_RXF3_PUTGET3_Msk (0xffffffffUL) /*!< RXF3_PUTGET3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GPIOBASE ======================================================== */ +#define PIO0_GPIOBASE_GPIOBASE_Pos (4UL) /*!< GPIOBASE (Bit 4) */ +#define PIO0_GPIOBASE_GPIOBASE_Msk (0x10UL) /*!< GPIOBASE (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR ========================================================== */ +#define PIO0_INTR_SM7_Pos (15UL) /*!< SM7 (Bit 15) */ +#define PIO0_INTR_SM7_Msk (0x8000UL) /*!< SM7 (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM6_Pos (14UL) /*!< SM6 (Bit 14) */ +#define PIO0_INTR_SM6_Msk (0x4000UL) /*!< SM6 (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM5_Pos (13UL) /*!< SM5 (Bit 13) */ +#define PIO0_INTR_SM5_Msk (0x2000UL) /*!< SM5 (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM4_Pos (12UL) /*!< SM4 (Bit 12) */ +#define PIO0_INTR_SM4_Msk (0x1000UL) /*!< SM4 (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM3_Pos (11UL) /*!< SM3 (Bit 11) */ +#define PIO0_INTR_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM2_Pos (10UL) /*!< SM2 (Bit 10) */ +#define PIO0_INTR_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM1_Pos (9UL) /*!< SM1 (Bit 9) */ +#define PIO0_INTR_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM0_Pos (8UL) /*!< SM0 (Bit 8) */ +#define PIO0_INTR_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */ +#define PIO0_INTR_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */ +#define PIO0_INTR_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */ +#define PIO0_INTR_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */ +#define PIO0_INTR_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */ +#define PIO0_INTR_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */ +#define PIO0_INTR_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */ +#define PIO0_INTR_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_INTR_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */ +#define PIO0_INTR_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ0_INTE ======================================================= */ +#define PIO0_IRQ0_INTE_SM7_Pos (15UL) /*!< SM7 (Bit 15) */ +#define PIO0_IRQ0_INTE_SM7_Msk (0x8000UL) /*!< SM7 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM6_Pos (14UL) /*!< SM6 (Bit 14) */ +#define PIO0_IRQ0_INTE_SM6_Msk (0x4000UL) /*!< SM6 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM5_Pos (13UL) /*!< SM5 (Bit 13) */ +#define PIO0_IRQ0_INTE_SM5_Msk (0x2000UL) /*!< SM5 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM4_Pos (12UL) /*!< SM4 (Bit 12) */ +#define PIO0_IRQ0_INTE_SM4_Msk (0x1000UL) /*!< SM4 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM3_Pos (11UL) /*!< SM3 (Bit 11) */ +#define PIO0_IRQ0_INTE_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM2_Pos (10UL) /*!< SM2 (Bit 10) */ +#define PIO0_IRQ0_INTE_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM1_Pos (9UL) /*!< SM1 (Bit 9) */ +#define PIO0_IRQ0_INTE_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM0_Pos (8UL) /*!< SM0 (Bit 8) */ +#define PIO0_IRQ0_INTE_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */ +#define PIO0_IRQ0_INTE_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */ +#define PIO0_IRQ0_INTE_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */ +#define PIO0_IRQ0_INTE_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */ +#define PIO0_IRQ0_INTE_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */ +#define PIO0_IRQ0_INTE_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */ +#define PIO0_IRQ0_INTE_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */ +#define PIO0_IRQ0_INTE_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTE_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */ +#define PIO0_IRQ0_INTE_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ0_INTF ======================================================= */ +#define PIO0_IRQ0_INTF_SM7_Pos (15UL) /*!< SM7 (Bit 15) */ +#define PIO0_IRQ0_INTF_SM7_Msk (0x8000UL) /*!< SM7 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM6_Pos (14UL) /*!< SM6 (Bit 14) */ +#define PIO0_IRQ0_INTF_SM6_Msk (0x4000UL) /*!< SM6 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM5_Pos (13UL) /*!< SM5 (Bit 13) */ +#define PIO0_IRQ0_INTF_SM5_Msk (0x2000UL) /*!< SM5 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM4_Pos (12UL) /*!< SM4 (Bit 12) */ +#define PIO0_IRQ0_INTF_SM4_Msk (0x1000UL) /*!< SM4 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM3_Pos (11UL) /*!< SM3 (Bit 11) */ +#define PIO0_IRQ0_INTF_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM2_Pos (10UL) /*!< SM2 (Bit 10) */ +#define PIO0_IRQ0_INTF_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM1_Pos (9UL) /*!< SM1 (Bit 9) */ +#define PIO0_IRQ0_INTF_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM0_Pos (8UL) /*!< SM0 (Bit 8) */ +#define PIO0_IRQ0_INTF_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */ +#define PIO0_IRQ0_INTF_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */ +#define PIO0_IRQ0_INTF_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */ +#define PIO0_IRQ0_INTF_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */ +#define PIO0_IRQ0_INTF_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */ +#define PIO0_IRQ0_INTF_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */ +#define PIO0_IRQ0_INTF_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */ +#define PIO0_IRQ0_INTF_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTF_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */ +#define PIO0_IRQ0_INTF_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ0_INTS ======================================================= */ +#define PIO0_IRQ0_INTS_SM7_Pos (15UL) /*!< SM7 (Bit 15) */ +#define PIO0_IRQ0_INTS_SM7_Msk (0x8000UL) /*!< SM7 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM6_Pos (14UL) /*!< SM6 (Bit 14) */ +#define PIO0_IRQ0_INTS_SM6_Msk (0x4000UL) /*!< SM6 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM5_Pos (13UL) /*!< SM5 (Bit 13) */ +#define PIO0_IRQ0_INTS_SM5_Msk (0x2000UL) /*!< SM5 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM4_Pos (12UL) /*!< SM4 (Bit 12) */ +#define PIO0_IRQ0_INTS_SM4_Msk (0x1000UL) /*!< SM4 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM3_Pos (11UL) /*!< SM3 (Bit 11) */ +#define PIO0_IRQ0_INTS_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM2_Pos (10UL) /*!< SM2 (Bit 10) */ +#define PIO0_IRQ0_INTS_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM1_Pos (9UL) /*!< SM1 (Bit 9) */ +#define PIO0_IRQ0_INTS_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM0_Pos (8UL) /*!< SM0 (Bit 8) */ +#define PIO0_IRQ0_INTS_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */ +#define PIO0_IRQ0_INTS_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */ +#define PIO0_IRQ0_INTS_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */ +#define PIO0_IRQ0_INTS_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */ +#define PIO0_IRQ0_INTS_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */ +#define PIO0_IRQ0_INTS_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */ +#define PIO0_IRQ0_INTS_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */ +#define PIO0_IRQ0_INTS_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ0_INTS_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */ +#define PIO0_IRQ0_INTS_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ1_INTE ======================================================= */ +#define PIO0_IRQ1_INTE_SM7_Pos (15UL) /*!< SM7 (Bit 15) */ +#define PIO0_IRQ1_INTE_SM7_Msk (0x8000UL) /*!< SM7 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM6_Pos (14UL) /*!< SM6 (Bit 14) */ +#define PIO0_IRQ1_INTE_SM6_Msk (0x4000UL) /*!< SM6 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM5_Pos (13UL) /*!< SM5 (Bit 13) */ +#define PIO0_IRQ1_INTE_SM5_Msk (0x2000UL) /*!< SM5 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM4_Pos (12UL) /*!< SM4 (Bit 12) */ +#define PIO0_IRQ1_INTE_SM4_Msk (0x1000UL) /*!< SM4 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM3_Pos (11UL) /*!< SM3 (Bit 11) */ +#define PIO0_IRQ1_INTE_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM2_Pos (10UL) /*!< SM2 (Bit 10) */ +#define PIO0_IRQ1_INTE_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM1_Pos (9UL) /*!< SM1 (Bit 9) */ +#define PIO0_IRQ1_INTE_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM0_Pos (8UL) /*!< SM0 (Bit 8) */ +#define PIO0_IRQ1_INTE_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */ +#define PIO0_IRQ1_INTE_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */ +#define PIO0_IRQ1_INTE_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */ +#define PIO0_IRQ1_INTE_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */ +#define PIO0_IRQ1_INTE_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */ +#define PIO0_IRQ1_INTE_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */ +#define PIO0_IRQ1_INTE_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */ +#define PIO0_IRQ1_INTE_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTE_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */ +#define PIO0_IRQ1_INTE_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ1_INTF ======================================================= */ +#define PIO0_IRQ1_INTF_SM7_Pos (15UL) /*!< SM7 (Bit 15) */ +#define PIO0_IRQ1_INTF_SM7_Msk (0x8000UL) /*!< SM7 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM6_Pos (14UL) /*!< SM6 (Bit 14) */ +#define PIO0_IRQ1_INTF_SM6_Msk (0x4000UL) /*!< SM6 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM5_Pos (13UL) /*!< SM5 (Bit 13) */ +#define PIO0_IRQ1_INTF_SM5_Msk (0x2000UL) /*!< SM5 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM4_Pos (12UL) /*!< SM4 (Bit 12) */ +#define PIO0_IRQ1_INTF_SM4_Msk (0x1000UL) /*!< SM4 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM3_Pos (11UL) /*!< SM3 (Bit 11) */ +#define PIO0_IRQ1_INTF_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM2_Pos (10UL) /*!< SM2 (Bit 10) */ +#define PIO0_IRQ1_INTF_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM1_Pos (9UL) /*!< SM1 (Bit 9) */ +#define PIO0_IRQ1_INTF_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM0_Pos (8UL) /*!< SM0 (Bit 8) */ +#define PIO0_IRQ1_INTF_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */ +#define PIO0_IRQ1_INTF_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */ +#define PIO0_IRQ1_INTF_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */ +#define PIO0_IRQ1_INTF_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */ +#define PIO0_IRQ1_INTF_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */ +#define PIO0_IRQ1_INTF_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */ +#define PIO0_IRQ1_INTF_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */ +#define PIO0_IRQ1_INTF_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTF_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */ +#define PIO0_IRQ1_INTF_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */ +/* ======================================================= IRQ1_INTS ======================================================= */ +#define PIO0_IRQ1_INTS_SM7_Pos (15UL) /*!< SM7 (Bit 15) */ +#define PIO0_IRQ1_INTS_SM7_Msk (0x8000UL) /*!< SM7 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM6_Pos (14UL) /*!< SM6 (Bit 14) */ +#define PIO0_IRQ1_INTS_SM6_Msk (0x4000UL) /*!< SM6 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM5_Pos (13UL) /*!< SM5 (Bit 13) */ +#define PIO0_IRQ1_INTS_SM5_Msk (0x2000UL) /*!< SM5 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM4_Pos (12UL) /*!< SM4 (Bit 12) */ +#define PIO0_IRQ1_INTS_SM4_Msk (0x1000UL) /*!< SM4 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM3_Pos (11UL) /*!< SM3 (Bit 11) */ +#define PIO0_IRQ1_INTS_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM2_Pos (10UL) /*!< SM2 (Bit 10) */ +#define PIO0_IRQ1_INTS_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM1_Pos (9UL) /*!< SM1 (Bit 9) */ +#define PIO0_IRQ1_INTS_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM0_Pos (8UL) /*!< SM0 (Bit 8) */ +#define PIO0_IRQ1_INTS_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */ +#define PIO0_IRQ1_INTS_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */ +#define PIO0_IRQ1_INTS_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */ +#define PIO0_IRQ1_INTS_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */ +#define PIO0_IRQ1_INTS_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */ +#define PIO0_IRQ1_INTS_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */ +#define PIO0_IRQ1_INTS_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */ +#define PIO0_IRQ1_INTS_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */ +#define PIO0_IRQ1_INTS_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */ +#define PIO0_IRQ1_INTS_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ BUSCTRL ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BUS_PRIORITY ====================================================== */ +#define BUSCTRL_BUS_PRIORITY_DMA_W_Pos (12UL) /*!< DMA_W (Bit 12) */ +#define BUSCTRL_BUS_PRIORITY_DMA_W_Msk (0x1000UL) /*!< DMA_W (Bitfield-Mask: 0x01) */ +#define BUSCTRL_BUS_PRIORITY_DMA_R_Pos (8UL) /*!< DMA_R (Bit 8) */ +#define BUSCTRL_BUS_PRIORITY_DMA_R_Msk (0x100UL) /*!< DMA_R (Bitfield-Mask: 0x01) */ +#define BUSCTRL_BUS_PRIORITY_PROC1_Pos (4UL) /*!< PROC1 (Bit 4) */ +#define BUSCTRL_BUS_PRIORITY_PROC1_Msk (0x10UL) /*!< PROC1 (Bitfield-Mask: 0x01) */ +#define BUSCTRL_BUS_PRIORITY_PROC0_Pos (0UL) /*!< PROC0 (Bit 0) */ +#define BUSCTRL_BUS_PRIORITY_PROC0_Msk (0x1UL) /*!< PROC0 (Bitfield-Mask: 0x01) */ +/* =================================================== BUS_PRIORITY_ACK ==================================================== */ +#define BUSCTRL_BUS_PRIORITY_ACK_BUS_PRIORITY_ACK_Pos (0UL) /*!< BUS_PRIORITY_ACK (Bit 0) */ +#define BUSCTRL_BUS_PRIORITY_ACK_BUS_PRIORITY_ACK_Msk (0x1UL) /*!< BUS_PRIORITY_ACK (Bitfield-Mask: 0x01) */ +/* ====================================================== PERFCTR_EN ======================================================= */ +#define BUSCTRL_PERFCTR_EN_PERFCTR_EN_Pos (0UL) /*!< PERFCTR_EN (Bit 0) */ +#define BUSCTRL_PERFCTR_EN_PERFCTR_EN_Msk (0x1UL) /*!< PERFCTR_EN (Bitfield-Mask: 0x01) */ +/* ======================================================= PERFCTR0 ======================================================== */ +#define BUSCTRL_PERFCTR0_PERFCTR0_Pos (0UL) /*!< PERFCTR0 (Bit 0) */ +#define BUSCTRL_PERFCTR0_PERFCTR0_Msk (0xffffffUL) /*!< PERFCTR0 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= PERFSEL0 ======================================================== */ +#define BUSCTRL_PERFSEL0_PERFSEL0_Pos (0UL) /*!< PERFSEL0 (Bit 0) */ +#define BUSCTRL_PERFSEL0_PERFSEL0_Msk (0x7fUL) /*!< PERFSEL0 (Bitfield-Mask: 0x7f) */ +/* ======================================================= PERFCTR1 ======================================================== */ +#define BUSCTRL_PERFCTR1_PERFCTR1_Pos (0UL) /*!< PERFCTR1 (Bit 0) */ +#define BUSCTRL_PERFCTR1_PERFCTR1_Msk (0xffffffUL) /*!< PERFCTR1 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= PERFSEL1 ======================================================== */ +#define BUSCTRL_PERFSEL1_PERFSEL1_Pos (0UL) /*!< PERFSEL1 (Bit 0) */ +#define BUSCTRL_PERFSEL1_PERFSEL1_Msk (0x7fUL) /*!< PERFSEL1 (Bitfield-Mask: 0x7f) */ +/* ======================================================= PERFCTR2 ======================================================== */ +#define BUSCTRL_PERFCTR2_PERFCTR2_Pos (0UL) /*!< PERFCTR2 (Bit 0) */ +#define BUSCTRL_PERFCTR2_PERFCTR2_Msk (0xffffffUL) /*!< PERFCTR2 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= PERFSEL2 ======================================================== */ +#define BUSCTRL_PERFSEL2_PERFSEL2_Pos (0UL) /*!< PERFSEL2 (Bit 0) */ +#define BUSCTRL_PERFSEL2_PERFSEL2_Msk (0x7fUL) /*!< PERFSEL2 (Bitfield-Mask: 0x7f) */ +/* ======================================================= PERFCTR3 ======================================================== */ +#define BUSCTRL_PERFCTR3_PERFCTR3_Pos (0UL) /*!< PERFCTR3 (Bit 0) */ +#define BUSCTRL_PERFCTR3_PERFCTR3_Msk (0xffffffUL) /*!< PERFCTR3 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= PERFSEL3 ======================================================== */ +#define BUSCTRL_PERFSEL3_PERFSEL3_Pos (0UL) /*!< PERFSEL3 (Bit 0) */ +#define BUSCTRL_PERFSEL3_PERFSEL3_Msk (0x7fUL) /*!< PERFSEL3 (Bitfield-Mask: 0x7f) */ + + +/* =========================================================================================================================== */ +/* ================ SIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CPUID ========================================================= */ +#define SIO_CPUID_CPUID_Pos (0UL) /*!< CPUID (Bit 0) */ +#define SIO_CPUID_CPUID_Msk (0xffffffffUL) /*!< CPUID (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GPIO_IN ======================================================== */ +#define SIO_GPIO_IN_GPIO_IN_Pos (0UL) /*!< GPIO_IN (Bit 0) */ +#define SIO_GPIO_IN_GPIO_IN_Msk (0xffffffffUL) /*!< GPIO_IN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GPIO_HI_IN ======================================================= */ +#define SIO_GPIO_HI_IN_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SIO_GPIO_HI_IN_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SIO_GPIO_HI_IN_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SIO_GPIO_HI_IN_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_IN_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SIO_GPIO_HI_IN_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_IN_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SIO_GPIO_HI_IN_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_IN_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SIO_GPIO_HI_IN_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_IN_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SIO_GPIO_HI_IN_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ======================================================= GPIO_OUT ======================================================== */ +#define SIO_GPIO_OUT_GPIO_OUT_Pos (0UL) /*!< GPIO_OUT (Bit 0) */ +#define SIO_GPIO_OUT_GPIO_OUT_Msk (0xffffffffUL) /*!< GPIO_OUT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GPIO_HI_OUT ====================================================== */ +#define SIO_GPIO_HI_OUT_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SIO_GPIO_HI_OUT_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SIO_GPIO_HI_OUT_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SIO_GPIO_HI_OUT_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SIO_GPIO_HI_OUT_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SIO_GPIO_HI_OUT_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SIO_GPIO_HI_OUT_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SIO_GPIO_HI_OUT_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ===================================================== GPIO_OUT_SET ====================================================== */ +#define SIO_GPIO_OUT_SET_GPIO_OUT_SET_Pos (0UL) /*!< GPIO_OUT_SET (Bit 0) */ +#define SIO_GPIO_OUT_SET_GPIO_OUT_SET_Msk (0xffffffffUL) /*!< GPIO_OUT_SET (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== GPIO_HI_OUT_SET ==================================================== */ +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_SET_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SIO_GPIO_HI_OUT_SET_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_SET_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SIO_GPIO_HI_OUT_SET_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_SET_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SIO_GPIO_HI_OUT_SET_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ===================================================== GPIO_OUT_CLR ====================================================== */ +#define SIO_GPIO_OUT_CLR_GPIO_OUT_CLR_Pos (0UL) /*!< GPIO_OUT_CLR (Bit 0) */ +#define SIO_GPIO_OUT_CLR_GPIO_OUT_CLR_Msk (0xffffffffUL) /*!< GPIO_OUT_CLR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== GPIO_HI_OUT_CLR ==================================================== */ +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_CLR_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SIO_GPIO_HI_OUT_CLR_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_CLR_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SIO_GPIO_HI_OUT_CLR_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_CLR_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SIO_GPIO_HI_OUT_CLR_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ===================================================== GPIO_OUT_XOR ====================================================== */ +#define SIO_GPIO_OUT_XOR_GPIO_OUT_XOR_Pos (0UL) /*!< GPIO_OUT_XOR (Bit 0) */ +#define SIO_GPIO_OUT_XOR_GPIO_OUT_XOR_Msk (0xffffffffUL) /*!< GPIO_OUT_XOR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== GPIO_HI_OUT_XOR ==================================================== */ +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_XOR_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SIO_GPIO_HI_OUT_XOR_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_XOR_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SIO_GPIO_HI_OUT_XOR_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OUT_XOR_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SIO_GPIO_HI_OUT_XOR_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ======================================================== GPIO_OE ======================================================== */ +#define SIO_GPIO_OE_GPIO_OE_Pos (0UL) /*!< GPIO_OE (Bit 0) */ +#define SIO_GPIO_OE_GPIO_OE_Msk (0xffffffffUL) /*!< GPIO_OE (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GPIO_HI_OE ======================================================= */ +#define SIO_GPIO_HI_OE_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SIO_GPIO_HI_OE_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SIO_GPIO_HI_OE_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SIO_GPIO_HI_OE_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SIO_GPIO_HI_OE_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SIO_GPIO_HI_OE_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SIO_GPIO_HI_OE_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SIO_GPIO_HI_OE_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ====================================================== GPIO_OE_SET ====================================================== */ +#define SIO_GPIO_OE_SET_GPIO_OE_SET_Pos (0UL) /*!< GPIO_OE_SET (Bit 0) */ +#define SIO_GPIO_OE_SET_GPIO_OE_SET_Msk (0xffffffffUL) /*!< GPIO_OE_SET (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== GPIO_HI_OE_SET ===================================================== */ +#define SIO_GPIO_HI_OE_SET_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SIO_GPIO_HI_OE_SET_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_SET_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SIO_GPIO_HI_OE_SET_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_SET_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SIO_GPIO_HI_OE_SET_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_SET_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SIO_GPIO_HI_OE_SET_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ====================================================== GPIO_OE_CLR ====================================================== */ +#define SIO_GPIO_OE_CLR_GPIO_OE_CLR_Pos (0UL) /*!< GPIO_OE_CLR (Bit 0) */ +#define SIO_GPIO_OE_CLR_GPIO_OE_CLR_Msk (0xffffffffUL) /*!< GPIO_OE_CLR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== GPIO_HI_OE_CLR ===================================================== */ +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_CLR_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SIO_GPIO_HI_OE_CLR_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_CLR_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SIO_GPIO_HI_OE_CLR_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_CLR_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SIO_GPIO_HI_OE_CLR_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ====================================================== GPIO_OE_XOR ====================================================== */ +#define SIO_GPIO_OE_XOR_GPIO_OE_XOR_Pos (0UL) /*!< GPIO_OE_XOR (Bit 0) */ +#define SIO_GPIO_OE_XOR_GPIO_OE_XOR_Msk (0xffffffffUL) /*!< GPIO_OE_XOR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== GPIO_HI_OE_XOR ===================================================== */ +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_Pos (28UL) /*!< QSPI_SD (Bit 28) */ +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_Msk (0xf0000000UL) /*!< QSPI_SD (Bitfield-Mask: 0x0f) */ +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_Pos (27UL) /*!< QSPI_CSN (Bit 27) */ +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_Msk (0x8000000UL) /*!< QSPI_CSN (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_Pos (26UL) /*!< QSPI_SCK (Bit 26) */ +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_Msk (0x4000000UL) /*!< QSPI_SCK (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_XOR_USB_DM_Pos (25UL) /*!< USB_DM (Bit 25) */ +#define SIO_GPIO_HI_OE_XOR_USB_DM_Msk (0x2000000UL) /*!< USB_DM (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_XOR_USB_DP_Pos (24UL) /*!< USB_DP (Bit 24) */ +#define SIO_GPIO_HI_OE_XOR_USB_DP_Msk (0x1000000UL) /*!< USB_DP (Bitfield-Mask: 0x01) */ +#define SIO_GPIO_HI_OE_XOR_GPIO_Pos (0UL) /*!< GPIO (Bit 0) */ +#define SIO_GPIO_HI_OE_XOR_GPIO_Msk (0xffffUL) /*!< GPIO (Bitfield-Mask: 0xffff) */ +/* ======================================================== FIFO_ST ======================================================== */ +#define SIO_FIFO_ST_ROE_Pos (3UL) /*!< ROE (Bit 3) */ +#define SIO_FIFO_ST_ROE_Msk (0x8UL) /*!< ROE (Bitfield-Mask: 0x01) */ +#define SIO_FIFO_ST_WOF_Pos (2UL) /*!< WOF (Bit 2) */ +#define SIO_FIFO_ST_WOF_Msk (0x4UL) /*!< WOF (Bitfield-Mask: 0x01) */ +#define SIO_FIFO_ST_RDY_Pos (1UL) /*!< RDY (Bit 1) */ +#define SIO_FIFO_ST_RDY_Msk (0x2UL) /*!< RDY (Bitfield-Mask: 0x01) */ +#define SIO_FIFO_ST_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define SIO_FIFO_ST_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFO_WR ======================================================== */ +#define SIO_FIFO_WR_FIFO_WR_Pos (0UL) /*!< FIFO_WR (Bit 0) */ +#define SIO_FIFO_WR_FIFO_WR_Msk (0xffffffffUL) /*!< FIFO_WR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FIFO_RD ======================================================== */ +#define SIO_FIFO_RD_FIFO_RD_Pos (0UL) /*!< FIFO_RD (Bit 0) */ +#define SIO_FIFO_RD_FIFO_RD_Msk (0xffffffffUL) /*!< FIFO_RD (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK_ST ====================================================== */ +#define SIO_SPINLOCK_ST_SPINLOCK_ST_Pos (0UL) /*!< SPINLOCK_ST (Bit 0) */ +#define SIO_SPINLOCK_ST_SPINLOCK_ST_Msk (0xffffffffUL) /*!< SPINLOCK_ST (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== INTERP0_ACCUM0 ===================================================== */ +#define SIO_INTERP0_ACCUM0_INTERP0_ACCUM0_Pos (0UL) /*!< INTERP0_ACCUM0 (Bit 0) */ +#define SIO_INTERP0_ACCUM0_INTERP0_ACCUM0_Msk (0xffffffffUL) /*!< INTERP0_ACCUM0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== INTERP0_ACCUM1 ===================================================== */ +#define SIO_INTERP0_ACCUM1_INTERP0_ACCUM1_Pos (0UL) /*!< INTERP0_ACCUM1 (Bit 0) */ +#define SIO_INTERP0_ACCUM1_INTERP0_ACCUM1_Msk (0xffffffffUL) /*!< INTERP0_ACCUM1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== INTERP0_BASE0 ===================================================== */ +#define SIO_INTERP0_BASE0_INTERP0_BASE0_Pos (0UL) /*!< INTERP0_BASE0 (Bit 0) */ +#define SIO_INTERP0_BASE0_INTERP0_BASE0_Msk (0xffffffffUL) /*!< INTERP0_BASE0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== INTERP0_BASE1 ===================================================== */ +#define SIO_INTERP0_BASE1_INTERP0_BASE1_Pos (0UL) /*!< INTERP0_BASE1 (Bit 0) */ +#define SIO_INTERP0_BASE1_INTERP0_BASE1_Msk (0xffffffffUL) /*!< INTERP0_BASE1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== INTERP0_BASE2 ===================================================== */ +#define SIO_INTERP0_BASE2_INTERP0_BASE2_Pos (0UL) /*!< INTERP0_BASE2 (Bit 0) */ +#define SIO_INTERP0_BASE2_INTERP0_BASE2_Msk (0xffffffffUL) /*!< INTERP0_BASE2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== INTERP0_POP_LANE0 =================================================== */ +#define SIO_INTERP0_POP_LANE0_INTERP0_POP_LANE0_Pos (0UL) /*!< INTERP0_POP_LANE0 (Bit 0) */ +#define SIO_INTERP0_POP_LANE0_INTERP0_POP_LANE0_Msk (0xffffffffUL) /*!< INTERP0_POP_LANE0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== INTERP0_POP_LANE1 =================================================== */ +#define SIO_INTERP0_POP_LANE1_INTERP0_POP_LANE1_Pos (0UL) /*!< INTERP0_POP_LANE1 (Bit 0) */ +#define SIO_INTERP0_POP_LANE1_INTERP0_POP_LANE1_Msk (0xffffffffUL) /*!< INTERP0_POP_LANE1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== INTERP0_POP_FULL ==================================================== */ +#define SIO_INTERP0_POP_FULL_INTERP0_POP_FULL_Pos (0UL) /*!< INTERP0_POP_FULL (Bit 0) */ +#define SIO_INTERP0_POP_FULL_INTERP0_POP_FULL_Msk (0xffffffffUL) /*!< INTERP0_POP_FULL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== INTERP0_PEEK_LANE0 =================================================== */ +#define SIO_INTERP0_PEEK_LANE0_INTERP0_PEEK_LANE0_Pos (0UL) /*!< INTERP0_PEEK_LANE0 (Bit 0) */ +#define SIO_INTERP0_PEEK_LANE0_INTERP0_PEEK_LANE0_Msk (0xffffffffUL) /*!< INTERP0_PEEK_LANE0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== INTERP0_PEEK_LANE1 =================================================== */ +#define SIO_INTERP0_PEEK_LANE1_INTERP0_PEEK_LANE1_Pos (0UL) /*!< INTERP0_PEEK_LANE1 (Bit 0) */ +#define SIO_INTERP0_PEEK_LANE1_INTERP0_PEEK_LANE1_Msk (0xffffffffUL) /*!< INTERP0_PEEK_LANE1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== INTERP0_PEEK_FULL =================================================== */ +#define SIO_INTERP0_PEEK_FULL_INTERP0_PEEK_FULL_Pos (0UL) /*!< INTERP0_PEEK_FULL (Bit 0) */ +#define SIO_INTERP0_PEEK_FULL_INTERP0_PEEK_FULL_Msk (0xffffffffUL) /*!< INTERP0_PEEK_FULL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== INTERP0_CTRL_LANE0 =================================================== */ +#define SIO_INTERP0_CTRL_LANE0_OVERF_Pos (25UL) /*!< OVERF (Bit 25) */ +#define SIO_INTERP0_CTRL_LANE0_OVERF_Msk (0x2000000UL) /*!< OVERF (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE0_OVERF1_Pos (24UL) /*!< OVERF1 (Bit 24) */ +#define SIO_INTERP0_CTRL_LANE0_OVERF1_Msk (0x1000000UL) /*!< OVERF1 (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE0_OVERF0_Pos (23UL) /*!< OVERF0 (Bit 23) */ +#define SIO_INTERP0_CTRL_LANE0_OVERF0_Msk (0x800000UL) /*!< OVERF0 (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE0_BLEND_Pos (21UL) /*!< BLEND (Bit 21) */ +#define SIO_INTERP0_CTRL_LANE0_BLEND_Msk (0x200000UL) /*!< BLEND (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_Pos (19UL) /*!< FORCE_MSB (Bit 19) */ +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_Msk (0x180000UL) /*!< FORCE_MSB (Bitfield-Mask: 0x03) */ +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_Pos (18UL) /*!< ADD_RAW (Bit 18) */ +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_Msk (0x40000UL) /*!< ADD_RAW (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_Pos (17UL) /*!< CROSS_RESULT (Bit 17) */ +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_Msk (0x20000UL) /*!< CROSS_RESULT (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_Pos (16UL) /*!< CROSS_INPUT (Bit 16) */ +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_Msk (0x10000UL) /*!< CROSS_INPUT (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE0_SIGNED_Pos (15UL) /*!< SIGNED (Bit 15) */ +#define SIO_INTERP0_CTRL_LANE0_SIGNED_Msk (0x8000UL) /*!< SIGNED (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_Pos (10UL) /*!< MASK_MSB (Bit 10) */ +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_Msk (0x7c00UL) /*!< MASK_MSB (Bitfield-Mask: 0x1f) */ +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_Pos (5UL) /*!< MASK_LSB (Bit 5) */ +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_Msk (0x3e0UL) /*!< MASK_LSB (Bitfield-Mask: 0x1f) */ +#define SIO_INTERP0_CTRL_LANE0_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */ +#define SIO_INTERP0_CTRL_LANE0_SHIFT_Msk (0x1fUL) /*!< SHIFT (Bitfield-Mask: 0x1f) */ +/* ================================================== INTERP0_CTRL_LANE1 =================================================== */ +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_Pos (19UL) /*!< FORCE_MSB (Bit 19) */ +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_Msk (0x180000UL) /*!< FORCE_MSB (Bitfield-Mask: 0x03) */ +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_Pos (18UL) /*!< ADD_RAW (Bit 18) */ +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_Msk (0x40000UL) /*!< ADD_RAW (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_Pos (17UL) /*!< CROSS_RESULT (Bit 17) */ +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_Msk (0x20000UL) /*!< CROSS_RESULT (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_Pos (16UL) /*!< CROSS_INPUT (Bit 16) */ +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_Msk (0x10000UL) /*!< CROSS_INPUT (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE1_SIGNED_Pos (15UL) /*!< SIGNED (Bit 15) */ +#define SIO_INTERP0_CTRL_LANE1_SIGNED_Msk (0x8000UL) /*!< SIGNED (Bitfield-Mask: 0x01) */ +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_Pos (10UL) /*!< MASK_MSB (Bit 10) */ +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_Msk (0x7c00UL) /*!< MASK_MSB (Bitfield-Mask: 0x1f) */ +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_Pos (5UL) /*!< MASK_LSB (Bit 5) */ +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_Msk (0x3e0UL) /*!< MASK_LSB (Bitfield-Mask: 0x1f) */ +#define SIO_INTERP0_CTRL_LANE1_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */ +#define SIO_INTERP0_CTRL_LANE1_SHIFT_Msk (0x1fUL) /*!< SHIFT (Bitfield-Mask: 0x1f) */ +/* ================================================== INTERP0_ACCUM0_ADD =================================================== */ +#define SIO_INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Pos (0UL) /*!< INTERP0_ACCUM0_ADD (Bit 0) */ +#define SIO_INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Msk (0xffffffUL) /*!< INTERP0_ACCUM0_ADD (Bitfield-Mask: 0xffffff) */ +/* ================================================== INTERP0_ACCUM1_ADD =================================================== */ +#define SIO_INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Pos (0UL) /*!< INTERP0_ACCUM1_ADD (Bit 0) */ +#define SIO_INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Msk (0xffffffUL) /*!< INTERP0_ACCUM1_ADD (Bitfield-Mask: 0xffffff) */ +/* ================================================== INTERP0_BASE_1AND0 =================================================== */ +#define SIO_INTERP0_BASE_1AND0_INTERP0_BASE_1AND0_Pos (0UL) /*!< INTERP0_BASE_1AND0 (Bit 0) */ +#define SIO_INTERP0_BASE_1AND0_INTERP0_BASE_1AND0_Msk (0xffffffffUL) /*!< INTERP0_BASE_1AND0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== INTERP1_ACCUM0 ===================================================== */ +#define SIO_INTERP1_ACCUM0_INTERP1_ACCUM0_Pos (0UL) /*!< INTERP1_ACCUM0 (Bit 0) */ +#define SIO_INTERP1_ACCUM0_INTERP1_ACCUM0_Msk (0xffffffffUL) /*!< INTERP1_ACCUM0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== INTERP1_ACCUM1 ===================================================== */ +#define SIO_INTERP1_ACCUM1_INTERP1_ACCUM1_Pos (0UL) /*!< INTERP1_ACCUM1 (Bit 0) */ +#define SIO_INTERP1_ACCUM1_INTERP1_ACCUM1_Msk (0xffffffffUL) /*!< INTERP1_ACCUM1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== INTERP1_BASE0 ===================================================== */ +#define SIO_INTERP1_BASE0_INTERP1_BASE0_Pos (0UL) /*!< INTERP1_BASE0 (Bit 0) */ +#define SIO_INTERP1_BASE0_INTERP1_BASE0_Msk (0xffffffffUL) /*!< INTERP1_BASE0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== INTERP1_BASE1 ===================================================== */ +#define SIO_INTERP1_BASE1_INTERP1_BASE1_Pos (0UL) /*!< INTERP1_BASE1 (Bit 0) */ +#define SIO_INTERP1_BASE1_INTERP1_BASE1_Msk (0xffffffffUL) /*!< INTERP1_BASE1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== INTERP1_BASE2 ===================================================== */ +#define SIO_INTERP1_BASE2_INTERP1_BASE2_Pos (0UL) /*!< INTERP1_BASE2 (Bit 0) */ +#define SIO_INTERP1_BASE2_INTERP1_BASE2_Msk (0xffffffffUL) /*!< INTERP1_BASE2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== INTERP1_POP_LANE0 =================================================== */ +#define SIO_INTERP1_POP_LANE0_INTERP1_POP_LANE0_Pos (0UL) /*!< INTERP1_POP_LANE0 (Bit 0) */ +#define SIO_INTERP1_POP_LANE0_INTERP1_POP_LANE0_Msk (0xffffffffUL) /*!< INTERP1_POP_LANE0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== INTERP1_POP_LANE1 =================================================== */ +#define SIO_INTERP1_POP_LANE1_INTERP1_POP_LANE1_Pos (0UL) /*!< INTERP1_POP_LANE1 (Bit 0) */ +#define SIO_INTERP1_POP_LANE1_INTERP1_POP_LANE1_Msk (0xffffffffUL) /*!< INTERP1_POP_LANE1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== INTERP1_POP_FULL ==================================================== */ +#define SIO_INTERP1_POP_FULL_INTERP1_POP_FULL_Pos (0UL) /*!< INTERP1_POP_FULL (Bit 0) */ +#define SIO_INTERP1_POP_FULL_INTERP1_POP_FULL_Msk (0xffffffffUL) /*!< INTERP1_POP_FULL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== INTERP1_PEEK_LANE0 =================================================== */ +#define SIO_INTERP1_PEEK_LANE0_INTERP1_PEEK_LANE0_Pos (0UL) /*!< INTERP1_PEEK_LANE0 (Bit 0) */ +#define SIO_INTERP1_PEEK_LANE0_INTERP1_PEEK_LANE0_Msk (0xffffffffUL) /*!< INTERP1_PEEK_LANE0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== INTERP1_PEEK_LANE1 =================================================== */ +#define SIO_INTERP1_PEEK_LANE1_INTERP1_PEEK_LANE1_Pos (0UL) /*!< INTERP1_PEEK_LANE1 (Bit 0) */ +#define SIO_INTERP1_PEEK_LANE1_INTERP1_PEEK_LANE1_Msk (0xffffffffUL) /*!< INTERP1_PEEK_LANE1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== INTERP1_PEEK_FULL =================================================== */ +#define SIO_INTERP1_PEEK_FULL_INTERP1_PEEK_FULL_Pos (0UL) /*!< INTERP1_PEEK_FULL (Bit 0) */ +#define SIO_INTERP1_PEEK_FULL_INTERP1_PEEK_FULL_Msk (0xffffffffUL) /*!< INTERP1_PEEK_FULL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== INTERP1_CTRL_LANE0 =================================================== */ +#define SIO_INTERP1_CTRL_LANE0_OVERF_Pos (25UL) /*!< OVERF (Bit 25) */ +#define SIO_INTERP1_CTRL_LANE0_OVERF_Msk (0x2000000UL) /*!< OVERF (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE0_OVERF1_Pos (24UL) /*!< OVERF1 (Bit 24) */ +#define SIO_INTERP1_CTRL_LANE0_OVERF1_Msk (0x1000000UL) /*!< OVERF1 (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE0_OVERF0_Pos (23UL) /*!< OVERF0 (Bit 23) */ +#define SIO_INTERP1_CTRL_LANE0_OVERF0_Msk (0x800000UL) /*!< OVERF0 (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE0_CLAMP_Pos (22UL) /*!< CLAMP (Bit 22) */ +#define SIO_INTERP1_CTRL_LANE0_CLAMP_Msk (0x400000UL) /*!< CLAMP (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_Pos (19UL) /*!< FORCE_MSB (Bit 19) */ +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_Msk (0x180000UL) /*!< FORCE_MSB (Bitfield-Mask: 0x03) */ +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_Pos (18UL) /*!< ADD_RAW (Bit 18) */ +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_Msk (0x40000UL) /*!< ADD_RAW (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_Pos (17UL) /*!< CROSS_RESULT (Bit 17) */ +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_Msk (0x20000UL) /*!< CROSS_RESULT (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_Pos (16UL) /*!< CROSS_INPUT (Bit 16) */ +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_Msk (0x10000UL) /*!< CROSS_INPUT (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE0_SIGNED_Pos (15UL) /*!< SIGNED (Bit 15) */ +#define SIO_INTERP1_CTRL_LANE0_SIGNED_Msk (0x8000UL) /*!< SIGNED (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_Pos (10UL) /*!< MASK_MSB (Bit 10) */ +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_Msk (0x7c00UL) /*!< MASK_MSB (Bitfield-Mask: 0x1f) */ +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_Pos (5UL) /*!< MASK_LSB (Bit 5) */ +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_Msk (0x3e0UL) /*!< MASK_LSB (Bitfield-Mask: 0x1f) */ +#define SIO_INTERP1_CTRL_LANE0_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */ +#define SIO_INTERP1_CTRL_LANE0_SHIFT_Msk (0x1fUL) /*!< SHIFT (Bitfield-Mask: 0x1f) */ +/* ================================================== INTERP1_CTRL_LANE1 =================================================== */ +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_Pos (19UL) /*!< FORCE_MSB (Bit 19) */ +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_Msk (0x180000UL) /*!< FORCE_MSB (Bitfield-Mask: 0x03) */ +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_Pos (18UL) /*!< ADD_RAW (Bit 18) */ +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_Msk (0x40000UL) /*!< ADD_RAW (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_Pos (17UL) /*!< CROSS_RESULT (Bit 17) */ +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_Msk (0x20000UL) /*!< CROSS_RESULT (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_Pos (16UL) /*!< CROSS_INPUT (Bit 16) */ +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_Msk (0x10000UL) /*!< CROSS_INPUT (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE1_SIGNED_Pos (15UL) /*!< SIGNED (Bit 15) */ +#define SIO_INTERP1_CTRL_LANE1_SIGNED_Msk (0x8000UL) /*!< SIGNED (Bitfield-Mask: 0x01) */ +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_Pos (10UL) /*!< MASK_MSB (Bit 10) */ +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_Msk (0x7c00UL) /*!< MASK_MSB (Bitfield-Mask: 0x1f) */ +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_Pos (5UL) /*!< MASK_LSB (Bit 5) */ +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_Msk (0x3e0UL) /*!< MASK_LSB (Bitfield-Mask: 0x1f) */ +#define SIO_INTERP1_CTRL_LANE1_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */ +#define SIO_INTERP1_CTRL_LANE1_SHIFT_Msk (0x1fUL) /*!< SHIFT (Bitfield-Mask: 0x1f) */ +/* ================================================== INTERP1_ACCUM0_ADD =================================================== */ +#define SIO_INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Pos (0UL) /*!< INTERP1_ACCUM0_ADD (Bit 0) */ +#define SIO_INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Msk (0xffffffUL) /*!< INTERP1_ACCUM0_ADD (Bitfield-Mask: 0xffffff) */ +/* ================================================== INTERP1_ACCUM1_ADD =================================================== */ +#define SIO_INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Pos (0UL) /*!< INTERP1_ACCUM1_ADD (Bit 0) */ +#define SIO_INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Msk (0xffffffUL) /*!< INTERP1_ACCUM1_ADD (Bitfield-Mask: 0xffffff) */ +/* ================================================== INTERP1_BASE_1AND0 =================================================== */ +#define SIO_INTERP1_BASE_1AND0_INTERP1_BASE_1AND0_Pos (0UL) /*!< INTERP1_BASE_1AND0 (Bit 0) */ +#define SIO_INTERP1_BASE_1AND0_INTERP1_BASE_1AND0_Msk (0xffffffffUL) /*!< INTERP1_BASE_1AND0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK0 ======================================================= */ +#define SIO_SPINLOCK0_SPINLOCK0_Pos (0UL) /*!< SPINLOCK0 (Bit 0) */ +#define SIO_SPINLOCK0_SPINLOCK0_Msk (0xffffffffUL) /*!< SPINLOCK0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK1 ======================================================= */ +#define SIO_SPINLOCK1_SPINLOCK1_Pos (0UL) /*!< SPINLOCK1 (Bit 0) */ +#define SIO_SPINLOCK1_SPINLOCK1_Msk (0xffffffffUL) /*!< SPINLOCK1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK2 ======================================================= */ +#define SIO_SPINLOCK2_SPINLOCK2_Pos (0UL) /*!< SPINLOCK2 (Bit 0) */ +#define SIO_SPINLOCK2_SPINLOCK2_Msk (0xffffffffUL) /*!< SPINLOCK2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK3 ======================================================= */ +#define SIO_SPINLOCK3_SPINLOCK3_Pos (0UL) /*!< SPINLOCK3 (Bit 0) */ +#define SIO_SPINLOCK3_SPINLOCK3_Msk (0xffffffffUL) /*!< SPINLOCK3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK4 ======================================================= */ +#define SIO_SPINLOCK4_SPINLOCK4_Pos (0UL) /*!< SPINLOCK4 (Bit 0) */ +#define SIO_SPINLOCK4_SPINLOCK4_Msk (0xffffffffUL) /*!< SPINLOCK4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK5 ======================================================= */ +#define SIO_SPINLOCK5_SPINLOCK5_Pos (0UL) /*!< SPINLOCK5 (Bit 0) */ +#define SIO_SPINLOCK5_SPINLOCK5_Msk (0xffffffffUL) /*!< SPINLOCK5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK6 ======================================================= */ +#define SIO_SPINLOCK6_SPINLOCK6_Pos (0UL) /*!< SPINLOCK6 (Bit 0) */ +#define SIO_SPINLOCK6_SPINLOCK6_Msk (0xffffffffUL) /*!< SPINLOCK6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK7 ======================================================= */ +#define SIO_SPINLOCK7_SPINLOCK7_Pos (0UL) /*!< SPINLOCK7 (Bit 0) */ +#define SIO_SPINLOCK7_SPINLOCK7_Msk (0xffffffffUL) /*!< SPINLOCK7 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK8 ======================================================= */ +#define SIO_SPINLOCK8_SPINLOCK8_Pos (0UL) /*!< SPINLOCK8 (Bit 0) */ +#define SIO_SPINLOCK8_SPINLOCK8_Msk (0xffffffffUL) /*!< SPINLOCK8 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SPINLOCK9 ======================================================= */ +#define SIO_SPINLOCK9_SPINLOCK9_Pos (0UL) /*!< SPINLOCK9 (Bit 0) */ +#define SIO_SPINLOCK9_SPINLOCK9_Msk (0xffffffffUL) /*!< SPINLOCK9 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK10 ======================================================= */ +#define SIO_SPINLOCK10_SPINLOCK10_Pos (0UL) /*!< SPINLOCK10 (Bit 0) */ +#define SIO_SPINLOCK10_SPINLOCK10_Msk (0xffffffffUL) /*!< SPINLOCK10 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK11 ======================================================= */ +#define SIO_SPINLOCK11_SPINLOCK11_Pos (0UL) /*!< SPINLOCK11 (Bit 0) */ +#define SIO_SPINLOCK11_SPINLOCK11_Msk (0xffffffffUL) /*!< SPINLOCK11 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK12 ======================================================= */ +#define SIO_SPINLOCK12_SPINLOCK12_Pos (0UL) /*!< SPINLOCK12 (Bit 0) */ +#define SIO_SPINLOCK12_SPINLOCK12_Msk (0xffffffffUL) /*!< SPINLOCK12 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK13 ======================================================= */ +#define SIO_SPINLOCK13_SPINLOCK13_Pos (0UL) /*!< SPINLOCK13 (Bit 0) */ +#define SIO_SPINLOCK13_SPINLOCK13_Msk (0xffffffffUL) /*!< SPINLOCK13 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK14 ======================================================= */ +#define SIO_SPINLOCK14_SPINLOCK14_Pos (0UL) /*!< SPINLOCK14 (Bit 0) */ +#define SIO_SPINLOCK14_SPINLOCK14_Msk (0xffffffffUL) /*!< SPINLOCK14 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK15 ======================================================= */ +#define SIO_SPINLOCK15_SPINLOCK15_Pos (0UL) /*!< SPINLOCK15 (Bit 0) */ +#define SIO_SPINLOCK15_SPINLOCK15_Msk (0xffffffffUL) /*!< SPINLOCK15 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK16 ======================================================= */ +#define SIO_SPINLOCK16_SPINLOCK16_Pos (0UL) /*!< SPINLOCK16 (Bit 0) */ +#define SIO_SPINLOCK16_SPINLOCK16_Msk (0xffffffffUL) /*!< SPINLOCK16 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK17 ======================================================= */ +#define SIO_SPINLOCK17_SPINLOCK17_Pos (0UL) /*!< SPINLOCK17 (Bit 0) */ +#define SIO_SPINLOCK17_SPINLOCK17_Msk (0xffffffffUL) /*!< SPINLOCK17 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK18 ======================================================= */ +#define SIO_SPINLOCK18_SPINLOCK18_Pos (0UL) /*!< SPINLOCK18 (Bit 0) */ +#define SIO_SPINLOCK18_SPINLOCK18_Msk (0xffffffffUL) /*!< SPINLOCK18 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK19 ======================================================= */ +#define SIO_SPINLOCK19_SPINLOCK19_Pos (0UL) /*!< SPINLOCK19 (Bit 0) */ +#define SIO_SPINLOCK19_SPINLOCK19_Msk (0xffffffffUL) /*!< SPINLOCK19 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK20 ======================================================= */ +#define SIO_SPINLOCK20_SPINLOCK20_Pos (0UL) /*!< SPINLOCK20 (Bit 0) */ +#define SIO_SPINLOCK20_SPINLOCK20_Msk (0xffffffffUL) /*!< SPINLOCK20 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK21 ======================================================= */ +#define SIO_SPINLOCK21_SPINLOCK21_Pos (0UL) /*!< SPINLOCK21 (Bit 0) */ +#define SIO_SPINLOCK21_SPINLOCK21_Msk (0xffffffffUL) /*!< SPINLOCK21 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK22 ======================================================= */ +#define SIO_SPINLOCK22_SPINLOCK22_Pos (0UL) /*!< SPINLOCK22 (Bit 0) */ +#define SIO_SPINLOCK22_SPINLOCK22_Msk (0xffffffffUL) /*!< SPINLOCK22 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK23 ======================================================= */ +#define SIO_SPINLOCK23_SPINLOCK23_Pos (0UL) /*!< SPINLOCK23 (Bit 0) */ +#define SIO_SPINLOCK23_SPINLOCK23_Msk (0xffffffffUL) /*!< SPINLOCK23 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK24 ======================================================= */ +#define SIO_SPINLOCK24_SPINLOCK24_Pos (0UL) /*!< SPINLOCK24 (Bit 0) */ +#define SIO_SPINLOCK24_SPINLOCK24_Msk (0xffffffffUL) /*!< SPINLOCK24 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK25 ======================================================= */ +#define SIO_SPINLOCK25_SPINLOCK25_Pos (0UL) /*!< SPINLOCK25 (Bit 0) */ +#define SIO_SPINLOCK25_SPINLOCK25_Msk (0xffffffffUL) /*!< SPINLOCK25 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK26 ======================================================= */ +#define SIO_SPINLOCK26_SPINLOCK26_Pos (0UL) /*!< SPINLOCK26 (Bit 0) */ +#define SIO_SPINLOCK26_SPINLOCK26_Msk (0xffffffffUL) /*!< SPINLOCK26 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK27 ======================================================= */ +#define SIO_SPINLOCK27_SPINLOCK27_Pos (0UL) /*!< SPINLOCK27 (Bit 0) */ +#define SIO_SPINLOCK27_SPINLOCK27_Msk (0xffffffffUL) /*!< SPINLOCK27 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK28 ======================================================= */ +#define SIO_SPINLOCK28_SPINLOCK28_Pos (0UL) /*!< SPINLOCK28 (Bit 0) */ +#define SIO_SPINLOCK28_SPINLOCK28_Msk (0xffffffffUL) /*!< SPINLOCK28 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK29 ======================================================= */ +#define SIO_SPINLOCK29_SPINLOCK29_Pos (0UL) /*!< SPINLOCK29 (Bit 0) */ +#define SIO_SPINLOCK29_SPINLOCK29_Msk (0xffffffffUL) /*!< SPINLOCK29 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK30 ======================================================= */ +#define SIO_SPINLOCK30_SPINLOCK30_Pos (0UL) /*!< SPINLOCK30 (Bit 0) */ +#define SIO_SPINLOCK30_SPINLOCK30_Msk (0xffffffffUL) /*!< SPINLOCK30 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SPINLOCK31 ======================================================= */ +#define SIO_SPINLOCK31_SPINLOCK31_Pos (0UL) /*!< SPINLOCK31 (Bit 0) */ +#define SIO_SPINLOCK31_SPINLOCK31_Msk (0xffffffffUL) /*!< SPINLOCK31 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DOORBELL_OUT_SET ==================================================== */ +#define SIO_DOORBELL_OUT_SET_DOORBELL_OUT_SET_Pos (0UL) /*!< DOORBELL_OUT_SET (Bit 0) */ +#define SIO_DOORBELL_OUT_SET_DOORBELL_OUT_SET_Msk (0xffUL) /*!< DOORBELL_OUT_SET (Bitfield-Mask: 0xff) */ +/* =================================================== DOORBELL_OUT_CLR ==================================================== */ +#define SIO_DOORBELL_OUT_CLR_DOORBELL_OUT_CLR_Pos (0UL) /*!< DOORBELL_OUT_CLR (Bit 0) */ +#define SIO_DOORBELL_OUT_CLR_DOORBELL_OUT_CLR_Msk (0xffUL) /*!< DOORBELL_OUT_CLR (Bitfield-Mask: 0xff) */ +/* ==================================================== DOORBELL_IN_SET ==================================================== */ +#define SIO_DOORBELL_IN_SET_DOORBELL_IN_SET_Pos (0UL) /*!< DOORBELL_IN_SET (Bit 0) */ +#define SIO_DOORBELL_IN_SET_DOORBELL_IN_SET_Msk (0xffUL) /*!< DOORBELL_IN_SET (Bitfield-Mask: 0xff) */ +/* ==================================================== DOORBELL_IN_CLR ==================================================== */ +#define SIO_DOORBELL_IN_CLR_DOORBELL_IN_CLR_Pos (0UL) /*!< DOORBELL_IN_CLR (Bit 0) */ +#define SIO_DOORBELL_IN_CLR_DOORBELL_IN_CLR_Msk (0xffUL) /*!< DOORBELL_IN_CLR (Bitfield-Mask: 0xff) */ +/* ====================================================== PERI_NONSEC ====================================================== */ +#define SIO_PERI_NONSEC_TMDS_Pos (5UL) /*!< TMDS (Bit 5) */ +#define SIO_PERI_NONSEC_TMDS_Msk (0x20UL) /*!< TMDS (Bitfield-Mask: 0x01) */ +#define SIO_PERI_NONSEC_INTERP1_Pos (1UL) /*!< INTERP1 (Bit 1) */ +#define SIO_PERI_NONSEC_INTERP1_Msk (0x2UL) /*!< INTERP1 (Bitfield-Mask: 0x01) */ +#define SIO_PERI_NONSEC_INTERP0_Pos (0UL) /*!< INTERP0 (Bit 0) */ +#define SIO_PERI_NONSEC_INTERP0_Msk (0x1UL) /*!< INTERP0 (Bitfield-Mask: 0x01) */ +/* ===================================================== RISCV_SOFTIRQ ===================================================== */ +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_Pos (9UL) /*!< CORE1_CLR (Bit 9) */ +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_Msk (0x200UL) /*!< CORE1_CLR (Bitfield-Mask: 0x01) */ +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_Pos (8UL) /*!< CORE0_CLR (Bit 8) */ +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_Msk (0x100UL) /*!< CORE0_CLR (Bitfield-Mask: 0x01) */ +#define SIO_RISCV_SOFTIRQ_CORE1_SET_Pos (1UL) /*!< CORE1_SET (Bit 1) */ +#define SIO_RISCV_SOFTIRQ_CORE1_SET_Msk (0x2UL) /*!< CORE1_SET (Bitfield-Mask: 0x01) */ +#define SIO_RISCV_SOFTIRQ_CORE0_SET_Pos (0UL) /*!< CORE0_SET (Bit 0) */ +#define SIO_RISCV_SOFTIRQ_CORE0_SET_Msk (0x1UL) /*!< CORE0_SET (Bitfield-Mask: 0x01) */ +/* ====================================================== MTIME_CTRL ======================================================= */ +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_Pos (3UL) /*!< DBGPAUSE_CORE1 (Bit 3) */ +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_Msk (0x8UL) /*!< DBGPAUSE_CORE1 (Bitfield-Mask: 0x01) */ +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_Pos (2UL) /*!< DBGPAUSE_CORE0 (Bit 2) */ +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_Msk (0x4UL) /*!< DBGPAUSE_CORE0 (Bitfield-Mask: 0x01) */ +#define SIO_MTIME_CTRL_FULLSPEED_Pos (1UL) /*!< FULLSPEED (Bit 1) */ +#define SIO_MTIME_CTRL_FULLSPEED_Msk (0x2UL) /*!< FULLSPEED (Bitfield-Mask: 0x01) */ +#define SIO_MTIME_CTRL_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define SIO_MTIME_CTRL_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= MTIME ========================================================= */ +#define SIO_MTIME_MTIME_Pos (0UL) /*!< MTIME (Bit 0) */ +#define SIO_MTIME_MTIME_Msk (0xffffffffUL) /*!< MTIME (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTIMEH ========================================================= */ +#define SIO_MTIMEH_MTIMEH_Pos (0UL) /*!< MTIMEH (Bit 0) */ +#define SIO_MTIMEH_MTIMEH_Msk (0xffffffffUL) /*!< MTIMEH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MTIMECMP ======================================================== */ +#define SIO_MTIMECMP_MTIMECMP_Pos (0UL) /*!< MTIMECMP (Bit 0) */ +#define SIO_MTIMECMP_MTIMECMP_Msk (0xffffffffUL) /*!< MTIMECMP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MTIMECMPH ======================================================= */ +#define SIO_MTIMECMPH_MTIMECMPH_Pos (0UL) /*!< MTIMECMPH (Bit 0) */ +#define SIO_MTIMECMPH_MTIMECMPH_Msk (0xffffffffUL) /*!< MTIMECMPH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TMDS_CTRL ======================================================= */ +#define SIO_TMDS_CTRL_CLEAR_BALANCE_Pos (28UL) /*!< CLEAR_BALANCE (Bit 28) */ +#define SIO_TMDS_CTRL_CLEAR_BALANCE_Msk (0x10000000UL) /*!< CLEAR_BALANCE (Bitfield-Mask: 0x01) */ +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_Pos (27UL) /*!< PIX2_NOSHIFT (Bit 27) */ +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_Msk (0x8000000UL) /*!< PIX2_NOSHIFT (Bitfield-Mask: 0x01) */ +#define SIO_TMDS_CTRL_PIX_SHIFT_Pos (24UL) /*!< PIX_SHIFT (Bit 24) */ +#define SIO_TMDS_CTRL_PIX_SHIFT_Msk (0x7000000UL) /*!< PIX_SHIFT (Bitfield-Mask: 0x07) */ +#define SIO_TMDS_CTRL_INTERLEAVE_Pos (23UL) /*!< INTERLEAVE (Bit 23) */ +#define SIO_TMDS_CTRL_INTERLEAVE_Msk (0x800000UL) /*!< INTERLEAVE (Bitfield-Mask: 0x01) */ +#define SIO_TMDS_CTRL_L2_NBITS_Pos (18UL) /*!< L2_NBITS (Bit 18) */ +#define SIO_TMDS_CTRL_L2_NBITS_Msk (0x1c0000UL) /*!< L2_NBITS (Bitfield-Mask: 0x07) */ +#define SIO_TMDS_CTRL_L1_NBITS_Pos (15UL) /*!< L1_NBITS (Bit 15) */ +#define SIO_TMDS_CTRL_L1_NBITS_Msk (0x38000UL) /*!< L1_NBITS (Bitfield-Mask: 0x07) */ +#define SIO_TMDS_CTRL_L0_NBITS_Pos (12UL) /*!< L0_NBITS (Bit 12) */ +#define SIO_TMDS_CTRL_L0_NBITS_Msk (0x7000UL) /*!< L0_NBITS (Bitfield-Mask: 0x07) */ +#define SIO_TMDS_CTRL_L2_ROT_Pos (8UL) /*!< L2_ROT (Bit 8) */ +#define SIO_TMDS_CTRL_L2_ROT_Msk (0xf00UL) /*!< L2_ROT (Bitfield-Mask: 0x0f) */ +#define SIO_TMDS_CTRL_L1_ROT_Pos (4UL) /*!< L1_ROT (Bit 4) */ +#define SIO_TMDS_CTRL_L1_ROT_Msk (0xf0UL) /*!< L1_ROT (Bitfield-Mask: 0x0f) */ +#define SIO_TMDS_CTRL_L0_ROT_Pos (0UL) /*!< L0_ROT (Bit 0) */ +#define SIO_TMDS_CTRL_L0_ROT_Msk (0xfUL) /*!< L0_ROT (Bitfield-Mask: 0x0f) */ +/* ====================================================== TMDS_WDATA ======================================================= */ +#define SIO_TMDS_WDATA_TMDS_WDATA_Pos (0UL) /*!< TMDS_WDATA (Bit 0) */ +#define SIO_TMDS_WDATA_TMDS_WDATA_Msk (0xffffffffUL) /*!< TMDS_WDATA (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TMDS_PEEK_SINGLE ==================================================== */ +#define SIO_TMDS_PEEK_SINGLE_TMDS_PEEK_SINGLE_Pos (0UL) /*!< TMDS_PEEK_SINGLE (Bit 0) */ +#define SIO_TMDS_PEEK_SINGLE_TMDS_PEEK_SINGLE_Msk (0xffffffffUL) /*!< TMDS_PEEK_SINGLE (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TMDS_POP_SINGLE ==================================================== */ +#define SIO_TMDS_POP_SINGLE_TMDS_POP_SINGLE_Pos (0UL) /*!< TMDS_POP_SINGLE (Bit 0) */ +#define SIO_TMDS_POP_SINGLE_TMDS_POP_SINGLE_Msk (0xffffffffUL) /*!< TMDS_POP_SINGLE (Bitfield-Mask: 0xffffffff) */ +/* ================================================== TMDS_PEEK_DOUBLE_L0 ================================================== */ +#define SIO_TMDS_PEEK_DOUBLE_L0_TMDS_PEEK_DOUBLE_L0_Pos (0UL) /*!< TMDS_PEEK_DOUBLE_L0 (Bit 0) */ +#define SIO_TMDS_PEEK_DOUBLE_L0_TMDS_PEEK_DOUBLE_L0_Msk (0xffffffffUL) /*!< TMDS_PEEK_DOUBLE_L0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== TMDS_POP_DOUBLE_L0 =================================================== */ +#define SIO_TMDS_POP_DOUBLE_L0_TMDS_POP_DOUBLE_L0_Pos (0UL) /*!< TMDS_POP_DOUBLE_L0 (Bit 0) */ +#define SIO_TMDS_POP_DOUBLE_L0_TMDS_POP_DOUBLE_L0_Msk (0xffffffffUL) /*!< TMDS_POP_DOUBLE_L0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== TMDS_PEEK_DOUBLE_L1 ================================================== */ +#define SIO_TMDS_PEEK_DOUBLE_L1_TMDS_PEEK_DOUBLE_L1_Pos (0UL) /*!< TMDS_PEEK_DOUBLE_L1 (Bit 0) */ +#define SIO_TMDS_PEEK_DOUBLE_L1_TMDS_PEEK_DOUBLE_L1_Msk (0xffffffffUL) /*!< TMDS_PEEK_DOUBLE_L1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== TMDS_POP_DOUBLE_L1 =================================================== */ +#define SIO_TMDS_POP_DOUBLE_L1_TMDS_POP_DOUBLE_L1_Pos (0UL) /*!< TMDS_POP_DOUBLE_L1 (Bit 0) */ +#define SIO_TMDS_POP_DOUBLE_L1_TMDS_POP_DOUBLE_L1_Msk (0xffffffffUL) /*!< TMDS_POP_DOUBLE_L1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== TMDS_PEEK_DOUBLE_L2 ================================================== */ +#define SIO_TMDS_PEEK_DOUBLE_L2_TMDS_PEEK_DOUBLE_L2_Pos (0UL) /*!< TMDS_PEEK_DOUBLE_L2 (Bit 0) */ +#define SIO_TMDS_PEEK_DOUBLE_L2_TMDS_PEEK_DOUBLE_L2_Msk (0xffffffffUL) /*!< TMDS_PEEK_DOUBLE_L2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== TMDS_POP_DOUBLE_L2 =================================================== */ +#define SIO_TMDS_POP_DOUBLE_L2_TMDS_POP_DOUBLE_L2_Pos (0UL) /*!< TMDS_POP_DOUBLE_L2 (Bit 0) */ +#define SIO_TMDS_POP_DOUBLE_L2_TMDS_POP_DOUBLE_L2_Msk (0xffffffffUL) /*!< TMDS_POP_DOUBLE_L2 (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ BOOTRAM ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== WRITE_ONCE0 ====================================================== */ +#define BOOTRAM_WRITE_ONCE0_WRITE_ONCE0_Pos (0UL) /*!< WRITE_ONCE0 (Bit 0) */ +#define BOOTRAM_WRITE_ONCE0_WRITE_ONCE0_Msk (0xffffffffUL) /*!< WRITE_ONCE0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== WRITE_ONCE1 ====================================================== */ +#define BOOTRAM_WRITE_ONCE1_WRITE_ONCE1_Pos (0UL) /*!< WRITE_ONCE1 (Bit 0) */ +#define BOOTRAM_WRITE_ONCE1_WRITE_ONCE1_Msk (0xffffffffUL) /*!< WRITE_ONCE1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== BOOTLOCK_STAT ===================================================== */ +#define BOOTRAM_BOOTLOCK_STAT_BOOTLOCK_STAT_Pos (0UL) /*!< BOOTLOCK_STAT (Bit 0) */ +#define BOOTRAM_BOOTLOCK_STAT_BOOTLOCK_STAT_Msk (0xffUL) /*!< BOOTLOCK_STAT (Bitfield-Mask: 0xff) */ +/* ======================================================= BOOTLOCK0 ======================================================= */ +#define BOOTRAM_BOOTLOCK0_BOOTLOCK0_Pos (0UL) /*!< BOOTLOCK0 (Bit 0) */ +#define BOOTRAM_BOOTLOCK0_BOOTLOCK0_Msk (0xffffffffUL) /*!< BOOTLOCK0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= BOOTLOCK1 ======================================================= */ +#define BOOTRAM_BOOTLOCK1_BOOTLOCK1_Pos (0UL) /*!< BOOTLOCK1 (Bit 0) */ +#define BOOTRAM_BOOTLOCK1_BOOTLOCK1_Msk (0xffffffffUL) /*!< BOOTLOCK1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= BOOTLOCK2 ======================================================= */ +#define BOOTRAM_BOOTLOCK2_BOOTLOCK2_Pos (0UL) /*!< BOOTLOCK2 (Bit 0) */ +#define BOOTRAM_BOOTLOCK2_BOOTLOCK2_Msk (0xffffffffUL) /*!< BOOTLOCK2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= BOOTLOCK3 ======================================================= */ +#define BOOTRAM_BOOTLOCK3_BOOTLOCK3_Pos (0UL) /*!< BOOTLOCK3 (Bit 0) */ +#define BOOTRAM_BOOTLOCK3_BOOTLOCK3_Msk (0xffffffffUL) /*!< BOOTLOCK3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= BOOTLOCK4 ======================================================= */ +#define BOOTRAM_BOOTLOCK4_BOOTLOCK4_Pos (0UL) /*!< BOOTLOCK4 (Bit 0) */ +#define BOOTRAM_BOOTLOCK4_BOOTLOCK4_Msk (0xffffffffUL) /*!< BOOTLOCK4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= BOOTLOCK5 ======================================================= */ +#define BOOTRAM_BOOTLOCK5_BOOTLOCK5_Pos (0UL) /*!< BOOTLOCK5 (Bit 0) */ +#define BOOTRAM_BOOTLOCK5_BOOTLOCK5_Msk (0xffffffffUL) /*!< BOOTLOCK5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= BOOTLOCK6 ======================================================= */ +#define BOOTRAM_BOOTLOCK6_BOOTLOCK6_Pos (0UL) /*!< BOOTLOCK6 (Bit 0) */ +#define BOOTRAM_BOOTLOCK6_BOOTLOCK6_Msk (0xffffffffUL) /*!< BOOTLOCK6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= BOOTLOCK7 ======================================================= */ +#define BOOTRAM_BOOTLOCK7_BOOTLOCK7_Pos (0UL) /*!< BOOTLOCK7 (Bit 0) */ +#define BOOTRAM_BOOTLOCK7_BOOTLOCK7_Msk (0xffffffffUL) /*!< BOOTLOCK7 (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ CORESIGHT_TRACE ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CTRL_STATUS ====================================================== */ +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_Pos (1UL) /*!< TRACE_CAPTURE_FIFO_OVERFLOW (Bit 1) */ +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_Msk (0x2UL) /*!< TRACE_CAPTURE_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_Pos (0UL) /*!< TRACE_CAPTURE_FIFO_FLUSH (Bit 0) */ +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_Msk (0x1UL) /*!< TRACE_CAPTURE_FIFO_FLUSH (Bitfield-Mask: 0x01) */ +/* ================================================== TRACE_CAPTURE_FIFO =================================================== */ +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_Msk (0xffffffffUL) /*!< RDATA (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ADDR_ENDP ======================================================= */ +#define USB_ADDR_ENDP_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP1 ======================================================= */ +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP1_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP1_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP1_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP1_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP1_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP1_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP2 ======================================================= */ +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP2_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP2_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP2_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP2_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP2_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP2_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP3 ======================================================= */ +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP3_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP3_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP3_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP3_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP3_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP3_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP4 ======================================================= */ +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP4_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP4_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP4_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP4_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP4_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP4_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP5 ======================================================= */ +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP5_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP5_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP5_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP5_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP5_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP5_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP6 ======================================================= */ +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP6_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP6_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP6_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP6_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP6_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP6_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP7 ======================================================= */ +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP7_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP7_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP7_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP7_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP7_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP7_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP8 ======================================================= */ +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP8_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP8_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP8_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP8_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP8_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP8_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP9 ======================================================= */ +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP9_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP9_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP9_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP9_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP9_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP9_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP10 ====================================================== */ +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP10_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP10_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP10_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP10_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP10_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP10_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP11 ====================================================== */ +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP11_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP11_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP11_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP11_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP11_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP11_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP12 ====================================================== */ +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP12_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP12_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP12_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP12_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP12_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP12_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP13 ====================================================== */ +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP13_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP13_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP13_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP13_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP13_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP13_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP14 ====================================================== */ +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP14_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP14_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP14_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP14_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP14_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP14_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ====================================================== ADDR_ENDP15 ====================================================== */ +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */ +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP15_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */ +#define USB_ADDR_ENDP15_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */ +#define USB_ADDR_ENDP15_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */ +#define USB_ADDR_ENDP15_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */ +#define USB_ADDR_ENDP15_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ +#define USB_ADDR_ENDP15_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */ +/* ======================================================= MAIN_CTRL ======================================================= */ +#define USB_MAIN_CTRL_SIM_TIMING_Pos (31UL) /*!< SIM_TIMING (Bit 31) */ +#define USB_MAIN_CTRL_SIM_TIMING_Msk (0x80000000UL) /*!< SIM_TIMING (Bitfield-Mask: 0x01) */ +#define USB_MAIN_CTRL_PHY_ISO_Pos (2UL) /*!< PHY_ISO (Bit 2) */ +#define USB_MAIN_CTRL_PHY_ISO_Msk (0x4UL) /*!< PHY_ISO (Bitfield-Mask: 0x01) */ +#define USB_MAIN_CTRL_HOST_NDEVICE_Pos (1UL) /*!< HOST_NDEVICE (Bit 1) */ +#define USB_MAIN_CTRL_HOST_NDEVICE_Msk (0x2UL) /*!< HOST_NDEVICE (Bitfield-Mask: 0x01) */ +#define USB_MAIN_CTRL_CONTROLLER_EN_Pos (0UL) /*!< CONTROLLER_EN (Bit 0) */ +#define USB_MAIN_CTRL_CONTROLLER_EN_Msk (0x1UL) /*!< CONTROLLER_EN (Bitfield-Mask: 0x01) */ +/* ======================================================== SOF_WR ========================================================= */ +#define USB_SOF_WR_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define USB_SOF_WR_COUNT_Msk (0x7ffUL) /*!< COUNT (Bitfield-Mask: 0x7ff) */ +/* ======================================================== SOF_RD ========================================================= */ +#define USB_SOF_RD_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define USB_SOF_RD_COUNT_Msk (0x7ffUL) /*!< COUNT (Bitfield-Mask: 0x7ff) */ +/* ======================================================= SIE_CTRL ======================================================== */ +#define USB_SIE_CTRL_EP0_INT_STALL_Pos (31UL) /*!< EP0_INT_STALL (Bit 31) */ +#define USB_SIE_CTRL_EP0_INT_STALL_Msk (0x80000000UL) /*!< EP0_INT_STALL (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_Pos (30UL) /*!< EP0_DOUBLE_BUF (Bit 30) */ +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_Msk (0x40000000UL) /*!< EP0_DOUBLE_BUF (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_EP0_INT_1BUF_Pos (29UL) /*!< EP0_INT_1BUF (Bit 29) */ +#define USB_SIE_CTRL_EP0_INT_1BUF_Msk (0x20000000UL) /*!< EP0_INT_1BUF (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_EP0_INT_2BUF_Pos (28UL) /*!< EP0_INT_2BUF (Bit 28) */ +#define USB_SIE_CTRL_EP0_INT_2BUF_Msk (0x10000000UL) /*!< EP0_INT_2BUF (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_EP0_INT_NAK_Pos (27UL) /*!< EP0_INT_NAK (Bit 27) */ +#define USB_SIE_CTRL_EP0_INT_NAK_Msk (0x8000000UL) /*!< EP0_INT_NAK (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_DIRECT_EN_Pos (26UL) /*!< DIRECT_EN (Bit 26) */ +#define USB_SIE_CTRL_DIRECT_EN_Msk (0x4000000UL) /*!< DIRECT_EN (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_DIRECT_DP_Pos (25UL) /*!< DIRECT_DP (Bit 25) */ +#define USB_SIE_CTRL_DIRECT_DP_Msk (0x2000000UL) /*!< DIRECT_DP (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_DIRECT_DM_Pos (24UL) /*!< DIRECT_DM (Bit 24) */ +#define USB_SIE_CTRL_DIRECT_DM_Msk (0x1000000UL) /*!< DIRECT_DM (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_Pos (19UL) /*!< EP0_STOP_ON_SHORT_PACKET (Bit 19) */ +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_Msk (0x80000UL) /*!< EP0_STOP_ON_SHORT_PACKET (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_TRANSCEIVER_PD_Pos (18UL) /*!< TRANSCEIVER_PD (Bit 18) */ +#define USB_SIE_CTRL_TRANSCEIVER_PD_Msk (0x40000UL) /*!< TRANSCEIVER_PD (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_RPU_OPT_Pos (17UL) /*!< RPU_OPT (Bit 17) */ +#define USB_SIE_CTRL_RPU_OPT_Msk (0x20000UL) /*!< RPU_OPT (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_PULLUP_EN_Pos (16UL) /*!< PULLUP_EN (Bit 16) */ +#define USB_SIE_CTRL_PULLUP_EN_Msk (0x10000UL) /*!< PULLUP_EN (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_PULLDOWN_EN_Pos (15UL) /*!< PULLDOWN_EN (Bit 15) */ +#define USB_SIE_CTRL_PULLDOWN_EN_Msk (0x8000UL) /*!< PULLDOWN_EN (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_RESET_BUS_Pos (13UL) /*!< RESET_BUS (Bit 13) */ +#define USB_SIE_CTRL_RESET_BUS_Msk (0x2000UL) /*!< RESET_BUS (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_RESUME_Pos (12UL) /*!< RESUME (Bit 12) */ +#define USB_SIE_CTRL_RESUME_Msk (0x1000UL) /*!< RESUME (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_VBUS_EN_Pos (11UL) /*!< VBUS_EN (Bit 11) */ +#define USB_SIE_CTRL_VBUS_EN_Msk (0x800UL) /*!< VBUS_EN (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_KEEP_ALIVE_EN_Pos (10UL) /*!< KEEP_ALIVE_EN (Bit 10) */ +#define USB_SIE_CTRL_KEEP_ALIVE_EN_Msk (0x400UL) /*!< KEEP_ALIVE_EN (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_SOF_EN_Pos (9UL) /*!< SOF_EN (Bit 9) */ +#define USB_SIE_CTRL_SOF_EN_Msk (0x200UL) /*!< SOF_EN (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_SOF_SYNC_Pos (8UL) /*!< SOF_SYNC (Bit 8) */ +#define USB_SIE_CTRL_SOF_SYNC_Msk (0x100UL) /*!< SOF_SYNC (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_PREAMBLE_EN_Pos (6UL) /*!< PREAMBLE_EN (Bit 6) */ +#define USB_SIE_CTRL_PREAMBLE_EN_Msk (0x40UL) /*!< PREAMBLE_EN (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_STOP_TRANS_Pos (4UL) /*!< STOP_TRANS (Bit 4) */ +#define USB_SIE_CTRL_STOP_TRANS_Msk (0x10UL) /*!< STOP_TRANS (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_RECEIVE_DATA_Pos (3UL) /*!< RECEIVE_DATA (Bit 3) */ +#define USB_SIE_CTRL_RECEIVE_DATA_Msk (0x8UL) /*!< RECEIVE_DATA (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_SEND_DATA_Pos (2UL) /*!< SEND_DATA (Bit 2) */ +#define USB_SIE_CTRL_SEND_DATA_Msk (0x4UL) /*!< SEND_DATA (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_SEND_SETUP_Pos (1UL) /*!< SEND_SETUP (Bit 1) */ +#define USB_SIE_CTRL_SEND_SETUP_Msk (0x2UL) /*!< SEND_SETUP (Bitfield-Mask: 0x01) */ +#define USB_SIE_CTRL_START_TRANS_Pos (0UL) /*!< START_TRANS (Bit 0) */ +#define USB_SIE_CTRL_START_TRANS_Msk (0x1UL) /*!< START_TRANS (Bitfield-Mask: 0x01) */ +/* ====================================================== SIE_STATUS ======================================================= */ +#define USB_SIE_STATUS_DATA_SEQ_ERROR_Pos (31UL) /*!< DATA_SEQ_ERROR (Bit 31) */ +#define USB_SIE_STATUS_DATA_SEQ_ERROR_Msk (0x80000000UL) /*!< DATA_SEQ_ERROR (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_ACK_REC_Pos (30UL) /*!< ACK_REC (Bit 30) */ +#define USB_SIE_STATUS_ACK_REC_Msk (0x40000000UL) /*!< ACK_REC (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_STALL_REC_Pos (29UL) /*!< STALL_REC (Bit 29) */ +#define USB_SIE_STATUS_STALL_REC_Msk (0x20000000UL) /*!< STALL_REC (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_NAK_REC_Pos (28UL) /*!< NAK_REC (Bit 28) */ +#define USB_SIE_STATUS_NAK_REC_Msk (0x10000000UL) /*!< NAK_REC (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_RX_TIMEOUT_Pos (27UL) /*!< RX_TIMEOUT (Bit 27) */ +#define USB_SIE_STATUS_RX_TIMEOUT_Msk (0x8000000UL) /*!< RX_TIMEOUT (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_RX_OVERFLOW_Pos (26UL) /*!< RX_OVERFLOW (Bit 26) */ +#define USB_SIE_STATUS_RX_OVERFLOW_Msk (0x4000000UL) /*!< RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_BIT_STUFF_ERROR_Pos (25UL) /*!< BIT_STUFF_ERROR (Bit 25) */ +#define USB_SIE_STATUS_BIT_STUFF_ERROR_Msk (0x2000000UL) /*!< BIT_STUFF_ERROR (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_CRC_ERROR_Pos (24UL) /*!< CRC_ERROR (Bit 24) */ +#define USB_SIE_STATUS_CRC_ERROR_Msk (0x1000000UL) /*!< CRC_ERROR (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_ENDPOINT_ERROR_Pos (23UL) /*!< ENDPOINT_ERROR (Bit 23) */ +#define USB_SIE_STATUS_ENDPOINT_ERROR_Msk (0x800000UL) /*!< ENDPOINT_ERROR (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_BUS_RESET_Pos (19UL) /*!< BUS_RESET (Bit 19) */ +#define USB_SIE_STATUS_BUS_RESET_Msk (0x80000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_TRANS_COMPLETE_Pos (18UL) /*!< TRANS_COMPLETE (Bit 18) */ +#define USB_SIE_STATUS_TRANS_COMPLETE_Msk (0x40000UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_SETUP_REC_Pos (17UL) /*!< SETUP_REC (Bit 17) */ +#define USB_SIE_STATUS_SETUP_REC_Msk (0x20000UL) /*!< SETUP_REC (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_CONNECTED_Pos (16UL) /*!< CONNECTED (Bit 16) */ +#define USB_SIE_STATUS_CONNECTED_Msk (0x10000UL) /*!< CONNECTED (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_RX_SHORT_PACKET_Pos (12UL) /*!< RX_SHORT_PACKET (Bit 12) */ +#define USB_SIE_STATUS_RX_SHORT_PACKET_Msk (0x1000UL) /*!< RX_SHORT_PACKET (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_RESUME_Pos (11UL) /*!< RESUME (Bit 11) */ +#define USB_SIE_STATUS_RESUME_Msk (0x800UL) /*!< RESUME (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_VBUS_OVER_CURR_Pos (10UL) /*!< VBUS_OVER_CURR (Bit 10) */ +#define USB_SIE_STATUS_VBUS_OVER_CURR_Msk (0x400UL) /*!< VBUS_OVER_CURR (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_SPEED_Pos (8UL) /*!< SPEED (Bit 8) */ +#define USB_SIE_STATUS_SPEED_Msk (0x300UL) /*!< SPEED (Bitfield-Mask: 0x03) */ +#define USB_SIE_STATUS_SUSPENDED_Pos (4UL) /*!< SUSPENDED (Bit 4) */ +#define USB_SIE_STATUS_SUSPENDED_Msk (0x10UL) /*!< SUSPENDED (Bitfield-Mask: 0x01) */ +#define USB_SIE_STATUS_LINE_STATE_Pos (2UL) /*!< LINE_STATE (Bit 2) */ +#define USB_SIE_STATUS_LINE_STATE_Msk (0xcUL) /*!< LINE_STATE (Bitfield-Mask: 0x03) */ +#define USB_SIE_STATUS_VBUS_DETECTED_Pos (0UL) /*!< VBUS_DETECTED (Bit 0) */ +#define USB_SIE_STATUS_VBUS_DETECTED_Msk (0x1UL) /*!< VBUS_DETECTED (Bitfield-Mask: 0x01) */ +/* ====================================================== INT_EP_CTRL ====================================================== */ +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_Pos (1UL) /*!< INT_EP_ACTIVE (Bit 1) */ +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_Msk (0xfffeUL) /*!< INT_EP_ACTIVE (Bitfield-Mask: 0x7fff) */ +/* ====================================================== BUFF_STATUS ====================================================== */ +#define USB_BUFF_STATUS_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */ +#define USB_BUFF_STATUS_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */ +#define USB_BUFF_STATUS_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */ +#define USB_BUFF_STATUS_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */ +#define USB_BUFF_STATUS_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */ +#define USB_BUFF_STATUS_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */ +#define USB_BUFF_STATUS_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */ +#define USB_BUFF_STATUS_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */ +#define USB_BUFF_STATUS_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */ +#define USB_BUFF_STATUS_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */ +#define USB_BUFF_STATUS_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */ +#define USB_BUFF_STATUS_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */ +#define USB_BUFF_STATUS_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */ +#define USB_BUFF_STATUS_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */ +#define USB_BUFF_STATUS_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */ +#define USB_BUFF_STATUS_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */ +#define USB_BUFF_STATUS_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */ +#define USB_BUFF_STATUS_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */ +#define USB_BUFF_STATUS_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */ +#define USB_BUFF_STATUS_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */ +#define USB_BUFF_STATUS_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */ +#define USB_BUFF_STATUS_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */ +#define USB_BUFF_STATUS_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */ +#define USB_BUFF_STATUS_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */ +#define USB_BUFF_STATUS_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */ +#define USB_BUFF_STATUS_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */ +#define USB_BUFF_STATUS_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */ +#define USB_BUFF_STATUS_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */ +#define USB_BUFF_STATUS_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */ +#define USB_BUFF_STATUS_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */ +#define USB_BUFF_STATUS_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */ +#define USB_BUFF_STATUS_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_STATUS_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */ +#define USB_BUFF_STATUS_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */ +/* ================================================ BUFF_CPU_SHOULD_HANDLE ================================================= */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */ +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */ +/* ======================================================= EP_ABORT ======================================================== */ +#define USB_EP_ABORT_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */ +#define USB_EP_ABORT_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */ +#define USB_EP_ABORT_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */ +#define USB_EP_ABORT_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */ +#define USB_EP_ABORT_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */ +#define USB_EP_ABORT_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */ +#define USB_EP_ABORT_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */ +#define USB_EP_ABORT_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */ +#define USB_EP_ABORT_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */ +#define USB_EP_ABORT_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */ +#define USB_EP_ABORT_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */ +#define USB_EP_ABORT_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */ +#define USB_EP_ABORT_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */ +#define USB_EP_ABORT_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */ +#define USB_EP_ABORT_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */ +#define USB_EP_ABORT_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */ +#define USB_EP_ABORT_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */ +#define USB_EP_ABORT_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */ +#define USB_EP_ABORT_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */ +#define USB_EP_ABORT_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */ +#define USB_EP_ABORT_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */ +#define USB_EP_ABORT_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */ +#define USB_EP_ABORT_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */ +#define USB_EP_ABORT_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */ +#define USB_EP_ABORT_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */ +#define USB_EP_ABORT_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */ +#define USB_EP_ABORT_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */ +#define USB_EP_ABORT_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */ +#define USB_EP_ABORT_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */ +#define USB_EP_ABORT_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */ +#define USB_EP_ABORT_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */ +#define USB_EP_ABORT_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */ +#define USB_EP_ABORT_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */ +/* ===================================================== EP_ABORT_DONE ===================================================== */ +#define USB_EP_ABORT_DONE_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */ +#define USB_EP_ABORT_DONE_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */ +#define USB_EP_ABORT_DONE_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */ +#define USB_EP_ABORT_DONE_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */ +#define USB_EP_ABORT_DONE_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */ +#define USB_EP_ABORT_DONE_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */ +#define USB_EP_ABORT_DONE_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */ +#define USB_EP_ABORT_DONE_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */ +#define USB_EP_ABORT_DONE_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */ +#define USB_EP_ABORT_DONE_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */ +#define USB_EP_ABORT_DONE_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */ +#define USB_EP_ABORT_DONE_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */ +#define USB_EP_ABORT_DONE_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */ +#define USB_EP_ABORT_DONE_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */ +#define USB_EP_ABORT_DONE_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */ +#define USB_EP_ABORT_DONE_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */ +#define USB_EP_ABORT_DONE_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */ +#define USB_EP_ABORT_DONE_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */ +#define USB_EP_ABORT_DONE_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */ +#define USB_EP_ABORT_DONE_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */ +#define USB_EP_ABORT_DONE_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */ +#define USB_EP_ABORT_DONE_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */ +#define USB_EP_ABORT_DONE_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */ +#define USB_EP_ABORT_DONE_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */ +#define USB_EP_ABORT_DONE_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */ +#define USB_EP_ABORT_DONE_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */ +#define USB_EP_ABORT_DONE_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */ +#define USB_EP_ABORT_DONE_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */ +#define USB_EP_ABORT_DONE_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */ +#define USB_EP_ABORT_DONE_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */ +#define USB_EP_ABORT_DONE_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */ +#define USB_EP_ABORT_DONE_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_ABORT_DONE_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */ +#define USB_EP_ABORT_DONE_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */ +/* ===================================================== EP_STALL_ARM ====================================================== */ +#define USB_EP_STALL_ARM_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */ +#define USB_EP_STALL_ARM_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STALL_ARM_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */ +#define USB_EP_STALL_ARM_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */ +/* ======================================================= NAK_POLL ======================================================== */ +#define USB_NAK_POLL_RETRY_COUNT_HI_Pos (28UL) /*!< RETRY_COUNT_HI (Bit 28) */ +#define USB_NAK_POLL_RETRY_COUNT_HI_Msk (0xf0000000UL) /*!< RETRY_COUNT_HI (Bitfield-Mask: 0x0f) */ +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_Pos (27UL) /*!< EPX_STOPPED_ON_NAK (Bit 27) */ +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_Msk (0x8000000UL) /*!< EPX_STOPPED_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_NAK_POLL_STOP_EPX_ON_NAK_Pos (26UL) /*!< STOP_EPX_ON_NAK (Bit 26) */ +#define USB_NAK_POLL_STOP_EPX_ON_NAK_Msk (0x4000000UL) /*!< STOP_EPX_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_NAK_POLL_DELAY_FS_Pos (16UL) /*!< DELAY_FS (Bit 16) */ +#define USB_NAK_POLL_DELAY_FS_Msk (0x3ff0000UL) /*!< DELAY_FS (Bitfield-Mask: 0x3ff) */ +#define USB_NAK_POLL_RETRY_COUNT_LO_Pos (10UL) /*!< RETRY_COUNT_LO (Bit 10) */ +#define USB_NAK_POLL_RETRY_COUNT_LO_Msk (0xfc00UL) /*!< RETRY_COUNT_LO (Bitfield-Mask: 0x3f) */ +#define USB_NAK_POLL_DELAY_LS_Pos (0UL) /*!< DELAY_LS (Bit 0) */ +#define USB_NAK_POLL_DELAY_LS_Msk (0x3ffUL) /*!< DELAY_LS (Bitfield-Mask: 0x3ff) */ +/* ================================================== EP_STATUS_STALL_NAK ================================================== */ +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */ +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */ +#define USB_EP_STATUS_STALL_NAK_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */ +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */ +#define USB_EP_STATUS_STALL_NAK_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */ +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */ +#define USB_EP_STATUS_STALL_NAK_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */ +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */ +#define USB_EP_STATUS_STALL_NAK_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */ +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */ +#define USB_EP_STATUS_STALL_NAK_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */ +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */ +#define USB_EP_STATUS_STALL_NAK_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */ +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */ +#define USB_EP_STATUS_STALL_NAK_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */ +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */ +#define USB_EP_STATUS_STALL_NAK_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */ +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */ +#define USB_EP_STATUS_STALL_NAK_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */ +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */ +#define USB_EP_STATUS_STALL_NAK_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */ +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */ +#define USB_EP_STATUS_STALL_NAK_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */ +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */ +#define USB_EP_STATUS_STALL_NAK_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */ +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */ +#define USB_EP_STATUS_STALL_NAK_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */ +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */ +#define USB_EP_STATUS_STALL_NAK_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */ +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */ +#define USB_EP_STATUS_STALL_NAK_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */ +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */ +#define USB_EP_STATUS_STALL_NAK_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */ +#define USB_EP_STATUS_STALL_NAK_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */ +/* ====================================================== USB_MUXING ======================================================= */ +#define USB_USB_MUXING_SWAP_DPDM_Pos (31UL) /*!< SWAP_DPDM (Bit 31) */ +#define USB_USB_MUXING_SWAP_DPDM_Msk (0x80000000UL) /*!< SWAP_DPDM (Bitfield-Mask: 0x01) */ +#define USB_USB_MUXING_USBPHY_AS_GPIO_Pos (4UL) /*!< USBPHY_AS_GPIO (Bit 4) */ +#define USB_USB_MUXING_USBPHY_AS_GPIO_Msk (0x10UL) /*!< USBPHY_AS_GPIO (Bitfield-Mask: 0x01) */ +#define USB_USB_MUXING_SOFTCON_Pos (3UL) /*!< SOFTCON (Bit 3) */ +#define USB_USB_MUXING_SOFTCON_Msk (0x8UL) /*!< SOFTCON (Bitfield-Mask: 0x01) */ +#define USB_USB_MUXING_TO_DIGITAL_PAD_Pos (2UL) /*!< TO_DIGITAL_PAD (Bit 2) */ +#define USB_USB_MUXING_TO_DIGITAL_PAD_Msk (0x4UL) /*!< TO_DIGITAL_PAD (Bitfield-Mask: 0x01) */ +#define USB_USB_MUXING_TO_EXTPHY_Pos (1UL) /*!< TO_EXTPHY (Bit 1) */ +#define USB_USB_MUXING_TO_EXTPHY_Msk (0x2UL) /*!< TO_EXTPHY (Bitfield-Mask: 0x01) */ +#define USB_USB_MUXING_TO_PHY_Pos (0UL) /*!< TO_PHY (Bit 0) */ +#define USB_USB_MUXING_TO_PHY_Msk (0x1UL) /*!< TO_PHY (Bitfield-Mask: 0x01) */ +/* ======================================================== USB_PWR ======================================================== */ +#define USB_USB_PWR_OVERCURR_DETECT_EN_Pos (5UL) /*!< OVERCURR_DETECT_EN (Bit 5) */ +#define USB_USB_PWR_OVERCURR_DETECT_EN_Msk (0x20UL) /*!< OVERCURR_DETECT_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_PWR_OVERCURR_DETECT_Pos (4UL) /*!< OVERCURR_DETECT (Bit 4) */ +#define USB_USB_PWR_OVERCURR_DETECT_Msk (0x10UL) /*!< OVERCURR_DETECT (Bitfield-Mask: 0x01) */ +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_Pos (3UL) /*!< VBUS_DETECT_OVERRIDE_EN (Bit 3) */ +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_Msk (0x8UL) /*!< VBUS_DETECT_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_PWR_VBUS_DETECT_Pos (2UL) /*!< VBUS_DETECT (Bit 2) */ +#define USB_USB_PWR_VBUS_DETECT_Msk (0x4UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */ +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_Pos (1UL) /*!< VBUS_EN_OVERRIDE_EN (Bit 1) */ +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_Msk (0x2UL) /*!< VBUS_EN_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_PWR_VBUS_EN_Pos (0UL) /*!< VBUS_EN (Bit 0) */ +#define USB_USB_PWR_VBUS_EN_Msk (0x1UL) /*!< VBUS_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== USBPHY_DIRECT ===================================================== */ +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_Pos (25UL) /*!< RX_DM_OVERRIDE (Bit 25) */ +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_Msk (0x2000000UL) /*!< RX_DM_OVERRIDE (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_Pos (24UL) /*!< RX_DP_OVERRIDE (Bit 24) */ +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_Msk (0x1000000UL) /*!< RX_DP_OVERRIDE (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_Pos (23UL) /*!< RX_DD_OVERRIDE (Bit 23) */ +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_Msk (0x800000UL) /*!< RX_DD_OVERRIDE (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DM_OVV_Pos (22UL) /*!< DM_OVV (Bit 22) */ +#define USB_USBPHY_DIRECT_DM_OVV_Msk (0x400000UL) /*!< DM_OVV (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DP_OVV_Pos (21UL) /*!< DP_OVV (Bit 21) */ +#define USB_USBPHY_DIRECT_DP_OVV_Msk (0x200000UL) /*!< DP_OVV (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DM_OVCN_Pos (20UL) /*!< DM_OVCN (Bit 20) */ +#define USB_USBPHY_DIRECT_DM_OVCN_Msk (0x100000UL) /*!< DM_OVCN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DP_OVCN_Pos (19UL) /*!< DP_OVCN (Bit 19) */ +#define USB_USBPHY_DIRECT_DP_OVCN_Msk (0x80000UL) /*!< DP_OVCN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_RX_DM_Pos (18UL) /*!< RX_DM (Bit 18) */ +#define USB_USBPHY_DIRECT_RX_DM_Msk (0x40000UL) /*!< RX_DM (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_RX_DP_Pos (17UL) /*!< RX_DP (Bit 17) */ +#define USB_USBPHY_DIRECT_RX_DP_Msk (0x20000UL) /*!< RX_DP (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_RX_DD_Pos (16UL) /*!< RX_DD (Bit 16) */ +#define USB_USBPHY_DIRECT_RX_DD_Msk (0x10000UL) /*!< RX_DD (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_TX_DIFFMODE_Pos (15UL) /*!< TX_DIFFMODE (Bit 15) */ +#define USB_USBPHY_DIRECT_TX_DIFFMODE_Msk (0x8000UL) /*!< TX_DIFFMODE (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_TX_FSSLEW_Pos (14UL) /*!< TX_FSSLEW (Bit 14) */ +#define USB_USBPHY_DIRECT_TX_FSSLEW_Msk (0x4000UL) /*!< TX_FSSLEW (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_TX_PD_Pos (13UL) /*!< TX_PD (Bit 13) */ +#define USB_USBPHY_DIRECT_TX_PD_Msk (0x2000UL) /*!< TX_PD (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_RX_PD_Pos (12UL) /*!< RX_PD (Bit 12) */ +#define USB_USBPHY_DIRECT_RX_PD_Msk (0x1000UL) /*!< RX_PD (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_TX_DM_Pos (11UL) /*!< TX_DM (Bit 11) */ +#define USB_USBPHY_DIRECT_TX_DM_Msk (0x800UL) /*!< TX_DM (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_TX_DP_Pos (10UL) /*!< TX_DP (Bit 10) */ +#define USB_USBPHY_DIRECT_TX_DP_Msk (0x400UL) /*!< TX_DP (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_TX_DM_OE_Pos (9UL) /*!< TX_DM_OE (Bit 9) */ +#define USB_USBPHY_DIRECT_TX_DM_OE_Msk (0x200UL) /*!< TX_DM_OE (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_TX_DP_OE_Pos (8UL) /*!< TX_DP_OE (Bit 8) */ +#define USB_USBPHY_DIRECT_TX_DP_OE_Msk (0x100UL) /*!< TX_DP_OE (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_Pos (6UL) /*!< DM_PULLDN_EN (Bit 6) */ +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_Msk (0x40UL) /*!< DM_PULLDN_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_Pos (5UL) /*!< DM_PULLUP_EN (Bit 5) */ +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_Msk (0x20UL) /*!< DM_PULLUP_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_Pos (4UL) /*!< DM_PULLUP_HISEL (Bit 4) */ +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_Msk (0x10UL) /*!< DM_PULLUP_HISEL (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_Pos (2UL) /*!< DP_PULLDN_EN (Bit 2) */ +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_Msk (0x4UL) /*!< DP_PULLDN_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_Pos (1UL) /*!< DP_PULLUP_EN (Bit 1) */ +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_Msk (0x2UL) /*!< DP_PULLUP_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_Pos (0UL) /*!< DP_PULLUP_HISEL (Bit 0) */ +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_Msk (0x1UL) /*!< DP_PULLUP_HISEL (Bitfield-Mask: 0x01) */ +/* ================================================ USBPHY_DIRECT_OVERRIDE ================================================= */ +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_Pos (18UL) /*!< RX_DM_OVERRIDE_EN (Bit 18) */ +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_Msk (0x40000UL) /*!< RX_DM_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_Pos (17UL) /*!< RX_DP_OVERRIDE_EN (Bit 17) */ +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_Msk (0x20000UL) /*!< RX_DP_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_Pos (16UL) /*!< RX_DD_OVERRIDE_EN (Bit 16) */ +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_Msk (0x10000UL) /*!< RX_DD_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_Pos (15UL) /*!< TX_DIFFMODE_OVERRIDE_EN (Bit 15) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_Msk (0x8000UL) /*!< TX_DIFFMODE_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_Pos (12UL) /*!< DM_PULLUP_OVERRIDE_EN (Bit 12) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_Msk (0x1000UL) /*!< DM_PULLUP_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_Pos (11UL) /*!< TX_FSSLEW_OVERRIDE_EN (Bit 11) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_Msk (0x800UL) /*!< TX_FSSLEW_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_Pos (10UL) /*!< TX_PD_OVERRIDE_EN (Bit 10) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_Msk (0x400UL) /*!< TX_PD_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_Pos (9UL) /*!< RX_PD_OVERRIDE_EN (Bit 9) */ +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_Msk (0x200UL) /*!< RX_PD_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_Pos (8UL) /*!< TX_DM_OVERRIDE_EN (Bit 8) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_Msk (0x100UL) /*!< TX_DM_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_Pos (7UL) /*!< TX_DP_OVERRIDE_EN (Bit 7) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_Msk (0x80UL) /*!< TX_DP_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_Pos (6UL) /*!< TX_DM_OE_OVERRIDE_EN (Bit 6) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_Msk (0x40UL) /*!< TX_DM_OE_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_Pos (5UL) /*!< TX_DP_OE_OVERRIDE_EN (Bit 5) */ +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_Msk (0x20UL) /*!< TX_DP_OE_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_Pos (4UL) /*!< DM_PULLDN_EN_OVERRIDE_EN (Bit 4) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_Msk (0x10UL) /*!< DM_PULLDN_EN_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_Pos (3UL) /*!< DP_PULLDN_EN_OVERRIDE_EN (Bit 3) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_Msk (0x8UL) /*!< DP_PULLDN_EN_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_Pos (2UL) /*!< DP_PULLUP_EN_OVERRIDE_EN (Bit 2) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_Msk (0x4UL) /*!< DP_PULLUP_EN_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_Pos (1UL) /*!< DM_PULLUP_HISEL_OVERRIDE_EN (Bit 1) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_Msk (0x2UL) /*!< DM_PULLUP_HISEL_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_Pos (0UL) /*!< DP_PULLUP_HISEL_OVERRIDE_EN (Bit 0) */ +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_Msk (0x1UL) /*!< DP_PULLUP_HISEL_OVERRIDE_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== USBPHY_TRIM ====================================================== */ +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_Pos (8UL) /*!< DM_PULLDN_TRIM (Bit 8) */ +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_Msk (0x1f00UL) /*!< DM_PULLDN_TRIM (Bitfield-Mask: 0x1f) */ +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_Pos (0UL) /*!< DP_PULLDN_TRIM (Bit 0) */ +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_Msk (0x1fUL) /*!< DP_PULLDN_TRIM (Bitfield-Mask: 0x1f) */ +/* =================================================== LINESTATE_TUNING ==================================================== */ +#define USB_LINESTATE_TUNING_SPARE_FIX_Pos (8UL) /*!< SPARE_FIX (Bit 8) */ +#define USB_LINESTATE_TUNING_SPARE_FIX_Msk (0xf00UL) /*!< SPARE_FIX (Bitfield-Mask: 0x0f) */ +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_Pos (7UL) /*!< DEV_LS_WAKE_FIX (Bit 7) */ +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_Msk (0x80UL) /*!< DEV_LS_WAKE_FIX (Bitfield-Mask: 0x01) */ +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_Pos (6UL) /*!< DEV_RX_ERR_QUIESCE (Bit 6) */ +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_Msk (0x40UL) /*!< DEV_RX_ERR_QUIESCE (Bitfield-Mask: 0x01) */ +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_Pos (5UL) /*!< SIE_RX_CHATTER_SE0_FIX (Bit 5) */ +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_Msk (0x20UL) /*!< SIE_RX_CHATTER_SE0_FIX (Bitfield-Mask: 0x01) */ +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_Pos (4UL) /*!< SIE_RX_BITSTUFF_FIX (Bit 4) */ +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_Msk (0x10UL) /*!< SIE_RX_BITSTUFF_FIX (Bitfield-Mask: 0x01) */ +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_Pos (3UL) /*!< DEV_BUFF_CONTROL_DOUBLE_READ_FIX (Bit 3) */ +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_Msk (0x8UL) /*!< DEV_BUFF_CONTROL_DOUBLE_READ_FIX (Bitfield-Mask: 0x01) */ +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_Pos (2UL) /*!< MULTI_HUB_FIX (Bit 2) */ +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_Msk (0x4UL) /*!< MULTI_HUB_FIX (Bitfield-Mask: 0x01) */ +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_Pos (1UL) /*!< LINESTATE_DELAY (Bit 1) */ +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_Msk (0x2UL) /*!< LINESTATE_DELAY (Bitfield-Mask: 0x01) */ +#define USB_LINESTATE_TUNING_RCV_DELAY_Pos (0UL) /*!< RCV_DELAY (Bit 0) */ +#define USB_LINESTATE_TUNING_RCV_DELAY_Msk (0x1UL) /*!< RCV_DELAY (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR ========================================================== */ +#define USB_INTR_EPX_STOPPED_ON_NAK_Pos (23UL) /*!< EPX_STOPPED_ON_NAK (Bit 23) */ +#define USB_INTR_EPX_STOPPED_ON_NAK_Msk (0x800000UL) /*!< EPX_STOPPED_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_Pos (22UL) /*!< DEV_SM_WATCHDOG_FIRED (Bit 22) */ +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_Msk (0x400000UL) /*!< DEV_SM_WATCHDOG_FIRED (Bitfield-Mask: 0x01) */ +#define USB_INTR_ENDPOINT_ERROR_Pos (21UL) /*!< ENDPOINT_ERROR (Bit 21) */ +#define USB_INTR_ENDPOINT_ERROR_Msk (0x200000UL) /*!< ENDPOINT_ERROR (Bitfield-Mask: 0x01) */ +#define USB_INTR_RX_SHORT_PACKET_Pos (20UL) /*!< RX_SHORT_PACKET (Bit 20) */ +#define USB_INTR_RX_SHORT_PACKET_Msk (0x100000UL) /*!< RX_SHORT_PACKET (Bitfield-Mask: 0x01) */ +#define USB_INTR_EP_STALL_NAK_Pos (19UL) /*!< EP_STALL_NAK (Bit 19) */ +#define USB_INTR_EP_STALL_NAK_Msk (0x80000UL) /*!< EP_STALL_NAK (Bitfield-Mask: 0x01) */ +#define USB_INTR_ABORT_DONE_Pos (18UL) /*!< ABORT_DONE (Bit 18) */ +#define USB_INTR_ABORT_DONE_Msk (0x40000UL) /*!< ABORT_DONE (Bitfield-Mask: 0x01) */ +#define USB_INTR_DEV_SOF_Pos (17UL) /*!< DEV_SOF (Bit 17) */ +#define USB_INTR_DEV_SOF_Msk (0x20000UL) /*!< DEV_SOF (Bitfield-Mask: 0x01) */ +#define USB_INTR_SETUP_REQ_Pos (16UL) /*!< SETUP_REQ (Bit 16) */ +#define USB_INTR_SETUP_REQ_Msk (0x10000UL) /*!< SETUP_REQ (Bitfield-Mask: 0x01) */ +#define USB_INTR_DEV_RESUME_FROM_HOST_Pos (15UL) /*!< DEV_RESUME_FROM_HOST (Bit 15) */ +#define USB_INTR_DEV_RESUME_FROM_HOST_Msk (0x8000UL) /*!< DEV_RESUME_FROM_HOST (Bitfield-Mask: 0x01) */ +#define USB_INTR_DEV_SUSPEND_Pos (14UL) /*!< DEV_SUSPEND (Bit 14) */ +#define USB_INTR_DEV_SUSPEND_Msk (0x4000UL) /*!< DEV_SUSPEND (Bitfield-Mask: 0x01) */ +#define USB_INTR_DEV_CONN_DIS_Pos (13UL) /*!< DEV_CONN_DIS (Bit 13) */ +#define USB_INTR_DEV_CONN_DIS_Msk (0x2000UL) /*!< DEV_CONN_DIS (Bitfield-Mask: 0x01) */ +#define USB_INTR_BUS_RESET_Pos (12UL) /*!< BUS_RESET (Bit 12) */ +#define USB_INTR_BUS_RESET_Msk (0x1000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */ +#define USB_INTR_VBUS_DETECT_Pos (11UL) /*!< VBUS_DETECT (Bit 11) */ +#define USB_INTR_VBUS_DETECT_Msk (0x800UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */ +#define USB_INTR_STALL_Pos (10UL) /*!< STALL (Bit 10) */ +#define USB_INTR_STALL_Msk (0x400UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_INTR_ERROR_CRC_Pos (9UL) /*!< ERROR_CRC (Bit 9) */ +#define USB_INTR_ERROR_CRC_Msk (0x200UL) /*!< ERROR_CRC (Bitfield-Mask: 0x01) */ +#define USB_INTR_ERROR_BIT_STUFF_Pos (8UL) /*!< ERROR_BIT_STUFF (Bit 8) */ +#define USB_INTR_ERROR_BIT_STUFF_Msk (0x100UL) /*!< ERROR_BIT_STUFF (Bitfield-Mask: 0x01) */ +#define USB_INTR_ERROR_RX_OVERFLOW_Pos (7UL) /*!< ERROR_RX_OVERFLOW (Bit 7) */ +#define USB_INTR_ERROR_RX_OVERFLOW_Msk (0x80UL) /*!< ERROR_RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define USB_INTR_ERROR_RX_TIMEOUT_Pos (6UL) /*!< ERROR_RX_TIMEOUT (Bit 6) */ +#define USB_INTR_ERROR_RX_TIMEOUT_Msk (0x40UL) /*!< ERROR_RX_TIMEOUT (Bitfield-Mask: 0x01) */ +#define USB_INTR_ERROR_DATA_SEQ_Pos (5UL) /*!< ERROR_DATA_SEQ (Bit 5) */ +#define USB_INTR_ERROR_DATA_SEQ_Msk (0x20UL) /*!< ERROR_DATA_SEQ (Bitfield-Mask: 0x01) */ +#define USB_INTR_BUFF_STATUS_Pos (4UL) /*!< BUFF_STATUS (Bit 4) */ +#define USB_INTR_BUFF_STATUS_Msk (0x10UL) /*!< BUFF_STATUS (Bitfield-Mask: 0x01) */ +#define USB_INTR_TRANS_COMPLETE_Pos (3UL) /*!< TRANS_COMPLETE (Bit 3) */ +#define USB_INTR_TRANS_COMPLETE_Msk (0x8UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */ +#define USB_INTR_HOST_SOF_Pos (2UL) /*!< HOST_SOF (Bit 2) */ +#define USB_INTR_HOST_SOF_Msk (0x4UL) /*!< HOST_SOF (Bitfield-Mask: 0x01) */ +#define USB_INTR_HOST_RESUME_Pos (1UL) /*!< HOST_RESUME (Bit 1) */ +#define USB_INTR_HOST_RESUME_Msk (0x2UL) /*!< HOST_RESUME (Bitfield-Mask: 0x01) */ +#define USB_INTR_HOST_CONN_DIS_Pos (0UL) /*!< HOST_CONN_DIS (Bit 0) */ +#define USB_INTR_HOST_CONN_DIS_Msk (0x1UL) /*!< HOST_CONN_DIS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ +#define USB_INTE_EPX_STOPPED_ON_NAK_Pos (23UL) /*!< EPX_STOPPED_ON_NAK (Bit 23) */ +#define USB_INTE_EPX_STOPPED_ON_NAK_Msk (0x800000UL) /*!< EPX_STOPPED_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_Pos (22UL) /*!< DEV_SM_WATCHDOG_FIRED (Bit 22) */ +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_Msk (0x400000UL) /*!< DEV_SM_WATCHDOG_FIRED (Bitfield-Mask: 0x01) */ +#define USB_INTE_ENDPOINT_ERROR_Pos (21UL) /*!< ENDPOINT_ERROR (Bit 21) */ +#define USB_INTE_ENDPOINT_ERROR_Msk (0x200000UL) /*!< ENDPOINT_ERROR (Bitfield-Mask: 0x01) */ +#define USB_INTE_RX_SHORT_PACKET_Pos (20UL) /*!< RX_SHORT_PACKET (Bit 20) */ +#define USB_INTE_RX_SHORT_PACKET_Msk (0x100000UL) /*!< RX_SHORT_PACKET (Bitfield-Mask: 0x01) */ +#define USB_INTE_EP_STALL_NAK_Pos (19UL) /*!< EP_STALL_NAK (Bit 19) */ +#define USB_INTE_EP_STALL_NAK_Msk (0x80000UL) /*!< EP_STALL_NAK (Bitfield-Mask: 0x01) */ +#define USB_INTE_ABORT_DONE_Pos (18UL) /*!< ABORT_DONE (Bit 18) */ +#define USB_INTE_ABORT_DONE_Msk (0x40000UL) /*!< ABORT_DONE (Bitfield-Mask: 0x01) */ +#define USB_INTE_DEV_SOF_Pos (17UL) /*!< DEV_SOF (Bit 17) */ +#define USB_INTE_DEV_SOF_Msk (0x20000UL) /*!< DEV_SOF (Bitfield-Mask: 0x01) */ +#define USB_INTE_SETUP_REQ_Pos (16UL) /*!< SETUP_REQ (Bit 16) */ +#define USB_INTE_SETUP_REQ_Msk (0x10000UL) /*!< SETUP_REQ (Bitfield-Mask: 0x01) */ +#define USB_INTE_DEV_RESUME_FROM_HOST_Pos (15UL) /*!< DEV_RESUME_FROM_HOST (Bit 15) */ +#define USB_INTE_DEV_RESUME_FROM_HOST_Msk (0x8000UL) /*!< DEV_RESUME_FROM_HOST (Bitfield-Mask: 0x01) */ +#define USB_INTE_DEV_SUSPEND_Pos (14UL) /*!< DEV_SUSPEND (Bit 14) */ +#define USB_INTE_DEV_SUSPEND_Msk (0x4000UL) /*!< DEV_SUSPEND (Bitfield-Mask: 0x01) */ +#define USB_INTE_DEV_CONN_DIS_Pos (13UL) /*!< DEV_CONN_DIS (Bit 13) */ +#define USB_INTE_DEV_CONN_DIS_Msk (0x2000UL) /*!< DEV_CONN_DIS (Bitfield-Mask: 0x01) */ +#define USB_INTE_BUS_RESET_Pos (12UL) /*!< BUS_RESET (Bit 12) */ +#define USB_INTE_BUS_RESET_Msk (0x1000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */ +#define USB_INTE_VBUS_DETECT_Pos (11UL) /*!< VBUS_DETECT (Bit 11) */ +#define USB_INTE_VBUS_DETECT_Msk (0x800UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */ +#define USB_INTE_STALL_Pos (10UL) /*!< STALL (Bit 10) */ +#define USB_INTE_STALL_Msk (0x400UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_INTE_ERROR_CRC_Pos (9UL) /*!< ERROR_CRC (Bit 9) */ +#define USB_INTE_ERROR_CRC_Msk (0x200UL) /*!< ERROR_CRC (Bitfield-Mask: 0x01) */ +#define USB_INTE_ERROR_BIT_STUFF_Pos (8UL) /*!< ERROR_BIT_STUFF (Bit 8) */ +#define USB_INTE_ERROR_BIT_STUFF_Msk (0x100UL) /*!< ERROR_BIT_STUFF (Bitfield-Mask: 0x01) */ +#define USB_INTE_ERROR_RX_OVERFLOW_Pos (7UL) /*!< ERROR_RX_OVERFLOW (Bit 7) */ +#define USB_INTE_ERROR_RX_OVERFLOW_Msk (0x80UL) /*!< ERROR_RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define USB_INTE_ERROR_RX_TIMEOUT_Pos (6UL) /*!< ERROR_RX_TIMEOUT (Bit 6) */ +#define USB_INTE_ERROR_RX_TIMEOUT_Msk (0x40UL) /*!< ERROR_RX_TIMEOUT (Bitfield-Mask: 0x01) */ +#define USB_INTE_ERROR_DATA_SEQ_Pos (5UL) /*!< ERROR_DATA_SEQ (Bit 5) */ +#define USB_INTE_ERROR_DATA_SEQ_Msk (0x20UL) /*!< ERROR_DATA_SEQ (Bitfield-Mask: 0x01) */ +#define USB_INTE_BUFF_STATUS_Pos (4UL) /*!< BUFF_STATUS (Bit 4) */ +#define USB_INTE_BUFF_STATUS_Msk (0x10UL) /*!< BUFF_STATUS (Bitfield-Mask: 0x01) */ +#define USB_INTE_TRANS_COMPLETE_Pos (3UL) /*!< TRANS_COMPLETE (Bit 3) */ +#define USB_INTE_TRANS_COMPLETE_Msk (0x8UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */ +#define USB_INTE_HOST_SOF_Pos (2UL) /*!< HOST_SOF (Bit 2) */ +#define USB_INTE_HOST_SOF_Msk (0x4UL) /*!< HOST_SOF (Bitfield-Mask: 0x01) */ +#define USB_INTE_HOST_RESUME_Pos (1UL) /*!< HOST_RESUME (Bit 1) */ +#define USB_INTE_HOST_RESUME_Msk (0x2UL) /*!< HOST_RESUME (Bitfield-Mask: 0x01) */ +#define USB_INTE_HOST_CONN_DIS_Pos (0UL) /*!< HOST_CONN_DIS (Bit 0) */ +#define USB_INTE_HOST_CONN_DIS_Msk (0x1UL) /*!< HOST_CONN_DIS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define USB_INTF_EPX_STOPPED_ON_NAK_Pos (23UL) /*!< EPX_STOPPED_ON_NAK (Bit 23) */ +#define USB_INTF_EPX_STOPPED_ON_NAK_Msk (0x800000UL) /*!< EPX_STOPPED_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_Pos (22UL) /*!< DEV_SM_WATCHDOG_FIRED (Bit 22) */ +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_Msk (0x400000UL) /*!< DEV_SM_WATCHDOG_FIRED (Bitfield-Mask: 0x01) */ +#define USB_INTF_ENDPOINT_ERROR_Pos (21UL) /*!< ENDPOINT_ERROR (Bit 21) */ +#define USB_INTF_ENDPOINT_ERROR_Msk (0x200000UL) /*!< ENDPOINT_ERROR (Bitfield-Mask: 0x01) */ +#define USB_INTF_RX_SHORT_PACKET_Pos (20UL) /*!< RX_SHORT_PACKET (Bit 20) */ +#define USB_INTF_RX_SHORT_PACKET_Msk (0x100000UL) /*!< RX_SHORT_PACKET (Bitfield-Mask: 0x01) */ +#define USB_INTF_EP_STALL_NAK_Pos (19UL) /*!< EP_STALL_NAK (Bit 19) */ +#define USB_INTF_EP_STALL_NAK_Msk (0x80000UL) /*!< EP_STALL_NAK (Bitfield-Mask: 0x01) */ +#define USB_INTF_ABORT_DONE_Pos (18UL) /*!< ABORT_DONE (Bit 18) */ +#define USB_INTF_ABORT_DONE_Msk (0x40000UL) /*!< ABORT_DONE (Bitfield-Mask: 0x01) */ +#define USB_INTF_DEV_SOF_Pos (17UL) /*!< DEV_SOF (Bit 17) */ +#define USB_INTF_DEV_SOF_Msk (0x20000UL) /*!< DEV_SOF (Bitfield-Mask: 0x01) */ +#define USB_INTF_SETUP_REQ_Pos (16UL) /*!< SETUP_REQ (Bit 16) */ +#define USB_INTF_SETUP_REQ_Msk (0x10000UL) /*!< SETUP_REQ (Bitfield-Mask: 0x01) */ +#define USB_INTF_DEV_RESUME_FROM_HOST_Pos (15UL) /*!< DEV_RESUME_FROM_HOST (Bit 15) */ +#define USB_INTF_DEV_RESUME_FROM_HOST_Msk (0x8000UL) /*!< DEV_RESUME_FROM_HOST (Bitfield-Mask: 0x01) */ +#define USB_INTF_DEV_SUSPEND_Pos (14UL) /*!< DEV_SUSPEND (Bit 14) */ +#define USB_INTF_DEV_SUSPEND_Msk (0x4000UL) /*!< DEV_SUSPEND (Bitfield-Mask: 0x01) */ +#define USB_INTF_DEV_CONN_DIS_Pos (13UL) /*!< DEV_CONN_DIS (Bit 13) */ +#define USB_INTF_DEV_CONN_DIS_Msk (0x2000UL) /*!< DEV_CONN_DIS (Bitfield-Mask: 0x01) */ +#define USB_INTF_BUS_RESET_Pos (12UL) /*!< BUS_RESET (Bit 12) */ +#define USB_INTF_BUS_RESET_Msk (0x1000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */ +#define USB_INTF_VBUS_DETECT_Pos (11UL) /*!< VBUS_DETECT (Bit 11) */ +#define USB_INTF_VBUS_DETECT_Msk (0x800UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */ +#define USB_INTF_STALL_Pos (10UL) /*!< STALL (Bit 10) */ +#define USB_INTF_STALL_Msk (0x400UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_INTF_ERROR_CRC_Pos (9UL) /*!< ERROR_CRC (Bit 9) */ +#define USB_INTF_ERROR_CRC_Msk (0x200UL) /*!< ERROR_CRC (Bitfield-Mask: 0x01) */ +#define USB_INTF_ERROR_BIT_STUFF_Pos (8UL) /*!< ERROR_BIT_STUFF (Bit 8) */ +#define USB_INTF_ERROR_BIT_STUFF_Msk (0x100UL) /*!< ERROR_BIT_STUFF (Bitfield-Mask: 0x01) */ +#define USB_INTF_ERROR_RX_OVERFLOW_Pos (7UL) /*!< ERROR_RX_OVERFLOW (Bit 7) */ +#define USB_INTF_ERROR_RX_OVERFLOW_Msk (0x80UL) /*!< ERROR_RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define USB_INTF_ERROR_RX_TIMEOUT_Pos (6UL) /*!< ERROR_RX_TIMEOUT (Bit 6) */ +#define USB_INTF_ERROR_RX_TIMEOUT_Msk (0x40UL) /*!< ERROR_RX_TIMEOUT (Bitfield-Mask: 0x01) */ +#define USB_INTF_ERROR_DATA_SEQ_Pos (5UL) /*!< ERROR_DATA_SEQ (Bit 5) */ +#define USB_INTF_ERROR_DATA_SEQ_Msk (0x20UL) /*!< ERROR_DATA_SEQ (Bitfield-Mask: 0x01) */ +#define USB_INTF_BUFF_STATUS_Pos (4UL) /*!< BUFF_STATUS (Bit 4) */ +#define USB_INTF_BUFF_STATUS_Msk (0x10UL) /*!< BUFF_STATUS (Bitfield-Mask: 0x01) */ +#define USB_INTF_TRANS_COMPLETE_Pos (3UL) /*!< TRANS_COMPLETE (Bit 3) */ +#define USB_INTF_TRANS_COMPLETE_Msk (0x8UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */ +#define USB_INTF_HOST_SOF_Pos (2UL) /*!< HOST_SOF (Bit 2) */ +#define USB_INTF_HOST_SOF_Msk (0x4UL) /*!< HOST_SOF (Bitfield-Mask: 0x01) */ +#define USB_INTF_HOST_RESUME_Pos (1UL) /*!< HOST_RESUME (Bit 1) */ +#define USB_INTF_HOST_RESUME_Msk (0x2UL) /*!< HOST_RESUME (Bitfield-Mask: 0x01) */ +#define USB_INTF_HOST_CONN_DIS_Pos (0UL) /*!< HOST_CONN_DIS (Bit 0) */ +#define USB_INTF_HOST_CONN_DIS_Msk (0x1UL) /*!< HOST_CONN_DIS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ +#define USB_INTS_EPX_STOPPED_ON_NAK_Pos (23UL) /*!< EPX_STOPPED_ON_NAK (Bit 23) */ +#define USB_INTS_EPX_STOPPED_ON_NAK_Msk (0x800000UL) /*!< EPX_STOPPED_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_Pos (22UL) /*!< DEV_SM_WATCHDOG_FIRED (Bit 22) */ +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_Msk (0x400000UL) /*!< DEV_SM_WATCHDOG_FIRED (Bitfield-Mask: 0x01) */ +#define USB_INTS_ENDPOINT_ERROR_Pos (21UL) /*!< ENDPOINT_ERROR (Bit 21) */ +#define USB_INTS_ENDPOINT_ERROR_Msk (0x200000UL) /*!< ENDPOINT_ERROR (Bitfield-Mask: 0x01) */ +#define USB_INTS_RX_SHORT_PACKET_Pos (20UL) /*!< RX_SHORT_PACKET (Bit 20) */ +#define USB_INTS_RX_SHORT_PACKET_Msk (0x100000UL) /*!< RX_SHORT_PACKET (Bitfield-Mask: 0x01) */ +#define USB_INTS_EP_STALL_NAK_Pos (19UL) /*!< EP_STALL_NAK (Bit 19) */ +#define USB_INTS_EP_STALL_NAK_Msk (0x80000UL) /*!< EP_STALL_NAK (Bitfield-Mask: 0x01) */ +#define USB_INTS_ABORT_DONE_Pos (18UL) /*!< ABORT_DONE (Bit 18) */ +#define USB_INTS_ABORT_DONE_Msk (0x40000UL) /*!< ABORT_DONE (Bitfield-Mask: 0x01) */ +#define USB_INTS_DEV_SOF_Pos (17UL) /*!< DEV_SOF (Bit 17) */ +#define USB_INTS_DEV_SOF_Msk (0x20000UL) /*!< DEV_SOF (Bitfield-Mask: 0x01) */ +#define USB_INTS_SETUP_REQ_Pos (16UL) /*!< SETUP_REQ (Bit 16) */ +#define USB_INTS_SETUP_REQ_Msk (0x10000UL) /*!< SETUP_REQ (Bitfield-Mask: 0x01) */ +#define USB_INTS_DEV_RESUME_FROM_HOST_Pos (15UL) /*!< DEV_RESUME_FROM_HOST (Bit 15) */ +#define USB_INTS_DEV_RESUME_FROM_HOST_Msk (0x8000UL) /*!< DEV_RESUME_FROM_HOST (Bitfield-Mask: 0x01) */ +#define USB_INTS_DEV_SUSPEND_Pos (14UL) /*!< DEV_SUSPEND (Bit 14) */ +#define USB_INTS_DEV_SUSPEND_Msk (0x4000UL) /*!< DEV_SUSPEND (Bitfield-Mask: 0x01) */ +#define USB_INTS_DEV_CONN_DIS_Pos (13UL) /*!< DEV_CONN_DIS (Bit 13) */ +#define USB_INTS_DEV_CONN_DIS_Msk (0x2000UL) /*!< DEV_CONN_DIS (Bitfield-Mask: 0x01) */ +#define USB_INTS_BUS_RESET_Pos (12UL) /*!< BUS_RESET (Bit 12) */ +#define USB_INTS_BUS_RESET_Msk (0x1000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */ +#define USB_INTS_VBUS_DETECT_Pos (11UL) /*!< VBUS_DETECT (Bit 11) */ +#define USB_INTS_VBUS_DETECT_Msk (0x800UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */ +#define USB_INTS_STALL_Pos (10UL) /*!< STALL (Bit 10) */ +#define USB_INTS_STALL_Msk (0x400UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_INTS_ERROR_CRC_Pos (9UL) /*!< ERROR_CRC (Bit 9) */ +#define USB_INTS_ERROR_CRC_Msk (0x200UL) /*!< ERROR_CRC (Bitfield-Mask: 0x01) */ +#define USB_INTS_ERROR_BIT_STUFF_Pos (8UL) /*!< ERROR_BIT_STUFF (Bit 8) */ +#define USB_INTS_ERROR_BIT_STUFF_Msk (0x100UL) /*!< ERROR_BIT_STUFF (Bitfield-Mask: 0x01) */ +#define USB_INTS_ERROR_RX_OVERFLOW_Pos (7UL) /*!< ERROR_RX_OVERFLOW (Bit 7) */ +#define USB_INTS_ERROR_RX_OVERFLOW_Msk (0x80UL) /*!< ERROR_RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define USB_INTS_ERROR_RX_TIMEOUT_Pos (6UL) /*!< ERROR_RX_TIMEOUT (Bit 6) */ +#define USB_INTS_ERROR_RX_TIMEOUT_Msk (0x40UL) /*!< ERROR_RX_TIMEOUT (Bitfield-Mask: 0x01) */ +#define USB_INTS_ERROR_DATA_SEQ_Pos (5UL) /*!< ERROR_DATA_SEQ (Bit 5) */ +#define USB_INTS_ERROR_DATA_SEQ_Msk (0x20UL) /*!< ERROR_DATA_SEQ (Bitfield-Mask: 0x01) */ +#define USB_INTS_BUFF_STATUS_Pos (4UL) /*!< BUFF_STATUS (Bit 4) */ +#define USB_INTS_BUFF_STATUS_Msk (0x10UL) /*!< BUFF_STATUS (Bitfield-Mask: 0x01) */ +#define USB_INTS_TRANS_COMPLETE_Pos (3UL) /*!< TRANS_COMPLETE (Bit 3) */ +#define USB_INTS_TRANS_COMPLETE_Msk (0x8UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */ +#define USB_INTS_HOST_SOF_Pos (2UL) /*!< HOST_SOF (Bit 2) */ +#define USB_INTS_HOST_SOF_Msk (0x4UL) /*!< HOST_SOF (Bitfield-Mask: 0x01) */ +#define USB_INTS_HOST_RESUME_Pos (1UL) /*!< HOST_RESUME (Bit 1) */ +#define USB_INTS_HOST_RESUME_Msk (0x2UL) /*!< HOST_RESUME (Bitfield-Mask: 0x01) */ +#define USB_INTS_HOST_CONN_DIS_Pos (0UL) /*!< HOST_CONN_DIS (Bit 0) */ +#define USB_INTS_HOST_CONN_DIS_Msk (0x1UL) /*!< HOST_CONN_DIS (Bitfield-Mask: 0x01) */ +/* =================================================== SOF_TIMESTAMP_RAW =================================================== */ +#define USB_SOF_TIMESTAMP_RAW_SOF_TIMESTAMP_RAW_Pos (0UL) /*!< SOF_TIMESTAMP_RAW (Bit 0) */ +#define USB_SOF_TIMESTAMP_RAW_SOF_TIMESTAMP_RAW_Msk (0x1fffffUL) /*!< SOF_TIMESTAMP_RAW (Bitfield-Mask: 0x1fffff) */ +/* ================================================== SOF_TIMESTAMP_LAST =================================================== */ +#define USB_SOF_TIMESTAMP_LAST_SOF_TIMESTAMP_LAST_Pos (0UL) /*!< SOF_TIMESTAMP_LAST (Bit 0) */ +#define USB_SOF_TIMESTAMP_LAST_SOF_TIMESTAMP_LAST_Msk (0x1fffffUL) /*!< SOF_TIMESTAMP_LAST (Bitfield-Mask: 0x1fffff) */ +/* ======================================================= SM_STATE ======================================================== */ +#define USB_SM_STATE_RX_DASM_Pos (8UL) /*!< RX_DASM (Bit 8) */ +#define USB_SM_STATE_RX_DASM_Msk (0xf00UL) /*!< RX_DASM (Bitfield-Mask: 0x0f) */ +#define USB_SM_STATE_BC_STATE_Pos (5UL) /*!< BC_STATE (Bit 5) */ +#define USB_SM_STATE_BC_STATE_Msk (0xe0UL) /*!< BC_STATE (Bitfield-Mask: 0x07) */ +#define USB_SM_STATE_STATE_Pos (0UL) /*!< STATE (Bit 0) */ +#define USB_SM_STATE_STATE_Msk (0x1fUL) /*!< STATE (Bitfield-Mask: 0x1f) */ +/* ====================================================== EP_TX_ERROR ====================================================== */ +#define USB_EP_TX_ERROR_EP15_Pos (30UL) /*!< EP15 (Bit 30) */ +#define USB_EP_TX_ERROR_EP15_Msk (0xc0000000UL) /*!< EP15 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP14_Pos (28UL) /*!< EP14 (Bit 28) */ +#define USB_EP_TX_ERROR_EP14_Msk (0x30000000UL) /*!< EP14 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP13_Pos (26UL) /*!< EP13 (Bit 26) */ +#define USB_EP_TX_ERROR_EP13_Msk (0xc000000UL) /*!< EP13 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP12_Pos (24UL) /*!< EP12 (Bit 24) */ +#define USB_EP_TX_ERROR_EP12_Msk (0x3000000UL) /*!< EP12 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP11_Pos (22UL) /*!< EP11 (Bit 22) */ +#define USB_EP_TX_ERROR_EP11_Msk (0xc00000UL) /*!< EP11 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP10_Pos (20UL) /*!< EP10 (Bit 20) */ +#define USB_EP_TX_ERROR_EP10_Msk (0x300000UL) /*!< EP10 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP9_Pos (18UL) /*!< EP9 (Bit 18) */ +#define USB_EP_TX_ERROR_EP9_Msk (0xc0000UL) /*!< EP9 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP8_Pos (16UL) /*!< EP8 (Bit 16) */ +#define USB_EP_TX_ERROR_EP8_Msk (0x30000UL) /*!< EP8 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP7_Pos (14UL) /*!< EP7 (Bit 14) */ +#define USB_EP_TX_ERROR_EP7_Msk (0xc000UL) /*!< EP7 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP6_Pos (12UL) /*!< EP6 (Bit 12) */ +#define USB_EP_TX_ERROR_EP6_Msk (0x3000UL) /*!< EP6 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP5_Pos (10UL) /*!< EP5 (Bit 10) */ +#define USB_EP_TX_ERROR_EP5_Msk (0xc00UL) /*!< EP5 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP4_Pos (8UL) /*!< EP4 (Bit 8) */ +#define USB_EP_TX_ERROR_EP4_Msk (0x300UL) /*!< EP4 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP3_Pos (6UL) /*!< EP3 (Bit 6) */ +#define USB_EP_TX_ERROR_EP3_Msk (0xc0UL) /*!< EP3 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP2_Pos (4UL) /*!< EP2 (Bit 4) */ +#define USB_EP_TX_ERROR_EP2_Msk (0x30UL) /*!< EP2 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP1_Pos (2UL) /*!< EP1 (Bit 2) */ +#define USB_EP_TX_ERROR_EP1_Msk (0xcUL) /*!< EP1 (Bitfield-Mask: 0x03) */ +#define USB_EP_TX_ERROR_EP0_Pos (0UL) /*!< EP0 (Bit 0) */ +#define USB_EP_TX_ERROR_EP0_Msk (0x3UL) /*!< EP0 (Bitfield-Mask: 0x03) */ +/* ====================================================== EP_RX_ERROR ====================================================== */ +#define USB_EP_RX_ERROR_EP15_SEQ_Pos (31UL) /*!< EP15_SEQ (Bit 31) */ +#define USB_EP_RX_ERROR_EP15_SEQ_Msk (0x80000000UL) /*!< EP15_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP15_TRANSACTION_Pos (30UL) /*!< EP15_TRANSACTION (Bit 30) */ +#define USB_EP_RX_ERROR_EP15_TRANSACTION_Msk (0x40000000UL) /*!< EP15_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP14_SEQ_Pos (29UL) /*!< EP14_SEQ (Bit 29) */ +#define USB_EP_RX_ERROR_EP14_SEQ_Msk (0x20000000UL) /*!< EP14_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP14_TRANSACTION_Pos (28UL) /*!< EP14_TRANSACTION (Bit 28) */ +#define USB_EP_RX_ERROR_EP14_TRANSACTION_Msk (0x10000000UL) /*!< EP14_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP13_SEQ_Pos (27UL) /*!< EP13_SEQ (Bit 27) */ +#define USB_EP_RX_ERROR_EP13_SEQ_Msk (0x8000000UL) /*!< EP13_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP13_TRANSACTION_Pos (26UL) /*!< EP13_TRANSACTION (Bit 26) */ +#define USB_EP_RX_ERROR_EP13_TRANSACTION_Msk (0x4000000UL) /*!< EP13_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP12_SEQ_Pos (25UL) /*!< EP12_SEQ (Bit 25) */ +#define USB_EP_RX_ERROR_EP12_SEQ_Msk (0x2000000UL) /*!< EP12_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP12_TRANSACTION_Pos (24UL) /*!< EP12_TRANSACTION (Bit 24) */ +#define USB_EP_RX_ERROR_EP12_TRANSACTION_Msk (0x1000000UL) /*!< EP12_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP11_SEQ_Pos (23UL) /*!< EP11_SEQ (Bit 23) */ +#define USB_EP_RX_ERROR_EP11_SEQ_Msk (0x800000UL) /*!< EP11_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP11_TRANSACTION_Pos (22UL) /*!< EP11_TRANSACTION (Bit 22) */ +#define USB_EP_RX_ERROR_EP11_TRANSACTION_Msk (0x400000UL) /*!< EP11_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP10_SEQ_Pos (21UL) /*!< EP10_SEQ (Bit 21) */ +#define USB_EP_RX_ERROR_EP10_SEQ_Msk (0x200000UL) /*!< EP10_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP10_TRANSACTION_Pos (20UL) /*!< EP10_TRANSACTION (Bit 20) */ +#define USB_EP_RX_ERROR_EP10_TRANSACTION_Msk (0x100000UL) /*!< EP10_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP9_SEQ_Pos (19UL) /*!< EP9_SEQ (Bit 19) */ +#define USB_EP_RX_ERROR_EP9_SEQ_Msk (0x80000UL) /*!< EP9_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP9_TRANSACTION_Pos (18UL) /*!< EP9_TRANSACTION (Bit 18) */ +#define USB_EP_RX_ERROR_EP9_TRANSACTION_Msk (0x40000UL) /*!< EP9_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP8_SEQ_Pos (17UL) /*!< EP8_SEQ (Bit 17) */ +#define USB_EP_RX_ERROR_EP8_SEQ_Msk (0x20000UL) /*!< EP8_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP8_TRANSACTION_Pos (16UL) /*!< EP8_TRANSACTION (Bit 16) */ +#define USB_EP_RX_ERROR_EP8_TRANSACTION_Msk (0x10000UL) /*!< EP8_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP7_SEQ_Pos (15UL) /*!< EP7_SEQ (Bit 15) */ +#define USB_EP_RX_ERROR_EP7_SEQ_Msk (0x8000UL) /*!< EP7_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP7_TRANSACTION_Pos (14UL) /*!< EP7_TRANSACTION (Bit 14) */ +#define USB_EP_RX_ERROR_EP7_TRANSACTION_Msk (0x4000UL) /*!< EP7_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP6_SEQ_Pos (13UL) /*!< EP6_SEQ (Bit 13) */ +#define USB_EP_RX_ERROR_EP6_SEQ_Msk (0x2000UL) /*!< EP6_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP6_TRANSACTION_Pos (12UL) /*!< EP6_TRANSACTION (Bit 12) */ +#define USB_EP_RX_ERROR_EP6_TRANSACTION_Msk (0x1000UL) /*!< EP6_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP5_SEQ_Pos (11UL) /*!< EP5_SEQ (Bit 11) */ +#define USB_EP_RX_ERROR_EP5_SEQ_Msk (0x800UL) /*!< EP5_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP5_TRANSACTION_Pos (10UL) /*!< EP5_TRANSACTION (Bit 10) */ +#define USB_EP_RX_ERROR_EP5_TRANSACTION_Msk (0x400UL) /*!< EP5_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP4_SEQ_Pos (9UL) /*!< EP4_SEQ (Bit 9) */ +#define USB_EP_RX_ERROR_EP4_SEQ_Msk (0x200UL) /*!< EP4_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP4_TRANSACTION_Pos (8UL) /*!< EP4_TRANSACTION (Bit 8) */ +#define USB_EP_RX_ERROR_EP4_TRANSACTION_Msk (0x100UL) /*!< EP4_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP3_SEQ_Pos (7UL) /*!< EP3_SEQ (Bit 7) */ +#define USB_EP_RX_ERROR_EP3_SEQ_Msk (0x80UL) /*!< EP3_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP3_TRANSACTION_Pos (6UL) /*!< EP3_TRANSACTION (Bit 6) */ +#define USB_EP_RX_ERROR_EP3_TRANSACTION_Msk (0x40UL) /*!< EP3_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP2_SEQ_Pos (5UL) /*!< EP2_SEQ (Bit 5) */ +#define USB_EP_RX_ERROR_EP2_SEQ_Msk (0x20UL) /*!< EP2_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP2_TRANSACTION_Pos (4UL) /*!< EP2_TRANSACTION (Bit 4) */ +#define USB_EP_RX_ERROR_EP2_TRANSACTION_Msk (0x10UL) /*!< EP2_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP1_SEQ_Pos (3UL) /*!< EP1_SEQ (Bit 3) */ +#define USB_EP_RX_ERROR_EP1_SEQ_Msk (0x8UL) /*!< EP1_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP1_TRANSACTION_Pos (2UL) /*!< EP1_TRANSACTION (Bit 2) */ +#define USB_EP_RX_ERROR_EP1_TRANSACTION_Msk (0x4UL) /*!< EP1_TRANSACTION (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP0_SEQ_Pos (1UL) /*!< EP0_SEQ (Bit 1) */ +#define USB_EP_RX_ERROR_EP0_SEQ_Msk (0x2UL) /*!< EP0_SEQ (Bitfield-Mask: 0x01) */ +#define USB_EP_RX_ERROR_EP0_TRANSACTION_Pos (0UL) /*!< EP0_TRANSACTION (Bit 0) */ +#define USB_EP_RX_ERROR_EP0_TRANSACTION_Msk (0x1UL) /*!< EP0_TRANSACTION (Bitfield-Mask: 0x01) */ +/* ==================================================== DEV_SM_WATCHDOG ==================================================== */ +#define USB_DEV_SM_WATCHDOG_FIRED_Pos (20UL) /*!< FIRED (Bit 20) */ +#define USB_DEV_SM_WATCHDOG_FIRED_Msk (0x100000UL) /*!< FIRED (Bitfield-Mask: 0x01) */ +#define USB_DEV_SM_WATCHDOG_RESET_Pos (19UL) /*!< RESET (Bit 19) */ +#define USB_DEV_SM_WATCHDOG_RESET_Msk (0x80000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DEV_SM_WATCHDOG_ENABLE_Pos (18UL) /*!< ENABLE (Bit 18) */ +#define USB_DEV_SM_WATCHDOG_ENABLE_Msk (0x40000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DEV_SM_WATCHDOG_LIMIT_Pos (0UL) /*!< LIMIT (Bit 0) */ +#define USB_DEV_SM_WATCHDOG_LIMIT_Msk (0x3ffffUL) /*!< LIMIT (Bitfield-Mask: 0x3ffff) */ + + +/* =========================================================================================================================== */ +/* ================ TRNG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== RNG_IMR ======================================================== */ +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_Pos (3UL) /*!< VN_ERR_INT_MASK (Bit 3) */ +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_Msk (0x8UL) /*!< VN_ERR_INT_MASK (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_Pos (2UL) /*!< CRNGT_ERR_INT_MASK (Bit 2) */ +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_Msk (0x4UL) /*!< CRNGT_ERR_INT_MASK (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_Pos (1UL) /*!< AUTOCORR_ERR_INT_MASK (Bit 1) */ +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_Msk (0x2UL) /*!< AUTOCORR_ERR_INT_MASK (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_Pos (0UL) /*!< EHR_VALID_INT_MASK (Bit 0) */ +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_Msk (0x1UL) /*!< EHR_VALID_INT_MASK (Bitfield-Mask: 0x01) */ +/* ======================================================== RNG_ISR ======================================================== */ +#define TRNG_RNG_ISR_VN_ERR_Pos (3UL) /*!< VN_ERR (Bit 3) */ +#define TRNG_RNG_ISR_VN_ERR_Msk (0x8UL) /*!< VN_ERR (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_ISR_CRNGT_ERR_Pos (2UL) /*!< CRNGT_ERR (Bit 2) */ +#define TRNG_RNG_ISR_CRNGT_ERR_Msk (0x4UL) /*!< CRNGT_ERR (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_ISR_AUTOCORR_ERR_Pos (1UL) /*!< AUTOCORR_ERR (Bit 1) */ +#define TRNG_RNG_ISR_AUTOCORR_ERR_Msk (0x2UL) /*!< AUTOCORR_ERR (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_ISR_EHR_VALID_Pos (0UL) /*!< EHR_VALID (Bit 0) */ +#define TRNG_RNG_ISR_EHR_VALID_Msk (0x1UL) /*!< EHR_VALID (Bitfield-Mask: 0x01) */ +/* ======================================================== RNG_ICR ======================================================== */ +#define TRNG_RNG_ICR_VN_ERR_Pos (3UL) /*!< VN_ERR (Bit 3) */ +#define TRNG_RNG_ICR_VN_ERR_Msk (0x8UL) /*!< VN_ERR (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_ICR_CRNGT_ERR_Pos (2UL) /*!< CRNGT_ERR (Bit 2) */ +#define TRNG_RNG_ICR_CRNGT_ERR_Msk (0x4UL) /*!< CRNGT_ERR (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_ICR_AUTOCORR_ERR_Pos (1UL) /*!< AUTOCORR_ERR (Bit 1) */ +#define TRNG_RNG_ICR_AUTOCORR_ERR_Msk (0x2UL) /*!< AUTOCORR_ERR (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_ICR_EHR_VALID_Pos (0UL) /*!< EHR_VALID (Bit 0) */ +#define TRNG_RNG_ICR_EHR_VALID_Msk (0x1UL) /*!< EHR_VALID (Bitfield-Mask: 0x01) */ +/* ====================================================== TRNG_CONFIG ====================================================== */ +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_Pos (0UL) /*!< RND_SRC_SEL (Bit 0) */ +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_Msk (0x3UL) /*!< RND_SRC_SEL (Bitfield-Mask: 0x03) */ +/* ====================================================== TRNG_VALID ======================================================= */ +#define TRNG_TRNG_VALID_EHR_VALID_Pos (0UL) /*!< EHR_VALID (Bit 0) */ +#define TRNG_TRNG_VALID_EHR_VALID_Msk (0x1UL) /*!< EHR_VALID (Bitfield-Mask: 0x01) */ +/* ======================================================= EHR_DATA0 ======================================================= */ +#define TRNG_EHR_DATA0_EHR_DATA0_Pos (0UL) /*!< EHR_DATA0 (Bit 0) */ +#define TRNG_EHR_DATA0_EHR_DATA0_Msk (0xffffffffUL) /*!< EHR_DATA0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EHR_DATA1 ======================================================= */ +#define TRNG_EHR_DATA1_EHR_DATA1_Pos (0UL) /*!< EHR_DATA1 (Bit 0) */ +#define TRNG_EHR_DATA1_EHR_DATA1_Msk (0xffffffffUL) /*!< EHR_DATA1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EHR_DATA2 ======================================================= */ +#define TRNG_EHR_DATA2_EHR_DATA2_Pos (0UL) /*!< EHR_DATA2 (Bit 0) */ +#define TRNG_EHR_DATA2_EHR_DATA2_Msk (0xffffffffUL) /*!< EHR_DATA2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EHR_DATA3 ======================================================= */ +#define TRNG_EHR_DATA3_EHR_DATA3_Pos (0UL) /*!< EHR_DATA3 (Bit 0) */ +#define TRNG_EHR_DATA3_EHR_DATA3_Msk (0xffffffffUL) /*!< EHR_DATA3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EHR_DATA4 ======================================================= */ +#define TRNG_EHR_DATA4_EHR_DATA4_Pos (0UL) /*!< EHR_DATA4 (Bit 0) */ +#define TRNG_EHR_DATA4_EHR_DATA4_Msk (0xffffffffUL) /*!< EHR_DATA4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EHR_DATA5 ======================================================= */ +#define TRNG_EHR_DATA5_EHR_DATA5_Pos (0UL) /*!< EHR_DATA5 (Bit 0) */ +#define TRNG_EHR_DATA5_EHR_DATA5_Msk (0xffffffffUL) /*!< EHR_DATA5 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== RND_SOURCE_ENABLE =================================================== */ +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_Pos (0UL) /*!< RND_SRC_EN (Bit 0) */ +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_Msk (0x1UL) /*!< RND_SRC_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== SAMPLE_CNT1 ====================================================== */ +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_Pos (0UL) /*!< SAMPLE_CNTR1 (Bit 0) */ +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_Msk (0xffffffffUL) /*!< SAMPLE_CNTR1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== AUTOCORR_STATISTIC =================================================== */ +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Pos (14UL) /*!< AUTOCORR_FAILS (Bit 14) */ +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Msk (0x3fc000UL) /*!< AUTOCORR_FAILS (Bitfield-Mask: 0xff) */ +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Pos (0UL) /*!< AUTOCORR_TRYS (Bit 0) */ +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Msk (0x3fffUL) /*!< AUTOCORR_TRYS (Bitfield-Mask: 0x3fff) */ +/* ================================================== TRNG_DEBUG_CONTROL =================================================== */ +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_Pos (3UL) /*!< AUTO_CORRELATE_BYPASS (Bit 3) */ +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_Msk (0x8UL) /*!< AUTO_CORRELATE_BYPASS (Bitfield-Mask: 0x01) */ +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_Pos (2UL) /*!< TRNG_CRNGT_BYPASS (Bit 2) */ +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_Msk (0x4UL) /*!< TRNG_CRNGT_BYPASS (Bitfield-Mask: 0x01) */ +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_Pos (1UL) /*!< VNC_BYPASS (Bit 1) */ +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_Msk (0x2UL) /*!< VNC_BYPASS (Bitfield-Mask: 0x01) */ +/* ===================================================== TRNG_SW_RESET ===================================================== */ +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_Pos (0UL) /*!< TRNG_SW_RESET (Bit 0) */ +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_Msk (0x1UL) /*!< TRNG_SW_RESET (Bitfield-Mask: 0x01) */ +/* ================================================== RNG_DEBUG_EN_INPUT =================================================== */ +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_Pos (0UL) /*!< RNG_DEBUG_EN (Bit 0) */ +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_Msk (0x1UL) /*!< RNG_DEBUG_EN (Bitfield-Mask: 0x01) */ +/* ======================================================= TRNG_BUSY ======================================================= */ +#define TRNG_TRNG_BUSY_TRNG_BUSY_Pos (0UL) /*!< TRNG_BUSY (Bit 0) */ +#define TRNG_TRNG_BUSY_TRNG_BUSY_Msk (0x1UL) /*!< TRNG_BUSY (Bitfield-Mask: 0x01) */ +/* =================================================== RST_BITS_COUNTER ==================================================== */ +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_Pos (0UL) /*!< RST_BITS_COUNTER (Bit 0) */ +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_Msk (0x1UL) /*!< RST_BITS_COUNTER (Bitfield-Mask: 0x01) */ +/* ====================================================== RNG_VERSION ====================================================== */ +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_Pos (7UL) /*!< RNG_USE_5_SBOXES (Bit 7) */ +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_Msk (0x80UL) /*!< RNG_USE_5_SBOXES (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_Pos (6UL) /*!< RESEEDING_EXISTS (Bit 6) */ +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_Msk (0x40UL) /*!< RESEEDING_EXISTS (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_VERSION_KAT_EXISTS_Pos (5UL) /*!< KAT_EXISTS (Bit 5) */ +#define TRNG_RNG_VERSION_KAT_EXISTS_Msk (0x20UL) /*!< KAT_EXISTS (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_VERSION_PRNG_EXISTS_Pos (4UL) /*!< PRNG_EXISTS (Bit 4) */ +#define TRNG_RNG_VERSION_PRNG_EXISTS_Msk (0x10UL) /*!< PRNG_EXISTS (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_Pos (3UL) /*!< TRNG_TESTS_BYPASS_EN (Bit 3) */ +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_Msk (0x8UL) /*!< TRNG_TESTS_BYPASS_EN (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_Pos (2UL) /*!< AUTOCORR_EXISTS (Bit 2) */ +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_Msk (0x4UL) /*!< AUTOCORR_EXISTS (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_VERSION_CRNGT_EXISTS_Pos (1UL) /*!< CRNGT_EXISTS (Bit 1) */ +#define TRNG_RNG_VERSION_CRNGT_EXISTS_Msk (0x2UL) /*!< CRNGT_EXISTS (Bitfield-Mask: 0x01) */ +#define TRNG_RNG_VERSION_EHR_WIDTH_192_Pos (0UL) /*!< EHR_WIDTH_192 (Bit 0) */ +#define TRNG_RNG_VERSION_EHR_WIDTH_192_Msk (0x1UL) /*!< EHR_WIDTH_192 (Bitfield-Mask: 0x01) */ +/* ==================================================== RNG_BIST_CNTR_0 ==================================================== */ +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_Pos (0UL) /*!< ROSC_CNTR_VAL (Bit 0) */ +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_Msk (0x3fffffUL) /*!< ROSC_CNTR_VAL (Bitfield-Mask: 0x3fffff) */ +/* ==================================================== RNG_BIST_CNTR_1 ==================================================== */ +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_Pos (0UL) /*!< ROSC_CNTR_VAL (Bit 0) */ +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_Msk (0x3fffffUL) /*!< ROSC_CNTR_VAL (Bitfield-Mask: 0x3fffff) */ +/* ==================================================== RNG_BIST_CNTR_2 ==================================================== */ +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_Pos (0UL) /*!< ROSC_CNTR_VAL (Bit 0) */ +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_Msk (0x3fffffUL) /*!< ROSC_CNTR_VAL (Bitfield-Mask: 0x3fffff) */ + + +/* =========================================================================================================================== */ +/* ================ GLITCH_DETECTOR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ARM ========================================================== */ +#define GLITCH_DETECTOR_ARM_ARM_Pos (0UL) /*!< ARM (Bit 0) */ +#define GLITCH_DETECTOR_ARM_ARM_Msk (0xffffUL) /*!< ARM (Bitfield-Mask: 0xffff) */ +/* ======================================================== DISARM ========================================================= */ +#define GLITCH_DETECTOR_DISARM_DISARM_Pos (0UL) /*!< DISARM (Bit 0) */ +#define GLITCH_DETECTOR_DISARM_DISARM_Msk (0xffffUL) /*!< DISARM (Bitfield-Mask: 0xffff) */ +/* ====================================================== SENSITIVITY ====================================================== */ +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_Pos (24UL) /*!< DEFAULT (Bit 24) */ +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_Msk (0xff000000UL) /*!< DEFAULT (Bitfield-Mask: 0xff) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_Pos (14UL) /*!< DET3_INV (Bit 14) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_Msk (0xc000UL) /*!< DET3_INV (Bitfield-Mask: 0x03) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_Pos (12UL) /*!< DET2_INV (Bit 12) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_Msk (0x3000UL) /*!< DET2_INV (Bitfield-Mask: 0x03) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_Pos (10UL) /*!< DET1_INV (Bit 10) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_Msk (0xc00UL) /*!< DET1_INV (Bitfield-Mask: 0x03) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_Pos (8UL) /*!< DET0_INV (Bit 8) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_Msk (0x300UL) /*!< DET0_INV (Bitfield-Mask: 0x03) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET3_Pos (6UL) /*!< DET3 (Bit 6) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET3_Msk (0xc0UL) /*!< DET3 (Bitfield-Mask: 0x03) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET2_Pos (4UL) /*!< DET2 (Bit 4) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET2_Msk (0x30UL) /*!< DET2 (Bitfield-Mask: 0x03) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET1_Pos (2UL) /*!< DET1 (Bit 2) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET1_Msk (0xcUL) /*!< DET1 (Bitfield-Mask: 0x03) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET0_Pos (0UL) /*!< DET0 (Bit 0) */ +#define GLITCH_DETECTOR_SENSITIVITY_DET0_Msk (0x3UL) /*!< DET0 (Bitfield-Mask: 0x03) */ +/* ========================================================= LOCK ========================================================== */ +#define GLITCH_DETECTOR_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ +#define GLITCH_DETECTOR_LOCK_LOCK_Msk (0xffUL) /*!< LOCK (Bitfield-Mask: 0xff) */ +/* ====================================================== TRIG_STATUS ====================================================== */ +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_Pos (3UL) /*!< DET3 (Bit 3) */ +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_Msk (0x8UL) /*!< DET3 (Bitfield-Mask: 0x01) */ +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_Pos (2UL) /*!< DET2 (Bit 2) */ +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_Msk (0x4UL) /*!< DET2 (Bitfield-Mask: 0x01) */ +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_Pos (1UL) /*!< DET1 (Bit 1) */ +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_Msk (0x2UL) /*!< DET1 (Bitfield-Mask: 0x01) */ +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_Pos (0UL) /*!< DET0 (Bit 0) */ +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_Msk (0x1UL) /*!< DET0 (Bitfield-Mask: 0x01) */ +/* ====================================================== TRIG_FORCE ======================================================= */ +#define GLITCH_DETECTOR_TRIG_FORCE_TRIG_FORCE_Pos (0UL) /*!< TRIG_FORCE (Bit 0) */ +#define GLITCH_DETECTOR_TRIG_FORCE_TRIG_FORCE_Msk (0xfUL) /*!< TRIG_FORCE (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ OTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SW_LOCK0 ======================================================== */ +#define OTP_SW_LOCK0_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK0_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK0_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK0_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK1 ======================================================== */ +#define OTP_SW_LOCK1_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK1_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK1_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK1_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK2 ======================================================== */ +#define OTP_SW_LOCK2_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK2_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK2_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK2_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK3 ======================================================== */ +#define OTP_SW_LOCK3_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK3_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK3_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK3_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK4 ======================================================== */ +#define OTP_SW_LOCK4_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK4_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK4_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK4_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK5 ======================================================== */ +#define OTP_SW_LOCK5_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK5_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK5_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK5_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK6 ======================================================== */ +#define OTP_SW_LOCK6_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK6_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK6_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK6_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK7 ======================================================== */ +#define OTP_SW_LOCK7_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK7_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK7_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK7_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK8 ======================================================== */ +#define OTP_SW_LOCK8_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK8_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK8_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK8_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK9 ======================================================== */ +#define OTP_SW_LOCK9_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK9_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK9_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK9_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK10 ======================================================= */ +#define OTP_SW_LOCK10_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK10_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK10_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK10_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK11 ======================================================= */ +#define OTP_SW_LOCK11_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK11_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK11_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK11_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK12 ======================================================= */ +#define OTP_SW_LOCK12_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK12_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK12_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK12_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK13 ======================================================= */ +#define OTP_SW_LOCK13_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK13_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK13_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK13_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK14 ======================================================= */ +#define OTP_SW_LOCK14_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK14_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK14_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK14_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK15 ======================================================= */ +#define OTP_SW_LOCK15_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK15_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK15_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK15_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK16 ======================================================= */ +#define OTP_SW_LOCK16_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK16_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK16_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK16_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK17 ======================================================= */ +#define OTP_SW_LOCK17_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK17_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK17_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK17_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK18 ======================================================= */ +#define OTP_SW_LOCK18_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK18_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK18_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK18_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK19 ======================================================= */ +#define OTP_SW_LOCK19_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK19_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK19_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK19_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK20 ======================================================= */ +#define OTP_SW_LOCK20_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK20_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK20_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK20_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK21 ======================================================= */ +#define OTP_SW_LOCK21_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK21_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK21_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK21_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK22 ======================================================= */ +#define OTP_SW_LOCK22_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK22_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK22_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK22_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK23 ======================================================= */ +#define OTP_SW_LOCK23_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK23_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK23_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK23_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK24 ======================================================= */ +#define OTP_SW_LOCK24_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK24_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK24_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK24_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK25 ======================================================= */ +#define OTP_SW_LOCK25_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK25_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK25_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK25_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK26 ======================================================= */ +#define OTP_SW_LOCK26_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK26_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK26_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK26_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK27 ======================================================= */ +#define OTP_SW_LOCK27_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK27_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK27_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK27_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK28 ======================================================= */ +#define OTP_SW_LOCK28_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK28_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK28_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK28_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK29 ======================================================= */ +#define OTP_SW_LOCK29_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK29_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK29_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK29_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK30 ======================================================= */ +#define OTP_SW_LOCK30_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK30_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK30_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK30_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK31 ======================================================= */ +#define OTP_SW_LOCK31_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK31_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK31_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK31_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK32 ======================================================= */ +#define OTP_SW_LOCK32_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK32_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK32_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK32_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK33 ======================================================= */ +#define OTP_SW_LOCK33_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK33_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK33_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK33_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK34 ======================================================= */ +#define OTP_SW_LOCK34_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK34_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK34_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK34_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK35 ======================================================= */ +#define OTP_SW_LOCK35_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK35_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK35_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK35_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK36 ======================================================= */ +#define OTP_SW_LOCK36_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK36_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK36_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK36_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK37 ======================================================= */ +#define OTP_SW_LOCK37_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK37_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK37_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK37_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK38 ======================================================= */ +#define OTP_SW_LOCK38_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK38_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK38_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK38_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK39 ======================================================= */ +#define OTP_SW_LOCK39_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK39_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK39_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK39_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK40 ======================================================= */ +#define OTP_SW_LOCK40_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK40_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK40_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK40_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK41 ======================================================= */ +#define OTP_SW_LOCK41_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK41_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK41_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK41_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK42 ======================================================= */ +#define OTP_SW_LOCK42_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK42_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK42_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK42_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK43 ======================================================= */ +#define OTP_SW_LOCK43_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK43_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK43_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK43_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK44 ======================================================= */ +#define OTP_SW_LOCK44_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK44_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK44_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK44_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK45 ======================================================= */ +#define OTP_SW_LOCK45_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK45_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK45_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK45_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK46 ======================================================= */ +#define OTP_SW_LOCK46_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK46_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK46_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK46_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK47 ======================================================= */ +#define OTP_SW_LOCK47_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK47_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK47_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK47_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK48 ======================================================= */ +#define OTP_SW_LOCK48_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK48_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK48_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK48_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK49 ======================================================= */ +#define OTP_SW_LOCK49_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK49_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK49_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK49_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK50 ======================================================= */ +#define OTP_SW_LOCK50_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK50_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK50_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK50_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK51 ======================================================= */ +#define OTP_SW_LOCK51_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK51_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK51_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK51_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK52 ======================================================= */ +#define OTP_SW_LOCK52_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK52_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK52_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK52_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK53 ======================================================= */ +#define OTP_SW_LOCK53_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK53_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK53_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK53_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK54 ======================================================= */ +#define OTP_SW_LOCK54_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK54_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK54_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK54_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK55 ======================================================= */ +#define OTP_SW_LOCK55_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK55_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK55_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK55_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK56 ======================================================= */ +#define OTP_SW_LOCK56_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK56_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK56_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK56_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK57 ======================================================= */ +#define OTP_SW_LOCK57_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK57_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK57_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK57_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK58 ======================================================= */ +#define OTP_SW_LOCK58_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK58_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK58_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK58_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK59 ======================================================= */ +#define OTP_SW_LOCK59_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK59_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK59_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK59_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK60 ======================================================= */ +#define OTP_SW_LOCK60_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK60_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK60_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK60_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK61 ======================================================= */ +#define OTP_SW_LOCK61_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK61_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK61_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK61_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK62 ======================================================= */ +#define OTP_SW_LOCK62_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK62_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK62_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK62_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ======================================================= SW_LOCK63 ======================================================= */ +#define OTP_SW_LOCK63_NSEC_Pos (2UL) /*!< NSEC (Bit 2) */ +#define OTP_SW_LOCK63_NSEC_Msk (0xcUL) /*!< NSEC (Bitfield-Mask: 0x03) */ +#define OTP_SW_LOCK63_SEC_Pos (0UL) /*!< SEC (Bit 0) */ +#define OTP_SW_LOCK63_SEC_Msk (0x3UL) /*!< SEC (Bitfield-Mask: 0x03) */ +/* ====================================================== SBPI_INSTR ======================================================= */ +#define OTP_SBPI_INSTR_EXEC_Pos (30UL) /*!< EXEC (Bit 30) */ +#define OTP_SBPI_INSTR_EXEC_Msk (0x40000000UL) /*!< EXEC (Bitfield-Mask: 0x01) */ +#define OTP_SBPI_INSTR_IS_WR_Pos (29UL) /*!< IS_WR (Bit 29) */ +#define OTP_SBPI_INSTR_IS_WR_Msk (0x20000000UL) /*!< IS_WR (Bitfield-Mask: 0x01) */ +#define OTP_SBPI_INSTR_HAS_PAYLOAD_Pos (28UL) /*!< HAS_PAYLOAD (Bit 28) */ +#define OTP_SBPI_INSTR_HAS_PAYLOAD_Msk (0x10000000UL) /*!< HAS_PAYLOAD (Bitfield-Mask: 0x01) */ +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_Pos (24UL) /*!< PAYLOAD_SIZE_M1 (Bit 24) */ +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_Msk (0xf000000UL) /*!< PAYLOAD_SIZE_M1 (Bitfield-Mask: 0x0f) */ +#define OTP_SBPI_INSTR_TARGET_Pos (16UL) /*!< TARGET (Bit 16) */ +#define OTP_SBPI_INSTR_TARGET_Msk (0xff0000UL) /*!< TARGET (Bitfield-Mask: 0xff) */ +#define OTP_SBPI_INSTR_CMD_Pos (8UL) /*!< CMD (Bit 8) */ +#define OTP_SBPI_INSTR_CMD_Msk (0xff00UL) /*!< CMD (Bitfield-Mask: 0xff) */ +#define OTP_SBPI_INSTR_SHORT_WDATA_Pos (0UL) /*!< SHORT_WDATA (Bit 0) */ +#define OTP_SBPI_INSTR_SHORT_WDATA_Msk (0xffUL) /*!< SHORT_WDATA (Bitfield-Mask: 0xff) */ +/* ===================================================== SBPI_WDATA_0 ====================================================== */ +#define OTP_SBPI_WDATA_0_SBPI_WDATA_0_Pos (0UL) /*!< SBPI_WDATA_0 (Bit 0) */ +#define OTP_SBPI_WDATA_0_SBPI_WDATA_0_Msk (0xffffffffUL) /*!< SBPI_WDATA_0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SBPI_WDATA_1 ====================================================== */ +#define OTP_SBPI_WDATA_1_SBPI_WDATA_1_Pos (0UL) /*!< SBPI_WDATA_1 (Bit 0) */ +#define OTP_SBPI_WDATA_1_SBPI_WDATA_1_Msk (0xffffffffUL) /*!< SBPI_WDATA_1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SBPI_WDATA_2 ====================================================== */ +#define OTP_SBPI_WDATA_2_SBPI_WDATA_2_Pos (0UL) /*!< SBPI_WDATA_2 (Bit 0) */ +#define OTP_SBPI_WDATA_2_SBPI_WDATA_2_Msk (0xffffffffUL) /*!< SBPI_WDATA_2 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SBPI_WDATA_3 ====================================================== */ +#define OTP_SBPI_WDATA_3_SBPI_WDATA_3_Pos (0UL) /*!< SBPI_WDATA_3 (Bit 0) */ +#define OTP_SBPI_WDATA_3_SBPI_WDATA_3_Msk (0xffffffffUL) /*!< SBPI_WDATA_3 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SBPI_RDATA_0 ====================================================== */ +#define OTP_SBPI_RDATA_0_SBPI_RDATA_0_Pos (0UL) /*!< SBPI_RDATA_0 (Bit 0) */ +#define OTP_SBPI_RDATA_0_SBPI_RDATA_0_Msk (0xffffffffUL) /*!< SBPI_RDATA_0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SBPI_RDATA_1 ====================================================== */ +#define OTP_SBPI_RDATA_1_SBPI_RDATA_1_Pos (0UL) /*!< SBPI_RDATA_1 (Bit 0) */ +#define OTP_SBPI_RDATA_1_SBPI_RDATA_1_Msk (0xffffffffUL) /*!< SBPI_RDATA_1 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SBPI_RDATA_2 ====================================================== */ +#define OTP_SBPI_RDATA_2_SBPI_RDATA_2_Pos (0UL) /*!< SBPI_RDATA_2 (Bit 0) */ +#define OTP_SBPI_RDATA_2_SBPI_RDATA_2_Msk (0xffffffffUL) /*!< SBPI_RDATA_2 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SBPI_RDATA_3 ====================================================== */ +#define OTP_SBPI_RDATA_3_SBPI_RDATA_3_Pos (0UL) /*!< SBPI_RDATA_3 (Bit 0) */ +#define OTP_SBPI_RDATA_3_SBPI_RDATA_3_Msk (0xffffffffUL) /*!< SBPI_RDATA_3 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SBPI_STATUS ====================================================== */ +#define OTP_SBPI_STATUS_MISO_Pos (16UL) /*!< MISO (Bit 16) */ +#define OTP_SBPI_STATUS_MISO_Msk (0xff0000UL) /*!< MISO (Bitfield-Mask: 0xff) */ +#define OTP_SBPI_STATUS_FLAG_Pos (12UL) /*!< FLAG (Bit 12) */ +#define OTP_SBPI_STATUS_FLAG_Msk (0x1000UL) /*!< FLAG (Bitfield-Mask: 0x01) */ +#define OTP_SBPI_STATUS_INSTR_MISS_Pos (8UL) /*!< INSTR_MISS (Bit 8) */ +#define OTP_SBPI_STATUS_INSTR_MISS_Msk (0x100UL) /*!< INSTR_MISS (Bitfield-Mask: 0x01) */ +#define OTP_SBPI_STATUS_INSTR_DONE_Pos (4UL) /*!< INSTR_DONE (Bit 4) */ +#define OTP_SBPI_STATUS_INSTR_DONE_Msk (0x10UL) /*!< INSTR_DONE (Bitfield-Mask: 0x01) */ +#define OTP_SBPI_STATUS_RDATA_VLD_Pos (0UL) /*!< RDATA_VLD (Bit 0) */ +#define OTP_SBPI_STATUS_RDATA_VLD_Msk (0x1UL) /*!< RDATA_VLD (Bitfield-Mask: 0x01) */ +/* ========================================================== USR ========================================================== */ +#define OTP_USR_PD_Pos (4UL) /*!< PD (Bit 4) */ +#define OTP_USR_PD_Msk (0x10UL) /*!< PD (Bitfield-Mask: 0x01) */ +#define OTP_USR_DCTRL_Pos (0UL) /*!< DCTRL (Bit 0) */ +#define OTP_USR_DCTRL_Msk (0x1UL) /*!< DCTRL (Bitfield-Mask: 0x01) */ +/* ========================================================== DBG ========================================================== */ +#define OTP_DBG_CUSTOMER_RMA_FLAG_Pos (12UL) /*!< CUSTOMER_RMA_FLAG (Bit 12) */ +#define OTP_DBG_CUSTOMER_RMA_FLAG_Msk (0x1000UL) /*!< CUSTOMER_RMA_FLAG (Bitfield-Mask: 0x01) */ +#define OTP_DBG_PSM_STATE_Pos (4UL) /*!< PSM_STATE (Bit 4) */ +#define OTP_DBG_PSM_STATE_Msk (0xf0UL) /*!< PSM_STATE (Bitfield-Mask: 0x0f) */ +#define OTP_DBG_ROSC_UP_Pos (3UL) /*!< ROSC_UP (Bit 3) */ +#define OTP_DBG_ROSC_UP_Msk (0x8UL) /*!< ROSC_UP (Bitfield-Mask: 0x01) */ +#define OTP_DBG_ROSC_UP_SEEN_Pos (2UL) /*!< ROSC_UP_SEEN (Bit 2) */ +#define OTP_DBG_ROSC_UP_SEEN_Msk (0x4UL) /*!< ROSC_UP_SEEN (Bitfield-Mask: 0x01) */ +#define OTP_DBG_BOOT_DONE_Pos (1UL) /*!< BOOT_DONE (Bit 1) */ +#define OTP_DBG_BOOT_DONE_Msk (0x2UL) /*!< BOOT_DONE (Bitfield-Mask: 0x01) */ +#define OTP_DBG_PSM_DONE_Pos (0UL) /*!< PSM_DONE (Bit 0) */ +#define OTP_DBG_PSM_DONE_Msk (0x1UL) /*!< PSM_DONE (Bitfield-Mask: 0x01) */ +/* ========================================================= BIST ========================================================== */ +#define OTP_BIST_CNT_FAIL_Pos (30UL) /*!< CNT_FAIL (Bit 30) */ +#define OTP_BIST_CNT_FAIL_Msk (0x40000000UL) /*!< CNT_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_BIST_CNT_CLR_Pos (29UL) /*!< CNT_CLR (Bit 29) */ +#define OTP_BIST_CNT_CLR_Msk (0x20000000UL) /*!< CNT_CLR (Bitfield-Mask: 0x01) */ +#define OTP_BIST_CNT_ENA_Pos (28UL) /*!< CNT_ENA (Bit 28) */ +#define OTP_BIST_CNT_ENA_Msk (0x10000000UL) /*!< CNT_ENA (Bitfield-Mask: 0x01) */ +#define OTP_BIST_CNT_MAX_Pos (16UL) /*!< CNT_MAX (Bit 16) */ +#define OTP_BIST_CNT_MAX_Msk (0xfff0000UL) /*!< CNT_MAX (Bitfield-Mask: 0xfff) */ +#define OTP_BIST_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define OTP_BIST_CNT_Msk (0x1fffUL) /*!< CNT (Bitfield-Mask: 0x1fff) */ +/* ====================================================== CRT_KEY_W0 ======================================================= */ +#define OTP_CRT_KEY_W0_CRT_KEY_W0_Pos (0UL) /*!< CRT_KEY_W0 (Bit 0) */ +#define OTP_CRT_KEY_W0_CRT_KEY_W0_Msk (0xffffffffUL) /*!< CRT_KEY_W0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CRT_KEY_W1 ======================================================= */ +#define OTP_CRT_KEY_W1_CRT_KEY_W1_Pos (0UL) /*!< CRT_KEY_W1 (Bit 0) */ +#define OTP_CRT_KEY_W1_CRT_KEY_W1_Msk (0xffffffffUL) /*!< CRT_KEY_W1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CRT_KEY_W2 ======================================================= */ +#define OTP_CRT_KEY_W2_CRT_KEY_W2_Pos (0UL) /*!< CRT_KEY_W2 (Bit 0) */ +#define OTP_CRT_KEY_W2_CRT_KEY_W2_Msk (0xffffffffUL) /*!< CRT_KEY_W2 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CRT_KEY_W3 ======================================================= */ +#define OTP_CRT_KEY_W3_CRT_KEY_W3_Pos (0UL) /*!< CRT_KEY_W3 (Bit 0) */ +#define OTP_CRT_KEY_W3_CRT_KEY_W3_Msk (0xffffffffUL) /*!< CRT_KEY_W3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRITICAL ======================================================== */ +#define OTP_CRITICAL_RISCV_DISABLE_Pos (17UL) /*!< RISCV_DISABLE (Bit 17) */ +#define OTP_CRITICAL_RISCV_DISABLE_Msk (0x20000UL) /*!< RISCV_DISABLE (Bitfield-Mask: 0x01) */ +#define OTP_CRITICAL_ARM_DISABLE_Pos (16UL) /*!< ARM_DISABLE (Bit 16) */ +#define OTP_CRITICAL_ARM_DISABLE_Msk (0x10000UL) /*!< ARM_DISABLE (Bitfield-Mask: 0x01) */ +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_Pos (5UL) /*!< GLITCH_DETECTOR_SENS (Bit 5) */ +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_Msk (0x60UL) /*!< GLITCH_DETECTOR_SENS (Bitfield-Mask: 0x03) */ +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_Pos (4UL) /*!< GLITCH_DETECTOR_ENABLE (Bit 4) */ +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_Msk (0x10UL) /*!< GLITCH_DETECTOR_ENABLE (Bitfield-Mask: 0x01) */ +#define OTP_CRITICAL_DEFAULT_ARCHSEL_Pos (3UL) /*!< DEFAULT_ARCHSEL (Bit 3) */ +#define OTP_CRITICAL_DEFAULT_ARCHSEL_Msk (0x8UL) /*!< DEFAULT_ARCHSEL (Bitfield-Mask: 0x01) */ +#define OTP_CRITICAL_DEBUG_DISABLE_Pos (2UL) /*!< DEBUG_DISABLE (Bit 2) */ +#define OTP_CRITICAL_DEBUG_DISABLE_Msk (0x4UL) /*!< DEBUG_DISABLE (Bitfield-Mask: 0x01) */ +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_Pos (1UL) /*!< SECURE_DEBUG_DISABLE (Bit 1) */ +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_Msk (0x2UL) /*!< SECURE_DEBUG_DISABLE (Bitfield-Mask: 0x01) */ +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_Pos (0UL) /*!< SECURE_BOOT_ENABLE (Bit 0) */ +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_Msk (0x1UL) /*!< SECURE_BOOT_ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= KEY_VALID ======================================================= */ +#define OTP_KEY_VALID_KEY_VALID_Pos (0UL) /*!< KEY_VALID (Bit 0) */ +#define OTP_KEY_VALID_KEY_VALID_Msk (0xffUL) /*!< KEY_VALID (Bitfield-Mask: 0xff) */ +/* ======================================================== DEBUGEN ======================================================== */ +#define OTP_DEBUGEN_MISC_Pos (8UL) /*!< MISC (Bit 8) */ +#define OTP_DEBUGEN_MISC_Msk (0x100UL) /*!< MISC (Bitfield-Mask: 0x01) */ +#define OTP_DEBUGEN_PROC1_SECURE_Pos (3UL) /*!< PROC1_SECURE (Bit 3) */ +#define OTP_DEBUGEN_PROC1_SECURE_Msk (0x8UL) /*!< PROC1_SECURE (Bitfield-Mask: 0x01) */ +#define OTP_DEBUGEN_PROC1_Pos (2UL) /*!< PROC1 (Bit 2) */ +#define OTP_DEBUGEN_PROC1_Msk (0x4UL) /*!< PROC1 (Bitfield-Mask: 0x01) */ +#define OTP_DEBUGEN_PROC0_SECURE_Pos (1UL) /*!< PROC0_SECURE (Bit 1) */ +#define OTP_DEBUGEN_PROC0_SECURE_Msk (0x2UL) /*!< PROC0_SECURE (Bitfield-Mask: 0x01) */ +#define OTP_DEBUGEN_PROC0_Pos (0UL) /*!< PROC0 (Bit 0) */ +#define OTP_DEBUGEN_PROC0_Msk (0x1UL) /*!< PROC0 (Bitfield-Mask: 0x01) */ +/* ===================================================== DEBUGEN_LOCK ====================================================== */ +#define OTP_DEBUGEN_LOCK_MISC_Pos (8UL) /*!< MISC (Bit 8) */ +#define OTP_DEBUGEN_LOCK_MISC_Msk (0x100UL) /*!< MISC (Bitfield-Mask: 0x01) */ +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_Pos (3UL) /*!< PROC1_SECURE (Bit 3) */ +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_Msk (0x8UL) /*!< PROC1_SECURE (Bitfield-Mask: 0x01) */ +#define OTP_DEBUGEN_LOCK_PROC1_Pos (2UL) /*!< PROC1 (Bit 2) */ +#define OTP_DEBUGEN_LOCK_PROC1_Msk (0x4UL) /*!< PROC1 (Bitfield-Mask: 0x01) */ +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_Pos (1UL) /*!< PROC0_SECURE (Bit 1) */ +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_Msk (0x2UL) /*!< PROC0_SECURE (Bitfield-Mask: 0x01) */ +#define OTP_DEBUGEN_LOCK_PROC0_Pos (0UL) /*!< PROC0 (Bit 0) */ +#define OTP_DEBUGEN_LOCK_PROC0_Msk (0x1UL) /*!< PROC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ARCHSEL ======================================================== */ +#define OTP_ARCHSEL_CORE1_Pos (1UL) /*!< CORE1 (Bit 1) */ +#define OTP_ARCHSEL_CORE1_Msk (0x2UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define OTP_ARCHSEL_CORE0_Pos (0UL) /*!< CORE0 (Bit 0) */ +#define OTP_ARCHSEL_CORE0_Msk (0x1UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +/* ==================================================== ARCHSEL_STATUS ===================================================== */ +#define OTP_ARCHSEL_STATUS_CORE1_Pos (1UL) /*!< CORE1 (Bit 1) */ +#define OTP_ARCHSEL_STATUS_CORE1_Msk (0x2UL) /*!< CORE1 (Bitfield-Mask: 0x01) */ +#define OTP_ARCHSEL_STATUS_CORE0_Pos (0UL) /*!< CORE0 (Bit 0) */ +#define OTP_ARCHSEL_STATUS_CORE0_Msk (0x1UL) /*!< CORE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BOOTDIS ======================================================== */ +#define OTP_BOOTDIS_NEXT_Pos (1UL) /*!< NEXT (Bit 1) */ +#define OTP_BOOTDIS_NEXT_Msk (0x2UL) /*!< NEXT (Bitfield-Mask: 0x01) */ +#define OTP_BOOTDIS_NOW_Pos (0UL) /*!< NOW (Bit 0) */ +#define OTP_BOOTDIS_NOW_Msk (0x1UL) /*!< NOW (Bitfield-Mask: 0x01) */ +/* ========================================================= INTR ========================================================== */ +#define OTP_INTR_APB_RD_NSEC_FAIL_Pos (4UL) /*!< APB_RD_NSEC_FAIL (Bit 4) */ +#define OTP_INTR_APB_RD_NSEC_FAIL_Msk (0x10UL) /*!< APB_RD_NSEC_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTR_APB_RD_SEC_FAIL_Pos (3UL) /*!< APB_RD_SEC_FAIL (Bit 3) */ +#define OTP_INTR_APB_RD_SEC_FAIL_Msk (0x8UL) /*!< APB_RD_SEC_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTR_APB_DCTRL_FAIL_Pos (2UL) /*!< APB_DCTRL_FAIL (Bit 2) */ +#define OTP_INTR_APB_DCTRL_FAIL_Msk (0x4UL) /*!< APB_DCTRL_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTR_SBPI_WR_FAIL_Pos (1UL) /*!< SBPI_WR_FAIL (Bit 1) */ +#define OTP_INTR_SBPI_WR_FAIL_Msk (0x2UL) /*!< SBPI_WR_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTR_SBPI_FLAG_N_Pos (0UL) /*!< SBPI_FLAG_N (Bit 0) */ +#define OTP_INTR_SBPI_FLAG_N_Msk (0x1UL) /*!< SBPI_FLAG_N (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ +#define OTP_INTE_APB_RD_NSEC_FAIL_Pos (4UL) /*!< APB_RD_NSEC_FAIL (Bit 4) */ +#define OTP_INTE_APB_RD_NSEC_FAIL_Msk (0x10UL) /*!< APB_RD_NSEC_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTE_APB_RD_SEC_FAIL_Pos (3UL) /*!< APB_RD_SEC_FAIL (Bit 3) */ +#define OTP_INTE_APB_RD_SEC_FAIL_Msk (0x8UL) /*!< APB_RD_SEC_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTE_APB_DCTRL_FAIL_Pos (2UL) /*!< APB_DCTRL_FAIL (Bit 2) */ +#define OTP_INTE_APB_DCTRL_FAIL_Msk (0x4UL) /*!< APB_DCTRL_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTE_SBPI_WR_FAIL_Pos (1UL) /*!< SBPI_WR_FAIL (Bit 1) */ +#define OTP_INTE_SBPI_WR_FAIL_Msk (0x2UL) /*!< SBPI_WR_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTE_SBPI_FLAG_N_Pos (0UL) /*!< SBPI_FLAG_N (Bit 0) */ +#define OTP_INTE_SBPI_FLAG_N_Msk (0x1UL) /*!< SBPI_FLAG_N (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define OTP_INTF_APB_RD_NSEC_FAIL_Pos (4UL) /*!< APB_RD_NSEC_FAIL (Bit 4) */ +#define OTP_INTF_APB_RD_NSEC_FAIL_Msk (0x10UL) /*!< APB_RD_NSEC_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTF_APB_RD_SEC_FAIL_Pos (3UL) /*!< APB_RD_SEC_FAIL (Bit 3) */ +#define OTP_INTF_APB_RD_SEC_FAIL_Msk (0x8UL) /*!< APB_RD_SEC_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTF_APB_DCTRL_FAIL_Pos (2UL) /*!< APB_DCTRL_FAIL (Bit 2) */ +#define OTP_INTF_APB_DCTRL_FAIL_Msk (0x4UL) /*!< APB_DCTRL_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTF_SBPI_WR_FAIL_Pos (1UL) /*!< SBPI_WR_FAIL (Bit 1) */ +#define OTP_INTF_SBPI_WR_FAIL_Msk (0x2UL) /*!< SBPI_WR_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTF_SBPI_FLAG_N_Pos (0UL) /*!< SBPI_FLAG_N (Bit 0) */ +#define OTP_INTF_SBPI_FLAG_N_Msk (0x1UL) /*!< SBPI_FLAG_N (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ +#define OTP_INTS_APB_RD_NSEC_FAIL_Pos (4UL) /*!< APB_RD_NSEC_FAIL (Bit 4) */ +#define OTP_INTS_APB_RD_NSEC_FAIL_Msk (0x10UL) /*!< APB_RD_NSEC_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTS_APB_RD_SEC_FAIL_Pos (3UL) /*!< APB_RD_SEC_FAIL (Bit 3) */ +#define OTP_INTS_APB_RD_SEC_FAIL_Msk (0x8UL) /*!< APB_RD_SEC_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTS_APB_DCTRL_FAIL_Pos (2UL) /*!< APB_DCTRL_FAIL (Bit 2) */ +#define OTP_INTS_APB_DCTRL_FAIL_Msk (0x4UL) /*!< APB_DCTRL_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTS_SBPI_WR_FAIL_Pos (1UL) /*!< SBPI_WR_FAIL (Bit 1) */ +#define OTP_INTS_SBPI_WR_FAIL_Msk (0x2UL) /*!< SBPI_WR_FAIL (Bitfield-Mask: 0x01) */ +#define OTP_INTS_SBPI_FLAG_N_Pos (0UL) /*!< SBPI_FLAG_N (Bit 0) */ +#define OTP_INTS_SBPI_FLAG_N_Msk (0x1UL) /*!< SBPI_FLAG_N (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIPID0 ======================================================== */ +#define OTP_DATA_CHIPID0_CHIPID0_Pos (0UL) /*!< CHIPID0 (Bit 0) */ +#define OTP_DATA_CHIPID0_CHIPID0_Msk (0xffffUL) /*!< CHIPID0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CHIPID1 ======================================================== */ +#define OTP_DATA_CHIPID1_CHIPID1_Pos (0UL) /*!< CHIPID1 (Bit 0) */ +#define OTP_DATA_CHIPID1_CHIPID1_Msk (0xffffUL) /*!< CHIPID1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CHIPID2 ======================================================== */ +#define OTP_DATA_CHIPID2_CHIPID2_Pos (0UL) /*!< CHIPID2 (Bit 0) */ +#define OTP_DATA_CHIPID2_CHIPID2_Msk (0xffffUL) /*!< CHIPID2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CHIPID3 ======================================================== */ +#define OTP_DATA_CHIPID3_CHIPID3_Pos (0UL) /*!< CHIPID3 (Bit 0) */ +#define OTP_DATA_CHIPID3_CHIPID3_Msk (0xffffUL) /*!< CHIPID3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID0 ======================================================== */ +#define OTP_DATA_RANDID0_RANDID0_Pos (0UL) /*!< RANDID0 (Bit 0) */ +#define OTP_DATA_RANDID0_RANDID0_Msk (0xffffUL) /*!< RANDID0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID1 ======================================================== */ +#define OTP_DATA_RANDID1_RANDID1_Pos (0UL) /*!< RANDID1 (Bit 0) */ +#define OTP_DATA_RANDID1_RANDID1_Msk (0xffffUL) /*!< RANDID1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID2 ======================================================== */ +#define OTP_DATA_RANDID2_RANDID2_Pos (0UL) /*!< RANDID2 (Bit 0) */ +#define OTP_DATA_RANDID2_RANDID2_Msk (0xffffUL) /*!< RANDID2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID3 ======================================================== */ +#define OTP_DATA_RANDID3_RANDID3_Pos (0UL) /*!< RANDID3 (Bit 0) */ +#define OTP_DATA_RANDID3_RANDID3_Msk (0xffffUL) /*!< RANDID3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID4 ======================================================== */ +#define OTP_DATA_RANDID4_RANDID4_Pos (0UL) /*!< RANDID4 (Bit 0) */ +#define OTP_DATA_RANDID4_RANDID4_Msk (0xffffUL) /*!< RANDID4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID5 ======================================================== */ +#define OTP_DATA_RANDID5_RANDID5_Pos (0UL) /*!< RANDID5 (Bit 0) */ +#define OTP_DATA_RANDID5_RANDID5_Msk (0xffffUL) /*!< RANDID5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID6 ======================================================== */ +#define OTP_DATA_RANDID6_RANDID6_Pos (0UL) /*!< RANDID6 (Bit 0) */ +#define OTP_DATA_RANDID6_RANDID6_Msk (0xffffUL) /*!< RANDID6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID7 ======================================================== */ +#define OTP_DATA_RANDID7_RANDID7_Pos (0UL) /*!< RANDID7 (Bit 0) */ +#define OTP_DATA_RANDID7_RANDID7_Msk (0xffffUL) /*!< RANDID7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== ROSC_CALIB ======================================================= */ +#define OTP_DATA_ROSC_CALIB_ROSC_CALIB_Pos (0UL) /*!< ROSC_CALIB (Bit 0) */ +#define OTP_DATA_ROSC_CALIB_ROSC_CALIB_Msk (0xffffUL) /*!< ROSC_CALIB (Bitfield-Mask: 0xffff) */ +/* ====================================================== LPOSC_CALIB ====================================================== */ +#define OTP_DATA_LPOSC_CALIB_LPOSC_CALIB_Pos (0UL) /*!< LPOSC_CALIB (Bit 0) */ +#define OTP_DATA_LPOSC_CALIB_LPOSC_CALIB_Msk (0xffffUL) /*!< LPOSC_CALIB (Bitfield-Mask: 0xffff) */ +/* ======================================================= NUM_GPIOS ======================================================= */ +#define OTP_DATA_NUM_GPIOS_NUM_GPIOS_Pos (0UL) /*!< NUM_GPIOS (Bit 0) */ +#define OTP_DATA_NUM_GPIOS_NUM_GPIOS_Msk (0xffUL) /*!< NUM_GPIOS (Bitfield-Mask: 0xff) */ +/* ======================================================= INFO_CRC0 ======================================================= */ +#define OTP_DATA_INFO_CRC0_INFO_CRC0_Pos (0UL) /*!< INFO_CRC0 (Bit 0) */ +#define OTP_DATA_INFO_CRC0_INFO_CRC0_Msk (0xffffUL) /*!< INFO_CRC0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= INFO_CRC1 ======================================================= */ +#define OTP_DATA_INFO_CRC1_INFO_CRC1_Pos (0UL) /*!< INFO_CRC1 (Bit 0) */ +#define OTP_DATA_INFO_CRC1_INFO_CRC1_Msk (0xffffUL) /*!< INFO_CRC1 (Bitfield-Mask: 0xffff) */ +/* ===================================================== FLASH_DEVINFO ===================================================== */ +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_Pos (12UL) /*!< CS1_SIZE (Bit 12) */ +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_Msk (0xf000UL) /*!< CS1_SIZE (Bitfield-Mask: 0x0f) */ +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_Pos (8UL) /*!< CS0_SIZE (Bit 8) */ +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_Msk (0xf00UL) /*!< CS0_SIZE (Bitfield-Mask: 0x0f) */ +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_Pos (7UL) /*!< D8H_ERASE_SUPPORTED (Bit 7) */ +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_Msk (0x80UL) /*!< D8H_ERASE_SUPPORTED (Bitfield-Mask: 0x01) */ +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_Pos (0UL) /*!< CS1_GPIO (Bit 0) */ +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_Msk (0x3fUL) /*!< CS1_GPIO (Bitfield-Mask: 0x3f) */ +/* =============================================== FLASH_PARTITION_SLOT_SIZE =============================================== */ +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_FLASH_PARTITION_SLOT_SIZE_Pos (0UL) /*!< FLASH_PARTITION_SLOT_SIZE (Bit 0) */ +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_FLASH_PARTITION_SLOT_SIZE_Msk (0xffffUL) /*!< FLASH_PARTITION_SLOT_SIZE (Bitfield-Mask: 0xffff) */ +/* ==================================================== BOOTSEL_LED_CFG ==================================================== */ +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_Pos (8UL) /*!< ACTIVELOW (Bit 8) */ +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_Msk (0x100UL) /*!< ACTIVELOW (Bitfield-Mask: 0x01) */ +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_Pos (0UL) /*!< PIN (Bit 0) */ +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_Msk (0x3fUL) /*!< PIN (Bitfield-Mask: 0x3f) */ +/* ==================================================== BOOTSEL_PLL_CFG ==================================================== */ +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_Pos (15UL) /*!< REFDIV (Bit 15) */ +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_Msk (0x8000UL) /*!< REFDIV (Bitfield-Mask: 0x01) */ +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_Pos (12UL) /*!< POSTDIV2 (Bit 12) */ +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_Msk (0x7000UL) /*!< POSTDIV2 (Bitfield-Mask: 0x07) */ +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_Pos (9UL) /*!< POSTDIV1 (Bit 9) */ +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_Msk (0xe00UL) /*!< POSTDIV1 (Bitfield-Mask: 0x07) */ +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_Pos (0UL) /*!< FBDIV (Bit 0) */ +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_Msk (0x1ffUL) /*!< FBDIV (Bitfield-Mask: 0x1ff) */ +/* =================================================== BOOTSEL_XOSC_CFG ==================================================== */ +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_Pos (14UL) /*!< RANGE (Bit 14) */ +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_Msk (0xc000UL) /*!< RANGE (Bitfield-Mask: 0x03) */ +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_Pos (0UL) /*!< STARTUP (Bit 0) */ +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_Msk (0x3fffUL) /*!< STARTUP (Bitfield-Mask: 0x3fff) */ +/* ================================================= USB_WHITE_LABEL_ADDR ================================================== */ +#define OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_Pos (0UL) /*!< USB_WHITE_LABEL_ADDR (Bit 0) */ +#define OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_Msk (0xffffUL) /*!< USB_WHITE_LABEL_ADDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== OTPBOOT_SRC ====================================================== */ +#define OTP_DATA_OTPBOOT_SRC_OTPBOOT_SRC_Pos (0UL) /*!< OTPBOOT_SRC (Bit 0) */ +#define OTP_DATA_OTPBOOT_SRC_OTPBOOT_SRC_Msk (0xffffUL) /*!< OTPBOOT_SRC (Bitfield-Mask: 0xffff) */ +/* ====================================================== OTPBOOT_LEN ====================================================== */ +#define OTP_DATA_OTPBOOT_LEN_OTPBOOT_LEN_Pos (0UL) /*!< OTPBOOT_LEN (Bit 0) */ +#define OTP_DATA_OTPBOOT_LEN_OTPBOOT_LEN_Msk (0xffffUL) /*!< OTPBOOT_LEN (Bitfield-Mask: 0xffff) */ +/* ===================================================== OTPBOOT_DST0 ====================================================== */ +#define OTP_DATA_OTPBOOT_DST0_OTPBOOT_DST0_Pos (0UL) /*!< OTPBOOT_DST0 (Bit 0) */ +#define OTP_DATA_OTPBOOT_DST0_OTPBOOT_DST0_Msk (0xffffUL) /*!< OTPBOOT_DST0 (Bitfield-Mask: 0xffff) */ +/* ===================================================== OTPBOOT_DST1 ====================================================== */ +#define OTP_DATA_OTPBOOT_DST1_OTPBOOT_DST1_Pos (0UL) /*!< OTPBOOT_DST1 (Bit 0) */ +#define OTP_DATA_OTPBOOT_DST1_OTPBOOT_DST1_Msk (0xffffUL) /*!< OTPBOOT_DST1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_0 ======================================================= */ +#define OTP_DATA_BOOTKEY0_0_BOOTKEY0_0_Pos (0UL) /*!< BOOTKEY0_0 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_0_BOOTKEY0_0_Msk (0xffffUL) /*!< BOOTKEY0_0 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_1 ======================================================= */ +#define OTP_DATA_BOOTKEY0_1_BOOTKEY0_1_Pos (0UL) /*!< BOOTKEY0_1 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_1_BOOTKEY0_1_Msk (0xffffUL) /*!< BOOTKEY0_1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_2 ======================================================= */ +#define OTP_DATA_BOOTKEY0_2_BOOTKEY0_2_Pos (0UL) /*!< BOOTKEY0_2 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_2_BOOTKEY0_2_Msk (0xffffUL) /*!< BOOTKEY0_2 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_3 ======================================================= */ +#define OTP_DATA_BOOTKEY0_3_BOOTKEY0_3_Pos (0UL) /*!< BOOTKEY0_3 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_3_BOOTKEY0_3_Msk (0xffffUL) /*!< BOOTKEY0_3 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_4 ======================================================= */ +#define OTP_DATA_BOOTKEY0_4_BOOTKEY0_4_Pos (0UL) /*!< BOOTKEY0_4 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_4_BOOTKEY0_4_Msk (0xffffUL) /*!< BOOTKEY0_4 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_5 ======================================================= */ +#define OTP_DATA_BOOTKEY0_5_BOOTKEY0_5_Pos (0UL) /*!< BOOTKEY0_5 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_5_BOOTKEY0_5_Msk (0xffffUL) /*!< BOOTKEY0_5 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_6 ======================================================= */ +#define OTP_DATA_BOOTKEY0_6_BOOTKEY0_6_Pos (0UL) /*!< BOOTKEY0_6 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_6_BOOTKEY0_6_Msk (0xffffUL) /*!< BOOTKEY0_6 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_7 ======================================================= */ +#define OTP_DATA_BOOTKEY0_7_BOOTKEY0_7_Pos (0UL) /*!< BOOTKEY0_7 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_7_BOOTKEY0_7_Msk (0xffffUL) /*!< BOOTKEY0_7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_8 ======================================================= */ +#define OTP_DATA_BOOTKEY0_8_BOOTKEY0_8_Pos (0UL) /*!< BOOTKEY0_8 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_8_BOOTKEY0_8_Msk (0xffffUL) /*!< BOOTKEY0_8 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_9 ======================================================= */ +#define OTP_DATA_BOOTKEY0_9_BOOTKEY0_9_Pos (0UL) /*!< BOOTKEY0_9 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_9_BOOTKEY0_9_Msk (0xffffUL) /*!< BOOTKEY0_9 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_10 ====================================================== */ +#define OTP_DATA_BOOTKEY0_10_BOOTKEY0_10_Pos (0UL) /*!< BOOTKEY0_10 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_10_BOOTKEY0_10_Msk (0xffffUL) /*!< BOOTKEY0_10 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_11 ====================================================== */ +#define OTP_DATA_BOOTKEY0_11_BOOTKEY0_11_Pos (0UL) /*!< BOOTKEY0_11 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_11_BOOTKEY0_11_Msk (0xffffUL) /*!< BOOTKEY0_11 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_12 ====================================================== */ +#define OTP_DATA_BOOTKEY0_12_BOOTKEY0_12_Pos (0UL) /*!< BOOTKEY0_12 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_12_BOOTKEY0_12_Msk (0xffffUL) /*!< BOOTKEY0_12 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_13 ====================================================== */ +#define OTP_DATA_BOOTKEY0_13_BOOTKEY0_13_Pos (0UL) /*!< BOOTKEY0_13 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_13_BOOTKEY0_13_Msk (0xffffUL) /*!< BOOTKEY0_13 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_14 ====================================================== */ +#define OTP_DATA_BOOTKEY0_14_BOOTKEY0_14_Pos (0UL) /*!< BOOTKEY0_14 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_14_BOOTKEY0_14_Msk (0xffffUL) /*!< BOOTKEY0_14 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_15 ====================================================== */ +#define OTP_DATA_BOOTKEY0_15_BOOTKEY0_15_Pos (0UL) /*!< BOOTKEY0_15 (Bit 0) */ +#define OTP_DATA_BOOTKEY0_15_BOOTKEY0_15_Msk (0xffffUL) /*!< BOOTKEY0_15 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_0 ======================================================= */ +#define OTP_DATA_BOOTKEY1_0_BOOTKEY1_0_Pos (0UL) /*!< BOOTKEY1_0 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_0_BOOTKEY1_0_Msk (0xffffUL) /*!< BOOTKEY1_0 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_1 ======================================================= */ +#define OTP_DATA_BOOTKEY1_1_BOOTKEY1_1_Pos (0UL) /*!< BOOTKEY1_1 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_1_BOOTKEY1_1_Msk (0xffffUL) /*!< BOOTKEY1_1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_2 ======================================================= */ +#define OTP_DATA_BOOTKEY1_2_BOOTKEY1_2_Pos (0UL) /*!< BOOTKEY1_2 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_2_BOOTKEY1_2_Msk (0xffffUL) /*!< BOOTKEY1_2 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_3 ======================================================= */ +#define OTP_DATA_BOOTKEY1_3_BOOTKEY1_3_Pos (0UL) /*!< BOOTKEY1_3 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_3_BOOTKEY1_3_Msk (0xffffUL) /*!< BOOTKEY1_3 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_4 ======================================================= */ +#define OTP_DATA_BOOTKEY1_4_BOOTKEY1_4_Pos (0UL) /*!< BOOTKEY1_4 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_4_BOOTKEY1_4_Msk (0xffffUL) /*!< BOOTKEY1_4 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_5 ======================================================= */ +#define OTP_DATA_BOOTKEY1_5_BOOTKEY1_5_Pos (0UL) /*!< BOOTKEY1_5 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_5_BOOTKEY1_5_Msk (0xffffUL) /*!< BOOTKEY1_5 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_6 ======================================================= */ +#define OTP_DATA_BOOTKEY1_6_BOOTKEY1_6_Pos (0UL) /*!< BOOTKEY1_6 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_6_BOOTKEY1_6_Msk (0xffffUL) /*!< BOOTKEY1_6 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_7 ======================================================= */ +#define OTP_DATA_BOOTKEY1_7_BOOTKEY1_7_Pos (0UL) /*!< BOOTKEY1_7 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_7_BOOTKEY1_7_Msk (0xffffUL) /*!< BOOTKEY1_7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_8 ======================================================= */ +#define OTP_DATA_BOOTKEY1_8_BOOTKEY1_8_Pos (0UL) /*!< BOOTKEY1_8 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_8_BOOTKEY1_8_Msk (0xffffUL) /*!< BOOTKEY1_8 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_9 ======================================================= */ +#define OTP_DATA_BOOTKEY1_9_BOOTKEY1_9_Pos (0UL) /*!< BOOTKEY1_9 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_9_BOOTKEY1_9_Msk (0xffffUL) /*!< BOOTKEY1_9 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_10 ====================================================== */ +#define OTP_DATA_BOOTKEY1_10_BOOTKEY1_10_Pos (0UL) /*!< BOOTKEY1_10 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_10_BOOTKEY1_10_Msk (0xffffUL) /*!< BOOTKEY1_10 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_11 ====================================================== */ +#define OTP_DATA_BOOTKEY1_11_BOOTKEY1_11_Pos (0UL) /*!< BOOTKEY1_11 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_11_BOOTKEY1_11_Msk (0xffffUL) /*!< BOOTKEY1_11 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_12 ====================================================== */ +#define OTP_DATA_BOOTKEY1_12_BOOTKEY1_12_Pos (0UL) /*!< BOOTKEY1_12 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_12_BOOTKEY1_12_Msk (0xffffUL) /*!< BOOTKEY1_12 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_13 ====================================================== */ +#define OTP_DATA_BOOTKEY1_13_BOOTKEY1_13_Pos (0UL) /*!< BOOTKEY1_13 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_13_BOOTKEY1_13_Msk (0xffffUL) /*!< BOOTKEY1_13 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_14 ====================================================== */ +#define OTP_DATA_BOOTKEY1_14_BOOTKEY1_14_Pos (0UL) /*!< BOOTKEY1_14 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_14_BOOTKEY1_14_Msk (0xffffUL) /*!< BOOTKEY1_14 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_15 ====================================================== */ +#define OTP_DATA_BOOTKEY1_15_BOOTKEY1_15_Pos (0UL) /*!< BOOTKEY1_15 (Bit 0) */ +#define OTP_DATA_BOOTKEY1_15_BOOTKEY1_15_Msk (0xffffUL) /*!< BOOTKEY1_15 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_0 ======================================================= */ +#define OTP_DATA_BOOTKEY2_0_BOOTKEY2_0_Pos (0UL) /*!< BOOTKEY2_0 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_0_BOOTKEY2_0_Msk (0xffffUL) /*!< BOOTKEY2_0 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_1 ======================================================= */ +#define OTP_DATA_BOOTKEY2_1_BOOTKEY2_1_Pos (0UL) /*!< BOOTKEY2_1 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_1_BOOTKEY2_1_Msk (0xffffUL) /*!< BOOTKEY2_1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_2 ======================================================= */ +#define OTP_DATA_BOOTKEY2_2_BOOTKEY2_2_Pos (0UL) /*!< BOOTKEY2_2 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_2_BOOTKEY2_2_Msk (0xffffUL) /*!< BOOTKEY2_2 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_3 ======================================================= */ +#define OTP_DATA_BOOTKEY2_3_BOOTKEY2_3_Pos (0UL) /*!< BOOTKEY2_3 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_3_BOOTKEY2_3_Msk (0xffffUL) /*!< BOOTKEY2_3 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_4 ======================================================= */ +#define OTP_DATA_BOOTKEY2_4_BOOTKEY2_4_Pos (0UL) /*!< BOOTKEY2_4 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_4_BOOTKEY2_4_Msk (0xffffUL) /*!< BOOTKEY2_4 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_5 ======================================================= */ +#define OTP_DATA_BOOTKEY2_5_BOOTKEY2_5_Pos (0UL) /*!< BOOTKEY2_5 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_5_BOOTKEY2_5_Msk (0xffffUL) /*!< BOOTKEY2_5 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_6 ======================================================= */ +#define OTP_DATA_BOOTKEY2_6_BOOTKEY2_6_Pos (0UL) /*!< BOOTKEY2_6 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_6_BOOTKEY2_6_Msk (0xffffUL) /*!< BOOTKEY2_6 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_7 ======================================================= */ +#define OTP_DATA_BOOTKEY2_7_BOOTKEY2_7_Pos (0UL) /*!< BOOTKEY2_7 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_7_BOOTKEY2_7_Msk (0xffffUL) /*!< BOOTKEY2_7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_8 ======================================================= */ +#define OTP_DATA_BOOTKEY2_8_BOOTKEY2_8_Pos (0UL) /*!< BOOTKEY2_8 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_8_BOOTKEY2_8_Msk (0xffffUL) /*!< BOOTKEY2_8 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_9 ======================================================= */ +#define OTP_DATA_BOOTKEY2_9_BOOTKEY2_9_Pos (0UL) /*!< BOOTKEY2_9 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_9_BOOTKEY2_9_Msk (0xffffUL) /*!< BOOTKEY2_9 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_10 ====================================================== */ +#define OTP_DATA_BOOTKEY2_10_BOOTKEY2_10_Pos (0UL) /*!< BOOTKEY2_10 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_10_BOOTKEY2_10_Msk (0xffffUL) /*!< BOOTKEY2_10 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_11 ====================================================== */ +#define OTP_DATA_BOOTKEY2_11_BOOTKEY2_11_Pos (0UL) /*!< BOOTKEY2_11 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_11_BOOTKEY2_11_Msk (0xffffUL) /*!< BOOTKEY2_11 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_12 ====================================================== */ +#define OTP_DATA_BOOTKEY2_12_BOOTKEY2_12_Pos (0UL) /*!< BOOTKEY2_12 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_12_BOOTKEY2_12_Msk (0xffffUL) /*!< BOOTKEY2_12 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_13 ====================================================== */ +#define OTP_DATA_BOOTKEY2_13_BOOTKEY2_13_Pos (0UL) /*!< BOOTKEY2_13 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_13_BOOTKEY2_13_Msk (0xffffUL) /*!< BOOTKEY2_13 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_14 ====================================================== */ +#define OTP_DATA_BOOTKEY2_14_BOOTKEY2_14_Pos (0UL) /*!< BOOTKEY2_14 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_14_BOOTKEY2_14_Msk (0xffffUL) /*!< BOOTKEY2_14 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_15 ====================================================== */ +#define OTP_DATA_BOOTKEY2_15_BOOTKEY2_15_Pos (0UL) /*!< BOOTKEY2_15 (Bit 0) */ +#define OTP_DATA_BOOTKEY2_15_BOOTKEY2_15_Msk (0xffffUL) /*!< BOOTKEY2_15 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_0 ======================================================= */ +#define OTP_DATA_BOOTKEY3_0_BOOTKEY3_0_Pos (0UL) /*!< BOOTKEY3_0 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_0_BOOTKEY3_0_Msk (0xffffUL) /*!< BOOTKEY3_0 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_1 ======================================================= */ +#define OTP_DATA_BOOTKEY3_1_BOOTKEY3_1_Pos (0UL) /*!< BOOTKEY3_1 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_1_BOOTKEY3_1_Msk (0xffffUL) /*!< BOOTKEY3_1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_2 ======================================================= */ +#define OTP_DATA_BOOTKEY3_2_BOOTKEY3_2_Pos (0UL) /*!< BOOTKEY3_2 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_2_BOOTKEY3_2_Msk (0xffffUL) /*!< BOOTKEY3_2 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_3 ======================================================= */ +#define OTP_DATA_BOOTKEY3_3_BOOTKEY3_3_Pos (0UL) /*!< BOOTKEY3_3 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_3_BOOTKEY3_3_Msk (0xffffUL) /*!< BOOTKEY3_3 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_4 ======================================================= */ +#define OTP_DATA_BOOTKEY3_4_BOOTKEY3_4_Pos (0UL) /*!< BOOTKEY3_4 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_4_BOOTKEY3_4_Msk (0xffffUL) /*!< BOOTKEY3_4 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_5 ======================================================= */ +#define OTP_DATA_BOOTKEY3_5_BOOTKEY3_5_Pos (0UL) /*!< BOOTKEY3_5 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_5_BOOTKEY3_5_Msk (0xffffUL) /*!< BOOTKEY3_5 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_6 ======================================================= */ +#define OTP_DATA_BOOTKEY3_6_BOOTKEY3_6_Pos (0UL) /*!< BOOTKEY3_6 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_6_BOOTKEY3_6_Msk (0xffffUL) /*!< BOOTKEY3_6 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_7 ======================================================= */ +#define OTP_DATA_BOOTKEY3_7_BOOTKEY3_7_Pos (0UL) /*!< BOOTKEY3_7 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_7_BOOTKEY3_7_Msk (0xffffUL) /*!< BOOTKEY3_7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_8 ======================================================= */ +#define OTP_DATA_BOOTKEY3_8_BOOTKEY3_8_Pos (0UL) /*!< BOOTKEY3_8 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_8_BOOTKEY3_8_Msk (0xffffUL) /*!< BOOTKEY3_8 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_9 ======================================================= */ +#define OTP_DATA_BOOTKEY3_9_BOOTKEY3_9_Pos (0UL) /*!< BOOTKEY3_9 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_9_BOOTKEY3_9_Msk (0xffffUL) /*!< BOOTKEY3_9 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_10 ====================================================== */ +#define OTP_DATA_BOOTKEY3_10_BOOTKEY3_10_Pos (0UL) /*!< BOOTKEY3_10 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_10_BOOTKEY3_10_Msk (0xffffUL) /*!< BOOTKEY3_10 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_11 ====================================================== */ +#define OTP_DATA_BOOTKEY3_11_BOOTKEY3_11_Pos (0UL) /*!< BOOTKEY3_11 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_11_BOOTKEY3_11_Msk (0xffffUL) /*!< BOOTKEY3_11 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_12 ====================================================== */ +#define OTP_DATA_BOOTKEY3_12_BOOTKEY3_12_Pos (0UL) /*!< BOOTKEY3_12 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_12_BOOTKEY3_12_Msk (0xffffUL) /*!< BOOTKEY3_12 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_13 ====================================================== */ +#define OTP_DATA_BOOTKEY3_13_BOOTKEY3_13_Pos (0UL) /*!< BOOTKEY3_13 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_13_BOOTKEY3_13_Msk (0xffffUL) /*!< BOOTKEY3_13 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_14 ====================================================== */ +#define OTP_DATA_BOOTKEY3_14_BOOTKEY3_14_Pos (0UL) /*!< BOOTKEY3_14 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_14_BOOTKEY3_14_Msk (0xffffUL) /*!< BOOTKEY3_14 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_15 ====================================================== */ +#define OTP_DATA_BOOTKEY3_15_BOOTKEY3_15_Pos (0UL) /*!< BOOTKEY3_15 (Bit 0) */ +#define OTP_DATA_BOOTKEY3_15_BOOTKEY3_15_Msk (0xffffUL) /*!< BOOTKEY3_15 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_0 ========================================================= */ +#define OTP_DATA_KEY1_0_KEY1_0_Pos (0UL) /*!< KEY1_0 (Bit 0) */ +#define OTP_DATA_KEY1_0_KEY1_0_Msk (0xffffUL) /*!< KEY1_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_1 ========================================================= */ +#define OTP_DATA_KEY1_1_KEY1_1_Pos (0UL) /*!< KEY1_1 (Bit 0) */ +#define OTP_DATA_KEY1_1_KEY1_1_Msk (0xffffUL) /*!< KEY1_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_2 ========================================================= */ +#define OTP_DATA_KEY1_2_KEY1_2_Pos (0UL) /*!< KEY1_2 (Bit 0) */ +#define OTP_DATA_KEY1_2_KEY1_2_Msk (0xffffUL) /*!< KEY1_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_3 ========================================================= */ +#define OTP_DATA_KEY1_3_KEY1_3_Pos (0UL) /*!< KEY1_3 (Bit 0) */ +#define OTP_DATA_KEY1_3_KEY1_3_Msk (0xffffUL) /*!< KEY1_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_4 ========================================================= */ +#define OTP_DATA_KEY1_4_KEY1_4_Pos (0UL) /*!< KEY1_4 (Bit 0) */ +#define OTP_DATA_KEY1_4_KEY1_4_Msk (0xffffUL) /*!< KEY1_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_5 ========================================================= */ +#define OTP_DATA_KEY1_5_KEY1_5_Pos (0UL) /*!< KEY1_5 (Bit 0) */ +#define OTP_DATA_KEY1_5_KEY1_5_Msk (0xffffUL) /*!< KEY1_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_6 ========================================================= */ +#define OTP_DATA_KEY1_6_KEY1_6_Pos (0UL) /*!< KEY1_6 (Bit 0) */ +#define OTP_DATA_KEY1_6_KEY1_6_Msk (0xffffUL) /*!< KEY1_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_7 ========================================================= */ +#define OTP_DATA_KEY1_7_KEY1_7_Pos (0UL) /*!< KEY1_7 (Bit 0) */ +#define OTP_DATA_KEY1_7_KEY1_7_Msk (0xffffUL) /*!< KEY1_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_0 ========================================================= */ +#define OTP_DATA_KEY2_0_KEY2_0_Pos (0UL) /*!< KEY2_0 (Bit 0) */ +#define OTP_DATA_KEY2_0_KEY2_0_Msk (0xffffUL) /*!< KEY2_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_1 ========================================================= */ +#define OTP_DATA_KEY2_1_KEY2_1_Pos (0UL) /*!< KEY2_1 (Bit 0) */ +#define OTP_DATA_KEY2_1_KEY2_1_Msk (0xffffUL) /*!< KEY2_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_2 ========================================================= */ +#define OTP_DATA_KEY2_2_KEY2_2_Pos (0UL) /*!< KEY2_2 (Bit 0) */ +#define OTP_DATA_KEY2_2_KEY2_2_Msk (0xffffUL) /*!< KEY2_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_3 ========================================================= */ +#define OTP_DATA_KEY2_3_KEY2_3_Pos (0UL) /*!< KEY2_3 (Bit 0) */ +#define OTP_DATA_KEY2_3_KEY2_3_Msk (0xffffUL) /*!< KEY2_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_4 ========================================================= */ +#define OTP_DATA_KEY2_4_KEY2_4_Pos (0UL) /*!< KEY2_4 (Bit 0) */ +#define OTP_DATA_KEY2_4_KEY2_4_Msk (0xffffUL) /*!< KEY2_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_5 ========================================================= */ +#define OTP_DATA_KEY2_5_KEY2_5_Pos (0UL) /*!< KEY2_5 (Bit 0) */ +#define OTP_DATA_KEY2_5_KEY2_5_Msk (0xffffUL) /*!< KEY2_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_6 ========================================================= */ +#define OTP_DATA_KEY2_6_KEY2_6_Pos (0UL) /*!< KEY2_6 (Bit 0) */ +#define OTP_DATA_KEY2_6_KEY2_6_Msk (0xffffUL) /*!< KEY2_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_7 ========================================================= */ +#define OTP_DATA_KEY2_7_KEY2_7_Pos (0UL) /*!< KEY2_7 (Bit 0) */ +#define OTP_DATA_KEY2_7_KEY2_7_Msk (0xffffUL) /*!< KEY2_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_0 ========================================================= */ +#define OTP_DATA_KEY3_0_KEY3_0_Pos (0UL) /*!< KEY3_0 (Bit 0) */ +#define OTP_DATA_KEY3_0_KEY3_0_Msk (0xffffUL) /*!< KEY3_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_1 ========================================================= */ +#define OTP_DATA_KEY3_1_KEY3_1_Pos (0UL) /*!< KEY3_1 (Bit 0) */ +#define OTP_DATA_KEY3_1_KEY3_1_Msk (0xffffUL) /*!< KEY3_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_2 ========================================================= */ +#define OTP_DATA_KEY3_2_KEY3_2_Pos (0UL) /*!< KEY3_2 (Bit 0) */ +#define OTP_DATA_KEY3_2_KEY3_2_Msk (0xffffUL) /*!< KEY3_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_3 ========================================================= */ +#define OTP_DATA_KEY3_3_KEY3_3_Pos (0UL) /*!< KEY3_3 (Bit 0) */ +#define OTP_DATA_KEY3_3_KEY3_3_Msk (0xffffUL) /*!< KEY3_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_4 ========================================================= */ +#define OTP_DATA_KEY3_4_KEY3_4_Pos (0UL) /*!< KEY3_4 (Bit 0) */ +#define OTP_DATA_KEY3_4_KEY3_4_Msk (0xffffUL) /*!< KEY3_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_5 ========================================================= */ +#define OTP_DATA_KEY3_5_KEY3_5_Pos (0UL) /*!< KEY3_5 (Bit 0) */ +#define OTP_DATA_KEY3_5_KEY3_5_Msk (0xffffUL) /*!< KEY3_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_6 ========================================================= */ +#define OTP_DATA_KEY3_6_KEY3_6_Pos (0UL) /*!< KEY3_6 (Bit 0) */ +#define OTP_DATA_KEY3_6_KEY3_6_Msk (0xffffUL) /*!< KEY3_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_7 ========================================================= */ +#define OTP_DATA_KEY3_7_KEY3_7_Pos (0UL) /*!< KEY3_7 (Bit 0) */ +#define OTP_DATA_KEY3_7_KEY3_7_Msk (0xffffUL) /*!< KEY3_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_0 ========================================================= */ +#define OTP_DATA_KEY4_0_KEY4_0_Pos (0UL) /*!< KEY4_0 (Bit 0) */ +#define OTP_DATA_KEY4_0_KEY4_0_Msk (0xffffUL) /*!< KEY4_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_1 ========================================================= */ +#define OTP_DATA_KEY4_1_KEY4_1_Pos (0UL) /*!< KEY4_1 (Bit 0) */ +#define OTP_DATA_KEY4_1_KEY4_1_Msk (0xffffUL) /*!< KEY4_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_2 ========================================================= */ +#define OTP_DATA_KEY4_2_KEY4_2_Pos (0UL) /*!< KEY4_2 (Bit 0) */ +#define OTP_DATA_KEY4_2_KEY4_2_Msk (0xffffUL) /*!< KEY4_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_3 ========================================================= */ +#define OTP_DATA_KEY4_3_KEY4_3_Pos (0UL) /*!< KEY4_3 (Bit 0) */ +#define OTP_DATA_KEY4_3_KEY4_3_Msk (0xffffUL) /*!< KEY4_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_4 ========================================================= */ +#define OTP_DATA_KEY4_4_KEY4_4_Pos (0UL) /*!< KEY4_4 (Bit 0) */ +#define OTP_DATA_KEY4_4_KEY4_4_Msk (0xffffUL) /*!< KEY4_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_5 ========================================================= */ +#define OTP_DATA_KEY4_5_KEY4_5_Pos (0UL) /*!< KEY4_5 (Bit 0) */ +#define OTP_DATA_KEY4_5_KEY4_5_Msk (0xffffUL) /*!< KEY4_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_6 ========================================================= */ +#define OTP_DATA_KEY4_6_KEY4_6_Pos (0UL) /*!< KEY4_6 (Bit 0) */ +#define OTP_DATA_KEY4_6_KEY4_6_Msk (0xffffUL) /*!< KEY4_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_7 ========================================================= */ +#define OTP_DATA_KEY4_7_KEY4_7_Pos (0UL) /*!< KEY4_7 (Bit 0) */ +#define OTP_DATA_KEY4_7_KEY4_7_Msk (0xffffUL) /*!< KEY4_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_0 ========================================================= */ +#define OTP_DATA_KEY5_0_KEY5_0_Pos (0UL) /*!< KEY5_0 (Bit 0) */ +#define OTP_DATA_KEY5_0_KEY5_0_Msk (0xffffUL) /*!< KEY5_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_1 ========================================================= */ +#define OTP_DATA_KEY5_1_KEY5_1_Pos (0UL) /*!< KEY5_1 (Bit 0) */ +#define OTP_DATA_KEY5_1_KEY5_1_Msk (0xffffUL) /*!< KEY5_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_2 ========================================================= */ +#define OTP_DATA_KEY5_2_KEY5_2_Pos (0UL) /*!< KEY5_2 (Bit 0) */ +#define OTP_DATA_KEY5_2_KEY5_2_Msk (0xffffUL) /*!< KEY5_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_3 ========================================================= */ +#define OTP_DATA_KEY5_3_KEY5_3_Pos (0UL) /*!< KEY5_3 (Bit 0) */ +#define OTP_DATA_KEY5_3_KEY5_3_Msk (0xffffUL) /*!< KEY5_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_4 ========================================================= */ +#define OTP_DATA_KEY5_4_KEY5_4_Pos (0UL) /*!< KEY5_4 (Bit 0) */ +#define OTP_DATA_KEY5_4_KEY5_4_Msk (0xffffUL) /*!< KEY5_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_5 ========================================================= */ +#define OTP_DATA_KEY5_5_KEY5_5_Pos (0UL) /*!< KEY5_5 (Bit 0) */ +#define OTP_DATA_KEY5_5_KEY5_5_Msk (0xffffUL) /*!< KEY5_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_6 ========================================================= */ +#define OTP_DATA_KEY5_6_KEY5_6_Pos (0UL) /*!< KEY5_6 (Bit 0) */ +#define OTP_DATA_KEY5_6_KEY5_6_Msk (0xffffUL) /*!< KEY5_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_7 ========================================================= */ +#define OTP_DATA_KEY5_7_KEY5_7_Pos (0UL) /*!< KEY5_7 (Bit 0) */ +#define OTP_DATA_KEY5_7_KEY5_7_Msk (0xffffUL) /*!< KEY5_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_0 ========================================================= */ +#define OTP_DATA_KEY6_0_KEY6_0_Pos (0UL) /*!< KEY6_0 (Bit 0) */ +#define OTP_DATA_KEY6_0_KEY6_0_Msk (0xffffUL) /*!< KEY6_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_1 ========================================================= */ +#define OTP_DATA_KEY6_1_KEY6_1_Pos (0UL) /*!< KEY6_1 (Bit 0) */ +#define OTP_DATA_KEY6_1_KEY6_1_Msk (0xffffUL) /*!< KEY6_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_2 ========================================================= */ +#define OTP_DATA_KEY6_2_KEY6_2_Pos (0UL) /*!< KEY6_2 (Bit 0) */ +#define OTP_DATA_KEY6_2_KEY6_2_Msk (0xffffUL) /*!< KEY6_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_3 ========================================================= */ +#define OTP_DATA_KEY6_3_KEY6_3_Pos (0UL) /*!< KEY6_3 (Bit 0) */ +#define OTP_DATA_KEY6_3_KEY6_3_Msk (0xffffUL) /*!< KEY6_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_4 ========================================================= */ +#define OTP_DATA_KEY6_4_KEY6_4_Pos (0UL) /*!< KEY6_4 (Bit 0) */ +#define OTP_DATA_KEY6_4_KEY6_4_Msk (0xffffUL) /*!< KEY6_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_5 ========================================================= */ +#define OTP_DATA_KEY6_5_KEY6_5_Pos (0UL) /*!< KEY6_5 (Bit 0) */ +#define OTP_DATA_KEY6_5_KEY6_5_Msk (0xffffUL) /*!< KEY6_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_6 ========================================================= */ +#define OTP_DATA_KEY6_6_KEY6_6_Pos (0UL) /*!< KEY6_6 (Bit 0) */ +#define OTP_DATA_KEY6_6_KEY6_6_Msk (0xffffUL) /*!< KEY6_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_7 ========================================================= */ +#define OTP_DATA_KEY6_7_KEY6_7_Pos (0UL) /*!< KEY6_7 (Bit 0) */ +#define OTP_DATA_KEY6_7_KEY6_7_Msk (0xffffUL) /*!< KEY6_7 (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA_RAW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIPID0 ======================================================== */ +#define OTP_DATA_RAW_CHIPID0_CHIPID0_Pos (0UL) /*!< CHIPID0 (Bit 0) */ +#define OTP_DATA_RAW_CHIPID0_CHIPID0_Msk (0xffffUL) /*!< CHIPID0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CHIPID1 ======================================================== */ +#define OTP_DATA_RAW_CHIPID1_CHIPID1_Pos (0UL) /*!< CHIPID1 (Bit 0) */ +#define OTP_DATA_RAW_CHIPID1_CHIPID1_Msk (0xffffUL) /*!< CHIPID1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CHIPID2 ======================================================== */ +#define OTP_DATA_RAW_CHIPID2_CHIPID2_Pos (0UL) /*!< CHIPID2 (Bit 0) */ +#define OTP_DATA_RAW_CHIPID2_CHIPID2_Msk (0xffffUL) /*!< CHIPID2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CHIPID3 ======================================================== */ +#define OTP_DATA_RAW_CHIPID3_CHIPID3_Pos (0UL) /*!< CHIPID3 (Bit 0) */ +#define OTP_DATA_RAW_CHIPID3_CHIPID3_Msk (0xffffUL) /*!< CHIPID3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID0 ======================================================== */ +#define OTP_DATA_RAW_RANDID0_RANDID0_Pos (0UL) /*!< RANDID0 (Bit 0) */ +#define OTP_DATA_RAW_RANDID0_RANDID0_Msk (0xffffUL) /*!< RANDID0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID1 ======================================================== */ +#define OTP_DATA_RAW_RANDID1_RANDID1_Pos (0UL) /*!< RANDID1 (Bit 0) */ +#define OTP_DATA_RAW_RANDID1_RANDID1_Msk (0xffffUL) /*!< RANDID1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID2 ======================================================== */ +#define OTP_DATA_RAW_RANDID2_RANDID2_Pos (0UL) /*!< RANDID2 (Bit 0) */ +#define OTP_DATA_RAW_RANDID2_RANDID2_Msk (0xffffUL) /*!< RANDID2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID3 ======================================================== */ +#define OTP_DATA_RAW_RANDID3_RANDID3_Pos (0UL) /*!< RANDID3 (Bit 0) */ +#define OTP_DATA_RAW_RANDID3_RANDID3_Msk (0xffffUL) /*!< RANDID3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID4 ======================================================== */ +#define OTP_DATA_RAW_RANDID4_RANDID4_Pos (0UL) /*!< RANDID4 (Bit 0) */ +#define OTP_DATA_RAW_RANDID4_RANDID4_Msk (0xffffUL) /*!< RANDID4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID5 ======================================================== */ +#define OTP_DATA_RAW_RANDID5_RANDID5_Pos (0UL) /*!< RANDID5 (Bit 0) */ +#define OTP_DATA_RAW_RANDID5_RANDID5_Msk (0xffffUL) /*!< RANDID5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID6 ======================================================== */ +#define OTP_DATA_RAW_RANDID6_RANDID6_Pos (0UL) /*!< RANDID6 (Bit 0) */ +#define OTP_DATA_RAW_RANDID6_RANDID6_Msk (0xffffUL) /*!< RANDID6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== RANDID7 ======================================================== */ +#define OTP_DATA_RAW_RANDID7_RANDID7_Pos (0UL) /*!< RANDID7 (Bit 0) */ +#define OTP_DATA_RAW_RANDID7_RANDID7_Msk (0xffffUL) /*!< RANDID7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== ROSC_CALIB ======================================================= */ +#define OTP_DATA_RAW_ROSC_CALIB_ROSC_CALIB_Pos (0UL) /*!< ROSC_CALIB (Bit 0) */ +#define OTP_DATA_RAW_ROSC_CALIB_ROSC_CALIB_Msk (0xffffUL) /*!< ROSC_CALIB (Bitfield-Mask: 0xffff) */ +/* ====================================================== LPOSC_CALIB ====================================================== */ +#define OTP_DATA_RAW_LPOSC_CALIB_LPOSC_CALIB_Pos (0UL) /*!< LPOSC_CALIB (Bit 0) */ +#define OTP_DATA_RAW_LPOSC_CALIB_LPOSC_CALIB_Msk (0xffffUL) /*!< LPOSC_CALIB (Bitfield-Mask: 0xffff) */ +/* ======================================================= NUM_GPIOS ======================================================= */ +#define OTP_DATA_RAW_NUM_GPIOS_NUM_GPIOS_Pos (0UL) /*!< NUM_GPIOS (Bit 0) */ +#define OTP_DATA_RAW_NUM_GPIOS_NUM_GPIOS_Msk (0xffUL) /*!< NUM_GPIOS (Bitfield-Mask: 0xff) */ +/* ======================================================= INFO_CRC0 ======================================================= */ +#define OTP_DATA_RAW_INFO_CRC0_INFO_CRC0_Pos (0UL) /*!< INFO_CRC0 (Bit 0) */ +#define OTP_DATA_RAW_INFO_CRC0_INFO_CRC0_Msk (0xffffUL) /*!< INFO_CRC0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= INFO_CRC1 ======================================================= */ +#define OTP_DATA_RAW_INFO_CRC1_INFO_CRC1_Pos (0UL) /*!< INFO_CRC1 (Bit 0) */ +#define OTP_DATA_RAW_INFO_CRC1_INFO_CRC1_Msk (0xffffUL) /*!< INFO_CRC1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CRIT0 ========================================================= */ +#define OTP_DATA_RAW_CRIT0_RISCV_DISABLE_Pos (1UL) /*!< RISCV_DISABLE (Bit 1) */ +#define OTP_DATA_RAW_CRIT0_RISCV_DISABLE_Msk (0x2UL) /*!< RISCV_DISABLE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_CRIT0_ARM_DISABLE_Pos (0UL) /*!< ARM_DISABLE (Bit 0) */ +#define OTP_DATA_RAW_CRIT0_ARM_DISABLE_Msk (0x1UL) /*!< ARM_DISABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CRIT0_R1 ======================================================== */ +#define OTP_DATA_RAW_CRIT0_R1_CRIT0_R1_Pos (0UL) /*!< CRIT0_R1 (Bit 0) */ +#define OTP_DATA_RAW_CRIT0_R1_CRIT0_R1_Msk (0xffffffUL) /*!< CRIT0_R1 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT0_R2 ======================================================== */ +#define OTP_DATA_RAW_CRIT0_R2_CRIT0_R2_Pos (0UL) /*!< CRIT0_R2 (Bit 0) */ +#define OTP_DATA_RAW_CRIT0_R2_CRIT0_R2_Msk (0xffffffUL) /*!< CRIT0_R2 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT0_R3 ======================================================== */ +#define OTP_DATA_RAW_CRIT0_R3_CRIT0_R3_Pos (0UL) /*!< CRIT0_R3 (Bit 0) */ +#define OTP_DATA_RAW_CRIT0_R3_CRIT0_R3_Msk (0xffffffUL) /*!< CRIT0_R3 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT0_R4 ======================================================== */ +#define OTP_DATA_RAW_CRIT0_R4_CRIT0_R4_Pos (0UL) /*!< CRIT0_R4 (Bit 0) */ +#define OTP_DATA_RAW_CRIT0_R4_CRIT0_R4_Msk (0xffffffUL) /*!< CRIT0_R4 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT0_R5 ======================================================== */ +#define OTP_DATA_RAW_CRIT0_R5_CRIT0_R5_Pos (0UL) /*!< CRIT0_R5 (Bit 0) */ +#define OTP_DATA_RAW_CRIT0_R5_CRIT0_R5_Msk (0xffffffUL) /*!< CRIT0_R5 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT0_R6 ======================================================== */ +#define OTP_DATA_RAW_CRIT0_R6_CRIT0_R6_Pos (0UL) /*!< CRIT0_R6 (Bit 0) */ +#define OTP_DATA_RAW_CRIT0_R6_CRIT0_R6_Msk (0xffffffUL) /*!< CRIT0_R6 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT0_R7 ======================================================== */ +#define OTP_DATA_RAW_CRIT0_R7_CRIT0_R7_Pos (0UL) /*!< CRIT0_R7 (Bit 0) */ +#define OTP_DATA_RAW_CRIT0_R7_CRIT0_R7_Msk (0xffffffUL) /*!< CRIT0_R7 (Bitfield-Mask: 0xffffff) */ +/* ========================================================= CRIT1 ========================================================= */ +#define OTP_DATA_RAW_CRIT1_GLITCH_DETECTOR_SENS_Pos (5UL) /*!< GLITCH_DETECTOR_SENS (Bit 5) */ +#define OTP_DATA_RAW_CRIT1_GLITCH_DETECTOR_SENS_Msk (0x60UL) /*!< GLITCH_DETECTOR_SENS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_CRIT1_GLITCH_DETECTOR_ENABLE_Pos (4UL) /*!< GLITCH_DETECTOR_ENABLE (Bit 4) */ +#define OTP_DATA_RAW_CRIT1_GLITCH_DETECTOR_ENABLE_Msk (0x10UL) /*!< GLITCH_DETECTOR_ENABLE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_CRIT1_BOOT_ARCH_Pos (3UL) /*!< BOOT_ARCH (Bit 3) */ +#define OTP_DATA_RAW_CRIT1_BOOT_ARCH_Msk (0x8UL) /*!< BOOT_ARCH (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_CRIT1_DEBUG_DISABLE_Pos (2UL) /*!< DEBUG_DISABLE (Bit 2) */ +#define OTP_DATA_RAW_CRIT1_DEBUG_DISABLE_Msk (0x4UL) /*!< DEBUG_DISABLE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_CRIT1_SECURE_DEBUG_DISABLE_Pos (1UL) /*!< SECURE_DEBUG_DISABLE (Bit 1) */ +#define OTP_DATA_RAW_CRIT1_SECURE_DEBUG_DISABLE_Msk (0x2UL) /*!< SECURE_DEBUG_DISABLE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_CRIT1_SECURE_BOOT_ENABLE_Pos (0UL) /*!< SECURE_BOOT_ENABLE (Bit 0) */ +#define OTP_DATA_RAW_CRIT1_SECURE_BOOT_ENABLE_Msk (0x1UL) /*!< SECURE_BOOT_ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CRIT1_R1 ======================================================== */ +#define OTP_DATA_RAW_CRIT1_R1_CRIT1_R1_Pos (0UL) /*!< CRIT1_R1 (Bit 0) */ +#define OTP_DATA_RAW_CRIT1_R1_CRIT1_R1_Msk (0xffffffUL) /*!< CRIT1_R1 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT1_R2 ======================================================== */ +#define OTP_DATA_RAW_CRIT1_R2_CRIT1_R2_Pos (0UL) /*!< CRIT1_R2 (Bit 0) */ +#define OTP_DATA_RAW_CRIT1_R2_CRIT1_R2_Msk (0xffffffUL) /*!< CRIT1_R2 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT1_R3 ======================================================== */ +#define OTP_DATA_RAW_CRIT1_R3_CRIT1_R3_Pos (0UL) /*!< CRIT1_R3 (Bit 0) */ +#define OTP_DATA_RAW_CRIT1_R3_CRIT1_R3_Msk (0xffffffUL) /*!< CRIT1_R3 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT1_R4 ======================================================== */ +#define OTP_DATA_RAW_CRIT1_R4_CRIT1_R4_Pos (0UL) /*!< CRIT1_R4 (Bit 0) */ +#define OTP_DATA_RAW_CRIT1_R4_CRIT1_R4_Msk (0xffffffUL) /*!< CRIT1_R4 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT1_R5 ======================================================== */ +#define OTP_DATA_RAW_CRIT1_R5_CRIT1_R5_Pos (0UL) /*!< CRIT1_R5 (Bit 0) */ +#define OTP_DATA_RAW_CRIT1_R5_CRIT1_R5_Msk (0xffffffUL) /*!< CRIT1_R5 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT1_R6 ======================================================== */ +#define OTP_DATA_RAW_CRIT1_R6_CRIT1_R6_Pos (0UL) /*!< CRIT1_R6 (Bit 0) */ +#define OTP_DATA_RAW_CRIT1_R6_CRIT1_R6_Msk (0xffffffUL) /*!< CRIT1_R6 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= CRIT1_R7 ======================================================== */ +#define OTP_DATA_RAW_CRIT1_R7_CRIT1_R7_Pos (0UL) /*!< CRIT1_R7 (Bit 0) */ +#define OTP_DATA_RAW_CRIT1_R7_CRIT1_R7_Msk (0xffffffUL) /*!< CRIT1_R7 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== BOOT_FLAGS0 ====================================================== */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_Pos (21UL) /*!< DISABLE_SRAM_WINDOW_BOOT (Bit 21) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_Msk (0x200000UL) /*!< DISABLE_SRAM_WINDOW_BOOT (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_Pos (20UL) /*!< DISABLE_XIP_ACCESS_ON_SRAM_ENTRY (Bit 20) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_Msk (0x100000UL) /*!< DISABLE_XIP_ACCESS_ON_SRAM_ENTRY (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_Pos (19UL) /*!< DISABLE_BOOTSEL_UART_BOOT (Bit 19) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_Msk (0x80000UL) /*!< DISABLE_BOOTSEL_UART_BOOT (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_Pos (18UL) /*!< DISABLE_BOOTSEL_USB_PICOBOOT_IFC (Bit 18) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_Msk (0x40000UL) /*!< DISABLE_BOOTSEL_USB_PICOBOOT_IFC (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_Pos (17UL) /*!< DISABLE_BOOTSEL_USB_MSD_IFC (Bit 17) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_Msk (0x20000UL) /*!< DISABLE_BOOTSEL_USB_MSD_IFC (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_Pos (16UL) /*!< DISABLE_WATCHDOG_SCRATCH (Bit 16) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_Msk (0x10000UL) /*!< DISABLE_WATCHDOG_SCRATCH (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_Pos (15UL) /*!< DISABLE_POWER_SCRATCH (Bit 15) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_Msk (0x8000UL) /*!< DISABLE_POWER_SCRATCH (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_ENABLE_OTP_BOOT_Pos (14UL) /*!< ENABLE_OTP_BOOT (Bit 14) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_ENABLE_OTP_BOOT_Msk (0x4000UL) /*!< ENABLE_OTP_BOOT (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_OTP_BOOT_Pos (13UL) /*!< DISABLE_OTP_BOOT (Bit 13) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_OTP_BOOT_Msk (0x2000UL) /*!< DISABLE_OTP_BOOT (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_FLASH_BOOT_Pos (12UL) /*!< DISABLE_FLASH_BOOT (Bit 12) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_FLASH_BOOT_Msk (0x1000UL) /*!< DISABLE_FLASH_BOOT (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_ROLLBACK_REQUIRED_Pos (11UL) /*!< ROLLBACK_REQUIRED (Bit 11) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_ROLLBACK_REQUIRED_Msk (0x800UL) /*!< ROLLBACK_REQUIRED (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_HASHED_PARTITION_TABLE_Pos (10UL) /*!< HASHED_PARTITION_TABLE (Bit 10) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_HASHED_PARTITION_TABLE_Msk (0x400UL) /*!< HASHED_PARTITION_TABLE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_SECURE_PARTITION_TABLE_Pos (9UL) /*!< SECURE_PARTITION_TABLE (Bit 9) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_SECURE_PARTITION_TABLE_Msk (0x200UL) /*!< SECURE_PARTITION_TABLE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_Pos (8UL) /*!< DISABLE_AUTO_SWITCH_ARCH (Bit 8) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_Msk (0x100UL) /*!< DISABLE_AUTO_SWITCH_ARCH (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_SINGLE_FLASH_BINARY_Pos (7UL) /*!< SINGLE_FLASH_BINARY (Bit 7) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_SINGLE_FLASH_BINARY_Msk (0x80UL) /*!< SINGLE_FLASH_BINARY (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_Pos (6UL) /*!< OVERRIDE_FLASH_PARTITION_SLOT_SIZE (Bit 6) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_Msk (0x40UL) /*!< OVERRIDE_FLASH_PARTITION_SLOT_SIZE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_Pos (5UL) /*!< FLASH_DEVINFO_ENABLE (Bit 5) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_Msk (0x20UL) /*!< FLASH_DEVINFO_ENABLE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_Pos (4UL) /*!< FAST_SIGCHECK_ROSC_DIV (Bit 4) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_Msk (0x10UL) /*!< FAST_SIGCHECK_ROSC_DIV (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_Pos (3UL) /*!< FLASH_IO_VOLTAGE_1V8 (Bit 3) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_Msk (0x8UL) /*!< FLASH_IO_VOLTAGE_1V8 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_Pos (2UL) /*!< ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG (Bit 2) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_Msk (0x4UL) /*!< ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_Pos (1UL) /*!< ENABLE_BOOTSEL_LED (Bit 1) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_Msk (0x2UL) /*!< ENABLE_BOOTSEL_LED (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_Pos (0UL) /*!< DISABLE_BOOTSEL_EXEC2 (Bit 0) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_Msk (0x1UL) /*!< DISABLE_BOOTSEL_EXEC2 (Bitfield-Mask: 0x01) */ +/* ==================================================== BOOT_FLAGS0_R1 ===================================================== */ +#define OTP_DATA_RAW_BOOT_FLAGS0_R1_BOOT_FLAGS0_R1_Pos (0UL) /*!< BOOT_FLAGS0_R1 (Bit 0) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_R1_BOOT_FLAGS0_R1_Msk (0xffffffUL) /*!< BOOT_FLAGS0_R1 (Bitfield-Mask: 0xffffff) */ +/* ==================================================== BOOT_FLAGS0_R2 ===================================================== */ +#define OTP_DATA_RAW_BOOT_FLAGS0_R2_BOOT_FLAGS0_R2_Pos (0UL) /*!< BOOT_FLAGS0_R2 (Bit 0) */ +#define OTP_DATA_RAW_BOOT_FLAGS0_R2_BOOT_FLAGS0_R2_Msk (0xffffffUL) /*!< BOOT_FLAGS0_R2 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== BOOT_FLAGS1 ====================================================== */ +#define OTP_DATA_RAW_BOOT_FLAGS1_DOUBLE_TAP_Pos (19UL) /*!< DOUBLE_TAP (Bit 19) */ +#define OTP_DATA_RAW_BOOT_FLAGS1_DOUBLE_TAP_Msk (0x80000UL) /*!< DOUBLE_TAP (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOT_FLAGS1_DOUBLE_TAP_DELAY_Pos (16UL) /*!< DOUBLE_TAP_DELAY (Bit 16) */ +#define OTP_DATA_RAW_BOOT_FLAGS1_DOUBLE_TAP_DELAY_Msk (0x70000UL) /*!< DOUBLE_TAP_DELAY (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_BOOT_FLAGS1_KEY_INVALID_Pos (8UL) /*!< KEY_INVALID (Bit 8) */ +#define OTP_DATA_RAW_BOOT_FLAGS1_KEY_INVALID_Msk (0xf00UL) /*!< KEY_INVALID (Bitfield-Mask: 0x0f) */ +#define OTP_DATA_RAW_BOOT_FLAGS1_KEY_VALID_Pos (0UL) /*!< KEY_VALID (Bit 0) */ +#define OTP_DATA_RAW_BOOT_FLAGS1_KEY_VALID_Msk (0xfUL) /*!< KEY_VALID (Bitfield-Mask: 0x0f) */ +/* ==================================================== BOOT_FLAGS1_R1 ===================================================== */ +#define OTP_DATA_RAW_BOOT_FLAGS1_R1_BOOT_FLAGS1_R1_Pos (0UL) /*!< BOOT_FLAGS1_R1 (Bit 0) */ +#define OTP_DATA_RAW_BOOT_FLAGS1_R1_BOOT_FLAGS1_R1_Msk (0xffffffUL) /*!< BOOT_FLAGS1_R1 (Bitfield-Mask: 0xffffff) */ +/* ==================================================== BOOT_FLAGS1_R2 ===================================================== */ +#define OTP_DATA_RAW_BOOT_FLAGS1_R2_BOOT_FLAGS1_R2_Pos (0UL) /*!< BOOT_FLAGS1_R2 (Bit 0) */ +#define OTP_DATA_RAW_BOOT_FLAGS1_R2_BOOT_FLAGS1_R2_Msk (0xffffffUL) /*!< BOOT_FLAGS1_R2 (Bitfield-Mask: 0xffffff) */ +/* ================================================= DEFAULT_BOOT_VERSION0 ================================================= */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION0_DEFAULT_BOOT_VERSION0_Pos (0UL) /*!< DEFAULT_BOOT_VERSION0 (Bit 0) */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION0_DEFAULT_BOOT_VERSION0_Msk (0xffffffUL) /*!< DEFAULT_BOOT_VERSION0 (Bitfield-Mask: 0xffffff) */ +/* =============================================== DEFAULT_BOOT_VERSION0_R1 ================================================ */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION0_R1_DEFAULT_BOOT_VERSION0_R1_Pos (0UL) /*!< DEFAULT_BOOT_VERSION0_R1 (Bit 0) */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION0_R1_DEFAULT_BOOT_VERSION0_R1_Msk (0xffffffUL) /*!< DEFAULT_BOOT_VERSION0_R1 (Bitfield-Mask: 0xffffff) */ +/* =============================================== DEFAULT_BOOT_VERSION0_R2 ================================================ */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION0_R2_DEFAULT_BOOT_VERSION0_R2_Pos (0UL) /*!< DEFAULT_BOOT_VERSION0_R2 (Bit 0) */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION0_R2_DEFAULT_BOOT_VERSION0_R2_Msk (0xffffffUL) /*!< DEFAULT_BOOT_VERSION0_R2 (Bitfield-Mask: 0xffffff) */ +/* ================================================= DEFAULT_BOOT_VERSION1 ================================================= */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION1_DEFAULT_BOOT_VERSION1_Pos (0UL) /*!< DEFAULT_BOOT_VERSION1 (Bit 0) */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION1_DEFAULT_BOOT_VERSION1_Msk (0xffffffUL) /*!< DEFAULT_BOOT_VERSION1 (Bitfield-Mask: 0xffffff) */ +/* =============================================== DEFAULT_BOOT_VERSION1_R1 ================================================ */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION1_R1_DEFAULT_BOOT_VERSION1_R1_Pos (0UL) /*!< DEFAULT_BOOT_VERSION1_R1 (Bit 0) */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION1_R1_DEFAULT_BOOT_VERSION1_R1_Msk (0xffffffUL) /*!< DEFAULT_BOOT_VERSION1_R1 (Bitfield-Mask: 0xffffff) */ +/* =============================================== DEFAULT_BOOT_VERSION1_R2 ================================================ */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION1_R2_DEFAULT_BOOT_VERSION1_R2_Pos (0UL) /*!< DEFAULT_BOOT_VERSION1_R2 (Bit 0) */ +#define OTP_DATA_RAW_DEFAULT_BOOT_VERSION1_R2_DEFAULT_BOOT_VERSION1_R2_Msk (0xffffffUL) /*!< DEFAULT_BOOT_VERSION1_R2 (Bitfield-Mask: 0xffffff) */ +/* ===================================================== FLASH_DEVINFO ===================================================== */ +#define OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_Pos (12UL) /*!< CS1_SIZE (Bit 12) */ +#define OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_Msk (0xf000UL) /*!< CS1_SIZE (Bitfield-Mask: 0x0f) */ +#define OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_Pos (8UL) /*!< CS0_SIZE (Bit 8) */ +#define OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_Msk (0xf00UL) /*!< CS0_SIZE (Bitfield-Mask: 0x0f) */ +#define OTP_DATA_RAW_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_Pos (7UL) /*!< D8H_ERASE_SUPPORTED (Bit 7) */ +#define OTP_DATA_RAW_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_Msk (0x80UL) /*!< D8H_ERASE_SUPPORTED (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_FLASH_DEVINFO_CS1_GPIO_Pos (0UL) /*!< CS1_GPIO (Bit 0) */ +#define OTP_DATA_RAW_FLASH_DEVINFO_CS1_GPIO_Msk (0x3fUL) /*!< CS1_GPIO (Bitfield-Mask: 0x3f) */ +/* =============================================== FLASH_PARTITION_SLOT_SIZE =============================================== */ +#define OTP_DATA_RAW_FLASH_PARTITION_SLOT_SIZE_FLASH_PARTITION_SLOT_SIZE_Pos (0UL) /*!< FLASH_PARTITION_SLOT_SIZE (Bit 0) */ +#define OTP_DATA_RAW_FLASH_PARTITION_SLOT_SIZE_FLASH_PARTITION_SLOT_SIZE_Msk (0xffffUL) /*!< FLASH_PARTITION_SLOT_SIZE (Bitfield-Mask: 0xffff) */ +/* ==================================================== BOOTSEL_LED_CFG ==================================================== */ +#define OTP_DATA_RAW_BOOTSEL_LED_CFG_ACTIVELOW_Pos (8UL) /*!< ACTIVELOW (Bit 8) */ +#define OTP_DATA_RAW_BOOTSEL_LED_CFG_ACTIVELOW_Msk (0x100UL) /*!< ACTIVELOW (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOTSEL_LED_CFG_PIN_Pos (0UL) /*!< PIN (Bit 0) */ +#define OTP_DATA_RAW_BOOTSEL_LED_CFG_PIN_Msk (0x3fUL) /*!< PIN (Bitfield-Mask: 0x3f) */ +/* ==================================================== BOOTSEL_PLL_CFG ==================================================== */ +#define OTP_DATA_RAW_BOOTSEL_PLL_CFG_REFDIV_Pos (15UL) /*!< REFDIV (Bit 15) */ +#define OTP_DATA_RAW_BOOTSEL_PLL_CFG_REFDIV_Msk (0x8000UL) /*!< REFDIV (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_BOOTSEL_PLL_CFG_POSTDIV2_Pos (12UL) /*!< POSTDIV2 (Bit 12) */ +#define OTP_DATA_RAW_BOOTSEL_PLL_CFG_POSTDIV2_Msk (0x7000UL) /*!< POSTDIV2 (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_BOOTSEL_PLL_CFG_POSTDIV1_Pos (9UL) /*!< POSTDIV1 (Bit 9) */ +#define OTP_DATA_RAW_BOOTSEL_PLL_CFG_POSTDIV1_Msk (0xe00UL) /*!< POSTDIV1 (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_BOOTSEL_PLL_CFG_FBDIV_Pos (0UL) /*!< FBDIV (Bit 0) */ +#define OTP_DATA_RAW_BOOTSEL_PLL_CFG_FBDIV_Msk (0x1ffUL) /*!< FBDIV (Bitfield-Mask: 0x1ff) */ +/* =================================================== BOOTSEL_XOSC_CFG ==================================================== */ +#define OTP_DATA_RAW_BOOTSEL_XOSC_CFG_RANGE_Pos (14UL) /*!< RANGE (Bit 14) */ +#define OTP_DATA_RAW_BOOTSEL_XOSC_CFG_RANGE_Msk (0xc000UL) /*!< RANGE (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_BOOTSEL_XOSC_CFG_STARTUP_Pos (0UL) /*!< STARTUP (Bit 0) */ +#define OTP_DATA_RAW_BOOTSEL_XOSC_CFG_STARTUP_Msk (0x3fffUL) /*!< STARTUP (Bitfield-Mask: 0x3fff) */ +/* ==================================================== USB_BOOT_FLAGS ===================================================== */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_DP_DM_SWAP_Pos (23UL) /*!< DP_DM_SWAP (Bit 23) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_DP_DM_SWAP_Msk (0x800000UL) /*!< DP_DM_SWAP (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_Pos (22UL) /*!< WHITE_LABEL_ADDR_VALID (Bit 22) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_Msk (0x400000UL) /*!< WHITE_LABEL_ADDR_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_Pos (15UL) /*!< WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID (Bit 15) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_Msk (0x8000UL) /*!< WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_Pos (14UL) /*!< WL_INFO_UF2_TXT_MODEL_STRDEF_VALID (Bit 14) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_Msk (0x4000UL) /*!< WL_INFO_UF2_TXT_MODEL_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_Pos (13UL) /*!< WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID (Bit 13) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_Msk (0x2000UL) /*!< WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_Pos (12UL) /*!< WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID (Bit 12) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_Msk (0x1000UL) /*!< WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_Pos (11UL) /*!< WL_SCSI_INQUIRY_VERSION_STRDEF_VALID (Bit 11) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_Msk (0x800UL) /*!< WL_SCSI_INQUIRY_VERSION_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_Pos (10UL) /*!< WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID (Bit 10) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_Msk (0x400UL) /*!< WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_Pos (9UL) /*!< WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID (Bit 9) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_Msk (0x200UL) /*!< WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_Pos (8UL) /*!< WL_VOLUME_LABEL_STRDEF_VALID (Bit 8) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_Msk (0x100UL) /*!< WL_VOLUME_LABEL_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_Pos (7UL) /*!< WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID (Bit 7) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_Msk (0x80UL) /*!< WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_Pos (6UL) /*!< WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID (Bit 6) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_Msk (0x40UL) /*!< WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_Pos (5UL) /*!< WL_USB_DEVICE_PRODUCT_STRDEF_VALID (Bit 5) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_Msk (0x20UL) /*!< WL_USB_DEVICE_PRODUCT_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_Pos (4UL) /*!< WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID (Bit 4) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_Msk (0x10UL) /*!< WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_Pos (3UL) /*!< WL_USB_DEVICE_LANG_ID_VALUE_VALID (Bit 3) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_Msk (0x8UL) /*!< WL_USB_DEVICE_LANG_ID_VALUE_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_Pos (2UL) /*!< WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID (Bit 2) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_Msk (0x4UL) /*!< WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_Pos (1UL) /*!< WL_USB_DEVICE_PID_VALUE_VALID (Bit 1) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_Msk (0x2UL) /*!< WL_USB_DEVICE_PID_VALUE_VALID (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_Pos (0UL) /*!< WL_USB_DEVICE_VID_VALUE_VALID (Bit 0) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_Msk (0x1UL) /*!< WL_USB_DEVICE_VID_VALUE_VALID (Bitfield-Mask: 0x01) */ +/* =================================================== USB_BOOT_FLAGS_R1 =================================================== */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_R1_USB_BOOT_FLAGS_R1_Pos (0UL) /*!< USB_BOOT_FLAGS_R1 (Bit 0) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_R1_USB_BOOT_FLAGS_R1_Msk (0xffffffUL) /*!< USB_BOOT_FLAGS_R1 (Bitfield-Mask: 0xffffff) */ +/* =================================================== USB_BOOT_FLAGS_R2 =================================================== */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_R2_USB_BOOT_FLAGS_R2_Pos (0UL) /*!< USB_BOOT_FLAGS_R2 (Bit 0) */ +#define OTP_DATA_RAW_USB_BOOT_FLAGS_R2_USB_BOOT_FLAGS_R2_Msk (0xffffffUL) /*!< USB_BOOT_FLAGS_R2 (Bitfield-Mask: 0xffffff) */ +/* ================================================= USB_WHITE_LABEL_ADDR ================================================== */ +#define OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_Pos (0UL) /*!< USB_WHITE_LABEL_ADDR (Bit 0) */ +#define OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_Msk (0xffffUL) /*!< USB_WHITE_LABEL_ADDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== OTPBOOT_SRC ====================================================== */ +#define OTP_DATA_RAW_OTPBOOT_SRC_OTPBOOT_SRC_Pos (0UL) /*!< OTPBOOT_SRC (Bit 0) */ +#define OTP_DATA_RAW_OTPBOOT_SRC_OTPBOOT_SRC_Msk (0xffffUL) /*!< OTPBOOT_SRC (Bitfield-Mask: 0xffff) */ +/* ====================================================== OTPBOOT_LEN ====================================================== */ +#define OTP_DATA_RAW_OTPBOOT_LEN_OTPBOOT_LEN_Pos (0UL) /*!< OTPBOOT_LEN (Bit 0) */ +#define OTP_DATA_RAW_OTPBOOT_LEN_OTPBOOT_LEN_Msk (0xffffUL) /*!< OTPBOOT_LEN (Bitfield-Mask: 0xffff) */ +/* ===================================================== OTPBOOT_DST0 ====================================================== */ +#define OTP_DATA_RAW_OTPBOOT_DST0_OTPBOOT_DST0_Pos (0UL) /*!< OTPBOOT_DST0 (Bit 0) */ +#define OTP_DATA_RAW_OTPBOOT_DST0_OTPBOOT_DST0_Msk (0xffffUL) /*!< OTPBOOT_DST0 (Bitfield-Mask: 0xffff) */ +/* ===================================================== OTPBOOT_DST1 ====================================================== */ +#define OTP_DATA_RAW_OTPBOOT_DST1_OTPBOOT_DST1_Pos (0UL) /*!< OTPBOOT_DST1 (Bit 0) */ +#define OTP_DATA_RAW_OTPBOOT_DST1_OTPBOOT_DST1_Msk (0xffffUL) /*!< OTPBOOT_DST1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_0 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_0_BOOTKEY0_0_Pos (0UL) /*!< BOOTKEY0_0 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_0_BOOTKEY0_0_Msk (0xffffUL) /*!< BOOTKEY0_0 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_1 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_1_BOOTKEY0_1_Pos (0UL) /*!< BOOTKEY0_1 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_1_BOOTKEY0_1_Msk (0xffffUL) /*!< BOOTKEY0_1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_2 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_2_BOOTKEY0_2_Pos (0UL) /*!< BOOTKEY0_2 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_2_BOOTKEY0_2_Msk (0xffffUL) /*!< BOOTKEY0_2 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_3 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_3_BOOTKEY0_3_Pos (0UL) /*!< BOOTKEY0_3 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_3_BOOTKEY0_3_Msk (0xffffUL) /*!< BOOTKEY0_3 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_4 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_4_BOOTKEY0_4_Pos (0UL) /*!< BOOTKEY0_4 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_4_BOOTKEY0_4_Msk (0xffffUL) /*!< BOOTKEY0_4 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_5 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_5_BOOTKEY0_5_Pos (0UL) /*!< BOOTKEY0_5 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_5_BOOTKEY0_5_Msk (0xffffUL) /*!< BOOTKEY0_5 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_6 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_6_BOOTKEY0_6_Pos (0UL) /*!< BOOTKEY0_6 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_6_BOOTKEY0_6_Msk (0xffffUL) /*!< BOOTKEY0_6 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_7 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_7_BOOTKEY0_7_Pos (0UL) /*!< BOOTKEY0_7 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_7_BOOTKEY0_7_Msk (0xffffUL) /*!< BOOTKEY0_7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_8 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_8_BOOTKEY0_8_Pos (0UL) /*!< BOOTKEY0_8 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_8_BOOTKEY0_8_Msk (0xffffUL) /*!< BOOTKEY0_8 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_9 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY0_9_BOOTKEY0_9_Pos (0UL) /*!< BOOTKEY0_9 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_9_BOOTKEY0_9_Msk (0xffffUL) /*!< BOOTKEY0_9 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_10 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY0_10_BOOTKEY0_10_Pos (0UL) /*!< BOOTKEY0_10 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_10_BOOTKEY0_10_Msk (0xffffUL) /*!< BOOTKEY0_10 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_11 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY0_11_BOOTKEY0_11_Pos (0UL) /*!< BOOTKEY0_11 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_11_BOOTKEY0_11_Msk (0xffffUL) /*!< BOOTKEY0_11 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_12 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY0_12_BOOTKEY0_12_Pos (0UL) /*!< BOOTKEY0_12 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_12_BOOTKEY0_12_Msk (0xffffUL) /*!< BOOTKEY0_12 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_13 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY0_13_BOOTKEY0_13_Pos (0UL) /*!< BOOTKEY0_13 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_13_BOOTKEY0_13_Msk (0xffffUL) /*!< BOOTKEY0_13 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_14 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY0_14_BOOTKEY0_14_Pos (0UL) /*!< BOOTKEY0_14 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_14_BOOTKEY0_14_Msk (0xffffUL) /*!< BOOTKEY0_14 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY0_15 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY0_15_BOOTKEY0_15_Pos (0UL) /*!< BOOTKEY0_15 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY0_15_BOOTKEY0_15_Msk (0xffffUL) /*!< BOOTKEY0_15 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_0 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_0_BOOTKEY1_0_Pos (0UL) /*!< BOOTKEY1_0 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_0_BOOTKEY1_0_Msk (0xffffUL) /*!< BOOTKEY1_0 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_1 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_1_BOOTKEY1_1_Pos (0UL) /*!< BOOTKEY1_1 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_1_BOOTKEY1_1_Msk (0xffffUL) /*!< BOOTKEY1_1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_2 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_2_BOOTKEY1_2_Pos (0UL) /*!< BOOTKEY1_2 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_2_BOOTKEY1_2_Msk (0xffffUL) /*!< BOOTKEY1_2 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_3 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_3_BOOTKEY1_3_Pos (0UL) /*!< BOOTKEY1_3 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_3_BOOTKEY1_3_Msk (0xffffUL) /*!< BOOTKEY1_3 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_4 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_4_BOOTKEY1_4_Pos (0UL) /*!< BOOTKEY1_4 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_4_BOOTKEY1_4_Msk (0xffffUL) /*!< BOOTKEY1_4 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_5 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_5_BOOTKEY1_5_Pos (0UL) /*!< BOOTKEY1_5 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_5_BOOTKEY1_5_Msk (0xffffUL) /*!< BOOTKEY1_5 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_6 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_6_BOOTKEY1_6_Pos (0UL) /*!< BOOTKEY1_6 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_6_BOOTKEY1_6_Msk (0xffffUL) /*!< BOOTKEY1_6 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_7 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_7_BOOTKEY1_7_Pos (0UL) /*!< BOOTKEY1_7 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_7_BOOTKEY1_7_Msk (0xffffUL) /*!< BOOTKEY1_7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_8 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_8_BOOTKEY1_8_Pos (0UL) /*!< BOOTKEY1_8 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_8_BOOTKEY1_8_Msk (0xffffUL) /*!< BOOTKEY1_8 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_9 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY1_9_BOOTKEY1_9_Pos (0UL) /*!< BOOTKEY1_9 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_9_BOOTKEY1_9_Msk (0xffffUL) /*!< BOOTKEY1_9 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_10 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY1_10_BOOTKEY1_10_Pos (0UL) /*!< BOOTKEY1_10 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_10_BOOTKEY1_10_Msk (0xffffUL) /*!< BOOTKEY1_10 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_11 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY1_11_BOOTKEY1_11_Pos (0UL) /*!< BOOTKEY1_11 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_11_BOOTKEY1_11_Msk (0xffffUL) /*!< BOOTKEY1_11 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_12 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY1_12_BOOTKEY1_12_Pos (0UL) /*!< BOOTKEY1_12 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_12_BOOTKEY1_12_Msk (0xffffUL) /*!< BOOTKEY1_12 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_13 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY1_13_BOOTKEY1_13_Pos (0UL) /*!< BOOTKEY1_13 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_13_BOOTKEY1_13_Msk (0xffffUL) /*!< BOOTKEY1_13 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_14 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY1_14_BOOTKEY1_14_Pos (0UL) /*!< BOOTKEY1_14 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_14_BOOTKEY1_14_Msk (0xffffUL) /*!< BOOTKEY1_14 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY1_15 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY1_15_BOOTKEY1_15_Pos (0UL) /*!< BOOTKEY1_15 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY1_15_BOOTKEY1_15_Msk (0xffffUL) /*!< BOOTKEY1_15 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_0 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_0_BOOTKEY2_0_Pos (0UL) /*!< BOOTKEY2_0 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_0_BOOTKEY2_0_Msk (0xffffUL) /*!< BOOTKEY2_0 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_1 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_1_BOOTKEY2_1_Pos (0UL) /*!< BOOTKEY2_1 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_1_BOOTKEY2_1_Msk (0xffffUL) /*!< BOOTKEY2_1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_2 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_2_BOOTKEY2_2_Pos (0UL) /*!< BOOTKEY2_2 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_2_BOOTKEY2_2_Msk (0xffffUL) /*!< BOOTKEY2_2 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_3 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_3_BOOTKEY2_3_Pos (0UL) /*!< BOOTKEY2_3 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_3_BOOTKEY2_3_Msk (0xffffUL) /*!< BOOTKEY2_3 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_4 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_4_BOOTKEY2_4_Pos (0UL) /*!< BOOTKEY2_4 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_4_BOOTKEY2_4_Msk (0xffffUL) /*!< BOOTKEY2_4 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_5 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_5_BOOTKEY2_5_Pos (0UL) /*!< BOOTKEY2_5 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_5_BOOTKEY2_5_Msk (0xffffUL) /*!< BOOTKEY2_5 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_6 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_6_BOOTKEY2_6_Pos (0UL) /*!< BOOTKEY2_6 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_6_BOOTKEY2_6_Msk (0xffffUL) /*!< BOOTKEY2_6 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_7 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_7_BOOTKEY2_7_Pos (0UL) /*!< BOOTKEY2_7 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_7_BOOTKEY2_7_Msk (0xffffUL) /*!< BOOTKEY2_7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_8 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_8_BOOTKEY2_8_Pos (0UL) /*!< BOOTKEY2_8 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_8_BOOTKEY2_8_Msk (0xffffUL) /*!< BOOTKEY2_8 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_9 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY2_9_BOOTKEY2_9_Pos (0UL) /*!< BOOTKEY2_9 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_9_BOOTKEY2_9_Msk (0xffffUL) /*!< BOOTKEY2_9 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_10 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY2_10_BOOTKEY2_10_Pos (0UL) /*!< BOOTKEY2_10 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_10_BOOTKEY2_10_Msk (0xffffUL) /*!< BOOTKEY2_10 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_11 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY2_11_BOOTKEY2_11_Pos (0UL) /*!< BOOTKEY2_11 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_11_BOOTKEY2_11_Msk (0xffffUL) /*!< BOOTKEY2_11 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_12 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY2_12_BOOTKEY2_12_Pos (0UL) /*!< BOOTKEY2_12 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_12_BOOTKEY2_12_Msk (0xffffUL) /*!< BOOTKEY2_12 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_13 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY2_13_BOOTKEY2_13_Pos (0UL) /*!< BOOTKEY2_13 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_13_BOOTKEY2_13_Msk (0xffffUL) /*!< BOOTKEY2_13 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_14 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY2_14_BOOTKEY2_14_Pos (0UL) /*!< BOOTKEY2_14 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_14_BOOTKEY2_14_Msk (0xffffUL) /*!< BOOTKEY2_14 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY2_15 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY2_15_BOOTKEY2_15_Pos (0UL) /*!< BOOTKEY2_15 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY2_15_BOOTKEY2_15_Msk (0xffffUL) /*!< BOOTKEY2_15 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_0 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_0_BOOTKEY3_0_Pos (0UL) /*!< BOOTKEY3_0 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_0_BOOTKEY3_0_Msk (0xffffUL) /*!< BOOTKEY3_0 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_1 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_1_BOOTKEY3_1_Pos (0UL) /*!< BOOTKEY3_1 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_1_BOOTKEY3_1_Msk (0xffffUL) /*!< BOOTKEY3_1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_2 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_2_BOOTKEY3_2_Pos (0UL) /*!< BOOTKEY3_2 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_2_BOOTKEY3_2_Msk (0xffffUL) /*!< BOOTKEY3_2 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_3 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_3_BOOTKEY3_3_Pos (0UL) /*!< BOOTKEY3_3 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_3_BOOTKEY3_3_Msk (0xffffUL) /*!< BOOTKEY3_3 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_4 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_4_BOOTKEY3_4_Pos (0UL) /*!< BOOTKEY3_4 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_4_BOOTKEY3_4_Msk (0xffffUL) /*!< BOOTKEY3_4 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_5 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_5_BOOTKEY3_5_Pos (0UL) /*!< BOOTKEY3_5 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_5_BOOTKEY3_5_Msk (0xffffUL) /*!< BOOTKEY3_5 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_6 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_6_BOOTKEY3_6_Pos (0UL) /*!< BOOTKEY3_6 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_6_BOOTKEY3_6_Msk (0xffffUL) /*!< BOOTKEY3_6 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_7 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_7_BOOTKEY3_7_Pos (0UL) /*!< BOOTKEY3_7 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_7_BOOTKEY3_7_Msk (0xffffUL) /*!< BOOTKEY3_7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_8 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_8_BOOTKEY3_8_Pos (0UL) /*!< BOOTKEY3_8 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_8_BOOTKEY3_8_Msk (0xffffUL) /*!< BOOTKEY3_8 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_9 ======================================================= */ +#define OTP_DATA_RAW_BOOTKEY3_9_BOOTKEY3_9_Pos (0UL) /*!< BOOTKEY3_9 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_9_BOOTKEY3_9_Msk (0xffffUL) /*!< BOOTKEY3_9 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_10 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY3_10_BOOTKEY3_10_Pos (0UL) /*!< BOOTKEY3_10 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_10_BOOTKEY3_10_Msk (0xffffUL) /*!< BOOTKEY3_10 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_11 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY3_11_BOOTKEY3_11_Pos (0UL) /*!< BOOTKEY3_11 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_11_BOOTKEY3_11_Msk (0xffffUL) /*!< BOOTKEY3_11 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_12 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY3_12_BOOTKEY3_12_Pos (0UL) /*!< BOOTKEY3_12 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_12_BOOTKEY3_12_Msk (0xffffUL) /*!< BOOTKEY3_12 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_13 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY3_13_BOOTKEY3_13_Pos (0UL) /*!< BOOTKEY3_13 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_13_BOOTKEY3_13_Msk (0xffffUL) /*!< BOOTKEY3_13 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_14 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY3_14_BOOTKEY3_14_Pos (0UL) /*!< BOOTKEY3_14 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_14_BOOTKEY3_14_Msk (0xffffUL) /*!< BOOTKEY3_14 (Bitfield-Mask: 0xffff) */ +/* ====================================================== BOOTKEY3_15 ====================================================== */ +#define OTP_DATA_RAW_BOOTKEY3_15_BOOTKEY3_15_Pos (0UL) /*!< BOOTKEY3_15 (Bit 0) */ +#define OTP_DATA_RAW_BOOTKEY3_15_BOOTKEY3_15_Msk (0xffffUL) /*!< BOOTKEY3_15 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_0 ========================================================= */ +#define OTP_DATA_RAW_KEY1_0_KEY1_0_Pos (0UL) /*!< KEY1_0 (Bit 0) */ +#define OTP_DATA_RAW_KEY1_0_KEY1_0_Msk (0xffffUL) /*!< KEY1_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_1 ========================================================= */ +#define OTP_DATA_RAW_KEY1_1_KEY1_1_Pos (0UL) /*!< KEY1_1 (Bit 0) */ +#define OTP_DATA_RAW_KEY1_1_KEY1_1_Msk (0xffffUL) /*!< KEY1_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_2 ========================================================= */ +#define OTP_DATA_RAW_KEY1_2_KEY1_2_Pos (0UL) /*!< KEY1_2 (Bit 0) */ +#define OTP_DATA_RAW_KEY1_2_KEY1_2_Msk (0xffffUL) /*!< KEY1_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_3 ========================================================= */ +#define OTP_DATA_RAW_KEY1_3_KEY1_3_Pos (0UL) /*!< KEY1_3 (Bit 0) */ +#define OTP_DATA_RAW_KEY1_3_KEY1_3_Msk (0xffffUL) /*!< KEY1_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_4 ========================================================= */ +#define OTP_DATA_RAW_KEY1_4_KEY1_4_Pos (0UL) /*!< KEY1_4 (Bit 0) */ +#define OTP_DATA_RAW_KEY1_4_KEY1_4_Msk (0xffffUL) /*!< KEY1_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_5 ========================================================= */ +#define OTP_DATA_RAW_KEY1_5_KEY1_5_Pos (0UL) /*!< KEY1_5 (Bit 0) */ +#define OTP_DATA_RAW_KEY1_5_KEY1_5_Msk (0xffffUL) /*!< KEY1_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_6 ========================================================= */ +#define OTP_DATA_RAW_KEY1_6_KEY1_6_Pos (0UL) /*!< KEY1_6 (Bit 0) */ +#define OTP_DATA_RAW_KEY1_6_KEY1_6_Msk (0xffffUL) /*!< KEY1_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY1_7 ========================================================= */ +#define OTP_DATA_RAW_KEY1_7_KEY1_7_Pos (0UL) /*!< KEY1_7 (Bit 0) */ +#define OTP_DATA_RAW_KEY1_7_KEY1_7_Msk (0xffffUL) /*!< KEY1_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_0 ========================================================= */ +#define OTP_DATA_RAW_KEY2_0_KEY2_0_Pos (0UL) /*!< KEY2_0 (Bit 0) */ +#define OTP_DATA_RAW_KEY2_0_KEY2_0_Msk (0xffffUL) /*!< KEY2_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_1 ========================================================= */ +#define OTP_DATA_RAW_KEY2_1_KEY2_1_Pos (0UL) /*!< KEY2_1 (Bit 0) */ +#define OTP_DATA_RAW_KEY2_1_KEY2_1_Msk (0xffffUL) /*!< KEY2_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_2 ========================================================= */ +#define OTP_DATA_RAW_KEY2_2_KEY2_2_Pos (0UL) /*!< KEY2_2 (Bit 0) */ +#define OTP_DATA_RAW_KEY2_2_KEY2_2_Msk (0xffffUL) /*!< KEY2_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_3 ========================================================= */ +#define OTP_DATA_RAW_KEY2_3_KEY2_3_Pos (0UL) /*!< KEY2_3 (Bit 0) */ +#define OTP_DATA_RAW_KEY2_3_KEY2_3_Msk (0xffffUL) /*!< KEY2_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_4 ========================================================= */ +#define OTP_DATA_RAW_KEY2_4_KEY2_4_Pos (0UL) /*!< KEY2_4 (Bit 0) */ +#define OTP_DATA_RAW_KEY2_4_KEY2_4_Msk (0xffffUL) /*!< KEY2_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_5 ========================================================= */ +#define OTP_DATA_RAW_KEY2_5_KEY2_5_Pos (0UL) /*!< KEY2_5 (Bit 0) */ +#define OTP_DATA_RAW_KEY2_5_KEY2_5_Msk (0xffffUL) /*!< KEY2_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_6 ========================================================= */ +#define OTP_DATA_RAW_KEY2_6_KEY2_6_Pos (0UL) /*!< KEY2_6 (Bit 0) */ +#define OTP_DATA_RAW_KEY2_6_KEY2_6_Msk (0xffffUL) /*!< KEY2_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY2_7 ========================================================= */ +#define OTP_DATA_RAW_KEY2_7_KEY2_7_Pos (0UL) /*!< KEY2_7 (Bit 0) */ +#define OTP_DATA_RAW_KEY2_7_KEY2_7_Msk (0xffffUL) /*!< KEY2_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_0 ========================================================= */ +#define OTP_DATA_RAW_KEY3_0_KEY3_0_Pos (0UL) /*!< KEY3_0 (Bit 0) */ +#define OTP_DATA_RAW_KEY3_0_KEY3_0_Msk (0xffffUL) /*!< KEY3_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_1 ========================================================= */ +#define OTP_DATA_RAW_KEY3_1_KEY3_1_Pos (0UL) /*!< KEY3_1 (Bit 0) */ +#define OTP_DATA_RAW_KEY3_1_KEY3_1_Msk (0xffffUL) /*!< KEY3_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_2 ========================================================= */ +#define OTP_DATA_RAW_KEY3_2_KEY3_2_Pos (0UL) /*!< KEY3_2 (Bit 0) */ +#define OTP_DATA_RAW_KEY3_2_KEY3_2_Msk (0xffffUL) /*!< KEY3_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_3 ========================================================= */ +#define OTP_DATA_RAW_KEY3_3_KEY3_3_Pos (0UL) /*!< KEY3_3 (Bit 0) */ +#define OTP_DATA_RAW_KEY3_3_KEY3_3_Msk (0xffffUL) /*!< KEY3_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_4 ========================================================= */ +#define OTP_DATA_RAW_KEY3_4_KEY3_4_Pos (0UL) /*!< KEY3_4 (Bit 0) */ +#define OTP_DATA_RAW_KEY3_4_KEY3_4_Msk (0xffffUL) /*!< KEY3_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_5 ========================================================= */ +#define OTP_DATA_RAW_KEY3_5_KEY3_5_Pos (0UL) /*!< KEY3_5 (Bit 0) */ +#define OTP_DATA_RAW_KEY3_5_KEY3_5_Msk (0xffffUL) /*!< KEY3_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_6 ========================================================= */ +#define OTP_DATA_RAW_KEY3_6_KEY3_6_Pos (0UL) /*!< KEY3_6 (Bit 0) */ +#define OTP_DATA_RAW_KEY3_6_KEY3_6_Msk (0xffffUL) /*!< KEY3_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY3_7 ========================================================= */ +#define OTP_DATA_RAW_KEY3_7_KEY3_7_Pos (0UL) /*!< KEY3_7 (Bit 0) */ +#define OTP_DATA_RAW_KEY3_7_KEY3_7_Msk (0xffffUL) /*!< KEY3_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_0 ========================================================= */ +#define OTP_DATA_RAW_KEY4_0_KEY4_0_Pos (0UL) /*!< KEY4_0 (Bit 0) */ +#define OTP_DATA_RAW_KEY4_0_KEY4_0_Msk (0xffffUL) /*!< KEY4_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_1 ========================================================= */ +#define OTP_DATA_RAW_KEY4_1_KEY4_1_Pos (0UL) /*!< KEY4_1 (Bit 0) */ +#define OTP_DATA_RAW_KEY4_1_KEY4_1_Msk (0xffffUL) /*!< KEY4_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_2 ========================================================= */ +#define OTP_DATA_RAW_KEY4_2_KEY4_2_Pos (0UL) /*!< KEY4_2 (Bit 0) */ +#define OTP_DATA_RAW_KEY4_2_KEY4_2_Msk (0xffffUL) /*!< KEY4_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_3 ========================================================= */ +#define OTP_DATA_RAW_KEY4_3_KEY4_3_Pos (0UL) /*!< KEY4_3 (Bit 0) */ +#define OTP_DATA_RAW_KEY4_3_KEY4_3_Msk (0xffffUL) /*!< KEY4_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_4 ========================================================= */ +#define OTP_DATA_RAW_KEY4_4_KEY4_4_Pos (0UL) /*!< KEY4_4 (Bit 0) */ +#define OTP_DATA_RAW_KEY4_4_KEY4_4_Msk (0xffffUL) /*!< KEY4_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_5 ========================================================= */ +#define OTP_DATA_RAW_KEY4_5_KEY4_5_Pos (0UL) /*!< KEY4_5 (Bit 0) */ +#define OTP_DATA_RAW_KEY4_5_KEY4_5_Msk (0xffffUL) /*!< KEY4_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_6 ========================================================= */ +#define OTP_DATA_RAW_KEY4_6_KEY4_6_Pos (0UL) /*!< KEY4_6 (Bit 0) */ +#define OTP_DATA_RAW_KEY4_6_KEY4_6_Msk (0xffffUL) /*!< KEY4_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY4_7 ========================================================= */ +#define OTP_DATA_RAW_KEY4_7_KEY4_7_Pos (0UL) /*!< KEY4_7 (Bit 0) */ +#define OTP_DATA_RAW_KEY4_7_KEY4_7_Msk (0xffffUL) /*!< KEY4_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_0 ========================================================= */ +#define OTP_DATA_RAW_KEY5_0_KEY5_0_Pos (0UL) /*!< KEY5_0 (Bit 0) */ +#define OTP_DATA_RAW_KEY5_0_KEY5_0_Msk (0xffffUL) /*!< KEY5_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_1 ========================================================= */ +#define OTP_DATA_RAW_KEY5_1_KEY5_1_Pos (0UL) /*!< KEY5_1 (Bit 0) */ +#define OTP_DATA_RAW_KEY5_1_KEY5_1_Msk (0xffffUL) /*!< KEY5_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_2 ========================================================= */ +#define OTP_DATA_RAW_KEY5_2_KEY5_2_Pos (0UL) /*!< KEY5_2 (Bit 0) */ +#define OTP_DATA_RAW_KEY5_2_KEY5_2_Msk (0xffffUL) /*!< KEY5_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_3 ========================================================= */ +#define OTP_DATA_RAW_KEY5_3_KEY5_3_Pos (0UL) /*!< KEY5_3 (Bit 0) */ +#define OTP_DATA_RAW_KEY5_3_KEY5_3_Msk (0xffffUL) /*!< KEY5_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_4 ========================================================= */ +#define OTP_DATA_RAW_KEY5_4_KEY5_4_Pos (0UL) /*!< KEY5_4 (Bit 0) */ +#define OTP_DATA_RAW_KEY5_4_KEY5_4_Msk (0xffffUL) /*!< KEY5_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_5 ========================================================= */ +#define OTP_DATA_RAW_KEY5_5_KEY5_5_Pos (0UL) /*!< KEY5_5 (Bit 0) */ +#define OTP_DATA_RAW_KEY5_5_KEY5_5_Msk (0xffffUL) /*!< KEY5_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_6 ========================================================= */ +#define OTP_DATA_RAW_KEY5_6_KEY5_6_Pos (0UL) /*!< KEY5_6 (Bit 0) */ +#define OTP_DATA_RAW_KEY5_6_KEY5_6_Msk (0xffffUL) /*!< KEY5_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY5_7 ========================================================= */ +#define OTP_DATA_RAW_KEY5_7_KEY5_7_Pos (0UL) /*!< KEY5_7 (Bit 0) */ +#define OTP_DATA_RAW_KEY5_7_KEY5_7_Msk (0xffffUL) /*!< KEY5_7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_0 ========================================================= */ +#define OTP_DATA_RAW_KEY6_0_KEY6_0_Pos (0UL) /*!< KEY6_0 (Bit 0) */ +#define OTP_DATA_RAW_KEY6_0_KEY6_0_Msk (0xffffUL) /*!< KEY6_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_1 ========================================================= */ +#define OTP_DATA_RAW_KEY6_1_KEY6_1_Pos (0UL) /*!< KEY6_1 (Bit 0) */ +#define OTP_DATA_RAW_KEY6_1_KEY6_1_Msk (0xffffUL) /*!< KEY6_1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_2 ========================================================= */ +#define OTP_DATA_RAW_KEY6_2_KEY6_2_Pos (0UL) /*!< KEY6_2 (Bit 0) */ +#define OTP_DATA_RAW_KEY6_2_KEY6_2_Msk (0xffffUL) /*!< KEY6_2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_3 ========================================================= */ +#define OTP_DATA_RAW_KEY6_3_KEY6_3_Pos (0UL) /*!< KEY6_3 (Bit 0) */ +#define OTP_DATA_RAW_KEY6_3_KEY6_3_Msk (0xffffUL) /*!< KEY6_3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_4 ========================================================= */ +#define OTP_DATA_RAW_KEY6_4_KEY6_4_Pos (0UL) /*!< KEY6_4 (Bit 0) */ +#define OTP_DATA_RAW_KEY6_4_KEY6_4_Msk (0xffffUL) /*!< KEY6_4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_5 ========================================================= */ +#define OTP_DATA_RAW_KEY6_5_KEY6_5_Pos (0UL) /*!< KEY6_5 (Bit 0) */ +#define OTP_DATA_RAW_KEY6_5_KEY6_5_Msk (0xffffUL) /*!< KEY6_5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_6 ========================================================= */ +#define OTP_DATA_RAW_KEY6_6_KEY6_6_Pos (0UL) /*!< KEY6_6 (Bit 0) */ +#define OTP_DATA_RAW_KEY6_6_KEY6_6_Msk (0xffffUL) /*!< KEY6_6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== KEY6_7 ========================================================= */ +#define OTP_DATA_RAW_KEY6_7_KEY6_7_Pos (0UL) /*!< KEY6_7 (Bit 0) */ +#define OTP_DATA_RAW_KEY6_7_KEY6_7_Msk (0xffffUL) /*!< KEY6_7 (Bitfield-Mask: 0xffff) */ +/* ====================================================== KEY1_VALID ======================================================= */ +#define OTP_DATA_RAW_KEY1_VALID_VALID_R2_Pos (16UL) /*!< VALID_R2 (Bit 16) */ +#define OTP_DATA_RAW_KEY1_VALID_VALID_R2_Msk (0x10000UL) /*!< VALID_R2 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY1_VALID_VALID_R1_Pos (8UL) /*!< VALID_R1 (Bit 8) */ +#define OTP_DATA_RAW_KEY1_VALID_VALID_R1_Msk (0x100UL) /*!< VALID_R1 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY1_VALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */ +#define OTP_DATA_RAW_KEY1_VALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ +/* ====================================================== KEY2_VALID ======================================================= */ +#define OTP_DATA_RAW_KEY2_VALID_VALID_R2_Pos (16UL) /*!< VALID_R2 (Bit 16) */ +#define OTP_DATA_RAW_KEY2_VALID_VALID_R2_Msk (0x10000UL) /*!< VALID_R2 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY2_VALID_VALID_R1_Pos (8UL) /*!< VALID_R1 (Bit 8) */ +#define OTP_DATA_RAW_KEY2_VALID_VALID_R1_Msk (0x100UL) /*!< VALID_R1 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY2_VALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */ +#define OTP_DATA_RAW_KEY2_VALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ +/* ====================================================== KEY3_VALID ======================================================= */ +#define OTP_DATA_RAW_KEY3_VALID_VALID_R2_Pos (16UL) /*!< VALID_R2 (Bit 16) */ +#define OTP_DATA_RAW_KEY3_VALID_VALID_R2_Msk (0x10000UL) /*!< VALID_R2 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY3_VALID_VALID_R1_Pos (8UL) /*!< VALID_R1 (Bit 8) */ +#define OTP_DATA_RAW_KEY3_VALID_VALID_R1_Msk (0x100UL) /*!< VALID_R1 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY3_VALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */ +#define OTP_DATA_RAW_KEY3_VALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ +/* ====================================================== KEY4_VALID ======================================================= */ +#define OTP_DATA_RAW_KEY4_VALID_VALID_R2_Pos (16UL) /*!< VALID_R2 (Bit 16) */ +#define OTP_DATA_RAW_KEY4_VALID_VALID_R2_Msk (0x10000UL) /*!< VALID_R2 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY4_VALID_VALID_R1_Pos (8UL) /*!< VALID_R1 (Bit 8) */ +#define OTP_DATA_RAW_KEY4_VALID_VALID_R1_Msk (0x100UL) /*!< VALID_R1 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY4_VALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */ +#define OTP_DATA_RAW_KEY4_VALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ +/* ====================================================== KEY5_VALID ======================================================= */ +#define OTP_DATA_RAW_KEY5_VALID_VALID_R2_Pos (16UL) /*!< VALID_R2 (Bit 16) */ +#define OTP_DATA_RAW_KEY5_VALID_VALID_R2_Msk (0x10000UL) /*!< VALID_R2 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY5_VALID_VALID_R1_Pos (8UL) /*!< VALID_R1 (Bit 8) */ +#define OTP_DATA_RAW_KEY5_VALID_VALID_R1_Msk (0x100UL) /*!< VALID_R1 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY5_VALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */ +#define OTP_DATA_RAW_KEY5_VALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ +/* ====================================================== KEY6_VALID ======================================================= */ +#define OTP_DATA_RAW_KEY6_VALID_VALID_R2_Pos (16UL) /*!< VALID_R2 (Bit 16) */ +#define OTP_DATA_RAW_KEY6_VALID_VALID_R2_Msk (0x10000UL) /*!< VALID_R2 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY6_VALID_VALID_R1_Pos (8UL) /*!< VALID_R1 (Bit 8) */ +#define OTP_DATA_RAW_KEY6_VALID_VALID_R1_Msk (0x100UL) /*!< VALID_R1 (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_KEY6_VALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */ +#define OTP_DATA_RAW_KEY6_VALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ +/* ====================================================== PAGE0_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE0_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE0_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE0_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE0_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE0_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE0_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE0_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE0_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE0_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE0_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE0_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE0_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE0_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE0_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE0_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE0_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE0_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE0_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE0_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE0_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE0_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ====================================================== PAGE1_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE1_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE1_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE1_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE1_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE1_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE1_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE1_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE1_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE1_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE1_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE1_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE1_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE1_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE1_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE1_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE1_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE1_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE1_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE1_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE1_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE1_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ====================================================== PAGE2_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE2_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE2_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE2_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE2_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE2_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE2_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE2_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE2_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE2_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE2_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE2_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE2_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE2_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE2_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE2_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE2_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE2_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE2_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE2_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE2_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE2_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ====================================================== PAGE3_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE3_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE3_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE3_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE3_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE3_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE3_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE3_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE3_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE3_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE3_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE3_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE3_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE3_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE3_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE3_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE3_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE3_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE3_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE3_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE3_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE3_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ====================================================== PAGE4_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE4_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE4_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE4_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE4_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE4_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE4_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE4_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE4_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE4_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE4_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE4_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE4_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE4_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE4_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE4_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE4_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE4_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE4_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE4_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE4_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE4_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ====================================================== PAGE5_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE5_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE5_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE5_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE5_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE5_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE5_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE5_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE5_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE5_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE5_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE5_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE5_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE5_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE5_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE5_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE5_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE5_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE5_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE5_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE5_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE5_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ====================================================== PAGE6_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE6_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE6_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE6_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE6_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE6_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE6_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE6_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE6_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE6_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE6_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE6_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE6_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE6_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE6_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE6_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE6_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE6_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE6_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE6_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE6_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE6_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ====================================================== PAGE7_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE7_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE7_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE7_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE7_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE7_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE7_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE7_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE7_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE7_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE7_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE7_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE7_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE7_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE7_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE7_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE7_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE7_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE7_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE7_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE7_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE7_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ====================================================== PAGE8_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE8_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE8_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE8_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE8_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE8_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE8_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE8_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE8_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE8_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE8_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE8_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE8_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE8_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE8_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE8_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE8_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE8_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE8_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE8_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE8_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE8_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ====================================================== PAGE9_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE9_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE9_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE9_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE9_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE9_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE9_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE9_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE9_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE9_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE9_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ====================================================== PAGE9_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE9_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE9_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE9_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE9_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE9_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE9_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE9_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE9_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE9_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE9_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE10_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE10_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE10_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE10_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE10_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE10_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE10_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE10_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE10_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE10_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE10_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE10_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE10_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE10_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE10_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE10_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE10_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE10_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE10_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE10_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE10_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE10_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE11_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE11_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE11_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE11_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE11_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE11_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE11_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE11_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE11_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE11_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE11_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE11_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE11_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE11_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE11_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE11_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE11_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE11_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE11_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE11_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE11_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE11_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE12_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE12_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE12_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE12_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE12_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE12_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE12_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE12_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE12_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE12_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE12_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE12_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE12_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE12_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE12_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE12_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE12_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE12_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE12_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE12_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE12_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE12_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE13_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE13_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE13_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE13_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE13_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE13_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE13_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE13_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE13_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE13_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE13_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE13_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE13_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE13_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE13_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE13_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE13_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE13_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE13_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE13_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE13_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE13_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE14_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE14_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE14_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE14_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE14_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE14_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE14_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE14_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE14_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE14_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE14_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE14_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE14_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE14_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE14_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE14_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE14_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE14_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE14_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE14_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE14_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE14_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE15_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE15_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE15_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE15_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE15_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE15_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE15_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE15_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE15_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE15_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE15_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE15_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE15_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE15_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE15_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE15_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE15_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE15_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE15_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE15_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE15_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE15_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE16_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE16_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE16_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE16_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE16_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE16_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE16_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE16_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE16_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE16_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE16_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE16_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE16_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE16_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE16_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE16_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE16_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE16_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE16_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE16_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE16_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE16_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE17_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE17_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE17_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE17_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE17_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE17_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE17_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE17_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE17_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE17_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE17_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE17_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE17_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE17_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE17_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE17_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE17_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE17_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE17_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE17_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE17_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE17_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE18_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE18_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE18_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE18_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE18_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE18_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE18_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE18_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE18_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE18_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE18_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE18_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE18_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE18_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE18_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE18_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE18_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE18_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE18_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE18_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE18_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE18_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE19_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE19_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE19_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE19_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE19_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE19_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE19_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE19_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE19_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE19_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE19_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE19_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE19_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE19_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE19_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE19_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE19_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE19_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE19_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE19_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE19_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE19_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE20_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE20_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE20_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE20_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE20_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE20_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE20_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE20_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE20_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE20_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE20_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE20_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE20_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE20_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE20_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE20_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE20_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE20_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE20_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE20_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE20_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE20_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE21_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE21_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE21_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE21_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE21_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE21_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE21_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE21_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE21_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE21_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE21_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE21_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE21_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE21_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE21_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE21_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE21_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE21_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE21_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE21_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE21_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE21_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE22_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE22_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE22_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE22_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE22_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE22_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE22_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE22_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE22_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE22_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE22_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE22_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE22_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE22_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE22_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE22_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE22_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE22_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE22_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE22_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE22_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE22_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE23_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE23_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE23_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE23_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE23_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE23_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE23_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE23_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE23_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE23_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE23_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE23_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE23_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE23_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE23_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE23_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE23_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE23_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE23_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE23_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE23_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE23_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE24_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE24_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE24_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE24_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE24_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE24_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE24_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE24_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE24_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE24_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE24_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE24_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE24_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE24_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE24_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE24_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE24_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE24_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE24_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE24_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE24_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE24_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE25_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE25_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE25_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE25_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE25_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE25_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE25_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE25_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE25_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE25_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE25_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE25_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE25_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE25_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE25_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE25_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE25_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE25_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE25_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE25_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE25_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE25_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE26_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE26_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE26_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE26_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE26_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE26_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE26_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE26_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE26_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE26_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE26_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE26_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE26_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE26_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE26_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE26_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE26_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE26_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE26_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE26_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE26_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE26_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE27_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE27_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE27_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE27_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE27_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE27_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE27_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE27_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE27_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE27_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE27_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE27_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE27_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE27_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE27_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE27_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE27_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE27_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE27_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE27_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE27_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE27_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE28_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE28_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE28_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE28_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE28_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE28_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE28_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE28_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE28_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE28_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE28_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE28_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE28_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE28_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE28_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE28_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE28_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE28_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE28_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE28_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE28_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE28_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE29_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE29_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE29_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE29_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE29_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE29_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE29_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE29_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE29_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE29_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE29_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE29_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE29_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE29_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE29_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE29_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE29_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE29_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE29_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE29_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE29_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE29_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE30_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE30_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE30_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE30_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE30_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE30_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE30_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE30_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE30_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE30_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE30_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE30_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE30_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE30_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE30_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE30_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE30_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE30_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE30_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE30_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE30_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE30_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE31_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE31_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE31_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE31_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE31_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE31_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE31_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE31_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE31_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE31_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE31_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE31_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE31_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE31_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE31_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE31_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE31_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE31_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE31_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE31_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE31_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE31_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE32_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE32_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE32_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE32_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE32_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE32_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE32_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE32_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE32_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE32_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE32_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE32_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE32_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE32_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE32_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE32_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE32_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE32_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE32_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE32_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE32_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE32_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE33_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE33_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE33_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE33_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE33_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE33_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE33_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE33_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE33_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE33_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE33_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE33_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE33_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE33_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE33_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE33_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE33_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE33_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE33_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE33_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE33_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE33_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE34_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE34_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE34_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE34_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE34_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE34_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE34_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE34_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE34_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE34_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE34_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE34_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE34_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE34_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE34_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE34_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE34_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE34_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE34_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE34_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE34_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE34_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE35_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE35_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE35_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE35_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE35_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE35_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE35_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE35_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE35_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE35_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE35_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE35_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE35_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE35_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE35_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE35_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE35_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE35_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE35_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE35_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE35_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE35_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE36_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE36_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE36_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE36_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE36_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE36_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE36_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE36_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE36_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE36_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE36_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE36_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE36_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE36_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE36_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE36_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE36_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE36_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE36_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE36_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE36_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE36_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE37_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE37_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE37_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE37_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE37_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE37_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE37_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE37_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE37_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE37_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE37_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE37_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE37_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE37_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE37_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE37_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE37_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE37_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE37_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE37_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE37_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE37_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE38_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE38_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE38_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE38_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE38_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE38_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE38_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE38_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE38_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE38_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE38_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE38_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE38_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE38_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE38_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE38_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE38_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE38_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE38_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE38_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE38_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE38_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE39_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE39_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE39_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE39_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE39_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE39_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE39_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE39_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE39_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE39_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE39_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE39_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE39_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE39_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE39_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE39_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE39_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE39_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE39_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE39_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE39_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE39_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE40_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE40_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE40_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE40_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE40_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE40_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE40_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE40_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE40_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE40_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE40_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE40_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE40_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE40_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE40_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE40_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE40_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE40_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE40_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE40_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE40_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE40_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE41_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE41_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE41_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE41_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE41_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE41_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE41_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE41_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE41_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE41_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE41_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE41_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE41_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE41_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE41_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE41_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE41_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE41_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE41_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE41_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE41_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE41_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE42_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE42_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE42_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE42_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE42_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE42_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE42_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE42_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE42_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE42_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE42_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE42_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE42_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE42_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE42_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE42_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE42_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE42_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE42_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE42_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE42_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE42_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE43_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE43_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE43_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE43_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE43_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE43_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE43_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE43_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE43_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE43_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE43_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE43_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE43_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE43_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE43_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE43_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE43_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE43_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE43_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE43_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE43_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE43_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE44_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE44_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE44_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE44_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE44_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE44_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE44_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE44_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE44_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE44_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE44_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE44_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE44_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE44_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE44_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE44_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE44_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE44_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE44_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE44_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE44_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE44_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE45_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE45_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE45_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE45_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE45_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE45_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE45_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE45_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE45_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE45_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE45_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE45_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE45_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE45_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE45_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE45_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE45_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE45_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE45_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE45_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE45_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE45_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE46_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE46_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE46_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE46_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE46_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE46_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE46_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE46_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE46_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE46_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE46_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE46_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE46_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE46_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE46_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE46_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE46_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE46_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE46_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE46_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE46_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE46_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE47_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE47_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE47_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE47_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE47_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE47_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE47_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE47_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE47_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE47_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE47_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE47_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE47_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE47_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE47_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE47_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE47_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE47_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE47_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE47_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE47_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE47_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE48_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE48_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE48_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE48_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE48_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE48_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE48_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE48_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE48_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE48_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE48_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE48_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE48_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE48_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE48_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE48_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE48_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE48_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE48_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE48_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE48_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE48_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE49_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE49_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE49_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE49_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE49_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE49_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE49_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE49_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE49_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE49_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE49_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE49_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE49_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE49_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE49_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE49_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE49_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE49_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE49_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE49_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE49_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE49_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE50_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE50_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE50_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE50_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE50_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE50_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE50_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE50_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE50_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE50_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE50_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE50_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE50_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE50_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE50_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE50_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE50_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE50_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE50_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE50_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE50_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE50_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE51_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE51_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE51_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE51_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE51_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE51_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE51_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE51_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE51_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE51_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE51_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE51_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE51_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE51_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE51_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE51_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE51_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE51_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE51_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE51_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE51_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE51_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE52_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE52_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE52_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE52_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE52_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE52_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE52_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE52_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE52_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE52_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE52_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE52_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE52_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE52_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE52_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE52_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE52_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE52_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE52_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE52_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE52_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE52_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE53_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE53_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE53_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE53_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE53_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE53_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE53_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE53_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE53_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE53_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE53_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE53_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE53_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE53_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE53_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE53_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE53_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE53_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE53_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE53_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE53_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE53_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE54_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE54_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE54_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE54_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE54_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE54_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE54_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE54_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE54_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE54_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE54_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE54_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE54_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE54_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE54_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE54_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE54_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE54_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE54_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE54_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE54_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE54_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE55_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE55_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE55_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE55_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE55_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE55_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE55_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE55_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE55_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE55_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE55_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE55_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE55_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE55_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE55_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE55_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE55_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE55_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE55_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE55_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE55_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE55_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE56_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE56_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE56_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE56_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE56_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE56_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE56_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE56_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE56_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE56_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE56_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE56_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE56_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE56_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE56_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE56_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE56_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE56_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE56_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE56_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE56_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE56_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE57_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE57_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE57_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE57_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE57_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE57_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE57_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE57_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE57_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE57_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE57_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE57_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE57_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE57_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE57_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE57_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE57_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE57_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE57_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE57_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE57_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE57_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE58_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE58_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE58_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE58_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE58_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE58_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE58_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE58_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE58_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE58_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE58_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE58_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE58_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE58_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE58_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE58_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE58_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE58_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE58_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE58_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE58_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE58_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE59_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE59_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE59_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE59_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE59_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE59_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE59_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE59_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE59_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE59_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE59_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE59_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE59_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE59_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE59_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE59_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE59_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE59_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE59_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE59_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE59_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE59_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE60_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE60_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE60_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE60_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE60_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE60_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE60_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE60_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE60_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE60_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE60_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE60_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE60_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE60_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE60_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE60_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE60_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE60_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE60_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE60_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE60_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE60_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE61_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE61_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE61_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE61_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE61_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE61_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE61_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE61_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE61_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE61_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE61_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE61_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE61_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE61_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE61_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE61_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE61_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE61_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE61_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE61_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE61_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE61_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE62_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE62_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE62_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE62_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE62_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE62_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE62_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE62_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE62_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE62_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE62_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE62_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE62_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE62_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE62_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE62_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE62_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE62_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE62_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE62_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE62_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE62_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ +/* ===================================================== PAGE63_LOCK0 ====================================================== */ +#define OTP_DATA_RAW_PAGE63_LOCK0_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_RMA_Pos (7UL) /*!< RMA (Bit 7) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_RMA_Msk (0x80UL) /*!< RMA (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_NO_KEY_STATE_Pos (6UL) /*!< NO_KEY_STATE (Bit 6) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_NO_KEY_STATE_Msk (0x40UL) /*!< NO_KEY_STATE (Bitfield-Mask: 0x01) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_KEY_R_Pos (3UL) /*!< KEY_R (Bit 3) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_KEY_R_Msk (0x38UL) /*!< KEY_R (Bitfield-Mask: 0x07) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_KEY_W_Pos (0UL) /*!< KEY_W (Bit 0) */ +#define OTP_DATA_RAW_PAGE63_LOCK0_KEY_W_Msk (0x7UL) /*!< KEY_W (Bitfield-Mask: 0x07) */ +/* ===================================================== PAGE63_LOCK1 ====================================================== */ +#define OTP_DATA_RAW_PAGE63_LOCK1_R2_Pos (16UL) /*!< R2 (Bit 16) */ +#define OTP_DATA_RAW_PAGE63_LOCK1_R2_Msk (0xff0000UL) /*!< R2 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE63_LOCK1_R1_Pos (8UL) /*!< R1 (Bit 8) */ +#define OTP_DATA_RAW_PAGE63_LOCK1_R1_Msk (0xff00UL) /*!< R1 (Bitfield-Mask: 0xff) */ +#define OTP_DATA_RAW_PAGE63_LOCK1_LOCK_BL_Pos (4UL) /*!< LOCK_BL (Bit 4) */ +#define OTP_DATA_RAW_PAGE63_LOCK1_LOCK_BL_Msk (0x30UL) /*!< LOCK_BL (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE63_LOCK1_LOCK_NS_Pos (2UL) /*!< LOCK_NS (Bit 2) */ +#define OTP_DATA_RAW_PAGE63_LOCK1_LOCK_NS_Msk (0xcUL) /*!< LOCK_NS (Bitfield-Mask: 0x03) */ +#define OTP_DATA_RAW_PAGE63_LOCK1_LOCK_S_Pos (0UL) /*!< LOCK_S (Bit 0) */ +#define OTP_DATA_RAW_PAGE63_LOCK1_LOCK_S_Msk (0x3UL) /*!< LOCK_S (Bitfield-Mask: 0x03) */ + + +/* =========================================================================================================================== */ +/* ================ TBMAN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PLATFORM ======================================================== */ +#define TBMAN_PLATFORM_HDLSIM_Pos (2UL) /*!< HDLSIM (Bit 2) */ +#define TBMAN_PLATFORM_HDLSIM_Msk (0x4UL) /*!< HDLSIM (Bitfield-Mask: 0x01) */ +#define TBMAN_PLATFORM_FPGA_Pos (1UL) /*!< FPGA (Bit 1) */ +#define TBMAN_PLATFORM_FPGA_Msk (0x2UL) /*!< FPGA (Bitfield-Mask: 0x01) */ +#define TBMAN_PLATFORM_ASIC_Pos (0UL) /*!< ASIC (Bit 0) */ +#define TBMAN_PLATFORM_ASIC_Msk (0x1UL) /*!< ASIC (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ USB_DPRAM ================ */ +/* =========================================================================================================================== */ + +/* =================================================== SETUP_PACKET_LOW ==================================================== */ +#define USB_DPRAM_SETUP_PACKET_LOW_WVALUE_Pos (16UL) /*!< WVALUE (Bit 16) */ +#define USB_DPRAM_SETUP_PACKET_LOW_WVALUE_Msk (0xffff0000UL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +#define USB_DPRAM_SETUP_PACKET_LOW_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ +#define USB_DPRAM_SETUP_PACKET_LOW_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ +#define USB_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ +#define USB_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* =================================================== SETUP_PACKET_HIGH =================================================== */ +#define USB_DPRAM_SETUP_PACKET_HIGH_WLENGTH_Pos (16UL) /*!< WLENGTH (Bit 16) */ +#define USB_DPRAM_SETUP_PACKET_HIGH_WLENGTH_Msk (0xffff0000UL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +#define USB_DPRAM_SETUP_PACKET_HIGH_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ +#define USB_DPRAM_SETUP_PACKET_HIGH_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP1_IN_CONTROL ===================================================== */ +#define USB_DPRAM_EP1_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP1_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP1_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP1_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP1_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP2_IN_CONTROL ===================================================== */ +#define USB_DPRAM_EP2_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP2_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP2_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP2_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP2_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP3_IN_CONTROL ===================================================== */ +#define USB_DPRAM_EP3_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP3_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP3_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP3_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP3_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP4_IN_CONTROL ===================================================== */ +#define USB_DPRAM_EP4_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP4_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP4_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP4_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP4_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP5_IN_CONTROL ===================================================== */ +#define USB_DPRAM_EP5_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP5_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP5_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP5_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP5_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP6_IN_CONTROL ===================================================== */ +#define USB_DPRAM_EP6_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP6_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP6_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP6_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP6_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP7_IN_CONTROL ===================================================== */ +#define USB_DPRAM_EP7_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP7_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP7_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP7_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP7_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP8_IN_CONTROL ===================================================== */ +#define USB_DPRAM_EP8_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP8_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP8_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP8_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP8_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP9_IN_CONTROL ===================================================== */ +#define USB_DPRAM_EP9_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP9_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP9_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP9_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP9_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP10_IN_CONTROL ==================================================== */ +#define USB_DPRAM_EP10_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP10_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP10_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP10_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP10_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP11_IN_CONTROL ==================================================== */ +#define USB_DPRAM_EP11_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP11_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP11_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP11_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP11_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP12_IN_CONTROL ==================================================== */ +#define USB_DPRAM_EP12_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP12_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP12_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP12_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP12_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP13_IN_CONTROL ==================================================== */ +#define USB_DPRAM_EP13_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP13_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP13_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP13_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP13_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP14_IN_CONTROL ==================================================== */ +#define USB_DPRAM_EP14_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP14_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP14_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP14_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP14_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP15_IN_CONTROL ==================================================== */ +#define USB_DPRAM_EP15_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP15_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP15_OUT_CONTROL ==================================================== */ +#define USB_DPRAM_EP15_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USB_DPRAM_EP15_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USB_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USB_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USB_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USB_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USB_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USB_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USB_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ================================================= EP0_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP0_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP1_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP1_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP2_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP2_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP3_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP3_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP4_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP4_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP5_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP5_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP6_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP6_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP7_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP7_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP8_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP8_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP9_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP9_OUT_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP10_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP10_OUT_BUFFER_CONTROL ================================================ */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP11_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP11_OUT_BUFFER_CONTROL ================================================ */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP12_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP12_OUT_BUFFER_CONTROL ================================================ */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP13_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP13_OUT_BUFFER_CONTROL ================================================ */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP14_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP14_OUT_BUFFER_CONTROL ================================================ */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP15_IN_BUFFER_CONTROL ================================================= */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP15_OUT_BUFFER_CONTROL ================================================ */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USB_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Enumerated Values Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup EnumValue_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ RESETS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RESET ========================================================= */ +/* ========================================================= WDSEL ========================================================= */ +/* ====================================================== RESET_DONE ======================================================= */ + + +/* =========================================================================================================================== */ +/* ================ PSM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FRCE_ON ======================================================== */ +/* ======================================================= FRCE_OFF ======================================================== */ +/* ========================================================= WDSEL ========================================================= */ +/* ========================================================= DONE ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ CLOCKS ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== CLK_GPOUT0_CTRL ==================================================== */ +/* ========================================= CLOCKS CLK_GPOUT0_CTRL AUXSRC [5..8] ========================================== */ +typedef enum { /*!< CLOCKS_CLK_GPOUT0_CTRL_AUXSRC */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clksrc_gpin0 = 1,/*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clksrc_gpin1 = 2,/*!< clksrc_gpin1 : clksrc_gpin1 */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clksrc_pll_usb = 3,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clksrc_pll_usb_primary_ref_opcg = 4,/*!< clksrc_pll_usb_primary_ref_opcg : clksrc_pll_usb_primary_ref_opcg */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_rosc_clksrc = 5,/*!< rosc_clksrc : rosc_clksrc */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_xosc_clksrc = 6,/*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_lposc_clksrc = 7,/*!< lposc_clksrc : lposc_clksrc */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_sys = 8, /*!< clk_sys : clk_sys */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_usb = 9, /*!< clk_usb : clk_usb */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_adc = 10, /*!< clk_adc : clk_adc */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_ref = 11, /*!< clk_ref : clk_ref */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_peri = 12, /*!< clk_peri : clk_peri */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_hstx = 13, /*!< clk_hstx : clk_hstx */ + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_otp_clk2fc = 14,/*!< otp_clk2fc : otp_clk2fc */ +} CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum; + +/* ==================================================== CLK_GPOUT0_DIV ===================================================== */ +/* ================================================== CLK_GPOUT0_SELECTED ================================================== */ +/* ==================================================== CLK_GPOUT1_CTRL ==================================================== */ +/* ========================================= CLOCKS CLK_GPOUT1_CTRL AUXSRC [5..8] ========================================== */ +typedef enum { /*!< CLOCKS_CLK_GPOUT1_CTRL_AUXSRC */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clksrc_gpin0 = 1,/*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clksrc_gpin1 = 2,/*!< clksrc_gpin1 : clksrc_gpin1 */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clksrc_pll_usb = 3,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clksrc_pll_usb_primary_ref_opcg = 4,/*!< clksrc_pll_usb_primary_ref_opcg : clksrc_pll_usb_primary_ref_opcg */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_rosc_clksrc = 5,/*!< rosc_clksrc : rosc_clksrc */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_xosc_clksrc = 6,/*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_lposc_clksrc = 7,/*!< lposc_clksrc : lposc_clksrc */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_sys = 8, /*!< clk_sys : clk_sys */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_usb = 9, /*!< clk_usb : clk_usb */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_adc = 10, /*!< clk_adc : clk_adc */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_ref = 11, /*!< clk_ref : clk_ref */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_peri = 12, /*!< clk_peri : clk_peri */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_hstx = 13, /*!< clk_hstx : clk_hstx */ + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_otp_clk2fc = 14,/*!< otp_clk2fc : otp_clk2fc */ +} CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Enum; + +/* ==================================================== CLK_GPOUT1_DIV ===================================================== */ +/* ================================================== CLK_GPOUT1_SELECTED ================================================== */ +/* ==================================================== CLK_GPOUT2_CTRL ==================================================== */ +/* ========================================= CLOCKS CLK_GPOUT2_CTRL AUXSRC [5..8] ========================================== */ +typedef enum { /*!< CLOCKS_CLK_GPOUT2_CTRL_AUXSRC */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clksrc_gpin0 = 1,/*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clksrc_gpin1 = 2,/*!< clksrc_gpin1 : clksrc_gpin1 */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clksrc_pll_usb = 3,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clksrc_pll_usb_primary_ref_opcg = 4,/*!< clksrc_pll_usb_primary_ref_opcg : clksrc_pll_usb_primary_ref_opcg */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_rosc_clksrc_ph = 5,/*!< rosc_clksrc_ph : rosc_clksrc_ph */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_xosc_clksrc = 6,/*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_lposc_clksrc = 7,/*!< lposc_clksrc : lposc_clksrc */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_sys = 8, /*!< clk_sys : clk_sys */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_usb = 9, /*!< clk_usb : clk_usb */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_adc = 10, /*!< clk_adc : clk_adc */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_ref = 11, /*!< clk_ref : clk_ref */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_peri = 12, /*!< clk_peri : clk_peri */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_hstx = 13, /*!< clk_hstx : clk_hstx */ + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_otp_clk2fc = 14,/*!< otp_clk2fc : otp_clk2fc */ +} CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Enum; + +/* ==================================================== CLK_GPOUT2_DIV ===================================================== */ +/* ================================================== CLK_GPOUT2_SELECTED ================================================== */ +/* ==================================================== CLK_GPOUT3_CTRL ==================================================== */ +/* ========================================= CLOCKS CLK_GPOUT3_CTRL AUXSRC [5..8] ========================================== */ +typedef enum { /*!< CLOCKS_CLK_GPOUT3_CTRL_AUXSRC */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clksrc_gpin0 = 1,/*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clksrc_gpin1 = 2,/*!< clksrc_gpin1 : clksrc_gpin1 */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clksrc_pll_usb = 3,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clksrc_pll_usb_primary_ref_opcg = 4,/*!< clksrc_pll_usb_primary_ref_opcg : clksrc_pll_usb_primary_ref_opcg */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_rosc_clksrc_ph = 5,/*!< rosc_clksrc_ph : rosc_clksrc_ph */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_xosc_clksrc = 6,/*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_lposc_clksrc = 7,/*!< lposc_clksrc : lposc_clksrc */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_sys = 8, /*!< clk_sys : clk_sys */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_usb = 9, /*!< clk_usb : clk_usb */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_adc = 10, /*!< clk_adc : clk_adc */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_ref = 11, /*!< clk_ref : clk_ref */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_peri = 12, /*!< clk_peri : clk_peri */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_hstx = 13, /*!< clk_hstx : clk_hstx */ + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_otp_clk2fc = 14,/*!< otp_clk2fc : otp_clk2fc */ +} CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Enum; + +/* ==================================================== CLK_GPOUT3_DIV ===================================================== */ +/* ================================================== CLK_GPOUT3_SELECTED ================================================== */ +/* ===================================================== CLK_REF_CTRL ====================================================== */ +/* =========================================== CLOCKS CLK_REF_CTRL AUXSRC [5..6] =========================================== */ +typedef enum { /*!< CLOCKS_CLK_REF_CTRL_AUXSRC */ + CLOCKS_CLK_REF_CTRL_AUXSRC_clksrc_pll_usb = 0,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_REF_CTRL_AUXSRC_clksrc_gpin0 = 1, /*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_REF_CTRL_AUXSRC_clksrc_gpin1 = 2, /*!< clksrc_gpin1 : clksrc_gpin1 */ + CLOCKS_CLK_REF_CTRL_AUXSRC_clksrc_pll_usb_primary_ref_opcg = 3,/*!< clksrc_pll_usb_primary_ref_opcg : clksrc_pll_usb_primary_ref_opcg */ +} CLOCKS_CLK_REF_CTRL_AUXSRC_Enum; + +/* ============================================ CLOCKS CLK_REF_CTRL SRC [0..1] ============================================= */ +typedef enum { /*!< CLOCKS_CLK_REF_CTRL_SRC */ + CLOCKS_CLK_REF_CTRL_SRC_rosc_clksrc_ph = 0, /*!< rosc_clksrc_ph : rosc_clksrc_ph */ + CLOCKS_CLK_REF_CTRL_SRC_clksrc_clk_ref_aux = 1,/*!< clksrc_clk_ref_aux : clksrc_clk_ref_aux */ + CLOCKS_CLK_REF_CTRL_SRC_xosc_clksrc = 2, /*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_CLK_REF_CTRL_SRC_lposc_clksrc = 3, /*!< lposc_clksrc : lposc_clksrc */ +} CLOCKS_CLK_REF_CTRL_SRC_Enum; + +/* ====================================================== CLK_REF_DIV ====================================================== */ +/* =================================================== CLK_REF_SELECTED ==================================================== */ +/* ===================================================== CLK_SYS_CTRL ====================================================== */ +/* =========================================== CLOCKS CLK_SYS_CTRL AUXSRC [5..7] =========================================== */ +typedef enum { /*!< CLOCKS_CLK_SYS_CTRL_AUXSRC */ + CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */ + CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_pll_usb = 1,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_SYS_CTRL_AUXSRC_rosc_clksrc = 2, /*!< rosc_clksrc : rosc_clksrc */ + CLOCKS_CLK_SYS_CTRL_AUXSRC_xosc_clksrc = 3, /*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_gpin0 = 4, /*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_gpin1 = 5, /*!< clksrc_gpin1 : clksrc_gpin1 */ +} CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum; + +/* ============================================ CLOCKS CLK_SYS_CTRL SRC [0..0] ============================================= */ +typedef enum { /*!< CLOCKS_CLK_SYS_CTRL_SRC */ + CLOCKS_CLK_SYS_CTRL_SRC_clk_ref = 0, /*!< clk_ref : clk_ref */ + CLOCKS_CLK_SYS_CTRL_SRC_clksrc_clk_sys_aux = 1,/*!< clksrc_clk_sys_aux : clksrc_clk_sys_aux */ +} CLOCKS_CLK_SYS_CTRL_SRC_Enum; + +/* ====================================================== CLK_SYS_DIV ====================================================== */ +/* =================================================== CLK_SYS_SELECTED ==================================================== */ +/* ===================================================== CLK_PERI_CTRL ===================================================== */ +/* ========================================== CLOCKS CLK_PERI_CTRL AUXSRC [5..7] =========================================== */ +typedef enum { /*!< CLOCKS_CLK_PERI_CTRL_AUXSRC */ + CLOCKS_CLK_PERI_CTRL_AUXSRC_clk_sys = 0, /*!< clk_sys : clk_sys */ + CLOCKS_CLK_PERI_CTRL_AUXSRC_clksrc_pll_sys = 1,/*!< clksrc_pll_sys : clksrc_pll_sys */ + CLOCKS_CLK_PERI_CTRL_AUXSRC_clksrc_pll_usb = 2,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_PERI_CTRL_AUXSRC_rosc_clksrc_ph = 3,/*!< rosc_clksrc_ph : rosc_clksrc_ph */ + CLOCKS_CLK_PERI_CTRL_AUXSRC_xosc_clksrc = 4, /*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_CLK_PERI_CTRL_AUXSRC_clksrc_gpin0 = 5, /*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_PERI_CTRL_AUXSRC_clksrc_gpin1 = 6, /*!< clksrc_gpin1 : clksrc_gpin1 */ +} CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum; + +/* ===================================================== CLK_PERI_DIV ====================================================== */ +/* =================================================== CLK_PERI_SELECTED =================================================== */ +/* ===================================================== CLK_HSTX_CTRL ===================================================== */ +/* ========================================== CLOCKS CLK_HSTX_CTRL AUXSRC [5..7] =========================================== */ +typedef enum { /*!< CLOCKS_CLK_HSTX_CTRL_AUXSRC */ + CLOCKS_CLK_HSTX_CTRL_AUXSRC_clk_sys = 0, /*!< clk_sys : clk_sys */ + CLOCKS_CLK_HSTX_CTRL_AUXSRC_clksrc_pll_sys = 1,/*!< clksrc_pll_sys : clksrc_pll_sys */ + CLOCKS_CLK_HSTX_CTRL_AUXSRC_clksrc_pll_usb = 2,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_HSTX_CTRL_AUXSRC_clksrc_gpin0 = 3, /*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_HSTX_CTRL_AUXSRC_clksrc_gpin1 = 4, /*!< clksrc_gpin1 : clksrc_gpin1 */ +} CLOCKS_CLK_HSTX_CTRL_AUXSRC_Enum; + +/* ===================================================== CLK_HSTX_DIV ====================================================== */ +/* =================================================== CLK_HSTX_SELECTED =================================================== */ +/* ===================================================== CLK_USB_CTRL ====================================================== */ +/* =========================================== CLOCKS CLK_USB_CTRL AUXSRC [5..7] =========================================== */ +typedef enum { /*!< CLOCKS_CLK_USB_CTRL_AUXSRC */ + CLOCKS_CLK_USB_CTRL_AUXSRC_clksrc_pll_usb = 0,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_USB_CTRL_AUXSRC_clksrc_pll_sys = 1,/*!< clksrc_pll_sys : clksrc_pll_sys */ + CLOCKS_CLK_USB_CTRL_AUXSRC_rosc_clksrc_ph = 2,/*!< rosc_clksrc_ph : rosc_clksrc_ph */ + CLOCKS_CLK_USB_CTRL_AUXSRC_xosc_clksrc = 3, /*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_CLK_USB_CTRL_AUXSRC_clksrc_gpin0 = 4, /*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_USB_CTRL_AUXSRC_clksrc_gpin1 = 5, /*!< clksrc_gpin1 : clksrc_gpin1 */ +} CLOCKS_CLK_USB_CTRL_AUXSRC_Enum; + +/* ====================================================== CLK_USB_DIV ====================================================== */ +/* =================================================== CLK_USB_SELECTED ==================================================== */ +/* ===================================================== CLK_ADC_CTRL ====================================================== */ +/* =========================================== CLOCKS CLK_ADC_CTRL AUXSRC [5..7] =========================================== */ +typedef enum { /*!< CLOCKS_CLK_ADC_CTRL_AUXSRC */ + CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_pll_usb = 0,/*!< clksrc_pll_usb : clksrc_pll_usb */ + CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_pll_sys = 1,/*!< clksrc_pll_sys : clksrc_pll_sys */ + CLOCKS_CLK_ADC_CTRL_AUXSRC_rosc_clksrc_ph = 2,/*!< rosc_clksrc_ph : rosc_clksrc_ph */ + CLOCKS_CLK_ADC_CTRL_AUXSRC_xosc_clksrc = 3, /*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_gpin0 = 4, /*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_gpin1 = 5, /*!< clksrc_gpin1 : clksrc_gpin1 */ +} CLOCKS_CLK_ADC_CTRL_AUXSRC_Enum; + +/* ====================================================== CLK_ADC_DIV ====================================================== */ +/* =================================================== CLK_ADC_SELECTED ==================================================== */ +/* =================================================== DFTCLK_XOSC_CTRL ==================================================== */ +/* ========================================== CLOCKS DFTCLK_XOSC_CTRL SRC [0..1] =========================================== */ +typedef enum { /*!< CLOCKS_DFTCLK_XOSC_CTRL_SRC */ + CLOCKS_DFTCLK_XOSC_CTRL_SRC_NULL = 0, /*!< NULL : NULL */ + CLOCKS_DFTCLK_XOSC_CTRL_SRC_clksrc_pll_usb_primary = 1,/*!< clksrc_pll_usb_primary : clksrc_pll_usb_primary */ + CLOCKS_DFTCLK_XOSC_CTRL_SRC_clksrc_gpin0 = 2, /*!< clksrc_gpin0 : clksrc_gpin0 */ +} CLOCKS_DFTCLK_XOSC_CTRL_SRC_Enum; + +/* =================================================== DFTCLK_ROSC_CTRL ==================================================== */ +/* ========================================== CLOCKS DFTCLK_ROSC_CTRL SRC [0..1] =========================================== */ +typedef enum { /*!< CLOCKS_DFTCLK_ROSC_CTRL_SRC */ + CLOCKS_DFTCLK_ROSC_CTRL_SRC_NULL = 0, /*!< NULL : NULL */ + CLOCKS_DFTCLK_ROSC_CTRL_SRC_clksrc_pll_sys_primary_rosc = 1,/*!< clksrc_pll_sys_primary_rosc : clksrc_pll_sys_primary_rosc */ + CLOCKS_DFTCLK_ROSC_CTRL_SRC_clksrc_gpin1 = 2, /*!< clksrc_gpin1 : clksrc_gpin1 */ +} CLOCKS_DFTCLK_ROSC_CTRL_SRC_Enum; + +/* =================================================== DFTCLK_LPOSC_CTRL =================================================== */ +/* ========================================== CLOCKS DFTCLK_LPOSC_CTRL SRC [0..1] ========================================== */ +typedef enum { /*!< CLOCKS_DFTCLK_LPOSC_CTRL_SRC */ + CLOCKS_DFTCLK_LPOSC_CTRL_SRC_NULL = 0, /*!< NULL : NULL */ + CLOCKS_DFTCLK_LPOSC_CTRL_SRC_clksrc_pll_usb_primary_lposc = 1,/*!< clksrc_pll_usb_primary_lposc : clksrc_pll_usb_primary_lposc */ + CLOCKS_DFTCLK_LPOSC_CTRL_SRC_clksrc_gpin1 = 2,/*!< clksrc_gpin1 : clksrc_gpin1 */ +} CLOCKS_DFTCLK_LPOSC_CTRL_SRC_Enum; + +/* ================================================== CLK_SYS_RESUS_CTRL =================================================== */ +/* ================================================= CLK_SYS_RESUS_STATUS ================================================== */ +/* ====================================================== FC0_REF_KHZ ====================================================== */ +/* ====================================================== FC0_MIN_KHZ ====================================================== */ +/* ====================================================== FC0_MAX_KHZ ====================================================== */ +/* ======================================================= FC0_DELAY ======================================================= */ +/* ===================================================== FC0_INTERVAL ====================================================== */ +/* ======================================================== FC0_SRC ======================================================== */ +/* ============================================= CLOCKS FC0_SRC FC0_SRC [0..7] ============================================= */ +typedef enum { /*!< CLOCKS_FC0_SRC_FC0_SRC */ + CLOCKS_FC0_SRC_FC0_SRC_NULL = 0, /*!< NULL : NULL */ + CLOCKS_FC0_SRC_FC0_SRC_pll_sys_clksrc_primary = 1,/*!< pll_sys_clksrc_primary : pll_sys_clksrc_primary */ + CLOCKS_FC0_SRC_FC0_SRC_pll_usb_clksrc_primary = 2,/*!< pll_usb_clksrc_primary : pll_usb_clksrc_primary */ + CLOCKS_FC0_SRC_FC0_SRC_rosc_clksrc = 3, /*!< rosc_clksrc : rosc_clksrc */ + CLOCKS_FC0_SRC_FC0_SRC_rosc_clksrc_ph = 4, /*!< rosc_clksrc_ph : rosc_clksrc_ph */ + CLOCKS_FC0_SRC_FC0_SRC_xosc_clksrc = 5, /*!< xosc_clksrc : xosc_clksrc */ + CLOCKS_FC0_SRC_FC0_SRC_clksrc_gpin0 = 6, /*!< clksrc_gpin0 : clksrc_gpin0 */ + CLOCKS_FC0_SRC_FC0_SRC_clksrc_gpin1 = 7, /*!< clksrc_gpin1 : clksrc_gpin1 */ + CLOCKS_FC0_SRC_FC0_SRC_clk_ref = 8, /*!< clk_ref : clk_ref */ + CLOCKS_FC0_SRC_FC0_SRC_clk_sys = 9, /*!< clk_sys : clk_sys */ + CLOCKS_FC0_SRC_FC0_SRC_clk_peri = 10, /*!< clk_peri : clk_peri */ + CLOCKS_FC0_SRC_FC0_SRC_clk_usb = 11, /*!< clk_usb : clk_usb */ + CLOCKS_FC0_SRC_FC0_SRC_clk_adc = 12, /*!< clk_adc : clk_adc */ + CLOCKS_FC0_SRC_FC0_SRC_clk_hstx = 13, /*!< clk_hstx : clk_hstx */ + CLOCKS_FC0_SRC_FC0_SRC_lposc_clksrc = 14, /*!< lposc_clksrc : lposc_clksrc */ + CLOCKS_FC0_SRC_FC0_SRC_otp_clk2fc = 15, /*!< otp_clk2fc : otp_clk2fc */ + CLOCKS_FC0_SRC_FC0_SRC_pll_usb_clksrc_primary_dft = 16,/*!< pll_usb_clksrc_primary_dft : pll_usb_clksrc_primary_dft */ +} CLOCKS_FC0_SRC_FC0_SRC_Enum; + +/* ====================================================== FC0_STATUS ======================================================= */ +/* ====================================================== FC0_RESULT ======================================================= */ +/* ======================================================= WAKE_EN0 ======================================================== */ +/* ======================================================= WAKE_EN1 ======================================================== */ +/* ======================================================= SLEEP_EN0 ======================================================= */ +/* ======================================================= SLEEP_EN1 ======================================================= */ +/* ======================================================= ENABLED0 ======================================================== */ +/* ======================================================= ENABLED1 ======================================================== */ +/* ========================================================= INTR ========================================================== */ +/* ========================================================= INTE ========================================================== */ +/* ========================================================= INTF ========================================================== */ +/* ========================================================= INTS ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ TICKS ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== PROC0_CTRL ======================================================= */ +/* ===================================================== PROC0_CYCLES ====================================================== */ +/* ====================================================== PROC0_COUNT ====================================================== */ +/* ====================================================== PROC1_CTRL ======================================================= */ +/* ===================================================== PROC1_CYCLES ====================================================== */ +/* ====================================================== PROC1_COUNT ====================================================== */ +/* ====================================================== TIMER0_CTRL ====================================================== */ +/* ===================================================== TIMER0_CYCLES ===================================================== */ +/* ===================================================== TIMER0_COUNT ====================================================== */ +/* ====================================================== TIMER1_CTRL ====================================================== */ +/* ===================================================== TIMER1_CYCLES ===================================================== */ +/* ===================================================== TIMER1_COUNT ====================================================== */ +/* ===================================================== WATCHDOG_CTRL ===================================================== */ +/* ==================================================== WATCHDOG_CYCLES ==================================================== */ +/* ==================================================== WATCHDOG_COUNT ===================================================== */ +/* ====================================================== RISCV_CTRL ======================================================= */ +/* ===================================================== RISCV_CYCLES ====================================================== */ +/* ====================================================== RISCV_COUNT ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ PADS_BANK0 ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== VOLTAGE_SELECT ===================================================== */ +/* ==================================== PADS_BANK0 VOLTAGE_SELECT VOLTAGE_SELECT [0..0] ==================================== */ +typedef enum { /*!< PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT */ + PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_3v3 = 0,/*!< 3v3 : Set voltage to 3.3V (DVDD >= 2V5) */ + PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_1v8 = 1,/*!< 1v8 : Set voltage to 1.8V (DVDD <= 1V8) */ +} PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_Enum; + +/* ========================================================= GPIO0 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO0 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO0_DRIVE */ + PADS_BANK0_GPIO0_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO0_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO0_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO0_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO0_DRIVE_Enum; + +/* ========================================================= GPIO1 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO1 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO1_DRIVE */ + PADS_BANK0_GPIO1_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO1_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO1_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO1_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO1_DRIVE_Enum; + +/* ========================================================= GPIO2 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO2 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO2_DRIVE */ + PADS_BANK0_GPIO2_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO2_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO2_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO2_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO2_DRIVE_Enum; + +/* ========================================================= GPIO3 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO3 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO3_DRIVE */ + PADS_BANK0_GPIO3_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO3_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO3_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO3_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO3_DRIVE_Enum; + +/* ========================================================= GPIO4 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO4 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO4_DRIVE */ + PADS_BANK0_GPIO4_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO4_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO4_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO4_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO4_DRIVE_Enum; + +/* ========================================================= GPIO5 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO5 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO5_DRIVE */ + PADS_BANK0_GPIO5_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO5_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO5_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO5_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO5_DRIVE_Enum; + +/* ========================================================= GPIO6 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO6 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO6_DRIVE */ + PADS_BANK0_GPIO6_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO6_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO6_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO6_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO6_DRIVE_Enum; + +/* ========================================================= GPIO7 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO7 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO7_DRIVE */ + PADS_BANK0_GPIO7_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO7_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO7_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO7_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO7_DRIVE_Enum; + +/* ========================================================= GPIO8 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO8 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO8_DRIVE */ + PADS_BANK0_GPIO8_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO8_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO8_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO8_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO8_DRIVE_Enum; + +/* ========================================================= GPIO9 ========================================================= */ +/* ============================================= PADS_BANK0 GPIO9 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO9_DRIVE */ + PADS_BANK0_GPIO9_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO9_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO9_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO9_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO9_DRIVE_Enum; + +/* ======================================================== GPIO10 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO10 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO10_DRIVE */ + PADS_BANK0_GPIO10_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO10_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO10_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO10_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO10_DRIVE_Enum; + +/* ======================================================== GPIO11 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO11 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO11_DRIVE */ + PADS_BANK0_GPIO11_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO11_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO11_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO11_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO11_DRIVE_Enum; + +/* ======================================================== GPIO12 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO12 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO12_DRIVE */ + PADS_BANK0_GPIO12_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO12_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO12_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO12_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO12_DRIVE_Enum; + +/* ======================================================== GPIO13 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO13 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO13_DRIVE */ + PADS_BANK0_GPIO13_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO13_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO13_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO13_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO13_DRIVE_Enum; + +/* ======================================================== GPIO14 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO14 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO14_DRIVE */ + PADS_BANK0_GPIO14_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO14_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO14_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO14_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO14_DRIVE_Enum; + +/* ======================================================== GPIO15 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO15 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO15_DRIVE */ + PADS_BANK0_GPIO15_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO15_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO15_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO15_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO15_DRIVE_Enum; + +/* ======================================================== GPIO16 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO16 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO16_DRIVE */ + PADS_BANK0_GPIO16_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO16_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO16_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO16_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO16_DRIVE_Enum; + +/* ======================================================== GPIO17 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO17 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO17_DRIVE */ + PADS_BANK0_GPIO17_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO17_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO17_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO17_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO17_DRIVE_Enum; + +/* ======================================================== GPIO18 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO18 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO18_DRIVE */ + PADS_BANK0_GPIO18_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO18_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO18_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO18_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO18_DRIVE_Enum; + +/* ======================================================== GPIO19 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO19 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO19_DRIVE */ + PADS_BANK0_GPIO19_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO19_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO19_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO19_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO19_DRIVE_Enum; + +/* ======================================================== GPIO20 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO20 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO20_DRIVE */ + PADS_BANK0_GPIO20_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO20_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO20_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO20_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO20_DRIVE_Enum; + +/* ======================================================== GPIO21 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO21 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO21_DRIVE */ + PADS_BANK0_GPIO21_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO21_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO21_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO21_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO21_DRIVE_Enum; + +/* ======================================================== GPIO22 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO22 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO22_DRIVE */ + PADS_BANK0_GPIO22_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO22_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO22_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO22_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO22_DRIVE_Enum; + +/* ======================================================== GPIO23 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO23 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO23_DRIVE */ + PADS_BANK0_GPIO23_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO23_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO23_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO23_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO23_DRIVE_Enum; + +/* ======================================================== GPIO24 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO24 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO24_DRIVE */ + PADS_BANK0_GPIO24_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO24_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO24_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO24_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO24_DRIVE_Enum; + +/* ======================================================== GPIO25 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO25 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO25_DRIVE */ + PADS_BANK0_GPIO25_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO25_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO25_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO25_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO25_DRIVE_Enum; + +/* ======================================================== GPIO26 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO26 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO26_DRIVE */ + PADS_BANK0_GPIO26_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO26_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO26_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO26_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO26_DRIVE_Enum; + +/* ======================================================== GPIO27 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO27 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO27_DRIVE */ + PADS_BANK0_GPIO27_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO27_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO27_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO27_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO27_DRIVE_Enum; + +/* ======================================================== GPIO28 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO28 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO28_DRIVE */ + PADS_BANK0_GPIO28_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO28_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO28_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO28_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO28_DRIVE_Enum; + +/* ======================================================== GPIO29 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO29 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO29_DRIVE */ + PADS_BANK0_GPIO29_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO29_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO29_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO29_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO29_DRIVE_Enum; + +/* ======================================================== GPIO30 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO30 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO30_DRIVE */ + PADS_BANK0_GPIO30_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO30_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO30_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO30_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO30_DRIVE_Enum; + +/* ======================================================== GPIO31 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO31 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO31_DRIVE */ + PADS_BANK0_GPIO31_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO31_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO31_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO31_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO31_DRIVE_Enum; + +/* ======================================================== GPIO32 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO32 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO32_DRIVE */ + PADS_BANK0_GPIO32_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO32_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO32_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO32_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO32_DRIVE_Enum; + +/* ======================================================== GPIO33 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO33 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO33_DRIVE */ + PADS_BANK0_GPIO33_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO33_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO33_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO33_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO33_DRIVE_Enum; + +/* ======================================================== GPIO34 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO34 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO34_DRIVE */ + PADS_BANK0_GPIO34_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO34_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO34_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO34_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO34_DRIVE_Enum; + +/* ======================================================== GPIO35 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO35 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO35_DRIVE */ + PADS_BANK0_GPIO35_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO35_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO35_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO35_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO35_DRIVE_Enum; + +/* ======================================================== GPIO36 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO36 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO36_DRIVE */ + PADS_BANK0_GPIO36_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO36_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO36_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO36_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO36_DRIVE_Enum; + +/* ======================================================== GPIO37 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO37 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO37_DRIVE */ + PADS_BANK0_GPIO37_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO37_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO37_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO37_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO37_DRIVE_Enum; + +/* ======================================================== GPIO38 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO38 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO38_DRIVE */ + PADS_BANK0_GPIO38_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO38_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO38_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO38_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO38_DRIVE_Enum; + +/* ======================================================== GPIO39 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO39 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO39_DRIVE */ + PADS_BANK0_GPIO39_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO39_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO39_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO39_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO39_DRIVE_Enum; + +/* ======================================================== GPIO40 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO40 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO40_DRIVE */ + PADS_BANK0_GPIO40_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO40_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO40_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO40_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO40_DRIVE_Enum; + +/* ======================================================== GPIO41 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO41 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO41_DRIVE */ + PADS_BANK0_GPIO41_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO41_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO41_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO41_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO41_DRIVE_Enum; + +/* ======================================================== GPIO42 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO42 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO42_DRIVE */ + PADS_BANK0_GPIO42_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO42_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO42_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO42_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO42_DRIVE_Enum; + +/* ======================================================== GPIO43 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO43 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO43_DRIVE */ + PADS_BANK0_GPIO43_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO43_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO43_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO43_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO43_DRIVE_Enum; + +/* ======================================================== GPIO44 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO44 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO44_DRIVE */ + PADS_BANK0_GPIO44_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO44_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO44_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO44_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO44_DRIVE_Enum; + +/* ======================================================== GPIO45 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO45 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO45_DRIVE */ + PADS_BANK0_GPIO45_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO45_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO45_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO45_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO45_DRIVE_Enum; + +/* ======================================================== GPIO46 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO46 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO46_DRIVE */ + PADS_BANK0_GPIO46_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO46_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO46_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO46_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO46_DRIVE_Enum; + +/* ======================================================== GPIO47 ========================================================= */ +/* ============================================ PADS_BANK0 GPIO47 DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_GPIO47_DRIVE */ + PADS_BANK0_GPIO47_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_GPIO47_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_GPIO47_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_GPIO47_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_GPIO47_DRIVE_Enum; + +/* ========================================================= SWCLK ========================================================= */ +/* ============================================= PADS_BANK0 SWCLK DRIVE [4..5] ============================================= */ +typedef enum { /*!< PADS_BANK0_SWCLK_DRIVE */ + PADS_BANK0_SWCLK_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_SWCLK_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_SWCLK_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_SWCLK_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_SWCLK_DRIVE_Enum; + +/* ========================================================== SWD ========================================================== */ +/* ============================================== PADS_BANK0 SWD DRIVE [4..5] ============================================== */ +typedef enum { /*!< PADS_BANK0_SWD_DRIVE */ + PADS_BANK0_SWD_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_BANK0_SWD_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_BANK0_SWD_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_BANK0_SWD_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_BANK0_SWD_DRIVE_Enum; + + + +/* =========================================================================================================================== */ +/* ================ PADS_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== VOLTAGE_SELECT ===================================================== */ +/* ==================================== PADS_QSPI VOLTAGE_SELECT VOLTAGE_SELECT [0..0] ===================================== */ +typedef enum { /*!< PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT */ + PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_3v3 = 0,/*!< 3v3 : Set voltage to 3.3V (DVDD >= 2V5) */ + PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_1v8 = 1,/*!< 1v8 : Set voltage to 1.8V (DVDD <= 1V8) */ +} PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_Enum; + +/* ==================================================== GPIO_QSPI_SCLK ===================================================== */ +/* ========================================= PADS_QSPI GPIO_QSPI_SCLK DRIVE [4..5] ========================================= */ +typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SCLK_DRIVE */ + PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_Enum; + +/* ===================================================== GPIO_QSPI_SD0 ===================================================== */ +/* ========================================= PADS_QSPI GPIO_QSPI_SD0 DRIVE [4..5] ========================================== */ +typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SD0_DRIVE */ + PADS_QSPI_GPIO_QSPI_SD0_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_QSPI_GPIO_QSPI_SD0_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_QSPI_GPIO_QSPI_SD0_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_QSPI_GPIO_QSPI_SD0_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_QSPI_GPIO_QSPI_SD0_DRIVE_Enum; + +/* ===================================================== GPIO_QSPI_SD1 ===================================================== */ +/* ========================================= PADS_QSPI GPIO_QSPI_SD1 DRIVE [4..5] ========================================== */ +typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SD1_DRIVE */ + PADS_QSPI_GPIO_QSPI_SD1_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_QSPI_GPIO_QSPI_SD1_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_QSPI_GPIO_QSPI_SD1_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_QSPI_GPIO_QSPI_SD1_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_QSPI_GPIO_QSPI_SD1_DRIVE_Enum; + +/* ===================================================== GPIO_QSPI_SD2 ===================================================== */ +/* ========================================= PADS_QSPI GPIO_QSPI_SD2 DRIVE [4..5] ========================================== */ +typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SD2_DRIVE */ + PADS_QSPI_GPIO_QSPI_SD2_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_QSPI_GPIO_QSPI_SD2_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_QSPI_GPIO_QSPI_SD2_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_QSPI_GPIO_QSPI_SD2_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_QSPI_GPIO_QSPI_SD2_DRIVE_Enum; + +/* ===================================================== GPIO_QSPI_SD3 ===================================================== */ +/* ========================================= PADS_QSPI GPIO_QSPI_SD3 DRIVE [4..5] ========================================== */ +typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SD3_DRIVE */ + PADS_QSPI_GPIO_QSPI_SD3_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_QSPI_GPIO_QSPI_SD3_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_QSPI_GPIO_QSPI_SD3_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_QSPI_GPIO_QSPI_SD3_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_QSPI_GPIO_QSPI_SD3_DRIVE_Enum; + +/* ===================================================== GPIO_QSPI_SS ====================================================== */ +/* ========================================== PADS_QSPI GPIO_QSPI_SS DRIVE [4..5] ========================================== */ +typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SS_DRIVE */ + PADS_QSPI_GPIO_QSPI_SS_DRIVE_2mA = 0, /*!< 2mA : 2mA */ + PADS_QSPI_GPIO_QSPI_SS_DRIVE_4mA = 1, /*!< 4mA : 4mA */ + PADS_QSPI_GPIO_QSPI_SS_DRIVE_8mA = 2, /*!< 8mA : 8mA */ + PADS_QSPI_GPIO_QSPI_SS_DRIVE_12mA = 3, /*!< 12mA : 12mA */ +} PADS_QSPI_GPIO_QSPI_SS_DRIVE_Enum; + + + +/* =========================================================================================================================== */ +/* ================ IO_QSPI ================ */ +/* =========================================================================================================================== */ + +/* =================================================== USBPHY_DP_STATUS ==================================================== */ +/* ==================================================== USBPHY_DP_CTRL ===================================================== */ +/* ======================================== IO_QSPI USBPHY_DP_CTRL IRQOVER [28..29] ======================================== */ +typedef enum { /*!< IO_QSPI_USBPHY_DP_CTRL_IRQOVER */ + IO_QSPI_USBPHY_DP_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_QSPI_USBPHY_DP_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_QSPI_USBPHY_DP_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_QSPI_USBPHY_DP_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_QSPI_USBPHY_DP_CTRL_IRQOVER_Enum; + +/* ======================================== IO_QSPI USBPHY_DP_CTRL INOVER [16..17] ========================================= */ +typedef enum { /*!< IO_QSPI_USBPHY_DP_CTRL_INOVER */ + IO_QSPI_USBPHY_DP_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_QSPI_USBPHY_DP_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_QSPI_USBPHY_DP_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_QSPI_USBPHY_DP_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_QSPI_USBPHY_DP_CTRL_INOVER_Enum; + +/* ======================================== IO_QSPI USBPHY_DP_CTRL OEOVER [14..15] ========================================= */ +typedef enum { /*!< IO_QSPI_USBPHY_DP_CTRL_OEOVER */ + IO_QSPI_USBPHY_DP_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_QSPI_USBPHY_DP_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_QSPI_USBPHY_DP_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_QSPI_USBPHY_DP_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_QSPI_USBPHY_DP_CTRL_OEOVER_Enum; + +/* ======================================== IO_QSPI USBPHY_DP_CTRL OUTOVER [12..13] ======================================== */ +typedef enum { /*!< IO_QSPI_USBPHY_DP_CTRL_OUTOVER */ + IO_QSPI_USBPHY_DP_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_QSPI_USBPHY_DP_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_QSPI_USBPHY_DP_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_QSPI_USBPHY_DP_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_QSPI_USBPHY_DP_CTRL_OUTOVER_Enum; + +/* ========================================= IO_QSPI USBPHY_DP_CTRL FUNCSEL [0..4] ========================================= */ +typedef enum { /*!< IO_QSPI_USBPHY_DP_CTRL_FUNCSEL */ + IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */ + IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_siob_proc_56 = 5,/*!< siob_proc_56 : siob_proc_56 */ + IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_Enum; + +/* =================================================== USBPHY_DM_STATUS ==================================================== */ +/* ==================================================== USBPHY_DM_CTRL ===================================================== */ +/* ======================================== IO_QSPI USBPHY_DM_CTRL IRQOVER [28..29] ======================================== */ +typedef enum { /*!< IO_QSPI_USBPHY_DM_CTRL_IRQOVER */ + IO_QSPI_USBPHY_DM_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_QSPI_USBPHY_DM_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_QSPI_USBPHY_DM_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_QSPI_USBPHY_DM_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_QSPI_USBPHY_DM_CTRL_IRQOVER_Enum; + +/* ======================================== IO_QSPI USBPHY_DM_CTRL INOVER [16..17] ========================================= */ +typedef enum { /*!< IO_QSPI_USBPHY_DM_CTRL_INOVER */ + IO_QSPI_USBPHY_DM_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_QSPI_USBPHY_DM_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_QSPI_USBPHY_DM_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_QSPI_USBPHY_DM_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_QSPI_USBPHY_DM_CTRL_INOVER_Enum; + +/* ======================================== IO_QSPI USBPHY_DM_CTRL OEOVER [14..15] ========================================= */ +typedef enum { /*!< IO_QSPI_USBPHY_DM_CTRL_OEOVER */ + IO_QSPI_USBPHY_DM_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_QSPI_USBPHY_DM_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_QSPI_USBPHY_DM_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_QSPI_USBPHY_DM_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_QSPI_USBPHY_DM_CTRL_OEOVER_Enum; + +/* ======================================== IO_QSPI USBPHY_DM_CTRL OUTOVER [12..13] ======================================== */ +typedef enum { /*!< IO_QSPI_USBPHY_DM_CTRL_OUTOVER */ + IO_QSPI_USBPHY_DM_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_QSPI_USBPHY_DM_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_QSPI_USBPHY_DM_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_QSPI_USBPHY_DM_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_QSPI_USBPHY_DM_CTRL_OUTOVER_Enum; + +/* ========================================= IO_QSPI USBPHY_DM_CTRL FUNCSEL [0..4] ========================================= */ +typedef enum { /*!< IO_QSPI_USBPHY_DM_CTRL_FUNCSEL */ + IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */ + IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_siob_proc_57 = 5,/*!< siob_proc_57 : siob_proc_57 */ + IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_Enum; + +/* ================================================= GPIO_QSPI_SCLK_STATUS ================================================= */ +/* ================================================== GPIO_QSPI_SCLK_CTRL ================================================== */ +/* ===================================== IO_QSPI GPIO_QSPI_SCLK_CTRL IRQOVER [28..29] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SCLK_CTRL INOVER [16..17] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_NORMAL = 0,/*!< NORMAL : don't invert the peri input */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_INVERT = 1,/*!< INVERT : invert the peri input */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SCLK_CTRL OEOVER [14..15] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_NORMAL = 0,/*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_INVERT = 1,/*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ENABLE = 3,/*!< ENABLE : enable output */ +} IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_Enum; + +/* ===================================== IO_QSPI GPIO_QSPI_SCLK_CTRL OUTOVER [12..13] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SCLK_CTRL FUNCSEL [0..4] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_xip_sclk = 0,/*!< xip_sclk : xip_sclk */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_uart1_cts = 2,/*!< uart1_cts : uart1_cts */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_i2c1_sda = 3,/*!< i2c1_sda : i2c1_sda */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_siob_proc_58 = 5,/*!< siob_proc_58 : siob_proc_58 */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_uart1_tx = 11,/*!< uart1_tx : uart1_tx */ + IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_null = 31,/*!< null : null */ +} IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_Enum; + +/* ================================================== GPIO_QSPI_SS_STATUS ================================================== */ +/* =================================================== GPIO_QSPI_SS_CTRL =================================================== */ +/* ====================================== IO_QSPI GPIO_QSPI_SS_CTRL IRQOVER [28..29] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER */ + IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_Enum; + +/* ======================================= IO_QSPI GPIO_QSPI_SS_CTRL INOVER [16..17] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER */ + IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_Enum; + +/* ======================================= IO_QSPI GPIO_QSPI_SS_CTRL OEOVER [14..15] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER */ + IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SS_CTRL OUTOVER [12..13] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER */ + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_Enum; + +/* ======================================= IO_QSPI GPIO_QSPI_SS_CTRL FUNCSEL [0..4] ======================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL */ + IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_xip_ss_n_0 = 0,/*!< xip_ss_n_0 : xip_ss_n_0 */ + IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_uart1_rts = 2,/*!< uart1_rts : uart1_rts */ + IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_i2c1_scl = 3,/*!< i2c1_scl : i2c1_scl */ + IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_siob_proc_59 = 5,/*!< siob_proc_59 : siob_proc_59 */ + IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_uart1_rx = 11,/*!< uart1_rx : uart1_rx */ + IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_Enum; + +/* ================================================= GPIO_QSPI_SD0_STATUS ================================================== */ +/* ================================================== GPIO_QSPI_SD0_CTRL =================================================== */ +/* ====================================== IO_QSPI GPIO_QSPI_SD0_CTRL IRQOVER [28..29] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD0_CTRL INOVER [16..17] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD0_CTRL OEOVER [14..15] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD0_CTRL OUTOVER [12..13] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_Enum; + +/* ======================================= IO_QSPI GPIO_QSPI_SD0_CTRL FUNCSEL [0..4] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_xip_sd0 = 0,/*!< xip_sd0 : xip_sd0 */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_uart0_tx = 2,/*!< uart0_tx : uart0_tx */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_i2c0_sda = 3,/*!< i2c0_sda : i2c0_sda */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_siob_proc_60 = 5,/*!< siob_proc_60 : siob_proc_60 */ + IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_Enum; + +/* ================================================= GPIO_QSPI_SD1_STATUS ================================================== */ +/* ================================================== GPIO_QSPI_SD1_CTRL =================================================== */ +/* ====================================== IO_QSPI GPIO_QSPI_SD1_CTRL IRQOVER [28..29] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD1_CTRL INOVER [16..17] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD1_CTRL OEOVER [14..15] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD1_CTRL OUTOVER [12..13] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_Enum; + +/* ======================================= IO_QSPI GPIO_QSPI_SD1_CTRL FUNCSEL [0..4] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_xip_sd1 = 0,/*!< xip_sd1 : xip_sd1 */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_uart0_rx = 2,/*!< uart0_rx : uart0_rx */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_i2c0_scl = 3,/*!< i2c0_scl : i2c0_scl */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_siob_proc_61 = 5,/*!< siob_proc_61 : siob_proc_61 */ + IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_Enum; + +/* ================================================= GPIO_QSPI_SD2_STATUS ================================================== */ +/* ================================================== GPIO_QSPI_SD2_CTRL =================================================== */ +/* ====================================== IO_QSPI GPIO_QSPI_SD2_CTRL IRQOVER [28..29] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD2_CTRL INOVER [16..17] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD2_CTRL OEOVER [14..15] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD2_CTRL OUTOVER [12..13] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_Enum; + +/* ======================================= IO_QSPI GPIO_QSPI_SD2_CTRL FUNCSEL [0..4] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_xip_sd2 = 0,/*!< xip_sd2 : xip_sd2 */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_uart0_cts = 2,/*!< uart0_cts : uart0_cts */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_i2c1_sda = 3,/*!< i2c1_sda : i2c1_sda */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_siob_proc_62 = 5,/*!< siob_proc_62 : siob_proc_62 */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_uart0_tx = 11,/*!< uart0_tx : uart0_tx */ + IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_Enum; + +/* ================================================= GPIO_QSPI_SD3_STATUS ================================================== */ +/* ================================================== GPIO_QSPI_SD3_CTRL =================================================== */ +/* ====================================== IO_QSPI GPIO_QSPI_SD3_CTRL IRQOVER [28..29] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD3_CTRL INOVER [16..17] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD3_CTRL OEOVER [14..15] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_Enum; + +/* ====================================== IO_QSPI GPIO_QSPI_SD3_CTRL OUTOVER [12..13] ====================================== */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_Enum; + +/* ======================================= IO_QSPI GPIO_QSPI_SD3_CTRL FUNCSEL [0..4] ======================================= */ +typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_xip_sd3 = 0,/*!< xip_sd3 : xip_sd3 */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_uart0_rts = 2,/*!< uart0_rts : uart0_rts */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_i2c1_scl = 3,/*!< i2c1_scl : i2c1_scl */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_siob_proc_63 = 5,/*!< siob_proc_63 : siob_proc_63 */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_uart0_rx = 11,/*!< uart0_rx : uart0_rx */ + IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_Enum; + +/* ================================================ IRQSUMMARY_PROC0_SECURE ================================================ */ +/* ============================================== IRQSUMMARY_PROC0_NONSECURE =============================================== */ +/* ================================================ IRQSUMMARY_PROC1_SECURE ================================================ */ +/* ============================================== IRQSUMMARY_PROC1_NONSECURE =============================================== */ +/* ============================================ IRQSUMMARY_DORMANT_WAKE_SECURE ============================================= */ +/* =========================================== IRQSUMMARY_DORMANT_WAKE_NONSECURE =========================================== */ +/* ========================================================= INTR ========================================================== */ +/* ====================================================== PROC0_INTE ======================================================= */ +/* ====================================================== PROC0_INTF ======================================================= */ +/* ====================================================== PROC0_INTS ======================================================= */ +/* ====================================================== PROC1_INTE ======================================================= */ +/* ====================================================== PROC1_INTF ======================================================= */ +/* ====================================================== PROC1_INTS ======================================================= */ +/* =================================================== DORMANT_WAKE_INTE =================================================== */ +/* =================================================== DORMANT_WAKE_INTF =================================================== */ +/* =================================================== DORMANT_WAKE_INTS =================================================== */ + + +/* =========================================================================================================================== */ +/* ================ IO_BANK0 ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== GPIO0_STATUS ====================================================== */ +/* ====================================================== GPIO0_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO0_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO0_CTRL_IRQOVER */ + IO_BANK0_GPIO0_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO0_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO0_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO0_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO0_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO0_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO0_CTRL_INOVER */ + IO_BANK0_GPIO0_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO0_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO0_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO0_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO0_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO0_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO0_CTRL_OEOVER */ + IO_BANK0_GPIO0_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO0_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO0_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO0_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO0_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO0_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO0_CTRL_OUTOVER */ + IO_BANK0_GPIO0_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO0_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO0_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO0_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO0_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO0_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO0_CTRL_FUNCSEL */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_jtag_tck = 0, /*!< jtag_tck : jtag_tck */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_pwm_a_0 = 4, /*!< pwm_a_0 : pwm_a_0 */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_siob_proc_0 = 5, /*!< siob_proc_0 : siob_proc_0 */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_pio0_0 = 6, /*!< pio0_0 : pio0_0 */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_pio1_0 = 7, /*!< pio1_0 : pio1_0 */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_pio2_0 = 8, /*!< pio2_0 : pio2_0 */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_xip_ss_n_1 = 9, /*!< xip_ss_n_1 : xip_ss_n_1 */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO0_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO0_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO1_STATUS ====================================================== */ +/* ====================================================== GPIO1_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO1_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO1_CTRL_IRQOVER */ + IO_BANK0_GPIO1_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO1_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO1_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO1_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO1_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO1_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO1_CTRL_INOVER */ + IO_BANK0_GPIO1_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO1_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO1_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO1_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO1_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO1_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO1_CTRL_OEOVER */ + IO_BANK0_GPIO1_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO1_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO1_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO1_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO1_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO1_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO1_CTRL_OUTOVER */ + IO_BANK0_GPIO1_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO1_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO1_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO1_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO1_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO1_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO1_CTRL_FUNCSEL */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_jtag_tms = 0, /*!< jtag_tms : jtag_tms */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_pwm_b_0 = 4, /*!< pwm_b_0 : pwm_b_0 */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_siob_proc_1 = 5, /*!< siob_proc_1 : siob_proc_1 */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_pio0_1 = 6, /*!< pio0_1 : pio0_1 */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_pio1_1 = 7, /*!< pio1_1 : pio1_1 */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_pio2_1 = 8, /*!< pio2_1 : pio2_1 */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_coresight_traceclk = 9,/*!< coresight_traceclk : coresight_traceclk */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO1_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO1_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO2_STATUS ====================================================== */ +/* ====================================================== GPIO2_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO2_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO2_CTRL_IRQOVER */ + IO_BANK0_GPIO2_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO2_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO2_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO2_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO2_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO2_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO2_CTRL_INOVER */ + IO_BANK0_GPIO2_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO2_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO2_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO2_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO2_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO2_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO2_CTRL_OEOVER */ + IO_BANK0_GPIO2_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO2_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO2_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO2_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO2_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO2_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO2_CTRL_OUTOVER */ + IO_BANK0_GPIO2_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO2_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO2_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO2_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO2_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO2_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO2_CTRL_FUNCSEL */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_jtag_tdi = 0, /*!< jtag_tdi : jtag_tdi */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_uart0_cts = 2, /*!< uart0_cts : uart0_cts */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_pwm_a_1 = 4, /*!< pwm_a_1 : pwm_a_1 */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_siob_proc_2 = 5, /*!< siob_proc_2 : siob_proc_2 */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_pio0_2 = 6, /*!< pio0_2 : pio0_2 */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_pio1_2 = 7, /*!< pio1_2 : pio1_2 */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_pio2_2 = 8, /*!< pio2_2 : pio2_2 */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_coresight_tracedata_0 = 9,/*!< coresight_tracedata_0 : coresight_tracedata_0 */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_uart0_tx = 11, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO2_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO2_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO3_STATUS ====================================================== */ +/* ====================================================== GPIO3_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO3_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO3_CTRL_IRQOVER */ + IO_BANK0_GPIO3_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO3_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO3_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO3_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO3_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO3_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO3_CTRL_INOVER */ + IO_BANK0_GPIO3_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO3_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO3_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO3_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO3_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO3_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO3_CTRL_OEOVER */ + IO_BANK0_GPIO3_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO3_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO3_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO3_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO3_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO3_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO3_CTRL_OUTOVER */ + IO_BANK0_GPIO3_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO3_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO3_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO3_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO3_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO3_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO3_CTRL_FUNCSEL */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_jtag_tdo = 0, /*!< jtag_tdo : jtag_tdo */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_uart0_rts = 2, /*!< uart0_rts : uart0_rts */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_pwm_b_1 = 4, /*!< pwm_b_1 : pwm_b_1 */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_siob_proc_3 = 5, /*!< siob_proc_3 : siob_proc_3 */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_pio0_3 = 6, /*!< pio0_3 : pio0_3 */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_pio1_3 = 7, /*!< pio1_3 : pio1_3 */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_pio2_3 = 8, /*!< pio2_3 : pio2_3 */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_coresight_tracedata_1 = 9,/*!< coresight_tracedata_1 : coresight_tracedata_1 */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_uart0_rx = 11, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO3_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO3_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO4_STATUS ====================================================== */ +/* ====================================================== GPIO4_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO4_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO4_CTRL_IRQOVER */ + IO_BANK0_GPIO4_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO4_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO4_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO4_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO4_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO4_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO4_CTRL_INOVER */ + IO_BANK0_GPIO4_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO4_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO4_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO4_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO4_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO4_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO4_CTRL_OEOVER */ + IO_BANK0_GPIO4_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO4_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO4_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO4_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO4_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO4_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO4_CTRL_OUTOVER */ + IO_BANK0_GPIO4_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO4_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO4_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO4_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO4_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO4_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO4_CTRL_FUNCSEL */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_pwm_a_2 = 4, /*!< pwm_a_2 : pwm_a_2 */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_siob_proc_4 = 5, /*!< siob_proc_4 : siob_proc_4 */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_pio0_4 = 6, /*!< pio0_4 : pio0_4 */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_pio1_4 = 7, /*!< pio1_4 : pio1_4 */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_pio2_4 = 8, /*!< pio2_4 : pio2_4 */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_coresight_tracedata_2 = 9,/*!< coresight_tracedata_2 : coresight_tracedata_2 */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO4_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO4_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO5_STATUS ====================================================== */ +/* ====================================================== GPIO5_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO5_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO5_CTRL_IRQOVER */ + IO_BANK0_GPIO5_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO5_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO5_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO5_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO5_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO5_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO5_CTRL_INOVER */ + IO_BANK0_GPIO5_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO5_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO5_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO5_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO5_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO5_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO5_CTRL_OEOVER */ + IO_BANK0_GPIO5_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO5_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO5_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO5_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO5_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO5_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO5_CTRL_OUTOVER */ + IO_BANK0_GPIO5_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO5_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO5_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO5_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO5_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO5_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO5_CTRL_FUNCSEL */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_pwm_b_2 = 4, /*!< pwm_b_2 : pwm_b_2 */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_siob_proc_5 = 5, /*!< siob_proc_5 : siob_proc_5 */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_pio0_5 = 6, /*!< pio0_5 : pio0_5 */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_pio1_5 = 7, /*!< pio1_5 : pio1_5 */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_pio2_5 = 8, /*!< pio2_5 : pio2_5 */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_coresight_tracedata_3 = 9,/*!< coresight_tracedata_3 : coresight_tracedata_3 */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO5_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO5_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO6_STATUS ====================================================== */ +/* ====================================================== GPIO6_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO6_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO6_CTRL_IRQOVER */ + IO_BANK0_GPIO6_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO6_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO6_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO6_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO6_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO6_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO6_CTRL_INOVER */ + IO_BANK0_GPIO6_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO6_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO6_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO6_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO6_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO6_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO6_CTRL_OEOVER */ + IO_BANK0_GPIO6_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO6_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO6_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO6_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO6_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO6_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO6_CTRL_OUTOVER */ + IO_BANK0_GPIO6_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO6_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO6_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO6_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO6_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO6_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO6_CTRL_FUNCSEL */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_pwm_a_3 = 4, /*!< pwm_a_3 : pwm_a_3 */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_siob_proc_6 = 5, /*!< siob_proc_6 : siob_proc_6 */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_pio0_6 = 6, /*!< pio0_6 : pio0_6 */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_pio1_6 = 7, /*!< pio1_6 : pio1_6 */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_pio2_6 = 8, /*!< pio2_6 : pio2_6 */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_uart1_tx = 11, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO6_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO6_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO7_STATUS ====================================================== */ +/* ====================================================== GPIO7_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO7_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO7_CTRL_IRQOVER */ + IO_BANK0_GPIO7_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO7_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO7_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO7_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO7_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO7_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO7_CTRL_INOVER */ + IO_BANK0_GPIO7_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO7_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO7_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO7_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO7_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO7_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO7_CTRL_OEOVER */ + IO_BANK0_GPIO7_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO7_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO7_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO7_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO7_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO7_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO7_CTRL_OUTOVER */ + IO_BANK0_GPIO7_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO7_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO7_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO7_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO7_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO7_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO7_CTRL_FUNCSEL */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_pwm_b_3 = 4, /*!< pwm_b_3 : pwm_b_3 */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_siob_proc_7 = 5, /*!< siob_proc_7 : siob_proc_7 */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_pio0_7 = 6, /*!< pio0_7 : pio0_7 */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_pio1_7 = 7, /*!< pio1_7 : pio1_7 */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_pio2_7 = 8, /*!< pio2_7 : pio2_7 */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_uart1_rx = 11, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO7_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO7_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO8_STATUS ====================================================== */ +/* ====================================================== GPIO8_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO8_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO8_CTRL_IRQOVER */ + IO_BANK0_GPIO8_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO8_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO8_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO8_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO8_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO8_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO8_CTRL_INOVER */ + IO_BANK0_GPIO8_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO8_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO8_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO8_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO8_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO8_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO8_CTRL_OEOVER */ + IO_BANK0_GPIO8_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO8_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO8_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO8_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO8_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO8_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO8_CTRL_OUTOVER */ + IO_BANK0_GPIO8_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO8_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO8_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO8_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO8_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO8_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO8_CTRL_FUNCSEL */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_pwm_a_4 = 4, /*!< pwm_a_4 : pwm_a_4 */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_siob_proc_8 = 5, /*!< siob_proc_8 : siob_proc_8 */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_pio0_8 = 6, /*!< pio0_8 : pio0_8 */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_pio1_8 = 7, /*!< pio1_8 : pio1_8 */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_pio2_8 = 8, /*!< pio2_8 : pio2_8 */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_xip_ss_n_1 = 9, /*!< xip_ss_n_1 : xip_ss_n_1 */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO8_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO8_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO9_STATUS ====================================================== */ +/* ====================================================== GPIO9_CTRL ======================================================= */ +/* ========================================= IO_BANK0 GPIO9_CTRL IRQOVER [28..29] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO9_CTRL_IRQOVER */ + IO_BANK0_GPIO9_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO9_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO9_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO9_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO9_CTRL_IRQOVER_Enum; + +/* ========================================== IO_BANK0 GPIO9_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO9_CTRL_INOVER */ + IO_BANK0_GPIO9_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO9_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO9_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO9_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO9_CTRL_INOVER_Enum; + +/* ========================================== IO_BANK0 GPIO9_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO9_CTRL_OEOVER */ + IO_BANK0_GPIO9_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO9_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO9_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO9_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO9_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO9_CTRL OUTOVER [12..13] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO9_CTRL_OUTOVER */ + IO_BANK0_GPIO9_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO9_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO9_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO9_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO9_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO9_CTRL FUNCSEL [0..4] =========================================== */ +typedef enum { /*!< IO_BANK0_GPIO9_CTRL_FUNCSEL */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_pwm_b_4 = 4, /*!< pwm_b_4 : pwm_b_4 */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_siob_proc_9 = 5, /*!< siob_proc_9 : siob_proc_9 */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_pio0_9 = 6, /*!< pio0_9 : pio0_9 */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_pio1_9 = 7, /*!< pio1_9 : pio1_9 */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_pio2_9 = 8, /*!< pio2_9 : pio2_9 */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO9_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO9_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO10_STATUS ===================================================== */ +/* ====================================================== GPIO10_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO10_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO10_CTRL_IRQOVER */ + IO_BANK0_GPIO10_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO10_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO10_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO10_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO10_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO10_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO10_CTRL_INOVER */ + IO_BANK0_GPIO10_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO10_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO10_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO10_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO10_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO10_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO10_CTRL_OEOVER */ + IO_BANK0_GPIO10_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO10_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO10_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO10_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO10_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO10_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO10_CTRL_OUTOVER */ + IO_BANK0_GPIO10_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO10_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO10_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO10_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO10_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO10_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO10_CTRL_FUNCSEL */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_spi1_sclk = 1, /*!< spi1_sclk : spi1_sclk */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_pwm_a_5 = 4, /*!< pwm_a_5 : pwm_a_5 */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_siob_proc_10 = 5,/*!< siob_proc_10 : siob_proc_10 */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_pio0_10 = 6, /*!< pio0_10 : pio0_10 */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_pio1_10 = 7, /*!< pio1_10 : pio1_10 */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_pio2_10 = 8, /*!< pio2_10 : pio2_10 */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_uart1_tx = 11, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO10_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO10_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO11_STATUS ===================================================== */ +/* ====================================================== GPIO11_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO11_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO11_CTRL_IRQOVER */ + IO_BANK0_GPIO11_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO11_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO11_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO11_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO11_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO11_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO11_CTRL_INOVER */ + IO_BANK0_GPIO11_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO11_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO11_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO11_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO11_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO11_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO11_CTRL_OEOVER */ + IO_BANK0_GPIO11_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO11_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO11_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO11_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO11_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO11_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO11_CTRL_OUTOVER */ + IO_BANK0_GPIO11_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO11_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO11_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO11_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO11_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO11_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO11_CTRL_FUNCSEL */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_spi1_tx = 1, /*!< spi1_tx : spi1_tx */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_pwm_b_5 = 4, /*!< pwm_b_5 : pwm_b_5 */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_siob_proc_11 = 5,/*!< siob_proc_11 : siob_proc_11 */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_pio0_11 = 6, /*!< pio0_11 : pio0_11 */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_pio1_11 = 7, /*!< pio1_11 : pio1_11 */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_pio2_11 = 8, /*!< pio2_11 : pio2_11 */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_uart1_rx = 11, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO11_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO11_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO12_STATUS ===================================================== */ +/* ====================================================== GPIO12_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO12_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO12_CTRL_IRQOVER */ + IO_BANK0_GPIO12_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO12_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO12_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO12_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO12_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO12_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO12_CTRL_INOVER */ + IO_BANK0_GPIO12_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO12_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO12_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO12_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO12_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO12_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO12_CTRL_OEOVER */ + IO_BANK0_GPIO12_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO12_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO12_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO12_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO12_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO12_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO12_CTRL_OUTOVER */ + IO_BANK0_GPIO12_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO12_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO12_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO12_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO12_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO12_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO12_CTRL_FUNCSEL */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_hstx_0 = 0, /*!< hstx_0 : hstx_0 */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_pwm_a_6 = 4, /*!< pwm_a_6 : pwm_a_6 */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_siob_proc_12 = 5,/*!< siob_proc_12 : siob_proc_12 */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_pio0_12 = 6, /*!< pio0_12 : pio0_12 */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_pio1_12 = 7, /*!< pio1_12 : pio1_12 */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_pio2_12 = 8, /*!< pio2_12 : pio2_12 */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_clocks_gpin_0 = 9,/*!< clocks_gpin_0 : clocks_gpin_0 */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO12_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO12_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO13_STATUS ===================================================== */ +/* ====================================================== GPIO13_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO13_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO13_CTRL_IRQOVER */ + IO_BANK0_GPIO13_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO13_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO13_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO13_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO13_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO13_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO13_CTRL_INOVER */ + IO_BANK0_GPIO13_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO13_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO13_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO13_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO13_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO13_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO13_CTRL_OEOVER */ + IO_BANK0_GPIO13_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO13_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO13_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO13_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO13_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO13_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO13_CTRL_OUTOVER */ + IO_BANK0_GPIO13_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO13_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO13_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO13_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO13_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO13_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO13_CTRL_FUNCSEL */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_hstx_1 = 0, /*!< hstx_1 : hstx_1 */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_pwm_b_6 = 4, /*!< pwm_b_6 : pwm_b_6 */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_siob_proc_13 = 5,/*!< siob_proc_13 : siob_proc_13 */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_pio0_13 = 6, /*!< pio0_13 : pio0_13 */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_pio1_13 = 7, /*!< pio1_13 : pio1_13 */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_pio2_13 = 8, /*!< pio2_13 : pio2_13 */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_clocks_gpout_0 = 9,/*!< clocks_gpout_0 : clocks_gpout_0 */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO13_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO13_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO14_STATUS ===================================================== */ +/* ====================================================== GPIO14_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO14_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO14_CTRL_IRQOVER */ + IO_BANK0_GPIO14_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO14_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO14_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO14_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO14_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO14_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO14_CTRL_INOVER */ + IO_BANK0_GPIO14_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO14_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO14_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO14_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO14_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO14_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO14_CTRL_OEOVER */ + IO_BANK0_GPIO14_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO14_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO14_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO14_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO14_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO14_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO14_CTRL_OUTOVER */ + IO_BANK0_GPIO14_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO14_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO14_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO14_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO14_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO14_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO14_CTRL_FUNCSEL */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_hstx_2 = 0, /*!< hstx_2 : hstx_2 */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_spi1_sclk = 1, /*!< spi1_sclk : spi1_sclk */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_uart0_cts = 2, /*!< uart0_cts : uart0_cts */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_pwm_a_7 = 4, /*!< pwm_a_7 : pwm_a_7 */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_siob_proc_14 = 5,/*!< siob_proc_14 : siob_proc_14 */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_pio0_14 = 6, /*!< pio0_14 : pio0_14 */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_pio1_14 = 7, /*!< pio1_14 : pio1_14 */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_pio2_14 = 8, /*!< pio2_14 : pio2_14 */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_clocks_gpin_1 = 9,/*!< clocks_gpin_1 : clocks_gpin_1 */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_uart0_tx = 11, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO14_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO14_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO15_STATUS ===================================================== */ +/* ====================================================== GPIO15_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO15_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO15_CTRL_IRQOVER */ + IO_BANK0_GPIO15_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO15_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO15_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO15_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO15_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO15_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO15_CTRL_INOVER */ + IO_BANK0_GPIO15_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO15_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO15_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO15_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO15_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO15_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO15_CTRL_OEOVER */ + IO_BANK0_GPIO15_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO15_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO15_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO15_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO15_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO15_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO15_CTRL_OUTOVER */ + IO_BANK0_GPIO15_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO15_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO15_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO15_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO15_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO15_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO15_CTRL_FUNCSEL */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_hstx_3 = 0, /*!< hstx_3 : hstx_3 */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_spi1_tx = 1, /*!< spi1_tx : spi1_tx */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_uart0_rts = 2, /*!< uart0_rts : uart0_rts */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_pwm_b_7 = 4, /*!< pwm_b_7 : pwm_b_7 */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_siob_proc_15 = 5,/*!< siob_proc_15 : siob_proc_15 */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_pio0_15 = 6, /*!< pio0_15 : pio0_15 */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_pio1_15 = 7, /*!< pio1_15 : pio1_15 */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_pio2_15 = 8, /*!< pio2_15 : pio2_15 */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_clocks_gpout_1 = 9,/*!< clocks_gpout_1 : clocks_gpout_1 */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_uart0_rx = 11, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO15_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO15_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO16_STATUS ===================================================== */ +/* ====================================================== GPIO16_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO16_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO16_CTRL_IRQOVER */ + IO_BANK0_GPIO16_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO16_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO16_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO16_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO16_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO16_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO16_CTRL_INOVER */ + IO_BANK0_GPIO16_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO16_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO16_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO16_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO16_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO16_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO16_CTRL_OEOVER */ + IO_BANK0_GPIO16_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO16_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO16_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO16_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO16_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO16_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO16_CTRL_OUTOVER */ + IO_BANK0_GPIO16_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO16_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO16_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO16_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO16_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO16_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO16_CTRL_FUNCSEL */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_hstx_4 = 0, /*!< hstx_4 : hstx_4 */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_pwm_a_0 = 4, /*!< pwm_a_0 : pwm_a_0 */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_siob_proc_16 = 5,/*!< siob_proc_16 : siob_proc_16 */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_pio0_16 = 6, /*!< pio0_16 : pio0_16 */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_pio1_16 = 7, /*!< pio1_16 : pio1_16 */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_pio2_16 = 8, /*!< pio2_16 : pio2_16 */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO16_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO16_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO17_STATUS ===================================================== */ +/* ====================================================== GPIO17_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO17_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO17_CTRL_IRQOVER */ + IO_BANK0_GPIO17_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO17_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO17_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO17_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO17_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO17_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO17_CTRL_INOVER */ + IO_BANK0_GPIO17_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO17_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO17_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO17_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO17_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO17_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO17_CTRL_OEOVER */ + IO_BANK0_GPIO17_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO17_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO17_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO17_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO17_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO17_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO17_CTRL_OUTOVER */ + IO_BANK0_GPIO17_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO17_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO17_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO17_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO17_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO17_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO17_CTRL_FUNCSEL */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_hstx_5 = 0, /*!< hstx_5 : hstx_5 */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_pwm_b_0 = 4, /*!< pwm_b_0 : pwm_b_0 */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_siob_proc_17 = 5,/*!< siob_proc_17 : siob_proc_17 */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_pio0_17 = 6, /*!< pio0_17 : pio0_17 */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_pio1_17 = 7, /*!< pio1_17 : pio1_17 */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_pio2_17 = 8, /*!< pio2_17 : pio2_17 */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO17_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO17_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO18_STATUS ===================================================== */ +/* ====================================================== GPIO18_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO18_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO18_CTRL_IRQOVER */ + IO_BANK0_GPIO18_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO18_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO18_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO18_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO18_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO18_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO18_CTRL_INOVER */ + IO_BANK0_GPIO18_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO18_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO18_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO18_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO18_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO18_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO18_CTRL_OEOVER */ + IO_BANK0_GPIO18_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO18_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO18_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO18_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO18_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO18_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO18_CTRL_OUTOVER */ + IO_BANK0_GPIO18_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO18_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO18_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO18_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO18_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO18_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO18_CTRL_FUNCSEL */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_hstx_6 = 0, /*!< hstx_6 : hstx_6 */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_uart0_cts = 2, /*!< uart0_cts : uart0_cts */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_pwm_a_1 = 4, /*!< pwm_a_1 : pwm_a_1 */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_siob_proc_18 = 5,/*!< siob_proc_18 : siob_proc_18 */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_pio0_18 = 6, /*!< pio0_18 : pio0_18 */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_pio1_18 = 7, /*!< pio1_18 : pio1_18 */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_pio2_18 = 8, /*!< pio2_18 : pio2_18 */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_uart0_tx = 11, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO18_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO18_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO19_STATUS ===================================================== */ +/* ====================================================== GPIO19_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO19_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO19_CTRL_IRQOVER */ + IO_BANK0_GPIO19_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO19_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO19_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO19_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO19_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO19_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO19_CTRL_INOVER */ + IO_BANK0_GPIO19_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO19_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO19_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO19_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO19_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO19_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO19_CTRL_OEOVER */ + IO_BANK0_GPIO19_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO19_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO19_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO19_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO19_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO19_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO19_CTRL_OUTOVER */ + IO_BANK0_GPIO19_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO19_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO19_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO19_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO19_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO19_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO19_CTRL_FUNCSEL */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_hstx_7 = 0, /*!< hstx_7 : hstx_7 */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_uart0_rts = 2, /*!< uart0_rts : uart0_rts */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_pwm_b_1 = 4, /*!< pwm_b_1 : pwm_b_1 */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_siob_proc_19 = 5,/*!< siob_proc_19 : siob_proc_19 */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_pio0_19 = 6, /*!< pio0_19 : pio0_19 */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_pio1_19 = 7, /*!< pio1_19 : pio1_19 */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_pio2_19 = 8, /*!< pio2_19 : pio2_19 */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_xip_ss_n_1 = 9, /*!< xip_ss_n_1 : xip_ss_n_1 */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_uart0_rx = 11, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO19_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO19_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO20_STATUS ===================================================== */ +/* ====================================================== GPIO20_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO20_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO20_CTRL_IRQOVER */ + IO_BANK0_GPIO20_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO20_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO20_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO20_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO20_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO20_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO20_CTRL_INOVER */ + IO_BANK0_GPIO20_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO20_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO20_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO20_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO20_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO20_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO20_CTRL_OEOVER */ + IO_BANK0_GPIO20_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO20_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO20_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO20_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO20_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO20_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO20_CTRL_OUTOVER */ + IO_BANK0_GPIO20_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO20_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO20_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO20_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO20_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO20_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO20_CTRL_FUNCSEL */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_pwm_a_2 = 4, /*!< pwm_a_2 : pwm_a_2 */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_siob_proc_20 = 5,/*!< siob_proc_20 : siob_proc_20 */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_pio0_20 = 6, /*!< pio0_20 : pio0_20 */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_pio1_20 = 7, /*!< pio1_20 : pio1_20 */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_pio2_20 = 8, /*!< pio2_20 : pio2_20 */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_clocks_gpin_0 = 9,/*!< clocks_gpin_0 : clocks_gpin_0 */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO20_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO20_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO21_STATUS ===================================================== */ +/* ====================================================== GPIO21_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO21_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO21_CTRL_IRQOVER */ + IO_BANK0_GPIO21_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO21_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO21_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO21_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO21_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO21_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO21_CTRL_INOVER */ + IO_BANK0_GPIO21_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO21_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO21_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO21_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO21_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO21_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO21_CTRL_OEOVER */ + IO_BANK0_GPIO21_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO21_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO21_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO21_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO21_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO21_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO21_CTRL_OUTOVER */ + IO_BANK0_GPIO21_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO21_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO21_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO21_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO21_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO21_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO21_CTRL_FUNCSEL */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_pwm_b_2 = 4, /*!< pwm_b_2 : pwm_b_2 */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_siob_proc_21 = 5,/*!< siob_proc_21 : siob_proc_21 */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_pio0_21 = 6, /*!< pio0_21 : pio0_21 */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_pio1_21 = 7, /*!< pio1_21 : pio1_21 */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_pio2_21 = 8, /*!< pio2_21 : pio2_21 */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_clocks_gpout_0 = 9,/*!< clocks_gpout_0 : clocks_gpout_0 */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO21_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO21_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO22_STATUS ===================================================== */ +/* ====================================================== GPIO22_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO22_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO22_CTRL_IRQOVER */ + IO_BANK0_GPIO22_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO22_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO22_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO22_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO22_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO22_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO22_CTRL_INOVER */ + IO_BANK0_GPIO22_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO22_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO22_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO22_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO22_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO22_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO22_CTRL_OEOVER */ + IO_BANK0_GPIO22_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO22_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO22_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO22_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO22_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO22_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO22_CTRL_OUTOVER */ + IO_BANK0_GPIO22_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO22_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO22_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO22_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO22_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO22_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO22_CTRL_FUNCSEL */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_pwm_a_3 = 4, /*!< pwm_a_3 : pwm_a_3 */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_siob_proc_22 = 5,/*!< siob_proc_22 : siob_proc_22 */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_pio0_22 = 6, /*!< pio0_22 : pio0_22 */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_pio1_22 = 7, /*!< pio1_22 : pio1_22 */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_pio2_22 = 8, /*!< pio2_22 : pio2_22 */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_clocks_gpin_1 = 9,/*!< clocks_gpin_1 : clocks_gpin_1 */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_uart1_tx = 11, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO22_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO22_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO23_STATUS ===================================================== */ +/* ====================================================== GPIO23_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO23_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO23_CTRL_IRQOVER */ + IO_BANK0_GPIO23_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO23_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO23_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO23_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO23_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO23_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO23_CTRL_INOVER */ + IO_BANK0_GPIO23_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO23_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO23_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO23_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO23_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO23_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO23_CTRL_OEOVER */ + IO_BANK0_GPIO23_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO23_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO23_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO23_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO23_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO23_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO23_CTRL_OUTOVER */ + IO_BANK0_GPIO23_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO23_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO23_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO23_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO23_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO23_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO23_CTRL_FUNCSEL */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_pwm_b_3 = 4, /*!< pwm_b_3 : pwm_b_3 */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_siob_proc_23 = 5,/*!< siob_proc_23 : siob_proc_23 */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_pio0_23 = 6, /*!< pio0_23 : pio0_23 */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_pio1_23 = 7, /*!< pio1_23 : pio1_23 */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_pio2_23 = 8, /*!< pio2_23 : pio2_23 */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_clocks_gpout_1 = 9,/*!< clocks_gpout_1 : clocks_gpout_1 */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_uart1_rx = 11, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO23_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO23_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO24_STATUS ===================================================== */ +/* ====================================================== GPIO24_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO24_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO24_CTRL_IRQOVER */ + IO_BANK0_GPIO24_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO24_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO24_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO24_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO24_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO24_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO24_CTRL_INOVER */ + IO_BANK0_GPIO24_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO24_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO24_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO24_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO24_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO24_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO24_CTRL_OEOVER */ + IO_BANK0_GPIO24_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO24_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO24_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO24_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO24_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO24_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO24_CTRL_OUTOVER */ + IO_BANK0_GPIO24_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO24_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO24_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO24_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO24_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO24_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO24_CTRL_FUNCSEL */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_pwm_a_4 = 4, /*!< pwm_a_4 : pwm_a_4 */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_siob_proc_24 = 5,/*!< siob_proc_24 : siob_proc_24 */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_pio0_24 = 6, /*!< pio0_24 : pio0_24 */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_pio1_24 = 7, /*!< pio1_24 : pio1_24 */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_pio2_24 = 8, /*!< pio2_24 : pio2_24 */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_clocks_gpout_2 = 9,/*!< clocks_gpout_2 : clocks_gpout_2 */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO24_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO24_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO25_STATUS ===================================================== */ +/* ====================================================== GPIO25_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO25_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO25_CTRL_IRQOVER */ + IO_BANK0_GPIO25_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO25_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO25_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO25_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO25_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO25_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO25_CTRL_INOVER */ + IO_BANK0_GPIO25_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO25_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO25_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO25_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO25_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO25_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO25_CTRL_OEOVER */ + IO_BANK0_GPIO25_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO25_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO25_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO25_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO25_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO25_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO25_CTRL_OUTOVER */ + IO_BANK0_GPIO25_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO25_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO25_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO25_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO25_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO25_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO25_CTRL_FUNCSEL */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_pwm_b_4 = 4, /*!< pwm_b_4 : pwm_b_4 */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_siob_proc_25 = 5,/*!< siob_proc_25 : siob_proc_25 */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_pio0_25 = 6, /*!< pio0_25 : pio0_25 */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_pio1_25 = 7, /*!< pio1_25 : pio1_25 */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_pio2_25 = 8, /*!< pio2_25 : pio2_25 */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_clocks_gpout_3 = 9,/*!< clocks_gpout_3 : clocks_gpout_3 */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO25_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO25_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO26_STATUS ===================================================== */ +/* ====================================================== GPIO26_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO26_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO26_CTRL_IRQOVER */ + IO_BANK0_GPIO26_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO26_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO26_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO26_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO26_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO26_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO26_CTRL_INOVER */ + IO_BANK0_GPIO26_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO26_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO26_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO26_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO26_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO26_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO26_CTRL_OEOVER */ + IO_BANK0_GPIO26_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO26_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO26_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO26_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO26_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO26_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO26_CTRL_OUTOVER */ + IO_BANK0_GPIO26_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO26_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO26_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO26_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO26_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO26_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO26_CTRL_FUNCSEL */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_spi1_sclk = 1, /*!< spi1_sclk : spi1_sclk */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_pwm_a_5 = 4, /*!< pwm_a_5 : pwm_a_5 */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_siob_proc_26 = 5,/*!< siob_proc_26 : siob_proc_26 */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_pio0_26 = 6, /*!< pio0_26 : pio0_26 */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_pio1_26 = 7, /*!< pio1_26 : pio1_26 */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_pio2_26 = 8, /*!< pio2_26 : pio2_26 */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_uart1_tx = 11, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO26_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO26_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO27_STATUS ===================================================== */ +/* ====================================================== GPIO27_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO27_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO27_CTRL_IRQOVER */ + IO_BANK0_GPIO27_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO27_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO27_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO27_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO27_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO27_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO27_CTRL_INOVER */ + IO_BANK0_GPIO27_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO27_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO27_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO27_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO27_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO27_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO27_CTRL_OEOVER */ + IO_BANK0_GPIO27_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO27_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO27_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO27_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO27_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO27_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO27_CTRL_OUTOVER */ + IO_BANK0_GPIO27_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO27_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO27_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO27_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO27_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO27_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO27_CTRL_FUNCSEL */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_spi1_tx = 1, /*!< spi1_tx : spi1_tx */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_pwm_b_5 = 4, /*!< pwm_b_5 : pwm_b_5 */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_siob_proc_27 = 5,/*!< siob_proc_27 : siob_proc_27 */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_pio0_27 = 6, /*!< pio0_27 : pio0_27 */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_pio1_27 = 7, /*!< pio1_27 : pio1_27 */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_pio2_27 = 8, /*!< pio2_27 : pio2_27 */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_uart1_rx = 11, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO27_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO27_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO28_STATUS ===================================================== */ +/* ====================================================== GPIO28_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO28_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO28_CTRL_IRQOVER */ + IO_BANK0_GPIO28_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO28_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO28_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO28_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO28_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO28_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO28_CTRL_INOVER */ + IO_BANK0_GPIO28_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO28_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO28_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO28_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO28_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO28_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO28_CTRL_OEOVER */ + IO_BANK0_GPIO28_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO28_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO28_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO28_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO28_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO28_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO28_CTRL_OUTOVER */ + IO_BANK0_GPIO28_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO28_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO28_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO28_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO28_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO28_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO28_CTRL_FUNCSEL */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_pwm_a_6 = 4, /*!< pwm_a_6 : pwm_a_6 */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_siob_proc_28 = 5,/*!< siob_proc_28 : siob_proc_28 */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_pio0_28 = 6, /*!< pio0_28 : pio0_28 */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_pio1_28 = 7, /*!< pio1_28 : pio1_28 */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_pio2_28 = 8, /*!< pio2_28 : pio2_28 */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO28_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO28_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO29_STATUS ===================================================== */ +/* ====================================================== GPIO29_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO29_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO29_CTRL_IRQOVER */ + IO_BANK0_GPIO29_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO29_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO29_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO29_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO29_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO29_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO29_CTRL_INOVER */ + IO_BANK0_GPIO29_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO29_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO29_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO29_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO29_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO29_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO29_CTRL_OEOVER */ + IO_BANK0_GPIO29_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO29_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO29_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO29_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO29_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO29_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO29_CTRL_OUTOVER */ + IO_BANK0_GPIO29_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO29_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO29_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO29_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO29_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO29_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO29_CTRL_FUNCSEL */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_pwm_b_6 = 4, /*!< pwm_b_6 : pwm_b_6 */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_siob_proc_29 = 5,/*!< siob_proc_29 : siob_proc_29 */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_pio0_29 = 6, /*!< pio0_29 : pio0_29 */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_pio1_29 = 7, /*!< pio1_29 : pio1_29 */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_pio2_29 = 8, /*!< pio2_29 : pio2_29 */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO29_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO29_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO30_STATUS ===================================================== */ +/* ====================================================== GPIO30_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO30_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO30_CTRL_IRQOVER */ + IO_BANK0_GPIO30_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO30_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO30_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO30_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO30_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO30_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO30_CTRL_INOVER */ + IO_BANK0_GPIO30_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO30_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO30_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO30_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO30_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO30_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO30_CTRL_OEOVER */ + IO_BANK0_GPIO30_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO30_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO30_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO30_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO30_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO30_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO30_CTRL_OUTOVER */ + IO_BANK0_GPIO30_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO30_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO30_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO30_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO30_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO30_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO30_CTRL_FUNCSEL */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_spi1_sclk = 1, /*!< spi1_sclk : spi1_sclk */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_uart0_cts = 2, /*!< uart0_cts : uart0_cts */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_pwm_a_7 = 4, /*!< pwm_a_7 : pwm_a_7 */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_siob_proc_30 = 5,/*!< siob_proc_30 : siob_proc_30 */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_pio0_30 = 6, /*!< pio0_30 : pio0_30 */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_pio1_30 = 7, /*!< pio1_30 : pio1_30 */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_pio2_30 = 8, /*!< pio2_30 : pio2_30 */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_uart0_tx = 11, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO30_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO30_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO31_STATUS ===================================================== */ +/* ====================================================== GPIO31_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO31_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO31_CTRL_IRQOVER */ + IO_BANK0_GPIO31_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO31_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO31_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO31_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO31_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO31_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO31_CTRL_INOVER */ + IO_BANK0_GPIO31_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO31_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO31_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO31_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO31_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO31_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO31_CTRL_OEOVER */ + IO_BANK0_GPIO31_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO31_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO31_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO31_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO31_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO31_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO31_CTRL_OUTOVER */ + IO_BANK0_GPIO31_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO31_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO31_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO31_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO31_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO31_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO31_CTRL_FUNCSEL */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_spi1_tx = 1, /*!< spi1_tx : spi1_tx */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_uart0_rts = 2, /*!< uart0_rts : uart0_rts */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_pwm_b_7 = 4, /*!< pwm_b_7 : pwm_b_7 */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_siob_proc_31 = 5,/*!< siob_proc_31 : siob_proc_31 */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_pio0_31 = 6, /*!< pio0_31 : pio0_31 */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_pio1_31 = 7, /*!< pio1_31 : pio1_31 */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_pio2_31 = 8, /*!< pio2_31 : pio2_31 */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_uart0_rx = 11, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO31_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO31_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO32_STATUS ===================================================== */ +/* ====================================================== GPIO32_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO32_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO32_CTRL_IRQOVER */ + IO_BANK0_GPIO32_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO32_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO32_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO32_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO32_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO32_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO32_CTRL_INOVER */ + IO_BANK0_GPIO32_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO32_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO32_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO32_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO32_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO32_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO32_CTRL_OEOVER */ + IO_BANK0_GPIO32_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO32_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO32_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO32_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO32_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO32_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO32_CTRL_OUTOVER */ + IO_BANK0_GPIO32_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO32_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO32_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO32_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO32_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO32_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO32_CTRL_FUNCSEL */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_pwm_a_8 = 4, /*!< pwm_a_8 : pwm_a_8 */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_siob_proc_32 = 5,/*!< siob_proc_32 : siob_proc_32 */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_pio0_32 = 6, /*!< pio0_32 : pio0_32 */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_pio1_32 = 7, /*!< pio1_32 : pio1_32 */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_pio2_32 = 8, /*!< pio2_32 : pio2_32 */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO32_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO32_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO33_STATUS ===================================================== */ +/* ====================================================== GPIO33_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO33_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO33_CTRL_IRQOVER */ + IO_BANK0_GPIO33_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO33_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO33_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO33_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO33_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO33_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO33_CTRL_INOVER */ + IO_BANK0_GPIO33_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO33_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO33_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO33_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO33_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO33_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO33_CTRL_OEOVER */ + IO_BANK0_GPIO33_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO33_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO33_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO33_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO33_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO33_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO33_CTRL_OUTOVER */ + IO_BANK0_GPIO33_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO33_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO33_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO33_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO33_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO33_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO33_CTRL_FUNCSEL */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_pwm_b_8 = 4, /*!< pwm_b_8 : pwm_b_8 */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_siob_proc_33 = 5,/*!< siob_proc_33 : siob_proc_33 */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_pio0_33 = 6, /*!< pio0_33 : pio0_33 */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_pio1_33 = 7, /*!< pio1_33 : pio1_33 */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_pio2_33 = 8, /*!< pio2_33 : pio2_33 */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO33_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO33_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO34_STATUS ===================================================== */ +/* ====================================================== GPIO34_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO34_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO34_CTRL_IRQOVER */ + IO_BANK0_GPIO34_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO34_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO34_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO34_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO34_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO34_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO34_CTRL_INOVER */ + IO_BANK0_GPIO34_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO34_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO34_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO34_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO34_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO34_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO34_CTRL_OEOVER */ + IO_BANK0_GPIO34_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO34_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO34_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO34_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO34_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO34_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO34_CTRL_OUTOVER */ + IO_BANK0_GPIO34_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO34_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO34_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO34_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO34_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO34_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO34_CTRL_FUNCSEL */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_uart0_cts = 2, /*!< uart0_cts : uart0_cts */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_pwm_a_9 = 4, /*!< pwm_a_9 : pwm_a_9 */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_siob_proc_34 = 5,/*!< siob_proc_34 : siob_proc_34 */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_pio0_34 = 6, /*!< pio0_34 : pio0_34 */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_pio1_34 = 7, /*!< pio1_34 : pio1_34 */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_pio2_34 = 8, /*!< pio2_34 : pio2_34 */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_uart0_tx = 11, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO34_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO34_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO35_STATUS ===================================================== */ +/* ====================================================== GPIO35_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO35_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO35_CTRL_IRQOVER */ + IO_BANK0_GPIO35_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO35_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO35_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO35_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO35_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO35_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO35_CTRL_INOVER */ + IO_BANK0_GPIO35_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO35_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO35_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO35_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO35_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO35_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO35_CTRL_OEOVER */ + IO_BANK0_GPIO35_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO35_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO35_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO35_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO35_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO35_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO35_CTRL_OUTOVER */ + IO_BANK0_GPIO35_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO35_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO35_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO35_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO35_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO35_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO35_CTRL_FUNCSEL */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_uart0_rts = 2, /*!< uart0_rts : uart0_rts */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_pwm_b_9 = 4, /*!< pwm_b_9 : pwm_b_9 */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_siob_proc_35 = 5,/*!< siob_proc_35 : siob_proc_35 */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_pio0_35 = 6, /*!< pio0_35 : pio0_35 */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_pio1_35 = 7, /*!< pio1_35 : pio1_35 */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_pio2_35 = 8, /*!< pio2_35 : pio2_35 */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_uart0_rx = 11, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO35_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO35_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO36_STATUS ===================================================== */ +/* ====================================================== GPIO36_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO36_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO36_CTRL_IRQOVER */ + IO_BANK0_GPIO36_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO36_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO36_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO36_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO36_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO36_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO36_CTRL_INOVER */ + IO_BANK0_GPIO36_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO36_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO36_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO36_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO36_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO36_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO36_CTRL_OEOVER */ + IO_BANK0_GPIO36_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO36_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO36_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO36_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO36_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO36_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO36_CTRL_OUTOVER */ + IO_BANK0_GPIO36_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO36_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO36_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO36_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO36_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO36_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO36_CTRL_FUNCSEL */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_pwm_a_10 = 4, /*!< pwm_a_10 : pwm_a_10 */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_siob_proc_36 = 5,/*!< siob_proc_36 : siob_proc_36 */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_pio0_36 = 6, /*!< pio0_36 : pio0_36 */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_pio1_36 = 7, /*!< pio1_36 : pio1_36 */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_pio2_36 = 8, /*!< pio2_36 : pio2_36 */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO36_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO36_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO37_STATUS ===================================================== */ +/* ====================================================== GPIO37_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO37_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO37_CTRL_IRQOVER */ + IO_BANK0_GPIO37_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO37_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO37_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO37_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO37_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO37_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO37_CTRL_INOVER */ + IO_BANK0_GPIO37_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO37_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO37_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO37_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO37_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO37_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO37_CTRL_OEOVER */ + IO_BANK0_GPIO37_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO37_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO37_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO37_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO37_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO37_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO37_CTRL_OUTOVER */ + IO_BANK0_GPIO37_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO37_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO37_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO37_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO37_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO37_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO37_CTRL_FUNCSEL */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_pwm_b_10 = 4, /*!< pwm_b_10 : pwm_b_10 */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_siob_proc_37 = 5,/*!< siob_proc_37 : siob_proc_37 */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_pio0_37 = 6, /*!< pio0_37 : pio0_37 */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_pio1_37 = 7, /*!< pio1_37 : pio1_37 */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_pio2_37 = 8, /*!< pio2_37 : pio2_37 */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO37_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO37_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO38_STATUS ===================================================== */ +/* ====================================================== GPIO38_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO38_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO38_CTRL_IRQOVER */ + IO_BANK0_GPIO38_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO38_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO38_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO38_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO38_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO38_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO38_CTRL_INOVER */ + IO_BANK0_GPIO38_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO38_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO38_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO38_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO38_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO38_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO38_CTRL_OEOVER */ + IO_BANK0_GPIO38_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO38_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO38_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO38_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO38_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO38_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO38_CTRL_OUTOVER */ + IO_BANK0_GPIO38_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO38_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO38_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO38_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO38_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO38_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO38_CTRL_FUNCSEL */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_pwm_a_11 = 4, /*!< pwm_a_11 : pwm_a_11 */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_siob_proc_38 = 5,/*!< siob_proc_38 : siob_proc_38 */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_pio0_38 = 6, /*!< pio0_38 : pio0_38 */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_pio1_38 = 7, /*!< pio1_38 : pio1_38 */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_pio2_38 = 8, /*!< pio2_38 : pio2_38 */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_uart1_tx = 11, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO38_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO38_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO39_STATUS ===================================================== */ +/* ====================================================== GPIO39_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO39_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO39_CTRL_IRQOVER */ + IO_BANK0_GPIO39_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO39_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO39_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO39_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO39_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO39_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO39_CTRL_INOVER */ + IO_BANK0_GPIO39_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO39_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO39_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO39_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO39_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO39_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO39_CTRL_OEOVER */ + IO_BANK0_GPIO39_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO39_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO39_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO39_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO39_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO39_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO39_CTRL_OUTOVER */ + IO_BANK0_GPIO39_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO39_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO39_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO39_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO39_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO39_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO39_CTRL_FUNCSEL */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_pwm_b_11 = 4, /*!< pwm_b_11 : pwm_b_11 */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_siob_proc_39 = 5,/*!< siob_proc_39 : siob_proc_39 */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_pio0_39 = 6, /*!< pio0_39 : pio0_39 */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_pio1_39 = 7, /*!< pio1_39 : pio1_39 */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_pio2_39 = 8, /*!< pio2_39 : pio2_39 */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_uart1_rx = 11, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO39_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO39_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO40_STATUS ===================================================== */ +/* ====================================================== GPIO40_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO40_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO40_CTRL_IRQOVER */ + IO_BANK0_GPIO40_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO40_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO40_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO40_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO40_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO40_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO40_CTRL_INOVER */ + IO_BANK0_GPIO40_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO40_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO40_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO40_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO40_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO40_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO40_CTRL_OEOVER */ + IO_BANK0_GPIO40_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO40_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO40_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO40_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO40_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO40_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO40_CTRL_OUTOVER */ + IO_BANK0_GPIO40_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO40_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO40_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO40_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO40_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO40_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO40_CTRL_FUNCSEL */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_pwm_a_8 = 4, /*!< pwm_a_8 : pwm_a_8 */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_siob_proc_40 = 5,/*!< siob_proc_40 : siob_proc_40 */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_pio0_40 = 6, /*!< pio0_40 : pio0_40 */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_pio1_40 = 7, /*!< pio1_40 : pio1_40 */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_pio2_40 = 8, /*!< pio2_40 : pio2_40 */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO40_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO40_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO41_STATUS ===================================================== */ +/* ====================================================== GPIO41_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO41_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO41_CTRL_IRQOVER */ + IO_BANK0_GPIO41_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO41_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO41_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO41_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO41_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO41_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO41_CTRL_INOVER */ + IO_BANK0_GPIO41_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO41_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO41_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO41_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO41_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO41_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO41_CTRL_OEOVER */ + IO_BANK0_GPIO41_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO41_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO41_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO41_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO41_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO41_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO41_CTRL_OUTOVER */ + IO_BANK0_GPIO41_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO41_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO41_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO41_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO41_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO41_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO41_CTRL_FUNCSEL */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_pwm_b_8 = 4, /*!< pwm_b_8 : pwm_b_8 */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_siob_proc_41 = 5,/*!< siob_proc_41 : siob_proc_41 */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_pio0_41 = 6, /*!< pio0_41 : pio0_41 */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_pio1_41 = 7, /*!< pio1_41 : pio1_41 */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_pio2_41 = 8, /*!< pio2_41 : pio2_41 */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO41_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO41_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO42_STATUS ===================================================== */ +/* ====================================================== GPIO42_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO42_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO42_CTRL_IRQOVER */ + IO_BANK0_GPIO42_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO42_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO42_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO42_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO42_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO42_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO42_CTRL_INOVER */ + IO_BANK0_GPIO42_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO42_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO42_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO42_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO42_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO42_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO42_CTRL_OEOVER */ + IO_BANK0_GPIO42_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO42_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO42_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO42_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO42_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO42_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO42_CTRL_OUTOVER */ + IO_BANK0_GPIO42_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO42_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO42_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO42_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO42_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO42_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO42_CTRL_FUNCSEL */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_spi1_sclk = 1, /*!< spi1_sclk : spi1_sclk */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_pwm_a_9 = 4, /*!< pwm_a_9 : pwm_a_9 */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_siob_proc_42 = 5,/*!< siob_proc_42 : siob_proc_42 */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_pio0_42 = 6, /*!< pio0_42 : pio0_42 */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_pio1_42 = 7, /*!< pio1_42 : pio1_42 */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_pio2_42 = 8, /*!< pio2_42 : pio2_42 */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_uart1_tx = 11, /*!< uart1_tx : uart1_tx */ + IO_BANK0_GPIO42_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO42_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO43_STATUS ===================================================== */ +/* ====================================================== GPIO43_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO43_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO43_CTRL_IRQOVER */ + IO_BANK0_GPIO43_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO43_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO43_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO43_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO43_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO43_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO43_CTRL_INOVER */ + IO_BANK0_GPIO43_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO43_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO43_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO43_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO43_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO43_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO43_CTRL_OEOVER */ + IO_BANK0_GPIO43_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO43_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO43_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO43_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO43_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO43_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO43_CTRL_OUTOVER */ + IO_BANK0_GPIO43_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO43_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO43_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO43_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO43_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO43_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO43_CTRL_FUNCSEL */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_spi1_tx = 1, /*!< spi1_tx : spi1_tx */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_pwm_b_9 = 4, /*!< pwm_b_9 : pwm_b_9 */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_siob_proc_43 = 5,/*!< siob_proc_43 : siob_proc_43 */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_pio0_43 = 6, /*!< pio0_43 : pio0_43 */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_pio1_43 = 7, /*!< pio1_43 : pio1_43 */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_pio2_43 = 8, /*!< pio2_43 : pio2_43 */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_uart1_rx = 11, /*!< uart1_rx : uart1_rx */ + IO_BANK0_GPIO43_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO43_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO44_STATUS ===================================================== */ +/* ====================================================== GPIO44_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO44_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO44_CTRL_IRQOVER */ + IO_BANK0_GPIO44_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO44_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO44_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO44_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO44_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO44_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO44_CTRL_INOVER */ + IO_BANK0_GPIO44_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO44_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO44_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO44_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO44_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO44_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO44_CTRL_OEOVER */ + IO_BANK0_GPIO44_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO44_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO44_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO44_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO44_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO44_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO44_CTRL_OUTOVER */ + IO_BANK0_GPIO44_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO44_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO44_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO44_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO44_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO44_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO44_CTRL_FUNCSEL */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_pwm_a_10 = 4, /*!< pwm_a_10 : pwm_a_10 */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_siob_proc_44 = 5,/*!< siob_proc_44 : siob_proc_44 */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_pio0_44 = 6, /*!< pio0_44 : pio0_44 */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_pio1_44 = 7, /*!< pio1_44 : pio1_44 */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_pio2_44 = 8, /*!< pio2_44 : pio2_44 */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO44_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO44_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO45_STATUS ===================================================== */ +/* ====================================================== GPIO45_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO45_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO45_CTRL_IRQOVER */ + IO_BANK0_GPIO45_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO45_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO45_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO45_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO45_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO45_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO45_CTRL_INOVER */ + IO_BANK0_GPIO45_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO45_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO45_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO45_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO45_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO45_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO45_CTRL_OEOVER */ + IO_BANK0_GPIO45_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO45_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO45_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO45_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO45_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO45_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO45_CTRL_OUTOVER */ + IO_BANK0_GPIO45_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO45_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO45_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO45_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO45_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO45_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO45_CTRL_FUNCSEL */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_pwm_b_10 = 4, /*!< pwm_b_10 : pwm_b_10 */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_siob_proc_45 = 5,/*!< siob_proc_45 : siob_proc_45 */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_pio0_45 = 6, /*!< pio0_45 : pio0_45 */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_pio1_45 = 7, /*!< pio1_45 : pio1_45 */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_pio2_45 = 8, /*!< pio2_45 : pio2_45 */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 10,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */ + IO_BANK0_GPIO45_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO45_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO46_STATUS ===================================================== */ +/* ====================================================== GPIO46_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO46_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO46_CTRL_IRQOVER */ + IO_BANK0_GPIO46_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO46_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO46_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO46_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO46_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO46_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO46_CTRL_INOVER */ + IO_BANK0_GPIO46_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO46_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO46_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO46_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO46_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO46_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO46_CTRL_OEOVER */ + IO_BANK0_GPIO46_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO46_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO46_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO46_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO46_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO46_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO46_CTRL_OUTOVER */ + IO_BANK0_GPIO46_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO46_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO46_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO46_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO46_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO46_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO46_CTRL_FUNCSEL */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_spi1_sclk = 1, /*!< spi1_sclk : spi1_sclk */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_uart0_cts = 2, /*!< uart0_cts : uart0_cts */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_pwm_a_11 = 4, /*!< pwm_a_11 : pwm_a_11 */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_siob_proc_46 = 5,/*!< siob_proc_46 : siob_proc_46 */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_pio0_46 = 6, /*!< pio0_46 : pio0_46 */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_pio1_46 = 7, /*!< pio1_46 : pio1_46 */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_pio2_46 = 8, /*!< pio2_46 : pio2_46 */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_usb_muxing_vbus_detect = 10,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_uart0_tx = 11, /*!< uart0_tx : uart0_tx */ + IO_BANK0_GPIO46_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO46_CTRL_FUNCSEL_Enum; + +/* ===================================================== GPIO47_STATUS ===================================================== */ +/* ====================================================== GPIO47_CTRL ====================================================== */ +/* ========================================= IO_BANK0 GPIO47_CTRL IRQOVER [28..29] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO47_CTRL_IRQOVER */ + IO_BANK0_GPIO47_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */ + IO_BANK0_GPIO47_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */ + IO_BANK0_GPIO47_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */ + IO_BANK0_GPIO47_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */ +} IO_BANK0_GPIO47_CTRL_IRQOVER_Enum; + +/* ========================================= IO_BANK0 GPIO47_CTRL INOVER [16..17] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO47_CTRL_INOVER */ + IO_BANK0_GPIO47_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */ + IO_BANK0_GPIO47_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */ + IO_BANK0_GPIO47_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */ + IO_BANK0_GPIO47_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */ +} IO_BANK0_GPIO47_CTRL_INOVER_Enum; + +/* ========================================= IO_BANK0 GPIO47_CTRL OEOVER [14..15] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO47_CTRL_OEOVER */ + IO_BANK0_GPIO47_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected + by funcsel */ + IO_BANK0_GPIO47_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal + selected by funcsel */ + IO_BANK0_GPIO47_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */ + IO_BANK0_GPIO47_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */ +} IO_BANK0_GPIO47_CTRL_OEOVER_Enum; + +/* ========================================= IO_BANK0 GPIO47_CTRL OUTOVER [12..13] ========================================= */ +typedef enum { /*!< IO_BANK0_GPIO47_CTRL_OUTOVER */ + IO_BANK0_GPIO47_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */ + IO_BANK0_GPIO47_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected + by funcsel */ + IO_BANK0_GPIO47_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */ + IO_BANK0_GPIO47_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */ +} IO_BANK0_GPIO47_CTRL_OUTOVER_Enum; + +/* ========================================== IO_BANK0 GPIO47_CTRL FUNCSEL [0..4] ========================================== */ +typedef enum { /*!< IO_BANK0_GPIO47_CTRL_FUNCSEL */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_spi1_tx = 1, /*!< spi1_tx : spi1_tx */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_uart0_rts = 2, /*!< uart0_rts : uart0_rts */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_pwm_b_11 = 4, /*!< pwm_b_11 : pwm_b_11 */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_siob_proc_47 = 5,/*!< siob_proc_47 : siob_proc_47 */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_pio0_47 = 6, /*!< pio0_47 : pio0_47 */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_pio1_47 = 7, /*!< pio1_47 : pio1_47 */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_pio2_47 = 8, /*!< pio2_47 : pio2_47 */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_xip_ss_n_1 = 9, /*!< xip_ss_n_1 : xip_ss_n_1 */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_usb_muxing_vbus_en = 10,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_uart0_rx = 11, /*!< uart0_rx : uart0_rx */ + IO_BANK0_GPIO47_CTRL_FUNCSEL_null = 31, /*!< null : null */ +} IO_BANK0_GPIO47_CTRL_FUNCSEL_Enum; + +/* =============================================== IRQSUMMARY_PROC0_SECURE0 ================================================ */ +/* =============================================== IRQSUMMARY_PROC0_SECURE1 ================================================ */ +/* ============================================== IRQSUMMARY_PROC0_NONSECURE0 ============================================== */ +/* ============================================== IRQSUMMARY_PROC0_NONSECURE1 ============================================== */ +/* =============================================== IRQSUMMARY_PROC1_SECURE0 ================================================ */ +/* =============================================== IRQSUMMARY_PROC1_SECURE1 ================================================ */ +/* ============================================== IRQSUMMARY_PROC1_NONSECURE0 ============================================== */ +/* ============================================== IRQSUMMARY_PROC1_NONSECURE1 ============================================== */ +/* ============================================ IRQSUMMARY_DORMANT_WAKE_SECURE0 ============================================ */ +/* ============================================ IRQSUMMARY_DORMANT_WAKE_SECURE1 ============================================ */ +/* ========================================== IRQSUMMARY_DORMANT_WAKE_NONSECURE0 =========================================== */ +/* ========================================== IRQSUMMARY_DORMANT_WAKE_NONSECURE1 =========================================== */ +/* ========================================================= INTR0 ========================================================= */ +/* ========================================================= INTR1 ========================================================= */ +/* ========================================================= INTR2 ========================================================= */ +/* ========================================================= INTR3 ========================================================= */ +/* ========================================================= INTR4 ========================================================= */ +/* ========================================================= INTR5 ========================================================= */ +/* ====================================================== PROC0_INTE0 ====================================================== */ +/* ====================================================== PROC0_INTE1 ====================================================== */ +/* ====================================================== PROC0_INTE2 ====================================================== */ +/* ====================================================== PROC0_INTE3 ====================================================== */ +/* ====================================================== PROC0_INTE4 ====================================================== */ +/* ====================================================== PROC0_INTE5 ====================================================== */ +/* ====================================================== PROC0_INTF0 ====================================================== */ +/* ====================================================== PROC0_INTF1 ====================================================== */ +/* ====================================================== PROC0_INTF2 ====================================================== */ +/* ====================================================== PROC0_INTF3 ====================================================== */ +/* ====================================================== PROC0_INTF4 ====================================================== */ +/* ====================================================== PROC0_INTF5 ====================================================== */ +/* ====================================================== PROC0_INTS0 ====================================================== */ +/* ====================================================== PROC0_INTS1 ====================================================== */ +/* ====================================================== PROC0_INTS2 ====================================================== */ +/* ====================================================== PROC0_INTS3 ====================================================== */ +/* ====================================================== PROC0_INTS4 ====================================================== */ +/* ====================================================== PROC0_INTS5 ====================================================== */ +/* ====================================================== PROC1_INTE0 ====================================================== */ +/* ====================================================== PROC1_INTE1 ====================================================== */ +/* ====================================================== PROC1_INTE2 ====================================================== */ +/* ====================================================== PROC1_INTE3 ====================================================== */ +/* ====================================================== PROC1_INTE4 ====================================================== */ +/* ====================================================== PROC1_INTE5 ====================================================== */ +/* ====================================================== PROC1_INTF0 ====================================================== */ +/* ====================================================== PROC1_INTF1 ====================================================== */ +/* ====================================================== PROC1_INTF2 ====================================================== */ +/* ====================================================== PROC1_INTF3 ====================================================== */ +/* ====================================================== PROC1_INTF4 ====================================================== */ +/* ====================================================== PROC1_INTF5 ====================================================== */ +/* ====================================================== PROC1_INTS0 ====================================================== */ +/* ====================================================== PROC1_INTS1 ====================================================== */ +/* ====================================================== PROC1_INTS2 ====================================================== */ +/* ====================================================== PROC1_INTS3 ====================================================== */ +/* ====================================================== PROC1_INTS4 ====================================================== */ +/* ====================================================== PROC1_INTS5 ====================================================== */ +/* ================================================== DORMANT_WAKE_INTE0 =================================================== */ +/* ================================================== DORMANT_WAKE_INTE1 =================================================== */ +/* ================================================== DORMANT_WAKE_INTE2 =================================================== */ +/* ================================================== DORMANT_WAKE_INTE3 =================================================== */ +/* ================================================== DORMANT_WAKE_INTE4 =================================================== */ +/* ================================================== DORMANT_WAKE_INTE5 =================================================== */ +/* ================================================== DORMANT_WAKE_INTF0 =================================================== */ +/* ================================================== DORMANT_WAKE_INTF1 =================================================== */ +/* ================================================== DORMANT_WAKE_INTF2 =================================================== */ +/* ================================================== DORMANT_WAKE_INTF3 =================================================== */ +/* ================================================== DORMANT_WAKE_INTF4 =================================================== */ +/* ================================================== DORMANT_WAKE_INTF5 =================================================== */ +/* ================================================== DORMANT_WAKE_INTS0 =================================================== */ +/* ================================================== DORMANT_WAKE_INTS1 =================================================== */ +/* ================================================== DORMANT_WAKE_INTS2 =================================================== */ +/* ================================================== DORMANT_WAKE_INTS3 =================================================== */ +/* ================================================== DORMANT_WAKE_INTS4 =================================================== */ +/* ================================================== DORMANT_WAKE_INTS5 =================================================== */ + + +/* =========================================================================================================================== */ +/* ================ SYSINFO ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIP_ID ======================================================== */ +/* ====================================================== PACKAGE_SEL ====================================================== */ +/* ======================================================= PLATFORM ======================================================== */ +/* ===================================================== GITREF_RP2350 ===================================================== */ + + +/* =========================================================================================================================== */ +/* ================ SHA256 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +/* ============================================== SHA256 CSR DMA_SIZE [8..9] =============================================== */ +typedef enum { /*!< SHA256_CSR_DMA_SIZE */ + SHA256_CSR_DMA_SIZE_8bit = 0, /*!< 8bit : 8bit */ + SHA256_CSR_DMA_SIZE_16bit = 1, /*!< 16bit : 16bit */ + SHA256_CSR_DMA_SIZE_32bit = 2, /*!< 32bit : 32bit */ +} SHA256_CSR_DMA_SIZE_Enum; + +/* ========================================================= WDATA ========================================================= */ +/* ========================================================= SUM0 ========================================================== */ +/* ========================================================= SUM1 ========================================================== */ +/* ========================================================= SUM2 ========================================================== */ +/* ========================================================= SUM3 ========================================================== */ +/* ========================================================= SUM4 ========================================================== */ +/* ========================================================= SUM5 ========================================================== */ +/* ========================================================= SUM6 ========================================================== */ +/* ========================================================= SUM7 ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ HSTX_FIFO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ +/* ========================================================= FIFO ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ HSTX_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +/* ========================================================= BIT0 ========================================================== */ +/* ========================================================= BIT1 ========================================================== */ +/* ========================================================= BIT2 ========================================================== */ +/* ========================================================= BIT3 ========================================================== */ +/* ========================================================= BIT4 ========================================================== */ +/* ========================================================= BIT5 ========================================================== */ +/* ========================================================= BIT6 ========================================================== */ +/* ========================================================= BIT7 ========================================================== */ +/* ===================================================== EXPAND_SHIFT ====================================================== */ +/* ====================================================== EXPAND_TMDS ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ EPPB ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= NMI_MASK0 ======================================================= */ +/* ======================================================= NMI_MASK1 ======================================================= */ +/* ======================================================= SLEEPCTRL ======================================================= */ + + +/* =========================================================================================================================== */ +/* ================ PPB ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ITM_STIM0 ======================================================= */ +/* ======================================================= ITM_STIM1 ======================================================= */ +/* ======================================================= ITM_STIM2 ======================================================= */ +/* ======================================================= ITM_STIM3 ======================================================= */ +/* ======================================================= ITM_STIM4 ======================================================= */ +/* ======================================================= ITM_STIM5 ======================================================= */ +/* ======================================================= ITM_STIM6 ======================================================= */ +/* ======================================================= ITM_STIM7 ======================================================= */ +/* ======================================================= ITM_STIM8 ======================================================= */ +/* ======================================================= ITM_STIM9 ======================================================= */ +/* ====================================================== ITM_STIM10 ======================================================= */ +/* ====================================================== ITM_STIM11 ======================================================= */ +/* ====================================================== ITM_STIM12 ======================================================= */ +/* ====================================================== ITM_STIM13 ======================================================= */ +/* ====================================================== ITM_STIM14 ======================================================= */ +/* ====================================================== ITM_STIM15 ======================================================= */ +/* ====================================================== ITM_STIM16 ======================================================= */ +/* ====================================================== ITM_STIM17 ======================================================= */ +/* ====================================================== ITM_STIM18 ======================================================= */ +/* ====================================================== ITM_STIM19 ======================================================= */ +/* ====================================================== ITM_STIM20 ======================================================= */ +/* ====================================================== ITM_STIM21 ======================================================= */ +/* ====================================================== ITM_STIM22 ======================================================= */ +/* ====================================================== ITM_STIM23 ======================================================= */ +/* ====================================================== ITM_STIM24 ======================================================= */ +/* ====================================================== ITM_STIM25 ======================================================= */ +/* ====================================================== ITM_STIM26 ======================================================= */ +/* ====================================================== ITM_STIM27 ======================================================= */ +/* ====================================================== ITM_STIM28 ======================================================= */ +/* ====================================================== ITM_STIM29 ======================================================= */ +/* ====================================================== ITM_STIM30 ======================================================= */ +/* ====================================================== ITM_STIM31 ======================================================= */ +/* ======================================================= ITM_TER0 ======================================================== */ +/* ======================================================== ITM_TPR ======================================================== */ +/* ======================================================== ITM_TCR ======================================================== */ +/* ====================================================== INT_ATREADY ====================================================== */ +/* ====================================================== INT_ATVALID ====================================================== */ +/* ====================================================== ITM_ITCTRL ======================================================= */ +/* ====================================================== ITM_DEVARCH ====================================================== */ +/* ====================================================== ITM_DEVTYPE ====================================================== */ +/* ======================================================= ITM_PIDR4 ======================================================= */ +/* ======================================================= ITM_PIDR5 ======================================================= */ +/* ======================================================= ITM_PIDR6 ======================================================= */ +/* ======================================================= ITM_PIDR7 ======================================================= */ +/* ======================================================= ITM_PIDR0 ======================================================= */ +/* ======================================================= ITM_PIDR1 ======================================================= */ +/* ======================================================= ITM_PIDR2 ======================================================= */ +/* ======================================================= ITM_PIDR3 ======================================================= */ +/* ======================================================= ITM_CIDR0 ======================================================= */ +/* ======================================================= ITM_CIDR1 ======================================================= */ +/* ======================================================= ITM_CIDR2 ======================================================= */ +/* ======================================================= ITM_CIDR3 ======================================================= */ +/* ======================================================= DWT_CTRL ======================================================== */ +/* ====================================================== DWT_CYCCNT ======================================================= */ +/* ====================================================== DWT_EXCCNT ======================================================= */ +/* ====================================================== DWT_LSUCNT ======================================================= */ +/* ====================================================== DWT_FOLDCNT ====================================================== */ +/* ======================================================= DWT_COMP0 ======================================================= */ +/* ===================================================== DWT_FUNCTION0 ===================================================== */ +/* ======================================================= DWT_COMP1 ======================================================= */ +/* ===================================================== DWT_FUNCTION1 ===================================================== */ +/* ======================================================= DWT_COMP2 ======================================================= */ +/* ===================================================== DWT_FUNCTION2 ===================================================== */ +/* ======================================================= DWT_COMP3 ======================================================= */ +/* ===================================================== DWT_FUNCTION3 ===================================================== */ +/* ====================================================== DWT_DEVARCH ====================================================== */ +/* ====================================================== DWT_DEVTYPE ====================================================== */ +/* ======================================================= DWT_PIDR4 ======================================================= */ +/* ======================================================= DWT_PIDR5 ======================================================= */ +/* ======================================================= DWT_PIDR6 ======================================================= */ +/* ======================================================= DWT_PIDR7 ======================================================= */ +/* ======================================================= DWT_PIDR0 ======================================================= */ +/* ======================================================= DWT_PIDR1 ======================================================= */ +/* ======================================================= DWT_PIDR2 ======================================================= */ +/* ======================================================= DWT_PIDR3 ======================================================= */ +/* ======================================================= DWT_CIDR0 ======================================================= */ +/* ======================================================= DWT_CIDR1 ======================================================= */ +/* ======================================================= DWT_CIDR2 ======================================================= */ +/* ======================================================= DWT_CIDR3 ======================================================= */ +/* ======================================================== FP_CTRL ======================================================== */ +/* ======================================================= FP_REMAP ======================================================== */ +/* ======================================================= FP_COMP0 ======================================================== */ +/* ======================================================= FP_COMP1 ======================================================== */ +/* ======================================================= FP_COMP2 ======================================================== */ +/* ======================================================= FP_COMP3 ======================================================== */ +/* ======================================================= FP_COMP4 ======================================================== */ +/* ======================================================= FP_COMP5 ======================================================== */ +/* ======================================================= FP_COMP6 ======================================================== */ +/* ======================================================= FP_COMP7 ======================================================== */ +/* ====================================================== FP_DEVARCH ======================================================= */ +/* ====================================================== FP_DEVTYPE ======================================================= */ +/* ======================================================= FP_PIDR4 ======================================================== */ +/* ======================================================= FP_PIDR5 ======================================================== */ +/* ======================================================= FP_PIDR6 ======================================================== */ +/* ======================================================= FP_PIDR7 ======================================================== */ +/* ======================================================= FP_PIDR0 ======================================================== */ +/* ======================================================= FP_PIDR1 ======================================================== */ +/* ======================================================= FP_PIDR2 ======================================================== */ +/* ======================================================= FP_PIDR3 ======================================================== */ +/* ======================================================= FP_CIDR0 ======================================================== */ +/* ======================================================= FP_CIDR1 ======================================================== */ +/* ======================================================= FP_CIDR2 ======================================================== */ +/* ======================================================= FP_CIDR3 ======================================================== */ +/* ========================================================= ICTR ========================================================== */ +/* ========================================================= ACTLR ========================================================= */ +/* ======================================================= SYST_CSR ======================================================== */ +/* ======================================================= SYST_RVR ======================================================== */ +/* ======================================================= SYST_CVR ======================================================== */ +/* ====================================================== SYST_CALIB ======================================================= */ +/* ====================================================== NVIC_ISER0 ======================================================= */ +/* ====================================================== NVIC_ISER1 ======================================================= */ +/* ====================================================== NVIC_ICER0 ======================================================= */ +/* ====================================================== NVIC_ICER1 ======================================================= */ +/* ====================================================== NVIC_ISPR0 ======================================================= */ +/* ====================================================== NVIC_ISPR1 ======================================================= */ +/* ====================================================== NVIC_ICPR0 ======================================================= */ +/* ====================================================== NVIC_ICPR1 ======================================================= */ +/* ====================================================== NVIC_IABR0 ======================================================= */ +/* ====================================================== NVIC_IABR1 ======================================================= */ +/* ====================================================== NVIC_ITNS0 ======================================================= */ +/* ====================================================== NVIC_ITNS1 ======================================================= */ +/* ======================================================= NVIC_IPR0 ======================================================= */ +/* ======================================================= NVIC_IPR1 ======================================================= */ +/* ======================================================= NVIC_IPR2 ======================================================= */ +/* ======================================================= NVIC_IPR3 ======================================================= */ +/* ======================================================= NVIC_IPR4 ======================================================= */ +/* ======================================================= NVIC_IPR5 ======================================================= */ +/* ======================================================= NVIC_IPR6 ======================================================= */ +/* ======================================================= NVIC_IPR7 ======================================================= */ +/* ======================================================= NVIC_IPR8 ======================================================= */ +/* ======================================================= NVIC_IPR9 ======================================================= */ +/* ====================================================== NVIC_IPR10 ======================================================= */ +/* ====================================================== NVIC_IPR11 ======================================================= */ +/* ====================================================== NVIC_IPR12 ======================================================= */ +/* ====================================================== NVIC_IPR13 ======================================================= */ +/* ====================================================== NVIC_IPR14 ======================================================= */ +/* ====================================================== NVIC_IPR15 ======================================================= */ +/* ========================================================= CPUID ========================================================= */ +/* ========================================================= ICSR ========================================================== */ +/* ========================================================= VTOR ========================================================== */ +/* ========================================================= AIRCR ========================================================= */ +/* ========================================================== SCR ========================================================== */ +/* ========================================================== CCR ========================================================== */ +/* ========================================================= SHPR1 ========================================================= */ +/* ========================================================= SHPR2 ========================================================= */ +/* ========================================================= SHPR3 ========================================================= */ +/* ========================================================= SHCSR ========================================================= */ +/* ========================================================= CFSR ========================================================== */ +/* ========================================================= HFSR ========================================================== */ +/* ========================================================= DFSR ========================================================== */ +/* ========================================================= MMFAR ========================================================= */ +/* ========================================================= BFAR ========================================================== */ +/* ======================================================== ID_PFR0 ======================================================== */ +/* ======================================================== ID_PFR1 ======================================================== */ +/* ======================================================== ID_DFR0 ======================================================== */ +/* ======================================================== ID_AFR0 ======================================================== */ +/* ======================================================= ID_MMFR0 ======================================================== */ +/* ======================================================= ID_MMFR1 ======================================================== */ +/* ======================================================= ID_MMFR2 ======================================================== */ +/* ======================================================= ID_MMFR3 ======================================================== */ +/* ======================================================= ID_ISAR0 ======================================================== */ +/* ======================================================= ID_ISAR1 ======================================================== */ +/* ======================================================= ID_ISAR2 ======================================================== */ +/* ======================================================= ID_ISAR3 ======================================================== */ +/* ======================================================= ID_ISAR4 ======================================================== */ +/* ======================================================= ID_ISAR5 ======================================================== */ +/* ========================================================== CTR ========================================================== */ +/* ========================================================= CPACR ========================================================= */ +/* ========================================================= NSACR ========================================================= */ +/* ======================================================= MPU_TYPE ======================================================== */ +/* ======================================================= MPU_CTRL ======================================================== */ +/* ======================================================== MPU_RNR ======================================================== */ +/* ======================================================= MPU_RBAR ======================================================== */ +/* ======================================================= MPU_RLAR ======================================================== */ +/* ====================================================== MPU_RBAR_A1 ====================================================== */ +/* ====================================================== MPU_RLAR_A1 ====================================================== */ +/* ====================================================== MPU_RBAR_A2 ====================================================== */ +/* ====================================================== MPU_RLAR_A2 ====================================================== */ +/* ====================================================== MPU_RBAR_A3 ====================================================== */ +/* ====================================================== MPU_RLAR_A3 ====================================================== */ +/* ======================================================= MPU_MAIR0 ======================================================= */ +/* ======================================================= MPU_MAIR1 ======================================================= */ +/* ======================================================= SAU_CTRL ======================================================== */ +/* ======================================================= SAU_TYPE ======================================================== */ +/* ======================================================== SAU_RNR ======================================================== */ +/* ======================================================= SAU_RBAR ======================================================== */ +/* ======================================================= SAU_RLAR ======================================================== */ +/* ========================================================= SFSR ========================================================== */ +/* ========================================================= SFAR ========================================================== */ +/* ========================================================= DHCSR ========================================================= */ +/* ========================================================= DCRSR ========================================================= */ +/* ========================================================= DCRDR ========================================================= */ +/* ========================================================= DEMCR ========================================================= */ +/* ========================================================= DSCSR ========================================================= */ +/* ========================================================= STIR ========================================================== */ +/* ========================================================= FPCCR ========================================================= */ +/* ========================================================= FPCAR ========================================================= */ +/* ======================================================== FPDSCR ========================================================= */ +/* ========================================================= MVFR0 ========================================================= */ +/* ========================================================= MVFR1 ========================================================= */ +/* ========================================================= MVFR2 ========================================================= */ +/* ======================================================= DDEVARCH ======================================================== */ +/* ======================================================= DDEVTYPE ======================================================== */ +/* ======================================================== DPIDR4 ========================================================= */ +/* ======================================================== DPIDR5 ========================================================= */ +/* ======================================================== DPIDR6 ========================================================= */ +/* ======================================================== DPIDR7 ========================================================= */ +/* ======================================================== DPIDR0 ========================================================= */ +/* ======================================================== DPIDR1 ========================================================= */ +/* ======================================================== DPIDR2 ========================================================= */ +/* ======================================================== DPIDR3 ========================================================= */ +/* ======================================================== DCIDR0 ========================================================= */ +/* ======================================================== DCIDR1 ========================================================= */ +/* ======================================================== DCIDR2 ========================================================= */ +/* ======================================================== DCIDR3 ========================================================= */ +/* ====================================================== TRCPRGCTLR ======================================================= */ +/* ======================================================= TRCSTATR ======================================================== */ +/* ====================================================== TRCCONFIGR ======================================================= */ +/* ===================================================== TRCEVENTCTL0R ===================================================== */ +/* ===================================================== TRCEVENTCTL1R ===================================================== */ +/* ===================================================== TRCSTALLCTLR ====================================================== */ +/* ======================================================= TRCTSCTLR ======================================================= */ +/* ======================================================= TRCSYNCPR ======================================================= */ +/* ======================================================= TRCCCCTLR ======================================================= */ +/* ======================================================= TRCVICTLR ======================================================= */ +/* ===================================================== TRCCNTRLDVR0 ====================================================== */ +/* ======================================================== TRCIDR8 ======================================================== */ +/* ======================================================== TRCIDR9 ======================================================== */ +/* ======================================================= TRCIDR10 ======================================================== */ +/* ======================================================= TRCIDR11 ======================================================== */ +/* ======================================================= TRCIDR12 ======================================================== */ +/* ======================================================= TRCIDR13 ======================================================== */ +/* ======================================================= TRCIMSPEC ======================================================= */ +/* ======================================================== TRCIDR0 ======================================================== */ +/* ======================================================== TRCIDR1 ======================================================== */ +/* ======================================================== TRCIDR2 ======================================================== */ +/* ======================================================== TRCIDR3 ======================================================== */ +/* ======================================================== TRCIDR4 ======================================================== */ +/* ======================================================== TRCIDR5 ======================================================== */ +/* ======================================================== TRCIDR6 ======================================================== */ +/* ======================================================== TRCIDR7 ======================================================== */ +/* ====================================================== TRCRSCTLR2 ======================================================= */ +/* ====================================================== TRCRSCTLR3 ======================================================= */ +/* ======================================================= TRCSSCSR ======================================================== */ +/* ====================================================== TRCSSPCICR ======================================================= */ +/* ======================================================== TRCPDCR ======================================================== */ +/* ======================================================== TRCPDSR ======================================================== */ +/* ====================================================== TRCITATBIDR ====================================================== */ +/* ===================================================== TRCITIATBINR ====================================================== */ +/* ===================================================== TRCITIATBOUTR ===================================================== */ +/* ====================================================== TRCCLAIMSET ====================================================== */ +/* ====================================================== TRCCLAIMCLR ====================================================== */ +/* ===================================================== TRCAUTHSTATUS ===================================================== */ +/* ====================================================== TRCDEVARCH ======================================================= */ +/* ======================================================= TRCDEVID ======================================================== */ +/* ====================================================== TRCDEVTYPE ======================================================= */ +/* ======================================================= TRCPIDR4 ======================================================== */ +/* ======================================================= TRCPIDR5 ======================================================== */ +/* ======================================================= TRCPIDR6 ======================================================== */ +/* ======================================================= TRCPIDR7 ======================================================== */ +/* ======================================================= TRCPIDR0 ======================================================== */ +/* ======================================================= TRCPIDR1 ======================================================== */ +/* ======================================================= TRCPIDR2 ======================================================== */ +/* ======================================================= TRCPIDR3 ======================================================== */ +/* ======================================================= TRCCIDR0 ======================================================== */ +/* ======================================================= TRCCIDR1 ======================================================== */ +/* ======================================================= TRCCIDR2 ======================================================== */ +/* ======================================================= TRCCIDR3 ======================================================== */ +/* ====================================================== CTICONTROL ======================================================= */ +/* ======================================================= CTIINTACK ======================================================= */ +/* ======================================================= CTIAPPSET ======================================================= */ +/* ====================================================== CTIAPPCLEAR ====================================================== */ +/* ====================================================== CTIAPPPULSE ====================================================== */ +/* ======================================================= CTIINEN0 ======================================================== */ +/* ======================================================= CTIINEN1 ======================================================== */ +/* ======================================================= CTIINEN2 ======================================================== */ +/* ======================================================= CTIINEN3 ======================================================== */ +/* ======================================================= CTIINEN4 ======================================================== */ +/* ======================================================= CTIINEN5 ======================================================== */ +/* ======================================================= CTIINEN6 ======================================================== */ +/* ======================================================= CTIINEN7 ======================================================== */ +/* ======================================================= CTIOUTEN0 ======================================================= */ +/* ======================================================= CTIOUTEN1 ======================================================= */ +/* ======================================================= CTIOUTEN2 ======================================================= */ +/* ======================================================= CTIOUTEN3 ======================================================= */ +/* ======================================================= CTIOUTEN4 ======================================================= */ +/* ======================================================= CTIOUTEN5 ======================================================= */ +/* ======================================================= CTIOUTEN6 ======================================================= */ +/* ======================================================= CTIOUTEN7 ======================================================= */ +/* ==================================================== CTITRIGINSTATUS ==================================================== */ +/* =================================================== CTITRIGOUTSTATUS ==================================================== */ +/* ===================================================== CTICHINSTATUS ===================================================== */ +/* ======================================================== CTIGATE ======================================================== */ +/* ======================================================== ASICCTL ======================================================== */ +/* ======================================================== ITCHOUT ======================================================== */ +/* ======================================================= ITTRIGOUT ======================================================= */ +/* ======================================================== ITCHIN ========================================================= */ +/* ======================================================== ITCTRL ========================================================= */ +/* ======================================================== DEVARCH ======================================================== */ +/* ========================================================= DEVID ========================================================= */ +/* ======================================================== DEVTYPE ======================================================== */ +/* ========================================================= PIDR4 ========================================================= */ +/* ========================================================= PIDR5 ========================================================= */ +/* ========================================================= PIDR6 ========================================================= */ +/* ========================================================= PIDR7 ========================================================= */ +/* ========================================================= PIDR0 ========================================================= */ +/* ========================================================= PIDR1 ========================================================= */ +/* ========================================================= PIDR2 ========================================================= */ +/* ========================================================= PIDR3 ========================================================= */ +/* ========================================================= CIDR0 ========================================================= */ +/* ========================================================= CIDR1 ========================================================= */ +/* ========================================================= CIDR2 ========================================================= */ +/* ========================================================= CIDR3 ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ QMI ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== DIRECT_CSR ======================================================= */ +/* ======================================================= DIRECT_TX ======================================================= */ +/* ============================================= QMI DIRECT_TX IWIDTH [16..17] ============================================= */ +typedef enum { /*!< QMI_DIRECT_TX_IWIDTH */ + QMI_DIRECT_TX_IWIDTH_S = 0, /*!< S : Single width */ + QMI_DIRECT_TX_IWIDTH_D = 1, /*!< D : Dual width */ + QMI_DIRECT_TX_IWIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_DIRECT_TX_IWIDTH_Enum; + +/* ======================================================= DIRECT_RX ======================================================= */ +/* ======================================================= M0_TIMING ======================================================= */ +/* =========================================== QMI M0_TIMING PAGEBREAK [28..29] ============================================ */ +typedef enum { /*!< QMI_M0_TIMING_PAGEBREAK */ + QMI_M0_TIMING_PAGEBREAK_NONE = 0, /*!< NONE : No page boundary is enforced */ + QMI_M0_TIMING_PAGEBREAK_256 = 1, /*!< 256 : Break bursts crossing a 256-byte page boundary */ + QMI_M0_TIMING_PAGEBREAK_1024 = 2, /*!< 1024 : Break bursts crossing a 1024-byte quad-page boundary */ + QMI_M0_TIMING_PAGEBREAK_4096 = 3, /*!< 4096 : Break bursts crossing a 4096-byte sector boundary */ +} QMI_M0_TIMING_PAGEBREAK_Enum; + +/* ======================================================== M0_RFMT ======================================================== */ +/* ============================================ QMI M0_RFMT DUMMY_LEN [16..18] ============================================= */ +typedef enum { /*!< QMI_M0_RFMT_DUMMY_LEN */ + QMI_M0_RFMT_DUMMY_LEN_NONE = 0, /*!< NONE : No dummy phase */ + QMI_M0_RFMT_DUMMY_LEN_4 = 1, /*!< 4 : 4 dummy bits */ + QMI_M0_RFMT_DUMMY_LEN_8 = 2, /*!< 8 : 8 dummy bits */ + QMI_M0_RFMT_DUMMY_LEN_12 = 3, /*!< 12 : 12 dummy bits */ + QMI_M0_RFMT_DUMMY_LEN_16 = 4, /*!< 16 : 16 dummy bits */ + QMI_M0_RFMT_DUMMY_LEN_20 = 5, /*!< 20 : 20 dummy bits */ + QMI_M0_RFMT_DUMMY_LEN_24 = 6, /*!< 24 : 24 dummy bits */ + QMI_M0_RFMT_DUMMY_LEN_28 = 7, /*!< 28 : 28 dummy bits */ +} QMI_M0_RFMT_DUMMY_LEN_Enum; + +/* ============================================ QMI M0_RFMT SUFFIX_LEN [14..15] ============================================ */ +typedef enum { /*!< QMI_M0_RFMT_SUFFIX_LEN */ + QMI_M0_RFMT_SUFFIX_LEN_NONE = 0, /*!< NONE : No suffix */ + QMI_M0_RFMT_SUFFIX_LEN_8 = 2, /*!< 8 : 8-bit suffix */ +} QMI_M0_RFMT_SUFFIX_LEN_Enum; + +/* ============================================ QMI M0_RFMT PREFIX_LEN [12..12] ============================================ */ +typedef enum { /*!< QMI_M0_RFMT_PREFIX_LEN */ + QMI_M0_RFMT_PREFIX_LEN_NONE = 0, /*!< NONE : No prefix */ + QMI_M0_RFMT_PREFIX_LEN_8 = 1, /*!< 8 : 8-bit prefix */ +} QMI_M0_RFMT_PREFIX_LEN_Enum; + +/* ============================================= QMI M0_RFMT DATA_WIDTH [8..9] ============================================= */ +typedef enum { /*!< QMI_M0_RFMT_DATA_WIDTH */ + QMI_M0_RFMT_DATA_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_RFMT_DATA_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_RFMT_DATA_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_RFMT_DATA_WIDTH_Enum; + +/* ============================================ QMI M0_RFMT DUMMY_WIDTH [6..7] ============================================= */ +typedef enum { /*!< QMI_M0_RFMT_DUMMY_WIDTH */ + QMI_M0_RFMT_DUMMY_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_RFMT_DUMMY_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_RFMT_DUMMY_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_RFMT_DUMMY_WIDTH_Enum; + +/* ============================================ QMI M0_RFMT SUFFIX_WIDTH [4..5] ============================================ */ +typedef enum { /*!< QMI_M0_RFMT_SUFFIX_WIDTH */ + QMI_M0_RFMT_SUFFIX_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_RFMT_SUFFIX_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_RFMT_SUFFIX_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_RFMT_SUFFIX_WIDTH_Enum; + +/* ============================================= QMI M0_RFMT ADDR_WIDTH [2..3] ============================================= */ +typedef enum { /*!< QMI_M0_RFMT_ADDR_WIDTH */ + QMI_M0_RFMT_ADDR_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_RFMT_ADDR_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_RFMT_ADDR_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_RFMT_ADDR_WIDTH_Enum; + +/* ============================================ QMI M0_RFMT PREFIX_WIDTH [0..1] ============================================ */ +typedef enum { /*!< QMI_M0_RFMT_PREFIX_WIDTH */ + QMI_M0_RFMT_PREFIX_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_RFMT_PREFIX_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_RFMT_PREFIX_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_RFMT_PREFIX_WIDTH_Enum; + +/* ======================================================== M0_RCMD ======================================================== */ +/* ======================================================== M0_WFMT ======================================================== */ +/* ============================================ QMI M0_WFMT DUMMY_LEN [16..18] ============================================= */ +typedef enum { /*!< QMI_M0_WFMT_DUMMY_LEN */ + QMI_M0_WFMT_DUMMY_LEN_NONE = 0, /*!< NONE : No dummy phase */ + QMI_M0_WFMT_DUMMY_LEN_4 = 1, /*!< 4 : 4 dummy bits */ + QMI_M0_WFMT_DUMMY_LEN_8 = 2, /*!< 8 : 8 dummy bits */ + QMI_M0_WFMT_DUMMY_LEN_12 = 3, /*!< 12 : 12 dummy bits */ + QMI_M0_WFMT_DUMMY_LEN_16 = 4, /*!< 16 : 16 dummy bits */ + QMI_M0_WFMT_DUMMY_LEN_20 = 5, /*!< 20 : 20 dummy bits */ + QMI_M0_WFMT_DUMMY_LEN_24 = 6, /*!< 24 : 24 dummy bits */ + QMI_M0_WFMT_DUMMY_LEN_28 = 7, /*!< 28 : 28 dummy bits */ +} QMI_M0_WFMT_DUMMY_LEN_Enum; + +/* ============================================ QMI M0_WFMT SUFFIX_LEN [14..15] ============================================ */ +typedef enum { /*!< QMI_M0_WFMT_SUFFIX_LEN */ + QMI_M0_WFMT_SUFFIX_LEN_NONE = 0, /*!< NONE : No suffix */ + QMI_M0_WFMT_SUFFIX_LEN_8 = 2, /*!< 8 : 8-bit suffix */ +} QMI_M0_WFMT_SUFFIX_LEN_Enum; + +/* ============================================ QMI M0_WFMT PREFIX_LEN [12..12] ============================================ */ +typedef enum { /*!< QMI_M0_WFMT_PREFIX_LEN */ + QMI_M0_WFMT_PREFIX_LEN_NONE = 0, /*!< NONE : No prefix */ + QMI_M0_WFMT_PREFIX_LEN_8 = 1, /*!< 8 : 8-bit prefix */ +} QMI_M0_WFMT_PREFIX_LEN_Enum; + +/* ============================================= QMI M0_WFMT DATA_WIDTH [8..9] ============================================= */ +typedef enum { /*!< QMI_M0_WFMT_DATA_WIDTH */ + QMI_M0_WFMT_DATA_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_WFMT_DATA_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_WFMT_DATA_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_WFMT_DATA_WIDTH_Enum; + +/* ============================================ QMI M0_WFMT DUMMY_WIDTH [6..7] ============================================= */ +typedef enum { /*!< QMI_M0_WFMT_DUMMY_WIDTH */ + QMI_M0_WFMT_DUMMY_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_WFMT_DUMMY_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_WFMT_DUMMY_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_WFMT_DUMMY_WIDTH_Enum; + +/* ============================================ QMI M0_WFMT SUFFIX_WIDTH [4..5] ============================================ */ +typedef enum { /*!< QMI_M0_WFMT_SUFFIX_WIDTH */ + QMI_M0_WFMT_SUFFIX_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_WFMT_SUFFIX_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_WFMT_SUFFIX_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_WFMT_SUFFIX_WIDTH_Enum; + +/* ============================================= QMI M0_WFMT ADDR_WIDTH [2..3] ============================================= */ +typedef enum { /*!< QMI_M0_WFMT_ADDR_WIDTH */ + QMI_M0_WFMT_ADDR_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_WFMT_ADDR_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_WFMT_ADDR_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_WFMT_ADDR_WIDTH_Enum; + +/* ============================================ QMI M0_WFMT PREFIX_WIDTH [0..1] ============================================ */ +typedef enum { /*!< QMI_M0_WFMT_PREFIX_WIDTH */ + QMI_M0_WFMT_PREFIX_WIDTH_S = 0, /*!< S : Single width */ + QMI_M0_WFMT_PREFIX_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M0_WFMT_PREFIX_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M0_WFMT_PREFIX_WIDTH_Enum; + +/* ======================================================== M0_WCMD ======================================================== */ +/* ======================================================= M1_TIMING ======================================================= */ +/* =========================================== QMI M1_TIMING PAGEBREAK [28..29] ============================================ */ +typedef enum { /*!< QMI_M1_TIMING_PAGEBREAK */ + QMI_M1_TIMING_PAGEBREAK_NONE = 0, /*!< NONE : No page boundary is enforced */ + QMI_M1_TIMING_PAGEBREAK_256 = 1, /*!< 256 : Break bursts crossing a 256-byte page boundary */ + QMI_M1_TIMING_PAGEBREAK_1024 = 2, /*!< 1024 : Break bursts crossing a 1024-byte quad-page boundary */ + QMI_M1_TIMING_PAGEBREAK_4096 = 3, /*!< 4096 : Break bursts crossing a 4096-byte sector boundary */ +} QMI_M1_TIMING_PAGEBREAK_Enum; + +/* ======================================================== M1_RFMT ======================================================== */ +/* ============================================ QMI M1_RFMT DUMMY_LEN [16..18] ============================================= */ +typedef enum { /*!< QMI_M1_RFMT_DUMMY_LEN */ + QMI_M1_RFMT_DUMMY_LEN_NONE = 0, /*!< NONE : No dummy phase */ + QMI_M1_RFMT_DUMMY_LEN_4 = 1, /*!< 4 : 4 dummy bits */ + QMI_M1_RFMT_DUMMY_LEN_8 = 2, /*!< 8 : 8 dummy bits */ + QMI_M1_RFMT_DUMMY_LEN_12 = 3, /*!< 12 : 12 dummy bits */ + QMI_M1_RFMT_DUMMY_LEN_16 = 4, /*!< 16 : 16 dummy bits */ + QMI_M1_RFMT_DUMMY_LEN_20 = 5, /*!< 20 : 20 dummy bits */ + QMI_M1_RFMT_DUMMY_LEN_24 = 6, /*!< 24 : 24 dummy bits */ + QMI_M1_RFMT_DUMMY_LEN_28 = 7, /*!< 28 : 28 dummy bits */ +} QMI_M1_RFMT_DUMMY_LEN_Enum; + +/* ============================================ QMI M1_RFMT SUFFIX_LEN [14..15] ============================================ */ +typedef enum { /*!< QMI_M1_RFMT_SUFFIX_LEN */ + QMI_M1_RFMT_SUFFIX_LEN_NONE = 0, /*!< NONE : No suffix */ + QMI_M1_RFMT_SUFFIX_LEN_8 = 2, /*!< 8 : 8-bit suffix */ +} QMI_M1_RFMT_SUFFIX_LEN_Enum; + +/* ============================================ QMI M1_RFMT PREFIX_LEN [12..12] ============================================ */ +typedef enum { /*!< QMI_M1_RFMT_PREFIX_LEN */ + QMI_M1_RFMT_PREFIX_LEN_NONE = 0, /*!< NONE : No prefix */ + QMI_M1_RFMT_PREFIX_LEN_8 = 1, /*!< 8 : 8-bit prefix */ +} QMI_M1_RFMT_PREFIX_LEN_Enum; + +/* ============================================= QMI M1_RFMT DATA_WIDTH [8..9] ============================================= */ +typedef enum { /*!< QMI_M1_RFMT_DATA_WIDTH */ + QMI_M1_RFMT_DATA_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_RFMT_DATA_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_RFMT_DATA_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_RFMT_DATA_WIDTH_Enum; + +/* ============================================ QMI M1_RFMT DUMMY_WIDTH [6..7] ============================================= */ +typedef enum { /*!< QMI_M1_RFMT_DUMMY_WIDTH */ + QMI_M1_RFMT_DUMMY_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_RFMT_DUMMY_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_RFMT_DUMMY_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_RFMT_DUMMY_WIDTH_Enum; + +/* ============================================ QMI M1_RFMT SUFFIX_WIDTH [4..5] ============================================ */ +typedef enum { /*!< QMI_M1_RFMT_SUFFIX_WIDTH */ + QMI_M1_RFMT_SUFFIX_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_RFMT_SUFFIX_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_RFMT_SUFFIX_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_RFMT_SUFFIX_WIDTH_Enum; + +/* ============================================= QMI M1_RFMT ADDR_WIDTH [2..3] ============================================= */ +typedef enum { /*!< QMI_M1_RFMT_ADDR_WIDTH */ + QMI_M1_RFMT_ADDR_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_RFMT_ADDR_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_RFMT_ADDR_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_RFMT_ADDR_WIDTH_Enum; + +/* ============================================ QMI M1_RFMT PREFIX_WIDTH [0..1] ============================================ */ +typedef enum { /*!< QMI_M1_RFMT_PREFIX_WIDTH */ + QMI_M1_RFMT_PREFIX_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_RFMT_PREFIX_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_RFMT_PREFIX_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_RFMT_PREFIX_WIDTH_Enum; + +/* ======================================================== M1_RCMD ======================================================== */ +/* ======================================================== M1_WFMT ======================================================== */ +/* ============================================ QMI M1_WFMT DUMMY_LEN [16..18] ============================================= */ +typedef enum { /*!< QMI_M1_WFMT_DUMMY_LEN */ + QMI_M1_WFMT_DUMMY_LEN_NONE = 0, /*!< NONE : No dummy phase */ + QMI_M1_WFMT_DUMMY_LEN_4 = 1, /*!< 4 : 4 dummy bits */ + QMI_M1_WFMT_DUMMY_LEN_8 = 2, /*!< 8 : 8 dummy bits */ + QMI_M1_WFMT_DUMMY_LEN_12 = 3, /*!< 12 : 12 dummy bits */ + QMI_M1_WFMT_DUMMY_LEN_16 = 4, /*!< 16 : 16 dummy bits */ + QMI_M1_WFMT_DUMMY_LEN_20 = 5, /*!< 20 : 20 dummy bits */ + QMI_M1_WFMT_DUMMY_LEN_24 = 6, /*!< 24 : 24 dummy bits */ + QMI_M1_WFMT_DUMMY_LEN_28 = 7, /*!< 28 : 28 dummy bits */ +} QMI_M1_WFMT_DUMMY_LEN_Enum; + +/* ============================================ QMI M1_WFMT SUFFIX_LEN [14..15] ============================================ */ +typedef enum { /*!< QMI_M1_WFMT_SUFFIX_LEN */ + QMI_M1_WFMT_SUFFIX_LEN_NONE = 0, /*!< NONE : No suffix */ + QMI_M1_WFMT_SUFFIX_LEN_8 = 2, /*!< 8 : 8-bit suffix */ +} QMI_M1_WFMT_SUFFIX_LEN_Enum; + +/* ============================================ QMI M1_WFMT PREFIX_LEN [12..12] ============================================ */ +typedef enum { /*!< QMI_M1_WFMT_PREFIX_LEN */ + QMI_M1_WFMT_PREFIX_LEN_NONE = 0, /*!< NONE : No prefix */ + QMI_M1_WFMT_PREFIX_LEN_8 = 1, /*!< 8 : 8-bit prefix */ +} QMI_M1_WFMT_PREFIX_LEN_Enum; + +/* ============================================= QMI M1_WFMT DATA_WIDTH [8..9] ============================================= */ +typedef enum { /*!< QMI_M1_WFMT_DATA_WIDTH */ + QMI_M1_WFMT_DATA_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_WFMT_DATA_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_WFMT_DATA_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_WFMT_DATA_WIDTH_Enum; + +/* ============================================ QMI M1_WFMT DUMMY_WIDTH [6..7] ============================================= */ +typedef enum { /*!< QMI_M1_WFMT_DUMMY_WIDTH */ + QMI_M1_WFMT_DUMMY_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_WFMT_DUMMY_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_WFMT_DUMMY_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_WFMT_DUMMY_WIDTH_Enum; + +/* ============================================ QMI M1_WFMT SUFFIX_WIDTH [4..5] ============================================ */ +typedef enum { /*!< QMI_M1_WFMT_SUFFIX_WIDTH */ + QMI_M1_WFMT_SUFFIX_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_WFMT_SUFFIX_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_WFMT_SUFFIX_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_WFMT_SUFFIX_WIDTH_Enum; + +/* ============================================= QMI M1_WFMT ADDR_WIDTH [2..3] ============================================= */ +typedef enum { /*!< QMI_M1_WFMT_ADDR_WIDTH */ + QMI_M1_WFMT_ADDR_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_WFMT_ADDR_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_WFMT_ADDR_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_WFMT_ADDR_WIDTH_Enum; + +/* ============================================ QMI M1_WFMT PREFIX_WIDTH [0..1] ============================================ */ +typedef enum { /*!< QMI_M1_WFMT_PREFIX_WIDTH */ + QMI_M1_WFMT_PREFIX_WIDTH_S = 0, /*!< S : Single width */ + QMI_M1_WFMT_PREFIX_WIDTH_D = 1, /*!< D : Dual width */ + QMI_M1_WFMT_PREFIX_WIDTH_Q = 2, /*!< Q : Quad width */ +} QMI_M1_WFMT_PREFIX_WIDTH_Enum; + +/* ======================================================== M1_WCMD ======================================================== */ +/* ======================================================== ATRANS0 ======================================================== */ +/* ======================================================== ATRANS1 ======================================================== */ +/* ======================================================== ATRANS2 ======================================================== */ +/* ======================================================== ATRANS3 ======================================================== */ +/* ======================================================== ATRANS4 ======================================================== */ +/* ======================================================== ATRANS5 ======================================================== */ +/* ======================================================== ATRANS6 ======================================================== */ +/* ======================================================== ATRANS7 ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ XIP_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +/* ========================================================= STAT ========================================================== */ +/* ======================================================== CTR_HIT ======================================================== */ +/* ======================================================== CTR_ACC ======================================================== */ +/* ====================================================== STREAM_ADDR ====================================================== */ +/* ====================================================== STREAM_CTR ======================================================= */ +/* ====================================================== STREAM_FIFO ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ XIP_AUX ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== STREAM ========================================================= */ +/* ===================================================== QMI_DIRECT_TX ===================================================== */ +/* ========================================= XIP_AUX QMI_DIRECT_TX IWIDTH [16..17] ========================================= */ +typedef enum { /*!< XIP_AUX_QMI_DIRECT_TX_IWIDTH */ + XIP_AUX_QMI_DIRECT_TX_IWIDTH_S = 0, /*!< S : Single width */ + XIP_AUX_QMI_DIRECT_TX_IWIDTH_D = 1, /*!< D : Dual width */ + XIP_AUX_QMI_DIRECT_TX_IWIDTH_Q = 2, /*!< Q : Quad width */ +} XIP_AUX_QMI_DIRECT_TX_IWIDTH_Enum; + +/* ===================================================== QMI_DIRECT_RX ===================================================== */ + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== PROC_CONFIG ====================================================== */ +/* ================================================== PROC_IN_SYNC_BYPASS ================================================== */ +/* ================================================ PROC_IN_SYNC_BYPASS_HI ================================================= */ +/* ======================================================= DBGFORCE ======================================================== */ +/* ===================================================== MEMPOWERDOWN ====================================================== */ +/* ======================================================== AUXCTRL ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ XOSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +/* =============================================== XOSC CTRL ENABLE [12..23] =============================================== */ +typedef enum { /*!< XOSC_CTRL_ENABLE */ + XOSC_CTRL_ENABLE_DISABLE = 3358, /*!< DISABLE : DISABLE */ + XOSC_CTRL_ENABLE_ENABLE = 4011, /*!< ENABLE : ENABLE */ +} XOSC_CTRL_ENABLE_Enum; + +/* ============================================= XOSC CTRL FREQ_RANGE [0..11] ============================================== */ +typedef enum { /*!< XOSC_CTRL_FREQ_RANGE */ + XOSC_CTRL_FREQ_RANGE_1_15MHZ = 2720, /*!< 1_15MHZ : 1_15MHZ */ + XOSC_CTRL_FREQ_RANGE_10_30MHZ = 2721, /*!< 10_30MHZ : 10_30MHZ */ + XOSC_CTRL_FREQ_RANGE_25_60MHZ = 2722, /*!< 25_60MHZ : 25_60MHZ */ + XOSC_CTRL_FREQ_RANGE_40_100MHZ = 2723, /*!< 40_100MHZ : 40_100MHZ */ +} XOSC_CTRL_FREQ_RANGE_Enum; + +/* ======================================================== STATUS ========================================================= */ +/* ============================================= XOSC STATUS FREQ_RANGE [0..1] ============================================= */ +typedef enum { /*!< XOSC_STATUS_FREQ_RANGE */ + XOSC_STATUS_FREQ_RANGE_1_15MHZ = 0, /*!< 1_15MHZ : 1_15MHZ */ + XOSC_STATUS_FREQ_RANGE_10_30MHZ = 1, /*!< 10_30MHZ : 10_30MHZ */ + XOSC_STATUS_FREQ_RANGE_25_60MHZ = 2, /*!< 25_60MHZ : 25_60MHZ */ + XOSC_STATUS_FREQ_RANGE_40_100MHZ = 3, /*!< 40_100MHZ : 40_100MHZ */ +} XOSC_STATUS_FREQ_RANGE_Enum; + +/* ======================================================== DORMANT ======================================================== */ +/* ============================================= XOSC DORMANT DORMANT [0..31] ============================================== */ +typedef enum { /*!< XOSC_DORMANT_DORMANT */ + XOSC_DORMANT_DORMANT_dormant = 1668246881,/*!< dormant : dormant */ + XOSC_DORMANT_DORMANT_WAKE = 2002873189,/*!< WAKE : WAKE */ +} XOSC_DORMANT_DORMANT_Enum; + +/* ======================================================== STARTUP ======================================================== */ +/* ========================================================= COUNT ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ PLL_SYS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CS =========================================================== */ +/* ========================================================== PWR ========================================================== */ +/* ======================================================= FBDIV_INT ======================================================= */ +/* ========================================================= PRIM ========================================================== */ +/* ========================================================= INTR ========================================================== */ +/* ========================================================= INTE ========================================================== */ +/* ========================================================= INTF ========================================================== */ +/* ========================================================= INTS ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ ACCESSCTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LOCK ========================================================== */ +/* ===================================================== FORCE_CORE_NS ===================================================== */ +/* ======================================================= CFGRESET ======================================================== */ +/* ===================================================== GPIO_NSMASK0 ====================================================== */ +/* ===================================================== GPIO_NSMASK1 ====================================================== */ +/* ========================================================== ROM ========================================================== */ +/* ======================================================= XIP_MAIN ======================================================== */ +/* ========================================================= SRAM0 ========================================================= */ +/* ========================================================= SRAM1 ========================================================= */ +/* ========================================================= SRAM2 ========================================================= */ +/* ========================================================= SRAM3 ========================================================= */ +/* ========================================================= SRAM4 ========================================================= */ +/* ========================================================= SRAM5 ========================================================= */ +/* ========================================================= SRAM6 ========================================================= */ +/* ========================================================= SRAM7 ========================================================= */ +/* ========================================================= SRAM8 ========================================================= */ +/* ========================================================= SRAM9 ========================================================= */ +/* ========================================================== DMA ========================================================== */ +/* ======================================================== USBCTRL ======================================================== */ +/* ========================================================= PIO0 ========================================================== */ +/* ========================================================= PIO1 ========================================================== */ +/* ========================================================= PIO2 ========================================================== */ +/* ==================================================== CORESIGHT_TRACE ==================================================== */ +/* =================================================== CORESIGHT_PERIPH ==================================================== */ +/* ======================================================== SYSINFO ======================================================== */ +/* ======================================================== RESETS ========================================================= */ +/* ======================================================= IO_BANK0 ======================================================== */ +/* ======================================================= IO_BANK1 ======================================================== */ +/* ====================================================== PADS_BANK0 ======================================================= */ +/* ======================================================= PADS_QSPI ======================================================= */ +/* ======================================================== BUSCTRL ======================================================== */ +/* ========================================================= ADC0 ========================================================== */ +/* ========================================================= HSTX ========================================================== */ +/* ========================================================= I2C0 ========================================================== */ +/* ========================================================= I2C1 ========================================================== */ +/* ========================================================== PWM ========================================================== */ +/* ========================================================= SPI0 ========================================================== */ +/* ========================================================= SPI1 ========================================================== */ +/* ======================================================== TIMER0 ========================================================= */ +/* ======================================================== TIMER1 ========================================================= */ +/* ========================================================= UART0 ========================================================= */ +/* ========================================================= UART1 ========================================================= */ +/* ========================================================== OTP ========================================================== */ +/* ========================================================= TBMAN ========================================================= */ +/* ======================================================== POWMAN ========================================================= */ +/* ========================================================= TRNG ========================================================== */ +/* ======================================================== SHA256 ========================================================= */ +/* ======================================================== SYSCFG ========================================================= */ +/* ======================================================== CLOCKS ========================================================= */ +/* ========================================================= XOSC ========================================================== */ +/* ========================================================= ROSC ========================================================== */ +/* ======================================================== PLL_SYS ======================================================== */ +/* ======================================================== PLL_USB ======================================================== */ +/* ========================================================= TICKS ========================================================= */ +/* ======================================================= WATCHDOG ======================================================== */ +/* ========================================================== RSM ========================================================== */ +/* ======================================================= XIP_CTRL ======================================================== */ +/* ======================================================== XIP_QMI ======================================================== */ +/* ======================================================== XIP_AUX ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== UARTDR ========================================================= */ +/* ======================================================== UARTRSR ======================================================== */ +/* ======================================================== UARTFR ========================================================= */ +/* ======================================================= UARTILPR ======================================================== */ +/* ======================================================= UARTIBRD ======================================================== */ +/* ======================================================= UARTFBRD ======================================================== */ +/* ======================================================= UARTLCR_H ======================================================= */ +/* ======================================================== UARTCR ========================================================= */ +/* ======================================================= UARTIFLS ======================================================== */ +/* ======================================================= UARTIMSC ======================================================== */ +/* ======================================================== UARTRIS ======================================================== */ +/* ======================================================== UARTMIS ======================================================== */ +/* ======================================================== UARTICR ======================================================== */ +/* ======================================================= UARTDMACR ======================================================= */ +/* ===================================================== UARTPERIPHID0 ===================================================== */ +/* ===================================================== UARTPERIPHID1 ===================================================== */ +/* ===================================================== UARTPERIPHID2 ===================================================== */ +/* ===================================================== UARTPERIPHID3 ===================================================== */ +/* ===================================================== UARTPCELLID0 ====================================================== */ +/* ===================================================== UARTPCELLID1 ====================================================== */ +/* ===================================================== UARTPCELLID2 ====================================================== */ +/* ===================================================== UARTPCELLID3 ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ ROSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +/* =============================================== ROSC CTRL ENABLE [12..23] =============================================== */ +typedef enum { /*!< ROSC_CTRL_ENABLE */ + ROSC_CTRL_ENABLE_DISABLE = 3358, /*!< DISABLE : DISABLE */ + ROSC_CTRL_ENABLE_ENABLE = 4011, /*!< ENABLE : ENABLE */ +} ROSC_CTRL_ENABLE_Enum; + +/* ============================================= ROSC CTRL FREQ_RANGE [0..11] ============================================== */ +typedef enum { /*!< ROSC_CTRL_FREQ_RANGE */ + ROSC_CTRL_FREQ_RANGE_LOW = 4004, /*!< LOW : LOW */ + ROSC_CTRL_FREQ_RANGE_MEDIUM = 4005, /*!< MEDIUM : MEDIUM */ + ROSC_CTRL_FREQ_RANGE_HIGH = 4007, /*!< HIGH : HIGH */ + ROSC_CTRL_FREQ_RANGE_TOOHIGH = 4006, /*!< TOOHIGH : TOOHIGH */ +} ROSC_CTRL_FREQ_RANGE_Enum; + +/* ========================================================= FREQA ========================================================= */ +/* ============================================== ROSC FREQA PASSWD [16..31] =============================================== */ +typedef enum { /*!< ROSC_FREQA_PASSWD */ + ROSC_FREQA_PASSWD_PASS = 38550, /*!< PASS : PASS */ +} ROSC_FREQA_PASSWD_Enum; + +/* ========================================================= FREQB ========================================================= */ +/* ============================================== ROSC FREQB PASSWD [16..31] =============================================== */ +typedef enum { /*!< ROSC_FREQB_PASSWD */ + ROSC_FREQB_PASSWD_PASS = 38550, /*!< PASS : PASS */ +} ROSC_FREQB_PASSWD_Enum; + +/* ======================================================== RANDOM ========================================================= */ +/* ======================================================== DORMANT ======================================================== */ +/* ============================================= ROSC DORMANT DORMANT [0..31] ============================================== */ +typedef enum { /*!< ROSC_DORMANT_DORMANT */ + ROSC_DORMANT_DORMANT_dormant = 1668246881,/*!< dormant : dormant */ + ROSC_DORMANT_DORMANT_WAKE = 2002873189,/*!< WAKE : WAKE */ +} ROSC_DORMANT_DORMANT_Enum; + +/* ========================================================== DIV ========================================================== */ +/* ================================================= ROSC DIV DIV [0..15] ================================================== */ +typedef enum { /*!< ROSC_DIV_DIV */ + ROSC_DIV_DIV_PASS = 43520, /*!< PASS : PASS */ +} ROSC_DIV_DIV_Enum; + +/* ========================================================= PHASE ========================================================= */ +/* ======================================================== STATUS ========================================================= */ +/* ======================================================= RANDOMBIT ======================================================= */ +/* ========================================================= COUNT ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ POWMAN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= BADPASSWD ======================================================= */ +/* ======================================================= VREG_CTRL ======================================================= */ +/* ======================================================= VREG_STS ======================================================== */ +/* ========================================================= VREG ========================================================== */ +/* ===================================================== VREG_LP_ENTRY ===================================================== */ +/* ===================================================== VREG_LP_EXIT ====================================================== */ +/* ======================================================= BOD_CTRL ======================================================== */ +/* ========================================================== BOD ========================================================== */ +/* ===================================================== BOD_LP_ENTRY ====================================================== */ +/* ====================================================== BOD_LP_EXIT ====================================================== */ +/* ========================================================= LPOSC ========================================================= */ +/* ====================================================== CHIP_RESET ======================================================= */ +/* ========================================================= WDSEL ========================================================= */ +/* ======================================================== SEQ_CFG ======================================================== */ +/* ========================================================= STATE ========================================================= */ +/* ====================================================== POW_FASTDIV ====================================================== */ +/* ======================================================= POW_DELAY ======================================================= */ +/* ======================================================= EXT_CTRL0 ======================================================= */ +/* ======================================================= EXT_CTRL1 ======================================================= */ +/* ===================================================== EXT_TIME_REF ====================================================== */ +/* ================================================== LPOSC_FREQ_KHZ_INT =================================================== */ +/* ================================================== LPOSC_FREQ_KHZ_FRAC ================================================== */ +/* =================================================== XOSC_FREQ_KHZ_INT =================================================== */ +/* ================================================== XOSC_FREQ_KHZ_FRAC =================================================== */ +/* ==================================================== SET_TIME_63TO48 ==================================================== */ +/* ==================================================== SET_TIME_47TO32 ==================================================== */ +/* ==================================================== SET_TIME_31TO16 ==================================================== */ +/* ==================================================== SET_TIME_15TO0 ===================================================== */ +/* ==================================================== READ_TIME_UPPER ==================================================== */ +/* ==================================================== READ_TIME_LOWER ==================================================== */ +/* =================================================== ALARM_TIME_63TO48 =================================================== */ +/* =================================================== ALARM_TIME_47TO32 =================================================== */ +/* =================================================== ALARM_TIME_31TO16 =================================================== */ +/* =================================================== ALARM_TIME_15TO0 ==================================================== */ +/* ========================================================= TIMER ========================================================= */ +/* ======================================================== PWRUP0 ========================================================= */ +/* =============================================== POWMAN PWRUP0 MODE [8..8] =============================================== */ +typedef enum { /*!< POWMAN_PWRUP0_MODE */ + POWMAN_PWRUP0_MODE_level = 0, /*!< level : level */ + POWMAN_PWRUP0_MODE_edge = 1, /*!< edge : edge */ +} POWMAN_PWRUP0_MODE_Enum; + +/* ============================================ POWMAN PWRUP0 DIRECTION [7..7] ============================================= */ +typedef enum { /*!< POWMAN_PWRUP0_DIRECTION */ + POWMAN_PWRUP0_DIRECTION_low_falling = 0, /*!< low_falling : low_falling */ + POWMAN_PWRUP0_DIRECTION_high_rising = 1, /*!< high_rising : high_rising */ +} POWMAN_PWRUP0_DIRECTION_Enum; + +/* ======================================================== PWRUP1 ========================================================= */ +/* =============================================== POWMAN PWRUP1 MODE [8..8] =============================================== */ +typedef enum { /*!< POWMAN_PWRUP1_MODE */ + POWMAN_PWRUP1_MODE_level = 0, /*!< level : level */ + POWMAN_PWRUP1_MODE_edge = 1, /*!< edge : edge */ +} POWMAN_PWRUP1_MODE_Enum; + +/* ============================================ POWMAN PWRUP1 DIRECTION [7..7] ============================================= */ +typedef enum { /*!< POWMAN_PWRUP1_DIRECTION */ + POWMAN_PWRUP1_DIRECTION_low_falling = 0, /*!< low_falling : low_falling */ + POWMAN_PWRUP1_DIRECTION_high_rising = 1, /*!< high_rising : high_rising */ +} POWMAN_PWRUP1_DIRECTION_Enum; + +/* ======================================================== PWRUP2 ========================================================= */ +/* =============================================== POWMAN PWRUP2 MODE [8..8] =============================================== */ +typedef enum { /*!< POWMAN_PWRUP2_MODE */ + POWMAN_PWRUP2_MODE_level = 0, /*!< level : level */ + POWMAN_PWRUP2_MODE_edge = 1, /*!< edge : edge */ +} POWMAN_PWRUP2_MODE_Enum; + +/* ============================================ POWMAN PWRUP2 DIRECTION [7..7] ============================================= */ +typedef enum { /*!< POWMAN_PWRUP2_DIRECTION */ + POWMAN_PWRUP2_DIRECTION_low_falling = 0, /*!< low_falling : low_falling */ + POWMAN_PWRUP2_DIRECTION_high_rising = 1, /*!< high_rising : high_rising */ +} POWMAN_PWRUP2_DIRECTION_Enum; + +/* ======================================================== PWRUP3 ========================================================= */ +/* =============================================== POWMAN PWRUP3 MODE [8..8] =============================================== */ +typedef enum { /*!< POWMAN_PWRUP3_MODE */ + POWMAN_PWRUP3_MODE_level = 0, /*!< level : level */ + POWMAN_PWRUP3_MODE_edge = 1, /*!< edge : edge */ +} POWMAN_PWRUP3_MODE_Enum; + +/* ============================================ POWMAN PWRUP3 DIRECTION [7..7] ============================================= */ +typedef enum { /*!< POWMAN_PWRUP3_DIRECTION */ + POWMAN_PWRUP3_DIRECTION_low_falling = 0, /*!< low_falling : low_falling */ + POWMAN_PWRUP3_DIRECTION_high_rising = 1, /*!< high_rising : high_rising */ +} POWMAN_PWRUP3_DIRECTION_Enum; + +/* =================================================== CURRENT_PWRUP_REQ =================================================== */ +/* =================================================== LAST_SWCORE_PWRUP =================================================== */ +/* ====================================================== DBG_PWRCFG ======================================================= */ +/* ======================================================== BOOTDIS ======================================================== */ +/* ======================================================= DBGCONFIG ======================================================= */ +/* ======================================================= SCRATCH0 ======================================================== */ +/* ======================================================= SCRATCH1 ======================================================== */ +/* ======================================================= SCRATCH2 ======================================================== */ +/* ======================================================= SCRATCH3 ======================================================== */ +/* ======================================================= SCRATCH4 ======================================================== */ +/* ======================================================= SCRATCH5 ======================================================== */ +/* ======================================================= SCRATCH6 ======================================================== */ +/* ======================================================= SCRATCH7 ======================================================== */ +/* ========================================================= BOOT0 ========================================================= */ +/* ========================================================= BOOT1 ========================================================= */ +/* ========================================================= BOOT2 ========================================================= */ +/* ========================================================= BOOT3 ========================================================= */ +/* ========================================================= INTR ========================================================== */ +/* ========================================================= INTE ========================================================== */ +/* ========================================================= INTF ========================================================== */ +/* ========================================================= INTS ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ WATCHDOG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +/* ========================================================= LOAD ========================================================== */ +/* ======================================================== REASON ========================================================= */ +/* ======================================================= SCRATCH0 ======================================================== */ +/* ======================================================= SCRATCH1 ======================================================== */ +/* ======================================================= SCRATCH2 ======================================================== */ +/* ======================================================= SCRATCH3 ======================================================== */ +/* ======================================================= SCRATCH4 ======================================================== */ +/* ======================================================= SCRATCH5 ======================================================== */ +/* ======================================================= SCRATCH6 ======================================================== */ +/* ======================================================= SCRATCH7 ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== CH0_READ_ADDR ===================================================== */ +/* ==================================================== CH0_WRITE_ADDR ===================================================== */ +/* ==================================================== CH0_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH0_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH0_TRANS_COUNT_MODE */ + DMA_CH0_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH0_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH0_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH0_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH0_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH0_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH0_CTRL_TRIG_TREQ_SEL */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH0_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH0_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH0_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH0_CTRL_TRIG_RING_SIZE */ + DMA_CH0_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH0_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH0_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH0_CTRL_TRIG_DATA_SIZE */ + DMA_CH0_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH0_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH0_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH0_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH0_AL1_CTRL ====================================================== */ +/* =================================================== CH0_AL1_READ_ADDR =================================================== */ +/* ================================================== CH0_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH0_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH0_AL2_CTRL ====================================================== */ +/* ================================================== CH0_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH0_AL2_READ_ADDR =================================================== */ +/* ================================================ CH0_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH0_AL3_CTRL ====================================================== */ +/* ================================================== CH0_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH0_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH0_AL3_READ_ADDR_TRIG ================================================= */ +/* ===================================================== CH1_READ_ADDR ===================================================== */ +/* ==================================================== CH1_WRITE_ADDR ===================================================== */ +/* ==================================================== CH1_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH1_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH1_TRANS_COUNT_MODE */ + DMA_CH1_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH1_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH1_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH1_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH1_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH1_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH1_CTRL_TRIG_TREQ_SEL */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH1_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH1_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH1_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH1_CTRL_TRIG_RING_SIZE */ + DMA_CH1_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH1_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH1_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH1_CTRL_TRIG_DATA_SIZE */ + DMA_CH1_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH1_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH1_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH1_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH1_AL1_CTRL ====================================================== */ +/* =================================================== CH1_AL1_READ_ADDR =================================================== */ +/* ================================================== CH1_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH1_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH1_AL2_CTRL ====================================================== */ +/* ================================================== CH1_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH1_AL2_READ_ADDR =================================================== */ +/* ================================================ CH1_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH1_AL3_CTRL ====================================================== */ +/* ================================================== CH1_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH1_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH1_AL3_READ_ADDR_TRIG ================================================= */ +/* ===================================================== CH2_READ_ADDR ===================================================== */ +/* ==================================================== CH2_WRITE_ADDR ===================================================== */ +/* ==================================================== CH2_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH2_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH2_TRANS_COUNT_MODE */ + DMA_CH2_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH2_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH2_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH2_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH2_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH2_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH2_CTRL_TRIG_TREQ_SEL */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH2_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH2_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH2_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH2_CTRL_TRIG_RING_SIZE */ + DMA_CH2_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH2_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH2_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH2_CTRL_TRIG_DATA_SIZE */ + DMA_CH2_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH2_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH2_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH2_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH2_AL1_CTRL ====================================================== */ +/* =================================================== CH2_AL1_READ_ADDR =================================================== */ +/* ================================================== CH2_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH2_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH2_AL2_CTRL ====================================================== */ +/* ================================================== CH2_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH2_AL2_READ_ADDR =================================================== */ +/* ================================================ CH2_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH2_AL3_CTRL ====================================================== */ +/* ================================================== CH2_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH2_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH2_AL3_READ_ADDR_TRIG ================================================= */ +/* ===================================================== CH3_READ_ADDR ===================================================== */ +/* ==================================================== CH3_WRITE_ADDR ===================================================== */ +/* ==================================================== CH3_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH3_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH3_TRANS_COUNT_MODE */ + DMA_CH3_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH3_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH3_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH3_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH3_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH3_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH3_CTRL_TRIG_TREQ_SEL */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH3_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH3_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH3_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH3_CTRL_TRIG_RING_SIZE */ + DMA_CH3_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH3_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH3_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH3_CTRL_TRIG_DATA_SIZE */ + DMA_CH3_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH3_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH3_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH3_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH3_AL1_CTRL ====================================================== */ +/* =================================================== CH3_AL1_READ_ADDR =================================================== */ +/* ================================================== CH3_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH3_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH3_AL2_CTRL ====================================================== */ +/* ================================================== CH3_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH3_AL2_READ_ADDR =================================================== */ +/* ================================================ CH3_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH3_AL3_CTRL ====================================================== */ +/* ================================================== CH3_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH3_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH3_AL3_READ_ADDR_TRIG ================================================= */ +/* ===================================================== CH4_READ_ADDR ===================================================== */ +/* ==================================================== CH4_WRITE_ADDR ===================================================== */ +/* ==================================================== CH4_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH4_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH4_TRANS_COUNT_MODE */ + DMA_CH4_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH4_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH4_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH4_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH4_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH4_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH4_CTRL_TRIG_TREQ_SEL */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH4_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH4_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH4_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH4_CTRL_TRIG_RING_SIZE */ + DMA_CH4_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH4_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH4_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH4_CTRL_TRIG_DATA_SIZE */ + DMA_CH4_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH4_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH4_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH4_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH4_AL1_CTRL ====================================================== */ +/* =================================================== CH4_AL1_READ_ADDR =================================================== */ +/* ================================================== CH4_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH4_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH4_AL2_CTRL ====================================================== */ +/* ================================================== CH4_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH4_AL2_READ_ADDR =================================================== */ +/* ================================================ CH4_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH4_AL3_CTRL ====================================================== */ +/* ================================================== CH4_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH4_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH4_AL3_READ_ADDR_TRIG ================================================= */ +/* ===================================================== CH5_READ_ADDR ===================================================== */ +/* ==================================================== CH5_WRITE_ADDR ===================================================== */ +/* ==================================================== CH5_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH5_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH5_TRANS_COUNT_MODE */ + DMA_CH5_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH5_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH5_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH5_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH5_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH5_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH5_CTRL_TRIG_TREQ_SEL */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH5_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH5_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH5_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH5_CTRL_TRIG_RING_SIZE */ + DMA_CH5_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH5_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH5_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH5_CTRL_TRIG_DATA_SIZE */ + DMA_CH5_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH5_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH5_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH5_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH5_AL1_CTRL ====================================================== */ +/* =================================================== CH5_AL1_READ_ADDR =================================================== */ +/* ================================================== CH5_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH5_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH5_AL2_CTRL ====================================================== */ +/* ================================================== CH5_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH5_AL2_READ_ADDR =================================================== */ +/* ================================================ CH5_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH5_AL3_CTRL ====================================================== */ +/* ================================================== CH5_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH5_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH5_AL3_READ_ADDR_TRIG ================================================= */ +/* ===================================================== CH6_READ_ADDR ===================================================== */ +/* ==================================================== CH6_WRITE_ADDR ===================================================== */ +/* ==================================================== CH6_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH6_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH6_TRANS_COUNT_MODE */ + DMA_CH6_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH6_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH6_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH6_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH6_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH6_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH6_CTRL_TRIG_TREQ_SEL */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH6_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH6_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH6_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH6_CTRL_TRIG_RING_SIZE */ + DMA_CH6_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH6_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH6_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH6_CTRL_TRIG_DATA_SIZE */ + DMA_CH6_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH6_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH6_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH6_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH6_AL1_CTRL ====================================================== */ +/* =================================================== CH6_AL1_READ_ADDR =================================================== */ +/* ================================================== CH6_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH6_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH6_AL2_CTRL ====================================================== */ +/* ================================================== CH6_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH6_AL2_READ_ADDR =================================================== */ +/* ================================================ CH6_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH6_AL3_CTRL ====================================================== */ +/* ================================================== CH6_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH6_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH6_AL3_READ_ADDR_TRIG ================================================= */ +/* ===================================================== CH7_READ_ADDR ===================================================== */ +/* ==================================================== CH7_WRITE_ADDR ===================================================== */ +/* ==================================================== CH7_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH7_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH7_TRANS_COUNT_MODE */ + DMA_CH7_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH7_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH7_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH7_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH7_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH7_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH7_CTRL_TRIG_TREQ_SEL */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH7_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH7_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH7_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH7_CTRL_TRIG_RING_SIZE */ + DMA_CH7_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH7_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH7_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH7_CTRL_TRIG_DATA_SIZE */ + DMA_CH7_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH7_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH7_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH7_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH7_AL1_CTRL ====================================================== */ +/* =================================================== CH7_AL1_READ_ADDR =================================================== */ +/* ================================================== CH7_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH7_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH7_AL2_CTRL ====================================================== */ +/* ================================================== CH7_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH7_AL2_READ_ADDR =================================================== */ +/* ================================================ CH7_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH7_AL3_CTRL ====================================================== */ +/* ================================================== CH7_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH7_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH7_AL3_READ_ADDR_TRIG ================================================= */ +/* ===================================================== CH8_READ_ADDR ===================================================== */ +/* ==================================================== CH8_WRITE_ADDR ===================================================== */ +/* ==================================================== CH8_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH8_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH8_TRANS_COUNT_MODE */ + DMA_CH8_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH8_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH8_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH8_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH8_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH8_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH8_CTRL_TRIG_TREQ_SEL */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH8_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH8_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH8_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH8_CTRL_TRIG_RING_SIZE */ + DMA_CH8_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH8_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH8_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH8_CTRL_TRIG_DATA_SIZE */ + DMA_CH8_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH8_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH8_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH8_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH8_AL1_CTRL ====================================================== */ +/* =================================================== CH8_AL1_READ_ADDR =================================================== */ +/* ================================================== CH8_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH8_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH8_AL2_CTRL ====================================================== */ +/* ================================================== CH8_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH8_AL2_READ_ADDR =================================================== */ +/* ================================================ CH8_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH8_AL3_CTRL ====================================================== */ +/* ================================================== CH8_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH8_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH8_AL3_READ_ADDR_TRIG ================================================= */ +/* ===================================================== CH9_READ_ADDR ===================================================== */ +/* ==================================================== CH9_WRITE_ADDR ===================================================== */ +/* ==================================================== CH9_TRANS_COUNT ==================================================== */ +/* =========================================== DMA CH9_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH9_TRANS_COUNT_MODE */ + DMA_CH9_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH9_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH9_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH9_TRANS_COUNT_MODE_Enum; + +/* ===================================================== CH9_CTRL_TRIG ===================================================== */ +/* ========================================== DMA CH9_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH9_CTRL_TRIG_TREQ_SEL */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH9_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH9_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================== DMA CH9_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH9_CTRL_TRIG_RING_SIZE */ + DMA_CH9_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH9_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH9_CTRL_TRIG DATA_SIZE [2..3] =========================================== */ +typedef enum { /*!< DMA_CH9_CTRL_TRIG_DATA_SIZE */ + DMA_CH9_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH9_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH9_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH9_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH9_AL1_CTRL ====================================================== */ +/* =================================================== CH9_AL1_READ_ADDR =================================================== */ +/* ================================================== CH9_AL1_WRITE_ADDR =================================================== */ +/* =============================================== CH9_AL1_TRANS_COUNT_TRIG ================================================ */ +/* ===================================================== CH9_AL2_CTRL ====================================================== */ +/* ================================================== CH9_AL2_TRANS_COUNT ================================================== */ +/* =================================================== CH9_AL2_READ_ADDR =================================================== */ +/* ================================================ CH9_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH9_AL3_CTRL ====================================================== */ +/* ================================================== CH9_AL3_WRITE_ADDR =================================================== */ +/* ================================================== CH9_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH9_AL3_READ_ADDR_TRIG ================================================= */ +/* ==================================================== CH10_READ_ADDR ===================================================== */ +/* ==================================================== CH10_WRITE_ADDR ==================================================== */ +/* =================================================== CH10_TRANS_COUNT ==================================================== */ +/* ========================================== DMA CH10_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH10_TRANS_COUNT_MODE */ + DMA_CH10_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH10_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH10_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH10_TRANS_COUNT_MODE_Enum; + +/* ==================================================== CH10_CTRL_TRIG ===================================================== */ +/* ========================================= DMA CH10_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH10_CTRL_TRIG_TREQ_SEL */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH10_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH10_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================= DMA CH10_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH10_CTRL_TRIG_RING_SIZE */ + DMA_CH10_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH10_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH10_CTRL_TRIG DATA_SIZE [2..3] ========================================== */ +typedef enum { /*!< DMA_CH10_CTRL_TRIG_DATA_SIZE */ + DMA_CH10_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH10_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH10_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH10_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH10_AL1_CTRL ===================================================== */ +/* ================================================== CH10_AL1_READ_ADDR =================================================== */ +/* ================================================== CH10_AL1_WRITE_ADDR ================================================== */ +/* =============================================== CH10_AL1_TRANS_COUNT_TRIG =============================================== */ +/* ===================================================== CH10_AL2_CTRL ===================================================== */ +/* ================================================= CH10_AL2_TRANS_COUNT ================================================== */ +/* ================================================== CH10_AL2_READ_ADDR =================================================== */ +/* =============================================== CH10_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH10_AL3_CTRL ===================================================== */ +/* ================================================== CH10_AL3_WRITE_ADDR ================================================== */ +/* ================================================= CH10_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH10_AL3_READ_ADDR_TRIG ================================================ */ +/* ==================================================== CH11_READ_ADDR ===================================================== */ +/* ==================================================== CH11_WRITE_ADDR ==================================================== */ +/* =================================================== CH11_TRANS_COUNT ==================================================== */ +/* ========================================== DMA CH11_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH11_TRANS_COUNT_MODE */ + DMA_CH11_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH11_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH11_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH11_TRANS_COUNT_MODE_Enum; + +/* ==================================================== CH11_CTRL_TRIG ===================================================== */ +/* ========================================= DMA CH11_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH11_CTRL_TRIG_TREQ_SEL */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH11_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH11_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================= DMA CH11_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH11_CTRL_TRIG_RING_SIZE */ + DMA_CH11_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH11_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH11_CTRL_TRIG DATA_SIZE [2..3] ========================================== */ +typedef enum { /*!< DMA_CH11_CTRL_TRIG_DATA_SIZE */ + DMA_CH11_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH11_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH11_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH11_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH11_AL1_CTRL ===================================================== */ +/* ================================================== CH11_AL1_READ_ADDR =================================================== */ +/* ================================================== CH11_AL1_WRITE_ADDR ================================================== */ +/* =============================================== CH11_AL1_TRANS_COUNT_TRIG =============================================== */ +/* ===================================================== CH11_AL2_CTRL ===================================================== */ +/* ================================================= CH11_AL2_TRANS_COUNT ================================================== */ +/* ================================================== CH11_AL2_READ_ADDR =================================================== */ +/* =============================================== CH11_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH11_AL3_CTRL ===================================================== */ +/* ================================================== CH11_AL3_WRITE_ADDR ================================================== */ +/* ================================================= CH11_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH11_AL3_READ_ADDR_TRIG ================================================ */ +/* ==================================================== CH12_READ_ADDR ===================================================== */ +/* ==================================================== CH12_WRITE_ADDR ==================================================== */ +/* =================================================== CH12_TRANS_COUNT ==================================================== */ +/* ========================================== DMA CH12_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH12_TRANS_COUNT_MODE */ + DMA_CH12_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH12_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH12_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH12_TRANS_COUNT_MODE_Enum; + +/* ==================================================== CH12_CTRL_TRIG ===================================================== */ +/* ========================================= DMA CH12_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH12_CTRL_TRIG_TREQ_SEL */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH12_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH12_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================= DMA CH12_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH12_CTRL_TRIG_RING_SIZE */ + DMA_CH12_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH12_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH12_CTRL_TRIG DATA_SIZE [2..3] ========================================== */ +typedef enum { /*!< DMA_CH12_CTRL_TRIG_DATA_SIZE */ + DMA_CH12_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH12_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH12_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH12_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH12_AL1_CTRL ===================================================== */ +/* ================================================== CH12_AL1_READ_ADDR =================================================== */ +/* ================================================== CH12_AL1_WRITE_ADDR ================================================== */ +/* =============================================== CH12_AL1_TRANS_COUNT_TRIG =============================================== */ +/* ===================================================== CH12_AL2_CTRL ===================================================== */ +/* ================================================= CH12_AL2_TRANS_COUNT ================================================== */ +/* ================================================== CH12_AL2_READ_ADDR =================================================== */ +/* =============================================== CH12_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH12_AL3_CTRL ===================================================== */ +/* ================================================== CH12_AL3_WRITE_ADDR ================================================== */ +/* ================================================= CH12_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH12_AL3_READ_ADDR_TRIG ================================================ */ +/* ==================================================== CH13_READ_ADDR ===================================================== */ +/* ==================================================== CH13_WRITE_ADDR ==================================================== */ +/* =================================================== CH13_TRANS_COUNT ==================================================== */ +/* ========================================== DMA CH13_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH13_TRANS_COUNT_MODE */ + DMA_CH13_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH13_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH13_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH13_TRANS_COUNT_MODE_Enum; + +/* ==================================================== CH13_CTRL_TRIG ===================================================== */ +/* ========================================= DMA CH13_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH13_CTRL_TRIG_TREQ_SEL */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH13_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH13_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================= DMA CH13_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH13_CTRL_TRIG_RING_SIZE */ + DMA_CH13_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH13_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH13_CTRL_TRIG DATA_SIZE [2..3] ========================================== */ +typedef enum { /*!< DMA_CH13_CTRL_TRIG_DATA_SIZE */ + DMA_CH13_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH13_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH13_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH13_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH13_AL1_CTRL ===================================================== */ +/* ================================================== CH13_AL1_READ_ADDR =================================================== */ +/* ================================================== CH13_AL1_WRITE_ADDR ================================================== */ +/* =============================================== CH13_AL1_TRANS_COUNT_TRIG =============================================== */ +/* ===================================================== CH13_AL2_CTRL ===================================================== */ +/* ================================================= CH13_AL2_TRANS_COUNT ================================================== */ +/* ================================================== CH13_AL2_READ_ADDR =================================================== */ +/* =============================================== CH13_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH13_AL3_CTRL ===================================================== */ +/* ================================================== CH13_AL3_WRITE_ADDR ================================================== */ +/* ================================================= CH13_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH13_AL3_READ_ADDR_TRIG ================================================ */ +/* ==================================================== CH14_READ_ADDR ===================================================== */ +/* ==================================================== CH14_WRITE_ADDR ==================================================== */ +/* =================================================== CH14_TRANS_COUNT ==================================================== */ +/* ========================================== DMA CH14_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH14_TRANS_COUNT_MODE */ + DMA_CH14_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH14_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH14_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH14_TRANS_COUNT_MODE_Enum; + +/* ==================================================== CH14_CTRL_TRIG ===================================================== */ +/* ========================================= DMA CH14_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH14_CTRL_TRIG_TREQ_SEL */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH14_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH14_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================= DMA CH14_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH14_CTRL_TRIG_RING_SIZE */ + DMA_CH14_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH14_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH14_CTRL_TRIG DATA_SIZE [2..3] ========================================== */ +typedef enum { /*!< DMA_CH14_CTRL_TRIG_DATA_SIZE */ + DMA_CH14_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH14_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH14_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH14_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH14_AL1_CTRL ===================================================== */ +/* ================================================== CH14_AL1_READ_ADDR =================================================== */ +/* ================================================== CH14_AL1_WRITE_ADDR ================================================== */ +/* =============================================== CH14_AL1_TRANS_COUNT_TRIG =============================================== */ +/* ===================================================== CH14_AL2_CTRL ===================================================== */ +/* ================================================= CH14_AL2_TRANS_COUNT ================================================== */ +/* ================================================== CH14_AL2_READ_ADDR =================================================== */ +/* =============================================== CH14_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH14_AL3_CTRL ===================================================== */ +/* ================================================== CH14_AL3_WRITE_ADDR ================================================== */ +/* ================================================= CH14_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH14_AL3_READ_ADDR_TRIG ================================================ */ +/* ==================================================== CH15_READ_ADDR ===================================================== */ +/* ==================================================== CH15_WRITE_ADDR ==================================================== */ +/* =================================================== CH15_TRANS_COUNT ==================================================== */ +/* ========================================== DMA CH15_TRANS_COUNT MODE [28..31] =========================================== */ +typedef enum { /*!< DMA_CH15_TRANS_COUNT_MODE */ + DMA_CH15_TRANS_COUNT_MODE_NORMAL = 0, /*!< NORMAL : NORMAL */ + DMA_CH15_TRANS_COUNT_MODE_TRIGGER_SELF = 1, /*!< TRIGGER_SELF : TRIGGER_SELF */ + DMA_CH15_TRANS_COUNT_MODE_ENDLESS = 15, /*!< ENDLESS : ENDLESS */ +} DMA_CH15_TRANS_COUNT_MODE_Enum; + +/* ==================================================== CH15_CTRL_TRIG ===================================================== */ +/* ========================================= DMA CH15_CTRL_TRIG TREQ_SEL [17..22] ========================================== */ +typedef enum { /*!< DMA_CH15_CTRL_TRIG_TREQ_SEL */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO0_TX0 = 0, /*!< PIO0_TX0 : Select PIO0's TX FIFO 0 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO0_TX1 = 1, /*!< PIO0_TX1 : Select PIO0's TX FIFO 1 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO0_TX2 = 2, /*!< PIO0_TX2 : Select PIO0's TX FIFO 2 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO0_TX3 = 3, /*!< PIO0_TX3 : Select PIO0's TX FIFO 3 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO0_RX0 = 4, /*!< PIO0_RX0 : Select PIO0's RX FIFO 0 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO0_RX1 = 5, /*!< PIO0_RX1 : Select PIO0's RX FIFO 1 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO0_RX2 = 6, /*!< PIO0_RX2 : Select PIO0's RX FIFO 2 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO0_RX3 = 7, /*!< PIO0_RX3 : Select PIO0's RX FIFO 3 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO1_TX0 = 8, /*!< PIO1_TX0 : Select PIO1's TX FIFO 0 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO1_TX1 = 9, /*!< PIO1_TX1 : Select PIO1's TX FIFO 1 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO1_TX2 = 10, /*!< PIO1_TX2 : Select PIO1's TX FIFO 2 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO1_TX3 = 11, /*!< PIO1_TX3 : Select PIO1's TX FIFO 3 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO1_RX0 = 12, /*!< PIO1_RX0 : Select PIO1's RX FIFO 0 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO1_RX1 = 13, /*!< PIO1_RX1 : Select PIO1's RX FIFO 1 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO1_RX2 = 14, /*!< PIO1_RX2 : Select PIO1's RX FIFO 2 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO1_RX3 = 15, /*!< PIO1_RX3 : Select PIO1's RX FIFO 3 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO2_TX0 = 16, /*!< PIO2_TX0 : Select PIO2's TX FIFO 0 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO2_TX1 = 17, /*!< PIO2_TX1 : Select PIO2's TX FIFO 1 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO2_TX2 = 18, /*!< PIO2_TX2 : Select PIO2's TX FIFO 2 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO2_TX3 = 19, /*!< PIO2_TX3 : Select PIO2's TX FIFO 3 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO2_RX0 = 20, /*!< PIO2_RX0 : Select PIO2's RX FIFO 0 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO2_RX1 = 21, /*!< PIO2_RX1 : Select PIO2's RX FIFO 1 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO2_RX2 = 22, /*!< PIO2_RX2 : Select PIO2's RX FIFO 2 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PIO2_RX3 = 23, /*!< PIO2_RX3 : Select PIO2's RX FIFO 3 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_SPI0_TX = 24, /*!< SPI0_TX : Select SPI0's TX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_SPI0_RX = 25, /*!< SPI0_RX : Select SPI0's RX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_SPI1_TX = 26, /*!< SPI1_TX : Select SPI1's TX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_SPI1_RX = 27, /*!< SPI1_RX : Select SPI1's RX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_UART0_TX = 28, /*!< UART0_TX : Select UART0's TX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_UART0_RX = 29, /*!< UART0_RX : Select UART0's RX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_UART1_TX = 30, /*!< UART1_TX : Select UART1's TX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_UART1_RX = 31, /*!< UART1_RX : Select UART1's RX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP0 = 32, /*!< PWM_WRAP0 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP1 = 33, /*!< PWM_WRAP1 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP2 = 34, /*!< PWM_WRAP2 : Select PWM Counter 2's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP3 = 35, /*!< PWM_WRAP3 : Select PWM Counter 3's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP4 = 36, /*!< PWM_WRAP4 : Select PWM Counter 4's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP5 = 37, /*!< PWM_WRAP5 : Select PWM Counter 5's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP6 = 38, /*!< PWM_WRAP6 : Select PWM Counter 6's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP7 = 39, /*!< PWM_WRAP7 : Select PWM Counter 7's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP8 = 40, /*!< PWM_WRAP8 : Select PWM Counter 8's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP9 = 41, /*!< PWM_WRAP9 : Select PWM Counter 9's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP10 = 42, /*!< PWM_WRAP10 : Select PWM Counter 0's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PWM_WRAP11 = 43, /*!< PWM_WRAP11 : Select PWM Counter 1's Wrap Value as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_I2C0_TX = 44, /*!< I2C0_TX : Select I2C0's TX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_I2C0_RX = 45, /*!< I2C0_RX : Select I2C0's RX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_I2C1_TX = 46, /*!< I2C1_TX : Select I2C1's TX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_I2C1_RX = 47, /*!< I2C1_RX : Select I2C1's RX FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_ADC = 48, /*!< ADC : Select the ADC as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_XIP_STREAM = 49, /*!< XIP_STREAM : Select the XIP Streaming FIFO as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_XIP_QMITX = 50, /*!< XIP_QMITX : Select XIP_QMITX as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_XIP_QMIRX = 51, /*!< XIP_QMIRX : Select XIP_QMIRX as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_HSTX = 52, /*!< HSTX : Select HSTX as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_CORESIGHT = 53, /*!< CORESIGHT : Select CORESIGHT as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_SHA256 = 54, /*!< SHA256 : Select SHA256 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */ + DMA_CH15_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */ +} DMA_CH15_CTRL_TRIG_TREQ_SEL_Enum; + +/* ========================================= DMA CH15_CTRL_TRIG RING_SIZE [8..11] ========================================== */ +typedef enum { /*!< DMA_CH15_CTRL_TRIG_RING_SIZE */ + DMA_CH15_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */ +} DMA_CH15_CTRL_TRIG_RING_SIZE_Enum; + +/* ========================================== DMA CH15_CTRL_TRIG DATA_SIZE [2..3] ========================================== */ +typedef enum { /*!< DMA_CH15_CTRL_TRIG_DATA_SIZE */ + DMA_CH15_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */ + DMA_CH15_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */ + DMA_CH15_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */ +} DMA_CH15_CTRL_TRIG_DATA_SIZE_Enum; + +/* ===================================================== CH15_AL1_CTRL ===================================================== */ +/* ================================================== CH15_AL1_READ_ADDR =================================================== */ +/* ================================================== CH15_AL1_WRITE_ADDR ================================================== */ +/* =============================================== CH15_AL1_TRANS_COUNT_TRIG =============================================== */ +/* ===================================================== CH15_AL2_CTRL ===================================================== */ +/* ================================================= CH15_AL2_TRANS_COUNT ================================================== */ +/* ================================================== CH15_AL2_READ_ADDR =================================================== */ +/* =============================================== CH15_AL2_WRITE_ADDR_TRIG ================================================ */ +/* ===================================================== CH15_AL3_CTRL ===================================================== */ +/* ================================================== CH15_AL3_WRITE_ADDR ================================================== */ +/* ================================================= CH15_AL3_TRANS_COUNT ================================================== */ +/* ================================================ CH15_AL3_READ_ADDR_TRIG ================================================ */ +/* ========================================================= INTR ========================================================== */ +/* ========================================================= INTE0 ========================================================= */ +/* ========================================================= INTF0 ========================================================= */ +/* ========================================================= INTS0 ========================================================= */ +/* ========================================================= INTR1 ========================================================= */ +/* ========================================================= INTE1 ========================================================= */ +/* ========================================================= INTF1 ========================================================= */ +/* ========================================================= INTS1 ========================================================= */ +/* ========================================================= INTR2 ========================================================= */ +/* ========================================================= INTE2 ========================================================= */ +/* ========================================================= INTF2 ========================================================= */ +/* ========================================================= INTS2 ========================================================= */ +/* ========================================================= INTR3 ========================================================= */ +/* ========================================================= INTE3 ========================================================= */ +/* ========================================================= INTF3 ========================================================= */ +/* ========================================================= INTS3 ========================================================= */ +/* ======================================================== TIMER0 ========================================================= */ +/* ======================================================== TIMER1 ========================================================= */ +/* ======================================================== TIMER2 ========================================================= */ +/* ======================================================== TIMER3 ========================================================= */ +/* ================================================== MULTI_CHAN_TRIGGER =================================================== */ +/* ====================================================== SNIFF_CTRL ======================================================= */ +/* ============================================== DMA SNIFF_CTRL CALC [5..8] =============================================== */ +typedef enum { /*!< DMA_SNIFF_CTRL_CALC */ + DMA_SNIFF_CTRL_CALC_CRC32 = 0, /*!< CRC32 : Calculate a CRC-32 (IEEE802.3 polynomial) */ + DMA_SNIFF_CTRL_CALC_CRC32R = 1, /*!< CRC32R : Calculate a CRC-32 (IEEE802.3 polynomial) with bit + reversed data */ + DMA_SNIFF_CTRL_CALC_CRC16 = 2, /*!< CRC16 : Calculate a CRC-16-CCITT */ + DMA_SNIFF_CTRL_CALC_CRC16R = 3, /*!< CRC16R : Calculate a CRC-16-CCITT with bit reversed data */ + DMA_SNIFF_CTRL_CALC_EVEN = 14, /*!< EVEN : XOR reduction over all data. == 1 if the total 1 population + count is odd. */ + DMA_SNIFF_CTRL_CALC_SUM = 15, /*!< SUM : Calculate a simple 32-bit checksum (addition with a 32 + bit accumulator) */ +} DMA_SNIFF_CTRL_CALC_Enum; + +/* ====================================================== SNIFF_DATA ======================================================= */ +/* ====================================================== FIFO_LEVELS ====================================================== */ +/* ====================================================== CHAN_ABORT ======================================================= */ +/* ====================================================== N_CHANNELS ======================================================= */ +/* ====================================================== SECCFG_CH0 ======================================================= */ +/* ====================================================== SECCFG_CH1 ======================================================= */ +/* ====================================================== SECCFG_CH2 ======================================================= */ +/* ====================================================== SECCFG_CH3 ======================================================= */ +/* ====================================================== SECCFG_CH4 ======================================================= */ +/* ====================================================== SECCFG_CH5 ======================================================= */ +/* ====================================================== SECCFG_CH6 ======================================================= */ +/* ====================================================== SECCFG_CH7 ======================================================= */ +/* ====================================================== SECCFG_CH8 ======================================================= */ +/* ====================================================== SECCFG_CH9 ======================================================= */ +/* ====================================================== SECCFG_CH10 ====================================================== */ +/* ====================================================== SECCFG_CH11 ====================================================== */ +/* ====================================================== SECCFG_CH12 ====================================================== */ +/* ====================================================== SECCFG_CH13 ====================================================== */ +/* ====================================================== SECCFG_CH14 ====================================================== */ +/* ====================================================== SECCFG_CH15 ====================================================== */ +/* ====================================================== SECCFG_IRQ0 ====================================================== */ +/* ====================================================== SECCFG_IRQ1 ====================================================== */ +/* ====================================================== SECCFG_IRQ2 ====================================================== */ +/* ====================================================== SECCFG_IRQ3 ====================================================== */ +/* ====================================================== SECCFG_MISC ====================================================== */ +/* ======================================================= MPU_CTRL ======================================================== */ +/* ======================================================= MPU_BAR0 ======================================================== */ +/* ======================================================= MPU_LAR0 ======================================================== */ +/* ======================================================= MPU_BAR1 ======================================================== */ +/* ======================================================= MPU_LAR1 ======================================================== */ +/* ======================================================= MPU_BAR2 ======================================================== */ +/* ======================================================= MPU_LAR2 ======================================================== */ +/* ======================================================= MPU_BAR3 ======================================================== */ +/* ======================================================= MPU_LAR3 ======================================================== */ +/* ======================================================= MPU_BAR4 ======================================================== */ +/* ======================================================= MPU_LAR4 ======================================================== */ +/* ======================================================= MPU_BAR5 ======================================================== */ +/* ======================================================= MPU_LAR5 ======================================================== */ +/* ======================================================= MPU_BAR6 ======================================================== */ +/* ======================================================= MPU_LAR6 ======================================================== */ +/* ======================================================= MPU_BAR7 ======================================================== */ +/* ======================================================= MPU_LAR7 ======================================================== */ +/* ==================================================== CH0_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH0_DBG_TCR ====================================================== */ +/* ==================================================== CH1_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH1_DBG_TCR ====================================================== */ +/* ==================================================== CH2_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH2_DBG_TCR ====================================================== */ +/* ==================================================== CH3_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH3_DBG_TCR ====================================================== */ +/* ==================================================== CH4_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH4_DBG_TCR ====================================================== */ +/* ==================================================== CH5_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH5_DBG_TCR ====================================================== */ +/* ==================================================== CH6_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH6_DBG_TCR ====================================================== */ +/* ==================================================== CH7_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH7_DBG_TCR ====================================================== */ +/* ==================================================== CH8_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH8_DBG_TCR ====================================================== */ +/* ==================================================== CH9_DBG_CTDREQ ===================================================== */ +/* ====================================================== CH9_DBG_TCR ====================================================== */ +/* ==================================================== CH10_DBG_CTDREQ ==================================================== */ +/* ===================================================== CH10_DBG_TCR ====================================================== */ +/* ==================================================== CH11_DBG_CTDREQ ==================================================== */ +/* ===================================================== CH11_DBG_TCR ====================================================== */ +/* ==================================================== CH12_DBG_CTDREQ ==================================================== */ +/* ===================================================== CH12_DBG_TCR ====================================================== */ +/* ==================================================== CH13_DBG_CTDREQ ==================================================== */ +/* ===================================================== CH13_DBG_TCR ====================================================== */ +/* ==================================================== CH14_DBG_CTDREQ ==================================================== */ +/* ===================================================== CH14_DBG_TCR ====================================================== */ +/* ==================================================== CH15_DBG_CTDREQ ==================================================== */ +/* ===================================================== CH15_DBG_TCR ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TIMEHW ========================================================= */ +/* ======================================================== TIMELW ========================================================= */ +/* ======================================================== TIMEHR ========================================================= */ +/* ======================================================== TIMELR ========================================================= */ +/* ======================================================== ALARM0 ========================================================= */ +/* ======================================================== ALARM1 ========================================================= */ +/* ======================================================== ALARM2 ========================================================= */ +/* ======================================================== ALARM3 ========================================================= */ +/* ========================================================= ARMED ========================================================= */ +/* ======================================================= TIMERAWH ======================================================== */ +/* ======================================================= TIMERAWL ======================================================== */ +/* ======================================================= DBGPAUSE ======================================================== */ +/* ========================================================= PAUSE ========================================================= */ +/* ======================================================== LOCKED ========================================================= */ +/* ======================================================== SOURCE ========================================================= */ +/* ============================================= TIMER0 SOURCE CLK_SYS [0..0] ============================================== */ +typedef enum { /*!< TIMER0_SOURCE_CLK_SYS */ + TIMER0_SOURCE_CLK_SYS_TICK = 0, /*!< TICK : TICK */ + TIMER0_SOURCE_CLK_SYS_CLK_SYS = 1, /*!< CLK_SYS : CLK_SYS */ +} TIMER0_SOURCE_CLK_SYS_Enum; + +/* ========================================================= INTR ========================================================== */ +/* ========================================================= INTE ========================================================== */ +/* ========================================================= INTF ========================================================== */ +/* ========================================================= INTS ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CH0_CSR ======================================================== */ +/* ============================================== PWM CH0_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH0_CSR_DIVMODE */ + PWM_CH0_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH0_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH0_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH0_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH0_CSR_DIVMODE_Enum; + +/* ======================================================== CH0_DIV ======================================================== */ +/* ======================================================== CH0_CTR ======================================================== */ +/* ======================================================== CH0_CC ========================================================= */ +/* ======================================================== CH0_TOP ======================================================== */ +/* ======================================================== CH1_CSR ======================================================== */ +/* ============================================== PWM CH1_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH1_CSR_DIVMODE */ + PWM_CH1_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH1_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH1_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH1_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH1_CSR_DIVMODE_Enum; + +/* ======================================================== CH1_DIV ======================================================== */ +/* ======================================================== CH1_CTR ======================================================== */ +/* ======================================================== CH1_CC ========================================================= */ +/* ======================================================== CH1_TOP ======================================================== */ +/* ======================================================== CH2_CSR ======================================================== */ +/* ============================================== PWM CH2_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH2_CSR_DIVMODE */ + PWM_CH2_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH2_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH2_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH2_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH2_CSR_DIVMODE_Enum; + +/* ======================================================== CH2_DIV ======================================================== */ +/* ======================================================== CH2_CTR ======================================================== */ +/* ======================================================== CH2_CC ========================================================= */ +/* ======================================================== CH2_TOP ======================================================== */ +/* ======================================================== CH3_CSR ======================================================== */ +/* ============================================== PWM CH3_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH3_CSR_DIVMODE */ + PWM_CH3_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH3_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH3_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH3_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH3_CSR_DIVMODE_Enum; + +/* ======================================================== CH3_DIV ======================================================== */ +/* ======================================================== CH3_CTR ======================================================== */ +/* ======================================================== CH3_CC ========================================================= */ +/* ======================================================== CH3_TOP ======================================================== */ +/* ======================================================== CH4_CSR ======================================================== */ +/* ============================================== PWM CH4_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH4_CSR_DIVMODE */ + PWM_CH4_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH4_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH4_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH4_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH4_CSR_DIVMODE_Enum; + +/* ======================================================== CH4_DIV ======================================================== */ +/* ======================================================== CH4_CTR ======================================================== */ +/* ======================================================== CH4_CC ========================================================= */ +/* ======================================================== CH4_TOP ======================================================== */ +/* ======================================================== CH5_CSR ======================================================== */ +/* ============================================== PWM CH5_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH5_CSR_DIVMODE */ + PWM_CH5_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH5_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH5_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH5_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH5_CSR_DIVMODE_Enum; + +/* ======================================================== CH5_DIV ======================================================== */ +/* ======================================================== CH5_CTR ======================================================== */ +/* ======================================================== CH5_CC ========================================================= */ +/* ======================================================== CH5_TOP ======================================================== */ +/* ======================================================== CH6_CSR ======================================================== */ +/* ============================================== PWM CH6_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH6_CSR_DIVMODE */ + PWM_CH6_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH6_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH6_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH6_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH6_CSR_DIVMODE_Enum; + +/* ======================================================== CH6_DIV ======================================================== */ +/* ======================================================== CH6_CTR ======================================================== */ +/* ======================================================== CH6_CC ========================================================= */ +/* ======================================================== CH6_TOP ======================================================== */ +/* ======================================================== CH7_CSR ======================================================== */ +/* ============================================== PWM CH7_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH7_CSR_DIVMODE */ + PWM_CH7_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH7_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH7_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH7_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH7_CSR_DIVMODE_Enum; + +/* ======================================================== CH7_DIV ======================================================== */ +/* ======================================================== CH7_CTR ======================================================== */ +/* ======================================================== CH7_CC ========================================================= */ +/* ======================================================== CH7_TOP ======================================================== */ +/* ======================================================== CH8_CSR ======================================================== */ +/* ============================================== PWM CH8_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH8_CSR_DIVMODE */ + PWM_CH8_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH8_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH8_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH8_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH8_CSR_DIVMODE_Enum; + +/* ======================================================== CH8_DIV ======================================================== */ +/* ======================================================== CH8_CTR ======================================================== */ +/* ======================================================== CH8_CC ========================================================= */ +/* ======================================================== CH8_TOP ======================================================== */ +/* ======================================================== CH9_CSR ======================================================== */ +/* ============================================== PWM CH9_CSR DIVMODE [4..5] =============================================== */ +typedef enum { /*!< PWM_CH9_CSR_DIVMODE */ + PWM_CH9_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH9_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH9_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH9_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH9_CSR_DIVMODE_Enum; + +/* ======================================================== CH9_DIV ======================================================== */ +/* ======================================================== CH9_CTR ======================================================== */ +/* ======================================================== CH9_CC ========================================================= */ +/* ======================================================== CH9_TOP ======================================================== */ +/* ======================================================= CH10_CSR ======================================================== */ +/* ============================================== PWM CH10_CSR DIVMODE [4..5] ============================================== */ +typedef enum { /*!< PWM_CH10_CSR_DIVMODE */ + PWM_CH10_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH10_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH10_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH10_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH10_CSR_DIVMODE_Enum; + +/* ======================================================= CH10_DIV ======================================================== */ +/* ======================================================= CH10_CTR ======================================================== */ +/* ======================================================== CH10_CC ======================================================== */ +/* ======================================================= CH10_TOP ======================================================== */ +/* ======================================================= CH11_CSR ======================================================== */ +/* ============================================== PWM CH11_CSR DIVMODE [4..5] ============================================== */ +typedef enum { /*!< PWM_CH11_CSR_DIVMODE */ + PWM_CH11_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */ + PWM_CH11_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */ + PWM_CH11_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */ + PWM_CH11_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B + pin. */ +} PWM_CH11_CSR_DIVMODE_Enum; + +/* ======================================================= CH11_DIV ======================================================== */ +/* ======================================================= CH11_CTR ======================================================== */ +/* ======================================================== CH11_CC ======================================================== */ +/* ======================================================= CH11_TOP ======================================================== */ +/* ========================================================== EN =========================================================== */ +/* ========================================================= INTR ========================================================== */ +/* ======================================================= IRQ0_INTE ======================================================= */ +/* ======================================================= IRQ0_INTF ======================================================= */ +/* ======================================================= IRQ0_INTS ======================================================= */ +/* ======================================================= IRQ1_INTE ======================================================= */ +/* ======================================================= IRQ1_INTF ======================================================= */ +/* ======================================================= IRQ1_INTS ======================================================= */ + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CS =========================================================== */ +/* ======================================================== RESULT ========================================================= */ +/* ========================================================== FCS ========================================================== */ +/* ========================================================= FIFO ========================================================== */ +/* ========================================================== DIV ========================================================== */ +/* ========================================================= INTR ========================================================== */ +/* ========================================================= INTE ========================================================== */ +/* ========================================================= INTF ========================================================== */ +/* ========================================================= INTS ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IC_CON ========================================================= */ +/* ======================================= I2C0 IC_CON RX_FIFO_FULL_HLD_CTRL [9..9] ======================================== */ +typedef enum { /*!< I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL */ + I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_DISABLED = 0,/*!< DISABLED : Overflow when RX_FIFO is full */ + I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_ENABLED = 1,/*!< ENABLED : Hold bus when RX_FIFO is full */ +} I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_Enum; + +/* =========================================== I2C0 IC_CON TX_EMPTY_CTRL [8..8] ============================================ */ +typedef enum { /*!< I2C0_IC_CON_TX_EMPTY_CTRL */ + I2C0_IC_CON_TX_EMPTY_CTRL_DISABLED = 0, /*!< DISABLED : Default behaviour of TX_EMPTY interrupt */ + I2C0_IC_CON_TX_EMPTY_CTRL_ENABLED = 1, /*!< ENABLED : Controlled generation of TX_EMPTY interrupt */ +} I2C0_IC_CON_TX_EMPTY_CTRL_Enum; + +/* ======================================== I2C0 IC_CON STOP_DET_IFADDRESSED [7..7] ======================================== */ +typedef enum { /*!< I2C0_IC_CON_STOP_DET_IFADDRESSED */ + I2C0_IC_CON_STOP_DET_IFADDRESSED_DISABLED = 0,/*!< DISABLED : slave issues STOP_DET intr always */ + I2C0_IC_CON_STOP_DET_IFADDRESSED_ENABLED = 1, /*!< ENABLED : slave issues STOP_DET intr only if addressed */ +} I2C0_IC_CON_STOP_DET_IFADDRESSED_Enum; + +/* ========================================== I2C0 IC_CON IC_SLAVE_DISABLE [6..6] ========================================== */ +typedef enum { /*!< I2C0_IC_CON_IC_SLAVE_DISABLE */ + I2C0_IC_CON_IC_SLAVE_DISABLE_SLAVE_ENABLED = 0,/*!< SLAVE_ENABLED : Slave mode is enabled */ + I2C0_IC_CON_IC_SLAVE_DISABLE_SLAVE_DISABLED = 1,/*!< SLAVE_DISABLED : Slave mode is disabled */ +} I2C0_IC_CON_IC_SLAVE_DISABLE_Enum; + +/* =========================================== I2C0 IC_CON IC_RESTART_EN [5..5] ============================================ */ +typedef enum { /*!< I2C0_IC_CON_IC_RESTART_EN */ + I2C0_IC_CON_IC_RESTART_EN_DISABLED = 0, /*!< DISABLED : Master restart disabled */ + I2C0_IC_CON_IC_RESTART_EN_ENABLED = 1, /*!< ENABLED : Master restart enabled */ +} I2C0_IC_CON_IC_RESTART_EN_Enum; + +/* ======================================== I2C0 IC_CON IC_10BITADDR_MASTER [4..4] ========================================= */ +typedef enum { /*!< I2C0_IC_CON_IC_10BITADDR_MASTER */ + I2C0_IC_CON_IC_10BITADDR_MASTER_ADDR_7BITS = 0,/*!< ADDR_7BITS : Master 7Bit addressing mode */ + I2C0_IC_CON_IC_10BITADDR_MASTER_ADDR_10BITS = 1,/*!< ADDR_10BITS : Master 10Bit addressing mode */ +} I2C0_IC_CON_IC_10BITADDR_MASTER_Enum; + +/* ========================================= I2C0 IC_CON IC_10BITADDR_SLAVE [3..3] ========================================= */ +typedef enum { /*!< I2C0_IC_CON_IC_10BITADDR_SLAVE */ + I2C0_IC_CON_IC_10BITADDR_SLAVE_ADDR_7BITS = 0,/*!< ADDR_7BITS : Slave 7Bit addressing */ + I2C0_IC_CON_IC_10BITADDR_SLAVE_ADDR_10BITS = 1,/*!< ADDR_10BITS : Slave 10Bit addressing */ +} I2C0_IC_CON_IC_10BITADDR_SLAVE_Enum; + +/* =============================================== I2C0 IC_CON SPEED [1..2] ================================================ */ +typedef enum { /*!< I2C0_IC_CON_SPEED */ + I2C0_IC_CON_SPEED_STANDARD = 1, /*!< STANDARD : Standard Speed mode of operation */ + I2C0_IC_CON_SPEED_FAST = 2, /*!< FAST : Fast or Fast Plus mode of operation */ + I2C0_IC_CON_SPEED_HIGH = 3, /*!< HIGH : High Speed mode of operation */ +} I2C0_IC_CON_SPEED_Enum; + +/* ============================================ I2C0 IC_CON MASTER_MODE [0..0] ============================================= */ +typedef enum { /*!< I2C0_IC_CON_MASTER_MODE */ + I2C0_IC_CON_MASTER_MODE_DISABLED = 0, /*!< DISABLED : Master mode is disabled */ + I2C0_IC_CON_MASTER_MODE_ENABLED = 1, /*!< ENABLED : Master mode is enabled */ +} I2C0_IC_CON_MASTER_MODE_Enum; + +/* ======================================================== IC_TAR ========================================================= */ +/* ============================================= I2C0 IC_TAR SPECIAL [11..11] ============================================== */ +typedef enum { /*!< I2C0_IC_TAR_SPECIAL */ + I2C0_IC_TAR_SPECIAL_DISABLED = 0, /*!< DISABLED : Disables programming of GENERAL_CALL or START_BYTE + transmission */ + I2C0_IC_TAR_SPECIAL_ENABLED = 1, /*!< ENABLED : Enables programming of GENERAL_CALL or START_BYTE + transmission */ +} I2C0_IC_TAR_SPECIAL_Enum; + +/* =========================================== I2C0 IC_TAR GC_OR_START [10..10] ============================================ */ +typedef enum { /*!< I2C0_IC_TAR_GC_OR_START */ + I2C0_IC_TAR_GC_OR_START_GENERAL_CALL = 0, /*!< GENERAL_CALL : GENERAL_CALL byte transmission */ + I2C0_IC_TAR_GC_OR_START_START_BYTE = 1, /*!< START_BYTE : START byte transmission */ +} I2C0_IC_TAR_GC_OR_START_Enum; + +/* ======================================================== IC_SAR ========================================================= */ +/* ====================================================== IC_DATA_CMD ====================================================== */ +/* ======================================= I2C0 IC_DATA_CMD FIRST_DATA_BYTE [11..11] ======================================= */ +typedef enum { /*!< I2C0_IC_DATA_CMD_FIRST_DATA_BYTE */ + I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_INACTIVE = 0,/*!< INACTIVE : Sequential data byte received */ + I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_ACTIVE = 1, /*!< ACTIVE : Non sequential data byte received */ +} I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_Enum; + +/* =========================================== I2C0 IC_DATA_CMD RESTART [10..10] =========================================== */ +typedef enum { /*!< I2C0_IC_DATA_CMD_RESTART */ + I2C0_IC_DATA_CMD_RESTART_DISABLE = 0, /*!< DISABLE : Don't Issue RESTART before this command */ + I2C0_IC_DATA_CMD_RESTART_ENABLE = 1, /*!< ENABLE : Issue RESTART before this command */ +} I2C0_IC_DATA_CMD_RESTART_Enum; + +/* ============================================= I2C0 IC_DATA_CMD STOP [9..9] ============================================== */ +typedef enum { /*!< I2C0_IC_DATA_CMD_STOP */ + I2C0_IC_DATA_CMD_STOP_DISABLE = 0, /*!< DISABLE : Don't Issue STOP after this command */ + I2C0_IC_DATA_CMD_STOP_ENABLE = 1, /*!< ENABLE : Issue STOP after this command */ +} I2C0_IC_DATA_CMD_STOP_Enum; + +/* ============================================== I2C0 IC_DATA_CMD CMD [8..8] ============================================== */ +typedef enum { /*!< I2C0_IC_DATA_CMD_CMD */ + I2C0_IC_DATA_CMD_CMD_WRITE = 0, /*!< WRITE : Master Write Command */ + I2C0_IC_DATA_CMD_CMD_READ = 1, /*!< READ : Master Read Command */ +} I2C0_IC_DATA_CMD_CMD_Enum; + +/* ==================================================== IC_SS_SCL_HCNT ===================================================== */ +/* ==================================================== IC_SS_SCL_LCNT ===================================================== */ +/* ==================================================== IC_FS_SCL_HCNT ===================================================== */ +/* ==================================================== IC_FS_SCL_LCNT ===================================================== */ +/* ===================================================== IC_INTR_STAT ====================================================== */ +/* ======================================= I2C0 IC_INTR_STAT R_RESTART_DET [12..12] ======================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_RESTART_DET */ + I2C0_IC_INTR_STAT_R_RESTART_DET_INACTIVE = 0, /*!< INACTIVE : R_RESTART_DET interrupt is inactive */ + I2C0_IC_INTR_STAT_R_RESTART_DET_ACTIVE = 1, /*!< ACTIVE : R_RESTART_DET interrupt is active */ +} I2C0_IC_INTR_STAT_R_RESTART_DET_Enum; + +/* ========================================= I2C0 IC_INTR_STAT R_GEN_CALL [11..11] ========================================= */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_GEN_CALL */ + I2C0_IC_INTR_STAT_R_GEN_CALL_INACTIVE = 0, /*!< INACTIVE : R_GEN_CALL interrupt is inactive */ + I2C0_IC_INTR_STAT_R_GEN_CALL_ACTIVE = 1, /*!< ACTIVE : R_GEN_CALL interrupt is active */ +} I2C0_IC_INTR_STAT_R_GEN_CALL_Enum; + +/* ======================================== I2C0 IC_INTR_STAT R_START_DET [10..10] ========================================= */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_START_DET */ + I2C0_IC_INTR_STAT_R_START_DET_INACTIVE = 0, /*!< INACTIVE : R_START_DET interrupt is inactive */ + I2C0_IC_INTR_STAT_R_START_DET_ACTIVE = 1, /*!< ACTIVE : R_START_DET interrupt is active */ +} I2C0_IC_INTR_STAT_R_START_DET_Enum; + +/* ========================================== I2C0 IC_INTR_STAT R_STOP_DET [9..9] ========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_STOP_DET */ + I2C0_IC_INTR_STAT_R_STOP_DET_INACTIVE = 0, /*!< INACTIVE : R_STOP_DET interrupt is inactive */ + I2C0_IC_INTR_STAT_R_STOP_DET_ACTIVE = 1, /*!< ACTIVE : R_STOP_DET interrupt is active */ +} I2C0_IC_INTR_STAT_R_STOP_DET_Enum; + +/* ========================================== I2C0 IC_INTR_STAT R_ACTIVITY [8..8] ========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_ACTIVITY */ + I2C0_IC_INTR_STAT_R_ACTIVITY_INACTIVE = 0, /*!< INACTIVE : R_ACTIVITY interrupt is inactive */ + I2C0_IC_INTR_STAT_R_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : R_ACTIVITY interrupt is active */ +} I2C0_IC_INTR_STAT_R_ACTIVITY_Enum; + +/* ========================================== I2C0 IC_INTR_STAT R_RX_DONE [7..7] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_DONE */ + I2C0_IC_INTR_STAT_R_RX_DONE_INACTIVE = 0, /*!< INACTIVE : R_RX_DONE interrupt is inactive */ + I2C0_IC_INTR_STAT_R_RX_DONE_ACTIVE = 1, /*!< ACTIVE : R_RX_DONE interrupt is active */ +} I2C0_IC_INTR_STAT_R_RX_DONE_Enum; + +/* ========================================== I2C0 IC_INTR_STAT R_TX_ABRT [6..6] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_TX_ABRT */ + I2C0_IC_INTR_STAT_R_TX_ABRT_INACTIVE = 0, /*!< INACTIVE : R_TX_ABRT interrupt is inactive */ + I2C0_IC_INTR_STAT_R_TX_ABRT_ACTIVE = 1, /*!< ACTIVE : R_TX_ABRT interrupt is active */ +} I2C0_IC_INTR_STAT_R_TX_ABRT_Enum; + +/* =========================================== I2C0 IC_INTR_STAT R_RD_REQ [5..5] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_RD_REQ */ + I2C0_IC_INTR_STAT_R_RD_REQ_INACTIVE = 0, /*!< INACTIVE : R_RD_REQ interrupt is inactive */ + I2C0_IC_INTR_STAT_R_RD_REQ_ACTIVE = 1, /*!< ACTIVE : R_RD_REQ interrupt is active */ +} I2C0_IC_INTR_STAT_R_RD_REQ_Enum; + +/* ========================================== I2C0 IC_INTR_STAT R_TX_EMPTY [4..4] ========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_TX_EMPTY */ + I2C0_IC_INTR_STAT_R_TX_EMPTY_INACTIVE = 0, /*!< INACTIVE : R_TX_EMPTY interrupt is inactive */ + I2C0_IC_INTR_STAT_R_TX_EMPTY_ACTIVE = 1, /*!< ACTIVE : R_TX_EMPTY interrupt is active */ +} I2C0_IC_INTR_STAT_R_TX_EMPTY_Enum; + +/* ========================================== I2C0 IC_INTR_STAT R_TX_OVER [3..3] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_TX_OVER */ + I2C0_IC_INTR_STAT_R_TX_OVER_INACTIVE = 0, /*!< INACTIVE : R_TX_OVER interrupt is inactive */ + I2C0_IC_INTR_STAT_R_TX_OVER_ACTIVE = 1, /*!< ACTIVE : R_TX_OVER interrupt is active */ +} I2C0_IC_INTR_STAT_R_TX_OVER_Enum; + +/* ========================================== I2C0 IC_INTR_STAT R_RX_FULL [2..2] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_FULL */ + I2C0_IC_INTR_STAT_R_RX_FULL_INACTIVE = 0, /*!< INACTIVE : R_RX_FULL interrupt is inactive */ + I2C0_IC_INTR_STAT_R_RX_FULL_ACTIVE = 1, /*!< ACTIVE : R_RX_FULL interrupt is active */ +} I2C0_IC_INTR_STAT_R_RX_FULL_Enum; + +/* ========================================== I2C0 IC_INTR_STAT R_RX_OVER [1..1] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_OVER */ + I2C0_IC_INTR_STAT_R_RX_OVER_INACTIVE = 0, /*!< INACTIVE : R_RX_OVER interrupt is inactive */ + I2C0_IC_INTR_STAT_R_RX_OVER_ACTIVE = 1, /*!< ACTIVE : R_RX_OVER interrupt is active */ +} I2C0_IC_INTR_STAT_R_RX_OVER_Enum; + +/* ========================================== I2C0 IC_INTR_STAT R_RX_UNDER [0..0] ========================================== */ +typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_UNDER */ + I2C0_IC_INTR_STAT_R_RX_UNDER_INACTIVE = 0, /*!< INACTIVE : RX_UNDER interrupt is inactive */ + I2C0_IC_INTR_STAT_R_RX_UNDER_ACTIVE = 1, /*!< ACTIVE : RX_UNDER interrupt is active */ +} I2C0_IC_INTR_STAT_R_RX_UNDER_Enum; + +/* ===================================================== IC_INTR_MASK ====================================================== */ +/* ======================================= I2C0 IC_INTR_MASK M_RESTART_DET [12..12] ======================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_RESTART_DET */ + I2C0_IC_INTR_MASK_M_RESTART_DET_ENABLED = 0, /*!< ENABLED : RESTART_DET interrupt is masked */ + I2C0_IC_INTR_MASK_M_RESTART_DET_DISABLED = 1, /*!< DISABLED : RESTART_DET interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_RESTART_DET_Enum; + +/* ========================================= I2C0 IC_INTR_MASK M_GEN_CALL [11..11] ========================================= */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_GEN_CALL */ + I2C0_IC_INTR_MASK_M_GEN_CALL_ENABLED = 0, /*!< ENABLED : GEN_CALL interrupt is masked */ + I2C0_IC_INTR_MASK_M_GEN_CALL_DISABLED = 1, /*!< DISABLED : GEN_CALL interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_GEN_CALL_Enum; + +/* ======================================== I2C0 IC_INTR_MASK M_START_DET [10..10] ========================================= */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_START_DET */ + I2C0_IC_INTR_MASK_M_START_DET_ENABLED = 0, /*!< ENABLED : START_DET interrupt is masked */ + I2C0_IC_INTR_MASK_M_START_DET_DISABLED = 1, /*!< DISABLED : START_DET interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_START_DET_Enum; + +/* ========================================== I2C0 IC_INTR_MASK M_STOP_DET [9..9] ========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_STOP_DET */ + I2C0_IC_INTR_MASK_M_STOP_DET_ENABLED = 0, /*!< ENABLED : STOP_DET interrupt is masked */ + I2C0_IC_INTR_MASK_M_STOP_DET_DISABLED = 1, /*!< DISABLED : STOP_DET interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_STOP_DET_Enum; + +/* ========================================== I2C0 IC_INTR_MASK M_ACTIVITY [8..8] ========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_ACTIVITY */ + I2C0_IC_INTR_MASK_M_ACTIVITY_ENABLED = 0, /*!< ENABLED : ACTIVITY interrupt is masked */ + I2C0_IC_INTR_MASK_M_ACTIVITY_DISABLED = 1, /*!< DISABLED : ACTIVITY interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_ACTIVITY_Enum; + +/* ========================================== I2C0 IC_INTR_MASK M_RX_DONE [7..7] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_DONE */ + I2C0_IC_INTR_MASK_M_RX_DONE_ENABLED = 0, /*!< ENABLED : RX_DONE interrupt is masked */ + I2C0_IC_INTR_MASK_M_RX_DONE_DISABLED = 1, /*!< DISABLED : RX_DONE interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_RX_DONE_Enum; + +/* ========================================== I2C0 IC_INTR_MASK M_TX_ABRT [6..6] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_TX_ABRT */ + I2C0_IC_INTR_MASK_M_TX_ABRT_ENABLED = 0, /*!< ENABLED : TX_ABORT interrupt is masked */ + I2C0_IC_INTR_MASK_M_TX_ABRT_DISABLED = 1, /*!< DISABLED : TX_ABORT interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_TX_ABRT_Enum; + +/* =========================================== I2C0 IC_INTR_MASK M_RD_REQ [5..5] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_RD_REQ */ + I2C0_IC_INTR_MASK_M_RD_REQ_ENABLED = 0, /*!< ENABLED : RD_REQ interrupt is masked */ + I2C0_IC_INTR_MASK_M_RD_REQ_DISABLED = 1, /*!< DISABLED : RD_REQ interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_RD_REQ_Enum; + +/* ========================================== I2C0 IC_INTR_MASK M_TX_EMPTY [4..4] ========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_TX_EMPTY */ + I2C0_IC_INTR_MASK_M_TX_EMPTY_ENABLED = 0, /*!< ENABLED : TX_EMPTY interrupt is masked */ + I2C0_IC_INTR_MASK_M_TX_EMPTY_DISABLED = 1, /*!< DISABLED : TX_EMPTY interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_TX_EMPTY_Enum; + +/* ========================================== I2C0 IC_INTR_MASK M_TX_OVER [3..3] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_TX_OVER */ + I2C0_IC_INTR_MASK_M_TX_OVER_ENABLED = 0, /*!< ENABLED : TX_OVER interrupt is masked */ + I2C0_IC_INTR_MASK_M_TX_OVER_DISABLED = 1, /*!< DISABLED : TX_OVER interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_TX_OVER_Enum; + +/* ========================================== I2C0 IC_INTR_MASK M_RX_FULL [2..2] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_FULL */ + I2C0_IC_INTR_MASK_M_RX_FULL_ENABLED = 0, /*!< ENABLED : RX_FULL interrupt is masked */ + I2C0_IC_INTR_MASK_M_RX_FULL_DISABLED = 1, /*!< DISABLED : RX_FULL interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_RX_FULL_Enum; + +/* ========================================== I2C0 IC_INTR_MASK M_RX_OVER [1..1] =========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_OVER */ + I2C0_IC_INTR_MASK_M_RX_OVER_ENABLED = 0, /*!< ENABLED : RX_OVER interrupt is masked */ + I2C0_IC_INTR_MASK_M_RX_OVER_DISABLED = 1, /*!< DISABLED : RX_OVER interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_RX_OVER_Enum; + +/* ========================================== I2C0 IC_INTR_MASK M_RX_UNDER [0..0] ========================================== */ +typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_UNDER */ + I2C0_IC_INTR_MASK_M_RX_UNDER_ENABLED = 0, /*!< ENABLED : RX_UNDER interrupt is masked */ + I2C0_IC_INTR_MASK_M_RX_UNDER_DISABLED = 1, /*!< DISABLED : RX_UNDER interrupt is unmasked */ +} I2C0_IC_INTR_MASK_M_RX_UNDER_Enum; + +/* =================================================== IC_RAW_INTR_STAT ==================================================== */ +/* ====================================== I2C0 IC_RAW_INTR_STAT RESTART_DET [12..12] ======================================= */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RESTART_DET */ + I2C0_IC_RAW_INTR_STAT_RESTART_DET_INACTIVE = 0,/*!< INACTIVE : RESTART_DET interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_RESTART_DET_ACTIVE = 1, /*!< ACTIVE : RESTART_DET interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_RESTART_DET_Enum; + +/* ======================================== I2C0 IC_RAW_INTR_STAT GEN_CALL [11..11] ======================================== */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_GEN_CALL */ + I2C0_IC_RAW_INTR_STAT_GEN_CALL_INACTIVE = 0, /*!< INACTIVE : GEN_CALL interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_GEN_CALL_ACTIVE = 1, /*!< ACTIVE : GEN_CALL interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_GEN_CALL_Enum; + +/* ======================================= I2C0 IC_RAW_INTR_STAT START_DET [10..10] ======================================== */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_START_DET */ + I2C0_IC_RAW_INTR_STAT_START_DET_INACTIVE = 0, /*!< INACTIVE : START_DET interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_START_DET_ACTIVE = 1, /*!< ACTIVE : START_DET interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_START_DET_Enum; + +/* ========================================= I2C0 IC_RAW_INTR_STAT STOP_DET [9..9] ========================================= */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_STOP_DET */ + I2C0_IC_RAW_INTR_STAT_STOP_DET_INACTIVE = 0, /*!< INACTIVE : STOP_DET interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_STOP_DET_ACTIVE = 1, /*!< ACTIVE : STOP_DET interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_STOP_DET_Enum; + +/* ========================================= I2C0 IC_RAW_INTR_STAT ACTIVITY [8..8] ========================================= */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_ACTIVITY */ + I2C0_IC_RAW_INTR_STAT_ACTIVITY_INACTIVE = 0, /*!< INACTIVE : RAW_INTR_ACTIVITY interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : RAW_INTR_ACTIVITY interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_ACTIVITY_Enum; + +/* ========================================= I2C0 IC_RAW_INTR_STAT RX_DONE [7..7] ========================================== */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RX_DONE */ + I2C0_IC_RAW_INTR_STAT_RX_DONE_INACTIVE = 0, /*!< INACTIVE : RX_DONE interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_RX_DONE_ACTIVE = 1, /*!< ACTIVE : RX_DONE interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_RX_DONE_Enum; + +/* ========================================= I2C0 IC_RAW_INTR_STAT TX_ABRT [6..6] ========================================== */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_TX_ABRT */ + I2C0_IC_RAW_INTR_STAT_TX_ABRT_INACTIVE = 0, /*!< INACTIVE : TX_ABRT interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_TX_ABRT_ACTIVE = 1, /*!< ACTIVE : TX_ABRT interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_TX_ABRT_Enum; + +/* ========================================== I2C0 IC_RAW_INTR_STAT RD_REQ [5..5] ========================================== */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RD_REQ */ + I2C0_IC_RAW_INTR_STAT_RD_REQ_INACTIVE = 0, /*!< INACTIVE : RD_REQ interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_RD_REQ_ACTIVE = 1, /*!< ACTIVE : RD_REQ interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_RD_REQ_Enum; + +/* ========================================= I2C0 IC_RAW_INTR_STAT TX_EMPTY [4..4] ========================================= */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_TX_EMPTY */ + I2C0_IC_RAW_INTR_STAT_TX_EMPTY_INACTIVE = 0, /*!< INACTIVE : TX_EMPTY interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_TX_EMPTY_ACTIVE = 1, /*!< ACTIVE : TX_EMPTY interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_TX_EMPTY_Enum; + +/* ========================================= I2C0 IC_RAW_INTR_STAT TX_OVER [3..3] ========================================== */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_TX_OVER */ + I2C0_IC_RAW_INTR_STAT_TX_OVER_INACTIVE = 0, /*!< INACTIVE : TX_OVER interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_TX_OVER_ACTIVE = 1, /*!< ACTIVE : TX_OVER interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_TX_OVER_Enum; + +/* ========================================= I2C0 IC_RAW_INTR_STAT RX_FULL [2..2] ========================================== */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RX_FULL */ + I2C0_IC_RAW_INTR_STAT_RX_FULL_INACTIVE = 0, /*!< INACTIVE : RX_FULL interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_RX_FULL_ACTIVE = 1, /*!< ACTIVE : RX_FULL interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_RX_FULL_Enum; + +/* ========================================= I2C0 IC_RAW_INTR_STAT RX_OVER [1..1] ========================================== */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RX_OVER */ + I2C0_IC_RAW_INTR_STAT_RX_OVER_INACTIVE = 0, /*!< INACTIVE : RX_OVER interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_RX_OVER_ACTIVE = 1, /*!< ACTIVE : RX_OVER interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_RX_OVER_Enum; + +/* ========================================= I2C0 IC_RAW_INTR_STAT RX_UNDER [0..0] ========================================= */ +typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RX_UNDER */ + I2C0_IC_RAW_INTR_STAT_RX_UNDER_INACTIVE = 0, /*!< INACTIVE : RX_UNDER interrupt is inactive */ + I2C0_IC_RAW_INTR_STAT_RX_UNDER_ACTIVE = 1, /*!< ACTIVE : RX_UNDER interrupt is active */ +} I2C0_IC_RAW_INTR_STAT_RX_UNDER_Enum; + +/* ======================================================= IC_RX_TL ======================================================== */ +/* ======================================================= IC_TX_TL ======================================================== */ +/* ====================================================== IC_CLR_INTR ====================================================== */ +/* ==================================================== IC_CLR_RX_UNDER ==================================================== */ +/* ==================================================== IC_CLR_RX_OVER ===================================================== */ +/* ==================================================== IC_CLR_TX_OVER ===================================================== */ +/* ===================================================== IC_CLR_RD_REQ ===================================================== */ +/* ==================================================== IC_CLR_TX_ABRT ===================================================== */ +/* ==================================================== IC_CLR_RX_DONE ===================================================== */ +/* ==================================================== IC_CLR_ACTIVITY ==================================================== */ +/* ==================================================== IC_CLR_STOP_DET ==================================================== */ +/* =================================================== IC_CLR_START_DET ==================================================== */ +/* ==================================================== IC_CLR_GEN_CALL ==================================================== */ +/* ======================================================= IC_ENABLE ======================================================= */ +/* ========================================== I2C0 IC_ENABLE TX_CMD_BLOCK [2..2] =========================================== */ +typedef enum { /*!< I2C0_IC_ENABLE_TX_CMD_BLOCK */ + I2C0_IC_ENABLE_TX_CMD_BLOCK_NOT_BLOCKED = 0, /*!< NOT_BLOCKED : Tx Command execution not blocked */ + I2C0_IC_ENABLE_TX_CMD_BLOCK_BLOCKED = 1, /*!< BLOCKED : Tx Command execution blocked */ +} I2C0_IC_ENABLE_TX_CMD_BLOCK_Enum; + +/* ============================================== I2C0 IC_ENABLE ABORT [1..1] ============================================== */ +typedef enum { /*!< I2C0_IC_ENABLE_ABORT */ + I2C0_IC_ENABLE_ABORT_DISABLE = 0, /*!< DISABLE : ABORT operation not in progress */ + I2C0_IC_ENABLE_ABORT_ENABLED = 1, /*!< ENABLED : ABORT operation in progress */ +} I2C0_IC_ENABLE_ABORT_Enum; + +/* ============================================= I2C0 IC_ENABLE ENABLE [0..0] ============================================== */ +typedef enum { /*!< I2C0_IC_ENABLE_ENABLE */ + I2C0_IC_ENABLE_ENABLE_DISABLED = 0, /*!< DISABLED : I2C is disabled */ + I2C0_IC_ENABLE_ENABLE_ENABLED = 1, /*!< ENABLED : I2C is enabled */ +} I2C0_IC_ENABLE_ENABLE_Enum; + +/* ======================================================= IC_STATUS ======================================================= */ +/* ========================================== I2C0 IC_STATUS SLV_ACTIVITY [6..6] =========================================== */ +typedef enum { /*!< I2C0_IC_STATUS_SLV_ACTIVITY */ + I2C0_IC_STATUS_SLV_ACTIVITY_IDLE = 0, /*!< IDLE : Slave is idle */ + I2C0_IC_STATUS_SLV_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : Slave not idle */ +} I2C0_IC_STATUS_SLV_ACTIVITY_Enum; + +/* ========================================== I2C0 IC_STATUS MST_ACTIVITY [5..5] =========================================== */ +typedef enum { /*!< I2C0_IC_STATUS_MST_ACTIVITY */ + I2C0_IC_STATUS_MST_ACTIVITY_IDLE = 0, /*!< IDLE : Master is idle */ + I2C0_IC_STATUS_MST_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : Master not idle */ +} I2C0_IC_STATUS_MST_ACTIVITY_Enum; + +/* =============================================== I2C0 IC_STATUS RFF [4..4] =============================================== */ +typedef enum { /*!< I2C0_IC_STATUS_RFF */ + I2C0_IC_STATUS_RFF_NOT_FULL = 0, /*!< NOT_FULL : Rx FIFO not full */ + I2C0_IC_STATUS_RFF_FULL = 1, /*!< FULL : Rx FIFO is full */ +} I2C0_IC_STATUS_RFF_Enum; + +/* ============================================== I2C0 IC_STATUS RFNE [3..3] =============================================== */ +typedef enum { /*!< I2C0_IC_STATUS_RFNE */ + I2C0_IC_STATUS_RFNE_EMPTY = 0, /*!< EMPTY : Rx FIFO is empty */ + I2C0_IC_STATUS_RFNE_NOT_EMPTY = 1, /*!< NOT_EMPTY : Rx FIFO not empty */ +} I2C0_IC_STATUS_RFNE_Enum; + +/* =============================================== I2C0 IC_STATUS TFE [2..2] =============================================== */ +typedef enum { /*!< I2C0_IC_STATUS_TFE */ + I2C0_IC_STATUS_TFE_NON_EMPTY = 0, /*!< NON_EMPTY : Tx FIFO not empty */ + I2C0_IC_STATUS_TFE_EMPTY = 1, /*!< EMPTY : Tx FIFO is empty */ +} I2C0_IC_STATUS_TFE_Enum; + +/* ============================================== I2C0 IC_STATUS TFNF [1..1] =============================================== */ +typedef enum { /*!< I2C0_IC_STATUS_TFNF */ + I2C0_IC_STATUS_TFNF_FULL = 0, /*!< FULL : Tx FIFO is full */ + I2C0_IC_STATUS_TFNF_NOT_FULL = 1, /*!< NOT_FULL : Tx FIFO not full */ +} I2C0_IC_STATUS_TFNF_Enum; + +/* ============================================ I2C0 IC_STATUS ACTIVITY [0..0] ============================================= */ +typedef enum { /*!< I2C0_IC_STATUS_ACTIVITY */ + I2C0_IC_STATUS_ACTIVITY_INACTIVE = 0, /*!< INACTIVE : I2C is idle */ + I2C0_IC_STATUS_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : I2C is active */ +} I2C0_IC_STATUS_ACTIVITY_Enum; + +/* ======================================================= IC_TXFLR ======================================================== */ +/* ======================================================= IC_RXFLR ======================================================== */ +/* ====================================================== IC_SDA_HOLD ====================================================== */ +/* =================================================== IC_TX_ABRT_SOURCE =================================================== */ +/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_USER_ABRT [16..16] ===================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ABRT_USER_ABRT_VOID = 0,/*!< ABRT_USER_ABRT_VOID : Transfer abort detected by master- scenario + not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ABRT_USER_ABRT_GENERATED = 1,/*!< ABRT_USER_ABRT_GENERATED : Transfer abort detected by master */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_Enum; + +/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_SLVRD_INTX [15..15] ==================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ABRT_SLVRD_INTX_VOID = 0,/*!< ABRT_SLVRD_INTX_VOID : Slave trying to transmit to remote master + in read mode- scenario not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ABRT_SLVRD_INTX_GENERATED = 1,/*!< ABRT_SLVRD_INTX_GENERATED : Slave trying to transmit to remote + master in read mode */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_Enum; + +/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_SLV_ARBLOST [14..14] ==================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ABRT_SLV_ARBLOST_VOID = 0,/*!< ABRT_SLV_ARBLOST_VOID : Slave lost arbitration to remote master- + scenario not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ABRT_SLV_ARBLOST_GENERATED = 1,/*!< ABRT_SLV_ARBLOST_GENERATED : Slave lost arbitration to remote + master */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_Enum; + +/* ================================= I2C0 IC_TX_ABRT_SOURCE ABRT_SLVFLUSH_TXFIFO [13..13] ================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ABRT_SLVFLUSH_TXFIFO_VOID = 0,/*!< ABRT_SLVFLUSH_TXFIFO_VOID : Slave flushes existing data in TX-FIFO + upon getting read command- scenario not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ABRT_SLVFLUSH_TXFIFO_GENERATED = 1,/*!< ABRT_SLVFLUSH_TXFIFO_GENERATED : Slave flushes existing data + in TX-FIFO upon getting read command */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_Enum; + +/* ======================================= I2C0 IC_TX_ABRT_SOURCE ARB_LOST [12..12] ======================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ARB_LOST */ + I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_ABRT_LOST_VOID = 0,/*!< ABRT_LOST_VOID : Master or Slave-Transmitter lost arbitration- + scenario not present */ + I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_ABRT_LOST_GENERATED = 1,/*!< ABRT_LOST_GENERATED : Master or Slave-Transmitter lost arbitration */ +} I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_Enum; + +/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_MASTER_DIS [11..11] ==================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ABRT_MASTER_DIS_VOID = 0,/*!< ABRT_MASTER_DIS_VOID : User initiating master operation when + MASTER disabled- scenario not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ABRT_MASTER_DIS_GENERATED = 1,/*!< ABRT_MASTER_DIS_GENERATED : User initiating master operation + when MASTER disabled */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_Enum; + +/* ================================== I2C0 IC_TX_ABRT_SOURCE ABRT_10B_RD_NORSTRT [10..10] ================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ABRT_10B_RD_VOID = 0,/*!< ABRT_10B_RD_VOID : Master not trying to read in 10Bit addressing + mode when RESTART disabled */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ABRT_10B_RD_GENERATED = 1,/*!< ABRT_10B_RD_GENERATED : Master trying to read in 10Bit addressing + mode when RESTART disabled */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_Enum; + +/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_SBYTE_NORSTRT [9..9] ==================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ABRT_SBYTE_NORSTRT_VOID = 0,/*!< ABRT_SBYTE_NORSTRT_VOID : User trying to send START byte when + RESTART disabled- scenario not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ABRT_SBYTE_NORSTRT_GENERATED = 1,/*!< ABRT_SBYTE_NORSTRT_GENERATED : User trying to send START byte + when RESTART disabled */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_Enum; + +/* ===================================== I2C0 IC_TX_ABRT_SOURCE ABRT_HS_NORSTRT [8..8] ===================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ABRT_HS_NORSTRT_VOID = 0,/*!< ABRT_HS_NORSTRT_VOID : User trying to switch Master to HS mode + when RESTART disabled- scenario not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ABRT_HS_NORSTRT_GENERATED = 1,/*!< ABRT_HS_NORSTRT_GENERATED : User trying to switch Master to + HS mode when RESTART disabled */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_Enum; + +/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_SBYTE_ACKDET [7..7] ==================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ABRT_SBYTE_ACKDET_VOID = 0,/*!< ABRT_SBYTE_ACKDET_VOID : ACK detected for START byte- scenario + not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ABRT_SBYTE_ACKDET_GENERATED = 1,/*!< ABRT_SBYTE_ACKDET_GENERATED : ACK detected for START byte */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_Enum; + +/* ===================================== I2C0 IC_TX_ABRT_SOURCE ABRT_HS_ACKDET [6..6] ====================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ABRT_HS_ACK_VOID = 0,/*!< ABRT_HS_ACK_VOID : HS Master code ACKed in HS Mode- scenario + not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ABRT_HS_ACK_GENERATED = 1,/*!< ABRT_HS_ACK_GENERATED : HS Master code ACKed in HS Mode */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_Enum; + +/* ===================================== I2C0 IC_TX_ABRT_SOURCE ABRT_GCALL_READ [5..5] ===================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ABRT_GCALL_READ_VOID = 0,/*!< ABRT_GCALL_READ_VOID : GCALL is followed by read from bus-scenario + not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ABRT_GCALL_READ_GENERATED = 1,/*!< ABRT_GCALL_READ_GENERATED : GCALL is followed by read from bus */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_Enum; + +/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_GCALL_NOACK [4..4] ===================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ABRT_GCALL_NOACK_VOID = 0,/*!< ABRT_GCALL_NOACK_VOID : GCALL not ACKed by any slave-scenario + not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ABRT_GCALL_NOACK_GENERATED = 1,/*!< ABRT_GCALL_NOACK_GENERATED : GCALL not ACKed by any slave */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_Enum; + +/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_TXDATA_NOACK [3..3] ==================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ABRT_TXDATA_NOACK_VOID = 0,/*!< ABRT_TXDATA_NOACK_VOID : Transmitted data non-ACKed by addressed + slave-scenario not present */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ABRT_TXDATA_NOACK_GENERATED = 1,/*!< ABRT_TXDATA_NOACK_GENERATED : Transmitted data not ACKed by + addressed slave */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_Enum; + +/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_10ADDR2_NOACK [2..2] ==================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_INACTIVE = 0,/*!< INACTIVE : This abort is not generated */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACTIVE = 1,/*!< ACTIVE : Byte 2 of 10Bit Address not ACKed by any slave */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_Enum; + +/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_10ADDR1_NOACK [1..1] ==================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_INACTIVE = 0,/*!< INACTIVE : This abort is not generated */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACTIVE = 1,/*!< ACTIVE : Byte 1 of 10Bit Address not ACKed by any slave */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_Enum; + +/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_7B_ADDR_NOACK [0..0] ==================================== */ +typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_INACTIVE = 0,/*!< INACTIVE : This abort is not generated */ + I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACTIVE = 1,/*!< ACTIVE : This abort is generated because of NOACK for 7-bit + address */ +} I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_Enum; + +/* ================================================= IC_SLV_DATA_NACK_ONLY ================================================= */ +/* ======================================== I2C0 IC_SLV_DATA_NACK_ONLY NACK [0..0] ========================================= */ +typedef enum { /*!< I2C0_IC_SLV_DATA_NACK_ONLY_NACK */ + I2C0_IC_SLV_DATA_NACK_ONLY_NACK_DISABLED = 0, /*!< DISABLED : Slave receiver generates NACK normally */ + I2C0_IC_SLV_DATA_NACK_ONLY_NACK_ENABLED = 1, /*!< ENABLED : Slave receiver generates NACK upon data reception + only */ +} I2C0_IC_SLV_DATA_NACK_ONLY_NACK_Enum; + +/* ======================================================= IC_DMA_CR ======================================================= */ +/* ============================================== I2C0 IC_DMA_CR TDMAE [1..1] ============================================== */ +typedef enum { /*!< I2C0_IC_DMA_CR_TDMAE */ + I2C0_IC_DMA_CR_TDMAE_DISABLED = 0, /*!< DISABLED : transmit FIFO DMA channel disabled */ + I2C0_IC_DMA_CR_TDMAE_ENABLED = 1, /*!< ENABLED : Transmit FIFO DMA channel enabled */ +} I2C0_IC_DMA_CR_TDMAE_Enum; + +/* ============================================== I2C0 IC_DMA_CR RDMAE [0..0] ============================================== */ +typedef enum { /*!< I2C0_IC_DMA_CR_RDMAE */ + I2C0_IC_DMA_CR_RDMAE_DISABLED = 0, /*!< DISABLED : Receive FIFO DMA channel disabled */ + I2C0_IC_DMA_CR_RDMAE_ENABLED = 1, /*!< ENABLED : Receive FIFO DMA channel enabled */ +} I2C0_IC_DMA_CR_RDMAE_Enum; + +/* ====================================================== IC_DMA_TDLR ====================================================== */ +/* ====================================================== IC_DMA_RDLR ====================================================== */ +/* ===================================================== IC_SDA_SETUP ====================================================== */ +/* ================================================== IC_ACK_GENERAL_CALL ================================================== */ +/* ===================================== I2C0 IC_ACK_GENERAL_CALL ACK_GEN_CALL [0..0] ====================================== */ +typedef enum { /*!< I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL */ + I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_DISABLED = 0,/*!< DISABLED : Generate NACK for a General Call */ + I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ENABLED = 1,/*!< ENABLED : Generate ACK for a General Call */ +} I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_Enum; + +/* =================================================== IC_ENABLE_STATUS ==================================================== */ +/* ===================================== I2C0 IC_ENABLE_STATUS SLV_RX_DATA_LOST [2..2] ===================================== */ +typedef enum { /*!< I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST */ + I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_INACTIVE = 0,/*!< INACTIVE : Slave RX Data is not lost */ + I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACTIVE = 1,/*!< ACTIVE : Slave RX Data is lost */ +} I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_Enum; + +/* ================================= I2C0 IC_ENABLE_STATUS SLV_DISABLED_WHILE_BUSY [1..1] ================================== */ +typedef enum { /*!< I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY */ + I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_INACTIVE = 0,/*!< INACTIVE : Slave is disabled when it is idle */ + I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACTIVE = 1,/*!< ACTIVE : Slave is disabled when it is active */ +} I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_Enum; + +/* ========================================== I2C0 IC_ENABLE_STATUS IC_EN [0..0] =========================================== */ +typedef enum { /*!< I2C0_IC_ENABLE_STATUS_IC_EN */ + I2C0_IC_ENABLE_STATUS_IC_EN_DISABLED = 0, /*!< DISABLED : I2C disabled */ + I2C0_IC_ENABLE_STATUS_IC_EN_ENABLED = 1, /*!< ENABLED : I2C enabled */ +} I2C0_IC_ENABLE_STATUS_IC_EN_Enum; + +/* ===================================================== IC_FS_SPKLEN ====================================================== */ +/* ================================================== IC_CLR_RESTART_DET =================================================== */ +/* ==================================================== IC_COMP_PARAM_1 ==================================================== */ +/* ==================================================== IC_COMP_VERSION ==================================================== */ +/* ===================================================== IC_COMP_TYPE ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SSPCR0 ========================================================= */ +/* ======================================================== SSPCR1 ========================================================= */ +/* ========================================================= SSPDR ========================================================= */ +/* ========================================================= SSPSR ========================================================= */ +/* ======================================================== SSPCPSR ======================================================== */ +/* ======================================================== SSPIMSC ======================================================== */ +/* ======================================================== SSPRIS ========================================================= */ +/* ======================================================== SSPMIS ========================================================= */ +/* ======================================================== SSPICR ========================================================= */ +/* ======================================================= SSPDMACR ======================================================== */ +/* ===================================================== SSPPERIPHID0 ====================================================== */ +/* ===================================================== SSPPERIPHID1 ====================================================== */ +/* ===================================================== SSPPERIPHID2 ====================================================== */ +/* ===================================================== SSPPERIPHID3 ====================================================== */ +/* ====================================================== SSPPCELLID0 ====================================================== */ +/* ====================================================== SSPPCELLID1 ====================================================== */ +/* ====================================================== SSPPCELLID2 ====================================================== */ +/* ====================================================== SSPPCELLID3 ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ PIO0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +/* ========================================================= FSTAT ========================================================= */ +/* ======================================================== FDEBUG ========================================================= */ +/* ======================================================== FLEVEL ========================================================= */ +/* ========================================================= TXF0 ========================================================== */ +/* ========================================================= TXF1 ========================================================== */ +/* ========================================================= TXF2 ========================================================== */ +/* ========================================================= TXF3 ========================================================== */ +/* ========================================================= RXF0 ========================================================== */ +/* ========================================================= RXF1 ========================================================== */ +/* ========================================================= RXF2 ========================================================== */ +/* ========================================================= RXF3 ========================================================== */ +/* ========================================================== IRQ ========================================================== */ +/* ======================================================= IRQ_FORCE ======================================================= */ +/* =================================================== INPUT_SYNC_BYPASS =================================================== */ +/* ====================================================== DBG_PADOUT ======================================================= */ +/* ======================================================= DBG_PADOE ======================================================= */ +/* ====================================================== DBG_CFGINFO ====================================================== */ +/* =========================================== PIO0 DBG_CFGINFO VERSION [28..31] =========================================== */ +typedef enum { /*!< PIO0_DBG_CFGINFO_VERSION */ + PIO0_DBG_CFGINFO_VERSION_v0 = 0, /*!< v0 : Version 0 (RP2040) */ + PIO0_DBG_CFGINFO_VERSION_v1 = 1, /*!< v1 : Version 1 (RP2350) */ +} PIO0_DBG_CFGINFO_VERSION_Enum; + +/* ====================================================== INSTR_MEM0 ======================================================= */ +/* ====================================================== INSTR_MEM1 ======================================================= */ +/* ====================================================== INSTR_MEM2 ======================================================= */ +/* ====================================================== INSTR_MEM3 ======================================================= */ +/* ====================================================== INSTR_MEM4 ======================================================= */ +/* ====================================================== INSTR_MEM5 ======================================================= */ +/* ====================================================== INSTR_MEM6 ======================================================= */ +/* ====================================================== INSTR_MEM7 ======================================================= */ +/* ====================================================== INSTR_MEM8 ======================================================= */ +/* ====================================================== INSTR_MEM9 ======================================================= */ +/* ====================================================== INSTR_MEM10 ====================================================== */ +/* ====================================================== INSTR_MEM11 ====================================================== */ +/* ====================================================== INSTR_MEM12 ====================================================== */ +/* ====================================================== INSTR_MEM13 ====================================================== */ +/* ====================================================== INSTR_MEM14 ====================================================== */ +/* ====================================================== INSTR_MEM15 ====================================================== */ +/* ====================================================== INSTR_MEM16 ====================================================== */ +/* ====================================================== INSTR_MEM17 ====================================================== */ +/* ====================================================== INSTR_MEM18 ====================================================== */ +/* ====================================================== INSTR_MEM19 ====================================================== */ +/* ====================================================== INSTR_MEM20 ====================================================== */ +/* ====================================================== INSTR_MEM21 ====================================================== */ +/* ====================================================== INSTR_MEM22 ====================================================== */ +/* ====================================================== INSTR_MEM23 ====================================================== */ +/* ====================================================== INSTR_MEM24 ====================================================== */ +/* ====================================================== INSTR_MEM25 ====================================================== */ +/* ====================================================== INSTR_MEM26 ====================================================== */ +/* ====================================================== INSTR_MEM27 ====================================================== */ +/* ====================================================== INSTR_MEM28 ====================================================== */ +/* ====================================================== INSTR_MEM29 ====================================================== */ +/* ====================================================== INSTR_MEM30 ====================================================== */ +/* ====================================================== INSTR_MEM31 ====================================================== */ +/* ====================================================== SM0_CLKDIV ======================================================= */ +/* ===================================================== SM0_EXECCTRL ====================================================== */ +/* ========================================== PIO0 SM0_EXECCTRL STATUS_SEL [5..6] ========================================== */ +typedef enum { /*!< PIO0_SM0_EXECCTRL_STATUS_SEL */ + PIO0_SM0_EXECCTRL_STATUS_SEL_TXLEVEL = 0, /*!< TXLEVEL : All-ones if TX FIFO level < N, otherwise all-zeroes */ + PIO0_SM0_EXECCTRL_STATUS_SEL_RXLEVEL = 1, /*!< RXLEVEL : All-ones if RX FIFO level < N, otherwise all-zeroes */ + PIO0_SM0_EXECCTRL_STATUS_SEL_IRQ = 2, /*!< IRQ : All-ones if the indexed IRQ flag is raised, otherwise + all-zeroes */ +} PIO0_SM0_EXECCTRL_STATUS_SEL_Enum; + +/* =========================================== PIO0 SM0_EXECCTRL STATUS_N [0..4] =========================================== */ +typedef enum { /*!< PIO0_SM0_EXECCTRL_STATUS_N */ + PIO0_SM0_EXECCTRL_STATUS_N_IRQ = 0, /*!< IRQ : Index 0-7 of an IRQ flag in this PIO block */ + PIO0_SM0_EXECCTRL_STATUS_N_IRQ_PREVPIO = 8, /*!< IRQ_PREVPIO : Index 0-7 of an IRQ flag in the next lower-numbered + PIO block */ + PIO0_SM0_EXECCTRL_STATUS_N_IRQ_NEXTPIO = 16, /*!< IRQ_NEXTPIO : Index 0-7 of an IRQ flag in the next higher-numbered + PIO block */ +} PIO0_SM0_EXECCTRL_STATUS_N_Enum; + +/* ===================================================== SM0_SHIFTCTRL ===================================================== */ +/* ======================================================= SM0_ADDR ======================================================== */ +/* ======================================================= SM0_INSTR ======================================================= */ +/* ====================================================== SM0_PINCTRL ====================================================== */ +/* ====================================================== SM1_CLKDIV ======================================================= */ +/* ===================================================== SM1_EXECCTRL ====================================================== */ +/* ========================================== PIO0 SM1_EXECCTRL STATUS_SEL [5..6] ========================================== */ +typedef enum { /*!< PIO0_SM1_EXECCTRL_STATUS_SEL */ + PIO0_SM1_EXECCTRL_STATUS_SEL_TXLEVEL = 0, /*!< TXLEVEL : All-ones if TX FIFO level < N, otherwise all-zeroes */ + PIO0_SM1_EXECCTRL_STATUS_SEL_RXLEVEL = 1, /*!< RXLEVEL : All-ones if RX FIFO level < N, otherwise all-zeroes */ + PIO0_SM1_EXECCTRL_STATUS_SEL_IRQ = 2, /*!< IRQ : All-ones if the indexed IRQ flag is raised, otherwise + all-zeroes */ +} PIO0_SM1_EXECCTRL_STATUS_SEL_Enum; + +/* =========================================== PIO0 SM1_EXECCTRL STATUS_N [0..4] =========================================== */ +typedef enum { /*!< PIO0_SM1_EXECCTRL_STATUS_N */ + PIO0_SM1_EXECCTRL_STATUS_N_IRQ = 0, /*!< IRQ : Index 0-7 of an IRQ flag in this PIO block */ + PIO0_SM1_EXECCTRL_STATUS_N_IRQ_PREVPIO = 8, /*!< IRQ_PREVPIO : Index 0-7 of an IRQ flag in the next lower-numbered + PIO block */ + PIO0_SM1_EXECCTRL_STATUS_N_IRQ_NEXTPIO = 16, /*!< IRQ_NEXTPIO : Index 0-7 of an IRQ flag in the next higher-numbered + PIO block */ +} PIO0_SM1_EXECCTRL_STATUS_N_Enum; + +/* ===================================================== SM1_SHIFTCTRL ===================================================== */ +/* ======================================================= SM1_ADDR ======================================================== */ +/* ======================================================= SM1_INSTR ======================================================= */ +/* ====================================================== SM1_PINCTRL ====================================================== */ +/* ====================================================== SM2_CLKDIV ======================================================= */ +/* ===================================================== SM2_EXECCTRL ====================================================== */ +/* ========================================== PIO0 SM2_EXECCTRL STATUS_SEL [5..6] ========================================== */ +typedef enum { /*!< PIO0_SM2_EXECCTRL_STATUS_SEL */ + PIO0_SM2_EXECCTRL_STATUS_SEL_TXLEVEL = 0, /*!< TXLEVEL : All-ones if TX FIFO level < N, otherwise all-zeroes */ + PIO0_SM2_EXECCTRL_STATUS_SEL_RXLEVEL = 1, /*!< RXLEVEL : All-ones if RX FIFO level < N, otherwise all-zeroes */ + PIO0_SM2_EXECCTRL_STATUS_SEL_IRQ = 2, /*!< IRQ : All-ones if the indexed IRQ flag is raised, otherwise + all-zeroes */ +} PIO0_SM2_EXECCTRL_STATUS_SEL_Enum; + +/* =========================================== PIO0 SM2_EXECCTRL STATUS_N [0..4] =========================================== */ +typedef enum { /*!< PIO0_SM2_EXECCTRL_STATUS_N */ + PIO0_SM2_EXECCTRL_STATUS_N_IRQ = 0, /*!< IRQ : Index 0-7 of an IRQ flag in this PIO block */ + PIO0_SM2_EXECCTRL_STATUS_N_IRQ_PREVPIO = 8, /*!< IRQ_PREVPIO : Index 0-7 of an IRQ flag in the next lower-numbered + PIO block */ + PIO0_SM2_EXECCTRL_STATUS_N_IRQ_NEXTPIO = 16, /*!< IRQ_NEXTPIO : Index 0-7 of an IRQ flag in the next higher-numbered + PIO block */ +} PIO0_SM2_EXECCTRL_STATUS_N_Enum; + +/* ===================================================== SM2_SHIFTCTRL ===================================================== */ +/* ======================================================= SM2_ADDR ======================================================== */ +/* ======================================================= SM2_INSTR ======================================================= */ +/* ====================================================== SM2_PINCTRL ====================================================== */ +/* ====================================================== SM3_CLKDIV ======================================================= */ +/* ===================================================== SM3_EXECCTRL ====================================================== */ +/* ========================================== PIO0 SM3_EXECCTRL STATUS_SEL [5..6] ========================================== */ +typedef enum { /*!< PIO0_SM3_EXECCTRL_STATUS_SEL */ + PIO0_SM3_EXECCTRL_STATUS_SEL_TXLEVEL = 0, /*!< TXLEVEL : All-ones if TX FIFO level < N, otherwise all-zeroes */ + PIO0_SM3_EXECCTRL_STATUS_SEL_RXLEVEL = 1, /*!< RXLEVEL : All-ones if RX FIFO level < N, otherwise all-zeroes */ + PIO0_SM3_EXECCTRL_STATUS_SEL_IRQ = 2, /*!< IRQ : All-ones if the indexed IRQ flag is raised, otherwise + all-zeroes */ +} PIO0_SM3_EXECCTRL_STATUS_SEL_Enum; + +/* =========================================== PIO0 SM3_EXECCTRL STATUS_N [0..4] =========================================== */ +typedef enum { /*!< PIO0_SM3_EXECCTRL_STATUS_N */ + PIO0_SM3_EXECCTRL_STATUS_N_IRQ = 0, /*!< IRQ : Index 0-7 of an IRQ flag in this PIO block */ + PIO0_SM3_EXECCTRL_STATUS_N_IRQ_PREVPIO = 8, /*!< IRQ_PREVPIO : Index 0-7 of an IRQ flag in the next lower-numbered + PIO block */ + PIO0_SM3_EXECCTRL_STATUS_N_IRQ_NEXTPIO = 16, /*!< IRQ_NEXTPIO : Index 0-7 of an IRQ flag in the next higher-numbered + PIO block */ +} PIO0_SM3_EXECCTRL_STATUS_N_Enum; + +/* ===================================================== SM3_SHIFTCTRL ===================================================== */ +/* ======================================================= SM3_ADDR ======================================================== */ +/* ======================================================= SM3_INSTR ======================================================= */ +/* ====================================================== SM3_PINCTRL ====================================================== */ +/* ===================================================== RXF0_PUTGET0 ====================================================== */ +/* ===================================================== RXF0_PUTGET1 ====================================================== */ +/* ===================================================== RXF0_PUTGET2 ====================================================== */ +/* ===================================================== RXF0_PUTGET3 ====================================================== */ +/* ===================================================== RXF1_PUTGET0 ====================================================== */ +/* ===================================================== RXF1_PUTGET1 ====================================================== */ +/* ===================================================== RXF1_PUTGET2 ====================================================== */ +/* ===================================================== RXF1_PUTGET3 ====================================================== */ +/* ===================================================== RXF2_PUTGET0 ====================================================== */ +/* ===================================================== RXF2_PUTGET1 ====================================================== */ +/* ===================================================== RXF2_PUTGET2 ====================================================== */ +/* ===================================================== RXF2_PUTGET3 ====================================================== */ +/* ===================================================== RXF3_PUTGET0 ====================================================== */ +/* ===================================================== RXF3_PUTGET1 ====================================================== */ +/* ===================================================== RXF3_PUTGET2 ====================================================== */ +/* ===================================================== RXF3_PUTGET3 ====================================================== */ +/* ======================================================= GPIOBASE ======================================================== */ +/* ========================================================= INTR ========================================================== */ +/* ======================================================= IRQ0_INTE ======================================================= */ +/* ======================================================= IRQ0_INTF ======================================================= */ +/* ======================================================= IRQ0_INTS ======================================================= */ +/* ======================================================= IRQ1_INTE ======================================================= */ +/* ======================================================= IRQ1_INTF ======================================================= */ +/* ======================================================= IRQ1_INTS ======================================================= */ + + +/* =========================================================================================================================== */ +/* ================ BUSCTRL ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BUS_PRIORITY ====================================================== */ +/* =================================================== BUS_PRIORITY_ACK ==================================================== */ +/* ====================================================== PERFCTR_EN ======================================================= */ +/* ======================================================= PERFCTR0 ======================================================== */ +/* ======================================================= PERFSEL0 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL0 PERFSEL0 [0..6] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL0_PERFSEL0 */ + BUSCTRL_PERFSEL0_PERFSEL0_siob_proc1_stall_upstream = 0,/*!< siob_proc1_stall_upstream : siob_proc1_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_siob_proc1_stall_downstream = 1,/*!< siob_proc1_stall_downstream : siob_proc1_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_siob_proc1_access_contested = 2,/*!< siob_proc1_access_contested : siob_proc1_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_siob_proc1_access = 3,/*!< siob_proc1_access : siob_proc1_access */ + BUSCTRL_PERFSEL0_PERFSEL0_siob_proc0_stall_upstream = 4,/*!< siob_proc0_stall_upstream : siob_proc0_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_siob_proc0_stall_downstream = 5,/*!< siob_proc0_stall_downstream : siob_proc0_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_siob_proc0_access_contested = 6,/*!< siob_proc0_access_contested : siob_proc0_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_siob_proc0_access = 7,/*!< siob_proc0_access : siob_proc0_access */ + BUSCTRL_PERFSEL0_PERFSEL0_apb_stall_upstream = 8,/*!< apb_stall_upstream : apb_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_apb_stall_downstream = 9,/*!< apb_stall_downstream : apb_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_apb_access_contested = 10,/*!< apb_access_contested : apb_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_apb_access = 11, /*!< apb_access : apb_access */ + BUSCTRL_PERFSEL0_PERFSEL0_fastperi_stall_upstream = 12,/*!< fastperi_stall_upstream : fastperi_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_fastperi_stall_downstream = 13,/*!< fastperi_stall_downstream : fastperi_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_fastperi_access_contested = 14,/*!< fastperi_access_contested : fastperi_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_fastperi_access = 15,/*!< fastperi_access : fastperi_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram9_stall_upstream = 16,/*!< sram9_stall_upstream : sram9_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram9_stall_downstream = 17,/*!< sram9_stall_downstream : sram9_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram9_access_contested = 18,/*!< sram9_access_contested : sram9_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram9_access = 19, /*!< sram9_access : sram9_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram8_stall_upstream = 20,/*!< sram8_stall_upstream : sram8_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram8_stall_downstream = 21,/*!< sram8_stall_downstream : sram8_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram8_access_contested = 22,/*!< sram8_access_contested : sram8_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram8_access = 23, /*!< sram8_access : sram8_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram7_stall_upstream = 24,/*!< sram7_stall_upstream : sram7_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram7_stall_downstream = 25,/*!< sram7_stall_downstream : sram7_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram7_access_contested = 26,/*!< sram7_access_contested : sram7_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram7_access = 27, /*!< sram7_access : sram7_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram6_stall_upstream = 28,/*!< sram6_stall_upstream : sram6_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram6_stall_downstream = 29,/*!< sram6_stall_downstream : sram6_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram6_access_contested = 30,/*!< sram6_access_contested : sram6_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram6_access = 31, /*!< sram6_access : sram6_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram5_stall_upstream = 32,/*!< sram5_stall_upstream : sram5_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram5_stall_downstream = 33,/*!< sram5_stall_downstream : sram5_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram5_access_contested = 34,/*!< sram5_access_contested : sram5_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram5_access = 35, /*!< sram5_access : sram5_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram4_stall_upstream = 36,/*!< sram4_stall_upstream : sram4_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram4_stall_downstream = 37,/*!< sram4_stall_downstream : sram4_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram4_access_contested = 38,/*!< sram4_access_contested : sram4_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram4_access = 39, /*!< sram4_access : sram4_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram3_stall_upstream = 40,/*!< sram3_stall_upstream : sram3_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram3_stall_downstream = 41,/*!< sram3_stall_downstream : sram3_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram3_access_contested = 42,/*!< sram3_access_contested : sram3_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram3_access = 43, /*!< sram3_access : sram3_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram2_stall_upstream = 44,/*!< sram2_stall_upstream : sram2_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram2_stall_downstream = 45,/*!< sram2_stall_downstream : sram2_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram2_access_contested = 46,/*!< sram2_access_contested : sram2_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram2_access = 47, /*!< sram2_access : sram2_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram1_stall_upstream = 48,/*!< sram1_stall_upstream : sram1_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram1_stall_downstream = 49,/*!< sram1_stall_downstream : sram1_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram1_access_contested = 50,/*!< sram1_access_contested : sram1_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram1_access = 51, /*!< sram1_access : sram1_access */ + BUSCTRL_PERFSEL0_PERFSEL0_sram0_stall_upstream = 52,/*!< sram0_stall_upstream : sram0_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram0_stall_downstream = 53,/*!< sram0_stall_downstream : sram0_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_sram0_access_contested = 54,/*!< sram0_access_contested : sram0_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram0_access = 55, /*!< sram0_access : sram0_access */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main1_stall_upstream = 56,/*!< xip_main1_stall_upstream : xip_main1_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main1_stall_downstream = 57,/*!< xip_main1_stall_downstream : xip_main1_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main1_access_contested = 58,/*!< xip_main1_access_contested : xip_main1_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main1_access = 59,/*!< xip_main1_access : xip_main1_access */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main0_stall_upstream = 60,/*!< xip_main0_stall_upstream : xip_main0_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main0_stall_downstream = 61,/*!< xip_main0_stall_downstream : xip_main0_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main0_access_contested = 62,/*!< xip_main0_access_contested : xip_main0_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main0_access = 63,/*!< xip_main0_access : xip_main0_access */ + BUSCTRL_PERFSEL0_PERFSEL0_rom_stall_upstream = 64,/*!< rom_stall_upstream : rom_stall_upstream */ + BUSCTRL_PERFSEL0_PERFSEL0_rom_stall_downstream = 65,/*!< rom_stall_downstream : rom_stall_downstream */ + BUSCTRL_PERFSEL0_PERFSEL0_rom_access_contested = 66,/*!< rom_access_contested : rom_access_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_rom_access = 67, /*!< rom_access : rom_access */ +} BUSCTRL_PERFSEL0_PERFSEL0_Enum; + +/* ======================================================= PERFCTR1 ======================================================== */ +/* ======================================================= PERFSEL1 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL1 PERFSEL1 [0..6] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL1_PERFSEL1 */ + BUSCTRL_PERFSEL1_PERFSEL1_siob_proc1_stall_upstream = 0,/*!< siob_proc1_stall_upstream : siob_proc1_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_siob_proc1_stall_downstream = 1,/*!< siob_proc1_stall_downstream : siob_proc1_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_siob_proc1_access_contested = 2,/*!< siob_proc1_access_contested : siob_proc1_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_siob_proc1_access = 3,/*!< siob_proc1_access : siob_proc1_access */ + BUSCTRL_PERFSEL1_PERFSEL1_siob_proc0_stall_upstream = 4,/*!< siob_proc0_stall_upstream : siob_proc0_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_siob_proc0_stall_downstream = 5,/*!< siob_proc0_stall_downstream : siob_proc0_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_siob_proc0_access_contested = 6,/*!< siob_proc0_access_contested : siob_proc0_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_siob_proc0_access = 7,/*!< siob_proc0_access : siob_proc0_access */ + BUSCTRL_PERFSEL1_PERFSEL1_apb_stall_upstream = 8,/*!< apb_stall_upstream : apb_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_apb_stall_downstream = 9,/*!< apb_stall_downstream : apb_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_apb_access_contested = 10,/*!< apb_access_contested : apb_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_apb_access = 11, /*!< apb_access : apb_access */ + BUSCTRL_PERFSEL1_PERFSEL1_fastperi_stall_upstream = 12,/*!< fastperi_stall_upstream : fastperi_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_fastperi_stall_downstream = 13,/*!< fastperi_stall_downstream : fastperi_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_fastperi_access_contested = 14,/*!< fastperi_access_contested : fastperi_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_fastperi_access = 15,/*!< fastperi_access : fastperi_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram9_stall_upstream = 16,/*!< sram9_stall_upstream : sram9_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram9_stall_downstream = 17,/*!< sram9_stall_downstream : sram9_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram9_access_contested = 18,/*!< sram9_access_contested : sram9_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram9_access = 19, /*!< sram9_access : sram9_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram8_stall_upstream = 20,/*!< sram8_stall_upstream : sram8_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram8_stall_downstream = 21,/*!< sram8_stall_downstream : sram8_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram8_access_contested = 22,/*!< sram8_access_contested : sram8_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram8_access = 23, /*!< sram8_access : sram8_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram7_stall_upstream = 24,/*!< sram7_stall_upstream : sram7_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram7_stall_downstream = 25,/*!< sram7_stall_downstream : sram7_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram7_access_contested = 26,/*!< sram7_access_contested : sram7_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram7_access = 27, /*!< sram7_access : sram7_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram6_stall_upstream = 28,/*!< sram6_stall_upstream : sram6_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram6_stall_downstream = 29,/*!< sram6_stall_downstream : sram6_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram6_access_contested = 30,/*!< sram6_access_contested : sram6_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram6_access = 31, /*!< sram6_access : sram6_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram5_stall_upstream = 32,/*!< sram5_stall_upstream : sram5_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram5_stall_downstream = 33,/*!< sram5_stall_downstream : sram5_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram5_access_contested = 34,/*!< sram5_access_contested : sram5_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram5_access = 35, /*!< sram5_access : sram5_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram4_stall_upstream = 36,/*!< sram4_stall_upstream : sram4_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram4_stall_downstream = 37,/*!< sram4_stall_downstream : sram4_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram4_access_contested = 38,/*!< sram4_access_contested : sram4_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram4_access = 39, /*!< sram4_access : sram4_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram3_stall_upstream = 40,/*!< sram3_stall_upstream : sram3_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram3_stall_downstream = 41,/*!< sram3_stall_downstream : sram3_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram3_access_contested = 42,/*!< sram3_access_contested : sram3_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram3_access = 43, /*!< sram3_access : sram3_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram2_stall_upstream = 44,/*!< sram2_stall_upstream : sram2_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram2_stall_downstream = 45,/*!< sram2_stall_downstream : sram2_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram2_access_contested = 46,/*!< sram2_access_contested : sram2_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram2_access = 47, /*!< sram2_access : sram2_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram1_stall_upstream = 48,/*!< sram1_stall_upstream : sram1_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram1_stall_downstream = 49,/*!< sram1_stall_downstream : sram1_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram1_access_contested = 50,/*!< sram1_access_contested : sram1_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram1_access = 51, /*!< sram1_access : sram1_access */ + BUSCTRL_PERFSEL1_PERFSEL1_sram0_stall_upstream = 52,/*!< sram0_stall_upstream : sram0_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram0_stall_downstream = 53,/*!< sram0_stall_downstream : sram0_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_sram0_access_contested = 54,/*!< sram0_access_contested : sram0_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram0_access = 55, /*!< sram0_access : sram0_access */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main1_stall_upstream = 56,/*!< xip_main1_stall_upstream : xip_main1_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main1_stall_downstream = 57,/*!< xip_main1_stall_downstream : xip_main1_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main1_access_contested = 58,/*!< xip_main1_access_contested : xip_main1_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main1_access = 59,/*!< xip_main1_access : xip_main1_access */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main0_stall_upstream = 60,/*!< xip_main0_stall_upstream : xip_main0_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main0_stall_downstream = 61,/*!< xip_main0_stall_downstream : xip_main0_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main0_access_contested = 62,/*!< xip_main0_access_contested : xip_main0_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main0_access = 63,/*!< xip_main0_access : xip_main0_access */ + BUSCTRL_PERFSEL1_PERFSEL1_rom_stall_upstream = 64,/*!< rom_stall_upstream : rom_stall_upstream */ + BUSCTRL_PERFSEL1_PERFSEL1_rom_stall_downstream = 65,/*!< rom_stall_downstream : rom_stall_downstream */ + BUSCTRL_PERFSEL1_PERFSEL1_rom_access_contested = 66,/*!< rom_access_contested : rom_access_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_rom_access = 67, /*!< rom_access : rom_access */ +} BUSCTRL_PERFSEL1_PERFSEL1_Enum; + +/* ======================================================= PERFCTR2 ======================================================== */ +/* ======================================================= PERFSEL2 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL2 PERFSEL2 [0..6] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL2_PERFSEL2 */ + BUSCTRL_PERFSEL2_PERFSEL2_siob_proc1_stall_upstream = 0,/*!< siob_proc1_stall_upstream : siob_proc1_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_siob_proc1_stall_downstream = 1,/*!< siob_proc1_stall_downstream : siob_proc1_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_siob_proc1_access_contested = 2,/*!< siob_proc1_access_contested : siob_proc1_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_siob_proc1_access = 3,/*!< siob_proc1_access : siob_proc1_access */ + BUSCTRL_PERFSEL2_PERFSEL2_siob_proc0_stall_upstream = 4,/*!< siob_proc0_stall_upstream : siob_proc0_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_siob_proc0_stall_downstream = 5,/*!< siob_proc0_stall_downstream : siob_proc0_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_siob_proc0_access_contested = 6,/*!< siob_proc0_access_contested : siob_proc0_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_siob_proc0_access = 7,/*!< siob_proc0_access : siob_proc0_access */ + BUSCTRL_PERFSEL2_PERFSEL2_apb_stall_upstream = 8,/*!< apb_stall_upstream : apb_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_apb_stall_downstream = 9,/*!< apb_stall_downstream : apb_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_apb_access_contested = 10,/*!< apb_access_contested : apb_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_apb_access = 11, /*!< apb_access : apb_access */ + BUSCTRL_PERFSEL2_PERFSEL2_fastperi_stall_upstream = 12,/*!< fastperi_stall_upstream : fastperi_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_fastperi_stall_downstream = 13,/*!< fastperi_stall_downstream : fastperi_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_fastperi_access_contested = 14,/*!< fastperi_access_contested : fastperi_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_fastperi_access = 15,/*!< fastperi_access : fastperi_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram9_stall_upstream = 16,/*!< sram9_stall_upstream : sram9_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram9_stall_downstream = 17,/*!< sram9_stall_downstream : sram9_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram9_access_contested = 18,/*!< sram9_access_contested : sram9_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram9_access = 19, /*!< sram9_access : sram9_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram8_stall_upstream = 20,/*!< sram8_stall_upstream : sram8_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram8_stall_downstream = 21,/*!< sram8_stall_downstream : sram8_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram8_access_contested = 22,/*!< sram8_access_contested : sram8_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram8_access = 23, /*!< sram8_access : sram8_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram7_stall_upstream = 24,/*!< sram7_stall_upstream : sram7_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram7_stall_downstream = 25,/*!< sram7_stall_downstream : sram7_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram7_access_contested = 26,/*!< sram7_access_contested : sram7_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram7_access = 27, /*!< sram7_access : sram7_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram6_stall_upstream = 28,/*!< sram6_stall_upstream : sram6_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram6_stall_downstream = 29,/*!< sram6_stall_downstream : sram6_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram6_access_contested = 30,/*!< sram6_access_contested : sram6_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram6_access = 31, /*!< sram6_access : sram6_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram5_stall_upstream = 32,/*!< sram5_stall_upstream : sram5_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram5_stall_downstream = 33,/*!< sram5_stall_downstream : sram5_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram5_access_contested = 34,/*!< sram5_access_contested : sram5_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram5_access = 35, /*!< sram5_access : sram5_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram4_stall_upstream = 36,/*!< sram4_stall_upstream : sram4_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram4_stall_downstream = 37,/*!< sram4_stall_downstream : sram4_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram4_access_contested = 38,/*!< sram4_access_contested : sram4_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram4_access = 39, /*!< sram4_access : sram4_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram3_stall_upstream = 40,/*!< sram3_stall_upstream : sram3_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram3_stall_downstream = 41,/*!< sram3_stall_downstream : sram3_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram3_access_contested = 42,/*!< sram3_access_contested : sram3_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram3_access = 43, /*!< sram3_access : sram3_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram2_stall_upstream = 44,/*!< sram2_stall_upstream : sram2_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram2_stall_downstream = 45,/*!< sram2_stall_downstream : sram2_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram2_access_contested = 46,/*!< sram2_access_contested : sram2_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram2_access = 47, /*!< sram2_access : sram2_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram1_stall_upstream = 48,/*!< sram1_stall_upstream : sram1_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram1_stall_downstream = 49,/*!< sram1_stall_downstream : sram1_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram1_access_contested = 50,/*!< sram1_access_contested : sram1_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram1_access = 51, /*!< sram1_access : sram1_access */ + BUSCTRL_PERFSEL2_PERFSEL2_sram0_stall_upstream = 52,/*!< sram0_stall_upstream : sram0_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram0_stall_downstream = 53,/*!< sram0_stall_downstream : sram0_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_sram0_access_contested = 54,/*!< sram0_access_contested : sram0_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram0_access = 55, /*!< sram0_access : sram0_access */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main1_stall_upstream = 56,/*!< xip_main1_stall_upstream : xip_main1_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main1_stall_downstream = 57,/*!< xip_main1_stall_downstream : xip_main1_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main1_access_contested = 58,/*!< xip_main1_access_contested : xip_main1_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main1_access = 59,/*!< xip_main1_access : xip_main1_access */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main0_stall_upstream = 60,/*!< xip_main0_stall_upstream : xip_main0_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main0_stall_downstream = 61,/*!< xip_main0_stall_downstream : xip_main0_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main0_access_contested = 62,/*!< xip_main0_access_contested : xip_main0_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main0_access = 63,/*!< xip_main0_access : xip_main0_access */ + BUSCTRL_PERFSEL2_PERFSEL2_rom_stall_upstream = 64,/*!< rom_stall_upstream : rom_stall_upstream */ + BUSCTRL_PERFSEL2_PERFSEL2_rom_stall_downstream = 65,/*!< rom_stall_downstream : rom_stall_downstream */ + BUSCTRL_PERFSEL2_PERFSEL2_rom_access_contested = 66,/*!< rom_access_contested : rom_access_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_rom_access = 67, /*!< rom_access : rom_access */ +} BUSCTRL_PERFSEL2_PERFSEL2_Enum; + +/* ======================================================= PERFCTR3 ======================================================== */ +/* ======================================================= PERFSEL3 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL3 PERFSEL3 [0..6] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL3_PERFSEL3 */ + BUSCTRL_PERFSEL3_PERFSEL3_siob_proc1_stall_upstream = 0,/*!< siob_proc1_stall_upstream : siob_proc1_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_siob_proc1_stall_downstream = 1,/*!< siob_proc1_stall_downstream : siob_proc1_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_siob_proc1_access_contested = 2,/*!< siob_proc1_access_contested : siob_proc1_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_siob_proc1_access = 3,/*!< siob_proc1_access : siob_proc1_access */ + BUSCTRL_PERFSEL3_PERFSEL3_siob_proc0_stall_upstream = 4,/*!< siob_proc0_stall_upstream : siob_proc0_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_siob_proc0_stall_downstream = 5,/*!< siob_proc0_stall_downstream : siob_proc0_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_siob_proc0_access_contested = 6,/*!< siob_proc0_access_contested : siob_proc0_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_siob_proc0_access = 7,/*!< siob_proc0_access : siob_proc0_access */ + BUSCTRL_PERFSEL3_PERFSEL3_apb_stall_upstream = 8,/*!< apb_stall_upstream : apb_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_apb_stall_downstream = 9,/*!< apb_stall_downstream : apb_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_apb_access_contested = 10,/*!< apb_access_contested : apb_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_apb_access = 11, /*!< apb_access : apb_access */ + BUSCTRL_PERFSEL3_PERFSEL3_fastperi_stall_upstream = 12,/*!< fastperi_stall_upstream : fastperi_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_fastperi_stall_downstream = 13,/*!< fastperi_stall_downstream : fastperi_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_fastperi_access_contested = 14,/*!< fastperi_access_contested : fastperi_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_fastperi_access = 15,/*!< fastperi_access : fastperi_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram9_stall_upstream = 16,/*!< sram9_stall_upstream : sram9_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram9_stall_downstream = 17,/*!< sram9_stall_downstream : sram9_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram9_access_contested = 18,/*!< sram9_access_contested : sram9_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram9_access = 19, /*!< sram9_access : sram9_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram8_stall_upstream = 20,/*!< sram8_stall_upstream : sram8_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram8_stall_downstream = 21,/*!< sram8_stall_downstream : sram8_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram8_access_contested = 22,/*!< sram8_access_contested : sram8_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram8_access = 23, /*!< sram8_access : sram8_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram7_stall_upstream = 24,/*!< sram7_stall_upstream : sram7_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram7_stall_downstream = 25,/*!< sram7_stall_downstream : sram7_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram7_access_contested = 26,/*!< sram7_access_contested : sram7_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram7_access = 27, /*!< sram7_access : sram7_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram6_stall_upstream = 28,/*!< sram6_stall_upstream : sram6_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram6_stall_downstream = 29,/*!< sram6_stall_downstream : sram6_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram6_access_contested = 30,/*!< sram6_access_contested : sram6_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram6_access = 31, /*!< sram6_access : sram6_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram5_stall_upstream = 32,/*!< sram5_stall_upstream : sram5_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram5_stall_downstream = 33,/*!< sram5_stall_downstream : sram5_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram5_access_contested = 34,/*!< sram5_access_contested : sram5_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram5_access = 35, /*!< sram5_access : sram5_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram4_stall_upstream = 36,/*!< sram4_stall_upstream : sram4_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram4_stall_downstream = 37,/*!< sram4_stall_downstream : sram4_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram4_access_contested = 38,/*!< sram4_access_contested : sram4_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram4_access = 39, /*!< sram4_access : sram4_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram3_stall_upstream = 40,/*!< sram3_stall_upstream : sram3_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram3_stall_downstream = 41,/*!< sram3_stall_downstream : sram3_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram3_access_contested = 42,/*!< sram3_access_contested : sram3_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram3_access = 43, /*!< sram3_access : sram3_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram2_stall_upstream = 44,/*!< sram2_stall_upstream : sram2_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram2_stall_downstream = 45,/*!< sram2_stall_downstream : sram2_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram2_access_contested = 46,/*!< sram2_access_contested : sram2_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram2_access = 47, /*!< sram2_access : sram2_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram1_stall_upstream = 48,/*!< sram1_stall_upstream : sram1_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram1_stall_downstream = 49,/*!< sram1_stall_downstream : sram1_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram1_access_contested = 50,/*!< sram1_access_contested : sram1_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram1_access = 51, /*!< sram1_access : sram1_access */ + BUSCTRL_PERFSEL3_PERFSEL3_sram0_stall_upstream = 52,/*!< sram0_stall_upstream : sram0_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram0_stall_downstream = 53,/*!< sram0_stall_downstream : sram0_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_sram0_access_contested = 54,/*!< sram0_access_contested : sram0_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram0_access = 55, /*!< sram0_access : sram0_access */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main1_stall_upstream = 56,/*!< xip_main1_stall_upstream : xip_main1_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main1_stall_downstream = 57,/*!< xip_main1_stall_downstream : xip_main1_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main1_access_contested = 58,/*!< xip_main1_access_contested : xip_main1_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main1_access = 59,/*!< xip_main1_access : xip_main1_access */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main0_stall_upstream = 60,/*!< xip_main0_stall_upstream : xip_main0_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main0_stall_downstream = 61,/*!< xip_main0_stall_downstream : xip_main0_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main0_access_contested = 62,/*!< xip_main0_access_contested : xip_main0_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main0_access = 63,/*!< xip_main0_access : xip_main0_access */ + BUSCTRL_PERFSEL3_PERFSEL3_rom_stall_upstream = 64,/*!< rom_stall_upstream : rom_stall_upstream */ + BUSCTRL_PERFSEL3_PERFSEL3_rom_stall_downstream = 65,/*!< rom_stall_downstream : rom_stall_downstream */ + BUSCTRL_PERFSEL3_PERFSEL3_rom_access_contested = 66,/*!< rom_access_contested : rom_access_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_rom_access = 67, /*!< rom_access : rom_access */ +} BUSCTRL_PERFSEL3_PERFSEL3_Enum; + + + +/* =========================================================================================================================== */ +/* ================ SIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CPUID ========================================================= */ +/* ======================================================== GPIO_IN ======================================================== */ +/* ====================================================== GPIO_HI_IN ======================================================= */ +/* ======================================================= GPIO_OUT ======================================================== */ +/* ====================================================== GPIO_HI_OUT ====================================================== */ +/* ===================================================== GPIO_OUT_SET ====================================================== */ +/* ==================================================== GPIO_HI_OUT_SET ==================================================== */ +/* ===================================================== GPIO_OUT_CLR ====================================================== */ +/* ==================================================== GPIO_HI_OUT_CLR ==================================================== */ +/* ===================================================== GPIO_OUT_XOR ====================================================== */ +/* ==================================================== GPIO_HI_OUT_XOR ==================================================== */ +/* ======================================================== GPIO_OE ======================================================== */ +/* ====================================================== GPIO_HI_OE ======================================================= */ +/* ====================================================== GPIO_OE_SET ====================================================== */ +/* ==================================================== GPIO_HI_OE_SET ===================================================== */ +/* ====================================================== GPIO_OE_CLR ====================================================== */ +/* ==================================================== GPIO_HI_OE_CLR ===================================================== */ +/* ====================================================== GPIO_OE_XOR ====================================================== */ +/* ==================================================== GPIO_HI_OE_XOR ===================================================== */ +/* ======================================================== FIFO_ST ======================================================== */ +/* ======================================================== FIFO_WR ======================================================== */ +/* ======================================================== FIFO_RD ======================================================== */ +/* ====================================================== SPINLOCK_ST ====================================================== */ +/* ==================================================== INTERP0_ACCUM0 ===================================================== */ +/* ==================================================== INTERP0_ACCUM1 ===================================================== */ +/* ===================================================== INTERP0_BASE0 ===================================================== */ +/* ===================================================== INTERP0_BASE1 ===================================================== */ +/* ===================================================== INTERP0_BASE2 ===================================================== */ +/* =================================================== INTERP0_POP_LANE0 =================================================== */ +/* =================================================== INTERP0_POP_LANE1 =================================================== */ +/* =================================================== INTERP0_POP_FULL ==================================================== */ +/* ================================================== INTERP0_PEEK_LANE0 =================================================== */ +/* ================================================== INTERP0_PEEK_LANE1 =================================================== */ +/* =================================================== INTERP0_PEEK_FULL =================================================== */ +/* ================================================== INTERP0_CTRL_LANE0 =================================================== */ +/* ================================================== INTERP0_CTRL_LANE1 =================================================== */ +/* ================================================== INTERP0_ACCUM0_ADD =================================================== */ +/* ================================================== INTERP0_ACCUM1_ADD =================================================== */ +/* ================================================== INTERP0_BASE_1AND0 =================================================== */ +/* ==================================================== INTERP1_ACCUM0 ===================================================== */ +/* ==================================================== INTERP1_ACCUM1 ===================================================== */ +/* ===================================================== INTERP1_BASE0 ===================================================== */ +/* ===================================================== INTERP1_BASE1 ===================================================== */ +/* ===================================================== INTERP1_BASE2 ===================================================== */ +/* =================================================== INTERP1_POP_LANE0 =================================================== */ +/* =================================================== INTERP1_POP_LANE1 =================================================== */ +/* =================================================== INTERP1_POP_FULL ==================================================== */ +/* ================================================== INTERP1_PEEK_LANE0 =================================================== */ +/* ================================================== INTERP1_PEEK_LANE1 =================================================== */ +/* =================================================== INTERP1_PEEK_FULL =================================================== */ +/* ================================================== INTERP1_CTRL_LANE0 =================================================== */ +/* ================================================== INTERP1_CTRL_LANE1 =================================================== */ +/* ================================================== INTERP1_ACCUM0_ADD =================================================== */ +/* ================================================== INTERP1_ACCUM1_ADD =================================================== */ +/* ================================================== INTERP1_BASE_1AND0 =================================================== */ +/* ======================================================= SPINLOCK0 ======================================================= */ +/* ======================================================= SPINLOCK1 ======================================================= */ +/* ======================================================= SPINLOCK2 ======================================================= */ +/* ======================================================= SPINLOCK3 ======================================================= */ +/* ======================================================= SPINLOCK4 ======================================================= */ +/* ======================================================= SPINLOCK5 ======================================================= */ +/* ======================================================= SPINLOCK6 ======================================================= */ +/* ======================================================= SPINLOCK7 ======================================================= */ +/* ======================================================= SPINLOCK8 ======================================================= */ +/* ======================================================= SPINLOCK9 ======================================================= */ +/* ====================================================== SPINLOCK10 ======================================================= */ +/* ====================================================== SPINLOCK11 ======================================================= */ +/* ====================================================== SPINLOCK12 ======================================================= */ +/* ====================================================== SPINLOCK13 ======================================================= */ +/* ====================================================== SPINLOCK14 ======================================================= */ +/* ====================================================== SPINLOCK15 ======================================================= */ +/* ====================================================== SPINLOCK16 ======================================================= */ +/* ====================================================== SPINLOCK17 ======================================================= */ +/* ====================================================== SPINLOCK18 ======================================================= */ +/* ====================================================== SPINLOCK19 ======================================================= */ +/* ====================================================== SPINLOCK20 ======================================================= */ +/* ====================================================== SPINLOCK21 ======================================================= */ +/* ====================================================== SPINLOCK22 ======================================================= */ +/* ====================================================== SPINLOCK23 ======================================================= */ +/* ====================================================== SPINLOCK24 ======================================================= */ +/* ====================================================== SPINLOCK25 ======================================================= */ +/* ====================================================== SPINLOCK26 ======================================================= */ +/* ====================================================== SPINLOCK27 ======================================================= */ +/* ====================================================== SPINLOCK28 ======================================================= */ +/* ====================================================== SPINLOCK29 ======================================================= */ +/* ====================================================== SPINLOCK30 ======================================================= */ +/* ====================================================== SPINLOCK31 ======================================================= */ +/* =================================================== DOORBELL_OUT_SET ==================================================== */ +/* =================================================== DOORBELL_OUT_CLR ==================================================== */ +/* ==================================================== DOORBELL_IN_SET ==================================================== */ +/* ==================================================== DOORBELL_IN_CLR ==================================================== */ +/* ====================================================== PERI_NONSEC ====================================================== */ +/* ===================================================== RISCV_SOFTIRQ ===================================================== */ +/* ====================================================== MTIME_CTRL ======================================================= */ +/* ========================================================= MTIME ========================================================= */ +/* ======================================================== MTIMEH ========================================================= */ +/* ======================================================= MTIMECMP ======================================================== */ +/* ======================================================= MTIMECMPH ======================================================= */ +/* ======================================================= TMDS_CTRL ======================================================= */ +/* =========================================== SIO TMDS_CTRL PIX_SHIFT [24..26] ============================================ */ +typedef enum { /*!< SIO_TMDS_CTRL_PIX_SHIFT */ + SIO_TMDS_CTRL_PIX_SHIFT_0 = 0, /*!< 0 : Do not shift the colour data register. */ + SIO_TMDS_CTRL_PIX_SHIFT_1 = 1, /*!< 1 : Shift the colour data register by 1 bit */ + SIO_TMDS_CTRL_PIX_SHIFT_2 = 2, /*!< 2 : Shift the colour data register by 2 bits */ + SIO_TMDS_CTRL_PIX_SHIFT_4 = 3, /*!< 4 : Shift the colour data register by 4 bits */ + SIO_TMDS_CTRL_PIX_SHIFT_8 = 4, /*!< 8 : Shift the colour data register by 8 bits */ + SIO_TMDS_CTRL_PIX_SHIFT_16 = 5, /*!< 16 : Shift the colour data register by 16 bits */ +} SIO_TMDS_CTRL_PIX_SHIFT_Enum; + +/* ====================================================== TMDS_WDATA ======================================================= */ +/* =================================================== TMDS_PEEK_SINGLE ==================================================== */ +/* ==================================================== TMDS_POP_SINGLE ==================================================== */ +/* ================================================== TMDS_PEEK_DOUBLE_L0 ================================================== */ +/* ================================================== TMDS_POP_DOUBLE_L0 =================================================== */ +/* ================================================== TMDS_PEEK_DOUBLE_L1 ================================================== */ +/* ================================================== TMDS_POP_DOUBLE_L1 =================================================== */ +/* ================================================== TMDS_PEEK_DOUBLE_L2 ================================================== */ +/* ================================================== TMDS_POP_DOUBLE_L2 =================================================== */ + + +/* =========================================================================================================================== */ +/* ================ BOOTRAM ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== WRITE_ONCE0 ====================================================== */ +/* ====================================================== WRITE_ONCE1 ====================================================== */ +/* ===================================================== BOOTLOCK_STAT ===================================================== */ +/* ======================================================= BOOTLOCK0 ======================================================= */ +/* ======================================================= BOOTLOCK1 ======================================================= */ +/* ======================================================= BOOTLOCK2 ======================================================= */ +/* ======================================================= BOOTLOCK3 ======================================================= */ +/* ======================================================= BOOTLOCK4 ======================================================= */ +/* ======================================================= BOOTLOCK5 ======================================================= */ +/* ======================================================= BOOTLOCK6 ======================================================= */ +/* ======================================================= BOOTLOCK7 ======================================================= */ + + +/* =========================================================================================================================== */ +/* ================ CORESIGHT_TRACE ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CTRL_STATUS ====================================================== */ +/* ================================================== TRACE_CAPTURE_FIFO =================================================== */ + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ADDR_ENDP ======================================================= */ +/* ====================================================== ADDR_ENDP1 ======================================================= */ +/* ====================================================== ADDR_ENDP2 ======================================================= */ +/* ====================================================== ADDR_ENDP3 ======================================================= */ +/* ====================================================== ADDR_ENDP4 ======================================================= */ +/* ====================================================== ADDR_ENDP5 ======================================================= */ +/* ====================================================== ADDR_ENDP6 ======================================================= */ +/* ====================================================== ADDR_ENDP7 ======================================================= */ +/* ====================================================== ADDR_ENDP8 ======================================================= */ +/* ====================================================== ADDR_ENDP9 ======================================================= */ +/* ====================================================== ADDR_ENDP10 ====================================================== */ +/* ====================================================== ADDR_ENDP11 ====================================================== */ +/* ====================================================== ADDR_ENDP12 ====================================================== */ +/* ====================================================== ADDR_ENDP13 ====================================================== */ +/* ====================================================== ADDR_ENDP14 ====================================================== */ +/* ====================================================== ADDR_ENDP15 ====================================================== */ +/* ======================================================= MAIN_CTRL ======================================================= */ +/* ======================================================== SOF_WR ========================================================= */ +/* ======================================================== SOF_RD ========================================================= */ +/* ======================================================= SIE_CTRL ======================================================== */ +/* ====================================================== SIE_STATUS ======================================================= */ +/* ====================================================== INT_EP_CTRL ====================================================== */ +/* ====================================================== BUFF_STATUS ====================================================== */ +/* ================================================ BUFF_CPU_SHOULD_HANDLE ================================================= */ +/* ======================================================= EP_ABORT ======================================================== */ +/* ===================================================== EP_ABORT_DONE ===================================================== */ +/* ===================================================== EP_STALL_ARM ====================================================== */ +/* ======================================================= NAK_POLL ======================================================== */ +/* ================================================== EP_STATUS_STALL_NAK ================================================== */ +/* ====================================================== USB_MUXING ======================================================= */ +/* ======================================================== USB_PWR ======================================================== */ +/* ===================================================== USBPHY_DIRECT ===================================================== */ +/* ================================================ USBPHY_DIRECT_OVERRIDE ================================================= */ +/* ====================================================== USBPHY_TRIM ====================================================== */ +/* =================================================== LINESTATE_TUNING ==================================================== */ +/* ========================================================= INTR ========================================================== */ +/* ========================================================= INTE ========================================================== */ +/* ========================================================= INTF ========================================================== */ +/* ========================================================= INTS ========================================================== */ +/* =================================================== SOF_TIMESTAMP_RAW =================================================== */ +/* ================================================== SOF_TIMESTAMP_LAST =================================================== */ +/* ======================================================= SM_STATE ======================================================== */ +/* ====================================================== EP_TX_ERROR ====================================================== */ +/* ====================================================== EP_RX_ERROR ====================================================== */ +/* ==================================================== DEV_SM_WATCHDOG ==================================================== */ + + +/* =========================================================================================================================== */ +/* ================ TRNG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== RNG_IMR ======================================================== */ +/* ======================================================== RNG_ISR ======================================================== */ +/* ======================================================== RNG_ICR ======================================================== */ +/* ====================================================== TRNG_CONFIG ====================================================== */ +/* ====================================================== TRNG_VALID ======================================================= */ +/* ======================================================= EHR_DATA0 ======================================================= */ +/* ======================================================= EHR_DATA1 ======================================================= */ +/* ======================================================= EHR_DATA2 ======================================================= */ +/* ======================================================= EHR_DATA3 ======================================================= */ +/* ======================================================= EHR_DATA4 ======================================================= */ +/* ======================================================= EHR_DATA5 ======================================================= */ +/* =================================================== RND_SOURCE_ENABLE =================================================== */ +/* ====================================================== SAMPLE_CNT1 ====================================================== */ +/* ================================================== AUTOCORR_STATISTIC =================================================== */ +/* ================================================== TRNG_DEBUG_CONTROL =================================================== */ +/* ===================================================== TRNG_SW_RESET ===================================================== */ +/* ================================================== RNG_DEBUG_EN_INPUT =================================================== */ +/* ======================================================= TRNG_BUSY ======================================================= */ +/* =================================================== RST_BITS_COUNTER ==================================================== */ +/* ====================================================== RNG_VERSION ====================================================== */ +/* ==================================================== RNG_BIST_CNTR_0 ==================================================== */ +/* ==================================================== RNG_BIST_CNTR_1 ==================================================== */ +/* ==================================================== RNG_BIST_CNTR_2 ==================================================== */ + + +/* =========================================================================================================================== */ +/* ================ GLITCH_DETECTOR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ARM ========================================================== */ +/* ============================================ GLITCH_DETECTOR ARM ARM [0..15] ============================================ */ +typedef enum { /*!< GLITCH_DETECTOR_ARM_ARM */ + GLITCH_DETECTOR_ARM_ARM_no = 23469, /*!< no : Do not force the glitch detectors to be armed */ + GLITCH_DETECTOR_ARM_ARM_yes = 0, /*!< yes : Force the glitch detectors to be armed. (Any value other + than ARM_NO counts as YES) */ +} GLITCH_DETECTOR_ARM_ARM_Enum; + +/* ======================================================== DISARM ========================================================= */ +/* ========================================= GLITCH_DETECTOR DISARM DISARM [0..15] ========================================= */ +typedef enum { /*!< GLITCH_DETECTOR_DISARM_DISARM */ + GLITCH_DETECTOR_DISARM_DISARM_no = 0, /*!< no : Do not disarm the glitch detectors. (Any value other than + DISARM_YES counts as NO) */ + GLITCH_DETECTOR_DISARM_DISARM_yes = 56495, /*!< yes : Disarm the glitch detectors */ +} GLITCH_DETECTOR_DISARM_DISARM_Enum; + +/* ====================================================== SENSITIVITY ====================================================== */ +/* ===================================== GLITCH_DETECTOR SENSITIVITY DEFAULT [24..31] ====================================== */ +typedef enum { /*!< GLITCH_DETECTOR_SENSITIVITY_DEFAULT */ + GLITCH_DETECTOR_SENSITIVITY_DEFAULT_yes = 0, /*!< yes : Use the default sensitivity configured in OTP for all + detectors. (Any value other than DEFAULT_NO counts as YES) */ + GLITCH_DETECTOR_SENSITIVITY_DEFAULT_no = 222, /*!< no : Do not use the default sensitivity configured in OTP. Instead + use the value from this register. */ +} GLITCH_DETECTOR_SENSITIVITY_DEFAULT_Enum; + +/* ========================================================= LOCK ========================================================== */ +/* ====================================================== TRIG_STATUS ====================================================== */ +/* ====================================================== TRIG_FORCE ======================================================= */ + + +/* =========================================================================================================================== */ +/* ================ OTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SW_LOCK0 ======================================================== */ +/* =============================================== OTP SW_LOCK0 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK0_NSEC */ + OTP_SW_LOCK0_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK0_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK0_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK0_NSEC_Enum; + +/* ================================================ OTP SW_LOCK0 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK0_SEC */ + OTP_SW_LOCK0_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK0_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK0_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK0_SEC_Enum; + +/* ======================================================= SW_LOCK1 ======================================================== */ +/* =============================================== OTP SW_LOCK1 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK1_NSEC */ + OTP_SW_LOCK1_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK1_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK1_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK1_NSEC_Enum; + +/* ================================================ OTP SW_LOCK1 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK1_SEC */ + OTP_SW_LOCK1_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK1_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK1_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK1_SEC_Enum; + +/* ======================================================= SW_LOCK2 ======================================================== */ +/* =============================================== OTP SW_LOCK2 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK2_NSEC */ + OTP_SW_LOCK2_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK2_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK2_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK2_NSEC_Enum; + +/* ================================================ OTP SW_LOCK2 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK2_SEC */ + OTP_SW_LOCK2_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK2_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK2_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK2_SEC_Enum; + +/* ======================================================= SW_LOCK3 ======================================================== */ +/* =============================================== OTP SW_LOCK3 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK3_NSEC */ + OTP_SW_LOCK3_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK3_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK3_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK3_NSEC_Enum; + +/* ================================================ OTP SW_LOCK3 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK3_SEC */ + OTP_SW_LOCK3_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK3_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK3_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK3_SEC_Enum; + +/* ======================================================= SW_LOCK4 ======================================================== */ +/* =============================================== OTP SW_LOCK4 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK4_NSEC */ + OTP_SW_LOCK4_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK4_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK4_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK4_NSEC_Enum; + +/* ================================================ OTP SW_LOCK4 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK4_SEC */ + OTP_SW_LOCK4_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK4_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK4_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK4_SEC_Enum; + +/* ======================================================= SW_LOCK5 ======================================================== */ +/* =============================================== OTP SW_LOCK5 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK5_NSEC */ + OTP_SW_LOCK5_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK5_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK5_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK5_NSEC_Enum; + +/* ================================================ OTP SW_LOCK5 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK5_SEC */ + OTP_SW_LOCK5_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK5_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK5_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK5_SEC_Enum; + +/* ======================================================= SW_LOCK6 ======================================================== */ +/* =============================================== OTP SW_LOCK6 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK6_NSEC */ + OTP_SW_LOCK6_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK6_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK6_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK6_NSEC_Enum; + +/* ================================================ OTP SW_LOCK6 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK6_SEC */ + OTP_SW_LOCK6_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK6_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK6_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK6_SEC_Enum; + +/* ======================================================= SW_LOCK7 ======================================================== */ +/* =============================================== OTP SW_LOCK7 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK7_NSEC */ + OTP_SW_LOCK7_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK7_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK7_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK7_NSEC_Enum; + +/* ================================================ OTP SW_LOCK7 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK7_SEC */ + OTP_SW_LOCK7_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK7_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK7_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK7_SEC_Enum; + +/* ======================================================= SW_LOCK8 ======================================================== */ +/* =============================================== OTP SW_LOCK8 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK8_NSEC */ + OTP_SW_LOCK8_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK8_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK8_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK8_NSEC_Enum; + +/* ================================================ OTP SW_LOCK8 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK8_SEC */ + OTP_SW_LOCK8_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK8_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK8_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK8_SEC_Enum; + +/* ======================================================= SW_LOCK9 ======================================================== */ +/* =============================================== OTP SW_LOCK9 NSEC [2..3] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK9_NSEC */ + OTP_SW_LOCK9_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK9_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK9_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK9_NSEC_Enum; + +/* ================================================ OTP SW_LOCK9 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK9_SEC */ + OTP_SW_LOCK9_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK9_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK9_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK9_SEC_Enum; + +/* ======================================================= SW_LOCK10 ======================================================= */ +/* =============================================== OTP SW_LOCK10 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK10_NSEC */ + OTP_SW_LOCK10_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK10_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK10_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK10_NSEC_Enum; + +/* =============================================== OTP SW_LOCK10 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK10_SEC */ + OTP_SW_LOCK10_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK10_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK10_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK10_SEC_Enum; + +/* ======================================================= SW_LOCK11 ======================================================= */ +/* =============================================== OTP SW_LOCK11 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK11_NSEC */ + OTP_SW_LOCK11_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK11_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK11_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK11_NSEC_Enum; + +/* =============================================== OTP SW_LOCK11 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK11_SEC */ + OTP_SW_LOCK11_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK11_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK11_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK11_SEC_Enum; + +/* ======================================================= SW_LOCK12 ======================================================= */ +/* =============================================== OTP SW_LOCK12 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK12_NSEC */ + OTP_SW_LOCK12_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK12_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK12_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK12_NSEC_Enum; + +/* =============================================== OTP SW_LOCK12 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK12_SEC */ + OTP_SW_LOCK12_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK12_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK12_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK12_SEC_Enum; + +/* ======================================================= SW_LOCK13 ======================================================= */ +/* =============================================== OTP SW_LOCK13 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK13_NSEC */ + OTP_SW_LOCK13_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK13_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK13_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK13_NSEC_Enum; + +/* =============================================== OTP SW_LOCK13 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK13_SEC */ + OTP_SW_LOCK13_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK13_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK13_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK13_SEC_Enum; + +/* ======================================================= SW_LOCK14 ======================================================= */ +/* =============================================== OTP SW_LOCK14 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK14_NSEC */ + OTP_SW_LOCK14_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK14_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK14_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK14_NSEC_Enum; + +/* =============================================== OTP SW_LOCK14 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK14_SEC */ + OTP_SW_LOCK14_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK14_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK14_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK14_SEC_Enum; + +/* ======================================================= SW_LOCK15 ======================================================= */ +/* =============================================== OTP SW_LOCK15 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK15_NSEC */ + OTP_SW_LOCK15_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK15_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK15_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK15_NSEC_Enum; + +/* =============================================== OTP SW_LOCK15 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK15_SEC */ + OTP_SW_LOCK15_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK15_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK15_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK15_SEC_Enum; + +/* ======================================================= SW_LOCK16 ======================================================= */ +/* =============================================== OTP SW_LOCK16 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK16_NSEC */ + OTP_SW_LOCK16_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK16_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK16_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK16_NSEC_Enum; + +/* =============================================== OTP SW_LOCK16 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK16_SEC */ + OTP_SW_LOCK16_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK16_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK16_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK16_SEC_Enum; + +/* ======================================================= SW_LOCK17 ======================================================= */ +/* =============================================== OTP SW_LOCK17 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK17_NSEC */ + OTP_SW_LOCK17_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK17_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK17_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK17_NSEC_Enum; + +/* =============================================== OTP SW_LOCK17 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK17_SEC */ + OTP_SW_LOCK17_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK17_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK17_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK17_SEC_Enum; + +/* ======================================================= SW_LOCK18 ======================================================= */ +/* =============================================== OTP SW_LOCK18 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK18_NSEC */ + OTP_SW_LOCK18_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK18_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK18_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK18_NSEC_Enum; + +/* =============================================== OTP SW_LOCK18 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK18_SEC */ + OTP_SW_LOCK18_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK18_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK18_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK18_SEC_Enum; + +/* ======================================================= SW_LOCK19 ======================================================= */ +/* =============================================== OTP SW_LOCK19 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK19_NSEC */ + OTP_SW_LOCK19_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK19_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK19_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK19_NSEC_Enum; + +/* =============================================== OTP SW_LOCK19 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK19_SEC */ + OTP_SW_LOCK19_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK19_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK19_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK19_SEC_Enum; + +/* ======================================================= SW_LOCK20 ======================================================= */ +/* =============================================== OTP SW_LOCK20 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK20_NSEC */ + OTP_SW_LOCK20_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK20_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK20_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK20_NSEC_Enum; + +/* =============================================== OTP SW_LOCK20 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK20_SEC */ + OTP_SW_LOCK20_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK20_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK20_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK20_SEC_Enum; + +/* ======================================================= SW_LOCK21 ======================================================= */ +/* =============================================== OTP SW_LOCK21 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK21_NSEC */ + OTP_SW_LOCK21_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK21_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK21_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK21_NSEC_Enum; + +/* =============================================== OTP SW_LOCK21 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK21_SEC */ + OTP_SW_LOCK21_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK21_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK21_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK21_SEC_Enum; + +/* ======================================================= SW_LOCK22 ======================================================= */ +/* =============================================== OTP SW_LOCK22 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK22_NSEC */ + OTP_SW_LOCK22_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK22_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK22_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK22_NSEC_Enum; + +/* =============================================== OTP SW_LOCK22 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK22_SEC */ + OTP_SW_LOCK22_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK22_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK22_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK22_SEC_Enum; + +/* ======================================================= SW_LOCK23 ======================================================= */ +/* =============================================== OTP SW_LOCK23 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK23_NSEC */ + OTP_SW_LOCK23_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK23_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK23_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK23_NSEC_Enum; + +/* =============================================== OTP SW_LOCK23 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK23_SEC */ + OTP_SW_LOCK23_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK23_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK23_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK23_SEC_Enum; + +/* ======================================================= SW_LOCK24 ======================================================= */ +/* =============================================== OTP SW_LOCK24 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK24_NSEC */ + OTP_SW_LOCK24_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK24_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK24_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK24_NSEC_Enum; + +/* =============================================== OTP SW_LOCK24 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK24_SEC */ + OTP_SW_LOCK24_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK24_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK24_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK24_SEC_Enum; + +/* ======================================================= SW_LOCK25 ======================================================= */ +/* =============================================== OTP SW_LOCK25 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK25_NSEC */ + OTP_SW_LOCK25_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK25_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK25_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK25_NSEC_Enum; + +/* =============================================== OTP SW_LOCK25 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK25_SEC */ + OTP_SW_LOCK25_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK25_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK25_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK25_SEC_Enum; + +/* ======================================================= SW_LOCK26 ======================================================= */ +/* =============================================== OTP SW_LOCK26 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK26_NSEC */ + OTP_SW_LOCK26_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK26_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK26_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK26_NSEC_Enum; + +/* =============================================== OTP SW_LOCK26 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK26_SEC */ + OTP_SW_LOCK26_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK26_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK26_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK26_SEC_Enum; + +/* ======================================================= SW_LOCK27 ======================================================= */ +/* =============================================== OTP SW_LOCK27 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK27_NSEC */ + OTP_SW_LOCK27_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK27_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK27_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK27_NSEC_Enum; + +/* =============================================== OTP SW_LOCK27 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK27_SEC */ + OTP_SW_LOCK27_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK27_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK27_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK27_SEC_Enum; + +/* ======================================================= SW_LOCK28 ======================================================= */ +/* =============================================== OTP SW_LOCK28 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK28_NSEC */ + OTP_SW_LOCK28_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK28_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK28_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK28_NSEC_Enum; + +/* =============================================== OTP SW_LOCK28 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK28_SEC */ + OTP_SW_LOCK28_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK28_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK28_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK28_SEC_Enum; + +/* ======================================================= SW_LOCK29 ======================================================= */ +/* =============================================== OTP SW_LOCK29 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK29_NSEC */ + OTP_SW_LOCK29_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK29_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK29_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK29_NSEC_Enum; + +/* =============================================== OTP SW_LOCK29 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK29_SEC */ + OTP_SW_LOCK29_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK29_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK29_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK29_SEC_Enum; + +/* ======================================================= SW_LOCK30 ======================================================= */ +/* =============================================== OTP SW_LOCK30 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK30_NSEC */ + OTP_SW_LOCK30_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK30_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK30_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK30_NSEC_Enum; + +/* =============================================== OTP SW_LOCK30 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK30_SEC */ + OTP_SW_LOCK30_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK30_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK30_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK30_SEC_Enum; + +/* ======================================================= SW_LOCK31 ======================================================= */ +/* =============================================== OTP SW_LOCK31 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK31_NSEC */ + OTP_SW_LOCK31_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK31_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK31_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK31_NSEC_Enum; + +/* =============================================== OTP SW_LOCK31 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK31_SEC */ + OTP_SW_LOCK31_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK31_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK31_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK31_SEC_Enum; + +/* ======================================================= SW_LOCK32 ======================================================= */ +/* =============================================== OTP SW_LOCK32 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK32_NSEC */ + OTP_SW_LOCK32_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK32_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK32_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK32_NSEC_Enum; + +/* =============================================== OTP SW_LOCK32 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK32_SEC */ + OTP_SW_LOCK32_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK32_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK32_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK32_SEC_Enum; + +/* ======================================================= SW_LOCK33 ======================================================= */ +/* =============================================== OTP SW_LOCK33 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK33_NSEC */ + OTP_SW_LOCK33_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK33_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK33_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK33_NSEC_Enum; + +/* =============================================== OTP SW_LOCK33 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK33_SEC */ + OTP_SW_LOCK33_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK33_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK33_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK33_SEC_Enum; + +/* ======================================================= SW_LOCK34 ======================================================= */ +/* =============================================== OTP SW_LOCK34 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK34_NSEC */ + OTP_SW_LOCK34_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK34_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK34_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK34_NSEC_Enum; + +/* =============================================== OTP SW_LOCK34 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK34_SEC */ + OTP_SW_LOCK34_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK34_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK34_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK34_SEC_Enum; + +/* ======================================================= SW_LOCK35 ======================================================= */ +/* =============================================== OTP SW_LOCK35 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK35_NSEC */ + OTP_SW_LOCK35_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK35_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK35_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK35_NSEC_Enum; + +/* =============================================== OTP SW_LOCK35 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK35_SEC */ + OTP_SW_LOCK35_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK35_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK35_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK35_SEC_Enum; + +/* ======================================================= SW_LOCK36 ======================================================= */ +/* =============================================== OTP SW_LOCK36 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK36_NSEC */ + OTP_SW_LOCK36_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK36_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK36_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK36_NSEC_Enum; + +/* =============================================== OTP SW_LOCK36 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK36_SEC */ + OTP_SW_LOCK36_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK36_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK36_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK36_SEC_Enum; + +/* ======================================================= SW_LOCK37 ======================================================= */ +/* =============================================== OTP SW_LOCK37 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK37_NSEC */ + OTP_SW_LOCK37_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK37_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK37_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK37_NSEC_Enum; + +/* =============================================== OTP SW_LOCK37 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK37_SEC */ + OTP_SW_LOCK37_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK37_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK37_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK37_SEC_Enum; + +/* ======================================================= SW_LOCK38 ======================================================= */ +/* =============================================== OTP SW_LOCK38 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK38_NSEC */ + OTP_SW_LOCK38_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK38_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK38_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK38_NSEC_Enum; + +/* =============================================== OTP SW_LOCK38 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK38_SEC */ + OTP_SW_LOCK38_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK38_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK38_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK38_SEC_Enum; + +/* ======================================================= SW_LOCK39 ======================================================= */ +/* =============================================== OTP SW_LOCK39 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK39_NSEC */ + OTP_SW_LOCK39_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK39_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK39_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK39_NSEC_Enum; + +/* =============================================== OTP SW_LOCK39 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK39_SEC */ + OTP_SW_LOCK39_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK39_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK39_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK39_SEC_Enum; + +/* ======================================================= SW_LOCK40 ======================================================= */ +/* =============================================== OTP SW_LOCK40 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK40_NSEC */ + OTP_SW_LOCK40_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK40_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK40_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK40_NSEC_Enum; + +/* =============================================== OTP SW_LOCK40 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK40_SEC */ + OTP_SW_LOCK40_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK40_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK40_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK40_SEC_Enum; + +/* ======================================================= SW_LOCK41 ======================================================= */ +/* =============================================== OTP SW_LOCK41 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK41_NSEC */ + OTP_SW_LOCK41_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK41_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK41_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK41_NSEC_Enum; + +/* =============================================== OTP SW_LOCK41 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK41_SEC */ + OTP_SW_LOCK41_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK41_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK41_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK41_SEC_Enum; + +/* ======================================================= SW_LOCK42 ======================================================= */ +/* =============================================== OTP SW_LOCK42 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK42_NSEC */ + OTP_SW_LOCK42_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK42_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK42_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK42_NSEC_Enum; + +/* =============================================== OTP SW_LOCK42 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK42_SEC */ + OTP_SW_LOCK42_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK42_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK42_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK42_SEC_Enum; + +/* ======================================================= SW_LOCK43 ======================================================= */ +/* =============================================== OTP SW_LOCK43 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK43_NSEC */ + OTP_SW_LOCK43_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK43_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK43_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK43_NSEC_Enum; + +/* =============================================== OTP SW_LOCK43 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK43_SEC */ + OTP_SW_LOCK43_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK43_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK43_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK43_SEC_Enum; + +/* ======================================================= SW_LOCK44 ======================================================= */ +/* =============================================== OTP SW_LOCK44 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK44_NSEC */ + OTP_SW_LOCK44_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK44_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK44_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK44_NSEC_Enum; + +/* =============================================== OTP SW_LOCK44 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK44_SEC */ + OTP_SW_LOCK44_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK44_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK44_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK44_SEC_Enum; + +/* ======================================================= SW_LOCK45 ======================================================= */ +/* =============================================== OTP SW_LOCK45 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK45_NSEC */ + OTP_SW_LOCK45_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK45_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK45_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK45_NSEC_Enum; + +/* =============================================== OTP SW_LOCK45 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK45_SEC */ + OTP_SW_LOCK45_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK45_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK45_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK45_SEC_Enum; + +/* ======================================================= SW_LOCK46 ======================================================= */ +/* =============================================== OTP SW_LOCK46 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK46_NSEC */ + OTP_SW_LOCK46_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK46_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK46_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK46_NSEC_Enum; + +/* =============================================== OTP SW_LOCK46 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK46_SEC */ + OTP_SW_LOCK46_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK46_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK46_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK46_SEC_Enum; + +/* ======================================================= SW_LOCK47 ======================================================= */ +/* =============================================== OTP SW_LOCK47 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK47_NSEC */ + OTP_SW_LOCK47_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK47_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK47_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK47_NSEC_Enum; + +/* =============================================== OTP SW_LOCK47 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK47_SEC */ + OTP_SW_LOCK47_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK47_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK47_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK47_SEC_Enum; + +/* ======================================================= SW_LOCK48 ======================================================= */ +/* =============================================== OTP SW_LOCK48 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK48_NSEC */ + OTP_SW_LOCK48_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK48_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK48_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK48_NSEC_Enum; + +/* =============================================== OTP SW_LOCK48 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK48_SEC */ + OTP_SW_LOCK48_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK48_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK48_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK48_SEC_Enum; + +/* ======================================================= SW_LOCK49 ======================================================= */ +/* =============================================== OTP SW_LOCK49 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK49_NSEC */ + OTP_SW_LOCK49_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK49_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK49_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK49_NSEC_Enum; + +/* =============================================== OTP SW_LOCK49 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK49_SEC */ + OTP_SW_LOCK49_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK49_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK49_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK49_SEC_Enum; + +/* ======================================================= SW_LOCK50 ======================================================= */ +/* =============================================== OTP SW_LOCK50 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK50_NSEC */ + OTP_SW_LOCK50_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK50_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK50_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK50_NSEC_Enum; + +/* =============================================== OTP SW_LOCK50 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK50_SEC */ + OTP_SW_LOCK50_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK50_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK50_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK50_SEC_Enum; + +/* ======================================================= SW_LOCK51 ======================================================= */ +/* =============================================== OTP SW_LOCK51 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK51_NSEC */ + OTP_SW_LOCK51_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK51_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK51_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK51_NSEC_Enum; + +/* =============================================== OTP SW_LOCK51 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK51_SEC */ + OTP_SW_LOCK51_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK51_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK51_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK51_SEC_Enum; + +/* ======================================================= SW_LOCK52 ======================================================= */ +/* =============================================== OTP SW_LOCK52 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK52_NSEC */ + OTP_SW_LOCK52_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK52_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK52_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK52_NSEC_Enum; + +/* =============================================== OTP SW_LOCK52 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK52_SEC */ + OTP_SW_LOCK52_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK52_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK52_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK52_SEC_Enum; + +/* ======================================================= SW_LOCK53 ======================================================= */ +/* =============================================== OTP SW_LOCK53 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK53_NSEC */ + OTP_SW_LOCK53_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK53_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK53_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK53_NSEC_Enum; + +/* =============================================== OTP SW_LOCK53 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK53_SEC */ + OTP_SW_LOCK53_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK53_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK53_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK53_SEC_Enum; + +/* ======================================================= SW_LOCK54 ======================================================= */ +/* =============================================== OTP SW_LOCK54 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK54_NSEC */ + OTP_SW_LOCK54_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK54_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK54_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK54_NSEC_Enum; + +/* =============================================== OTP SW_LOCK54 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK54_SEC */ + OTP_SW_LOCK54_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK54_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK54_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK54_SEC_Enum; + +/* ======================================================= SW_LOCK55 ======================================================= */ +/* =============================================== OTP SW_LOCK55 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK55_NSEC */ + OTP_SW_LOCK55_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK55_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK55_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK55_NSEC_Enum; + +/* =============================================== OTP SW_LOCK55 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK55_SEC */ + OTP_SW_LOCK55_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK55_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK55_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK55_SEC_Enum; + +/* ======================================================= SW_LOCK56 ======================================================= */ +/* =============================================== OTP SW_LOCK56 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK56_NSEC */ + OTP_SW_LOCK56_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK56_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK56_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK56_NSEC_Enum; + +/* =============================================== OTP SW_LOCK56 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK56_SEC */ + OTP_SW_LOCK56_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK56_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK56_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK56_SEC_Enum; + +/* ======================================================= SW_LOCK57 ======================================================= */ +/* =============================================== OTP SW_LOCK57 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK57_NSEC */ + OTP_SW_LOCK57_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK57_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK57_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK57_NSEC_Enum; + +/* =============================================== OTP SW_LOCK57 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK57_SEC */ + OTP_SW_LOCK57_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK57_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK57_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK57_SEC_Enum; + +/* ======================================================= SW_LOCK58 ======================================================= */ +/* =============================================== OTP SW_LOCK58 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK58_NSEC */ + OTP_SW_LOCK58_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK58_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK58_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK58_NSEC_Enum; + +/* =============================================== OTP SW_LOCK58 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK58_SEC */ + OTP_SW_LOCK58_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK58_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK58_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK58_SEC_Enum; + +/* ======================================================= SW_LOCK59 ======================================================= */ +/* =============================================== OTP SW_LOCK59 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK59_NSEC */ + OTP_SW_LOCK59_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK59_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK59_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK59_NSEC_Enum; + +/* =============================================== OTP SW_LOCK59 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK59_SEC */ + OTP_SW_LOCK59_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK59_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK59_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK59_SEC_Enum; + +/* ======================================================= SW_LOCK60 ======================================================= */ +/* =============================================== OTP SW_LOCK60 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK60_NSEC */ + OTP_SW_LOCK60_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK60_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK60_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK60_NSEC_Enum; + +/* =============================================== OTP SW_LOCK60 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK60_SEC */ + OTP_SW_LOCK60_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK60_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK60_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK60_SEC_Enum; + +/* ======================================================= SW_LOCK61 ======================================================= */ +/* =============================================== OTP SW_LOCK61 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK61_NSEC */ + OTP_SW_LOCK61_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK61_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK61_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK61_NSEC_Enum; + +/* =============================================== OTP SW_LOCK61 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK61_SEC */ + OTP_SW_LOCK61_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK61_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK61_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK61_SEC_Enum; + +/* ======================================================= SW_LOCK62 ======================================================= */ +/* =============================================== OTP SW_LOCK62 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK62_NSEC */ + OTP_SW_LOCK62_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK62_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK62_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK62_NSEC_Enum; + +/* =============================================== OTP SW_LOCK62 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK62_SEC */ + OTP_SW_LOCK62_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK62_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK62_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK62_SEC_Enum; + +/* ======================================================= SW_LOCK63 ======================================================= */ +/* =============================================== OTP SW_LOCK63 NSEC [2..3] =============================================== */ +typedef enum { /*!< OTP_SW_LOCK63_NSEC */ + OTP_SW_LOCK63_NSEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK63_NSEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK63_NSEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK63_NSEC_Enum; + +/* =============================================== OTP SW_LOCK63 SEC [0..1] ================================================ */ +typedef enum { /*!< OTP_SW_LOCK63_SEC */ + OTP_SW_LOCK63_SEC_read_write = 0, /*!< read_write : read_write */ + OTP_SW_LOCK63_SEC_read_only = 1, /*!< read_only : read_only */ + OTP_SW_LOCK63_SEC_inaccessible = 3, /*!< inaccessible : inaccessible */ +} OTP_SW_LOCK63_SEC_Enum; + +/* ====================================================== SBPI_INSTR ======================================================= */ +/* ===================================================== SBPI_WDATA_0 ====================================================== */ +/* ===================================================== SBPI_WDATA_1 ====================================================== */ +/* ===================================================== SBPI_WDATA_2 ====================================================== */ +/* ===================================================== SBPI_WDATA_3 ====================================================== */ +/* ===================================================== SBPI_RDATA_0 ====================================================== */ +/* ===================================================== SBPI_RDATA_1 ====================================================== */ +/* ===================================================== SBPI_RDATA_2 ====================================================== */ +/* ===================================================== SBPI_RDATA_3 ====================================================== */ +/* ====================================================== SBPI_STATUS ====================================================== */ +/* ========================================================== USR ========================================================== */ +/* ========================================================== DBG ========================================================== */ +/* ========================================================= BIST ========================================================== */ +/* ====================================================== CRT_KEY_W0 ======================================================= */ +/* ====================================================== CRT_KEY_W1 ======================================================= */ +/* ====================================================== CRT_KEY_W2 ======================================================= */ +/* ====================================================== CRT_KEY_W3 ======================================================= */ +/* ======================================================= CRITICAL ======================================================== */ +/* ======================================================= KEY_VALID ======================================================= */ +/* ======================================================== DEBUGEN ======================================================== */ +/* ===================================================== DEBUGEN_LOCK ====================================================== */ +/* ======================================================== ARCHSEL ======================================================== */ +/* =============================================== OTP ARCHSEL CORE1 [1..1] ================================================ */ +typedef enum { /*!< OTP_ARCHSEL_CORE1 */ + OTP_ARCHSEL_CORE1_arm = 0, /*!< arm : Switch core 1 to Arm (Cortex-M33) */ + OTP_ARCHSEL_CORE1_riscv = 1, /*!< riscv : Switch core 1 to RISC-V (Hazard3) */ +} OTP_ARCHSEL_CORE1_Enum; + +/* =============================================== OTP ARCHSEL CORE0 [0..0] ================================================ */ +typedef enum { /*!< OTP_ARCHSEL_CORE0 */ + OTP_ARCHSEL_CORE0_arm = 0, /*!< arm : Switch core 0 to Arm (Cortex-M33) */ + OTP_ARCHSEL_CORE0_riscv = 1, /*!< riscv : Switch core 0 to RISC-V (Hazard3) */ +} OTP_ARCHSEL_CORE0_Enum; + +/* ==================================================== ARCHSEL_STATUS ===================================================== */ +/* ============================================ OTP ARCHSEL_STATUS CORE1 [1..1] ============================================ */ +typedef enum { /*!< OTP_ARCHSEL_STATUS_CORE1 */ + OTP_ARCHSEL_STATUS_CORE1_arm = 0, /*!< arm : Core 1 is currently Arm (Cortex-M33) */ + OTP_ARCHSEL_STATUS_CORE1_riscv = 1, /*!< riscv : Core 1 is currently RISC-V (Hazard3) */ +} OTP_ARCHSEL_STATUS_CORE1_Enum; + +/* ============================================ OTP ARCHSEL_STATUS CORE0 [0..0] ============================================ */ +typedef enum { /*!< OTP_ARCHSEL_STATUS_CORE0 */ + OTP_ARCHSEL_STATUS_CORE0_arm = 0, /*!< arm : Core 0 is currently Arm (Cortex-M33) */ + OTP_ARCHSEL_STATUS_CORE0_riscv = 1, /*!< riscv : Core 0 is currently RISC-V (Hazard3) */ +} OTP_ARCHSEL_STATUS_CORE0_Enum; + +/* ======================================================== BOOTDIS ======================================================== */ +/* ========================================================= INTR ========================================================== */ +/* ========================================================= INTE ========================================================== */ +/* ========================================================= INTF ========================================================== */ +/* ========================================================= INTS ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIPID0 ======================================================== */ +/* ======================================================== CHIPID1 ======================================================== */ +/* ======================================================== CHIPID2 ======================================================== */ +/* ======================================================== CHIPID3 ======================================================== */ +/* ======================================================== RANDID0 ======================================================== */ +/* ======================================================== RANDID1 ======================================================== */ +/* ======================================================== RANDID2 ======================================================== */ +/* ======================================================== RANDID3 ======================================================== */ +/* ======================================================== RANDID4 ======================================================== */ +/* ======================================================== RANDID5 ======================================================== */ +/* ======================================================== RANDID6 ======================================================== */ +/* ======================================================== RANDID7 ======================================================== */ +/* ====================================================== ROSC_CALIB ======================================================= */ +/* ====================================================== LPOSC_CALIB ====================================================== */ +/* ======================================================= NUM_GPIOS ======================================================= */ +/* ======================================================= INFO_CRC0 ======================================================= */ +/* ======================================================= INFO_CRC1 ======================================================= */ +/* ===================================================== FLASH_DEVINFO ===================================================== */ +/* ======================================= OTP_DATA FLASH_DEVINFO CS1_SIZE [12..15] ======================================== */ +typedef enum { /*!< OTP_DATA_FLASH_DEVINFO_CS1_SIZE */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_NONE = 0, /*!< NONE : NONE */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_8K = 1, /*!< 8K : 8K */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_16K = 2, /*!< 16K : 16K */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_32K = 3, /*!< 32K : 32K */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_64k = 4, /*!< 64k : 64k */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_128K = 5, /*!< 128K : 128K */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_256K = 6, /*!< 256K : 256K */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_512K = 7, /*!< 512K : 512K */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_1M = 8, /*!< 1M : 1M */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_2M = 9, /*!< 2M : 2M */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_4M = 10, /*!< 4M : 4M */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_8M = 11, /*!< 8M : 8M */ + OTP_DATA_FLASH_DEVINFO_CS1_SIZE_16M = 12, /*!< 16M : 16M */ +} OTP_DATA_FLASH_DEVINFO_CS1_SIZE_Enum; + +/* ======================================== OTP_DATA FLASH_DEVINFO CS0_SIZE [8..11] ======================================== */ +typedef enum { /*!< OTP_DATA_FLASH_DEVINFO_CS0_SIZE */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_NONE = 0, /*!< NONE : NONE */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_8K = 1, /*!< 8K : 8K */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_16K = 2, /*!< 16K : 16K */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_32K = 3, /*!< 32K : 32K */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_64k = 4, /*!< 64k : 64k */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_128K = 5, /*!< 128K : 128K */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_256K = 6, /*!< 256K : 256K */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_512K = 7, /*!< 512K : 512K */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_1M = 8, /*!< 1M : 1M */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_2M = 9, /*!< 2M : 2M */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_4M = 10, /*!< 4M : 4M */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_8M = 11, /*!< 8M : 8M */ + OTP_DATA_FLASH_DEVINFO_CS0_SIZE_16M = 12, /*!< 16M : 16M */ +} OTP_DATA_FLASH_DEVINFO_CS0_SIZE_Enum; + +/* =============================================== FLASH_PARTITION_SLOT_SIZE =============================================== */ +/* ==================================================== BOOTSEL_LED_CFG ==================================================== */ +/* ==================================================== BOOTSEL_PLL_CFG ==================================================== */ +/* =================================================== BOOTSEL_XOSC_CFG ==================================================== */ +/* ======================================= OTP_DATA BOOTSEL_XOSC_CFG RANGE [14..15] ======================================== */ +typedef enum { /*!< OTP_DATA_BOOTSEL_XOSC_CFG_RANGE */ + OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_1_15MHZ = 0, /*!< 1_15MHZ : 1_15MHZ */ + OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_10_30MHZ = 1, /*!< 10_30MHZ : 10_30MHZ */ + OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_25_60MHZ = 2, /*!< 25_60MHZ : 25_60MHZ */ + OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_40_100MHZ = 3,/*!< 40_100MHZ : 40_100MHZ */ +} OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_Enum; + +/* ================================================= USB_WHITE_LABEL_ADDR ================================================== */ +/* ============================== OTP_DATA USB_WHITE_LABEL_ADDR USB_WHITE_LABEL_ADDR [0..15] =============================== */ +typedef enum { /*!< OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_VID_VALUE = 0,/*!< INDEX_USB_DEVICE_VID_VALUE : INDEX_USB_DEVICE_VID_VALUE */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_PID_VALUE = 1,/*!< INDEX_USB_DEVICE_PID_VALUE : INDEX_USB_DEVICE_PID_VALUE */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_BCD_DEVICE_VALUE = 2,/*!< INDEX_USB_DEVICE_BCD_DEVICE_VALUE : INDEX_USB_DEVICE_BCD_DEVICE_VALUE */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_LANG_ID_VALUE = 3,/*!< INDEX_USB_DEVICE_LANG_ID_VALUE : INDEX_USB_DEVICE_LANG_ID_VALUE */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_MANUFACTURER_STRDEF = 4,/*!< INDEX_USB_DEVICE_MANUFACTURER_STRDEF : INDEX_USB_DEVICE_MANUFACTURER_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_PRODUCT_STRDEF = 5,/*!< INDEX_USB_DEVICE_PRODUCT_STRDEF : INDEX_USB_DEVICE_PRODUCT_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF = 6,/*!< INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF : INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES = 7,/*!< INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES : INDEX_USB_CONFIG_ATTRIBUTES_MAX + POWER_VALUES */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_VOLUME_LABEL_STRDEF = 8,/*!< INDEX_VOLUME_LABEL_STRDEF : INDEX_VOLUME_LABEL_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_SCSI_INQUIRY_VENDOR_STRDEF = 9,/*!< INDEX_SCSI_INQUIRY_VENDOR_STRDEF : INDEX_SCSI_INQUIRY_VENDOR_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_SCSI_INQUIRY_PRODUCT_STRDEF = 10,/*!< INDEX_SCSI_INQUIRY_PRODUCT_STRDEF : INDEX_SCSI_INQUIRY_PRODUCT_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_SCSI_INQUIRY_VERSION_STRDEF = 11,/*!< INDEX_SCSI_INQUIRY_VERSION_STRDEF : INDEX_SCSI_INQUIRY_VERSION_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_INDEX_HTM_REDIRECT_URL_STRDEF = 12,/*!< INDEX_INDEX_HTM_REDIRECT_URL_STRDEF : INDEX_INDEX_HTM_REDIRECT_URL_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF = 13,/*!< INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF : INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_INFO_UF2_TXT_MODEL_STRDEF = 14,/*!< INDEX_INFO_UF2_TXT_MODEL_STRDEF : INDEX_INFO_UF2_TXT_MODEL_STRDEF */ + OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF = 15,/*!< INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF : INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF */ +} OTP_DATA_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_Enum; + +/* ====================================================== OTPBOOT_SRC ====================================================== */ +/* ====================================================== OTPBOOT_LEN ====================================================== */ +/* ===================================================== OTPBOOT_DST0 ====================================================== */ +/* ===================================================== OTPBOOT_DST1 ====================================================== */ +/* ====================================================== BOOTKEY0_0 ======================================================= */ +/* ====================================================== BOOTKEY0_1 ======================================================= */ +/* ====================================================== BOOTKEY0_2 ======================================================= */ +/* ====================================================== BOOTKEY0_3 ======================================================= */ +/* ====================================================== BOOTKEY0_4 ======================================================= */ +/* ====================================================== BOOTKEY0_5 ======================================================= */ +/* ====================================================== BOOTKEY0_6 ======================================================= */ +/* ====================================================== BOOTKEY0_7 ======================================================= */ +/* ====================================================== BOOTKEY0_8 ======================================================= */ +/* ====================================================== BOOTKEY0_9 ======================================================= */ +/* ====================================================== BOOTKEY0_10 ====================================================== */ +/* ====================================================== BOOTKEY0_11 ====================================================== */ +/* ====================================================== BOOTKEY0_12 ====================================================== */ +/* ====================================================== BOOTKEY0_13 ====================================================== */ +/* ====================================================== BOOTKEY0_14 ====================================================== */ +/* ====================================================== BOOTKEY0_15 ====================================================== */ +/* ====================================================== BOOTKEY1_0 ======================================================= */ +/* ====================================================== BOOTKEY1_1 ======================================================= */ +/* ====================================================== BOOTKEY1_2 ======================================================= */ +/* ====================================================== BOOTKEY1_3 ======================================================= */ +/* ====================================================== BOOTKEY1_4 ======================================================= */ +/* ====================================================== BOOTKEY1_5 ======================================================= */ +/* ====================================================== BOOTKEY1_6 ======================================================= */ +/* ====================================================== BOOTKEY1_7 ======================================================= */ +/* ====================================================== BOOTKEY1_8 ======================================================= */ +/* ====================================================== BOOTKEY1_9 ======================================================= */ +/* ====================================================== BOOTKEY1_10 ====================================================== */ +/* ====================================================== BOOTKEY1_11 ====================================================== */ +/* ====================================================== BOOTKEY1_12 ====================================================== */ +/* ====================================================== BOOTKEY1_13 ====================================================== */ +/* ====================================================== BOOTKEY1_14 ====================================================== */ +/* ====================================================== BOOTKEY1_15 ====================================================== */ +/* ====================================================== BOOTKEY2_0 ======================================================= */ +/* ====================================================== BOOTKEY2_1 ======================================================= */ +/* ====================================================== BOOTKEY2_2 ======================================================= */ +/* ====================================================== BOOTKEY2_3 ======================================================= */ +/* ====================================================== BOOTKEY2_4 ======================================================= */ +/* ====================================================== BOOTKEY2_5 ======================================================= */ +/* ====================================================== BOOTKEY2_6 ======================================================= */ +/* ====================================================== BOOTKEY2_7 ======================================================= */ +/* ====================================================== BOOTKEY2_8 ======================================================= */ +/* ====================================================== BOOTKEY2_9 ======================================================= */ +/* ====================================================== BOOTKEY2_10 ====================================================== */ +/* ====================================================== BOOTKEY2_11 ====================================================== */ +/* ====================================================== BOOTKEY2_12 ====================================================== */ +/* ====================================================== BOOTKEY2_13 ====================================================== */ +/* ====================================================== BOOTKEY2_14 ====================================================== */ +/* ====================================================== BOOTKEY2_15 ====================================================== */ +/* ====================================================== BOOTKEY3_0 ======================================================= */ +/* ====================================================== BOOTKEY3_1 ======================================================= */ +/* ====================================================== BOOTKEY3_2 ======================================================= */ +/* ====================================================== BOOTKEY3_3 ======================================================= */ +/* ====================================================== BOOTKEY3_4 ======================================================= */ +/* ====================================================== BOOTKEY3_5 ======================================================= */ +/* ====================================================== BOOTKEY3_6 ======================================================= */ +/* ====================================================== BOOTKEY3_7 ======================================================= */ +/* ====================================================== BOOTKEY3_8 ======================================================= */ +/* ====================================================== BOOTKEY3_9 ======================================================= */ +/* ====================================================== BOOTKEY3_10 ====================================================== */ +/* ====================================================== BOOTKEY3_11 ====================================================== */ +/* ====================================================== BOOTKEY3_12 ====================================================== */ +/* ====================================================== BOOTKEY3_13 ====================================================== */ +/* ====================================================== BOOTKEY3_14 ====================================================== */ +/* ====================================================== BOOTKEY3_15 ====================================================== */ +/* ======================================================== KEY1_0 ========================================================= */ +/* ======================================================== KEY1_1 ========================================================= */ +/* ======================================================== KEY1_2 ========================================================= */ +/* ======================================================== KEY1_3 ========================================================= */ +/* ======================================================== KEY1_4 ========================================================= */ +/* ======================================================== KEY1_5 ========================================================= */ +/* ======================================================== KEY1_6 ========================================================= */ +/* ======================================================== KEY1_7 ========================================================= */ +/* ======================================================== KEY2_0 ========================================================= */ +/* ======================================================== KEY2_1 ========================================================= */ +/* ======================================================== KEY2_2 ========================================================= */ +/* ======================================================== KEY2_3 ========================================================= */ +/* ======================================================== KEY2_4 ========================================================= */ +/* ======================================================== KEY2_5 ========================================================= */ +/* ======================================================== KEY2_6 ========================================================= */ +/* ======================================================== KEY2_7 ========================================================= */ +/* ======================================================== KEY3_0 ========================================================= */ +/* ======================================================== KEY3_1 ========================================================= */ +/* ======================================================== KEY3_2 ========================================================= */ +/* ======================================================== KEY3_3 ========================================================= */ +/* ======================================================== KEY3_4 ========================================================= */ +/* ======================================================== KEY3_5 ========================================================= */ +/* ======================================================== KEY3_6 ========================================================= */ +/* ======================================================== KEY3_7 ========================================================= */ +/* ======================================================== KEY4_0 ========================================================= */ +/* ======================================================== KEY4_1 ========================================================= */ +/* ======================================================== KEY4_2 ========================================================= */ +/* ======================================================== KEY4_3 ========================================================= */ +/* ======================================================== KEY4_4 ========================================================= */ +/* ======================================================== KEY4_5 ========================================================= */ +/* ======================================================== KEY4_6 ========================================================= */ +/* ======================================================== KEY4_7 ========================================================= */ +/* ======================================================== KEY5_0 ========================================================= */ +/* ======================================================== KEY5_1 ========================================================= */ +/* ======================================================== KEY5_2 ========================================================= */ +/* ======================================================== KEY5_3 ========================================================= */ +/* ======================================================== KEY5_4 ========================================================= */ +/* ======================================================== KEY5_5 ========================================================= */ +/* ======================================================== KEY5_6 ========================================================= */ +/* ======================================================== KEY5_7 ========================================================= */ +/* ======================================================== KEY6_0 ========================================================= */ +/* ======================================================== KEY6_1 ========================================================= */ +/* ======================================================== KEY6_2 ========================================================= */ +/* ======================================================== KEY6_3 ========================================================= */ +/* ======================================================== KEY6_4 ========================================================= */ +/* ======================================================== KEY6_5 ========================================================= */ +/* ======================================================== KEY6_6 ========================================================= */ +/* ======================================================== KEY6_7 ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA_RAW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIPID0 ======================================================== */ +/* ======================================================== CHIPID1 ======================================================== */ +/* ======================================================== CHIPID2 ======================================================== */ +/* ======================================================== CHIPID3 ======================================================== */ +/* ======================================================== RANDID0 ======================================================== */ +/* ======================================================== RANDID1 ======================================================== */ +/* ======================================================== RANDID2 ======================================================== */ +/* ======================================================== RANDID3 ======================================================== */ +/* ======================================================== RANDID4 ======================================================== */ +/* ======================================================== RANDID5 ======================================================== */ +/* ======================================================== RANDID6 ======================================================== */ +/* ======================================================== RANDID7 ======================================================== */ +/* ====================================================== ROSC_CALIB ======================================================= */ +/* ====================================================== LPOSC_CALIB ====================================================== */ +/* ======================================================= NUM_GPIOS ======================================================= */ +/* ======================================================= INFO_CRC0 ======================================================= */ +/* ======================================================= INFO_CRC1 ======================================================= */ +/* ========================================================= CRIT0 ========================================================= */ +/* ======================================================= CRIT0_R1 ======================================================== */ +/* ======================================================= CRIT0_R2 ======================================================== */ +/* ======================================================= CRIT0_R3 ======================================================== */ +/* ======================================================= CRIT0_R4 ======================================================== */ +/* ======================================================= CRIT0_R5 ======================================================== */ +/* ======================================================= CRIT0_R6 ======================================================== */ +/* ======================================================= CRIT0_R7 ======================================================== */ +/* ========================================================= CRIT1 ========================================================= */ +/* ======================================================= CRIT1_R1 ======================================================== */ +/* ======================================================= CRIT1_R2 ======================================================== */ +/* ======================================================= CRIT1_R3 ======================================================== */ +/* ======================================================= CRIT1_R4 ======================================================== */ +/* ======================================================= CRIT1_R5 ======================================================== */ +/* ======================================================= CRIT1_R6 ======================================================== */ +/* ======================================================= CRIT1_R7 ======================================================== */ +/* ====================================================== BOOT_FLAGS0 ====================================================== */ +/* ==================================================== BOOT_FLAGS0_R1 ===================================================== */ +/* ==================================================== BOOT_FLAGS0_R2 ===================================================== */ +/* ====================================================== BOOT_FLAGS1 ====================================================== */ +/* ==================================================== BOOT_FLAGS1_R1 ===================================================== */ +/* ==================================================== BOOT_FLAGS1_R2 ===================================================== */ +/* ================================================= DEFAULT_BOOT_VERSION0 ================================================= */ +/* =============================================== DEFAULT_BOOT_VERSION0_R1 ================================================ */ +/* =============================================== DEFAULT_BOOT_VERSION0_R2 ================================================ */ +/* ================================================= DEFAULT_BOOT_VERSION1 ================================================= */ +/* =============================================== DEFAULT_BOOT_VERSION1_R1 ================================================ */ +/* =============================================== DEFAULT_BOOT_VERSION1_R2 ================================================ */ +/* ===================================================== FLASH_DEVINFO ===================================================== */ +/* ===================================== OTP_DATA_RAW FLASH_DEVINFO CS1_SIZE [12..15] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_NONE = 0, /*!< NONE : NONE */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_8K = 1, /*!< 8K : 8K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_16K = 2, /*!< 16K : 16K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_32K = 3, /*!< 32K : 32K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_64k = 4, /*!< 64k : 64k */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_128K = 5, /*!< 128K : 128K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_256K = 6, /*!< 256K : 256K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_512K = 7, /*!< 512K : 512K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_1M = 8, /*!< 1M : 1M */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_2M = 9, /*!< 2M : 2M */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_4M = 10, /*!< 4M : 4M */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_8M = 11, /*!< 8M : 8M */ + OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_16M = 12, /*!< 16M : 16M */ +} OTP_DATA_RAW_FLASH_DEVINFO_CS1_SIZE_Enum; + +/* ====================================== OTP_DATA_RAW FLASH_DEVINFO CS0_SIZE [8..11] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_NONE = 0, /*!< NONE : NONE */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_8K = 1, /*!< 8K : 8K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_16K = 2, /*!< 16K : 16K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_32K = 3, /*!< 32K : 32K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_64k = 4, /*!< 64k : 64k */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_128K = 5, /*!< 128K : 128K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_256K = 6, /*!< 256K : 256K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_512K = 7, /*!< 512K : 512K */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_1M = 8, /*!< 1M : 1M */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_2M = 9, /*!< 2M : 2M */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_4M = 10, /*!< 4M : 4M */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_8M = 11, /*!< 8M : 8M */ + OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_16M = 12, /*!< 16M : 16M */ +} OTP_DATA_RAW_FLASH_DEVINFO_CS0_SIZE_Enum; + +/* =============================================== FLASH_PARTITION_SLOT_SIZE =============================================== */ +/* ==================================================== BOOTSEL_LED_CFG ==================================================== */ +/* ==================================================== BOOTSEL_PLL_CFG ==================================================== */ +/* =================================================== BOOTSEL_XOSC_CFG ==================================================== */ +/* ===================================== OTP_DATA_RAW BOOTSEL_XOSC_CFG RANGE [14..15] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_BOOTSEL_XOSC_CFG_RANGE */ + OTP_DATA_RAW_BOOTSEL_XOSC_CFG_RANGE_1_15MHZ = 0,/*!< 1_15MHZ : 1_15MHZ */ + OTP_DATA_RAW_BOOTSEL_XOSC_CFG_RANGE_10_30MHZ = 1,/*!< 10_30MHZ : 10_30MHZ */ + OTP_DATA_RAW_BOOTSEL_XOSC_CFG_RANGE_25_60MHZ = 2,/*!< 25_60MHZ : 25_60MHZ */ + OTP_DATA_RAW_BOOTSEL_XOSC_CFG_RANGE_40_100MHZ = 3,/*!< 40_100MHZ : 40_100MHZ */ +} OTP_DATA_RAW_BOOTSEL_XOSC_CFG_RANGE_Enum; + +/* ==================================================== USB_BOOT_FLAGS ===================================================== */ +/* =================================================== USB_BOOT_FLAGS_R1 =================================================== */ +/* =================================================== USB_BOOT_FLAGS_R2 =================================================== */ +/* ================================================= USB_WHITE_LABEL_ADDR ================================================== */ +/* ============================ OTP_DATA_RAW USB_WHITE_LABEL_ADDR USB_WHITE_LABEL_ADDR [0..15] ============================= */ +typedef enum { /*!< OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_VID_VALUE = 0,/*!< INDEX_USB_DEVICE_VID_VALUE : INDEX_USB_DEVICE_VID_VALUE */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_PID_VALUE = 1,/*!< INDEX_USB_DEVICE_PID_VALUE : INDEX_USB_DEVICE_PID_VALUE */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_BCD_DEVICE_VALUE = 2,/*!< INDEX_USB_DEVICE_BCD_DEVICE_VALUE : INDEX_USB_DEVICE_BCD_DEVICE_VALUE */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_LANG_ID_VALUE = 3,/*!< INDEX_USB_DEVICE_LANG_ID_VALUE : INDEX_USB_DEVICE_LANG_ID_VALUE */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_MANUFACTURER_STRDEF = 4,/*!< INDEX_USB_DEVICE_MANUFACTURER_STRDEF : INDEX_USB_DEVICE_MANUFACTURER_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_PRODUCT_STRDEF = 5,/*!< INDEX_USB_DEVICE_PRODUCT_STRDEF : INDEX_USB_DEVICE_PRODUCT_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF = 6,/*!< INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF : INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES = 7,/*!< INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES : INDEX_USB_CONFIG_ATTRIBUTES_MAX + POWER_VALUES */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_VOLUME_LABEL_STRDEF = 8,/*!< INDEX_VOLUME_LABEL_STRDEF : INDEX_VOLUME_LABEL_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_SCSI_INQUIRY_VENDOR_STRDEF = 9,/*!< INDEX_SCSI_INQUIRY_VENDOR_STRDEF : INDEX_SCSI_INQUIRY_VENDOR_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_SCSI_INQUIRY_PRODUCT_STRDEF = 10,/*!< INDEX_SCSI_INQUIRY_PRODUCT_STRDEF : INDEX_SCSI_INQUIRY_PRODUCT_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_SCSI_INQUIRY_VERSION_STRDEF = 11,/*!< INDEX_SCSI_INQUIRY_VERSION_STRDEF : INDEX_SCSI_INQUIRY_VERSION_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_INDEX_HTM_REDIRECT_URL_STRDEF = 12,/*!< INDEX_INDEX_HTM_REDIRECT_URL_STRDEF : INDEX_INDEX_HTM_REDIRECT_URL_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF = 13,/*!< INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF : INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_INFO_UF2_TXT_MODEL_STRDEF = 14,/*!< INDEX_INFO_UF2_TXT_MODEL_STRDEF : INDEX_INFO_UF2_TXT_MODEL_STRDEF */ + OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF = 15,/*!< INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF : INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF */ +} OTP_DATA_RAW_USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_Enum; + +/* ====================================================== OTPBOOT_SRC ====================================================== */ +/* ====================================================== OTPBOOT_LEN ====================================================== */ +/* ===================================================== OTPBOOT_DST0 ====================================================== */ +/* ===================================================== OTPBOOT_DST1 ====================================================== */ +/* ====================================================== BOOTKEY0_0 ======================================================= */ +/* ====================================================== BOOTKEY0_1 ======================================================= */ +/* ====================================================== BOOTKEY0_2 ======================================================= */ +/* ====================================================== BOOTKEY0_3 ======================================================= */ +/* ====================================================== BOOTKEY0_4 ======================================================= */ +/* ====================================================== BOOTKEY0_5 ======================================================= */ +/* ====================================================== BOOTKEY0_6 ======================================================= */ +/* ====================================================== BOOTKEY0_7 ======================================================= */ +/* ====================================================== BOOTKEY0_8 ======================================================= */ +/* ====================================================== BOOTKEY0_9 ======================================================= */ +/* ====================================================== BOOTKEY0_10 ====================================================== */ +/* ====================================================== BOOTKEY0_11 ====================================================== */ +/* ====================================================== BOOTKEY0_12 ====================================================== */ +/* ====================================================== BOOTKEY0_13 ====================================================== */ +/* ====================================================== BOOTKEY0_14 ====================================================== */ +/* ====================================================== BOOTKEY0_15 ====================================================== */ +/* ====================================================== BOOTKEY1_0 ======================================================= */ +/* ====================================================== BOOTKEY1_1 ======================================================= */ +/* ====================================================== BOOTKEY1_2 ======================================================= */ +/* ====================================================== BOOTKEY1_3 ======================================================= */ +/* ====================================================== BOOTKEY1_4 ======================================================= */ +/* ====================================================== BOOTKEY1_5 ======================================================= */ +/* ====================================================== BOOTKEY1_6 ======================================================= */ +/* ====================================================== BOOTKEY1_7 ======================================================= */ +/* ====================================================== BOOTKEY1_8 ======================================================= */ +/* ====================================================== BOOTKEY1_9 ======================================================= */ +/* ====================================================== BOOTKEY1_10 ====================================================== */ +/* ====================================================== BOOTKEY1_11 ====================================================== */ +/* ====================================================== BOOTKEY1_12 ====================================================== */ +/* ====================================================== BOOTKEY1_13 ====================================================== */ +/* ====================================================== BOOTKEY1_14 ====================================================== */ +/* ====================================================== BOOTKEY1_15 ====================================================== */ +/* ====================================================== BOOTKEY2_0 ======================================================= */ +/* ====================================================== BOOTKEY2_1 ======================================================= */ +/* ====================================================== BOOTKEY2_2 ======================================================= */ +/* ====================================================== BOOTKEY2_3 ======================================================= */ +/* ====================================================== BOOTKEY2_4 ======================================================= */ +/* ====================================================== BOOTKEY2_5 ======================================================= */ +/* ====================================================== BOOTKEY2_6 ======================================================= */ +/* ====================================================== BOOTKEY2_7 ======================================================= */ +/* ====================================================== BOOTKEY2_8 ======================================================= */ +/* ====================================================== BOOTKEY2_9 ======================================================= */ +/* ====================================================== BOOTKEY2_10 ====================================================== */ +/* ====================================================== BOOTKEY2_11 ====================================================== */ +/* ====================================================== BOOTKEY2_12 ====================================================== */ +/* ====================================================== BOOTKEY2_13 ====================================================== */ +/* ====================================================== BOOTKEY2_14 ====================================================== */ +/* ====================================================== BOOTKEY2_15 ====================================================== */ +/* ====================================================== BOOTKEY3_0 ======================================================= */ +/* ====================================================== BOOTKEY3_1 ======================================================= */ +/* ====================================================== BOOTKEY3_2 ======================================================= */ +/* ====================================================== BOOTKEY3_3 ======================================================= */ +/* ====================================================== BOOTKEY3_4 ======================================================= */ +/* ====================================================== BOOTKEY3_5 ======================================================= */ +/* ====================================================== BOOTKEY3_6 ======================================================= */ +/* ====================================================== BOOTKEY3_7 ======================================================= */ +/* ====================================================== BOOTKEY3_8 ======================================================= */ +/* ====================================================== BOOTKEY3_9 ======================================================= */ +/* ====================================================== BOOTKEY3_10 ====================================================== */ +/* ====================================================== BOOTKEY3_11 ====================================================== */ +/* ====================================================== BOOTKEY3_12 ====================================================== */ +/* ====================================================== BOOTKEY3_13 ====================================================== */ +/* ====================================================== BOOTKEY3_14 ====================================================== */ +/* ====================================================== BOOTKEY3_15 ====================================================== */ +/* ======================================================== KEY1_0 ========================================================= */ +/* ======================================================== KEY1_1 ========================================================= */ +/* ======================================================== KEY1_2 ========================================================= */ +/* ======================================================== KEY1_3 ========================================================= */ +/* ======================================================== KEY1_4 ========================================================= */ +/* ======================================================== KEY1_5 ========================================================= */ +/* ======================================================== KEY1_6 ========================================================= */ +/* ======================================================== KEY1_7 ========================================================= */ +/* ======================================================== KEY2_0 ========================================================= */ +/* ======================================================== KEY2_1 ========================================================= */ +/* ======================================================== KEY2_2 ========================================================= */ +/* ======================================================== KEY2_3 ========================================================= */ +/* ======================================================== KEY2_4 ========================================================= */ +/* ======================================================== KEY2_5 ========================================================= */ +/* ======================================================== KEY2_6 ========================================================= */ +/* ======================================================== KEY2_7 ========================================================= */ +/* ======================================================== KEY3_0 ========================================================= */ +/* ======================================================== KEY3_1 ========================================================= */ +/* ======================================================== KEY3_2 ========================================================= */ +/* ======================================================== KEY3_3 ========================================================= */ +/* ======================================================== KEY3_4 ========================================================= */ +/* ======================================================== KEY3_5 ========================================================= */ +/* ======================================================== KEY3_6 ========================================================= */ +/* ======================================================== KEY3_7 ========================================================= */ +/* ======================================================== KEY4_0 ========================================================= */ +/* ======================================================== KEY4_1 ========================================================= */ +/* ======================================================== KEY4_2 ========================================================= */ +/* ======================================================== KEY4_3 ========================================================= */ +/* ======================================================== KEY4_4 ========================================================= */ +/* ======================================================== KEY4_5 ========================================================= */ +/* ======================================================== KEY4_6 ========================================================= */ +/* ======================================================== KEY4_7 ========================================================= */ +/* ======================================================== KEY5_0 ========================================================= */ +/* ======================================================== KEY5_1 ========================================================= */ +/* ======================================================== KEY5_2 ========================================================= */ +/* ======================================================== KEY5_3 ========================================================= */ +/* ======================================================== KEY5_4 ========================================================= */ +/* ======================================================== KEY5_5 ========================================================= */ +/* ======================================================== KEY5_6 ========================================================= */ +/* ======================================================== KEY5_7 ========================================================= */ +/* ======================================================== KEY6_0 ========================================================= */ +/* ======================================================== KEY6_1 ========================================================= */ +/* ======================================================== KEY6_2 ========================================================= */ +/* ======================================================== KEY6_3 ========================================================= */ +/* ======================================================== KEY6_4 ========================================================= */ +/* ======================================================== KEY6_5 ========================================================= */ +/* ======================================================== KEY6_6 ========================================================= */ +/* ======================================================== KEY6_7 ========================================================= */ +/* ====================================================== KEY1_VALID ======================================================= */ +/* ====================================================== KEY2_VALID ======================================================= */ +/* ====================================================== KEY3_VALID ======================================================= */ +/* ====================================================== KEY4_VALID ======================================================= */ +/* ====================================================== KEY5_VALID ======================================================= */ +/* ====================================================== KEY6_VALID ======================================================= */ +/* ====================================================== PAGE0_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE0_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE0_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE0_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE0_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE0_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE0_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE0_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE0_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE0_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE0_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE0_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE0_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE0_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE0_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE0_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE0_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE0_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE0_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE0_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE0_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE0_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE0_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE0_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE0_LOCK1_LOCK_S_Enum; + +/* ====================================================== PAGE1_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE1_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE1_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE1_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE1_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE1_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE1_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE1_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE1_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE1_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE1_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE1_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE1_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE1_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE1_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE1_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE1_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE1_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE1_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE1_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE1_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE1_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE1_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE1_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE1_LOCK1_LOCK_S_Enum; + +/* ====================================================== PAGE2_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE2_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE2_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE2_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE2_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE2_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE2_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE2_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE2_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE2_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE2_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE2_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE2_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE2_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE2_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE2_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE2_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE2_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE2_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE2_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE2_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE2_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE2_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE2_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE2_LOCK1_LOCK_S_Enum; + +/* ====================================================== PAGE3_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE3_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE3_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE3_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE3_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE3_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE3_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE3_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE3_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE3_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE3_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE3_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE3_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE3_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE3_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE3_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE3_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE3_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE3_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE3_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE3_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE3_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE3_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE3_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE3_LOCK1_LOCK_S_Enum; + +/* ====================================================== PAGE4_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE4_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE4_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE4_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE4_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE4_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE4_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE4_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE4_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE4_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE4_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE4_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE4_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE4_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE4_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE4_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE4_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE4_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE4_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE4_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE4_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE4_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE4_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE4_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE4_LOCK1_LOCK_S_Enum; + +/* ====================================================== PAGE5_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE5_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE5_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE5_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE5_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE5_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE5_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE5_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE5_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE5_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE5_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE5_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE5_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE5_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE5_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE5_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE5_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE5_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE5_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE5_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE5_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE5_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE5_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE5_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE5_LOCK1_LOCK_S_Enum; + +/* ====================================================== PAGE6_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE6_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE6_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE6_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE6_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE6_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE6_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE6_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE6_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE6_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE6_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE6_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE6_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE6_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE6_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE6_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE6_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE6_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE6_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE6_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE6_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE6_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE6_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE6_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE6_LOCK1_LOCK_S_Enum; + +/* ====================================================== PAGE7_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE7_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE7_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE7_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE7_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE7_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE7_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE7_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE7_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE7_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE7_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE7_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE7_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE7_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE7_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE7_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE7_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE7_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE7_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE7_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE7_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE7_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE7_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE7_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE7_LOCK1_LOCK_S_Enum; + +/* ====================================================== PAGE8_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE8_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE8_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE8_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE8_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE8_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE8_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE8_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE8_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE8_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE8_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE8_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE8_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE8_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE8_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE8_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE8_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE8_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE8_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE8_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE8_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE8_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE8_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE8_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE8_LOCK1_LOCK_S_Enum; + +/* ====================================================== PAGE9_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE9_LOCK0 NO_KEY_STATE [6..6] ====================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE9_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE9_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE9_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE9_LOCK0_NO_KEY_STATE_Enum; + +/* ====================================================== PAGE9_LOCK1 ====================================================== */ +/* ======================================== OTP_DATA_RAW PAGE9_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE9_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE9_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE9_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE9_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE9_LOCK1_LOCK_BL_Enum; + +/* ======================================== OTP_DATA_RAW PAGE9_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE9_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE9_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE9_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE9_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE9_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE9_LOCK1 LOCK_S [0..1] ========================================= */ +typedef enum { /*!< OTP_DATA_RAW_PAGE9_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE9_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE9_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE9_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE9_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE10_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE10_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE10_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE10_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE10_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE10_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE10_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE10_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE10_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE10_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE10_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE10_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE10_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE10_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE10_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE10_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE10_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE10_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE10_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE10_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE10_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE10_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE10_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE10_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE10_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE11_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE11_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE11_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE11_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE11_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE11_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE11_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE11_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE11_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE11_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE11_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE11_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE11_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE11_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE11_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE11_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE11_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE11_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE11_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE11_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE11_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE11_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE11_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE11_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE11_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE12_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE12_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE12_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE12_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE12_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE12_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE12_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE12_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE12_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE12_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE12_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE12_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE12_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE12_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE12_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE12_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE12_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE12_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE12_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE12_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE12_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE12_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE12_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE12_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE12_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE13_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE13_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE13_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE13_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE13_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE13_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE13_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE13_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE13_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE13_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE13_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE13_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE13_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE13_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE13_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE13_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE13_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE13_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE13_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE13_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE13_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE13_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE13_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE13_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE13_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE14_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE14_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE14_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE14_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE14_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE14_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE14_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE14_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE14_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE14_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE14_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE14_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE14_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE14_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE14_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE14_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE14_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE14_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE14_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE14_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE14_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE14_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE14_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE14_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE14_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE15_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE15_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE15_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE15_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE15_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE15_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE15_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE15_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE15_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE15_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE15_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE15_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE15_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE15_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE15_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE15_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE15_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE15_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE15_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE15_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE15_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE15_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE15_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE15_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE15_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE16_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE16_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE16_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE16_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE16_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE16_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE16_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE16_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE16_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE16_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE16_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE16_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE16_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE16_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE16_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE16_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE16_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE16_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE16_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE16_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE16_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE16_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE16_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE16_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE16_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE17_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE17_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE17_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE17_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE17_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE17_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE17_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE17_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE17_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE17_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE17_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE17_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE17_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE17_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE17_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE17_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE17_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE17_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE17_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE17_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE17_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE17_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE17_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE17_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE17_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE18_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE18_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE18_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE18_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE18_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE18_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE18_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE18_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE18_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE18_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE18_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE18_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE18_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE18_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE18_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE18_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE18_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE18_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE18_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE18_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE18_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE18_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE18_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE18_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE18_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE19_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE19_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE19_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE19_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE19_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE19_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE19_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE19_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE19_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE19_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE19_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE19_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE19_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE19_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE19_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE19_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE19_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE19_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE19_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE19_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE19_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE19_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE19_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE19_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE19_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE20_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE20_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE20_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE20_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE20_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE20_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE20_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE20_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE20_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE20_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE20_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE20_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE20_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE20_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE20_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE20_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE20_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE20_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE20_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE20_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE20_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE20_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE20_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE20_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE20_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE21_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE21_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE21_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE21_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE21_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE21_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE21_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE21_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE21_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE21_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE21_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE21_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE21_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE21_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE21_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE21_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE21_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE21_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE21_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE21_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE21_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE21_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE21_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE21_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE21_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE22_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE22_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE22_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE22_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE22_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE22_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE22_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE22_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE22_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE22_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE22_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE22_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE22_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE22_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE22_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE22_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE22_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE22_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE22_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE22_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE22_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE22_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE22_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE22_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE22_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE23_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE23_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE23_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE23_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE23_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE23_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE23_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE23_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE23_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE23_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE23_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE23_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE23_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE23_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE23_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE23_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE23_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE23_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE23_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE23_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE23_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE23_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE23_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE23_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE23_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE24_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE24_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE24_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE24_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE24_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE24_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE24_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE24_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE24_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE24_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE24_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE24_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE24_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE24_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE24_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE24_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE24_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE24_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE24_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE24_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE24_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE24_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE24_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE24_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE24_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE25_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE25_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE25_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE25_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE25_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE25_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE25_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE25_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE25_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE25_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE25_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE25_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE25_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE25_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE25_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE25_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE25_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE25_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE25_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE25_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE25_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE25_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE25_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE25_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE25_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE26_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE26_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE26_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE26_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE26_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE26_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE26_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE26_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE26_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE26_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE26_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE26_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE26_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE26_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE26_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE26_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE26_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE26_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE26_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE26_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE26_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE26_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE26_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE26_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE26_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE27_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE27_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE27_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE27_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE27_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE27_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE27_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE27_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE27_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE27_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE27_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE27_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE27_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE27_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE27_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE27_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE27_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE27_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE27_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE27_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE27_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE27_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE27_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE27_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE27_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE28_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE28_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE28_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE28_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE28_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE28_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE28_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE28_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE28_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE28_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE28_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE28_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE28_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE28_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE28_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE28_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE28_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE28_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE28_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE28_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE28_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE28_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE28_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE28_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE28_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE29_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE29_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE29_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE29_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE29_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE29_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE29_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE29_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE29_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE29_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE29_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE29_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE29_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE29_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE29_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE29_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE29_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE29_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE29_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE29_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE29_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE29_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE29_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE29_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE29_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE30_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE30_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE30_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE30_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE30_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE30_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE30_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE30_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE30_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE30_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE30_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE30_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE30_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE30_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE30_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE30_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE30_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE30_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE30_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE30_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE30_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE30_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE30_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE30_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE30_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE31_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE31_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE31_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE31_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE31_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE31_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE31_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE31_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE31_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE31_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE31_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE31_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE31_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE31_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE31_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE31_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE31_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE31_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE31_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE31_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE31_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE31_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE31_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE31_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE31_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE32_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE32_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE32_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE32_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE32_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE32_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE32_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE32_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE32_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE32_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE32_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE32_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE32_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE32_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE32_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE32_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE32_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE32_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE32_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE32_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE32_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE32_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE32_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE32_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE32_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE33_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE33_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE33_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE33_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE33_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE33_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE33_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE33_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE33_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE33_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE33_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE33_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE33_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE33_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE33_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE33_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE33_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE33_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE33_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE33_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE33_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE33_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE33_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE33_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE33_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE34_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE34_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE34_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE34_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE34_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE34_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE34_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE34_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE34_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE34_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE34_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE34_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE34_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE34_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE34_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE34_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE34_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE34_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE34_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE34_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE34_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE34_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE34_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE34_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE34_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE35_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE35_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE35_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE35_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE35_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE35_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE35_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE35_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE35_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE35_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE35_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE35_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE35_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE35_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE35_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE35_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE35_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE35_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE35_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE35_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE35_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE35_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE35_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE35_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE35_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE36_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE36_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE36_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE36_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE36_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE36_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE36_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE36_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE36_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE36_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE36_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE36_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE36_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE36_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE36_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE36_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE36_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE36_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE36_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE36_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE36_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE36_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE36_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE36_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE36_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE37_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE37_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE37_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE37_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE37_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE37_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE37_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE37_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE37_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE37_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE37_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE37_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE37_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE37_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE37_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE37_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE37_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE37_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE37_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE37_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE37_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE37_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE37_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE37_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE37_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE38_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE38_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE38_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE38_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE38_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE38_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE38_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE38_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE38_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE38_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE38_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE38_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE38_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE38_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE38_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE38_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE38_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE38_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE38_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE38_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE38_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE38_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE38_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE38_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE38_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE39_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE39_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE39_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE39_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE39_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE39_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE39_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE39_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE39_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE39_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE39_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE39_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE39_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE39_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE39_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE39_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE39_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE39_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE39_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE39_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE39_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE39_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE39_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE39_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE39_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE40_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE40_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE40_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE40_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE40_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE40_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE40_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE40_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE40_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE40_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE40_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE40_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE40_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE40_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE40_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE40_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE40_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE40_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE40_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE40_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE40_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE40_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE40_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE40_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE40_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE41_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE41_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE41_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE41_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE41_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE41_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE41_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE41_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE41_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE41_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE41_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE41_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE41_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE41_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE41_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE41_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE41_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE41_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE41_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE41_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE41_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE41_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE41_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE41_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE41_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE42_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE42_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE42_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE42_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE42_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE42_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE42_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE42_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE42_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE42_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE42_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE42_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE42_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE42_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE42_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE42_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE42_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE42_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE42_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE42_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE42_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE42_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE42_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE42_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE42_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE43_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE43_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE43_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE43_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE43_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE43_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE43_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE43_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE43_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE43_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE43_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE43_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE43_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE43_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE43_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE43_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE43_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE43_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE43_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE43_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE43_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE43_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE43_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE43_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE43_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE44_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE44_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE44_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE44_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE44_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE44_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE44_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE44_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE44_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE44_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE44_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE44_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE44_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE44_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE44_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE44_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE44_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE44_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE44_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE44_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE44_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE44_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE44_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE44_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE44_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE45_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE45_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE45_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE45_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE45_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE45_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE45_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE45_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE45_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE45_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE45_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE45_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE45_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE45_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE45_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE45_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE45_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE45_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE45_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE45_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE45_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE45_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE45_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE45_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE45_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE46_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE46_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE46_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE46_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE46_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE46_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE46_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE46_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE46_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE46_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE46_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE46_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE46_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE46_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE46_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE46_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE46_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE46_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE46_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE46_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE46_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE46_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE46_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE46_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE46_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE47_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE47_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE47_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE47_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE47_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE47_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE47_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE47_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE47_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE47_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE47_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE47_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE47_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE47_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE47_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE47_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE47_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE47_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE47_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE47_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE47_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE47_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE47_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE47_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE47_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE48_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE48_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE48_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE48_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE48_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE48_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE48_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE48_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE48_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE48_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE48_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE48_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE48_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE48_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE48_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE48_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE48_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE48_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE48_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE48_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE48_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE48_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE48_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE48_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE48_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE49_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE49_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE49_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE49_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE49_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE49_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE49_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE49_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE49_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE49_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE49_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE49_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE49_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE49_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE49_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE49_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE49_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE49_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE49_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE49_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE49_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE49_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE49_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE49_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE49_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE50_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE50_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE50_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE50_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE50_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE50_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE50_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE50_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE50_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE50_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE50_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE50_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE50_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE50_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE50_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE50_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE50_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE50_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE50_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE50_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE50_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE50_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE50_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE50_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE50_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE51_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE51_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE51_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE51_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE51_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE51_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE51_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE51_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE51_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE51_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE51_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE51_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE51_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE51_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE51_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE51_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE51_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE51_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE51_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE51_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE51_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE51_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE51_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE51_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE51_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE52_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE52_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE52_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE52_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE52_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE52_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE52_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE52_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE52_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE52_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE52_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE52_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE52_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE52_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE52_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE52_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE52_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE52_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE52_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE52_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE52_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE52_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE52_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE52_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE52_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE53_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE53_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE53_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE53_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE53_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE53_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE53_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE53_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE53_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE53_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE53_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE53_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE53_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE53_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE53_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE53_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE53_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE53_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE53_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE53_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE53_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE53_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE53_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE53_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE53_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE54_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE54_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE54_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE54_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE54_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE54_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE54_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE54_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE54_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE54_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE54_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE54_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE54_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE54_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE54_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE54_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE54_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE54_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE54_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE54_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE54_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE54_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE54_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE54_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE54_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE55_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE55_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE55_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE55_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE55_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE55_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE55_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE55_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE55_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE55_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE55_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE55_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE55_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE55_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE55_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE55_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE55_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE55_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE55_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE55_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE55_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE55_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE55_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE55_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE55_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE56_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE56_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE56_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE56_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE56_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE56_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE56_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE56_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE56_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE56_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE56_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE56_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE56_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE56_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE56_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE56_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE56_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE56_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE56_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE56_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE56_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE56_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE56_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE56_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE56_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE57_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE57_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE57_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE57_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE57_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE57_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE57_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE57_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE57_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE57_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE57_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE57_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE57_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE57_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE57_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE57_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE57_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE57_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE57_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE57_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE57_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE57_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE57_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE57_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE57_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE58_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE58_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE58_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE58_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE58_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE58_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE58_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE58_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE58_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE58_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE58_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE58_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE58_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE58_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE58_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE58_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE58_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE58_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE58_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE58_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE58_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE58_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE58_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE58_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE58_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE59_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE59_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE59_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE59_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE59_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE59_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE59_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE59_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE59_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE59_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE59_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE59_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE59_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE59_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE59_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE59_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE59_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE59_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE59_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE59_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE59_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE59_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE59_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE59_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE59_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE60_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE60_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE60_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE60_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE60_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE60_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE60_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE60_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE60_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE60_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE60_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE60_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE60_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE60_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE60_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE60_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE60_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE60_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE60_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE60_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE60_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE60_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE60_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE60_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE60_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE61_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE61_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE61_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE61_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE61_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE61_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE61_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE61_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE61_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE61_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE61_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE61_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE61_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE61_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE61_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE61_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE61_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE61_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE61_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE61_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE61_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE61_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE61_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE61_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE61_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE62_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE62_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE62_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE62_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE62_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE62_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE62_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE62_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE62_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE62_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE62_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE62_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE62_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE62_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE62_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE62_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE62_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE62_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE62_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE62_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE62_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE62_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE62_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE62_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE62_LOCK1_LOCK_S_Enum; + +/* ===================================================== PAGE63_LOCK0 ====================================================== */ +/* ===================================== OTP_DATA_RAW PAGE63_LOCK0 NO_KEY_STATE [6..6] ===================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE63_LOCK0_NO_KEY_STATE */ + OTP_DATA_RAW_PAGE63_LOCK0_NO_KEY_STATE_read_only = 0,/*!< read_only : read_only */ + OTP_DATA_RAW_PAGE63_LOCK0_NO_KEY_STATE_inaccessible = 1,/*!< inaccessible : inaccessible */ +} OTP_DATA_RAW_PAGE63_LOCK0_NO_KEY_STATE_Enum; + +/* ===================================================== PAGE63_LOCK1 ====================================================== */ +/* ======================================= OTP_DATA_RAW PAGE63_LOCK1 LOCK_BL [4..5] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE63_LOCK1_LOCK_BL */ + OTP_DATA_RAW_PAGE63_LOCK1_LOCK_BL_read_write = 0,/*!< read_write : Bootloader permits user reads and writes to this + page */ + OTP_DATA_RAW_PAGE63_LOCK1_LOCK_BL_read_only = 1,/*!< read_only : Bootloader permits user reads of this page */ + OTP_DATA_RAW_PAGE63_LOCK1_LOCK_BL_inaccessible = 3,/*!< inaccessible : Bootloader does not permit user access to this + page */ +} OTP_DATA_RAW_PAGE63_LOCK1_LOCK_BL_Enum; + +/* ======================================= OTP_DATA_RAW PAGE63_LOCK1 LOCK_NS [2..3] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE63_LOCK1_LOCK_NS */ + OTP_DATA_RAW_PAGE63_LOCK1_LOCK_NS_read_write = 0,/*!< read_write : Page can be read by Non-secure software, and Secure + software may permit Non-secure writes. */ + OTP_DATA_RAW_PAGE63_LOCK1_LOCK_NS_read_only = 1,/*!< read_only : Page can be read by Non-secure software */ + OTP_DATA_RAW_PAGE63_LOCK1_LOCK_NS_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Non-secure software. */ +} OTP_DATA_RAW_PAGE63_LOCK1_LOCK_NS_Enum; + +/* ======================================== OTP_DATA_RAW PAGE63_LOCK1 LOCK_S [0..1] ======================================== */ +typedef enum { /*!< OTP_DATA_RAW_PAGE63_LOCK1_LOCK_S */ + OTP_DATA_RAW_PAGE63_LOCK1_LOCK_S_read_write = 0,/*!< read_write : Page is fully accessible by Secure software. */ + OTP_DATA_RAW_PAGE63_LOCK1_LOCK_S_read_only = 1,/*!< read_only : Page can be read by Secure software, but can not + be written. */ + OTP_DATA_RAW_PAGE63_LOCK1_LOCK_S_inaccessible = 3,/*!< inaccessible : Page can not be accessed by Secure software. */ +} OTP_DATA_RAW_PAGE63_LOCK1_LOCK_S_Enum; + + + +/* =========================================================================================================================== */ +/* ================ TBMAN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PLATFORM ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ USB_DPRAM ================ */ +/* =========================================================================================================================== */ + +/* =================================================== SETUP_PACKET_LOW ==================================================== */ +/* =================================================== SETUP_PACKET_HIGH =================================================== */ +/* ==================================================== EP1_IN_CONTROL ===================================================== */ +/* ==================================== USB_DPRAM EP1_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP1_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP1_OUT_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP2_IN_CONTROL ===================================================== */ +/* ==================================== USB_DPRAM EP2_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP2_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP2_OUT_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP3_IN_CONTROL ===================================================== */ +/* ==================================== USB_DPRAM EP3_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP3_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP3_OUT_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP4_IN_CONTROL ===================================================== */ +/* ==================================== USB_DPRAM EP4_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP4_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP4_OUT_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP5_IN_CONTROL ===================================================== */ +/* ==================================== USB_DPRAM EP5_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP5_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP5_OUT_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP6_IN_CONTROL ===================================================== */ +/* ==================================== USB_DPRAM EP6_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP6_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP6_OUT_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP7_IN_CONTROL ===================================================== */ +/* ==================================== USB_DPRAM EP7_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP7_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP7_OUT_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP8_IN_CONTROL ===================================================== */ +/* ==================================== USB_DPRAM EP8_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP8_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP8_OUT_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP9_IN_CONTROL ===================================================== */ +/* ==================================== USB_DPRAM EP9_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP9_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP9_OUT_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP10_IN_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP10_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP10_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP10_OUT_CONTROL ENDPOINT_TYPE [26..27] =================================== */ +typedef enum { /*!< USB_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP11_IN_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP11_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP11_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP11_OUT_CONTROL ENDPOINT_TYPE [26..27] =================================== */ +typedef enum { /*!< USB_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP12_IN_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP12_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP12_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP12_OUT_CONTROL ENDPOINT_TYPE [26..27] =================================== */ +typedef enum { /*!< USB_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP13_IN_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP13_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP13_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP13_OUT_CONTROL ENDPOINT_TYPE [26..27] =================================== */ +typedef enum { /*!< USB_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP14_IN_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP14_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP14_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP14_OUT_CONTROL ENDPOINT_TYPE [26..27] =================================== */ +typedef enum { /*!< USB_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP15_IN_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP15_IN_CONTROL ENDPOINT_TYPE [26..27] ==================================== */ +typedef enum { /*!< USB_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP15_OUT_CONTROL ==================================================== */ +/* =================================== USB_DPRAM EP15_OUT_CONTROL ENDPOINT_TYPE [26..27] =================================== */ +typedef enum { /*!< USB_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE */ + USB_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USB_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USB_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USB_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USB_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ================================================= EP0_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP0_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP0_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP0_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP1_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP1_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP1_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP1_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP2_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP2_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP2_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP2_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP3_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP3_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP3_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP3_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP4_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP4_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP4_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP4_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP5_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP5_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP5_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP5_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP6_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP6_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP6_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP6_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP7_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP7_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP7_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP7_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP8_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP8_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP8_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP8_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP9_IN_BUFFER_CONTROL ================================================= */ +/* =========================== USB_DPRAM EP9_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP9_OUT_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP9_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP10_IN_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP10_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP10_OUT_BUFFER_CONTROL ================================================ */ +/* ========================== USB_DPRAM EP10_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================== */ +typedef enum { /*!< USB_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP11_IN_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP11_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP11_OUT_BUFFER_CONTROL ================================================ */ +/* ========================== USB_DPRAM EP11_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================== */ +typedef enum { /*!< USB_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP12_IN_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP12_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP12_OUT_BUFFER_CONTROL ================================================ */ +/* ========================== USB_DPRAM EP12_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================== */ +typedef enum { /*!< USB_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP13_IN_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP13_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP13_OUT_BUFFER_CONTROL ================================================ */ +/* ========================== USB_DPRAM EP13_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================== */ +typedef enum { /*!< USB_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP14_IN_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP14_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP14_OUT_BUFFER_CONTROL ================================================ */ +/* ========================== USB_DPRAM EP14_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================== */ +typedef enum { /*!< USB_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP15_IN_BUFFER_CONTROL ================================================= */ +/* ========================== USB_DPRAM EP15_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] =========================== */ +typedef enum { /*!< USB_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP15_OUT_BUFFER_CONTROL ================================================ */ +/* ========================== USB_DPRAM EP15_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================== */ +typedef enum { /*!< USB_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USB_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USB_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USB_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USB_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USB_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + + +/** @} */ /* End of group EnumValue_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#endif /* RP2350_H */ + + +/** @} */ /* End of group RP2350 */ + +/** @} */ /* End of group Raspberry Pi */ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/RP2350.svd b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/RP2350.svd new file mode 100644 index 000000000..aa2c36213 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/RP2350.svd @@ -0,0 +1,105849 @@ + + + + Raspberry Pi + RP2350 + RP + 0.1 + + Dual Cortex-M33 or Hazard3 processors at 150MHz + 520kB on-chip SRAM, in 10 independent banks + Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD + 8kB of one-time-programmable storage (OTP) + Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus + Additional 16MB flash/PSRAM accessible via optional second chip-select + On-chip switched-mode power supply to generate core voltage + Low-quiescent-current LDO mode can be enabled for sleep states + 2x on-chip PLLs for internal or external clock generation + GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) + Security features: + Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP + Protected OTP storage for optional boot decryption key + Global bus filtering based on Arm or RISC-V security/privilege levels + Peripherals, GPIOs and DMA channels individually assignable to security domains + Hardware mitigations for fault injection attacks + Hardware SHA-256 accelerator + Peripherals: + 2x UARTs + 2x SPI controllers + 2x I2C controllers + 24x PWM channels + USB 1.1 controller and PHY, with host and device support + 12x PIO state machines + 1x HSTX peripheral + + 32 + 32 + 0xffffffff + 0x00000000 + read-write + + Copyright (c) 2024 Raspberry Pi Ltd. + + SPDX-License-Identifier: BSD-3-Clause + + + CM33 + r1p0 + little + true + true + 8 + 4 + 1 + 1 + false + 52 + + 8 + + + RESETS + 0x40020000 + + 0 + 12 + registers + + + + RESET + 0x00000000 + 0x1fffffff + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + WDSEL + 0x00000004 + 0x00000000 + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + RESET_DONE + 0x00000008 + 0x00000000 + + + USBCTRL + [28:28] + read-only + + + UART1 + [27:27] + read-only + + + UART0 + [26:26] + read-only + + + TRNG + [25:25] + read-only + + + TIMER1 + [24:24] + read-only + + + TIMER0 + [23:23] + read-only + + + TBMAN + [22:22] + read-only + + + SYSINFO + [21:21] + read-only + + + SYSCFG + [20:20] + read-only + + + SPI1 + [19:19] + read-only + + + SPI0 + [18:18] + read-only + + + SHA256 + [17:17] + read-only + + + PWM + [16:16] + read-only + + + PLL_USB + [15:15] + read-only + + + PLL_SYS + [14:14] + read-only + + + PIO2 + [13:13] + read-only + + + PIO1 + [12:12] + read-only + + + PIO0 + [11:11] + read-only + + + PADS_QSPI + [10:10] + read-only + + + PADS_BANK0 + [9:9] + read-only + + + JTAG + [8:8] + read-only + + + IO_QSPI + [7:7] + read-only + + + IO_BANK0 + [6:6] + read-only + + + I2C1 + [5:5] + read-only + + + I2C0 + [4:4] + read-only + + + HSTX + [3:3] + read-only + + + DMA + [2:2] + read-only + + + BUSCTRL + [1:1] + read-only + + + ADC + [0:0] + read-only + + + + + + + PSM + 0x40018000 + + 0 + 16 + registers + + + + FRCE_ON + 0x00000000 + Force block out of reset (i.e. power it on) + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + FRCE_OFF + 0x00000004 + Force into reset (i.e. power it off) + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + WDSEL + 0x00000008 + Set to 1 if the watchdog should reset this + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + DONE + 0x0000000c + Is the subsystem ready? + 0x00000000 + + + PROC1 + [24:24] + read-only + + + PROC0 + [23:23] + read-only + + + ACCESSCTRL + [22:22] + read-only + + + SIO + [21:21] + read-only + + + XIP + [20:20] + read-only + + + SRAM9 + [19:19] + read-only + + + SRAM8 + [18:18] + read-only + + + SRAM7 + [17:17] + read-only + + + SRAM6 + [16:16] + read-only + + + SRAM5 + [15:15] + read-only + + + SRAM4 + [14:14] + read-only + + + SRAM3 + [13:13] + read-only + + + SRAM2 + [12:12] + read-only + + + SRAM1 + [11:11] + read-only + + + SRAM0 + [10:10] + read-only + + + BOOTRAM + [9:9] + read-only + + + ROM + [8:8] + read-only + + + BUSFABRIC + [7:7] + read-only + + + PSM_READY + [6:6] + read-only + + + CLOCKS + [5:5] + read-only + + + RESETS + [4:4] + read-only + + + XOSC + [3:3] + read-only + + + ROSC + [2:2] + read-only + + + OTP + [1:1] + read-only + + + PROC_COLD + [0:0] + read-only + + + + + + + CLOCKS + 0x40010000 + + 0 + 212 + registers + + + CLOCKS_IRQ + 30 + + + + CLK_GPOUT0_CTRL + 0x00000000 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT0_DIV + 0x00000004 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT0_SELECTED + 0x00000008 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT0_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT1_CTRL + 0x0000000c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT1_DIV + 0x00000010 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT1_SELECTED + 0x00000014 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT1_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT2_CTRL + 0x00000018 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT2_DIV + 0x0000001c + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT2_SELECTED + 0x00000020 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT2_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT3_CTRL + 0x00000024 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT3_DIV + 0x00000028 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT3_SELECTED + 0x0000002c + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT3_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_REF_CTRL + 0x00000030 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [6:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb_primary_ref_opcg + 3 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [1:0] + read-write + + + rosc_clksrc_ph + 0 + + + clksrc_clk_ref_aux + 1 + + + xosc_clksrc + 2 + + + lposc_clksrc + 3 + + + + + + + CLK_REF_DIV + 0x00000034 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [23:16] + read-write + + + + + CLK_REF_SELECTED + 0x00000038 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_REF_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [3:0] + read-only + + + + + CLK_SYS_CTRL + 0x0000003c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_pll_usb + 1 + + + rosc_clksrc + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [0:0] + read-write + + + clk_ref + 0 + + + clksrc_clk_sys_aux + 1 + + + + + + + CLK_SYS_DIV + 0x00000040 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_SYS_SELECTED + 0x00000044 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_SYS_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [1:0] + read-only + + + + + CLK_PERI_CTRL + 0x00000048 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + rosc_clksrc_ph + 3 + + + xosc_clksrc + 4 + + + clksrc_gpin0 + 5 + + + clksrc_gpin1 + 6 + + + + + + + CLK_PERI_DIV + 0x0000004c + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_PERI_SELECTED + 0x00000050 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_PERI_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_HSTX_CTRL + 0x00000054 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + clksrc_gpin0 + 3 + + + clksrc_gpin1 + 4 + + + + + + + CLK_HSTX_DIV + 0x00000058 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_HSTX_SELECTED + 0x0000005c + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_HSTX_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_USB_CTRL + 0x00000060 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_USB_DIV + 0x00000064 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_USB_SELECTED + 0x00000068 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_USB_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_ADC_CTRL + 0x0000006c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_ADC_DIV + 0x00000070 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_ADC_SELECTED + 0x00000074 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_ADC_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + DFTCLK_XOSC_CTRL + 0x00000078 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary + 1 + + + clksrc_gpin0 + 2 + + + + + + + DFTCLK_ROSC_CTRL + 0x0000007c + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_sys_primary_rosc + 1 + + + clksrc_gpin1 + 2 + + + + + + + DFTCLK_LPOSC_CTRL + 0x00000080 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary_lposc + 1 + + + clksrc_gpin1 + 2 + + + + + + + CLK_SYS_RESUS_CTRL + 0x00000084 + 0x000000ff + + + CLEAR + For clearing the resus after the fault that triggered it has been corrected + [16:16] + read-write + + + FRCE + Force a resus, for test purposes only + [12:12] + read-write + + + ENABLE + Enable resus + [8:8] + read-write + + + TIMEOUT + This is expressed as a number of clk_ref cycles + and must be >= 2x clk_ref_freq/min_clk_tst_freq + [7:0] + read-write + + + + + CLK_SYS_RESUS_STATUS + 0x00000088 + 0x00000000 + + + RESUSSED + Clock has been resuscitated, correct the error then send ctrl_clear=1 + [0:0] + read-only + + + + + FC0_REF_KHZ + 0x0000008c + Reference clock frequency in kHz + 0x00000000 + + + FC0_REF_KHZ + [19:0] + read-write + + + + + FC0_MIN_KHZ + 0x00000090 + Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + 0x00000000 + + + FC0_MIN_KHZ + [24:0] + read-write + + + + + FC0_MAX_KHZ + 0x00000094 + Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + 0x01ffffff + + + FC0_MAX_KHZ + [24:0] + read-write + + + + + FC0_DELAY + 0x00000098 + Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period + 0x00000001 + + + FC0_DELAY + [2:0] + read-write + + + + + FC0_INTERVAL + 0x0000009c + The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval + The default gives a test interval of 250us + 0x00000008 + + + FC0_INTERVAL + [3:0] + read-write + + + + + FC0_SRC + 0x000000a0 + Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count + 0x00000000 + + + FC0_SRC + [7:0] + read-write + + + NULL + 0 + + + pll_sys_clksrc_primary + 1 + + + pll_usb_clksrc_primary + 2 + + + rosc_clksrc + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clksrc_gpin0 + 6 + + + clksrc_gpin1 + 7 + + + clk_ref + 8 + + + clk_sys + 9 + + + clk_peri + 10 + + + clk_usb + 11 + + + clk_adc + 12 + + + clk_hstx + 13 + + + lposc_clksrc + 14 + + + otp_clk2fc + 15 + + + pll_usb_clksrc_primary_dft + 16 + + + + + + + FC0_STATUS + 0x000000a4 + Frequency counter status + 0x00000000 + + + DIED + Test clock stopped during test + [28:28] + read-only + + + FAST + Test clock faster than expected, only valid when status_done=1 + [24:24] + read-only + + + SLOW + Test clock slower than expected, only valid when status_done=1 + [20:20] + read-only + + + FAIL + Test failed + [16:16] + read-only + + + WAITING + Waiting for test clock to start + [12:12] + read-only + + + RUNNING + Test running + [8:8] + read-only + + + DONE + Test complete + [4:4] + read-only + + + PASS + Test passed + [0:0] + read-only + + + + + FC0_RESULT + 0x000000a8 + Result of frequency measurement, only valid when status_done=1 + 0x00000000 + + + KHZ + [29:5] + read-only + + + FRAC + [4:0] + read-only + + + + + WAKE_EN0 + 0x000000ac + enable clock in wake mode + 0xffffffff + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + WAKE_EN1 + 0x000000b0 + enable clock in wake mode + 0x7fffffff + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + SLEEP_EN0 + 0x000000b4 + enable clock in sleep mode + 0xffffffff + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + SLEEP_EN1 + 0x000000b8 + enable clock in sleep mode + 0x7fffffff + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + ENABLED0 + 0x000000bc + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_SIO + [31:31] + read-only + + + CLK_SYS_SHA256 + [30:30] + read-only + + + CLK_SYS_PSM + [29:29] + read-only + + + CLK_SYS_ROSC + [28:28] + read-only + + + CLK_SYS_ROM + [27:27] + read-only + + + CLK_SYS_RESETS + [26:26] + read-only + + + CLK_SYS_PWM + [25:25] + read-only + + + CLK_SYS_POWMAN + [24:24] + read-only + + + CLK_REF_POWMAN + [23:23] + read-only + + + CLK_SYS_PLL_USB + [22:22] + read-only + + + CLK_SYS_PLL_SYS + [21:21] + read-only + + + CLK_SYS_PIO2 + [20:20] + read-only + + + CLK_SYS_PIO1 + [19:19] + read-only + + + CLK_SYS_PIO0 + [18:18] + read-only + + + CLK_SYS_PADS + [17:17] + read-only + + + CLK_SYS_OTP + [16:16] + read-only + + + CLK_REF_OTP + [15:15] + read-only + + + CLK_SYS_JTAG + [14:14] + read-only + + + CLK_SYS_IO + [13:13] + read-only + + + CLK_SYS_I2C1 + [12:12] + read-only + + + CLK_SYS_I2C0 + [11:11] + read-only + + + CLK_SYS_HSTX + [10:10] + read-only + + + CLK_HSTX + [9:9] + read-only + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-only + + + CLK_SYS_DMA + [7:7] + read-only + + + CLK_SYS_BUSFABRIC + [6:6] + read-only + + + CLK_SYS_BUSCTRL + [5:5] + read-only + + + CLK_SYS_BOOTRAM + [4:4] + read-only + + + CLK_SYS_ADC + [3:3] + read-only + + + CLK_ADC + [2:2] + read-only + + + CLK_SYS_ACCESSCTRL + [1:1] + read-only + + + CLK_SYS_CLOCKS + [0:0] + read-only + + + + + ENABLED1 + 0x000000c0 + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_XOSC + [30:30] + read-only + + + CLK_SYS_XIP + [29:29] + read-only + + + CLK_SYS_WATCHDOG + [28:28] + read-only + + + CLK_USB + [27:27] + read-only + + + CLK_SYS_USBCTRL + [26:26] + read-only + + + CLK_SYS_UART1 + [25:25] + read-only + + + CLK_PERI_UART1 + [24:24] + read-only + + + CLK_SYS_UART0 + [23:23] + read-only + + + CLK_PERI_UART0 + [22:22] + read-only + + + CLK_SYS_TRNG + [21:21] + read-only + + + CLK_SYS_TIMER1 + [20:20] + read-only + + + CLK_SYS_TIMER0 + [19:19] + read-only + + + CLK_SYS_TICKS + [18:18] + read-only + + + CLK_REF_TICKS + [17:17] + read-only + + + CLK_SYS_TBMAN + [16:16] + read-only + + + CLK_SYS_SYSINFO + [15:15] + read-only + + + CLK_SYS_SYSCFG + [14:14] + read-only + + + CLK_SYS_SRAM9 + [13:13] + read-only + + + CLK_SYS_SRAM8 + [12:12] + read-only + + + CLK_SYS_SRAM7 + [11:11] + read-only + + + CLK_SYS_SRAM6 + [10:10] + read-only + + + CLK_SYS_SRAM5 + [9:9] + read-only + + + CLK_SYS_SRAM4 + [8:8] + read-only + + + CLK_SYS_SRAM3 + [7:7] + read-only + + + CLK_SYS_SRAM2 + [6:6] + read-only + + + CLK_SYS_SRAM1 + [5:5] + read-only + + + CLK_SYS_SRAM0 + [4:4] + read-only + + + CLK_SYS_SPI1 + [3:3] + read-only + + + CLK_PERI_SPI1 + [2:2] + read-only + + + CLK_SYS_SPI0 + [1:1] + read-only + + + CLK_PERI_SPI0 + [0:0] + read-only + + + + + INTR + 0x000000c4 + Raw Interrupts + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + INTE + 0x000000c8 + Interrupt Enable + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTF + 0x000000cc + Interrupt Force + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTS + 0x000000d0 + Interrupt status after masking & forcing + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + + + TICKS + 0x40108000 + + 0 + 72 + registers + + + + PROC0_CTRL + 0x00000000 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + PROC0_CYCLES + 0x00000004 + 0x00000000 + + + PROC0_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + PROC0_COUNT + 0x00000008 + 0x00000000 + + + PROC0_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + PROC1_CTRL + 0x0000000c + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + PROC1_CYCLES + 0x00000010 + 0x00000000 + + + PROC1_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + PROC1_COUNT + 0x00000014 + 0x00000000 + + + PROC1_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + TIMER0_CTRL + 0x00000018 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + TIMER0_CYCLES + 0x0000001c + 0x00000000 + + + TIMER0_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + TIMER0_COUNT + 0x00000020 + 0x00000000 + + + TIMER0_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + TIMER1_CTRL + 0x00000024 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + TIMER1_CYCLES + 0x00000028 + 0x00000000 + + + TIMER1_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + TIMER1_COUNT + 0x0000002c + 0x00000000 + + + TIMER1_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + WATCHDOG_CTRL + 0x00000030 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + WATCHDOG_CYCLES + 0x00000034 + 0x00000000 + + + WATCHDOG_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + WATCHDOG_COUNT + 0x00000038 + 0x00000000 + + + WATCHDOG_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + RISCV_CTRL + 0x0000003c + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + RISCV_CYCLES + 0x00000040 + 0x00000000 + + + RISCV_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + RISCV_COUNT + 0x00000044 + 0x00000000 + + + RISCV_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + + + PADS_BANK0 + 0x40038000 + + 0 + 204 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO0 + 0x00000004 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO1 + 0x00000008 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO2 + 0x0000000c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO3 + 0x00000010 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO4 + 0x00000014 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO5 + 0x00000018 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO6 + 0x0000001c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO7 + 0x00000020 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO8 + 0x00000024 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO9 + 0x00000028 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO10 + 0x0000002c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO11 + 0x00000030 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO12 + 0x00000034 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO13 + 0x00000038 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO14 + 0x0000003c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO15 + 0x00000040 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO16 + 0x00000044 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO17 + 0x00000048 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO18 + 0x0000004c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO19 + 0x00000050 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO20 + 0x00000054 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO21 + 0x00000058 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO22 + 0x0000005c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO23 + 0x00000060 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO24 + 0x00000064 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO25 + 0x00000068 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO26 + 0x0000006c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO27 + 0x00000070 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO28 + 0x00000074 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO29 + 0x00000078 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO30 + 0x0000007c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO31 + 0x00000080 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO32 + 0x00000084 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO33 + 0x00000088 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO34 + 0x0000008c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO35 + 0x00000090 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO36 + 0x00000094 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO37 + 0x00000098 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO38 + 0x0000009c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO39 + 0x000000a0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO40 + 0x000000a4 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO41 + 0x000000a8 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO42 + 0x000000ac + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO43 + 0x000000b0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO44 + 0x000000b4 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO45 + 0x000000b8 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO46 + 0x000000bc + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO47 + 0x000000c0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWCLK + 0x000000c4 + 0x0000005a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWD + 0x000000c8 + 0x0000005a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + PADS_QSPI + 0x40040000 + + 0 + 28 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO_QSPI_SCLK + 0x00000004 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD0 + 0x00000008 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD1 + 0x0000000c + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD2 + 0x00000010 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD3 + 0x00000014 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SS + 0x00000018 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + IO_QSPI + 0x40030000 + + 0 + 576 + registers + + + IO_IRQ_QSPI + 23 + + + IO_IRQ_QSPI_NS + 24 + + + + USBPHY_DP_STATUS + 0x00000000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DP_CTRL + 0x00000004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + siob_proc_56 + 5 + + + null + 31 + + + + + + + USBPHY_DM_STATUS + 0x00000008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DM_CTRL + 0x0000000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + siob_proc_57 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SCLK_STATUS + 0x00000010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SCLK_CTRL + 0x00000014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sclk + 0 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + siob_proc_58 + 5 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SS_STATUS + 0x00000018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SS_CTRL + 0x0000001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_ss_n_0 + 0 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + siob_proc_59 + 5 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SD0_STATUS + 0x00000020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD0_CTRL + 0x00000024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd0 + 0 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + siob_proc_60 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD1_STATUS + 0x00000028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD1_CTRL + 0x0000002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd1 + 0 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + siob_proc_61 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD2_STATUS + 0x00000030 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD2_CTRL + 0x00000034 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd2 + 0 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + siob_proc_62 + 5 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SD3_STATUS + 0x00000038 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD3_CTRL + 0x0000003c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd3 + 0 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + siob_proc_63 + 5 + + + uart0_rx + 11 + + + null + 31 + + + + + + + IRQSUMMARY_PROC0_SECURE + 0x00000200 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE + 0x00000204 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE + 0x00000208 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE + 0x0000020c + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE + 0x00000210 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE + 0x00000214 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + INTR + 0x00000218 + Raw Interrupts + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + oneToClear + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + oneToClear + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + oneToClear + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + oneToClear + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE + 0x0000021c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF + 0x00000220 + Interrupt Force for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS + 0x00000224 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE + 0x00000228 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF + 0x0000022c + Interrupt Force for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS + 0x00000230 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE + 0x00000234 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF + 0x00000238 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS + 0x0000023c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + + + IO_BANK0 + 0x40028000 + + 0 + 800 + registers + + + IO_IRQ_BANK0 + 21 + + + IO_IRQ_BANK0_NS + 22 + + + + GPIO0_STATUS + 0x00000000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO0_CTRL + 0x00000004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tck + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + siob_proc_0 + 5 + + + pio0_0 + 6 + + + pio1_0 + 7 + + + pio2_0 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO1_STATUS + 0x00000008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO1_CTRL + 0x0000000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tms + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + siob_proc_1 + 5 + + + pio0_1 + 6 + + + pio1_1 + 7 + + + pio2_1 + 8 + + + coresight_traceclk + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO2_STATUS + 0x00000010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO2_CTRL + 0x00000014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdi + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + siob_proc_2 + 5 + + + pio0_2 + 6 + + + pio1_2 + 7 + + + pio2_2 + 8 + + + coresight_tracedata_0 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO3_STATUS + 0x00000018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO3_CTRL + 0x0000001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdo + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + siob_proc_3 + 5 + + + pio0_3 + 6 + + + pio1_3 + 7 + + + pio2_3 + 8 + + + coresight_tracedata_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO4_STATUS + 0x00000020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO4_CTRL + 0x00000024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + siob_proc_4 + 5 + + + pio0_4 + 6 + + + pio1_4 + 7 + + + pio2_4 + 8 + + + coresight_tracedata_2 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO5_STATUS + 0x00000028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO5_CTRL + 0x0000002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + siob_proc_5 + 5 + + + pio0_5 + 6 + + + pio1_5 + 7 + + + pio2_5 + 8 + + + coresight_tracedata_3 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO6_STATUS + 0x00000030 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO6_CTRL + 0x00000034 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + siob_proc_6 + 5 + + + pio0_6 + 6 + + + pio1_6 + 7 + + + pio2_6 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO7_STATUS + 0x00000038 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO7_CTRL + 0x0000003c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + siob_proc_7 + 5 + + + pio0_7 + 6 + + + pio1_7 + 7 + + + pio2_7 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO8_STATUS + 0x00000040 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO8_CTRL + 0x00000044 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + siob_proc_8 + 5 + + + pio0_8 + 6 + + + pio1_8 + 7 + + + pio2_8 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO9_STATUS + 0x00000048 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO9_CTRL + 0x0000004c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + siob_proc_9 + 5 + + + pio0_9 + 6 + + + pio1_9 + 7 + + + pio2_9 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO10_STATUS + 0x00000050 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO10_CTRL + 0x00000054 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + siob_proc_10 + 5 + + + pio0_10 + 6 + + + pio1_10 + 7 + + + pio2_10 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO11_STATUS + 0x00000058 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO11_CTRL + 0x0000005c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + siob_proc_11 + 5 + + + pio0_11 + 6 + + + pio1_11 + 7 + + + pio2_11 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO12_STATUS + 0x00000060 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO12_CTRL + 0x00000064 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_0 + 0 + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + siob_proc_12 + 5 + + + pio0_12 + 6 + + + pio1_12 + 7 + + + pio2_12 + 8 + + + clocks_gpin_0 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO13_STATUS + 0x00000068 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO13_CTRL + 0x0000006c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_1 + 0 + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + siob_proc_13 + 5 + + + pio0_13 + 6 + + + pio1_13 + 7 + + + pio2_13 + 8 + + + clocks_gpout_0 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO14_STATUS + 0x00000070 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO14_CTRL + 0x00000074 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_2 + 0 + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + siob_proc_14 + 5 + + + pio0_14 + 6 + + + pio1_14 + 7 + + + pio2_14 + 8 + + + clocks_gpin_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO15_STATUS + 0x00000078 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO15_CTRL + 0x0000007c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_3 + 0 + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + siob_proc_15 + 5 + + + pio0_15 + 6 + + + pio1_15 + 7 + + + pio2_15 + 8 + + + clocks_gpout_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO16_STATUS + 0x00000080 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO16_CTRL + 0x00000084 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_4 + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + siob_proc_16 + 5 + + + pio0_16 + 6 + + + pio1_16 + 7 + + + pio2_16 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO17_STATUS + 0x00000088 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO17_CTRL + 0x0000008c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_5 + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + siob_proc_17 + 5 + + + pio0_17 + 6 + + + pio1_17 + 7 + + + pio2_17 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO18_STATUS + 0x00000090 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO18_CTRL + 0x00000094 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_6 + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + siob_proc_18 + 5 + + + pio0_18 + 6 + + + pio1_18 + 7 + + + pio2_18 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO19_STATUS + 0x00000098 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO19_CTRL + 0x0000009c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_7 + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + siob_proc_19 + 5 + + + pio0_19 + 6 + + + pio1_19 + 7 + + + pio2_19 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO20_STATUS + 0x000000a0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO20_CTRL + 0x000000a4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + siob_proc_20 + 5 + + + pio0_20 + 6 + + + pio1_20 + 7 + + + pio2_20 + 8 + + + clocks_gpin_0 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO21_STATUS + 0x000000a8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO21_CTRL + 0x000000ac + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + siob_proc_21 + 5 + + + pio0_21 + 6 + + + pio1_21 + 7 + + + pio2_21 + 8 + + + clocks_gpout_0 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO22_STATUS + 0x000000b0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO22_CTRL + 0x000000b4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + siob_proc_22 + 5 + + + pio0_22 + 6 + + + pio1_22 + 7 + + + pio2_22 + 8 + + + clocks_gpin_1 + 9 + + + usb_muxing_vbus_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO23_STATUS + 0x000000b8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO23_CTRL + 0x000000bc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + siob_proc_23 + 5 + + + pio0_23 + 6 + + + pio1_23 + 7 + + + pio2_23 + 8 + + + clocks_gpout_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO24_STATUS + 0x000000c0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO24_CTRL + 0x000000c4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + siob_proc_24 + 5 + + + pio0_24 + 6 + + + pio1_24 + 7 + + + pio2_24 + 8 + + + clocks_gpout_2 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO25_STATUS + 0x000000c8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO25_CTRL + 0x000000cc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + siob_proc_25 + 5 + + + pio0_25 + 6 + + + pio1_25 + 7 + + + pio2_25 + 8 + + + clocks_gpout_3 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO26_STATUS + 0x000000d0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO26_CTRL + 0x000000d4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + siob_proc_26 + 5 + + + pio0_26 + 6 + + + pio1_26 + 7 + + + pio2_26 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO27_STATUS + 0x000000d8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO27_CTRL + 0x000000dc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + siob_proc_27 + 5 + + + pio0_27 + 6 + + + pio1_27 + 7 + + + pio2_27 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO28_STATUS + 0x000000e0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO28_CTRL + 0x000000e4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + siob_proc_28 + 5 + + + pio0_28 + 6 + + + pio1_28 + 7 + + + pio2_28 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO29_STATUS + 0x000000e8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO29_CTRL + 0x000000ec + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + siob_proc_29 + 5 + + + pio0_29 + 6 + + + pio1_29 + 7 + + + pio2_29 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO30_STATUS + 0x000000f0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO30_CTRL + 0x000000f4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + siob_proc_30 + 5 + + + pio0_30 + 6 + + + pio1_30 + 7 + + + pio2_30 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO31_STATUS + 0x000000f8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO31_CTRL + 0x000000fc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + siob_proc_31 + 5 + + + pio0_31 + 6 + + + pio1_31 + 7 + + + pio2_31 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO32_STATUS + 0x00000100 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO32_CTRL + 0x00000104 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_8 + 4 + + + siob_proc_32 + 5 + + + pio0_32 + 6 + + + pio1_32 + 7 + + + pio2_32 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO33_STATUS + 0x00000108 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO33_CTRL + 0x0000010c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_8 + 4 + + + siob_proc_33 + 5 + + + pio0_33 + 6 + + + pio1_33 + 7 + + + pio2_33 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO34_STATUS + 0x00000110 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO34_CTRL + 0x00000114 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_9 + 4 + + + siob_proc_34 + 5 + + + pio0_34 + 6 + + + pio1_34 + 7 + + + pio2_34 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO35_STATUS + 0x00000118 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO35_CTRL + 0x0000011c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_9 + 4 + + + siob_proc_35 + 5 + + + pio0_35 + 6 + + + pio1_35 + 7 + + + pio2_35 + 8 + + + usb_muxing_vbus_en + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO36_STATUS + 0x00000120 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO36_CTRL + 0x00000124 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_10 + 4 + + + siob_proc_36 + 5 + + + pio0_36 + 6 + + + pio1_36 + 7 + + + pio2_36 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO37_STATUS + 0x00000128 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO37_CTRL + 0x0000012c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_10 + 4 + + + siob_proc_37 + 5 + + + pio0_37 + 6 + + + pio1_37 + 7 + + + pio2_37 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO38_STATUS + 0x00000130 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO38_CTRL + 0x00000134 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_11 + 4 + + + siob_proc_38 + 5 + + + pio0_38 + 6 + + + pio1_38 + 7 + + + pio2_38 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO39_STATUS + 0x00000138 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO39_CTRL + 0x0000013c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_11 + 4 + + + siob_proc_39 + 5 + + + pio0_39 + 6 + + + pio1_39 + 7 + + + pio2_39 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO40_STATUS + 0x00000140 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO40_CTRL + 0x00000144 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_8 + 4 + + + siob_proc_40 + 5 + + + pio0_40 + 6 + + + pio1_40 + 7 + + + pio2_40 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO41_STATUS + 0x00000148 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO41_CTRL + 0x0000014c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_8 + 4 + + + siob_proc_41 + 5 + + + pio0_41 + 6 + + + pio1_41 + 7 + + + pio2_41 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO42_STATUS + 0x00000150 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO42_CTRL + 0x00000154 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_9 + 4 + + + siob_proc_42 + 5 + + + pio0_42 + 6 + + + pio1_42 + 7 + + + pio2_42 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO43_STATUS + 0x00000158 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO43_CTRL + 0x0000015c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_9 + 4 + + + siob_proc_43 + 5 + + + pio0_43 + 6 + + + pio1_43 + 7 + + + pio2_43 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO44_STATUS + 0x00000160 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO44_CTRL + 0x00000164 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_10 + 4 + + + siob_proc_44 + 5 + + + pio0_44 + 6 + + + pio1_44 + 7 + + + pio2_44 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO45_STATUS + 0x00000168 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO45_CTRL + 0x0000016c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_10 + 4 + + + siob_proc_45 + 5 + + + pio0_45 + 6 + + + pio1_45 + 7 + + + pio2_45 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO46_STATUS + 0x00000170 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO46_CTRL + 0x00000174 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_11 + 4 + + + siob_proc_46 + 5 + + + pio0_46 + 6 + + + pio1_46 + 7 + + + pio2_46 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO47_STATUS + 0x00000178 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO47_CTRL + 0x0000017c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_11 + 4 + + + siob_proc_47 + 5 + + + pio0_47 + 6 + + + pio1_47 + 7 + + + pio2_47 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + IRQSUMMARY_PROC0_SECURE0 + 0x00000200 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_SECURE1 + 0x00000204 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE0 + 0x00000208 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE1 + 0x0000020c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE0 + 0x00000210 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE1 + 0x00000214 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE0 + 0x00000218 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE1 + 0x0000021c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE0 + 0x00000220 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE1 + 0x00000224 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE0 + 0x00000228 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE1 + 0x0000022c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + INTR0 + 0x00000230 + Raw Interrupts + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO7_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO6_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO5_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO4_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO3_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO2_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO1_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO0_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + INTR1 + 0x00000234 + Raw Interrupts + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO15_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO14_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO13_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO12_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO11_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO10_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO9_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO8_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + INTR2 + 0x00000238 + Raw Interrupts + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO23_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO22_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO21_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO20_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO19_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO18_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO17_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO16_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + INTR3 + 0x0000023c + Raw Interrupts + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO31_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO30_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO29_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO28_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO27_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO26_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO25_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO24_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + INTR4 + 0x00000240 + Raw Interrupts + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO39_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO38_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO37_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO36_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO35_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO34_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO33_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO32_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + INTR5 + 0x00000244 + Raw Interrupts + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO47_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO46_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO45_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO44_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO43_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO42_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO41_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO40_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE0 + 0x00000248 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE1 + 0x0000024c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE2 + 0x00000250 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE3 + 0x00000254 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE4 + 0x00000258 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE5 + 0x0000025c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF0 + 0x00000260 + Interrupt Force for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF1 + 0x00000264 + Interrupt Force for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF2 + 0x00000268 + Interrupt Force for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF3 + 0x0000026c + Interrupt Force for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF4 + 0x00000270 + Interrupt Force for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF5 + 0x00000274 + Interrupt Force for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS0 + 0x00000278 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS1 + 0x0000027c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS2 + 0x00000280 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS3 + 0x00000284 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS4 + 0x00000288 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS5 + 0x0000028c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE0 + 0x00000290 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE1 + 0x00000294 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE2 + 0x00000298 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE3 + 0x0000029c + Interrupt Enable for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE4 + 0x000002a0 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE5 + 0x000002a4 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF0 + 0x000002a8 + Interrupt Force for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF1 + 0x000002ac + Interrupt Force for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF2 + 0x000002b0 + Interrupt Force for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF3 + 0x000002b4 + Interrupt Force for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF4 + 0x000002b8 + Interrupt Force for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF5 + 0x000002bc + Interrupt Force for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS0 + 0x000002c0 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS1 + 0x000002c4 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS2 + 0x000002c8 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS3 + 0x000002cc + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS4 + 0x000002d0 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS5 + 0x000002d4 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE0 + 0x000002d8 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE1 + 0x000002dc + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE2 + 0x000002e0 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE3 + 0x000002e4 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE4 + 0x000002e8 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE5 + 0x000002ec + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF0 + 0x000002f0 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF1 + 0x000002f4 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF2 + 0x000002f8 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF3 + 0x000002fc + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF4 + 0x00000300 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF5 + 0x00000304 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS0 + 0x00000308 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS1 + 0x0000030c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS2 + 0x00000310 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS3 + 0x00000314 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS4 + 0x00000318 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS5 + 0x0000031c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + + + SYSINFO + 0x40000000 + + 0 + 24 + registers + + + + CHIP_ID + 0x00000000 + JEDEC JEP-106 compliant chip identifier. + 0x00000001 + + + REVISION + [31:28] + read-only + + + PART + [27:12] + read-only + + + MANUFACTURER + [11:1] + read-only + + + STOP_BIT + [0:0] + read-only + + + + + PACKAGE_SEL + 0x00000004 + 0x00000000 + + + PACKAGE_SEL + [0:0] + read-only + + + + + PLATFORM + 0x00000008 + Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. + 0x00000000 + + + GATESIM + [4:4] + read-only + + + BATCHSIM + [3:3] + read-only + + + HDLSIM + [2:2] + read-only + + + ASIC + [1:1] + read-only + + + FPGA + [0:0] + read-only + + + + + GITREF_RP2350 + 0x00000014 + Git hash of the chip source. Used to identify chip version. + 0x00000000 + + + GITREF_RP2350 + [31:0] + read-only + + + + + + + SHA256 + SHA-256 hash function implementation + 0x400f8000 + + 0 + 40 + registers + + + + CSR + 0x00000000 + Control and status register + 0x00001206 + + + BSWAP + Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. + + This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. + + However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. + + This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around. + [12:12] + read-write + + + DMA_SIZE + Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. + + The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block. + [9:8] + read-write + + + 8bit + 0 + + + 16bit + 1 + + + 32bit + 2 + + + + + ERR_WDATA_NOT_RDY + Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear. + [4:4] + read-write + oneToClear + + + SUM_VLD + If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. + + Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed. + [2:2] + read-only + + + WDATA_RDY + If 1, the SHA-256 core is ready to accept more data through the WDATA register. + + After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest. + [1:1] + read-only + + + START + Write 1 to prepare the SHA-256 core for a new checksum. + + The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. + + START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers. + [0:0] + write-only + + + + + WDATA + 0x00000004 + Write data register + 0x00000000 + + + WDATA + After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. + + Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. + + After this, WDATA_RDY will return high, and more data can be written (if any). + + This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block. + [31:0] + write-only + + + + + SUM0 + 0x00000008 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM0 + [31:0] + read-only + + + + + SUM1 + 0x0000000c + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM1 + [31:0] + read-only + + + + + SUM2 + 0x00000010 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM2 + [31:0] + read-only + + + + + SUM3 + 0x00000014 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM3 + [31:0] + read-only + + + + + SUM4 + 0x00000018 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM4 + [31:0] + read-only + + + + + SUM5 + 0x0000001c + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM5 + [31:0] + read-only + + + + + SUM6 + 0x00000020 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM6 + [31:0] + read-only + + + + + SUM7 + 0x00000024 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM7 + [31:0] + read-only + + + + + + + HSTX_FIFO + FIFO status and write access for HSTX + 0x50600000 + + 0 + 8 + registers + + + + STAT + 0x00000000 + FIFO status + 0x00000000 + + + WOF + FIFO was written when full. Write 1 to clear. + [10:10] + read-write + oneToClear + + + EMPTY + [9:9] + read-only + + + FULL + [8:8] + read-only + + + LEVEL + [7:0] + read-only + + + + + FIFO + 0x00000004 + Write access to FIFO + 0x00000000 + + + FIFO + [31:0] + write-only + + + + + + + HSTX_CTRL + Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. + 0x400c0000 + + 0 + 44 + registers + + + + CSR + 0x00000000 + 0x10050600 + + + CLKDIV + Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. + + For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). + + A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles. + [31:28] + read-write + + + CLKPHASE + Set the initial phase of the generated clock. + + A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: + + * The clock will be initially low + + * The first rising edge will be 0.5 clk_hstx cycles after asserting first data + + * The first falling edge will be 1.5 clk_hstx cycles after asserting first data + + This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. + + When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. + + Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined. + [27:24] + read-write + + + N_SHIFTS + Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) + + A register value of 0 means shift 32 times. + [20:16] + read-write + + + SHIFT + How many bits to right-rotate the shift register by each cycle. + + The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32. + [12:8] + read-write + + + COUPLED_SEL + Select which PIO to use for coupled mode operation. + [6:5] + read-write + + + COUPLED_MODE + Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. + + When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. + + The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. + + For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged. + [4:4] + read-write + + + EXPAND_EN + Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. + + Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN. + [1:1] + read-write + + + EN + When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. + + When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. + + Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched. + [0:0] + read-write + + + + + BIT0 + 0x00000004 + Data control register for output bit 0 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT1 + 0x00000008 + Data control register for output bit 1 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT2 + 0x0000000c + Data control register for output bit 2 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT3 + 0x00000010 + Data control register for output bit 3 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT4 + 0x00000014 + Data control register for output bit 4 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT5 + 0x00000018 + Data control register for output bit 5 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT6 + 0x0000001c + Data control register for output bit 6 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT7 + 0x00000020 + Data control register for output bit 7 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + EXPAND_SHIFT + 0x00000024 + Configure the optional shifter inside the command expander + 0x01000100 + + + ENC_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times. + [28:24] + read-write + + + ENC_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS). + [20:16] + read-write + + + RAW_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times. + [12:8] + read-write + + + RAW_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command. + [4:0] + read-write + + + + + EXPAND_TMDS + 0x00000028 + Configure the optional TMDS encoder inside the command expander + 0x00000000 + + + L2_NBITS + Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [23:21] + read-write + + + L2_ROT + Right-rotate applied to the current shifter data before the lane 2 TMDS encoder. + [20:16] + read-write + + + L1_NBITS + Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [15:13] + read-write + + + L1_ROT + Right-rotate applied to the current shifter data before the lane 1 TMDS encoder. + [12:8] + read-write + + + L0_NBITS + Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [7:5] + read-write + + + L0_ROT + Right-rotate applied to the current shifter data before the lane 0 TMDS encoder. + [4:0] + read-write + + + + + + + EPPB + Cortex-M33 EPPB vendor register block for RP2350 + 0xe0080000 + + 0 + 12 + registers + + + + NMI_MASK0 + 0x00000000 + NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. + 0x00000000 + + + NMI_MASK0 + [31:0] + read-write + + + + + NMI_MASK1 + 0x00000004 + NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. + 0x00000000 + + + NMI_MASK1 + [19:0] + read-write + + + + + SLEEPCTRL + 0x00000008 + Nonstandard sleep control register + 0x00000002 + + + WICENACK + Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK. + [2:2] + read-only + + + WICENREQ + Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change. + [1:1] + read-write + + + LIGHT_SLEEP + By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. + + Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request. + [0:0] + read-write + + + + + + + PPB + TEAL registers accessible through the debug interface + 0xe0000000 + + 0 + 274432 + registers + + + + ITM_STIM0 + 0x00000000 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM1 + 0x00000004 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM2 + 0x00000008 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM3 + 0x0000000c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM4 + 0x00000010 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM5 + 0x00000014 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM6 + 0x00000018 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM7 + 0x0000001c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM8 + 0x00000020 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM9 + 0x00000024 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM10 + 0x00000028 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM11 + 0x0000002c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM12 + 0x00000030 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM13 + 0x00000034 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM14 + 0x00000038 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM15 + 0x0000003c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM16 + 0x00000040 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM17 + 0x00000044 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM18 + 0x00000048 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM19 + 0x0000004c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM20 + 0x00000050 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM21 + 0x00000054 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM22 + 0x00000058 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM23 + 0x0000005c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM24 + 0x00000060 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM25 + 0x00000064 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM26 + 0x00000068 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM27 + 0x0000006c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM28 + 0x00000070 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM29 + 0x00000074 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM30 + 0x00000078 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM31 + 0x0000007c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_TER0 + 0x00000e00 + Provide an individual enable bit for each ITM_STIM register + 0x00000000 + + + STIMENA + For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled + [31:0] + read-write + + + + + ITM_TPR + 0x00000e40 + Controls which stimulus ports can be accessed by unprivileged code + 0x00000000 + + + PRIVMASK + Bit mask to enable tracing on ITM stimulus ports + [3:0] + read-write + + + + + ITM_TCR + 0x00000e80 + Configures and controls transfers through the ITM interface + 0x00000000 + + + BUSY + Indicates whether the ITM is currently processing events + [23:23] + read-only + + + TRACEBUSID + Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field + [22:16] + read-write + + + GTSFREQ + Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps + [11:10] + read-write + + + TSPRESCALE + Local timestamp prescaler, used with the trace packet reference clock + [9:8] + read-write + + + STALLENA + Stall the PE to guarantee delivery of Data Trace packets. + [5:5] + read-write + + + SWOENA + Enables asynchronous clocking of the timestamp counter + [4:4] + read-write + + + TXENA + Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU + [3:3] + read-write + + + SYNCENA + Enables Synchronization packet transmission for a synchronous TPIU + [2:2] + read-write + + + TSENA + Enables Local timestamp generation + [1:1] + read-write + + + ITMENA + Enables the ITM + [0:0] + read-write + + + + + INT_ATREADY + 0x00000ef0 + Integration Mode: Read ATB Ready + 0x00000000 + + + AFVALID + A read of this bit returns the value of AFVALID + [1:1] + read-only + + + ATREADY + A read of this bit returns the value of ATREADY + [0:0] + read-only + + + + + INT_ATVALID + 0x00000ef8 + Integration Mode: Write ATB Valid + 0x00000000 + + + AFREADY + A write to this bit gives the value of AFREADY + [1:1] + read-write + + + ATREADY + A write to this bit gives the value of ATVALID + [0:0] + read-write + + + + + ITM_ITCTRL + 0x00000f00 + Integration Mode Control Register + 0x00000000 + + + IME + Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing. + [0:0] + read-write + + + + + ITM_DEVARCH + 0x00000fbc + Provides CoreSight discovery information for the ITM + 0x47701a01 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + ITM_DEVTYPE + 0x00000fcc + Provides CoreSight discovery information for the ITM + 0x00000043 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + ITM_PIDR4 + 0x00000fd0 + Provides CoreSight discovery information for the ITM + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR5 + 0x00000fd4 + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR5 + [31:0] + read-write + + + + + ITM_PIDR6 + 0x00000fd8 + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR6 + [31:0] + read-write + + + + + ITM_PIDR7 + 0x00000fdc + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR7 + [31:0] + read-write + + + + + ITM_PIDR0 + 0x00000fe0 + Provides CoreSight discovery information for the ITM + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_PIDR1 + 0x00000fe4 + Provides CoreSight discovery information for the ITM + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR2 + 0x00000fe8 + Provides CoreSight discovery information for the ITM + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + ITM_PIDR3 + 0x00000fec + Provides CoreSight discovery information for the ITM + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR0 + 0x00000ff0 + Provides CoreSight discovery information for the ITM + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR1 + 0x00000ff4 + Provides CoreSight discovery information for the ITM + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR2 + 0x00000ff8 + Provides CoreSight discovery information for the ITM + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR3 + 0x00000ffc + Provides CoreSight discovery information for the ITM + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CTRL + 0x00001000 + Provides configuration and status information for the DWT unit, and used to control features of the unit + 0x73741824 + + + NUMCOMP + Number of DWT comparators implemented + [31:28] + read-only + + + NOTRCPKT + Indicates whether the implementation does not support trace + [27:27] + read-only + + + NOEXTTRIG + Reserved, RAZ + [26:26] + read-only + + + NOCYCCNT + Indicates whether the implementation does not include a cycle counter + [25:25] + read-only + + + NOPRFCNT + Indicates whether the implementation does not include the profiling counters + [24:24] + read-only + + + CYCDISS + Controls whether the cycle counter is disabled in Secure state + [23:23] + read-write + + + CYCEVTENA + Enables Event Counter packet generation on POSTCNT underflow + [22:22] + read-write + + + FOLDEVTENA + Enables DWT_FOLDCNT counter + [21:21] + read-write + + + LSUEVTENA + Enables DWT_LSUCNT counter + [20:20] + read-write + + + SLEEPEVTENA + Enable DWT_SLEEPCNT counter + [19:19] + read-write + + + EXCEVTENA + Enables DWT_EXCCNT counter + [18:18] + read-write + + + CPIEVTENA + Enables DWT_CPICNT counter + [17:17] + read-write + + + EXTTRCENA + Enables generation of Exception Trace packets + [16:16] + read-write + + + PCSAMPLENA + Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation + [12:12] + read-write + + + SYNCTAP + Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate + [11:10] + read-write + + + CYCTAP + Selects the position of the POSTCNT tap on the CYCCNT counter + [9:9] + read-write + + + POSTINIT + Initial value for the POSTCNT counter + [8:5] + read-write + + + POSTPRESET + Reload value for the POSTCNT counter + [4:1] + read-write + + + CYCCNTENA + Enables CYCCNT + [0:0] + read-write + + + + + DWT_CYCCNT + 0x00001004 + Shows or sets the value of the processor cycle counter, CYCCNT + 0x00000000 + + + CYCCNT + Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero + [31:0] + read-write + + + + + DWT_EXCCNT + 0x0000100c + Counts the total cycles spent in exception processing + 0x00000000 + + + EXCCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_LSUCNT + 0x00001014 + Increments on the additional cycles required to execute all load or store instructions + 0x00000000 + + + LSUCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_FOLDCNT + 0x00001018 + Increments on the additional cycles required to execute all load or store instructions + 0x00000000 + + + FOLDCNT + Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one + [7:0] + read-write + + + + + DWT_COMP0 + 0x00001020 + Provides a reference value for use by watchpoint comparator 0 + 0x00000000 + + + DWT_COMP0 + [31:0] + read-write + + + + + DWT_FUNCTION0 + 0x00001028 + Controls the operation of watchpoint comparator 0 + 0x58000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP1 + 0x00001030 + Provides a reference value for use by watchpoint comparator 1 + 0x00000000 + + + DWT_COMP1 + [31:0] + read-write + + + + + DWT_FUNCTION1 + 0x00001038 + Controls the operation of watchpoint comparator 1 + 0x89000828 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP2 + 0x00001040 + Provides a reference value for use by watchpoint comparator 2 + 0x00000000 + + + DWT_COMP2 + [31:0] + read-write + + + + + DWT_FUNCTION2 + 0x00001048 + Controls the operation of watchpoint comparator 2 + 0x50000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP3 + 0x00001050 + Provides a reference value for use by watchpoint comparator 3 + 0x00000000 + + + DWT_COMP3 + [31:0] + read-write + + + + + DWT_FUNCTION3 + 0x00001058 + Controls the operation of watchpoint comparator 3 + 0x20000800 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_DEVARCH + 0x00001fbc + Provides CoreSight discovery information for the DWT + 0x47701a02 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DWT_DEVTYPE + 0x00001fcc + Provides CoreSight discovery information for the DWT + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + DWT_PIDR4 + 0x00001fd0 + Provides CoreSight discovery information for the DWT + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR5 + 0x00001fd4 + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR5 + [31:0] + read-write + + + + + DWT_PIDR6 + 0x00001fd8 + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR6 + [31:0] + read-write + + + + + DWT_PIDR7 + 0x00001fdc + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR7 + [31:0] + read-write + + + + + DWT_PIDR0 + 0x00001fe0 + Provides CoreSight discovery information for the DWT + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_PIDR1 + 0x00001fe4 + Provides CoreSight discovery information for the DWT + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR2 + 0x00001fe8 + Provides CoreSight discovery information for the DWT + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DWT_PIDR3 + 0x00001fec + Provides CoreSight discovery information for the DWT + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR0 + 0x00001ff0 + Provides CoreSight discovery information for the DWT + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR1 + 0x00001ff4 + Provides CoreSight discovery information for the DWT + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR2 + 0x00001ff8 + Provides CoreSight discovery information for the DWT + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR3 + 0x00001ffc + Provides CoreSight discovery information for the DWT + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CTRL + 0x00002000 + Provides FPB implementation information, and the global enable for the FPB unit + 0x60005580 + + + REV + Flash Patch and Breakpoint Unit architecture revision + [31:28] + read-only + + + NUM_CODE_14_12_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [14:12] + read-only + + + NUM_LIT + Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1 + [11:8] + read-only + + + NUM_CODE_7_4_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [7:4] + read-only + + + KEY + Writes to the FP_CTRL are ignored unless KEY is concurrently written to one + [1:1] + read-write + + + ENABLE + Enables the FPB + [0:0] + read-write + + + + + FP_REMAP + 0x00002004 + Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap + 0x00000000 + + + RMPSPT + Indicates whether the FPB unit supports the Flash Patch remap function + [29:29] + read-only + + + REMAP + Holds the bits[28:5] of the Flash Patch remap address + [28:5] + read-only + + + + + FP_COMP0 + 0x00002008 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP1 + 0x0000200c + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP2 + 0x00002010 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP3 + 0x00002014 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP4 + 0x00002018 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP5 + 0x0000201c + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP6 + 0x00002020 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP7 + 0x00002024 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_DEVARCH + 0x00002fbc + Provides CoreSight discovery information for the FPB + 0x47701a03 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + FP_DEVTYPE + 0x00002fcc + Provides CoreSight discovery information for the FPB + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + FP_PIDR4 + 0x00002fd0 + Provides CoreSight discovery information for the FP + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR5 + 0x00002fd4 + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR5 + [31:0] + read-write + + + + + FP_PIDR6 + 0x00002fd8 + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR6 + [31:0] + read-write + + + + + FP_PIDR7 + 0x00002fdc + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR7 + [31:0] + read-write + + + + + FP_PIDR0 + 0x00002fe0 + Provides CoreSight discovery information for the FP + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_PIDR1 + 0x00002fe4 + Provides CoreSight discovery information for the FP + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR2 + 0x00002fe8 + Provides CoreSight discovery information for the FP + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + FP_PIDR3 + 0x00002fec + Provides CoreSight discovery information for the FP + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR0 + 0x00002ff0 + Provides CoreSight discovery information for the FP + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR1 + 0x00002ff4 + Provides CoreSight discovery information for the FP + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR2 + 0x00002ff8 + Provides CoreSight discovery information for the FP + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR3 + 0x00002ffc + Provides CoreSight discovery information for the FP + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ICTR + 0x0000e004 + Provides information about the interrupt controller + 0x00000001 + + + INTLINESNUM + Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM + [3:0] + read-only + + + + + ACTLR + 0x0000e008 + Provides IMPLEMENTATION DEFINED configuration and control options + 0x00000000 + + + EXTEXCLALL + External Exclusives Allowed with no MPU + [29:29] + read-write + + + DISITMATBFLUSH + Disable ATB Flush + [12:12] + read-write + + + FPEXCODIS + Disable FPU exception outputs + [10:10] + read-write + + + DISOOFP + Disable out-of-order FP instruction completion + [9:9] + read-write + + + DISFOLD + Disable dual-issue. + [2:2] + read-write + + + DISMCYCINT + Disable dual-issue. + [0:0] + read-write + + + + + SYST_CSR + 0x0000e010 + Use the SysTick Control and Status Register to enable the SysTick features. + 0x00000000 + + + COUNTFLAG + Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. + [16:16] + read-only + + + CLKSOURCE + SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. + Selects the SysTick timer clock source: + 0 = External reference clock. + 1 = Processor clock. + [2:2] + read-write + + + TICKINT + Enables SysTick exception request: + 0 = Counting down to zero does not assert the SysTick exception request. + 1 = Counting down to zero to asserts the SysTick exception request. + [1:1] + read-write + + + ENABLE + Enable SysTick counter: + 0 = Counter disabled. + 1 = Counter enabled. + [0:0] + read-write + + + + + SYST_RVR + 0x0000e014 + Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + 0x00000000 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0. + [23:0] + read-write + + + + + SYST_CVR + 0x0000e018 + Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + 0x00000000 + + + CURRENT + Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. + [23:0] + read-write + + + + + SYST_CALIB + 0x0000e01c + Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + 0x00000000 + + + NOREF + If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. + [31:31] + read-only + + + SKEW + If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). + [30:30] + read-only + + + TENMS + An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. + [23:0] + read-only + + + + + NVIC_ISER0 + 0x0000e100 + Enables or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISER1 + 0x0000e104 + Enables or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER0 + 0x0000e180 + Clears or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER1 + 0x0000e184 + Clears or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISPR0 + 0x0000e200 + Enables or reads the pending state of each group of 32 interrupts + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ISPR1 + 0x0000e204 + Enables or reads the pending state of each group of 32 interrupts + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR0 + 0x0000e280 + Clears or reads the pending state of each group of 32 interrupts + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR1 + 0x0000e284 + Clears or reads the pending state of each group of 32 interrupts + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_IABR0 + 0x0000e300 + For each group of 32 interrupts, shows the active state of each interrupt + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IABR1 + 0x0000e304 + For each group of 32 interrupts, shows the active state of each interrupt + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS0 + 0x0000e380 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS1 + 0x0000e384 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IPR0 + 0x0000e400 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR1 + 0x0000e404 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR2 + 0x0000e408 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR3 + 0x0000e40c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR4 + 0x0000e410 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR5 + 0x0000e414 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR6 + 0x0000e418 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR7 + 0x0000e41c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR8 + 0x0000e420 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR9 + 0x0000e424 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR10 + 0x0000e428 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR11 + 0x0000e42c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR12 + 0x0000e430 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR13 + 0x0000e434 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR14 + 0x0000e438 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR15 + 0x0000e43c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + CPUID + 0x0000ed00 + Provides identification information for the PE, including an implementer code for the device and a device ID number + 0x411fd210 + + + IMPLEMENTER + This field must hold an implementer code that has been assigned by ARM + [31:24] + read-only + + + VARIANT + IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product + [23:20] + read-only + + + ARCHITECTURE + Defines the Architecture implemented by the PE + [19:16] + read-only + + + PARTNO + IMPLEMENTATION DEFINED primary part number for the device + [15:4] + read-only + + + REVISION + IMPLEMENTATION DEFINED revision number for the device + [3:0] + read-only + + + + + ICSR + 0x0000ed04 + Controls and provides status information for NMI, PendSV, SysTick and interrupts + 0x00000000 + + + PENDNMISET + Indicates whether the NMI exception is pending + [31:31] + read-only + + + PENDNMICLR + Allows the NMI exception pend state to be cleared + [30:30] + read-write + + + PENDSVSET + Indicates whether the PendSV `FTSSS exception is pending + [28:28] + read-only + + + PENDSVCLR + Allows the PendSV exception pend state to be cleared `FTSSS + [27:27] + read-write + + + PENDSTSET + Indicates whether the SysTick `FTSSS exception is pending + [26:26] + read-only + + + PENDSTCLR + Allows the SysTick exception pend state to be cleared `FTSSS + [25:25] + read-write + + + STTNS + Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure + [24:24] + read-write + + + ISRPREEMPT + Indicates whether a pending exception will be serviced on exit from debug halt state + [23:23] + read-only + + + ISRPENDING + Indicates whether an external interrupt, generated by the NVIC, is pending + [22:22] + read-only + + + VECTPENDING + The exception number of the highest priority pending and enabled interrupt + [20:12] + read-only + + + RETTOBASE + In Handler mode, indicates whether there is more than one active exception + [11:11] + read-only + + + VECTACTIVE + The exception number of the current executing exception + [8:0] + read-only + + + + + VTOR + 0x0000ed08 + The VTOR indicates the offset of the vector table base address from memory address 0x00000000. + 0x00000000 + + + TBLOFF + Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map. + [31:7] + read-write + + + + + AIRCR + 0x0000ed0c + Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + 0x00000000 + + + VECTKEY + Register key: + Reads as Unknown + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + [31:16] + read-write + + + ENDIANESS + Data endianness implemented: + 0 = Little-endian. + [15:15] + read-only + + + PRIS + Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. + 0 Priority ranges of Secure and Non-secure exceptions are identical. + 1 Non-secure exceptions are de-prioritized. + [14:14] + read-write + + + BFHFNMINS + BusFault, HardFault, and NMI Non-secure enable. + 0 BusFault, HardFault, and NMI are Secure. + 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. + [13:13] + read-write + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en + [10:8] + read-write + + + SYSRESETREQS + System reset request, Secure state only. + 0 SYSRESETREQ functionality is available to both Security states. + 1 SYSRESETREQ functionality is only available to Secure state. + [3:3] + read-write + + + SYSRESETREQ + Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. + [2:2] + read-write + + + VECTCLRACTIVE + Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. + [1:1] + read-write + + + + + SCR + 0x0000ed10 + System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + 0x00000000 + + + SEVONPEND + Send Event on Pending bit: + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the + processor is not waiting for an event, the event is registered and affects the next WFE. + The processor also wakes up on execution of an SEV instruction or an external event. + [4:4] + read-write + + + SLEEPDEEPS + 0 SLEEPDEEP is available to both security states + 1 SLEEPDEEP is only available to Secure state + [3:3] + read-write + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode: + 0 = Sleep. + 1 = Deep sleep. + [2:2] + read-write + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode: + 0 = Do not sleep when returning to Thread mode. + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. + [1:1] + read-write + + + + + CCR + 0x0000ed14 + Sets or returns configuration and control data + 0x00000201 + + + BP + Enables program flow prediction `FTSSS + [18:18] + read-only + + + IC + This is a global enable bit for instruction caches in the selected Security state + [17:17] + read-only + + + DC + Enables data caching of all data accesses to Normal memory `FTSSS + [16:16] + read-only + + + STKOFHFNMIGN + Controls the effect of a stack limit violation while executing at a requested priority less than 0 + [10:10] + read-write + + + RES1 + Reserved, RES1 + [9:9] + read-only + + + BFHFNMIGN + Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 + [8:8] + read-write + + + DIV_0_TRP + Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero + [4:4] + read-write + + + UNALIGN_TRP + Controls the trapping of unaligned word or halfword accesses + [3:3] + read-write + + + USERSETMPEND + Determines whether unprivileged accesses are permitted to pend interrupts via the STIR + [1:1] + read-write + + + RES1_1 + Reserved, RES1 + [0:0] + read-only + + + + + SHPR1 + 0x0000ed18 + Sets or returns priority for system handlers 4 - 7 + 0x00000000 + + + PRI_7_3 + Priority of system handler 7, SecureFault + [31:29] + read-write + + + PRI_6_3 + Priority of system handler 6, SecureFault + [23:21] + read-write + + + PRI_5_3 + Priority of system handler 5, SecureFault + [15:13] + read-write + + + PRI_4_3 + Priority of system handler 4, SecureFault + [7:5] + read-write + + + + + SHPR2 + 0x0000ed1c + Sets or returns priority for system handlers 8 - 11 + 0x00000000 + + + PRI_11_3 + Priority of system handler 11, SecureFault + [31:29] + read-write + + + PRI_10 + Reserved, RES0 + [23:16] + read-only + + + PRI_9 + Reserved, RES0 + [15:8] + read-only + + + PRI_8 + Reserved, RES0 + [7:0] + read-only + + + + + SHPR3 + 0x0000ed20 + Sets or returns priority for system handlers 12 - 15 + 0x00000000 + + + PRI_15_3 + Priority of system handler 15, SecureFault + [31:29] + read-write + + + PRI_14_3 + Priority of system handler 14, SecureFault + [23:21] + read-write + + + PRI_13 + Reserved, RES0 + [15:8] + read-only + + + PRI_12_3 + Priority of system handler 12, SecureFault + [7:5] + read-write + + + + + SHCSR + 0x0000ed24 + Provides access to the active and pending status of system exceptions + 0x00000000 + + + HARDFAULTPENDED + `IAAMO the pending state of the HardFault exception `CTTSSS + [21:21] + read-write + + + SECUREFAULTPENDED + `IAAMO the pending state of the SecureFault exception + [20:20] + read-write + + + SECUREFAULTENA + `DW the SecureFault exception is enabled + [19:19] + read-write + + + USGFAULTENA + `DW the UsageFault exception is enabled `FTSSS + [18:18] + read-write + + + BUSFAULTENA + `DW the BusFault exception is enabled + [17:17] + read-write + + + MEMFAULTENA + `DW the MemManage exception is enabled `FTSSS + [16:16] + read-write + + + SVCALLPENDED + `IAAMO the pending state of the SVCall exception `FTSSS + [15:15] + read-write + + + BUSFAULTPENDED + `IAAMO the pending state of the BusFault exception + [14:14] + read-write + + + MEMFAULTPENDED + `IAAMO the pending state of the MemManage exception `FTSSS + [13:13] + read-write + + + USGFAULTPENDED + The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS + [12:12] + read-write + + + SYSTICKACT + `IAAMO the active state of the SysTick exception `FTSSS + [11:11] + read-write + + + PENDSVACT + `IAAMO the active state of the PendSV exception `FTSSS + [10:10] + read-write + + + MONITORACT + `IAAMO the active state of the DebugMonitor exception + [8:8] + read-write + + + SVCALLACT + `IAAMO the active state of the SVCall exception `FTSSS + [7:7] + read-write + + + NMIACT + `IAAMO the active state of the NMI exception + [5:5] + read-write + + + SECUREFAULTACT + `IAAMO the active state of the SecureFault exception + [4:4] + read-write + + + USGFAULTACT + `IAAMO the active state of the UsageFault exception `FTSSS + [3:3] + read-write + + + HARDFAULTACT + Indicates and allows limited modification of the active state of the HardFault exception `FTSSS + [2:2] + read-write + + + BUSFAULTACT + `IAAMO the active state of the BusFault exception + [1:1] + read-write + + + MEMFAULTACT + `IAAMO the active state of the MemManage exception `FTSSS + [0:0] + read-write + + + + + CFSR + 0x0000ed28 + Contains the three Configurable Fault Status Registers. + + 31:16 UFSR: Provides information on UsageFault exceptions + + 15:8 BFSR: Provides information on BusFault exceptions + + 7:0 MMFSR: Provides information on MemManage exceptions + 0x00000000 + + + UFSR_DIVBYZERO + Sticky flag indicating whether an integer division by zero error has occurred + [25:25] + read-write + + + UFSR_UNALIGNED + Sticky flag indicating whether an unaligned access error has occurred + [24:24] + read-write + + + UFSR_STKOF + Sticky flag indicating whether a stack overflow error has occurred + [20:20] + read-write + + + UFSR_NOCP + Sticky flag indicating whether a coprocessor disabled or not present error has occurred + [19:19] + read-write + + + UFSR_INVPC + Sticky flag indicating whether an integrity check error has occurred + [18:18] + read-write + + + UFSR_INVSTATE + Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred + [17:17] + read-write + + + UFSR_UNDEFINSTR + Sticky flag indicating whether an undefined instruction error has occurred + [16:16] + read-write + + + BFSR_BFARVALID + Indicates validity of the contents of the BFAR register + [15:15] + read-write + + + BFSR_LSPERR + Records whether a BusFault occurred during FP lazy state preservation + [13:13] + read-write + + + BFSR_STKERR + Records whether a derived BusFault occurred during exception entry stacking + [12:12] + read-write + + + BFSR_UNSTKERR + Records whether a derived BusFault occurred during exception return unstacking + [11:11] + read-write + + + BFSR_IMPRECISERR + Records whether an imprecise data access error has occurred + [10:10] + read-write + + + BFSR_PRECISERR + Records whether a precise data access error has occurred + [9:9] + read-write + + + BFSR_IBUSERR + Records whether a BusFault on an instruction prefetch has occurred + [8:8] + read-write + + + MMFSR + Provides information on MemManage exceptions + [7:0] + read-write + + + + + HFSR + 0x0000ed2c + Shows the cause of any HardFaults + 0x00000000 + + + DEBUGEVT + Indicates when a Debug event has occurred + [31:31] + read-write + + + FORCED + Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled + [30:30] + read-write + + + VECTTBL + Indicates when a fault has occurred because of a vector table read error on exception processing + [1:1] + read-write + + + + + DFSR + 0x0000ed30 + Shows which debug event occurred + 0x00000000 + + + EXTERNAL + Sticky flag indicating whether an External debug request debug event has occurred + [4:4] + read-write + + + VCATCH + Sticky flag indicating whether a Vector catch debug event has occurred + [3:3] + read-write + + + DWTTRAP + Sticky flag indicating whether a Watchpoint debug event has occurred + [2:2] + read-write + + + BKPT + Sticky flag indicating whether a Breakpoint debug event has occurred + [1:1] + read-write + + + HALTED + Sticky flag indicating that a Halt request debug event or Step debug event has occurred + [0:0] + read-write + + + + + MMFAR + 0x0000ed34 + Shows the address of the memory location that caused an MPU fault + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + BFAR + 0x0000ed38 + Shows the address associated with a precise data access BusFault + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + ID_PFR0 + 0x0000ed40 + Gives top-level information about the instruction set supported by the PE + 0x00000030 + + + STATE1 + T32 instruction set support + [7:4] + read-only + + + STATE0 + A32 instruction set support + [3:0] + read-only + + + + + ID_PFR1 + 0x0000ed44 + Gives information about the programmers' model and Extensions support + 0x00000520 + + + MPROGMOD + Identifies support for the M-Profile programmers' model support + [11:8] + read-only + + + SECURITY + Identifies whether the Security Extension is implemented + [7:4] + read-only + + + + + ID_DFR0 + 0x0000ed48 + Provides top level information about the debug system + 0x00200000 + + + MPROFDBG + Indicates the supported M-profile debug architecture + [23:20] + read-only + + + + + ID_AFR0 + 0x0000ed4c + Provides information about the IMPLEMENTATION DEFINED features of the PE + 0x00000000 + + + IMPDEF3 + IMPLEMENTATION DEFINED meaning + [15:12] + read-only + + + IMPDEF2 + IMPLEMENTATION DEFINED meaning + [11:8] + read-only + + + IMPDEF1 + IMPLEMENTATION DEFINED meaning + [7:4] + read-only + + + IMPDEF0 + IMPLEMENTATION DEFINED meaning + [3:0] + read-only + + + + + ID_MMFR0 + 0x0000ed50 + Provides information about the implemented memory model and memory management support + 0x00101f40 + + + AUXREG + Indicates support for Auxiliary Control Registers + [23:20] + read-only + + + TCM + Indicates support for tightly coupled memories (TCMs) + [19:16] + read-only + + + SHARELVL + Indicates the number of shareability levels implemented + [15:12] + read-only + + + OUTERSHR + Indicates the outermost shareability domain implemented + [11:8] + read-only + + + PMSA + Indicates support for the protected memory system architecture (PMSA) + [7:4] + read-only + + + + + ID_MMFR1 + 0x0000ed54 + Provides information about the implemented memory model and memory management support + 0x00000000 + + + ID_MMFR1 + [31:0] + read-write + + + + + ID_MMFR2 + 0x0000ed58 + Provides information about the implemented memory model and memory management support + 0x01000000 + + + WFISTALL + Indicates the support for Wait For Interrupt (WFI) stalling + [27:24] + read-only + + + + + ID_MMFR3 + 0x0000ed5c + Provides information about the implemented memory model and memory management support + 0x00000000 + + + BPMAINT + Indicates the supported branch predictor maintenance + [11:8] + read-only + + + CMAINTSW + Indicates the supported cache maintenance operations by set/way + [7:4] + read-only + + + CMAINTVA + Indicates the supported cache maintenance operations by address + [3:0] + read-only + + + + + ID_ISAR0 + 0x0000ed60 + Provides information about the instruction set implemented by the PE + 0x08092300 + + + DIVIDE + Indicates the supported Divide instructions + [27:24] + read-only + + + DEBUG + Indicates the implemented Debug instructions + [23:20] + read-only + + + COPROC + Indicates the supported Coprocessor instructions + [19:16] + read-only + + + CMPBRANCH + Indicates the supported combined Compare and Branch instructions + [15:12] + read-only + + + BITFIELD + Indicates the supported bit field instructions + [11:8] + read-only + + + BITCOUNT + Indicates the supported bit count instructions + [7:4] + read-only + + + + + ID_ISAR1 + 0x0000ed64 + Provides information about the instruction set implemented by the PE + 0x05725000 + + + INTERWORK + Indicates the implemented Interworking instructions + [27:24] + read-only + + + IMMEDIATE + Indicates the implemented for data-processing instructions with long immediates + [23:20] + read-only + + + IFTHEN + Indicates the implemented If-Then instructions + [19:16] + read-only + + + EXTEND + Indicates the implemented Extend instructions + [15:12] + read-only + + + + + ID_ISAR2 + 0x0000ed68 + Provides information about the instruction set implemented by the PE + 0x30173426 + + + REVERSAL + Indicates the implemented Reversal instructions + [31:28] + read-only + + + MULTU + Indicates the implemented advanced unsigned Multiply instructions + [23:20] + read-only + + + MULTS + Indicates the implemented advanced signed Multiply instructions + [19:16] + read-only + + + MULT + Indicates the implemented additional Multiply instructions + [15:12] + read-only + + + MULTIACCESSINT + Indicates the support for interruptible multi-access instructions + [11:8] + read-only + + + MEMHINT + Indicates the implemented Memory Hint instructions + [7:4] + read-only + + + LOADSTORE + Indicates the implemented additional load/store instructions + [3:0] + read-only + + + + + ID_ISAR3 + 0x0000ed6c + Provides information about the instruction set implemented by the PE + 0x07895729 + + + TRUENOP + Indicates the implemented true NOP instructions + [27:24] + read-only + + + T32COPY + Indicates the support for T32 non flag-setting MOV instructions + [23:20] + read-only + + + TABBRANCH + Indicates the implemented Table Branch instructions + [19:16] + read-only + + + SYNCHPRIM + Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions + [15:12] + read-only + + + SVC + Indicates the implemented SVC instructions + [11:8] + read-only + + + SIMD + Indicates the implemented SIMD instructions + [7:4] + read-only + + + SATURATE + Indicates the implemented saturating instructions + [3:0] + read-only + + + + + ID_ISAR4 + 0x0000ed70 + Provides information about the instruction set implemented by the PE + 0x01310132 + + + PSR_M + Indicates the implemented M profile instructions to modify the PSRs + [27:24] + read-only + + + SYNCPRIM_FRAC + Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions + [23:20] + read-only + + + BARRIER + Indicates the implemented Barrier instructions + [19:16] + read-only + + + WRITEBACK + Indicates the support for writeback addressing modes + [11:8] + read-only + + + WITHSHIFTS + Indicates the support for writeback addressing modes + [7:4] + read-only + + + UNPRIV + Indicates the implemented unprivileged instructions + [3:0] + read-only + + + + + ID_ISAR5 + 0x0000ed74 + Provides information about the instruction set implemented by the PE + 0x00000000 + + + ID_ISAR5 + [31:0] + read-write + + + + + CTR + 0x0000ed7c + Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. + 0x8000c000 + + + RES1 + Reserved, RES1 + [31:31] + read-only + + + CWG + Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified + [27:24] + read-only + + + ERG + Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions + [23:20] + read-only + + + DMINLINE + Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE + [19:16] + read-only + + + RES1_1 + Reserved, RES1 + [15:14] + read-only + + + IMINLINE + Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE + [3:0] + read-only + + + + + CPACR + 0x0000ed88 + Specifies the access privileges for coprocessors and the FP Extension + 0x00000000 + + + CP11 + The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN + [23:22] + read-write + + + CP10 + Defines the access rights for the floating-point functionality + [21:20] + read-write + + + CP7 + Controls access privileges for coprocessor 7 + [15:14] + read-write + + + CP6 + Controls access privileges for coprocessor 6 + [13:12] + read-write + + + CP5 + Controls access privileges for coprocessor 5 + [11:10] + read-write + + + CP4 + Controls access privileges for coprocessor 4 + [9:8] + read-write + + + CP3 + Controls access privileges for coprocessor 3 + [7:6] + read-write + + + CP2 + Controls access privileges for coprocessor 2 + [5:4] + read-write + + + CP1 + Controls access privileges for coprocessor 1 + [3:2] + read-write + + + CP0 + Controls access privileges for coprocessor 0 + [1:0] + read-write + + + + + NSACR + 0x0000ed8c + Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + 0x00000000 + + + CP11 + Enables Non-secure access to the Floating-point Extension + [11:11] + read-write + + + CP10 + Enables Non-secure access to the Floating-point Extension + [10:10] + read-write + + + CP7 + Enables Non-secure access to coprocessor CP7 + [7:7] + read-write + + + CP6 + Enables Non-secure access to coprocessor CP6 + [6:6] + read-write + + + CP5 + Enables Non-secure access to coprocessor CP5 + [5:5] + read-write + + + CP4 + Enables Non-secure access to coprocessor CP4 + [4:4] + read-write + + + CP3 + Enables Non-secure access to coprocessor CP3 + [3:3] + read-write + + + CP2 + Enables Non-secure access to coprocessor CP2 + [2:2] + read-write + + + CP1 + Enables Non-secure access to coprocessor CP1 + [1:1] + read-write + + + CP0 + Enables Non-secure access to coprocessor CP0 + [0:0] + read-write + + + + + MPU_TYPE + 0x0000ed90 + The MPU Type Register indicates how many regions the MPU `FTSSS supports + 0x00000800 + + + DREGION + Number of regions supported by the MPU + [15:8] + read-only + + + SEPARATE + Indicates support for separate instructions and data address regions + [0:0] + read-only + + + + + MPU_CTRL + 0x0000ed94 + Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + 0x00000000 + + + PRIVDEFENA + Controls whether the default memory map is enabled for privileged software + [2:2] + read-write + + + HFNMIENA + Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + [1:1] + read-write + + + ENABLE + Enables the MPU + [0:0] + read-write + + + + + MPU_RNR + 0x0000ed98 + Selects the region currently accessed by MPU_RBAR and MPU_RLAR + 0x00000000 + + + REGION + Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + [2:0] + read-write + + + + + MPU_RBAR + 0x0000ed9c + Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR + 0x0000eda0 + Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A1 + 0x0000eda4 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A1 + 0x0000eda8 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A2 + 0x0000edac + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A2 + 0x0000edb0 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A3 + 0x0000edb4 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A3 + 0x0000edb8 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_MAIR0 + 0x0000edc0 + Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + 0x00000000 + + + ATTR3 + Memory attribute encoding for MPU regions with an AttrIndex of 3 + [31:24] + read-write + + + ATTR2 + Memory attribute encoding for MPU regions with an AttrIndex of 2 + [23:16] + read-write + + + ATTR1 + Memory attribute encoding for MPU regions with an AttrIndex of 1 + [15:8] + read-write + + + ATTR0 + Memory attribute encoding for MPU regions with an AttrIndex of 0 + [7:0] + read-write + + + + + MPU_MAIR1 + 0x0000edc4 + Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values + 0x00000000 + + + ATTR7 + Memory attribute encoding for MPU regions with an AttrIndex of 7 + [31:24] + read-write + + + ATTR6 + Memory attribute encoding for MPU regions with an AttrIndex of 6 + [23:16] + read-write + + + ATTR5 + Memory attribute encoding for MPU regions with an AttrIndex of 5 + [15:8] + read-write + + + ATTR4 + Memory attribute encoding for MPU regions with an AttrIndex of 4 + [7:0] + read-write + + + + + SAU_CTRL + 0x0000edd0 + Allows enabling of the Security Attribution Unit + 0x00000000 + + + ALLNS + When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure + [1:1] + read-write + + + ENABLE + Enables the SAU + [0:0] + read-write + + + + + SAU_TYPE + 0x0000edd4 + Indicates the number of regions implemented by the Security Attribution Unit + 0x00000008 + + + SREGION + The number of implemented SAU regions + [7:0] + read-only + + + + + SAU_RNR + 0x0000edd8 + Selects the region currently accessed by SAU_RBAR and SAU_RLAR + 0x00000000 + + + REGION + Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + [7:0] + read-write + + + + + SAU_RBAR + 0x0000eddc + Provides indirect read and write access to the base address of the currently selected SAU region + 0x00000000 + + + BADDR + Holds bits [31:5] of the base address for the selected SAU region + [31:5] + read-write + + + + + SAU_RLAR + 0x0000ede0 + Provides indirect read and write access to the limit address of the currently selected SAU region + 0x00000000 + + + LADDR + Holds bits [31:5] of the limit address for the selected SAU region + [31:5] + read-write + + + NSC + Controls whether Non-secure state is permitted to execute an SG instruction from this region + [1:1] + read-write + + + ENABLE + SAU region enable + [0:0] + read-write + + + + + SFSR + 0x0000ede4 + Provides information about any security related faults + 0x00000000 + + + LSERR + Sticky flag indicating that an error occurred during lazy state activation or deactivation + [7:7] + read-write + + + SFARVALID + This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault + [6:6] + read-write + + + LSPERR + Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state + [5:5] + read-write + + + INVTRAN + Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory + [4:4] + read-write + + + AUVIOL + Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR + [3:3] + read-write + + + INVER + This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state + [2:2] + read-write + + + INVIS + This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation + [1:1] + read-write + + + INVEP + This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set + [0:0] + read-write + + + + + SFAR + 0x0000ede8 + Shows the address of the memory location that caused a Security violation + 0x00000000 + + + ADDRESS + The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state + [31:0] + read-write + + + + + DHCSR + 0x0000edf0 + Controls halting debug + 0x00000000 + + + S_RESTART_ST + Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request + [26:26] + read-only + + + S_RESET_ST + Indicates whether the PE has been reset since the last read of the DHCSR + [25:25] + read-only + + + S_RETIRE_ST + Set to 1 every time the PE retires one of more instructions + [24:24] + read-only + + + S_SDE + Indicates whether Secure invasive debug is allowed + [20:20] + read-only + + + S_LOCKUP + Indicates whether the PE is in Lockup state + [19:19] + read-only + + + S_SLEEP + Indicates whether the PE is sleeping + [18:18] + read-only + + + S_HALT + Indicates whether the PE is in Debug state + [17:17] + read-only + + + S_REGRDY + Handshake flag to transfers through the DCRDR + [16:16] + read-only + + + C_SNAPSTALL + Allow imprecise entry to Debug state + [5:5] + read-write + + + C_MASKINTS + When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts + [3:3] + read-write + + + C_STEP + Enable single instruction step + [2:2] + read-write + + + C_HALT + PE enter Debug state halt request + [1:1] + read-write + + + C_DEBUGEN + Enable Halting debug + [0:0] + read-write + + + + + DCRSR + 0x0000edf4 + With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer + 0x00000000 + + + REGWNR + Specifies the access type for the transfer + [16:16] + read-write + + + REGSEL + Specifies the general-purpose register, special-purpose register, or FP register to transfer + [6:0] + read-write + + + + + DCRDR + 0x0000edf8 + With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE + 0x00000000 + + + DBGTMP + Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers + [31:0] + read-write + + + + + DEMCR + 0x0000edfc + Manages vector catch behavior and DebugMonitor handling when debugging + 0x00000000 + + + TRCENA + Global enable for all DWT and ITM features + [24:24] + read-write + + + SDME + Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state + [20:20] + read-only + + + MON_REQ + DebugMonitor semaphore bit + [19:19] + read-write + + + MON_STEP + Enable DebugMonitor stepping + [18:18] + read-write + + + MON_PEND + Sets or clears the pending state of the DebugMonitor exception + [17:17] + read-write + + + MON_EN + Enable the DebugMonitor exception + [16:16] + read-write + + + VC_SFERR + SecureFault exception halting debug vector catch enable + [11:11] + read-write + + + VC_HARDERR + HardFault exception halting debug vector catch enable + [10:10] + read-write + + + VC_INTERR + Enable halting debug vector catch for faults during exception entry and return + [9:9] + read-write + + + VC_BUSERR + BusFault exception halting debug vector catch enable + [8:8] + read-write + + + VC_STATERR + Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception + [7:7] + read-write + + + VC_CHKERR + Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error + [6:6] + read-write + + + VC_NOCPERR + Enable halting debug trap on a UsageFault caused by an access to a coprocessor + [5:5] + read-write + + + VC_MMERR + Enable halting debug trap on a MemManage exception + [4:4] + read-write + + + VC_CORERESET + Enable Reset Vector Catch. This causes a warm reset to halt a running system + [0:0] + read-write + + + + + DSCSR + 0x0000ee08 + Provides control and status information for Secure debug + 0x00000000 + + + CDSKEY + Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero + [17:17] + read-write + + + CDS + This field indicates the current Security state of the processor + [16:16] + read-write + + + SBRSEL + If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger + [1:1] + read-write + + + SBRSELEN + Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger + [0:0] + read-write + + + + + STIR + 0x0000ef00 + Provides a mechanism for software to generate an interrupt + 0x00000000 + + + INTID + Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) + [8:0] + read-write + + + + + FPCCR + 0x0000ef34 + Holds control data for the Floating-point extension + 0x20000472 + + + ASPEN + When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1 + [31:31] + read-write + + + LSPEN + Enables lazy context save of floating-point state + [30:30] + read-write + + + LSPENS + This bit controls whether the LSPEN bit is writeable from the Non-secure state + [29:29] + read-write + + + CLRONRET + Clear floating-point caller saved registers on exception return + [28:28] + read-write + + + CLRONRETS + This bit controls whether the CLRONRET bit is writeable from the Non-secure state + [27:27] + read-write + + + TS + Treat floating-point registers as Secure enable + [26:26] + read-write + + + UFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending + [10:10] + read-write + + + SPLIMVIOL + This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior + [9:9] + read-write + + + MONRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending + [8:8] + read-write + + + SFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state + [7:7] + read-write + + + BFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending + [6:6] + read-write + + + MMRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending + [5:5] + read-write + + + HFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending + [4:4] + read-write + + + THREAD + Indicates the PE mode when it allocated the floating-point stack frame + [3:3] + read-write + + + S + Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed + [2:2] + read-write + + + USER + Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame + [1:1] + read-write + + + LSPACT + Indicates whether lazy preservation of the floating-point state is active + [0:0] + read-write + + + + + FPCAR + 0x0000ef38 + Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + 0x00000000 + + + ADDRESS + The location of the unpopulated floating-point register space allocated on an exception stack frame + [31:3] + read-write + + + + + FPDSCR + 0x0000ef3c + Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context + 0x00000000 + + + AHP + Default value for FPSCR.AHP + [26:26] + read-write + + + DN + Default value for FPSCR.DN + [25:25] + read-write + + + FZ + Default value for FPSCR.FZ + [24:24] + read-write + + + RMODE + Default value for FPSCR.RMode + [23:22] + read-write + + + + + MVFR0 + 0x0000ef40 + Describes the features provided by the Floating-point Extension + 0x60540601 + + + FPROUND + Indicates the rounding modes supported by the FP Extension + [31:28] + read-only + + + FPSQRT + Indicates the support for FP square root operations + [23:20] + read-only + + + FPDIVIDE + Indicates the support for FP divide operations + [19:16] + read-only + + + FPDP + Indicates support for FP double-precision operations + [11:8] + read-only + + + FPSP + Indicates support for FP single-precision operations + [7:4] + read-only + + + SIMDREG + Indicates size of FP register file + [3:0] + read-only + + + + + MVFR1 + 0x0000ef44 + Describes the features provided by the Floating-point Extension + 0x85000089 + + + FMAC + Indicates whether the FP Extension implements the fused multiply accumulate instructions + [31:28] + read-only + + + FPHP + Indicates whether the FP Extension implements half-precision FP conversion instructions + [27:24] + read-only + + + FPDNAN + Indicates whether the FP hardware implementation supports NaN propagation + [7:4] + read-only + + + FPFTZ + Indicates whether subnormals are always flushed-to-zero + [3:0] + read-only + + + + + MVFR2 + 0x0000ef48 + Describes the features provided by the Floating-point Extension + 0x00000060 + + + FPMISC + Indicates support for miscellaneous FP features + [7:4] + read-only + + + + + DDEVARCH + 0x0000efbc + Provides CoreSight discovery information for the SCS + 0x47702a04 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DDEVTYPE + 0x0000efcc + Provides CoreSight discovery information for the SCS + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + CoreSight major type + [3:0] + read-only + + + + + DPIDR4 + 0x0000efd0 + Provides CoreSight discovery information for the SCS + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR5 + 0x0000efd4 + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR5 + [31:0] + read-write + + + + + DPIDR6 + 0x0000efd8 + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR6 + [31:0] + read-write + + + + + DPIDR7 + 0x0000efdc + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR7 + [31:0] + read-write + + + + + DPIDR0 + 0x0000efe0 + Provides CoreSight discovery information for the SCS + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DPIDR1 + 0x0000efe4 + Provides CoreSight discovery information for the SCS + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR2 + 0x0000efe8 + Provides CoreSight discovery information for the SCS + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DPIDR3 + 0x0000efec + Provides CoreSight discovery information for the SCS + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR0 + 0x0000eff0 + Provides CoreSight discovery information for the SCS + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR1 + 0x0000eff4 + Provides CoreSight discovery information for the SCS + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR2 + 0x0000eff8 + Provides CoreSight discovery information for the SCS + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR3 + 0x0000effc + Provides CoreSight discovery information for the SCS + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + TRCPRGCTLR + 0x00041004 + Programming Control Register + 0x00000000 + + + EN + Trace Unit Enable + [0:0] + read-write + + + + + TRCSTATR + 0x0004100c + The TRCSTATR indicates the ETM-Teal status + 0x00000000 + + + PMSTABLE + Indicates whether the ETM-Teal registers are stable and can be read + [1:1] + read-only + + + IDLE + Indicates that the trace unit is inactive + [0:0] + read-only + + + + + TRCCONFIGR + 0x00041010 + The TRCCONFIGR sets the basic tracing options for the trace unit + 0x00000000 + + + RS + Return stack enable + [12:12] + read-write + + + TS + Global timestamp tracing + [11:11] + read-write + + + COND + Conditional instruction tracing + [10:5] + read-write + + + CCI + Cycle counting in instruction trace + [4:4] + read-write + + + BB + Branch broadcast mode + [3:3] + read-write + + + + + TRCEVENTCTL0R + 0x00041020 + The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. + 0x00000000 + + + TYPE1 + Selects the resource type for event 1 + [15:15] + read-write + + + SEL1 + Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0] + [10:8] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [2:0] + read-write + + + + + TRCEVENTCTL1R + 0x00041024 + The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + 0x00000000 + + + LPOVERRIDE + Low power state behavior override + [12:12] + read-write + + + ATB + ATB enabled + [11:11] + read-write + + + INSTEN1 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [1:1] + read-write + + + INSTEN0 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [0:0] + read-write + + + + + TRCSTALLCTLR + 0x0004102c + The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow + 0x00000000 + + + INSTPRIORITY + Reserved, RES0 + [10:10] + read-only + + + ISTALL + Stall processor based on instruction trace buffer space + [8:8] + read-write + + + LEVEL + Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow + [3:2] + read-write + + + + + TRCTSCTLR + 0x00041030 + The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream + 0x00000000 + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCSYNCPR + 0x00041034 + The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two + 0x0000000a + + + PERIOD + Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes + [4:0] + read-only + + + + + TRCCCCTLR + 0x00041038 + The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets + 0x00000000 + + + THRESHOLD + Instruction trace cycle count threshold + [11:0] + read-write + + + + + TRCVICTLR + 0x00041080 + The TRCVICTLR controls instruction trace filtering + 0x00000000 + + + EXLEVEL_S3 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [19:19] + read-write + + + EXLEVEL_S0 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [16:16] + read-write + + + TRCERR + Selects whether a system error exception must always be traced + [11:11] + read-write + + + TRCRESET + Selects whether a reset exception must always be traced + [10:10] + read-write + + + SSSTATUS + Indicates the current status of the start/stop logic + [9:9] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCCNTRLDVR0 + 0x00041140 + The TRCCNTRLDVR defines the reload value for the reduced function counter + 0x00000000 + + + VALUE + Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs + [15:0] + read-write + + + + + TRCIDR8 + 0x00041180 + TRCIDR8 + 0x00000000 + + + MAXSPEC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR9 + 0x00041184 + TRCIDR9 + 0x00000000 + + + NUMP0KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR10 + 0x00041188 + TRCIDR10 + 0x00000000 + + + NUMP1KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR11 + 0x0004118c + TRCIDR11 + 0x00000000 + + + NUMP1SPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR12 + 0x00041190 + TRCIDR12 + 0x00000001 + + + NUMCONDKEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR13 + 0x00041194 + TRCIDR13 + 0x00000000 + + + NUMCONDSPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIMSPEC + 0x000411c0 + The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided + 0x00000000 + + + SUPPORT + Reserved, RES0 + [3:0] + read-only + + + + + TRCIDR0 + 0x000411e0 + TRCIDR0 + 0x280006e1 + + + COMMOPT + reads as `ImpDef + [29:29] + read-only + + + TSSIZE + reads as `ImpDef + [28:24] + read-only + + + TRCEXDATA + reads as `ImpDef + [17:17] + read-only + + + QSUPP + reads as `ImpDef + [16:15] + read-only + + + QFILT + reads as `ImpDef + [14:14] + read-only + + + CONDTYPE + reads as `ImpDef + [13:12] + read-only + + + NUMEVENT + reads as `ImpDef + [11:10] + read-only + + + RETSTACK + reads as `ImpDef + [9:9] + read-only + + + TRCCCI + reads as `ImpDef + [7:7] + read-only + + + TRCCOND + reads as `ImpDef + [6:6] + read-only + + + TRCBB + reads as `ImpDef + [5:5] + read-only + + + TRCDATA + reads as `ImpDef + [4:3] + read-only + + + INSTP0 + reads as `ImpDef + [2:1] + read-only + + + RES1 + Reserved, RES1 + [0:0] + read-only + + + + + TRCIDR1 + 0x000411e4 + TRCIDR1 + 0x4100f421 + + + DESIGNER + reads as `ImpDef + [31:24] + read-only + + + RES1 + Reserved, RES1 + [15:12] + read-only + + + TRCARCHMAJ + reads as 0b0100 + [11:8] + read-only + + + TRCARCHMIN + reads as 0b0000 + [7:4] + read-only + + + REVISION + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR2 + 0x000411e8 + TRCIDR2 + 0x00000004 + + + CCSIZE + reads as `ImpDef + [28:25] + read-only + + + DVSIZE + reads as `ImpDef + [24:20] + read-only + + + DASIZE + reads as `ImpDef + [19:15] + read-only + + + VMIDSIZE + reads as `ImpDef + [14:10] + read-only + + + CIDSIZE + reads as `ImpDef + [9:5] + read-only + + + IASIZE + reads as `ImpDef + [4:0] + read-only + + + + + TRCIDR3 + 0x000411ec + TRCIDR3 + 0x0f090004 + + + NOOVERFLOW + reads as `ImpDef + [31:31] + read-only + + + NUMPROC + reads as `ImpDef + [30:28] + read-only + + + SYSSTALL + reads as `ImpDef + [27:27] + read-only + + + STALLCTL + reads as `ImpDef + [26:26] + read-only + + + SYNCPR + reads as `ImpDef + [25:25] + read-only + + + TRCERR + reads as `ImpDef + [24:24] + read-only + + + EXLEVEL_NS + reads as `ImpDef + [23:20] + read-only + + + EXLEVEL_S + reads as `ImpDef + [19:16] + read-only + + + CCITMIN + reads as `ImpDef + [11:0] + read-only + + + + + TRCIDR4 + 0x000411f0 + TRCIDR4 + 0x00114000 + + + NUMVMIDC + reads as `ImpDef + [31:28] + read-only + + + NUMCIDC + reads as `ImpDef + [27:24] + read-only + + + NUMSSCC + reads as `ImpDef + [23:20] + read-only + + + NUMRSPAIR + reads as `ImpDef + [19:16] + read-only + + + NUMPC + reads as `ImpDef + [15:12] + read-only + + + SUPPDAC + reads as `ImpDef + [8:8] + read-only + + + NUMDVC + reads as `ImpDef + [7:4] + read-only + + + NUMACPAIRS + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR5 + 0x000411f4 + TRCIDR5 + 0x90c70004 + + + REDFUNCNTR + reads as `ImpDef + [31:31] + read-only + + + NUMCNTR + reads as `ImpDef + [30:28] + read-only + + + NUMSEQSTATE + reads as `ImpDef + [27:25] + read-only + + + LPOVERRIDE + reads as `ImpDef + [23:23] + read-only + + + ATBTRIG + reads as `ImpDef + [22:22] + read-only + + + TRACEIDSIZE + reads as 0x07 + [21:16] + read-only + + + NUMEXTINSEL + reads as `ImpDef + [11:9] + read-only + + + NUMEXTIN + reads as `ImpDef + [8:0] + read-only + + + + + TRCIDR6 + 0x000411f8 + TRCIDR6 + 0x00000000 + + + TRCIDR6 + [31:0] + read-write + + + + + TRCIDR7 + 0x000411fc + TRCIDR7 + 0x00000000 + + + TRCIDR7 + [31:0] + read-write + + + + + TRCRSCTLR2 + 0x00041208 + The TRCRSCTLR controls the trace resources + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCRSCTLR3 + 0x0004120c + The TRCRSCTLR controls the trace resources + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCSSCSR + 0x000412a0 + Controls the corresponding single-shot comparator resource + 0x00000000 + + + STATUS + Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched + [31:31] + read-write + + + PC + Reserved, RES1 + [3:3] + read-only + + + DV + Reserved, RES0 + [2:2] + read-only + + + DA + Reserved, RES0 + [1:1] + read-only + + + INST + Reserved, RES0 + [0:0] + read-only + + + + + TRCSSPCICR + 0x000412c0 + Selects the PE comparator inputs for Single-shot control + 0x00000000 + + + PC + Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control + [3:0] + read-write + + + + + TRCPDCR + 0x00041310 + Requests the system to provide power to the trace unit + 0x00000000 + + + PU + Powerup request bit: + [3:3] + read-write + + + + + TRCPDSR + 0x00041314 + Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status + 0x00000003 + + + OSLK + OS Lock status bit: + [5:5] + read-only + + + STICKYPD + Sticky powerdown status bit. Indicates whether the trace register state is valid: + [1:1] + read-only + + + POWER + Power status bit: + [0:0] + read-only + + + + + TRCITATBIDR + 0x00041ee4 + Trace Integration ATB Identification Register + 0x00000000 + + + ID + Trace ID + [6:0] + read-write + + + + + TRCITIATBINR + 0x00041ef4 + Trace Integration Instruction ATB In Register + 0x00000000 + + + AFVALIDM + Integration Mode instruction AFVALIDM in + [1:1] + read-write + + + ATREADYM + Integration Mode instruction ATREADYM in + [0:0] + read-write + + + + + TRCITIATBOUTR + 0x00041efc + Trace Integration Instruction ATB Out Register + 0x00000000 + + + AFREADY + Integration Mode instruction AFREADY out + [1:1] + read-write + + + ATVALID + Integration Mode instruction ATVALID out + [0:0] + read-write + + + + + TRCCLAIMSET + 0x00041fa0 + Claim Tag Set Register + 0x0000000f + + + SET3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + SET2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + SET1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + SET0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCCLAIMCLR + 0x00041fa4 + Claim Tag Clear Register + 0x00000000 + + + CLR3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + CLR2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + CLR1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + CLR0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCAUTHSTATUS + 0x00041fb8 + Returns the level of tracing that the trace unit can support + 0x00000000 + + + SNID + Indicates whether the system enables the trace unit to support Secure non-invasive debug: + [7:6] + read-only + + + SID + Indicates whether the trace unit supports Secure invasive debug: + [5:4] + read-only + + + NSNID + Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: + [3:2] + read-only + + + NSID + Indicates whether the trace unit supports Non-secure invasive debug: + [1:0] + read-only + + + + + TRCDEVARCH + 0x00041fbc + TRCDEVARCH + 0x47724a13 + + + ARCHITECT + reads as 0b01000111011 + [31:21] + read-only + + + PRESENT + reads as 0b1 + [20:20] + read-only + + + REVISION + reads as 0b0000 + [19:16] + read-only + + + ARCHID + reads as 0b0100101000010011 + [15:0] + read-only + + + + + TRCDEVID + 0x00041fc8 + TRCDEVID + 0x00000000 + + + TRCDEVID + [31:0] + read-write + + + + + TRCDEVTYPE + 0x00041fcc + TRCDEVTYPE + 0x00000013 + + + SUB + reads as 0b0001 + [7:4] + read-only + + + MAJOR + reads as 0b0011 + [3:0] + read-only + + + + + TRCPIDR4 + 0x00041fd0 + TRCPIDR4 + 0x00000004 + + + SIZE + reads as `ImpDef + [7:4] + read-only + + + DES_2 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR5 + 0x00041fd4 + TRCPIDR5 + 0x00000000 + + + TRCPIDR5 + [31:0] + read-write + + + + + TRCPIDR6 + 0x00041fd8 + TRCPIDR6 + 0x00000000 + + + TRCPIDR6 + [31:0] + read-write + + + + + TRCPIDR7 + 0x00041fdc + TRCPIDR7 + 0x00000000 + + + TRCPIDR7 + [31:0] + read-write + + + + + TRCPIDR0 + 0x00041fe0 + TRCPIDR0 + 0x00000021 + + + PART_0 + reads as `ImpDef + [7:0] + read-only + + + + + TRCPIDR1 + 0x00041fe4 + TRCPIDR1 + 0x000000bd + + + DES_0 + reads as `ImpDef + [7:4] + read-only + + + PART_0 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR2 + 0x00041fe8 + TRCPIDR2 + 0x0000002b + + + REVISION + reads as `ImpDef + [7:4] + read-only + + + JEDEC + reads as 0b1 + [3:3] + read-only + + + DES_0 + reads as `ImpDef + [2:0] + read-only + + + + + TRCPIDR3 + 0x00041fec + TRCPIDR3 + 0x00000000 + + + REVAND + reads as `ImpDef + [7:4] + read-only + + + CMOD + reads as `ImpDef + [3:0] + read-only + + + + + TRCCIDR0 + 0x00041ff0 + TRCCIDR0 + 0x0000000d + + + PRMBL_0 + reads as 0b00001101 + [7:0] + read-only + + + + + TRCCIDR1 + 0x00041ff4 + TRCCIDR1 + 0x00000090 + + + CLASS + reads as 0b1001 + [7:4] + read-only + + + PRMBL_1 + reads as 0b0000 + [3:0] + read-only + + + + + TRCCIDR2 + 0x00041ff8 + TRCCIDR2 + 0x00000005 + + + PRMBL_2 + reads as 0b00000101 + [7:0] + read-only + + + + + TRCCIDR3 + 0x00041ffc + TRCCIDR3 + 0x000000b1 + + + PRMBL_3 + reads as 0b10110001 + [7:0] + read-only + + + + + CTICONTROL + 0x00042000 + CTI Control Register + 0x00000000 + + + GLBEN + Enables or disables the CTI + [0:0] + read-write + + + + + CTIINTACK + 0x00042010 + CTI Interrupt Acknowledge Register + 0x00000000 + + + INTACK + Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared. + [7:0] + read-write + + + + + CTIAPPSET + 0x00042014 + CTI Application Trigger Set Register + 0x00000000 + + + APPSET + Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel + [3:0] + read-write + + + + + CTIAPPCLEAR + 0x00042018 + CTI Application Trigger Clear Register + 0x00000000 + + + APPCLEAR + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIAPPPULSE + 0x0004201c + CTI Application Pulse Register + 0x00000000 + + + APPULSE + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIINEN0 + 0x00042020 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN1 + 0x00042024 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN2 + 0x00042028 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN3 + 0x0004202c + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN4 + 0x00042030 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN5 + 0x00042034 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN6 + 0x00042038 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN7 + 0x0004203c + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIOUTEN0 + 0x000420a0 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN1 + 0x000420a4 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN2 + 0x000420a8 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN3 + 0x000420ac + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN4 + 0x000420b0 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN5 + 0x000420b4 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN6 + 0x000420b8 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN7 + 0x000420bc + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTITRIGINSTATUS + 0x00042130 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINSTATUS + Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. + [7:0] + read-only + + + + + CTITRIGOUTSTATUS + 0x00042134 + CTI Trigger In Status Register + 0x00000000 + + + TRIGOUTSTATUS + Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. + [7:0] + read-only + + + + + CTICHINSTATUS + 0x00042138 + CTI Channel In Status Register + 0x00000000 + + + CTICHOUTSTATUS + Shows the status of the ctichout outputs. There is one bit of the field for each channel output + [3:0] + read-only + + + + + CTIGATE + 0x00042140 + Enable CTI Channel Gate register + 0x0000000f + + + CTIGATEEN3 + Enable ctichout3. Set to 0 to disable channel propagation. + [3:3] + read-write + + + CTIGATEEN2 + Enable ctichout2. Set to 0 to disable channel propagation. + [2:2] + read-write + + + CTIGATEEN1 + Enable ctichout1. Set to 0 to disable channel propagation. + [1:1] + read-write + + + CTIGATEEN0 + Enable ctichout0. Set to 0 to disable channel propagation. + [0:0] + read-write + + + + + ASICCTL + 0x00042144 + External Multiplexer Control register + 0x00000000 + + + ASICCTL + [31:0] + read-write + + + + + ITCHOUT + 0x00042ee4 + Integration Test Channel Output register + 0x00000000 + + + CTCHOUT + Sets the value of the ctichout outputs + [3:0] + read-write + + + + + ITTRIGOUT + 0x00042ee8 + Integration Test Trigger Output register + 0x00000000 + + + CTTRIGOUT + Sets the value of the ctitrigout outputs + [7:0] + read-write + + + + + ITCHIN + 0x00042ef4 + Integration Test Channel Input register + 0x00000000 + + + CTCHIN + Reads the value of the ctichin inputs. + [3:0] + read-only + + + + + ITCTRL + 0x00042f00 + Integration Mode Control register + 0x00000000 + + + IME + Integration Mode Enable + [0:0] + read-write + + + + + DEVARCH + 0x00042fbc + Device Architecture register + 0x47701a14 + + + ARCHITECT + Indicates the component architect + [31:21] + read-only + + + PRESENT + Indicates whether the DEVARCH register is present + [20:20] + read-only + + + REVISION + Indicates the architecture revision + [19:16] + read-only + + + ARCHID + Indicates the component + [15:0] + read-only + + + + + DEVID + 0x00042fc8 + Device Configuration register + 0x00040800 + + + NUMCH + Number of ECT channels available + [19:16] + read-only + + + NUMTRIG + Number of ECT triggers available. + [15:8] + read-only + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. + [4:0] + read-only + + + + + DEVTYPE + 0x00042fcc + Device Type Identifier register + 0x00000014 + + + SUB + Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field. + [7:4] + read-only + + + MAJOR + Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component. + [3:0] + read-only + + + + + PIDR4 + 0x00042fd0 + CoreSight Peripheral ID4 + 0x00000004 + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory + [7:4] + read-only + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [3:0] + read-only + + + + + PIDR5 + 0x00042fd4 + CoreSight Peripheral ID5 + 0x00000000 + + + PIDR5 + [31:0] + read-write + + + + + PIDR6 + 0x00042fd8 + CoreSight Peripheral ID6 + 0x00000000 + + + PIDR6 + [31:0] + read-write + + + + + PIDR7 + 0x00042fdc + CoreSight Peripheral ID7 + 0x00000000 + + + PIDR7 + [31:0] + read-write + + + + + PIDR0 + 0x00042fe0 + CoreSight Peripheral ID0 + 0x00000021 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + [7:0] + read-only + + + + + PIDR1 + 0x00042fe4 + CoreSight Peripheral ID1 + 0x000000bd + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [7:4] + read-only + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + [3:0] + read-only + + + + + PIDR2 + 0x00042fe8 + CoreSight Peripheral ID2 + 0x0000000b + + + REVISION + This device is at r1p0 + [7:4] + read-only + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + [3:3] + read-only + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [2:0] + read-only + + + + + PIDR3 + 0x00042fec + CoreSight Peripheral ID3 + 0x00000000 + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + [7:4] + read-only + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. + [3:0] + read-only + + + + + CIDR0 + 0x00042ff0 + CoreSight Component ID0 + 0x0000000d + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code + [7:0] + read-only + + + + + CIDR1 + 0x00042ff4 + CoreSight Component ID1 + 0x00000090 + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. + [7:4] + read-only + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + [3:0] + read-only + + + + + CIDR2 + 0x00042ff8 + CoreSight Component ID2 + 0x00000005 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + [7:0] + read-only + + + + + CIDR3 + 0x00042ffc + CoreSight Component ID3 + 0x000000b1 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + [7:0] + read-only + + + + + + + PPB_NS + 0xe0020000 + + + QMI + QSPI Memory Interface. + + Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. + 0x400d0000 + + 0 + 84 + registers + + + + DIRECT_CSR + 0x00000000 + Control and status for direct serial mode + + Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. + 0x01800000 + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) + [31:30] + read-write + + + CLKDIV + Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte. + [29:22] + read-write + + + RXLEVEL + Current level of DIRECT_RX FIFO + [20:18] + read-only + + + RXFULL + When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full. + [17:17] + read-only + + + RXEMPTY + When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined. + [16:16] + read-only + + + TXLEVEL + Current level of DIRECT_TX FIFO + [14:12] + read-only + + + TXEMPTY + When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes. + [11:11] + read-only + + + TXFULL + When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored. + [10:10] + read-only + + + AUTO_CS1N + When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set. + [7:7] + read-write + + + AUTO_CS0N + When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set. + [6:6] + read-write + + + ASSERT_CS1N + When 1, assert (i.e. drive low) the CS1n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [3:3] + read-write + + + ASSERT_CS0N + When 1, assert (i.e. drive low) the CS0n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [2:2] + read-write + + + BUSY + Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. + + The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. + + (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.) + [1:1] + read-only + + + EN + Enable direct mode. + + In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. + + Memory-mapped accesses will generate bus errors when direct serial mode is enabled. + [0:0] + read-write + + + + + DIRECT_TX + 0x00000004 + Transmit FIFO for direct mode + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + DIRECT_RX + 0x00000008 + Receive FIFO for direct mode + 0x00000000 + + + DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + M0_TIMING + 0x0000000c + Timing configuration register for memory address window 0. + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + 0 + No page boundary is enforced + + + 256 + 1 + Break bursts crossing a 256-byte page boundary + + + 1024 + 2 + Break bursts crossing a 1024-byte quad-page boundary + + + 4096 + 3 + Break bursts crossing a 4096-byte sector boundary + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M0_RFMT + 0x00000010 + Read transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M0_RCMD + 0x00000014 + Command constants used for reads from memory address window 0. + + The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x0000a003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M0_WFMT + 0x00000018 + Write transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M0_WCMD + 0x0000001c + Command constants used for writes to memory address window 0. + + The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x0000a002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_TIMING + 0x00000020 + Timing configuration register for memory address window 1. + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + 0 + No page boundary is enforced + + + 256 + 1 + Break bursts crossing a 256-byte page boundary + + + 1024 + 2 + Break bursts crossing a 1024-byte quad-page boundary + + + 4096 + 3 + Break bursts crossing a 4096-byte sector boundary + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M1_RFMT + 0x00000024 + Read transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M1_RCMD + 0x00000028 + Command constants used for reads from memory address window 1. + + The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x0000a003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_WFMT + 0x0000002c + Write transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M1_WCMD + 0x00000030 + Command constants used for writes to memory address window 1. + + The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x0000a002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + ATRANS0 + 0x00000034 + Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS1 + 0x00000038 + Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS2 + 0x0000003c + Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS3 + 0x00000040 + Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000c00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS4 + 0x00000044 + Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS5 + 0x00000048 + Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS6 + 0x0000004c + Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS7 + 0x00000050 + Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000c00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + + + XIP_CTRL + QSPI flash execute-in-place block + 0x400c8000 + + 0 + 32 + registers + + + + CTRL + 0x00000000 + Cache control register. Read-only from a Non-secure context. + 0x00000083 + + + WRITABLE_M1 + If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [11:11] + read-write + + + WRITABLE_M0 + If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [10:10] + read-write + + + SPLIT_WAYS + When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. + + This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. + + A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation. + [9:9] + read-write + + + MAINT_NONSEC + When 0, Non-secure accesses to the cache maintenance address window (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. + + Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. + + Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code. + [8:8] + read-write + + + NO_UNTRANSLATED_NONSEC + When 1, Non-secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [7:7] + read-write + + + NO_UNTRANSLATED_SEC + When 1, Secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [6:6] + read-write + + + NO_UNCACHED_NONSEC + When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [5:5] + read-write + + + NO_UNCACHED_SEC + When 1, Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [4:4] + read-write + + + POWER_DOWN + When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down. + [3:3] + read-write + + + EN_NONSECURE + When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + [1:1] + read-write + + + EN_SECURE + When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + + There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled. + [0:0] + read-write + + + + + STAT + 0x00000008 + 0x00000002 + + + FIFO_FULL + When 1, indicates the XIP streaming FIFO is completely full. + The streaming FIFO is 2 entries deep, so the full and empty + flag allow its level to be ascertained. + [2:2] + read-only + + + FIFO_EMPTY + When 1, indicates the XIP streaming FIFO is completely empty. + [1:1] + read-only + + + + + CTR_HIT + 0x0000000c + Cache Hit counter + 0x00000000 + + + CTR_HIT + A 32 bit saturating counter that increments upon each cache hit, + i.e. when an XIP access is serviced directly from cached data. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + CTR_ACC + 0x00000010 + Cache Access counter + 0x00000000 + + + CTR_ACC + A 32 bit saturating counter that increments upon each XIP access, + whether the cache is hit or not. This includes noncacheable accesses. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + STREAM_ADDR + 0x00000014 + FIFO stream address + 0x00000000 + + + STREAM_ADDR + The address of the next word to be streamed from flash to the streaming FIFO. + Increments automatically after each flash access. + Write the initial access address here before starting a streaming read. + [31:2] + read-write + + + + + STREAM_CTR + 0x00000018 + FIFO stream control + 0x00000000 + + + STREAM_CTR + Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to transfer + a linear data block from flash to the streaming FIFO. + Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. + Write 0 to halt an in-progress stream, and discard any in-flight + read, so that a new stream can immediately be started (after + draining the FIFO and reinitialising STREAM_ADDR) + [21:0] + read-write + + + + + STREAM_FIFO + 0x0000001c + FIFO stream data + 0x00000000 + + + STREAM_FIFO + Streamed data is buffered here, for retrieval by the system DMA. + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing + the DMA to bus stalls caused by other XIP traffic. + [31:0] + read-only + modify + + + + + + + XIP_AUX + Auxiliary DMA access to XIP FIFOs, via fast AHB bus access + 0x50500000 + + 0 + 12 + registers + + + + STREAM + 0x00000000 + Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + 0x00000000 + + + STREAM + [31:0] + read-only + modify + + + + + QMI_DIRECT_TX + 0x00000004 + Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + QMI_DIRECT_RX + 0x00000008 + Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + 0x00000000 + + + QMI_DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + + + SYSCFG + Register block for various chip control signals + 0x40008000 + + 0 + 24 + registers + + + + PROC_CONFIG + 0x00000000 + Configuration for processors + 0x00000000 + + + PROC1_HALTED + Indication that proc1 has halted + [1:1] + read-only + + + PROC0_HALTED + Indication that proc0 has halted + [0:0] + read-only + + + + + PROC_IN_SYNC_BYPASS + 0x00000004 + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 0...31. + 0x00000000 + + + GPIO + [31:0] + read-write + + + + + PROC_IN_SYNC_BYPASS_HI + 0x00000008 + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + DBGFORCE + 0x0000000c + Directly control the chip SWD debug port + 0x00000006 + + + ATTACH + Attach chip debug port to syscfg controls, and disconnect it from external SWD pads. + [3:3] + read-write + + + SWCLK + Directly drive SWCLK, if ATTACH is set + [2:2] + read-write + + + SWDI + Directly drive SWDIO input, if ATTACH is set + [1:1] + read-write + + + SWDO + Observe the value of SWDIO output. + [0:0] + read-only + + + + + MEMPOWERDOWN + 0x00000010 + Control PD pins to memories. + Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible + Use with caution + 0x00000000 + + + BOOTRAM + [12:12] + read-write + + + ROM + [11:11] + read-write + + + USB + [10:10] + read-write + + + SRAM9 + [9:9] + read-write + + + SRAM8 + [8:8] + read-write + + + SRAM7 + [7:7] + read-write + + + SRAM6 + [6:6] + read-write + + + SRAM5 + [5:5] + read-write + + + SRAM4 + [4:4] + read-write + + + SRAM3 + [3:3] + read-write + + + SRAM2 + [2:2] + read-write + + + SRAM1 + [1:1] + read-write + + + SRAM0 + [0:0] + read-write + + + + + AUXCTRL + 0x00000014 + Auxiliary system control register + 0x00000000 + + + AUXCTRL + * Bits 7:2: Reserved + + * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. + + * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state. + [7:0] + read-write + + + + + + + XOSC + Controls the crystal oscillator + 0x40048000 + + 0 + 20 + registers + + + + CTRL + 0x00000000 + Crystal Oscillator Control + 0x00000000 + + + ENABLE + On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE + [11:0] + read-write + + + 1_15MHZ + 2720 + + + 10_30MHZ + 2721 + + + 25_60MHZ + 2722 + + + 40_100MHZ + 2723 + + + + + + + STATUS + 0x00000004 + Crystal Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + [24:24] + read-write + oneToClear + + + ENABLED + Oscillator is enabled but not necessarily running and stable, resets to 0 + [12:12] + read-only + + + FREQ_RANGE + The current frequency range setting + [1:0] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + + + DORMANT + 0x00000008 + Crystal Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the XOSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: stop the PLLs before selecting dormant mode + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + STARTUP + 0x0000000c + Controls the startup delay + 0x00000000 + + + X4 + Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0. + [20:20] + read-write + + + DELAY + in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. + [13:0] + read-write + + + + + COUNT + 0x00000010 + A down counter running at the xosc frequency which counts to zero and stops. + Can be used for short software pauses when setting up time sensitive hardware. + To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. + Minimum count value is 4. Count values <4 will be treated as count value =4. + Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + PLL_SYS + 0x40050000 + + 0 + 32 + registers + + + PLL_SYS_IRQ + 42 + + + + CS + 0x00000000 + Control and Status + GENERAL CONSTRAINTS: + Reference clock frequency min=5MHz, max=800MHz + Feedback divider min=16, max=320 + VCO frequency min=750MHz, max=1600MHz + 0x00000001 + + + LOCK + PLL is locked + [31:31] + read-only + + + LOCK_N + PLL is not locked + Ideally this is cleared when PLL lock is seen and this should never normally be set + [30:30] + read-write + oneToClear + + + BYPASS + Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. + [8:8] + read-write + + + REFDIV + Divides the PLL input reference clock. + Behaviour is undefined for div=0. + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. + [5:0] + read-write + + + + + PWR + 0x00000004 + Controls the PLL power modes. + 0x0000002d + + + VCOPD + PLL VCO powerdown + To save power set high when PLL output not required or bypass=1. + [5:5] + read-write + + + POSTDIVPD + PLL post divider powerdown + To save power set high when PLL output not required or bypass=1. + [3:3] + read-write + + + DSMPD + PLL DSM powerdown + Nothing is achieved by setting this low. + [2:2] + read-write + + + PD + PLL powerdown + To save power set high when PLL output not required. + [0:0] + read-write + + + + + FBDIV_INT + 0x00000008 + Feedback divisor + (note: this PLL does not support fractional division) + 0x00000000 + + + FBDIV_INT + see ctrl reg description for constraints + [11:0] + read-write + + + + + PRIM + 0x0000000c + Controls the PLL post dividers for the primary output + (note: this PLL does not have a secondary output) + the primary output is driven from VCO divided by postdiv1*postdiv2 + 0x00077000 + + + POSTDIV1 + divide by 1-7 + [18:16] + read-write + + + POSTDIV2 + divide by 1-7 + [14:12] + read-write + + + + + INTR + 0x00000010 + Raw Interrupts + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + oneToClear + + + + + INTE + 0x00000014 + Interrupt Enable + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTF + 0x00000018 + Interrupt Force + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTS + 0x0000001c + Interrupt status after masking & forcing + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-only + + + + + + + PLL_USB + 0x40058000 + + PLL_USB_IRQ + 43 + + + + ACCESSCTRL + Hardware access control registers + 0x40060000 + + 0 + 236 + registers + + + + LOCK + 0x00000000 + Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. + + LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL + + Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. + 0x00000004 + + + DEBUG + [3:3] + read-write + + + DMA + [2:2] + read-only + + + CORE1 + [1:1] + read-write + + + CORE0 + [0:0] + read-write + + + + + FORCE_CORE_NS + 0x00000004 + Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. + + Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. + 0x00000000 + + + CORE1 + [1:1] + read-write + + + + + CFGRESET + 0x00000008 + Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. + + This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. + + Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. + 0x00000000 + + + CFGRESET + [0:0] + write-only + + + + + GPIO_NSMASK0 + 0x0000000c + Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. + + 0 -> Secure access only + + 1 -> Secure + Non-secure access + 0x00000000 + + + GPIO_NSMASK0 + [31:0] + read-write + + + + + GPIO_NSMASK1 + 0x00000010 + Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + ROM + 0x00000014 + Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_MAIN + 0x00000018 + Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_MAIN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM0 + 0x0000001c + Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM1 + 0x00000020 + Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM2 + 0x00000024 + Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM3 + 0x00000028 + Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM3 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM3 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM4 + 0x0000002c + Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM4 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM4 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM5 + 0x00000030 + Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM5 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM5 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM6 + 0x00000034 + Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM6 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM6 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM7 + 0x00000038 + Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM7 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM7 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM8 + 0x0000003c + Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM8 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM8 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM9 + 0x00000040 + Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM9 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM9 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + DMA + 0x00000044 + Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, DMA can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, DMA can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + USBCTRL + 0x00000048 + Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, USBCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, USBCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO0 + 0x0000004c + Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO1 + 0x00000050 + Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO2 + 0x00000054 + Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_TRACE + 0x00000058 + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_PERIPH + 0x0000005c + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSINFO + 0x00000060 + Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSINFO can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSINFO can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RESETS + 0x00000064 + Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RESETS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RESETS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK0 + 0x00000068 + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK1 + 0x0000006c + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_BANK0 + 0x00000070 + Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_QSPI + 0x00000074 + Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_QSPI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + BUSCTRL + 0x00000078 + Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, BUSCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, BUSCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ADC0 + 0x0000007c + Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ADC0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ADC0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + HSTX + 0x00000080 + Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, HSTX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, HSTX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C0 + 0x00000084 + Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C1 + 0x00000088 + Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PWM + 0x0000008c + Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PWM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PWM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI0 + 0x00000090 + Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI1 + 0x00000094 + Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER0 + 0x00000098 + Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER1 + 0x0000009c + Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART0 + 0x000000a0 + Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART1 + 0x000000a4 + Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + OTP + 0x000000a8 + Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, OTP can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, OTP can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TBMAN + 0x000000ac + Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TBMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TBMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + POWMAN + 0x000000b0 + Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, POWMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, POWMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TRNG + 0x000000b4 + Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TRNG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TRNG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SHA256 + 0x000000b8 + Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000f8 + + + DBG + If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SHA256 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SHA256 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSCFG + 0x000000bc + Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSCFG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSCFG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CLOCKS + 0x000000c0 + Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CLOCKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CLOCKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XOSC + 0x000000c4 + Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XOSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XOSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ROSC + 0x000000c8 + Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_SYS + 0x000000cc + Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_SYS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_SYS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_USB + 0x000000d0 + Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_USB can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_USB can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TICKS + 0x000000d4 + Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TICKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TICKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + WATCHDOG + 0x000000d8 + Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, WATCHDOG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, WATCHDOG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RSM + 0x000000dc + Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RSM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RSM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_CTRL + 0x000000e0 + Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_CTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_QMI + 0x000000e4 + Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_QMI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_QMI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_AUX + 0x000000e8 + Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000f8 + + + DBG + If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_AUX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_AUX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + + + UART0 + 0x40070000 + + 0 + 4096 + registers + + + UART0_IRQ + 33 + + + + UARTDR + 0x00000000 + Data Register, UARTDR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. + [11:11] + read-only + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. + [10:10] + read-only + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. + [9:9] + read-only + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. + [8:8] + read-only + + + DATA + Receive (read) data character. Transmit (write) data character. + [7:0] + read-write + modify + + + + + UARTRSR + 0x00000004 + Receive Status Register/Error Clear Register, UARTRSR/UARTECR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. + [3:3] + read-write + oneToClear + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. + [2:2] + read-write + oneToClear + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [1:1] + read-write + oneToClear + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [0:0] + read-write + oneToClear + + + + + UARTFR + 0x00000018 + Flag Register, UARTFR + 0x00000090 + + + RI + Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. + [8:8] + read-only + + + TXFE + Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. + [7:7] + read-only + + + RXFF + Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. + [6:6] + read-only + + + TXFF + Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + [5:5] + read-only + + + RXFE + Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + [4:4] + read-only + + + BUSY + UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. + [3:3] + read-only + + + DCD + Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + [2:2] + read-only + + + DSR + Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. + [1:1] + read-only + + + CTS + Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. + [0:0] + read-only + + + + + UARTILPR + 0x00000020 + IrDA Low-Power Counter Register, UARTILPR + 0x00000000 + + + ILPDVSR + 8-bit low-power divisor value. These bits are cleared to 0 at reset. + [7:0] + read-write + + + + + UARTIBRD + 0x00000024 + Integer Baud Rate Register, UARTIBRD + 0x00000000 + + + BAUD_DIVINT + The integer baud rate divisor. These bits are cleared to 0 on reset. + [15:0] + read-write + + + + + UARTFBRD + 0x00000028 + Fractional Baud Rate Register, UARTFBRD + 0x00000000 + + + BAUD_DIVFRAC + The fractional baud rate divisor. These bits are cleared to 0 on reset. + [5:0] + read-write + + + + + UARTLCR_H + 0x0000002c + Line Control Register, UARTLCR_H + 0x00000000 + + + SPS + Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. + [7:7] + read-write + + + WLEN + Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + [6:5] + read-write + + + FEN + Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). + [4:4] + read-write + + + STP2 + Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. + [3:3] + read-write + + + EPS + Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. + [2:2] + read-write + + + PEN + Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + [1:1] + read-write + + + BRK + Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + [0:0] + read-write + + + + + UARTCR + 0x00000030 + Control Register, UARTCR + 0x00000300 + + + CTSEN + CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. + [15:15] + read-write + + + RTSEN + RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. + [14:14] + read-write + + + OUT2 + This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). + [13:13] + read-write + + + OUT1 + This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). + [12:12] + read-write + + + RTS + Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. + [11:11] + read-write + + + DTR + Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. + [10:10] + read-write + + + RXE + Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. + [9:9] + read-write + + + TXE + Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. + [8:8] + read-write + + + LBE + Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. + [7:7] + read-write + + + SIRLP + SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. + [2:2] + read-write + + + SIREN + SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. + [1:1] + read-write + + + UARTEN + UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. + [0:0] + read-write + + + + + UARTIFLS + 0x00000034 + Interrupt FIFO Level Select Register, UARTIFLS + 0x00000012 + + + RXIFLSEL + Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. + [5:3] + read-write + + + TXIFLSEL + Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. + [2:0] + read-write + + + + + UARTIMSC + 0x00000038 + Interrupt Mask Set/Clear Register, UARTIMSC + 0x00000000 + + + OEIM + Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. + [10:10] + read-write + + + BEIM + Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. + [9:9] + read-write + + + PEIM + Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. + [8:8] + read-write + + + FEIM + Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. + [7:7] + read-write + + + RTIM + Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. + [6:6] + read-write + + + TXIM + Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. + [5:5] + read-write + + + RXIM + Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. + [4:4] + read-write + + + DSRMIM + nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + [3:3] + read-write + + + DCDMIM + nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. + [2:2] + read-write + + + CTSMIM + nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + [1:1] + read-write + + + RIMIM + nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + [0:0] + read-write + + + + + UARTRIS + 0x0000003c + Raw Interrupt Status Register, UARTRIS + 0x00000000 + + + OERIS + Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BERIS + Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PERIS + Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FERIS + Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTRIS + Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a + [6:6] + read-only + + + TXRIS + Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXRIS + Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRRMIS + nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDRMIS + nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSRMIS + nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIRMIS + nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTMIS + 0x00000040 + Masked Interrupt Status Register, UARTMIS + 0x00000000 + + + OEMIS + Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BEMIS + Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PEMIS + Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FEMIS + Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTMIS + Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. + [6:6] + read-only + + + TXMIS + Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXMIS + Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRMMIS + nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDMMIS + nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSMMIS + nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIMMIS + nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTICR + 0x00000044 + Interrupt Clear Register, UARTICR + 0x00000000 + + + OEIC + Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + [10:10] + read-write + oneToClear + + + BEIC + Break error interrupt clear. Clears the UARTBEINTR interrupt. + [9:9] + read-write + oneToClear + + + PEIC + Parity error interrupt clear. Clears the UARTPEINTR interrupt. + [8:8] + read-write + oneToClear + + + FEIC + Framing error interrupt clear. Clears the UARTFEINTR interrupt. + [7:7] + read-write + oneToClear + + + RTIC + Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + [6:6] + read-write + oneToClear + + + TXIC + Transmit interrupt clear. Clears the UARTTXINTR interrupt. + [5:5] + read-write + oneToClear + + + RXIC + Receive interrupt clear. Clears the UARTRXINTR interrupt. + [4:4] + read-write + oneToClear + + + DSRMIC + nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + [3:3] + read-write + oneToClear + + + DCDMIC + nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + [2:2] + read-write + oneToClear + + + CTSMIC + nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + [1:1] + read-write + oneToClear + + + RIMIC + nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + [0:0] + read-write + oneToClear + + + + + UARTDMACR + 0x00000048 + DMA Control Register, UARTDMACR + 0x00000000 + + + DMAONERR + DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. + [2:2] + read-write + + + TXDMAE + Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + UARTPERIPHID0 + 0x00000fe0 + UARTPeriphID0 Register + 0x00000011 + + + PARTNUMBER0 + These bits read back as 0x11 + [7:0] + read-only + + + + + UARTPERIPHID1 + 0x00000fe4 + UARTPeriphID1 Register + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + UARTPERIPHID2 + 0x00000fe8 + UARTPeriphID2 Register + 0x00000034 + + + REVISION + This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + UARTPERIPHID3 + 0x00000fec + UARTPeriphID3 Register + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + UARTPCELLID0 + 0x00000ff0 + UARTPCellID0 Register + 0x0000000d + + + UARTPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + UARTPCELLID1 + 0x00000ff4 + UARTPCellID1 Register + 0x000000f0 + + + UARTPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + UARTPCELLID2 + 0x00000ff8 + UARTPCellID2 Register + 0x00000005 + + + UARTPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + UARTPCELLID3 + 0x00000ffc + UARTPCellID3 Register + 0x000000b1 + + + UARTPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + UART1 + 0x40078000 + + UART1_IRQ + 34 + + + + ROSC + 0x400e8000 + + 0 + 40 + registers + + + + CTRL + 0x00000000 + Ring Oscillator control + 0x00000aa0 + + + ENABLE + On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 2 to 7 + HIGH uses stages 4 to 7 + TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH + [11:0] + read-write + + + LOW + 4004 + + + MEDIUM + 4005 + + + HIGH + 4007 + + + TOOHIGH + 4006 + + + + + + + FREQA + 0x00000004 + The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + The drive strength has 4 levels determined by the number of bits set + Increasing the number of bits set increases the drive strength and increases the oscillation frequency + 0 bits set is the default drive strength + 1 bit set doubles the drive strength + 2 bits set triples drive strength + 3 bits set quadruples drive strength + For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS3 + Stage 3 drive strength + [14:12] + read-write + + + DS2 + Stage 2 drive strength + [10:8] + read-write + + + DS1_RANDOM + Randomises the stage 1 drive strength + [7:7] + read-write + + + DS1 + Stage 1 drive strength + [6:4] + read-write + + + DS0_RANDOM + Randomises the stage 0 drive strength + [3:3] + read-write + + + DS0 + Stage 0 drive strength + [2:0] + read-write + + + + + FREQB + 0x00000008 + For a detailed description see freqa register + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS7 + Stage 7 drive strength + [14:12] + read-write + + + DS6 + Stage 6 drive strength + [10:8] + read-write + + + DS5 + Stage 5 drive strength + [6:4] + read-write + + + DS4 + Stage 4 drive strength + [2:0] + read-write + + + + + RANDOM + 0x0000000c + Loads a value to the LFSR randomiser + 0x3f04b16d + + + SEED + [31:0] + read-write + + + + + DORMANT + 0x00000010 + Ring Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the ROSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + DIV + 0x00000014 + Controls the output divider + 0x00000000 + + + DIV + set to 0xaa00 + div where + div = 0 divides by 128 + div = 1-127 divides by div + any other value sets div=128 + this register resets to div=32 + [15:0] + read-write + + + PASS + 43520 + + + + + + + PHASE + 0x00000018 + Controls the phase shifted output + 0x00000008 + + + PASSWD + set to 0xaa + any other value enables the output with shift=0 + [11:4] + read-write + + + ENABLE + enable the phase-shifted output + this can be changed on-the-fly + [3:3] + read-write + + + FLIP + invert the phase-shifted output + this is ignored when div=1 + [2:2] + read-write + + + SHIFT + phase shift the phase-shifted output by SHIFT input clocks + this can be changed on-the-fly + must be set to 0 before setting div=1 + [1:0] + read-write + + + + + STATUS + 0x0000001c + Ring Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT + [24:24] + read-write + oneToClear + + + DIV_RUNNING + post-divider is running + this resets to 0 but transitions to 1 during chip startup + [16:16] + read-only + + + ENABLED + Oscillator is enabled but not necessarily running and stable + this resets to 0 but transitions to 1 during chip startup + [12:12] + read-only + + + + + RANDOMBIT + 0x00000020 + This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + 0x00000001 + + + RANDOMBIT + [0:0] + read-only + + + + + COUNT + 0x00000024 + A down counter running at the ROSC frequency which counts to zero and stops. + To start the counter write a non-zero value. + Can be used for short software pauses when setting up time sensitive hardware. + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + POWMAN + Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use + 0x40100000 + + 0 + 240 + registers + + + POWMAN_IRQ_POW + 44 + + + POWMAN_IRQ_TIMER + 45 + + + + BADPASSWD + 0x00000000 + Indicates a bad password has been used + 0x00000000 + + + BADPASSWD + [0:0] + read-write + oneToClear + + + + + VREG_CTRL + 0x00000004 + Voltage Regulator Control + 0x00008050 + + + RST_N + returns the regulator to its startup settings + 0 - reset + 1 - not reset (default) + [15:15] + read-write + + + UNLOCK + unlocks the VREG control interface after power up + 0 - Locked (default) + 1 - Unlocked + It cannot be relocked when it is unlocked. + [13:13] + read-write + + + ISOLATE + isolates the VREG control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + DISABLE_VOLTAGE_LIMIT + 0=not disabled, 1=enabled + [8:8] + read-write + + + HT_TH + high temperature protection threshold + regulator power transistors are disabled when junction temperature exceeds threshold + 000 - 100C + 001 - 105C + 010 - 110C + 011 - 115C + 100 - 120C + 101 - 125C + 110 - 135C + 111 - 150C + [6:4] + read-write + + + + + VREG_STS + 0x00000008 + Voltage Regulator Status + 0x00000000 + + + VOUT_OK + output regulation status + 0=not in regulation, 1=in regulation + [4:4] + read-only + + + STARTUP + startup status + 0=startup complete, 1=starting up + [0:0] + read-only + + + + + VREG + 0x0000000c + Voltage Regulator Settings + 0x000000b0 + + + UPDATE_IN_PROGRESS + regulator state is being updated + writes to the vreg register will be ignored when this field is set + [15:15] + read-only + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_ENTRY + 0x00000010 + Voltage Regulator Low Power Entry Settings + 0x000000b4 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_EXIT + 0x00000014 + Voltage Regulator Low Power Exit Settings + 0x000000b0 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + BOD_CTRL + 0x00000018 + Brown-out Detection Control + 0x00000000 + + + ISOLATE + isolates the brown-out detection control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + + + BOD + 0x0000001c + Brown-out Detection Settings + 0x000000b1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_ENTRY + 0x00000020 + Brown-out Detection Low Power Entry Settings + 0x000000b0 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_EXIT + 0x00000024 + Brown-out Detection Low Power Exit Settings + 0x000000b1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + LPOSC + 0x00000028 + Low power oscillator control register. + 0x00000203 + + + TRIM + Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3% + [9:4] + read-write + + + MODE + This feature has been removed + [1:0] + read-write + + + + + CHIP_RESET + 0x0000002c + Chip reset control and status + 0x00000000 + + + HAD_WATCHDOG_RESET_RSM + Last reset was a watchdog timeout which was configured to reset the power-on state machine + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [28:28] + read-only + + + HAD_HZD_SYS_RESET_REQ + Last reset was a system reset from the hazard debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [27:27] + read-only + + + HAD_GLITCH_DETECT + Last reset was due to a power supply glitch + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [26:26] + read-only + + + HAD_SWCORE_PD + Last reset was a switched core powerdown + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [25:25] + read-only + + + HAD_WATCHDOG_RESET_SWCORE + Last reset was a watchdog timeout which was configured to reset the switched-core + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [24:24] + read-only + + + HAD_WATCHDOG_RESET_POWMAN + Last reset was a watchdog timeout which was configured to reset the power manager + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [23:23] + read-only + + + HAD_WATCHDOG_RESET_POWMAN_ASYNC + Last reset was a watchdog timeout which was configured to reset the power manager asynchronously + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [22:22] + read-only + + + HAD_RESCUE + Last reset was a rescue reset from the debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no, it sets this flag + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [21:21] + read-only + + + HAD_DP_RESET_REQ + Last reset was an reset request from the arm debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [19:19] + read-only + + + HAD_RUN_LOW + Last reset was from the RUN pin + This resets: + double_tap flag no + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [18:18] + read-only + + + HAD_BOR + Last reset was from the brown-out detection block + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [17:17] + read-only + + + HAD_POR + Last reset was from the power-on reset + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [16:16] + read-only + + + RESCUE_FLAG + This is set by a rescue reset from the RP-AP. + Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. + The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up. + [4:4] + read-write + oneToClear + + + DOUBLE_TAP + This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader. + [0:0] + read-write + + + + + WDSEL + 0x00000030 + Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). + Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. + 0x00000000 + + + RESET_RSM + If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a reset from a glitch detector + [12:12] + read-write + + + RESET_SWCORE + If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain + [8:8] + read-write + + + RESET_POWMAN + If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain + and run the full power-on state machine (PSM) sequence + This relies on clk_ref running. Use reset_powman_async if that may not be true + [4:4] + read-write + + + RESET_POWMAN_ASYNC + If set to 1, a watchdog reset will restore powman defaults, reset the timer, + reset the switched core domain and run the full power-on state machine (PSM) sequence + This does not rely on clk_ref running + [0:0] + read-write + + + + + SEQ_CFG + 0x00000034 + For configuration of the power sequencer + Writes are ignored while POWMAN_STATE_CHANGING=1 + 0x001011f0 + + + USING_FAST_POWCK + 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) + 1 indicates the POWMAN clock is running from the reference clock (2-50MHz) + [20:20] + read-only + + + USING_BOD_LP + Indicates the brown-out detector (BOD) mode + 0 = BOD high power mode which is the default + 1 = BOD low power mode + [17:17] + read-only + + + USING_VREG_LP + Indicates the voltage regulator (VREG) mode + 0 = VREG high power mode which is the default + 1 = VREG low power mode + [16:16] + read-only + + + USE_FAST_POWCK + selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. + 0 always run the POWMAN clock from the slow clock (lposc) + 1 run the POWMAN clock from the fast clock when available + This setting takes effect when a power up sequence is next run + [12:12] + read-write + + + RUN_LPOSC_IN_LP + Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer + This setting takes effect when the swcore is next powered down + [8:8] + read-write + + + USE_BOD_HP + Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [7:7] + read-write + + + USE_BOD_LP + Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [6:6] + read-write + + + USE_VREG_HP + Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [5:5] + read-write + + + USE_VREG_LP + Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [4:4] + read-write + + + HW_PWRUP_SRAM0 + Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [1:1] + read-write + + + HW_PWRUP_SRAM1 + Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [0:0] + read-write + + + + + STATE + 0x00000038 + This register controls the power state of the 4 power domains. + The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. + To change the state, write to POWMAN_STATE_REQ. + The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states + defined in the datasheet: + bit 3 = SWCORE + bit 2 = XIP cache + bit 1 = SRAM0 + bit 0 = SRAM1 + 0 = powered up + 1 = powered down + When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. + 0x0000000f + + + CHANGING + [13:13] + read-only + + + WAITING + [12:12] + read-only + + + BAD_HW_REQ + Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up) + [11:11] + read-only + + + BAD_SW_REQ + Bad software initiated state request. No action taken. + [10:10] + read-only + + + PWRUP_WHILE_WAITING + Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down. + [9:9] + read-write + oneToClear + + + REQ_IGNORED + [8:8] + read-write + oneToClear + + + REQ + [7:4] + read-write + + + CURRENT + [3:0] + read-only + + + + + POW_FASTDIV + 0x0000003c + 0x00000040 + + + POW_FASTDIV + divides the POWMAN clock to provide a tick for the delay module and state machines + when clk_pow is running from the slow clock it is not divided + when clk_pow is running from the fast clock it is divided by tick_div + [10:0] + read-write + + + + + POW_DELAY + 0x00000040 + power state machine delays + 0x00002011 + + + SRAM_STEP + timing between the sram0 and sram1 power state machine steps + measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit + [15:8] + read-write + + + XIP_STEP + timing between the xip power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [7:4] + read-write + + + SWCORE_STEP + timing between the swcore power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [3:0] + read-write + + + + + EXT_CTRL0 + 0x00000044 + Configures a gpio as a power mode aware control output + 0x0000003f + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_CTRL1 + 0x00000048 + Configures a gpio as a power mode aware control output + 0x0000003f + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_TIME_REF + 0x0000004c + Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. + 0x00000000 + + + DRIVE_LPCK + Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 + [4:4] + read-write + + + SOURCE_SEL + 0 -> gpio12 + 1 -> gpio20 + 2 -> gpio14 + 3 -> gpio22 + [1:0] + read-write + + + + + LPOSC_FREQ_KHZ_INT + 0x00000050 + Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. + 0x00000020 + + + LPOSC_FREQ_KHZ_INT + Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [5:0] + read-write + + + + + LPOSC_FREQ_KHZ_FRAC + 0x00000054 + Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. + 0x0000c49c + + + LPOSC_FREQ_KHZ_FRAC + Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_INT + 0x00000058 + Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. + 0x00002ee0 + + + XOSC_FREQ_KHZ_INT + Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_FRAC + 0x0000005c + Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. + 0x00000000 + + + XOSC_FREQ_KHZ_FRAC + Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + SET_TIME_63TO48 + 0x00000060 + 0x00000000 + + + SET_TIME_63TO48 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_47TO32 + 0x00000064 + 0x00000000 + + + SET_TIME_47TO32 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_31TO16 + 0x00000068 + 0x00000000 + + + SET_TIME_31TO16 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_15TO0 + 0x0000006c + 0x00000000 + + + SET_TIME_15TO0 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + READ_TIME_UPPER + 0x00000070 + 0x00000000 + + + READ_TIME_UPPER + For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER. + [31:0] + read-only + + + + + READ_TIME_LOWER + 0x00000074 + 0x00000000 + + + READ_TIME_LOWER + For reading bits 31:0 of the timer. + [31:0] + read-only + + + + + ALARM_TIME_63TO48 + 0x00000078 + 0x00000000 + + + ALARM_TIME_63TO48 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_47TO32 + 0x0000007c + 0x00000000 + + + ALARM_TIME_47TO32 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_31TO16 + 0x00000080 + 0x00000000 + + + ALARM_TIME_31TO16 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_15TO0 + 0x00000084 + 0x00000000 + + + ALARM_TIME_15TO0 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + TIMER + 0x00000088 + 0x00000000 + + + USING_GPIO_1HZ + Timer is synchronised to a 1hz gpio source + [19:19] + read-only + + + USING_GPIO_1KHZ + Timer is running from a 1khz gpio source + [18:18] + read-only + + + USING_LPOSC + Timer is running from lposc + [17:17] + read-only + + + USING_XOSC + Timer is running from xosc + [16:16] + read-only + + + USE_GPIO_1HZ + Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference. + [13:13] + read-write + + + USE_GPIO_1KHZ + switch to gpio as the source of the 1kHz timer tick + [10:10] + write-only + + + USE_XOSC + switch to xosc as the source of the 1kHz timer tick + [9:9] + write-only + + + USE_LPOSC + Switch to lposc as the source of the 1kHz timer tick + [8:8] + write-only + + + ALARM + Alarm has fired. Write to 1 to clear the alarm. + [6:6] + read-write + oneToClear + + + PWRUP_ON_ALARM + Alarm wakes the chip from low power mode + [5:5] + read-write + + + ALARM_ENAB + Enables the alarm. The alarm must be disabled while writing the alarm time. + [4:4] + read-write + + + CLEAR + Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time. + [2:2] + write-only + + + RUN + Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. + + Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. + + Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 + [1:1] + read-write + + + NONSEC_WRITE + Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure. + [0:0] + read-write + + + + + PWRUP0 + 0x0000008c + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP1 + 0x00000090 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP2 + 0x00000094 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP3 + 0x00000098 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + CURRENT_PWRUP_REQ + 0x0000009c + Indicates current powerup request state + pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0x00000000 + + + CURRENT_PWRUP_REQ + [6:0] + read-only + + + + + LAST_SWCORE_PWRUP + 0x000000a0 + Indicates which pwrup source triggered the last switched-core power up + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0x00000000 + + + LAST_SWCORE_PWRUP + [6:0] + read-only + + + + + DBG_PWRCFG + 0x000000a4 + 0x00000000 + + + IGNORE + Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req + [0:0] + read-write + + + + + BOOTDIS + 0x000000a8 + Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the OTP BOOTDIS register. + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling. + [1:1] + read-write + + + NOW + When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + DBGCONFIG + 0x000000ac + 0x00000000 + + + DP_INSTID + Configure DP instance ID for SWD multidrop selection. + Recommend that this is NOT changed until you require debug access in multi-chip environment + [3:0] + read-write + + + + + SCRATCH0 + 0x000000b0 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + 0x000000b4 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + 0x000000b8 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + 0x000000bc + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + 0x000000c0 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + 0x000000c4 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + 0x000000c8 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + 0x000000cc + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + BOOT0 + 0x000000d0 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT0 + [31:0] + read-write + + + + + BOOT1 + 0x000000d4 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT1 + [31:0] + read-write + + + + + BOOT2 + 0x000000d8 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT2 + [31:0] + read-write + + + + + BOOT3 + 0x000000dc + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT3 + [31:0] + read-write + + + + + INTR + 0x000000e0 + Raw Interrupts + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-write + oneToClear + + + + + INTE + 0x000000e4 + Interrupt Enable + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTF + 0x000000e8 + Interrupt Force + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTS + 0x000000ec + Interrupt status after masking & forcing + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-only + + + + + + + WATCHDOG + 0x400d8000 + + 0 + 44 + registers + + + + CTRL + 0x00000000 + Watchdog control + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. + The watchdog can be triggered in software. + 0x07000000 + + + TRIGGER + Trigger a watchdog reset + [31:31] + write-only + + + ENABLE + When not enabled the watchdog timer is paused + [30:30] + read-write + + + PAUSE_DBG1 + Pause the watchdog timer when processor 1 is in debug mode + [26:26] + read-write + + + PAUSE_DBG0 + Pause the watchdog timer when processor 0 is in debug mode + [25:25] + read-write + + + PAUSE_JTAG + Pause the watchdog timer when JTAG is accessing the bus fabric + [24:24] + read-write + + + TIME + Indicates the time in usec before a watchdog reset will be triggered + [23:0] + read-only + + + + + LOAD + 0x00000004 + Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. + 0x00000000 + + + LOAD + [23:0] + write-only + + + + + REASON + 0x00000008 + Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + + Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. + 0x00000000 + + + FORCE + [1:1] + read-only + + + TIMER + [0:0] + read-only + + + + + SCRATCH0 + 0x0000000c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + 0x00000010 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + 0x00000014 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + 0x00000018 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + 0x0000001c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + 0x00000020 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + 0x00000024 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + 0x00000028 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + + + DMA + DMA with separate read and write masters + 0x50000000 + + 0 + 3016 + registers + + + DMA_IRQ_0 + 10 + + + DMA_IRQ_1 + 11 + + + DMA_IRQ_2 + 12 + + + DMA_IRQ_3 + 13 + + + + CH0_READ_ADDR + 0x00000000 + DMA Channel 0 Read Address pointer + 0x00000000 + + + CH0_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH0_WRITE_ADDR + 0x00000004 + DMA Channel 0 Write Address pointer + 0x00000000 + + + CH0_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH0_TRANS_COUNT + 0x00000008 + DMA Channel 0 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH0_CTRL_TRIG + 0x0000000c + DMA Channel 0 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH0_AL1_CTRL + 0x00000010 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL1_CTRL + [31:0] + read-write + + + + + CH0_AL1_READ_ADDR + 0x00000014 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL1_READ_ADDR + [31:0] + read-write + + + + + CH0_AL1_WRITE_ADDR + 0x00000018 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL1_TRANS_COUNT_TRIG + 0x0000001c + Alias for channel 0 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH0_AL2_CTRL + 0x00000020 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL2_CTRL + [31:0] + read-write + + + + + CH0_AL2_TRANS_COUNT + 0x00000024 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL2_READ_ADDR + 0x00000028 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL2_READ_ADDR + [31:0] + read-write + + + + + CH0_AL2_WRITE_ADDR_TRIG + 0x0000002c + Alias for channel 0 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH0_AL3_CTRL + 0x00000030 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL3_CTRL + [31:0] + read-write + + + + + CH0_AL3_WRITE_ADDR + 0x00000034 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL3_TRANS_COUNT + 0x00000038 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL3_READ_ADDR_TRIG + 0x0000003c + Alias for channel 0 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH1_READ_ADDR + 0x00000040 + DMA Channel 1 Read Address pointer + 0x00000000 + + + CH1_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH1_WRITE_ADDR + 0x00000044 + DMA Channel 1 Write Address pointer + 0x00000000 + + + CH1_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH1_TRANS_COUNT + 0x00000048 + DMA Channel 1 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH1_CTRL_TRIG + 0x0000004c + DMA Channel 1 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH1_AL1_CTRL + 0x00000050 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL1_CTRL + [31:0] + read-write + + + + + CH1_AL1_READ_ADDR + 0x00000054 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL1_READ_ADDR + [31:0] + read-write + + + + + CH1_AL1_WRITE_ADDR + 0x00000058 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL1_TRANS_COUNT_TRIG + 0x0000005c + Alias for channel 1 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH1_AL2_CTRL + 0x00000060 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL2_CTRL + [31:0] + read-write + + + + + CH1_AL2_TRANS_COUNT + 0x00000064 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL2_READ_ADDR + 0x00000068 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL2_READ_ADDR + [31:0] + read-write + + + + + CH1_AL2_WRITE_ADDR_TRIG + 0x0000006c + Alias for channel 1 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH1_AL3_CTRL + 0x00000070 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL3_CTRL + [31:0] + read-write + + + + + CH1_AL3_WRITE_ADDR + 0x00000074 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL3_TRANS_COUNT + 0x00000078 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL3_READ_ADDR_TRIG + 0x0000007c + Alias for channel 1 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH2_READ_ADDR + 0x00000080 + DMA Channel 2 Read Address pointer + 0x00000000 + + + CH2_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH2_WRITE_ADDR + 0x00000084 + DMA Channel 2 Write Address pointer + 0x00000000 + + + CH2_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH2_TRANS_COUNT + 0x00000088 + DMA Channel 2 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH2_CTRL_TRIG + 0x0000008c + DMA Channel 2 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH2_AL1_CTRL + 0x00000090 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL1_CTRL + [31:0] + read-write + + + + + CH2_AL1_READ_ADDR + 0x00000094 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL1_READ_ADDR + [31:0] + read-write + + + + + CH2_AL1_WRITE_ADDR + 0x00000098 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL1_TRANS_COUNT_TRIG + 0x0000009c + Alias for channel 2 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH2_AL2_CTRL + 0x000000a0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL2_CTRL + [31:0] + read-write + + + + + CH2_AL2_TRANS_COUNT + 0x000000a4 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL2_READ_ADDR + 0x000000a8 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL2_READ_ADDR + [31:0] + read-write + + + + + CH2_AL2_WRITE_ADDR_TRIG + 0x000000ac + Alias for channel 2 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH2_AL3_CTRL + 0x000000b0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL3_CTRL + [31:0] + read-write + + + + + CH2_AL3_WRITE_ADDR + 0x000000b4 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL3_TRANS_COUNT + 0x000000b8 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL3_READ_ADDR_TRIG + 0x000000bc + Alias for channel 2 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH3_READ_ADDR + 0x000000c0 + DMA Channel 3 Read Address pointer + 0x00000000 + + + CH3_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH3_WRITE_ADDR + 0x000000c4 + DMA Channel 3 Write Address pointer + 0x00000000 + + + CH3_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH3_TRANS_COUNT + 0x000000c8 + DMA Channel 3 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH3_CTRL_TRIG + 0x000000cc + DMA Channel 3 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH3_AL1_CTRL + 0x000000d0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL1_CTRL + [31:0] + read-write + + + + + CH3_AL1_READ_ADDR + 0x000000d4 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL1_READ_ADDR + [31:0] + read-write + + + + + CH3_AL1_WRITE_ADDR + 0x000000d8 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL1_TRANS_COUNT_TRIG + 0x000000dc + Alias for channel 3 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH3_AL2_CTRL + 0x000000e0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL2_CTRL + [31:0] + read-write + + + + + CH3_AL2_TRANS_COUNT + 0x000000e4 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL2_READ_ADDR + 0x000000e8 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL2_READ_ADDR + [31:0] + read-write + + + + + CH3_AL2_WRITE_ADDR_TRIG + 0x000000ec + Alias for channel 3 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH3_AL3_CTRL + 0x000000f0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL3_CTRL + [31:0] + read-write + + + + + CH3_AL3_WRITE_ADDR + 0x000000f4 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL3_TRANS_COUNT + 0x000000f8 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL3_READ_ADDR_TRIG + 0x000000fc + Alias for channel 3 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH4_READ_ADDR + 0x00000100 + DMA Channel 4 Read Address pointer + 0x00000000 + + + CH4_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH4_WRITE_ADDR + 0x00000104 + DMA Channel 4 Write Address pointer + 0x00000000 + + + CH4_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH4_TRANS_COUNT + 0x00000108 + DMA Channel 4 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH4_CTRL_TRIG + 0x0000010c + DMA Channel 4 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH4_AL1_CTRL + 0x00000110 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL1_CTRL + [31:0] + read-write + + + + + CH4_AL1_READ_ADDR + 0x00000114 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL1_READ_ADDR + [31:0] + read-write + + + + + CH4_AL1_WRITE_ADDR + 0x00000118 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL1_TRANS_COUNT_TRIG + 0x0000011c + Alias for channel 4 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH4_AL2_CTRL + 0x00000120 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL2_CTRL + [31:0] + read-write + + + + + CH4_AL2_TRANS_COUNT + 0x00000124 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL2_READ_ADDR + 0x00000128 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL2_READ_ADDR + [31:0] + read-write + + + + + CH4_AL2_WRITE_ADDR_TRIG + 0x0000012c + Alias for channel 4 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH4_AL3_CTRL + 0x00000130 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL3_CTRL + [31:0] + read-write + + + + + CH4_AL3_WRITE_ADDR + 0x00000134 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL3_TRANS_COUNT + 0x00000138 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL3_READ_ADDR_TRIG + 0x0000013c + Alias for channel 4 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH5_READ_ADDR + 0x00000140 + DMA Channel 5 Read Address pointer + 0x00000000 + + + CH5_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH5_WRITE_ADDR + 0x00000144 + DMA Channel 5 Write Address pointer + 0x00000000 + + + CH5_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH5_TRANS_COUNT + 0x00000148 + DMA Channel 5 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH5_CTRL_TRIG + 0x0000014c + DMA Channel 5 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH5_AL1_CTRL + 0x00000150 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL1_CTRL + [31:0] + read-write + + + + + CH5_AL1_READ_ADDR + 0x00000154 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL1_READ_ADDR + [31:0] + read-write + + + + + CH5_AL1_WRITE_ADDR + 0x00000158 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL1_TRANS_COUNT_TRIG + 0x0000015c + Alias for channel 5 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH5_AL2_CTRL + 0x00000160 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL2_CTRL + [31:0] + read-write + + + + + CH5_AL2_TRANS_COUNT + 0x00000164 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL2_READ_ADDR + 0x00000168 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL2_READ_ADDR + [31:0] + read-write + + + + + CH5_AL2_WRITE_ADDR_TRIG + 0x0000016c + Alias for channel 5 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH5_AL3_CTRL + 0x00000170 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL3_CTRL + [31:0] + read-write + + + + + CH5_AL3_WRITE_ADDR + 0x00000174 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL3_TRANS_COUNT + 0x00000178 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL3_READ_ADDR_TRIG + 0x0000017c + Alias for channel 5 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH6_READ_ADDR + 0x00000180 + DMA Channel 6 Read Address pointer + 0x00000000 + + + CH6_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH6_WRITE_ADDR + 0x00000184 + DMA Channel 6 Write Address pointer + 0x00000000 + + + CH6_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH6_TRANS_COUNT + 0x00000188 + DMA Channel 6 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH6_CTRL_TRIG + 0x0000018c + DMA Channel 6 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH6_AL1_CTRL + 0x00000190 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL1_CTRL + [31:0] + read-write + + + + + CH6_AL1_READ_ADDR + 0x00000194 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL1_READ_ADDR + [31:0] + read-write + + + + + CH6_AL1_WRITE_ADDR + 0x00000198 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL1_TRANS_COUNT_TRIG + 0x0000019c + Alias for channel 6 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH6_AL2_CTRL + 0x000001a0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL2_CTRL + [31:0] + read-write + + + + + CH6_AL2_TRANS_COUNT + 0x000001a4 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL2_READ_ADDR + 0x000001a8 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL2_READ_ADDR + [31:0] + read-write + + + + + CH6_AL2_WRITE_ADDR_TRIG + 0x000001ac + Alias for channel 6 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH6_AL3_CTRL + 0x000001b0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL3_CTRL + [31:0] + read-write + + + + + CH6_AL3_WRITE_ADDR + 0x000001b4 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL3_TRANS_COUNT + 0x000001b8 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL3_READ_ADDR_TRIG + 0x000001bc + Alias for channel 6 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH7_READ_ADDR + 0x000001c0 + DMA Channel 7 Read Address pointer + 0x00000000 + + + CH7_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH7_WRITE_ADDR + 0x000001c4 + DMA Channel 7 Write Address pointer + 0x00000000 + + + CH7_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH7_TRANS_COUNT + 0x000001c8 + DMA Channel 7 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH7_CTRL_TRIG + 0x000001cc + DMA Channel 7 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH7_AL1_CTRL + 0x000001d0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL1_CTRL + [31:0] + read-write + + + + + CH7_AL1_READ_ADDR + 0x000001d4 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL1_READ_ADDR + [31:0] + read-write + + + + + CH7_AL1_WRITE_ADDR + 0x000001d8 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL1_TRANS_COUNT_TRIG + 0x000001dc + Alias for channel 7 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH7_AL2_CTRL + 0x000001e0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL2_CTRL + [31:0] + read-write + + + + + CH7_AL2_TRANS_COUNT + 0x000001e4 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL2_READ_ADDR + 0x000001e8 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL2_READ_ADDR + [31:0] + read-write + + + + + CH7_AL2_WRITE_ADDR_TRIG + 0x000001ec + Alias for channel 7 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH7_AL3_CTRL + 0x000001f0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL3_CTRL + [31:0] + read-write + + + + + CH7_AL3_WRITE_ADDR + 0x000001f4 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL3_TRANS_COUNT + 0x000001f8 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL3_READ_ADDR_TRIG + 0x000001fc + Alias for channel 7 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH8_READ_ADDR + 0x00000200 + DMA Channel 8 Read Address pointer + 0x00000000 + + + CH8_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH8_WRITE_ADDR + 0x00000204 + DMA Channel 8 Write Address pointer + 0x00000000 + + + CH8_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH8_TRANS_COUNT + 0x00000208 + DMA Channel 8 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH8_CTRL_TRIG + 0x0000020c + DMA Channel 8 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH8_AL1_CTRL + 0x00000210 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL1_CTRL + [31:0] + read-write + + + + + CH8_AL1_READ_ADDR + 0x00000214 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL1_READ_ADDR + [31:0] + read-write + + + + + CH8_AL1_WRITE_ADDR + 0x00000218 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL1_TRANS_COUNT_TRIG + 0x0000021c + Alias for channel 8 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH8_AL2_CTRL + 0x00000220 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL2_CTRL + [31:0] + read-write + + + + + CH8_AL2_TRANS_COUNT + 0x00000224 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL2_READ_ADDR + 0x00000228 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL2_READ_ADDR + [31:0] + read-write + + + + + CH8_AL2_WRITE_ADDR_TRIG + 0x0000022c + Alias for channel 8 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH8_AL3_CTRL + 0x00000230 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL3_CTRL + [31:0] + read-write + + + + + CH8_AL3_WRITE_ADDR + 0x00000234 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL3_TRANS_COUNT + 0x00000238 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL3_READ_ADDR_TRIG + 0x0000023c + Alias for channel 8 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH9_READ_ADDR + 0x00000240 + DMA Channel 9 Read Address pointer + 0x00000000 + + + CH9_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH9_WRITE_ADDR + 0x00000244 + DMA Channel 9 Write Address pointer + 0x00000000 + + + CH9_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH9_TRANS_COUNT + 0x00000248 + DMA Channel 9 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH9_CTRL_TRIG + 0x0000024c + DMA Channel 9 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH9_AL1_CTRL + 0x00000250 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL1_CTRL + [31:0] + read-write + + + + + CH9_AL1_READ_ADDR + 0x00000254 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL1_READ_ADDR + [31:0] + read-write + + + + + CH9_AL1_WRITE_ADDR + 0x00000258 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL1_TRANS_COUNT_TRIG + 0x0000025c + Alias for channel 9 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH9_AL2_CTRL + 0x00000260 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL2_CTRL + [31:0] + read-write + + + + + CH9_AL2_TRANS_COUNT + 0x00000264 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL2_READ_ADDR + 0x00000268 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL2_READ_ADDR + [31:0] + read-write + + + + + CH9_AL2_WRITE_ADDR_TRIG + 0x0000026c + Alias for channel 9 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH9_AL3_CTRL + 0x00000270 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL3_CTRL + [31:0] + read-write + + + + + CH9_AL3_WRITE_ADDR + 0x00000274 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL3_TRANS_COUNT + 0x00000278 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL3_READ_ADDR_TRIG + 0x0000027c + Alias for channel 9 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH10_READ_ADDR + 0x00000280 + DMA Channel 10 Read Address pointer + 0x00000000 + + + CH10_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH10_WRITE_ADDR + 0x00000284 + DMA Channel 10 Write Address pointer + 0x00000000 + + + CH10_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH10_TRANS_COUNT + 0x00000288 + DMA Channel 10 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH10_CTRL_TRIG + 0x0000028c + DMA Channel 10 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH10_AL1_CTRL + 0x00000290 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL1_CTRL + [31:0] + read-write + + + + + CH10_AL1_READ_ADDR + 0x00000294 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL1_READ_ADDR + [31:0] + read-write + + + + + CH10_AL1_WRITE_ADDR + 0x00000298 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL1_TRANS_COUNT_TRIG + 0x0000029c + Alias for channel 10 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH10_AL2_CTRL + 0x000002a0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL2_CTRL + [31:0] + read-write + + + + + CH10_AL2_TRANS_COUNT + 0x000002a4 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL2_READ_ADDR + 0x000002a8 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL2_READ_ADDR + [31:0] + read-write + + + + + CH10_AL2_WRITE_ADDR_TRIG + 0x000002ac + Alias for channel 10 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH10_AL3_CTRL + 0x000002b0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL3_CTRL + [31:0] + read-write + + + + + CH10_AL3_WRITE_ADDR + 0x000002b4 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL3_TRANS_COUNT + 0x000002b8 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL3_READ_ADDR_TRIG + 0x000002bc + Alias for channel 10 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH11_READ_ADDR + 0x000002c0 + DMA Channel 11 Read Address pointer + 0x00000000 + + + CH11_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH11_WRITE_ADDR + 0x000002c4 + DMA Channel 11 Write Address pointer + 0x00000000 + + + CH11_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH11_TRANS_COUNT + 0x000002c8 + DMA Channel 11 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH11_CTRL_TRIG + 0x000002cc + DMA Channel 11 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH11_AL1_CTRL + 0x000002d0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL1_CTRL + [31:0] + read-write + + + + + CH11_AL1_READ_ADDR + 0x000002d4 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL1_READ_ADDR + [31:0] + read-write + + + + + CH11_AL1_WRITE_ADDR + 0x000002d8 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL1_TRANS_COUNT_TRIG + 0x000002dc + Alias for channel 11 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH11_AL2_CTRL + 0x000002e0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL2_CTRL + [31:0] + read-write + + + + + CH11_AL2_TRANS_COUNT + 0x000002e4 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL2_READ_ADDR + 0x000002e8 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL2_READ_ADDR + [31:0] + read-write + + + + + CH11_AL2_WRITE_ADDR_TRIG + 0x000002ec + Alias for channel 11 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH11_AL3_CTRL + 0x000002f0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL3_CTRL + [31:0] + read-write + + + + + CH11_AL3_WRITE_ADDR + 0x000002f4 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL3_TRANS_COUNT + 0x000002f8 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL3_READ_ADDR_TRIG + 0x000002fc + Alias for channel 11 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH12_READ_ADDR + 0x00000300 + DMA Channel 12 Read Address pointer + 0x00000000 + + + CH12_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH12_WRITE_ADDR + 0x00000304 + DMA Channel 12 Write Address pointer + 0x00000000 + + + CH12_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH12_TRANS_COUNT + 0x00000308 + DMA Channel 12 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH12_CTRL_TRIG + 0x0000030c + DMA Channel 12 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH12_AL1_CTRL + 0x00000310 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL1_CTRL + [31:0] + read-write + + + + + CH12_AL1_READ_ADDR + 0x00000314 + Alias for channel 12 READ_ADDR register + 0x00000000 + + + CH12_AL1_READ_ADDR + [31:0] + read-write + + + + + CH12_AL1_WRITE_ADDR + 0x00000318 + Alias for channel 12 WRITE_ADDR register + 0x00000000 + + + CH12_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH12_AL1_TRANS_COUNT_TRIG + 0x0000031c + Alias for channel 12 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH12_AL2_CTRL + 0x00000320 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL2_CTRL + [31:0] + read-write + + + + + CH12_AL2_TRANS_COUNT + 0x00000324 + Alias for channel 12 TRANS_COUNT register + 0x00000000 + + + CH12_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH12_AL2_READ_ADDR + 0x00000328 + Alias for channel 12 READ_ADDR register + 0x00000000 + + + CH12_AL2_READ_ADDR + [31:0] + read-write + + + + + CH12_AL2_WRITE_ADDR_TRIG + 0x0000032c + Alias for channel 12 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH12_AL3_CTRL + 0x00000330 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL3_CTRL + [31:0] + read-write + + + + + CH12_AL3_WRITE_ADDR + 0x00000334 + Alias for channel 12 WRITE_ADDR register + 0x00000000 + + + CH12_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH12_AL3_TRANS_COUNT + 0x00000338 + Alias for channel 12 TRANS_COUNT register + 0x00000000 + + + CH12_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH12_AL3_READ_ADDR_TRIG + 0x0000033c + Alias for channel 12 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH13_READ_ADDR + 0x00000340 + DMA Channel 13 Read Address pointer + 0x00000000 + + + CH13_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH13_WRITE_ADDR + 0x00000344 + DMA Channel 13 Write Address pointer + 0x00000000 + + + CH13_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH13_TRANS_COUNT + 0x00000348 + DMA Channel 13 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH13_CTRL_TRIG + 0x0000034c + DMA Channel 13 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH13_AL1_CTRL + 0x00000350 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL1_CTRL + [31:0] + read-write + + + + + CH13_AL1_READ_ADDR + 0x00000354 + Alias for channel 13 READ_ADDR register + 0x00000000 + + + CH13_AL1_READ_ADDR + [31:0] + read-write + + + + + CH13_AL1_WRITE_ADDR + 0x00000358 + Alias for channel 13 WRITE_ADDR register + 0x00000000 + + + CH13_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH13_AL1_TRANS_COUNT_TRIG + 0x0000035c + Alias for channel 13 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH13_AL2_CTRL + 0x00000360 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL2_CTRL + [31:0] + read-write + + + + + CH13_AL2_TRANS_COUNT + 0x00000364 + Alias for channel 13 TRANS_COUNT register + 0x00000000 + + + CH13_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH13_AL2_READ_ADDR + 0x00000368 + Alias for channel 13 READ_ADDR register + 0x00000000 + + + CH13_AL2_READ_ADDR + [31:0] + read-write + + + + + CH13_AL2_WRITE_ADDR_TRIG + 0x0000036c + Alias for channel 13 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH13_AL3_CTRL + 0x00000370 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL3_CTRL + [31:0] + read-write + + + + + CH13_AL3_WRITE_ADDR + 0x00000374 + Alias for channel 13 WRITE_ADDR register + 0x00000000 + + + CH13_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH13_AL3_TRANS_COUNT + 0x00000378 + Alias for channel 13 TRANS_COUNT register + 0x00000000 + + + CH13_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH13_AL3_READ_ADDR_TRIG + 0x0000037c + Alias for channel 13 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH14_READ_ADDR + 0x00000380 + DMA Channel 14 Read Address pointer + 0x00000000 + + + CH14_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH14_WRITE_ADDR + 0x00000384 + DMA Channel 14 Write Address pointer + 0x00000000 + + + CH14_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH14_TRANS_COUNT + 0x00000388 + DMA Channel 14 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH14_CTRL_TRIG + 0x0000038c + DMA Channel 14 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH14_AL1_CTRL + 0x00000390 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL1_CTRL + [31:0] + read-write + + + + + CH14_AL1_READ_ADDR + 0x00000394 + Alias for channel 14 READ_ADDR register + 0x00000000 + + + CH14_AL1_READ_ADDR + [31:0] + read-write + + + + + CH14_AL1_WRITE_ADDR + 0x00000398 + Alias for channel 14 WRITE_ADDR register + 0x00000000 + + + CH14_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH14_AL1_TRANS_COUNT_TRIG + 0x0000039c + Alias for channel 14 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH14_AL2_CTRL + 0x000003a0 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL2_CTRL + [31:0] + read-write + + + + + CH14_AL2_TRANS_COUNT + 0x000003a4 + Alias for channel 14 TRANS_COUNT register + 0x00000000 + + + CH14_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH14_AL2_READ_ADDR + 0x000003a8 + Alias for channel 14 READ_ADDR register + 0x00000000 + + + CH14_AL2_READ_ADDR + [31:0] + read-write + + + + + CH14_AL2_WRITE_ADDR_TRIG + 0x000003ac + Alias for channel 14 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH14_AL3_CTRL + 0x000003b0 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL3_CTRL + [31:0] + read-write + + + + + CH14_AL3_WRITE_ADDR + 0x000003b4 + Alias for channel 14 WRITE_ADDR register + 0x00000000 + + + CH14_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH14_AL3_TRANS_COUNT + 0x000003b8 + Alias for channel 14 TRANS_COUNT register + 0x00000000 + + + CH14_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH14_AL3_READ_ADDR_TRIG + 0x000003bc + Alias for channel 14 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH15_READ_ADDR + 0x000003c0 + DMA Channel 15 Read Address pointer + 0x00000000 + + + CH15_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH15_WRITE_ADDR + 0x000003c4 + DMA Channel 15 Write Address pointer + 0x00000000 + + + CH15_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH15_TRANS_COUNT + 0x000003c8 + DMA Channel 15 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH15_CTRL_TRIG + 0x000003cc + DMA Channel 15 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH15_AL1_CTRL + 0x000003d0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL1_CTRL + [31:0] + read-write + + + + + CH15_AL1_READ_ADDR + 0x000003d4 + Alias for channel 15 READ_ADDR register + 0x00000000 + + + CH15_AL1_READ_ADDR + [31:0] + read-write + + + + + CH15_AL1_WRITE_ADDR + 0x000003d8 + Alias for channel 15 WRITE_ADDR register + 0x00000000 + + + CH15_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH15_AL1_TRANS_COUNT_TRIG + 0x000003dc + Alias for channel 15 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH15_AL2_CTRL + 0x000003e0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL2_CTRL + [31:0] + read-write + + + + + CH15_AL2_TRANS_COUNT + 0x000003e4 + Alias for channel 15 TRANS_COUNT register + 0x00000000 + + + CH15_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH15_AL2_READ_ADDR + 0x000003e8 + Alias for channel 15 READ_ADDR register + 0x00000000 + + + CH15_AL2_READ_ADDR + [31:0] + read-write + + + + + CH15_AL2_WRITE_ADDR_TRIG + 0x000003ec + Alias for channel 15 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH15_AL3_CTRL + 0x000003f0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL3_CTRL + [31:0] + read-write + + + + + CH15_AL3_WRITE_ADDR + 0x000003f4 + Alias for channel 15 WRITE_ADDR register + 0x00000000 + + + CH15_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH15_AL3_TRANS_COUNT + 0x000003f8 + Alias for channel 15 TRANS_COUNT register + 0x00000000 + + + CH15_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH15_AL3_READ_ADDR_TRIG + 0x000003fc + Alias for channel 15 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + INTR + 0x00000400 + Interrupt Status (raw) + 0x00000000 + + + INTR + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE0 + 0x00000404 + Interrupt Enables for IRQ 0 + 0x00000000 + + + INTE0 + Set bit n to pass interrupts from channel n to DMA IRQ 0. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0. + [15:0] + read-write + + + + + INTF0 + 0x00000408 + Force Interrupts + 0x00000000 + + + INTF0 + Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS0 + 0x0000040c + Interrupt Status for IRQ 0 + 0x00000000 + + + INTS0 + Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR1 + 0x00000410 + Interrupt Status (raw) + 0x00000000 + + + INTR1 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE1 + 0x00000414 + Interrupt Enables for IRQ 1 + 0x00000000 + + + INTE1 + Set bit n to pass interrupts from channel n to DMA IRQ 1. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1. + [15:0] + read-write + + + + + INTF1 + 0x00000418 + Force Interrupts + 0x00000000 + + + INTF1 + Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared. + [15:0] + read-write + + + + + INTS1 + 0x0000041c + Interrupt Status for IRQ 1 + 0x00000000 + + + INTS1 + Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR2 + 0x00000420 + Interrupt Status (raw) + 0x00000000 + + + INTR2 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE2 + 0x00000424 + Interrupt Enables for IRQ 2 + 0x00000000 + + + INTE2 + Set bit n to pass interrupts from channel n to DMA IRQ 2. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2. + [15:0] + read-write + + + + + INTF2 + 0x00000428 + Force Interrupts + 0x00000000 + + + INTF2 + Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared. + [15:0] + read-write + + + + + INTS2 + 0x0000042c + Interrupt Status for IRQ 2 + 0x00000000 + + + INTS2 + Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR3 + 0x00000430 + Interrupt Status (raw) + 0x00000000 + + + INTR3 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE3 + 0x00000434 + Interrupt Enables for IRQ 3 + 0x00000000 + + + INTE3 + Set bit n to pass interrupts from channel n to DMA IRQ 3. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3. + [15:0] + read-write + + + + + INTF3 + 0x00000438 + Force Interrupts + 0x00000000 + + + INTF3 + Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared. + [15:0] + read-write + + + + + INTS3 + 0x0000043c + Interrupt Status for IRQ 3 + 0x00000000 + + + INTS3 + Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + TIMER0 + 0x00000440 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER1 + 0x00000444 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER2 + 0x00000448 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER3 + 0x0000044c + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + MULTI_CHAN_TRIGGER + 0x00000450 + Trigger one or more channels simultaneously + 0x00000000 + + + MULTI_CHAN_TRIGGER + Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. + [15:0] + write-only + + + + + SNIFF_CTRL + 0x00000454 + Sniffer Control + 0x00000000 + + + OUT_INV + If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [11:11] + read-write + + + OUT_REV + If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [10:10] + read-write + + + BSWAP + Locally perform a byte reverse on the sniffed data, before feeding into checksum. + + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + [9:9] + read-write + + + CALC + [8:5] + read-write + + + CRC32 + 0 + Calculate a CRC-32 (IEEE802.3 polynomial) + + + CRC32R + 1 + Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + + + CRC16 + 2 + Calculate a CRC-16-CCITT + + + CRC16R + 3 + Calculate a CRC-16-CCITT with bit reversed data + + + EVEN + 14 + XOR reduction over all data. == 1 if the total 1 population count is odd. + + + SUM + 15 + Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + + + + + DMACH + DMA channel for Sniffer to observe + [4:1] + read-write + + + EN + Enable sniffer + [0:0] + read-write + + + + + SNIFF_DATA + 0x00000458 + Data accumulator for sniff hardware + 0x00000000 + + + SNIFF_DATA + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + [31:0] + read-write + + + + + FIFO_LEVELS + 0x00000460 + Debug RAF, WAF, TDF levels + 0x00000000 + + + RAF_LVL + Current Read-Address-FIFO fill level + [23:16] + read-only + + + WAF_LVL + Current Write-Address-FIFO fill level + [15:8] + read-only + + + TDF_LVL + Current Transfer-Data-FIFO fill level + [7:0] + read-only + + + + + CHAN_ABORT + 0x00000464 + Abort an in-progress transfer sequence on one or more channels + 0x00000000 + + + CHAN_ABORT + Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. + + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. + [15:0] + write-only + + + + + N_CHANNELS + 0x00000468 + The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + 0x00000000 + + + N_CHANNELS + [4:0] + read-only + + + + + SECCFG_CH0 + 0x00000480 + Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH1 + 0x00000484 + Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH2 + 0x00000488 + Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH3 + 0x0000048c + Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH4 + 0x00000490 + Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH5 + 0x00000494 + Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH6 + 0x00000498 + Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH7 + 0x0000049c + Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH8 + 0x000004a0 + Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH9 + 0x000004a4 + Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH10 + 0x000004a8 + Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH11 + 0x000004ac + Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH12 + 0x000004b0 + Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH13 + 0x000004b4 + Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH14 + 0x000004b8 + Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH15 + 0x000004bc + Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_IRQ0 + 0x000004c0 + Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ1 + 0x000004c4 + Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ2 + 0x000004c8 + Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ3 + 0x000004cc + Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_MISC + 0x000004d0 + Miscellaneous security configuration + 0x000003ff + + + TIMER3_S + If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. + [9:9] + read-write + + + TIMER3_P + If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels. + [8:8] + read-write + + + TIMER2_S + If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels. + [7:7] + read-write + + + TIMER2_P + If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels. + [6:6] + read-write + + + TIMER1_S + If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels. + [5:5] + read-write + + + TIMER1_P + If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels. + [4:4] + read-write + + + TIMER0_S + If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels. + [3:3] + read-write + + + TIMER0_P + If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels. + [2:2] + read-write + + + SNIFF_S + If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. + + If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels. + [1:1] + read-write + + + SNIFF_P + If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. + + If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels. + [0:0] + read-write + + + + + MPU_CTRL + 0x00000500 + Control register for DMA MPU. Accessible only from a Privileged context. + 0x00000000 + + + NS_HIDE_ADDR + By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map. + [3:3] + read-write + + + S + Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0) + [2:2] + read-write + + + P + Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0) + [1:1] + read-write + + + + + MPU_BAR0 + 0x00000504 + Base address register for MPU region 0. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR0 + 0x00000508 + Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR1 + 0x0000050c + Base address register for MPU region 1. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR1 + 0x00000510 + Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR2 + 0x00000514 + Base address register for MPU region 2. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR2 + 0x00000518 + Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR3 + 0x0000051c + Base address register for MPU region 3. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR3 + 0x00000520 + Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR4 + 0x00000524 + Base address register for MPU region 4. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR4 + 0x00000528 + Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR5 + 0x0000052c + Base address register for MPU region 5. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR5 + 0x00000530 + Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR6 + 0x00000534 + Base address register for MPU region 6. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR6 + 0x00000538 + Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR7 + 0x0000053c + Base address register for MPU region 7. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR7 + 0x00000540 + Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + CH0_DBG_CTDREQ + 0x00000800 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH0_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH0_DBG_TCR + 0x00000804 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH0_DBG_TCR + [31:0] + read-only + + + + + CH1_DBG_CTDREQ + 0x00000840 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH1_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH1_DBG_TCR + 0x00000844 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH1_DBG_TCR + [31:0] + read-only + + + + + CH2_DBG_CTDREQ + 0x00000880 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH2_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH2_DBG_TCR + 0x00000884 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH2_DBG_TCR + [31:0] + read-only + + + + + CH3_DBG_CTDREQ + 0x000008c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH3_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH3_DBG_TCR + 0x000008c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH3_DBG_TCR + [31:0] + read-only + + + + + CH4_DBG_CTDREQ + 0x00000900 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH4_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH4_DBG_TCR + 0x00000904 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH4_DBG_TCR + [31:0] + read-only + + + + + CH5_DBG_CTDREQ + 0x00000940 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH5_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH5_DBG_TCR + 0x00000944 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH5_DBG_TCR + [31:0] + read-only + + + + + CH6_DBG_CTDREQ + 0x00000980 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH6_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH6_DBG_TCR + 0x00000984 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH6_DBG_TCR + [31:0] + read-only + + + + + CH7_DBG_CTDREQ + 0x000009c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH7_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH7_DBG_TCR + 0x000009c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH7_DBG_TCR + [31:0] + read-only + + + + + CH8_DBG_CTDREQ + 0x00000a00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH8_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH8_DBG_TCR + 0x00000a04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH8_DBG_TCR + [31:0] + read-only + + + + + CH9_DBG_CTDREQ + 0x00000a40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH9_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH9_DBG_TCR + 0x00000a44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH9_DBG_TCR + [31:0] + read-only + + + + + CH10_DBG_CTDREQ + 0x00000a80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH10_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH10_DBG_TCR + 0x00000a84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH10_DBG_TCR + [31:0] + read-only + + + + + CH11_DBG_CTDREQ + 0x00000ac0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH11_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH11_DBG_TCR + 0x00000ac4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH11_DBG_TCR + [31:0] + read-only + + + + + CH12_DBG_CTDREQ + 0x00000b00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH12_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH12_DBG_TCR + 0x00000b04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH12_DBG_TCR + [31:0] + read-only + + + + + CH13_DBG_CTDREQ + 0x00000b40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH13_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH13_DBG_TCR + 0x00000b44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH13_DBG_TCR + [31:0] + read-only + + + + + CH14_DBG_CTDREQ + 0x00000b80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH14_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH14_DBG_TCR + 0x00000b84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH14_DBG_TCR + [31:0] + read-only + + + + + CH15_DBG_CTDREQ + 0x00000bc0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH15_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH15_DBG_TCR + 0x00000bc4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH15_DBG_TCR + [31:0] + read-only + + + + + + + TIMER0 + Controls time and alarms + + time is a 64 bit value indicating the time since power-on + + timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr + + An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing + 0x400b0000 + + 0 + 76 + registers + + + TIMER0_IRQ_0 + 0 + + + TIMER0_IRQ_1 + 1 + + + TIMER0_IRQ_2 + 2 + + + TIMER0_IRQ_3 + 3 + + + + TIMEHW + 0x00000000 + Write to bits 63:32 of time always write timelw before timehw + 0x00000000 + + + TIMEHW + [31:0] + write-only + + + + + TIMELW + 0x00000004 + Write to bits 31:0 of time writes do not get copied to time until timehw is written + 0x00000000 + + + TIMELW + [31:0] + write-only + + + + + TIMEHR + 0x00000008 + Read from bits 63:32 of time always read timelr before timehr + 0x00000000 + + + TIMEHR + [31:0] + read-only + + + + + TIMELR + 0x0000000c + Read from bits 31:0 of time + 0x00000000 + + + TIMELR + [31:0] + read-only + modify + + + + + ALARM0 + 0x00000010 + Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM0 + [31:0] + read-write + + + + + ALARM1 + 0x00000014 + Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM1 + [31:0] + read-write + + + + + ALARM2 + 0x00000018 + Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM2 + [31:0] + read-write + + + + + ALARM3 + 0x0000001c + Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM3 + [31:0] + read-write + + + + + ARMED + 0x00000020 + Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. + 0x00000000 + + + ARMED + [3:0] + read-write + oneToClear + + + + + TIMERAWH + 0x00000024 + Raw read from bits 63:32 of time (no side effects) + 0x00000000 + + + TIMERAWH + [31:0] + read-only + + + + + TIMERAWL + 0x00000028 + Raw read from bits 31:0 of time (no side effects) + 0x00000000 + + + TIMERAWL + [31:0] + read-only + + + + + DBGPAUSE + 0x0000002c + Set bits high to enable pause when the corresponding debug ports are active + 0x00000007 + + + DBG1 + Pause when processor 1 is in debug mode + [2:2] + read-write + + + DBG0 + Pause when processor 0 is in debug mode + [1:1] + read-write + + + + + PAUSE + 0x00000030 + Set high to pause the timer + 0x00000000 + + + PAUSE + [0:0] + read-write + + + + + LOCKED + 0x00000034 + Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + 0x00000000 + + + LOCKED + [0:0] + read-write + + + + + SOURCE + 0x00000038 + Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. + 0x00000000 + + + CLK_SYS + [0:0] + read-write + + + TICK + 0 + + + CLK_SYS + 1 + + + + + + + INTR + 0x0000003c + Raw Interrupts + 0x00000000 + + + ALARM_3 + [3:3] + read-write + oneToClear + + + ALARM_2 + [2:2] + read-write + oneToClear + + + ALARM_1 + [1:1] + read-write + oneToClear + + + ALARM_0 + [0:0] + read-write + oneToClear + + + + + INTE + 0x00000040 + Interrupt Enable + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTF + 0x00000044 + Interrupt Force + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTS + 0x00000048 + Interrupt status after masking & forcing + 0x00000000 + + + ALARM_3 + [3:3] + read-only + + + ALARM_2 + [2:2] + read-only + + + ALARM_1 + [1:1] + read-only + + + ALARM_0 + [0:0] + read-only + + + + + + + TIMER1 + 0x400b8000 + + TIMER1_IRQ_0 + 4 + + + TIMER1_IRQ_1 + 5 + + + TIMER1_IRQ_2 + 6 + + + TIMER1_IRQ_3 + 7 + + + + PWM + Simple PWM + 0x400a8000 + + 0 + 272 + registers + + + PWM_IRQ_WRAP_0 + 8 + + + PWM_IRQ_WRAP_1 + 9 + + + + CH0_CSR + 0x00000000 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH0_DIV + 0x00000004 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH0_CTR + 0x00000008 + Direct access to the PWM counter + 0x00000000 + + + CH0_CTR + [15:0] + read-write + + + + + CH0_CC + 0x0000000c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH0_TOP + 0x00000010 + Counter wrap value + 0x0000ffff + + + CH0_TOP + [15:0] + read-write + + + + + CH1_CSR + 0x00000014 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH1_DIV + 0x00000018 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH1_CTR + 0x0000001c + Direct access to the PWM counter + 0x00000000 + + + CH1_CTR + [15:0] + read-write + + + + + CH1_CC + 0x00000020 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH1_TOP + 0x00000024 + Counter wrap value + 0x0000ffff + + + CH1_TOP + [15:0] + read-write + + + + + CH2_CSR + 0x00000028 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH2_DIV + 0x0000002c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH2_CTR + 0x00000030 + Direct access to the PWM counter + 0x00000000 + + + CH2_CTR + [15:0] + read-write + + + + + CH2_CC + 0x00000034 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH2_TOP + 0x00000038 + Counter wrap value + 0x0000ffff + + + CH2_TOP + [15:0] + read-write + + + + + CH3_CSR + 0x0000003c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH3_DIV + 0x00000040 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH3_CTR + 0x00000044 + Direct access to the PWM counter + 0x00000000 + + + CH3_CTR + [15:0] + read-write + + + + + CH3_CC + 0x00000048 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH3_TOP + 0x0000004c + Counter wrap value + 0x0000ffff + + + CH3_TOP + [15:0] + read-write + + + + + CH4_CSR + 0x00000050 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH4_DIV + 0x00000054 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH4_CTR + 0x00000058 + Direct access to the PWM counter + 0x00000000 + + + CH4_CTR + [15:0] + read-write + + + + + CH4_CC + 0x0000005c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH4_TOP + 0x00000060 + Counter wrap value + 0x0000ffff + + + CH4_TOP + [15:0] + read-write + + + + + CH5_CSR + 0x00000064 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH5_DIV + 0x00000068 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH5_CTR + 0x0000006c + Direct access to the PWM counter + 0x00000000 + + + CH5_CTR + [15:0] + read-write + + + + + CH5_CC + 0x00000070 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH5_TOP + 0x00000074 + Counter wrap value + 0x0000ffff + + + CH5_TOP + [15:0] + read-write + + + + + CH6_CSR + 0x00000078 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH6_DIV + 0x0000007c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH6_CTR + 0x00000080 + Direct access to the PWM counter + 0x00000000 + + + CH6_CTR + [15:0] + read-write + + + + + CH6_CC + 0x00000084 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH6_TOP + 0x00000088 + Counter wrap value + 0x0000ffff + + + CH6_TOP + [15:0] + read-write + + + + + CH7_CSR + 0x0000008c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH7_DIV + 0x00000090 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH7_CTR + 0x00000094 + Direct access to the PWM counter + 0x00000000 + + + CH7_CTR + [15:0] + read-write + + + + + CH7_CC + 0x00000098 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH7_TOP + 0x0000009c + Counter wrap value + 0x0000ffff + + + CH7_TOP + [15:0] + read-write + + + + + CH8_CSR + 0x000000a0 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH8_DIV + 0x000000a4 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH8_CTR + 0x000000a8 + Direct access to the PWM counter + 0x00000000 + + + CH8_CTR + [15:0] + read-write + + + + + CH8_CC + 0x000000ac + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH8_TOP + 0x000000b0 + Counter wrap value + 0x0000ffff + + + CH8_TOP + [15:0] + read-write + + + + + CH9_CSR + 0x000000b4 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH9_DIV + 0x000000b8 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH9_CTR + 0x000000bc + Direct access to the PWM counter + 0x00000000 + + + CH9_CTR + [15:0] + read-write + + + + + CH9_CC + 0x000000c0 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH9_TOP + 0x000000c4 + Counter wrap value + 0x0000ffff + + + CH9_TOP + [15:0] + read-write + + + + + CH10_CSR + 0x000000c8 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH10_DIV + 0x000000cc + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH10_CTR + 0x000000d0 + Direct access to the PWM counter + 0x00000000 + + + CH10_CTR + [15:0] + read-write + + + + + CH10_CC + 0x000000d4 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH10_TOP + 0x000000d8 + Counter wrap value + 0x0000ffff + + + CH10_TOP + [15:0] + read-write + + + + + CH11_CSR + 0x000000dc + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH11_DIV + 0x000000e0 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH11_CTR + 0x000000e4 + Direct access to the PWM counter + 0x00000000 + + + CH11_CTR + [15:0] + read-write + + + + + CH11_CC + 0x000000e8 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH11_TOP + 0x000000ec + Counter wrap value + 0x0000ffff + + + CH11_TOP + [15:0] + read-write + + + + + EN + 0x000000f0 + This register aliases the CSR_EN bits for all channels. + Writing to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect sync. + For each channel, there is only one physical EN register bit, + which can be accessed through here or CHx_CSR. + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTR + 0x000000f4 + Raw Interrupts + 0x00000000 + + + CH11 + [11:11] + read-write + oneToClear + + + CH10 + [10:10] + read-write + oneToClear + + + CH9 + [9:9] + read-write + oneToClear + + + CH8 + [8:8] + read-write + oneToClear + + + CH7 + [7:7] + read-write + oneToClear + + + CH6 + [6:6] + read-write + oneToClear + + + CH5 + [5:5] + read-write + oneToClear + + + CH4 + [4:4] + read-write + oneToClear + + + CH3 + [3:3] + read-write + oneToClear + + + CH2 + [2:2] + read-write + oneToClear + + + CH1 + [1:1] + read-write + oneToClear + + + CH0 + [0:0] + read-write + oneToClear + + + + + IRQ0_INTE + 0x000000f8 + Interrupt Enable for irq0 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTF + 0x000000fc + Interrupt Force for irq0 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTS + 0x00000100 + Interrupt status after masking & forcing for irq0 + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + IRQ1_INTE + 0x00000104 + Interrupt Enable for irq1 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTF + 0x00000108 + Interrupt Force for irq1 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTS + 0x0000010c + Interrupt status after masking & forcing for irq1 + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + + + ADC + Control and data interface to SAR ADC + 0x400a0000 + + 0 + 36 + registers + + + ADC_IRQ_FIFO + 35 + + + + CS + 0x00000000 + ADC Control and Status + 0x00000000 + + + RROBIN + Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. + The first channel to be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected channel. + [24:16] + read-write + + + AINSEL + Select analog mux input. Updated automatically in round-robin mode. + This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order + [15:12] + read-write + + + ERR_STICKY + Some past ADC conversion encountered an error. Write 1 to clear. + [10:10] + read-write + oneToClear + + + ERR + The most recent ADC conversion encountered an error; result is undefined or noisy. + [9:9] + read-only + + + READY + 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. + 0 whilst conversion in progress. + [8:8] + read-only + + + START_MANY + Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. + [3:3] + read-write + + + START_ONCE + Start a single conversion. Self-clearing. Ignored if start_many is asserted. + [2:2] + write-only + + + TS_EN + Power on temperature sensor. 1 - enabled. 0 - disabled. + [1:1] + read-write + + + EN + Power on ADC and enable its clock. + 1 - enabled. 0 - disabled. + [0:0] + read-write + + + + + RESULT + 0x00000004 + Result of most recent ADC conversion + 0x00000000 + + + RESULT + [11:0] + read-only + + + + + FCS + 0x00000008 + FIFO control and status + 0x00000000 + + + THRESH + DREQ/IRQ asserted when level >= threshold + [27:24] + read-write + + + LEVEL + The number of conversion results currently waiting in the FIFO + [19:16] + read-only + + + OVER + 1 if the FIFO has been overflowed. Write 1 to clear. + [11:11] + read-write + oneToClear + + + UNDER + 1 if the FIFO has been underflowed. Write 1 to clear. + [10:10] + read-write + oneToClear + + + FULL + [9:9] + read-only + + + EMPTY + [8:8] + read-only + + + DREQ_EN + If 1: assert DMA requests when FIFO contains data + [3:3] + read-write + + + ERR + If 1: conversion error bit appears in the FIFO alongside the result + [2:2] + read-write + + + SHIFT + If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. + [1:1] + read-write + + + EN + If 1: write result to the FIFO after each conversion. + [0:0] + read-write + + + + + FIFO + 0x0000000c + Conversion result FIFO + 0x00000000 + + + ERR + 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + [15:15] + read-only + modify + + + VAL + [11:0] + read-only + modify + + + + + DIV + 0x00000010 + Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. + The divider is reset when either of these fields are written. + Total period is 1 + INT + FRAC / 256 + 0x00000000 + + + INT + Integer part of clock divisor. + [23:8] + read-write + + + FRAC + Fractional part of clock divisor. First-order delta-sigma. + [7:0] + read-write + + + + + INTR + 0x00000014 + Raw Interrupts + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + INTE + 0x00000018 + Interrupt Enable + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTF + 0x0000001c + Interrupt Force + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTS + 0x00000020 + Interrupt status after masking & forcing + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + + + I2C0 + DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 + 0x40090000 + + 0 + 256 + registers + + + I2C0_IRQ + 36 + + + + IC_CON + 0x00000000 + I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + 0x00000065 + + + STOP_DET_IF_MASTER_ACTIVE + Master issues the STOP_DET interrupt irrespective of whether master is active or not + [10:10] + read-only + + + RX_FIFO_FULL_HLD_CTRL + This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0. + [9:9] + read-write + + + DISABLED + 0 + Overflow when RX_FIFO is full + + + ENABLED + 1 + Hold bus when RX_FIFO is full + + + + + TX_EMPTY_CTRL + This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0. + [8:8] + read-write + + + DISABLED + 0 + Default behaviour of TX_EMPTY interrupt + + + ENABLED + 1 + Controlled generation of TX_EMPTY interrupt + + + + + STOP_DET_IFADDRESSED + In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + [7:7] + read-write + + + DISABLED + 0 + slave issues STOP_DET intr always + + + ENABLED + 1 + slave issues STOP_DET intr only if addressed + + + + + IC_SLAVE_DISABLE + This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + [6:6] + read-write + + + SLAVE_ENABLED + 0 + Slave mode is enabled + + + SLAVE_DISABLED + 1 + Slave mode is disabled + + + + + IC_RESTART_EN + Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED + [5:5] + read-write + + + DISABLED + 0 + Master restart disabled + + + ENABLED + 1 + Master restart enabled + + + + + IC_10BITADDR_MASTER + Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + [4:4] + read-write + + + ADDR_7BITS + 0 + Master 7Bit addressing mode + + + ADDR_10BITS + 1 + Master 10Bit addressing mode + + + + + IC_10BITADDR_SLAVE + When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + [3:3] + read-write + + + ADDR_7BITS + 0 + Slave 7Bit addressing + + + ADDR_10BITS + 1 + Slave 10Bit addressing + + + + + SPEED + These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + [2:1] + read-write + + + STANDARD + 1 + Standard Speed mode of operation + + + FAST + 2 + Fast or Fast Plus mode of operation + + + HIGH + 3 + High Speed mode of operation + + + + + MASTER_MODE + This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + [0:0] + read-write + + + DISABLED + 0 + Master mode is disabled + + + ENABLED + 1 + Master mode is enabled + + + + + + + IC_TAR + 0x00000004 + I2C Target Address Register + + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. + + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + 0x00000055 + + + SPECIAL + This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + [11:11] + read-write + + + DISABLED + 0 + Disables programming of GENERAL_CALL or START_BYTE transmission + + + ENABLED + 1 + Enables programming of GENERAL_CALL or START_BYTE transmission + + + + + GC_OR_START + If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + [10:10] + read-write + + + GENERAL_CALL + 0 + GENERAL_CALL byte transmission + + + START_BYTE + 1 + START byte transmission + + + + + IC_TAR + This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. + + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. + [9:0] + read-write + + + + + IC_SAR + 0x00000008 + I2C Slave Address Register + 0x00000055 + + + IC_SAR + The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. + [9:0] + read-write + + + + + IC_DATA_CMD + 0x00000010 + I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. + + The size of the register changes as follows: + + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + 0x00000000 + + + FIRST_DATA_BYTE + Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. + + Reset value : 0x0 + + NOTE: In case of APB_DATA_WIDTH=8, + + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. + + 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). + + 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. + [11:11] + read-only + + + INACTIVE + 0 + Sequential data byte received + + + ACTIVE + 1 + Non sequential data byte received + + + + + RESTART + This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0 + [10:10] + write-only + + + DISABLE + 0 + Don't Issue RESTART before this command + + + ENABLE + 1 + Issue RESTART before this command + + + + + STOP + This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + [9:9] + write-only + + + DISABLE + 0 + Don't Issue STOP after this command + + + ENABLE + 1 + Issue STOP after this command + + + + + CMD + This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0 + [8:8] + write-only + + + WRITE + 0 + Master Write Command + + + READ + 1 + Master Read Command + + + + + DAT + This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. + + Reset value: 0x0 + [7:0] + read-write + + + + + IC_SS_SCL_HCNT + 0x00000014 + Standard Speed I2C Clock SCL High Count Register + 0x00000028 + + + IC_SS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. + [15:0] + read-write + + + + + IC_SS_SCL_LCNT + 0x00000018 + Standard Speed I2C Clock SCL Low Count Register + 0x0000002f + + + IC_SS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_HCNT + 0x0000001c + Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + 0x00000006 + + + IC_FS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_LCNT + 0x00000020 + Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + 0x0000000d + + + IC_FS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. + [15:0] + read-write + + + + + IC_INTR_STAT + 0x0000002c + I2C Interrupt Status Register + + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + 0x00000000 + + + R_RESTART_DET + See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + R_RESTART_DET interrupt is inactive + + + ACTIVE + 1 + R_RESTART_DET interrupt is active + + + + + R_GEN_CALL + See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + R_GEN_CALL interrupt is inactive + + + ACTIVE + 1 + R_GEN_CALL interrupt is active + + + + + R_START_DET + See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + R_START_DET interrupt is inactive + + + ACTIVE + 1 + R_START_DET interrupt is active + + + + + R_STOP_DET + See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. + + Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + R_STOP_DET interrupt is inactive + + + ACTIVE + 1 + R_STOP_DET interrupt is active + + + + + R_ACTIVITY + See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + R_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + R_ACTIVITY interrupt is active + + + + + R_RX_DONE + See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + R_RX_DONE interrupt is inactive + + + ACTIVE + 1 + R_RX_DONE interrupt is active + + + + + R_TX_ABRT + See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + R_TX_ABRT interrupt is inactive + + + ACTIVE + 1 + R_TX_ABRT interrupt is active + + + + + R_RD_REQ + See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + R_RD_REQ interrupt is inactive + + + ACTIVE + 1 + R_RD_REQ interrupt is active + + + + + R_TX_EMPTY + See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. + + Reset value: 0x0 + [4:4] + read-only + + + INACTIVE + 0 + R_TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + R_TX_EMPTY interrupt is active + + + + + R_TX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + R_TX_OVER interrupt is inactive + + + ACTIVE + 1 + R_TX_OVER interrupt is active + + + + + R_RX_FULL + See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + R_RX_FULL interrupt is inactive + + + ACTIVE + 1 + R_RX_FULL interrupt is active + + + + + R_RX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + R_RX_OVER interrupt is inactive + + + ACTIVE + 1 + R_RX_OVER interrupt is active + + + + + R_RX_UNDER + See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_INTR_MASK + 0x00000030 + I2C Interrupt Mask Register. + + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + 0x000008ff + + + M_RESTART_DET + This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [12:12] + read-write + + + ENABLED + 0 + RESTART_DET interrupt is masked + + + DISABLED + 1 + RESTART_DET interrupt is unmasked + + + + + M_GEN_CALL + This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [11:11] + read-write + + + ENABLED + 0 + GEN_CALL interrupt is masked + + + DISABLED + 1 + GEN_CALL interrupt is unmasked + + + + + M_START_DET + This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [10:10] + read-write + + + ENABLED + 0 + START_DET interrupt is masked + + + DISABLED + 1 + START_DET interrupt is unmasked + + + + + M_STOP_DET + This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [9:9] + read-write + + + ENABLED + 0 + STOP_DET interrupt is masked + + + DISABLED + 1 + STOP_DET interrupt is unmasked + + + + + M_ACTIVITY + This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [8:8] + read-write + + + ENABLED + 0 + ACTIVITY interrupt is masked + + + DISABLED + 1 + ACTIVITY interrupt is unmasked + + + + + M_RX_DONE + This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [7:7] + read-write + + + ENABLED + 0 + RX_DONE interrupt is masked + + + DISABLED + 1 + RX_DONE interrupt is unmasked + + + + + M_TX_ABRT + This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [6:6] + read-write + + + ENABLED + 0 + TX_ABORT interrupt is masked + + + DISABLED + 1 + TX_ABORT interrupt is unmasked + + + + + M_RD_REQ + This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [5:5] + read-write + + + ENABLED + 0 + RD_REQ interrupt is masked + + + DISABLED + 1 + RD_REQ interrupt is unmasked + + + + + M_TX_EMPTY + This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [4:4] + read-write + + + ENABLED + 0 + TX_EMPTY interrupt is masked + + + DISABLED + 1 + TX_EMPTY interrupt is unmasked + + + + + M_TX_OVER + This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [3:3] + read-write + + + ENABLED + 0 + TX_OVER interrupt is masked + + + DISABLED + 1 + TX_OVER interrupt is unmasked + + + + + M_RX_FULL + This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [2:2] + read-write + + + ENABLED + 0 + RX_FULL interrupt is masked + + + DISABLED + 1 + RX_FULL interrupt is unmasked + + + + + M_RX_OVER + This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [1:1] + read-write + + + ENABLED + 0 + RX_OVER interrupt is masked + + + DISABLED + 1 + RX_OVER interrupt is unmasked + + + + + M_RX_UNDER + This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [0:0] + read-write + + + ENABLED + 0 + RX_UNDER interrupt is masked + + + DISABLED + 1 + RX_UNDER interrupt is unmasked + + + + + + + IC_RAW_INTR_STAT + 0x00000034 + I2C Raw Interrupt Status Register + + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + 0x00000000 + + + RESTART_DET + Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + RESTART_DET interrupt is inactive + + + ACTIVE + 1 + RESTART_DET interrupt is active + + + + + GEN_CALL + Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + GEN_CALL interrupt is inactive + + + ACTIVE + 1 + GEN_CALL interrupt is active + + + + + START_DET + Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + START_DET interrupt is inactive + + + ACTIVE + 1 + START_DET interrupt is active + + + + + STOP_DET + Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + STOP_DET interrupt is inactive + + + ACTIVE + 1 + STOP_DET interrupt is active + + + + + ACTIVITY + This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + RAW_INTR_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + RAW_INTR_ACTIVITY interrupt is active + + + + + RX_DONE + When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + RX_DONE interrupt is inactive + + + ACTIVE + 1 + RX_DONE interrupt is active + + + + + TX_ABRT + This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. + + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + TX_ABRT interrupt is inactive + + + ACTIVE + 1 + TX_ABRT interrupt is active + + + + + RD_REQ + This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + RD_REQ interrupt is inactive + + + ACTIVE + 1 + RD_REQ interrupt is active + + + + + TX_EMPTY + The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. + + Reset value: 0x0. + [4:4] + read-only + + + INACTIVE + 0 + TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + TX_EMPTY interrupt is active + + + + + TX_OVER + Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + TX_OVER interrupt is inactive + + + ACTIVE + 1 + TX_OVER interrupt is active + + + + + RX_FULL + Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + RX_FULL interrupt is inactive + + + ACTIVE + 1 + RX_FULL interrupt is active + + + + + RX_OVER + Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + RX_OVER interrupt is inactive + + + ACTIVE + 1 + RX_OVER interrupt is active + + + + + RX_UNDER + Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_RX_TL + 0x00000038 + I2C Receive FIFO Threshold Register + 0x00000000 + + + RX_TL + Receive FIFO Threshold Level. + + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + [7:0] + read-write + + + + + IC_TX_TL + 0x0000003c + I2C Transmit FIFO Threshold Register + 0x00000000 + + + TX_TL + Transmit FIFO Threshold Level. + + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + [7:0] + read-write + + + + + IC_CLR_INTR + 0x00000040 + Clear Combined and Individual Interrupt Register + 0x00000000 + + + CLR_INTR + Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_UNDER + 0x00000044 + Clear RX_UNDER Interrupt Register + 0x00000000 + + + CLR_RX_UNDER + Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_OVER + 0x00000048 + Clear RX_OVER Interrupt Register + 0x00000000 + + + CLR_RX_OVER + Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_OVER + 0x0000004c + Clear TX_OVER Interrupt Register + 0x00000000 + + + CLR_TX_OVER + Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RD_REQ + 0x00000050 + Clear RD_REQ Interrupt Register + 0x00000000 + + + CLR_RD_REQ + Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_ABRT + 0x00000054 + Clear TX_ABRT Interrupt Register + 0x00000000 + + + CLR_TX_ABRT + Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_DONE + 0x00000058 + Clear RX_DONE Interrupt Register + 0x00000000 + + + CLR_RX_DONE + Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_ACTIVITY + 0x0000005c + Clear ACTIVITY Interrupt Register + 0x00000000 + + + CLR_ACTIVITY + Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_STOP_DET + 0x00000060 + Clear STOP_DET Interrupt Register + 0x00000000 + + + CLR_STOP_DET + Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_START_DET + 0x00000064 + Clear START_DET Interrupt Register + 0x00000000 + + + CLR_START_DET + Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_GEN_CALL + 0x00000068 + Clear GEN_CALL Interrupt Register + 0x00000000 + + + CLR_GEN_CALL + Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_ENABLE + 0x0000006c + I2C Enable Register + 0x00000000 + + + TX_CMD_BLOCK + In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + [2:2] + read-write + + + NOT_BLOCKED + 0 + Tx Command execution not blocked + + + BLOCKED + 1 + Tx Command execution blocked + + + + + ABORT + When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0 + [1:1] + read-write + + + DISABLE + 0 + ABORT operation not in progress + + + ENABLED + 1 + ABORT operation in progress + + + + + ENABLE + Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + I2C is disabled + + + ENABLED + 1 + I2C is enabled + + + + + + + IC_STATUS + 0x00000070 + I2C Status Register + + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. + + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + 0x00000006 + + + SLV_ACTIVITY + Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + [6:6] + read-only + + + IDLE + 0 + Slave is idle + + + ACTIVE + 1 + Slave not idle + + + + + MST_ACTIVITY + Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. + + Reset value: 0x0 + [5:5] + read-only + + + IDLE + 0 + Master is idle + + + ACTIVE + 1 + Master not idle + + + + + RFF + Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + [4:4] + read-only + + + NOT_FULL + 0 + Rx FIFO not full + + + FULL + 1 + Rx FIFO is full + + + + + RFNE + Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + [3:3] + read-only + + + EMPTY + 0 + Rx FIFO is empty + + + NOT_EMPTY + 1 + Rx FIFO not empty + + + + + TFE + Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + [2:2] + read-only + + + NON_EMPTY + 0 + Tx FIFO not empty + + + EMPTY + 1 + Tx FIFO is empty + + + + + TFNF + Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + [1:1] + read-only + + + FULL + 0 + Tx FIFO is full + + + NOT_FULL + 1 + Tx FIFO not full + + + + + ACTIVITY + I2C Activity Status. Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + I2C is idle + + + ACTIVE + 1 + I2C is active + + + + + + + IC_TXFLR + 0x00000074 + I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + 0x00000000 + + + TXFLR + Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_RXFLR + 0x00000078 + I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + 0x00000000 + + + RXFLR + Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_SDA_HOLD + 0x0000007c + I2C SDA Hold Time Length Register + + The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). + + The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. + + Writes to this register succeed only when IC_ENABLE[0]=0. + + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. + + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + 0x00000001 + + + IC_SDA_RX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. + + Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + [23:16] + read-write + + + IC_SDA_TX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. + + Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + [15:0] + read-write + + + + + IC_TX_ABRT_SOURCE + 0x00000080 + I2C Transmit Abort Source Register + + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). + + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + 0x00000000 + + + TX_FLUSH_CNT + This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [31:23] + read-only + + + ABRT_USER_ABRT + This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [16:16] + read-only + + + ABRT_USER_ABRT_VOID + 0 + Transfer abort detected by master- scenario not present + + + ABRT_USER_ABRT_GENERATED + 1 + Transfer abort detected by master + + + + + ABRT_SLVRD_INTX + 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [15:15] + read-only + + + ABRT_SLVRD_INTX_VOID + 0 + Slave trying to transmit to remote master in read mode- scenario not present + + + ABRT_SLVRD_INTX_GENERATED + 1 + Slave trying to transmit to remote master in read mode + + + + + ABRT_SLV_ARBLOST + This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [14:14] + read-only + + + ABRT_SLV_ARBLOST_VOID + 0 + Slave lost arbitration to remote master- scenario not present + + + ABRT_SLV_ARBLOST_GENERATED + 1 + Slave lost arbitration to remote master + + + + + ABRT_SLVFLUSH_TXFIFO + This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [13:13] + read-only + + + ABRT_SLVFLUSH_TXFIFO_VOID + 0 + Slave flushes existing data in TX-FIFO upon getting read command- scenario not present + + + ABRT_SLVFLUSH_TXFIFO_GENERATED + 1 + Slave flushes existing data in TX-FIFO upon getting read command + + + + + ARB_LOST + This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [12:12] + read-only + + + ABRT_LOST_VOID + 0 + Master or Slave-Transmitter lost arbitration- scenario not present + + + ABRT_LOST_GENERATED + 1 + Master or Slave-Transmitter lost arbitration + + + + + ABRT_MASTER_DIS + This field indicates that the User tries to initiate a Master operation with the Master mode disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [11:11] + read-only + + + ABRT_MASTER_DIS_VOID + 0 + User initiating master operation when MASTER disabled- scenario not present + + + ABRT_MASTER_DIS_GENERATED + 1 + User initiating master operation when MASTER disabled + + + + + ABRT_10B_RD_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Receiver + [10:10] + read-only + + + ABRT_10B_RD_VOID + 0 + Master not trying to read in 10Bit addressing mode when RESTART disabled + + + ABRT_10B_RD_GENERATED + 1 + Master trying to read in 10Bit addressing mode when RESTART disabled + + + + + ABRT_SBYTE_NORSTRT + To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [9:9] + read-only + + + ABRT_SBYTE_NORSTRT_VOID + 0 + User trying to send START byte when RESTART disabled- scenario not present + + + ABRT_SBYTE_NORSTRT_GENERATED + 1 + User trying to send START byte when RESTART disabled + + + + + ABRT_HS_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [8:8] + read-only + + + ABRT_HS_NORSTRT_VOID + 0 + User trying to switch Master to HS mode when RESTART disabled- scenario not present + + + ABRT_HS_NORSTRT_GENERATED + 1 + User trying to switch Master to HS mode when RESTART disabled + + + + + ABRT_SBYTE_ACKDET + This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [7:7] + read-only + + + ABRT_SBYTE_ACKDET_VOID + 0 + ACK detected for START byte- scenario not present + + + ABRT_SBYTE_ACKDET_GENERATED + 1 + ACK detected for START byte + + + + + ABRT_HS_ACKDET + This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [6:6] + read-only + + + ABRT_HS_ACK_VOID + 0 + HS Master code ACKed in HS Mode- scenario not present + + + ABRT_HS_ACK_GENERATED + 1 + HS Master code ACKed in HS Mode + + + + + ABRT_GCALL_READ + This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [5:5] + read-only + + + ABRT_GCALL_READ_VOID + 0 + GCALL is followed by read from bus-scenario not present + + + ABRT_GCALL_READ_GENERATED + 1 + GCALL is followed by read from bus + + + + + ABRT_GCALL_NOACK + This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [4:4] + read-only + + + ABRT_GCALL_NOACK_VOID + 0 + GCALL not ACKed by any slave-scenario not present + + + ABRT_GCALL_NOACK_GENERATED + 1 + GCALL not ACKed by any slave + + + + + ABRT_TXDATA_NOACK + This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [3:3] + read-only + + + ABRT_TXDATA_NOACK_VOID + 0 + Transmitted data non-ACKed by addressed slave-scenario not present + + + ABRT_TXDATA_NOACK_GENERATED + 1 + Transmitted data not ACKed by addressed slave + + + + + ABRT_10ADDR2_NOACK + This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [2:2] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 2 of 10Bit Address not ACKed by any slave + + + + + ABRT_10ADDR1_NOACK + This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [1:1] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 1 of 10Bit Address not ACKed by any slave + + + + + ABRT_7B_ADDR_NOACK + This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [0:0] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + This abort is generated because of NOACK for 7-bit address + + + + + + + IC_SLV_DATA_NACK_ONLY + 0x00000084 + Generate Slave Data NACK Register + + The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. + + A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + 0x00000000 + + + NACK + Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Slave receiver generates NACK normally + + + ENABLED + 1 + Slave receiver generates NACK upon data reception only + + + + + + + IC_DMA_CR + 0x00000088 + DMA Control Register + + The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + 0x00000000 + + + TDMAE + Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + [1:1] + read-write + + + DISABLED + 0 + transmit FIFO DMA channel disabled + + + ENABLED + 1 + Transmit FIFO DMA channel enabled + + + + + RDMAE + Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Receive FIFO DMA channel disabled + + + ENABLED + 1 + Receive FIFO DMA channel enabled + + + + + + + IC_DMA_TDLR + 0x0000008c + DMA Transmit Data Level Register + 0x00000000 + + + DMATDL + Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_DMA_RDLR + 0x00000090 + I2C Receive Data Level Register + 0x00000000 + + + DMARDL + Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_SDA_SETUP + 0x00000094 + I2C SDA Setup Register + + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. + + Writes to this register succeed only when IC_ENABLE[0] = 0. + + Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + 0x00000064 + + + SDA_SETUP + SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. + [7:0] + read-write + + + + + IC_ACK_GENERAL_CALL + 0x00000098 + I2C ACK General Call Register + + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. + + This register is applicable only when the DW_apb_i2c is in slave mode. + 0x00000001 + + + ACK_GEN_CALL + ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + [0:0] + read-write + + + DISABLED + 0 + Generate NACK for a General Call + + + ENABLED + 1 + Generate ACK for a General Call + + + + + + + IC_ENABLE_STATUS + 0x0000009c + I2C Enable Status Register + + The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. + + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. + + If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. + + Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + 0x00000000 + + + SLV_RX_DATA_LOST + Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + Slave RX Data is not lost + + + ACTIVE + 1 + Slave RX Data is lost + + + + + SLV_DISABLED_WHILE_BUSY + Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: + + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; + + OR, + + (b) address and data bytes of the Slave-Receiver operation from a remote master. + + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + Slave is disabled when it is idle + + + ACTIVE + 1 + Slave is disabled when it is active + + + + + IC_EN + ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). + + Reset value: 0x0 + [0:0] + read-only + + + DISABLED + 0 + I2C disabled + + + ENABLED + 1 + I2C enabled + + + + + + + IC_FS_SPKLEN + 0x000000a0 + I2C SS, FS or FM+ spike suppression limit + + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + 0x00000007 + + + IC_FS_SPKLEN + This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. + [7:0] + read-write + + + + + IC_CLR_RESTART_DET + 0x000000a8 + Clear RESTART_DET Interrupt Register + 0x00000000 + + + CLR_RESTART_DET + Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_COMP_PARAM_1 + 0x000000f4 + Component Parameter Register 1 + + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + 0x00000000 + + + TX_BUFFER_DEPTH + TX Buffer Depth = 16 + [23:16] + read-only + + + RX_BUFFER_DEPTH + RX Buffer Depth = 16 + [15:8] + read-only + + + ADD_ENCODED_PARAMS + Encoded parameters not visible + [7:7] + read-only + + + HAS_DMA + DMA handshaking signals are enabled + [6:6] + read-only + + + INTR_IO + COMBINED Interrupt outputs + [5:5] + read-only + + + HC_COUNT_VALUES + Programmable count values for each mode. + [4:4] + read-only + + + MAX_SPEED_MODE + MAX SPEED MODE = FAST MODE + [3:2] + read-only + + + APB_DATA_WIDTH + APB data bus width is 32 bits + [1:0] + read-only + + + + + IC_COMP_VERSION + 0x000000f8 + I2C Component Version Register + 0x3230312a + + + IC_COMP_VERSION + [31:0] + read-only + + + + + IC_COMP_TYPE + 0x000000fc + I2C Component Type Register + 0x44570140 + + + IC_COMP_TYPE + Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. + [31:0] + read-only + + + + + + + I2C1 + 0x40098000 + + I2C1_IRQ + 37 + + + + SPI0 + 0x40080000 + + 0 + 4096 + registers + + + SPI0_IRQ + 31 + + + + SSPCR0 + 0x00000000 + Control register 0, SSPCR0 on page 3-4 + 0x00000000 + + + SCR + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. + [15:8] + read-write + + + SPH + SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [7:7] + read-write + + + SPO + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [6:6] + read-write + + + FRF + Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. + [5:4] + read-write + + + DSS + Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. + [3:0] + read-write + + + + + SSPCR1 + 0x00000004 + Control register 1, SSPCR1 on page 3-5 + 0x00000000 + + + SOD + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + [3:3] + read-write + + + MS + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + [2:2] + read-write + + + SSE + Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. + [1:1] + read-write + + + LBM + Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. + [0:0] + read-write + + + + + SSPDR + 0x00000008 + Data register, SSPDR on page 3-6 + 0x00000000 + + + DATA + Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write + modify + + + + + SSPSR + 0x0000000c + Status register, SSPSR on page 3-7 + 0x00000003 + + + BSY + PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + RFF + Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + [3:3] + read-only + + + RNE + Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. + [2:2] + read-only + + + TNF + Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. + [1:1] + read-only + + + TFE + Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + [0:0] + read-only + + + + + SSPCPSR + 0x00000010 + Clock prescale register, SSPCPSR on page 3-8 + 0x00000000 + + + CPSDVSR + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + SSPIMSC + 0x00000014 + Interrupt mask set or clear register, SSPIMSC on page 3-9 + 0x00000000 + + + TXIM + Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + [3:3] + read-write + + + RXIM + Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + [2:2] + read-write + + + RTIM + Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + [1:1] + read-write + + + RORIM + Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + [0:0] + read-write + + + + + SSPRIS + 0x00000018 + Raw interrupt status register, SSPRIS on page 3-10 + 0x00000008 + + + TXRIS + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXRIS + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTRIS + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORRIS + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPMIS + 0x0000001c + Masked interrupt status register, SSPMIS on page 3-11 + 0x00000000 + + + TXMIS + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXMIS + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTMIS + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORMIS + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPICR + 0x00000020 + Interrupt clear register, SSPICR on page 3-11 + 0x00000000 + + + RTIC + Clears the SSPRTINTR interrupt + [1:1] + read-write + oneToClear + + + RORIC + Clears the SSPRORINTR interrupt + [0:0] + read-write + oneToClear + + + + + SSPDMACR + 0x00000024 + DMA control register, SSPDMACR on page 3-12 + 0x00000000 + + + TXDMAE + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + SSPPERIPHID0 + 0x00000fe0 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000022 + + + PARTNUMBER0 + These bits read back as 0x22 + [7:0] + read-only + + + + + SSPPERIPHID1 + 0x00000fe4 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + SSPPERIPHID2 + 0x00000fe8 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000034 + + + REVISION + These bits return the peripheral revision + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + SSPPERIPHID3 + 0x00000fec + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + SSPPCELLID0 + 0x00000ff0 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x0000000d + + + SSPPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + SSPPCELLID1 + 0x00000ff4 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000f0 + + + SSPPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + SSPPCELLID2 + 0x00000ff8 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x00000005 + + + SSPPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + SSPPCELLID3 + 0x00000ffc + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000b1 + + + SSPPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + SPI1 + 0x40088000 + + SPI1_IRQ + 32 + + + + PIO0 + Programmable IO block + 0x50200000 + + 0 + 392 + registers + + + PIO0_IRQ_0 + 15 + + + PIO0_IRQ_1 + 16 + + + + CTRL + 0x00000000 + PIO control register + 0x00000000 + + + NEXTPREV_CLKDIV_RESTART + Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. + [26:26] + write-only + + + NEXTPREV_SM_DISABLE + Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + [25:25] + write-only + + + NEXTPREV_SM_ENABLE + Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + + If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence. + [24:24] + write-only + + + NEXT_PIO_MASK + A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [23:20] + write-only + + + PREV_PIO_MASK + A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [19:16] + write-only + + + CLKDIV_RESTART + Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. + + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. + + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. + [11:8] + write-only + + + SM_RESTART + Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. + + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. + + The contents of the output shift register and the X/Y scratch registers are not affected. + [7:4] + write-only + + + SM_ENABLE + Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. + [3:0] + read-write + + + + + FSTAT + 0x00000004 + FIFO status register + 0x0f000f00 + + + TXEMPTY + State machine TX FIFO is empty + [27:24] + read-only + + + TXFULL + State machine TX FIFO is full + [19:16] + read-only + + + RXEMPTY + State machine RX FIFO is empty + [11:8] + read-only + + + RXFULL + State machine RX FIFO is full + [3:0] + read-only + + + + + FDEBUG + 0x00000008 + FIFO debug register + 0x00000000 + + + TXSTALL + State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + [27:24] + read-write + oneToClear + + + TXOVER + TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. + [19:16] + read-write + oneToClear + + + RXUNDER + RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. + [11:8] + read-write + oneToClear + + + RXSTALL + State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. + [3:0] + read-write + oneToClear + + + + + FLEVEL + 0x0000000c + FIFO levels + 0x00000000 + + + RX3 + [31:28] + read-only + + + TX3 + [27:24] + read-only + + + RX2 + [23:20] + read-only + + + TX2 + [19:16] + read-only + + + RX1 + [15:12] + read-only + + + TX1 + [11:8] + read-only + + + RX0 + [7:4] + read-only + + + TX0 + [3:0] + read-only + + + + + TXF0 + 0x00000010 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF0 + [31:0] + write-only + + + + + TXF1 + 0x00000014 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF1 + [31:0] + write-only + + + + + TXF2 + 0x00000018 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF2 + [31:0] + write-only + + + + + TXF3 + 0x0000001c + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF3 + [31:0] + write-only + + + + + RXF0 + 0x00000020 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF0 + [31:0] + read-only + modify + + + + + RXF1 + 0x00000024 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF1 + [31:0] + read-only + modify + + + + + RXF2 + 0x00000028 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF2 + [31:0] + read-only + modify + + + + + RXF3 + 0x0000002c + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF3 + [31:0] + read-only + modify + + + + + IRQ + 0x00000030 + State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. + + Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + 0x00000000 + + + IRQ + [7:0] + read-write + oneToClear + + + + + IRQ_FORCE + 0x00000034 + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + 0x00000000 + + + IRQ_FORCE + [7:0] + write-only + + + + + INPUT_SYNC_BYPASS + 0x00000038 + There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. + 0 -> input is synchronized (default) + 1 -> synchronizer is bypassed + If in doubt, leave this register as all zeroes. + 0x00000000 + + + INPUT_SYNC_BYPASS + [31:0] + read-write + + + + + DBG_PADOUT + 0x0000003c + Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOUT + [31:0] + read-only + + + + + DBG_PADOE + 0x00000040 + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOE + [31:0] + read-only + + + + + DBG_CFGINFO + 0x00000044 + The PIO hardware has some free parameters that may vary between chip products. + These should be provided in the chip datasheet, but are also exposed here. + 0x10000000 + + + VERSION + Version of the core PIO hardware. + [31:28] + read-only + + + v0 + 0 + Version 0 (RP2040) + + + v1 + 1 + Version 1 (RP2350) + + + + + IMEM_SIZE + The size of the instruction memory, measured in units of one instruction + [21:16] + read-only + + + SM_COUNT + The number of state machines this PIO instance is equipped with. + [11:8] + read-only + + + FIFO_DEPTH + The depth of the state machine TX/RX FIFOs, measured in words. + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + this depth. + [5:0] + read-only + + + + + INSTR_MEM0 + 0x00000048 + Write-only access to instruction memory location 0 + 0x00000000 + + + INSTR_MEM0 + [15:0] + write-only + + + + + INSTR_MEM1 + 0x0000004c + Write-only access to instruction memory location 1 + 0x00000000 + + + INSTR_MEM1 + [15:0] + write-only + + + + + INSTR_MEM2 + 0x00000050 + Write-only access to instruction memory location 2 + 0x00000000 + + + INSTR_MEM2 + [15:0] + write-only + + + + + INSTR_MEM3 + 0x00000054 + Write-only access to instruction memory location 3 + 0x00000000 + + + INSTR_MEM3 + [15:0] + write-only + + + + + INSTR_MEM4 + 0x00000058 + Write-only access to instruction memory location 4 + 0x00000000 + + + INSTR_MEM4 + [15:0] + write-only + + + + + INSTR_MEM5 + 0x0000005c + Write-only access to instruction memory location 5 + 0x00000000 + + + INSTR_MEM5 + [15:0] + write-only + + + + + INSTR_MEM6 + 0x00000060 + Write-only access to instruction memory location 6 + 0x00000000 + + + INSTR_MEM6 + [15:0] + write-only + + + + + INSTR_MEM7 + 0x00000064 + Write-only access to instruction memory location 7 + 0x00000000 + + + INSTR_MEM7 + [15:0] + write-only + + + + + INSTR_MEM8 + 0x00000068 + Write-only access to instruction memory location 8 + 0x00000000 + + + INSTR_MEM8 + [15:0] + write-only + + + + + INSTR_MEM9 + 0x0000006c + Write-only access to instruction memory location 9 + 0x00000000 + + + INSTR_MEM9 + [15:0] + write-only + + + + + INSTR_MEM10 + 0x00000070 + Write-only access to instruction memory location 10 + 0x00000000 + + + INSTR_MEM10 + [15:0] + write-only + + + + + INSTR_MEM11 + 0x00000074 + Write-only access to instruction memory location 11 + 0x00000000 + + + INSTR_MEM11 + [15:0] + write-only + + + + + INSTR_MEM12 + 0x00000078 + Write-only access to instruction memory location 12 + 0x00000000 + + + INSTR_MEM12 + [15:0] + write-only + + + + + INSTR_MEM13 + 0x0000007c + Write-only access to instruction memory location 13 + 0x00000000 + + + INSTR_MEM13 + [15:0] + write-only + + + + + INSTR_MEM14 + 0x00000080 + Write-only access to instruction memory location 14 + 0x00000000 + + + INSTR_MEM14 + [15:0] + write-only + + + + + INSTR_MEM15 + 0x00000084 + Write-only access to instruction memory location 15 + 0x00000000 + + + INSTR_MEM15 + [15:0] + write-only + + + + + INSTR_MEM16 + 0x00000088 + Write-only access to instruction memory location 16 + 0x00000000 + + + INSTR_MEM16 + [15:0] + write-only + + + + + INSTR_MEM17 + 0x0000008c + Write-only access to instruction memory location 17 + 0x00000000 + + + INSTR_MEM17 + [15:0] + write-only + + + + + INSTR_MEM18 + 0x00000090 + Write-only access to instruction memory location 18 + 0x00000000 + + + INSTR_MEM18 + [15:0] + write-only + + + + + INSTR_MEM19 + 0x00000094 + Write-only access to instruction memory location 19 + 0x00000000 + + + INSTR_MEM19 + [15:0] + write-only + + + + + INSTR_MEM20 + 0x00000098 + Write-only access to instruction memory location 20 + 0x00000000 + + + INSTR_MEM20 + [15:0] + write-only + + + + + INSTR_MEM21 + 0x0000009c + Write-only access to instruction memory location 21 + 0x00000000 + + + INSTR_MEM21 + [15:0] + write-only + + + + + INSTR_MEM22 + 0x000000a0 + Write-only access to instruction memory location 22 + 0x00000000 + + + INSTR_MEM22 + [15:0] + write-only + + + + + INSTR_MEM23 + 0x000000a4 + Write-only access to instruction memory location 23 + 0x00000000 + + + INSTR_MEM23 + [15:0] + write-only + + + + + INSTR_MEM24 + 0x000000a8 + Write-only access to instruction memory location 24 + 0x00000000 + + + INSTR_MEM24 + [15:0] + write-only + + + + + INSTR_MEM25 + 0x000000ac + Write-only access to instruction memory location 25 + 0x00000000 + + + INSTR_MEM25 + [15:0] + write-only + + + + + INSTR_MEM26 + 0x000000b0 + Write-only access to instruction memory location 26 + 0x00000000 + + + INSTR_MEM26 + [15:0] + write-only + + + + + INSTR_MEM27 + 0x000000b4 + Write-only access to instruction memory location 27 + 0x00000000 + + + INSTR_MEM27 + [15:0] + write-only + + + + + INSTR_MEM28 + 0x000000b8 + Write-only access to instruction memory location 28 + 0x00000000 + + + INSTR_MEM28 + [15:0] + write-only + + + + + INSTR_MEM29 + 0x000000bc + Write-only access to instruction memory location 29 + 0x00000000 + + + INSTR_MEM29 + [15:0] + write-only + + + + + INSTR_MEM30 + 0x000000c0 + Write-only access to instruction memory location 30 + 0x00000000 + + + INSTR_MEM30 + [15:0] + write-only + + + + + INSTR_MEM31 + 0x000000c4 + Write-only access to instruction memory location 31 + 0x00000000 + + + INSTR_MEM31 + [15:0] + write-only + + + + + SM0_CLKDIV + 0x000000c8 + Clock divisor register for state machine 0 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM0_EXECCTRL + 0x000000cc + Execution/behavioural settings for state machine 0 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM0_SHIFTCTRL + 0x000000d0 + Control behaviour of the input/output shift registers for state machine 0 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM0_ADDR + 0x000000d4 + Current instruction address of state machine 0 + 0x00000000 + + + SM0_ADDR + [4:0] + read-only + + + + + SM0_INSTR + 0x000000d8 + Read to see the instruction currently addressed by state machine 0's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM0_INSTR + [15:0] + read-write + + + + + SM0_PINCTRL + 0x000000dc + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM1_CLKDIV + 0x000000e0 + Clock divisor register for state machine 1 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM1_EXECCTRL + 0x000000e4 + Execution/behavioural settings for state machine 1 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM1_SHIFTCTRL + 0x000000e8 + Control behaviour of the input/output shift registers for state machine 1 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM1_ADDR + 0x000000ec + Current instruction address of state machine 1 + 0x00000000 + + + SM1_ADDR + [4:0] + read-only + + + + + SM1_INSTR + 0x000000f0 + Read to see the instruction currently addressed by state machine 1's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM1_INSTR + [15:0] + read-write + + + + + SM1_PINCTRL + 0x000000f4 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM2_CLKDIV + 0x000000f8 + Clock divisor register for state machine 2 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM2_EXECCTRL + 0x000000fc + Execution/behavioural settings for state machine 2 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM2_SHIFTCTRL + 0x00000100 + Control behaviour of the input/output shift registers for state machine 2 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM2_ADDR + 0x00000104 + Current instruction address of state machine 2 + 0x00000000 + + + SM2_ADDR + [4:0] + read-only + + + + + SM2_INSTR + 0x00000108 + Read to see the instruction currently addressed by state machine 2's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM2_INSTR + [15:0] + read-write + + + + + SM2_PINCTRL + 0x0000010c + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM3_CLKDIV + 0x00000110 + Clock divisor register for state machine 3 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM3_EXECCTRL + 0x00000114 + Execution/behavioural settings for state machine 3 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM3_SHIFTCTRL + 0x00000118 + Control behaviour of the input/output shift registers for state machine 3 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM3_ADDR + 0x0000011c + Current instruction address of state machine 3 + 0x00000000 + + + SM3_ADDR + [4:0] + read-only + + + + + SM3_INSTR + 0x00000120 + Read to see the instruction currently addressed by state machine 3's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM3_INSTR + [15:0] + read-write + + + + + SM3_PINCTRL + 0x00000124 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + RXF0_PUTGET0 + 0x00000128 + Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET0 + [31:0] + read-write + + + + + RXF0_PUTGET1 + 0x0000012c + Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET1 + [31:0] + read-write + + + + + RXF0_PUTGET2 + 0x00000130 + Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET2 + [31:0] + read-write + + + + + RXF0_PUTGET3 + 0x00000134 + Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET3 + [31:0] + read-write + + + + + RXF1_PUTGET0 + 0x00000138 + Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET0 + [31:0] + read-write + + + + + RXF1_PUTGET1 + 0x0000013c + Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET1 + [31:0] + read-write + + + + + RXF1_PUTGET2 + 0x00000140 + Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET2 + [31:0] + read-write + + + + + RXF1_PUTGET3 + 0x00000144 + Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET3 + [31:0] + read-write + + + + + RXF2_PUTGET0 + 0x00000148 + Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET0 + [31:0] + read-write + + + + + RXF2_PUTGET1 + 0x0000014c + Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET1 + [31:0] + read-write + + + + + RXF2_PUTGET2 + 0x00000150 + Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET2 + [31:0] + read-write + + + + + RXF2_PUTGET3 + 0x00000154 + Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET3 + [31:0] + read-write + + + + + RXF3_PUTGET0 + 0x00000158 + Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET0 + [31:0] + read-write + + + + + RXF3_PUTGET1 + 0x0000015c + Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET1 + [31:0] + read-write + + + + + RXF3_PUTGET2 + 0x00000160 + Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET2 + [31:0] + read-write + + + + + RXF3_PUTGET3 + 0x00000164 + Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET3 + [31:0] + read-write + + + + + GPIOBASE + 0x00000168 + Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. + + Only the values 0 and 16 are supported (only bit 4 is writable). + 0x00000000 + + + GPIOBASE + [4:4] + read-write + + + + + INTR + 0x0000016c + Raw Interrupts + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ0_INTE + 0x00000170 + Interrupt Enable for irq0 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTF + 0x00000174 + Interrupt Force for irq0 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTS + 0x00000178 + Interrupt status after masking & forcing for irq0 + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ1_INTE + 0x0000017c + Interrupt Enable for irq1 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTF + 0x00000180 + Interrupt Force for irq1 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTS + 0x00000184 + Interrupt status after masking & forcing for irq1 + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + + + PIO1 + 0x50300000 + + PIO1_IRQ_0 + 17 + + + PIO1_IRQ_1 + 18 + + + + PIO2 + 0x50400000 + + PIO2_IRQ_0 + 19 + + + PIO2_IRQ_1 + 20 + + + + BUSCTRL + Register block for busfabric control signals and performance counters + 0x40068000 + + 0 + 44 + registers + + + + BUS_PRIORITY + 0x00000000 + Set the priority of each master for bus arbitration. + 0x00000000 + + + DMA_W + 0 - low priority, 1 - high priority + [12:12] + read-write + + + DMA_R + 0 - low priority, 1 - high priority + [8:8] + read-write + + + PROC1 + 0 - low priority, 1 - high priority + [4:4] + read-write + + + PROC0 + 0 - low priority, 1 - high priority + [0:0] + read-write + + + + + BUS_PRIORITY_ACK + 0x00000004 + Bus priority acknowledge + 0x00000000 + + + BUS_PRIORITY_ACK + Goes to 1 once all arbiters have registered the new global priority levels. + Arbiters update their local priority when servicing a new nonsequential access. + In normal circumstances this will happen almost immediately. + [0:0] + read-only + + + + + PERFCTR_EN + 0x00000008 + Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. + + The performance counters are initially disabled, to save energy. + 0x00000000 + + + PERFCTR_EN + [0:0] + read-write + + + + + PERFCTR0 + 0x0000000c + Bus fabric performance counter 0 + 0x00000000 + + + PERFCTR0 + Busfabric saturating performance counter 0 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL0 + [23:0] + read-write + oneToClear + + + + + PERFSEL0 + 0x00000010 + Bus fabric performance event select for PERFCTR0 + 0x0000001f + + + PERFSEL0 + Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR1 + 0x00000014 + Bus fabric performance counter 1 + 0x00000000 + + + PERFCTR1 + Busfabric saturating performance counter 1 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL1 + [23:0] + read-write + oneToClear + + + + + PERFSEL1 + 0x00000018 + Bus fabric performance event select for PERFCTR1 + 0x0000001f + + + PERFSEL1 + Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR2 + 0x0000001c + Bus fabric performance counter 2 + 0x00000000 + + + PERFCTR2 + Busfabric saturating performance counter 2 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL2 + [23:0] + read-write + oneToClear + + + + + PERFSEL2 + 0x00000020 + Bus fabric performance event select for PERFCTR2 + 0x0000001f + + + PERFSEL2 + Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR3 + 0x00000024 + Bus fabric performance counter 3 + 0x00000000 + + + PERFCTR3 + Busfabric saturating performance counter 3 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL3 + [23:0] + read-write + oneToClear + + + + + PERFSEL3 + 0x00000028 + Bus fabric performance event select for PERFCTR3 + 0x0000001f + + + PERFSEL3 + Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + + + SIO + Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. + 0xd0000000 + + 0 + 488 + registers + + + SIO_IRQ_FIFO + 25 + + + SIO_IRQ_BELL + 26 + + + SIO_IRQ_FIFO_NS + 27 + + + SIO_IRQ_BELL_NS + 28 + + + SIO_IRQ_MTIMECMP + 29 + + + + CPUID + 0x00000000 + Processor core identifier + 0x00000000 + + + CPUID + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + [31:0] + read-only + + + + + GPIO_IN + 0x00000004 + Input value for GPIO0...31. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x00000000 + + + GPIO_IN + [31:0] + read-only + + + + + GPIO_HI_IN + 0x00000008 + Input value on GPIO32...47, QSPI IOs and USB pins + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x00000000 + + + QSPI_SD + Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-only + + + QSPI_CSN + Input value on QSPI CSn pin + [27:27] + read-only + + + QSPI_SCK + Input value on QSPI SCK pin + [26:26] + read-only + + + USB_DM + Input value on USB D- pin + [25:25] + read-only + + + USB_DP + Input value on USB D+ pin + [24:24] + read-only + + + GPIO + Input value on GPIO32...47 + [15:0] + read-only + + + + + GPIO_OUT + 0x00000010 + GPIO0...31 output value + 0x00000000 + + + GPIO_OUT + Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. + + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OUT + 0x00000014 + Output value for GPIO32...47, QSPI IOs and USB pins. + + Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x00000000 + + + QSPI_SD + Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output value for USB D- pin + [25:25] + read-write + + + USB_DP + Output value for USB D+ pin + [24:24] + read-write + + + GPIO + Output value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OUT_SET + 0x00000018 + GPIO0...31 output value set + 0x00000000 + + + GPIO_OUT_SET + Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_SET + 0x0000001c + Output value set for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_CLR + 0x00000020 + GPIO0...31 output value clear + 0x00000000 + + + GPIO_OUT_CLR + Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_CLR + 0x00000024 + Output value clear for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_XOR + 0x00000028 + GPIO0...31 output value XOR + 0x00000000 + + + GPIO_OUT_XOR + Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_XOR + 0x0000002c + Output value XOR for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE + 0x00000030 + GPIO0...31 output enable + 0x00000000 + + + GPIO_OE + Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. + + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OE + 0x00000034 + Output enable value for GPIO32...47, QSPI IOs and USB pins. + + Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x00000000 + + + QSPI_SD + Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output enable value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output enable value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output enable value for USB D- pin + [25:25] + read-write + + + USB_DP + Output enable value for USB D+ pin + [24:24] + read-write + + + GPIO + Output enable value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OE_SET + 0x00000038 + GPIO0...31 output enable set + 0x00000000 + + + GPIO_OE_SET + Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_SET + 0x0000003c + Output enable set for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_CLR + 0x00000040 + GPIO0...31 output enable clear + 0x00000000 + + + GPIO_OE_CLR + Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_CLR + 0x00000044 + Output enable clear for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_XOR + 0x00000048 + GPIO0...31 output enable XOR + 0x00000000 + + + GPIO_OE_XOR + Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_XOR + 0x0000004c + Output enable XOR for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + FIFO_ST + 0x00000050 + Status register for inter-core FIFOs (mailboxes). + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + 0x00000002 + + + ROE + Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + [3:3] + read-write + oneToClear + + + WOF + Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + [2:2] + read-write + oneToClear + + + RDY + Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + [1:1] + read-only + + + VLD + Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + [0:0] + read-only + + + + + FIFO_WR + 0x00000054 + Write access to this core's TX FIFO + 0x00000000 + + + FIFO_WR + [31:0] + write-only + + + + + FIFO_RD + 0x00000058 + Read access to this core's RX FIFO + 0x00000000 + + + FIFO_RD + [31:0] + read-only + modify + + + + + SPINLOCK_ST + 0x0000005c + Spinlock state + A bitmap containing the state of all 32 spinlocks (1=locked). + Mainly intended for debugging. + 0x00000000 + + + SPINLOCK_ST + [31:0] + read-only + + + + + INTERP0_ACCUM0 + 0x00000080 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP0_ACCUM0 + [31:0] + read-write + + + + + INTERP0_ACCUM1 + 0x00000084 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP0_ACCUM1 + [31:0] + read-write + + + + + INTERP0_BASE0 + 0x00000088 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP0_BASE0 + [31:0] + read-write + + + + + INTERP0_BASE1 + 0x0000008c + Read/write access to BASE1 register. + 0x00000000 + + + INTERP0_BASE1 + [31:0] + read-write + + + + + INTERP0_BASE2 + 0x00000090 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP0_BASE2 + [31:0] + read-write + + + + + INTERP0_POP_LANE0 + 0x00000094 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE0 + [31:0] + read-only + + + + + INTERP0_POP_LANE1 + 0x00000098 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE1 + [31:0] + read-only + + + + + INTERP0_POP_FULL + 0x0000009c + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_FULL + [31:0] + read-only + + + + + INTERP0_PEEK_LANE0 + 0x000000a0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP0_PEEK_LANE1 + 0x000000a4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP0_PEEK_FULL + 0x000000a8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_FULL + [31:0] + read-only + + + + + INTERP0_CTRL_LANE0 + 0x000000ac + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + BLEND + Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + by the 8 LSBs of lane 1 shift and mask value (a fractional number between + 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. + [21:21] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_CTRL_LANE1 + 0x000000b0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_ACCUM0_ADD + 0x000000b4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP0_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP0_ACCUM1_ADD + 0x000000b8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP0_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP0_BASE_1AND0 + 0x000000bc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP0_BASE_1AND0 + [31:0] + write-only + + + + + INTERP1_ACCUM0 + 0x000000c0 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP1_ACCUM0 + [31:0] + read-write + + + + + INTERP1_ACCUM1 + 0x000000c4 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP1_ACCUM1 + [31:0] + read-write + + + + + INTERP1_BASE0 + 0x000000c8 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP1_BASE0 + [31:0] + read-write + + + + + INTERP1_BASE1 + 0x000000cc + Read/write access to BASE1 register. + 0x00000000 + + + INTERP1_BASE1 + [31:0] + read-write + + + + + INTERP1_BASE2 + 0x000000d0 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP1_BASE2 + [31:0] + read-write + + + + + INTERP1_POP_LANE0 + 0x000000d4 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE0 + [31:0] + read-only + + + + + INTERP1_POP_LANE1 + 0x000000d8 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE1 + [31:0] + read-only + + + + + INTERP1_POP_FULL + 0x000000dc + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_FULL + [31:0] + read-only + + + + + INTERP1_PEEK_LANE0 + 0x000000e0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP1_PEEK_LANE1 + 0x000000e4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP1_PEEK_FULL + 0x000000e8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_FULL + [31:0] + read-only + + + + + INTERP1_CTRL_LANE0 + 0x000000ec + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + CLAMP + Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of + BASE0 and an upper bound of BASE1. + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + [22:22] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_CTRL_LANE1 + 0x000000f0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_ACCUM0_ADD + 0x000000f4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP1_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP1_ACCUM1_ADD + 0x000000f8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP1_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP1_BASE_1AND0 + 0x000000fc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP1_BASE_1AND0 + [31:0] + write-only + + + + + SPINLOCK0 + 0x00000100 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK0 + [31:0] + read-write + modify + + + + + SPINLOCK1 + 0x00000104 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK1 + [31:0] + read-write + modify + + + + + SPINLOCK2 + 0x00000108 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK2 + [31:0] + read-write + modify + + + + + SPINLOCK3 + 0x0000010c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK3 + [31:0] + read-write + modify + + + + + SPINLOCK4 + 0x00000110 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK4 + [31:0] + read-write + modify + + + + + SPINLOCK5 + 0x00000114 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK5 + [31:0] + read-write + modify + + + + + SPINLOCK6 + 0x00000118 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK6 + [31:0] + read-write + modify + + + + + SPINLOCK7 + 0x0000011c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK7 + [31:0] + read-write + modify + + + + + SPINLOCK8 + 0x00000120 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK8 + [31:0] + read-write + modify + + + + + SPINLOCK9 + 0x00000124 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK9 + [31:0] + read-write + modify + + + + + SPINLOCK10 + 0x00000128 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK10 + [31:0] + read-write + modify + + + + + SPINLOCK11 + 0x0000012c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK11 + [31:0] + read-write + modify + + + + + SPINLOCK12 + 0x00000130 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK12 + [31:0] + read-write + modify + + + + + SPINLOCK13 + 0x00000134 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK13 + [31:0] + read-write + modify + + + + + SPINLOCK14 + 0x00000138 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK14 + [31:0] + read-write + modify + + + + + SPINLOCK15 + 0x0000013c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK15 + [31:0] + read-write + modify + + + + + SPINLOCK16 + 0x00000140 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK16 + [31:0] + read-write + modify + + + + + SPINLOCK17 + 0x00000144 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK17 + [31:0] + read-write + modify + + + + + SPINLOCK18 + 0x00000148 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK18 + [31:0] + read-write + modify + + + + + SPINLOCK19 + 0x0000014c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK19 + [31:0] + read-write + modify + + + + + SPINLOCK20 + 0x00000150 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK20 + [31:0] + read-write + modify + + + + + SPINLOCK21 + 0x00000154 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK21 + [31:0] + read-write + modify + + + + + SPINLOCK22 + 0x00000158 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK22 + [31:0] + read-write + modify + + + + + SPINLOCK23 + 0x0000015c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK23 + [31:0] + read-write + modify + + + + + SPINLOCK24 + 0x00000160 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK24 + [31:0] + read-write + modify + + + + + SPINLOCK25 + 0x00000164 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK25 + [31:0] + read-write + modify + + + + + SPINLOCK26 + 0x00000168 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK26 + [31:0] + read-write + modify + + + + + SPINLOCK27 + 0x0000016c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK27 + [31:0] + read-write + modify + + + + + SPINLOCK28 + 0x00000170 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK28 + [31:0] + read-write + modify + + + + + SPINLOCK29 + 0x00000174 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK29 + [31:0] + read-write + modify + + + + + SPINLOCK30 + 0x00000178 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK30 + [31:0] + read-write + modify + + + + + SPINLOCK31 + 0x0000017c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK31 + [31:0] + read-write + modify + + + + + DOORBELL_OUT_SET + 0x00000180 + Trigger a doorbell interrupt on the opposite core. + + Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. + + Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. + 0x00000000 + + + DOORBELL_OUT_SET + [7:0] + read-write + + + + + DOORBELL_OUT_CLR + 0x00000184 + Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. + + Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. + + Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. + 0x00000000 + + + DOORBELL_OUT_CLR + [7:0] + read-write + oneToClear + + + + + DOORBELL_IN_SET + 0x00000188 + Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. + 0x00000000 + + + DOORBELL_IN_SET + [7:0] + read-write + + + + + DOORBELL_IN_CLR + 0x0000018c + Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. + + Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. + 0x00000000 + + + DOORBELL_IN_CLR + [7:0] + read-write + oneToClear + + + + + PERI_NONSEC + 0x00000190 + Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. + + This register is per-core, and is only present on the Secure SIO. + + Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. + 0x00000000 + + + TMDS + IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [5:5] + read-write + + + INTERP1 + If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [1:1] + read-write + + + INTERP0 + If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [0:0] + read-write + + + + + RISCV_SOFTIRQ + 0x000001a0 + Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. + + Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. + + It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. + 0x00000000 + + + CORE1_CLR + Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag. + [9:9] + read-write + + + CORE0_CLR + Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag. + [8:8] + read-write + + + CORE1_SET + Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag. + [1:1] + read-write + + + CORE0_SET + Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag. + [0:0] + read-write + + + + + MTIME_CTRL + 0x000001a4 + Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. + + Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. + 0x0000000d + + + DBGPAUSE_CORE1 + If 1, the timer pauses when core 1 is in the debug halt state. + [3:3] + read-write + + + DBGPAUSE_CORE0 + If 1, the timer pauses when core 0 is in the debug halt state. + [2:2] + read-write + + + FULLSPEED + If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input. + [1:1] + read-write + + + EN + Timer enable bit. When 0, the timer will not increment automatically. + [0:0] + read-write + + + + + MTIME + 0x000001b0 + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x00000000 + + + MTIME + [31:0] + read-write + + + + + MTIMEH + 0x000001b4 + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x00000000 + + + MTIMEH + [31:0] + read-write + + + + + MTIMECMP + 0x000001b8 + Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0xffffffff + + + MTIMECMP + [31:0] + read-write + + + + + MTIMECMPH + 0x000001bc + High half of RISC-V Machine-mode timer comparator. This register is core-local. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0xffffffff + + + MTIMECMPH + [31:0] + read-write + + + + + TMDS_CTRL + 0x000001c0 + Control register for TMDS encoder. + 0x00000000 + + + CLEAR_BALANCE + Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline. + [28:28] + write-only + + + PIX2_NOSHIFT + When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. + + This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling. + [27:27] + read-write + + + PIX_SHIFT + Shift applied to the colour data register with each read of a POP alias register. + + Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. + + Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.) + [26:24] + read-write + + + 0 + 0 + Do not shift the colour data register. + + + 1 + 1 + Shift the colour data register by 1 bit + + + 2 + 2 + Shift the colour data register by 2 bits + + + 4 + 3 + Shift the colour data register by 4 bits + + + 8 + 4 + Shift the colour data register by 8 bits + + + 16 + 5 + Shift the colour data register by 16 bits + + + + + INTERLEAVE + Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. + + When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. + + When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant. + [23:23] + read-write + + + L2_NBITS + Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [20:18] + read-write + + + L1_NBITS + Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [17:15] + read-write + + + L0_NBITS + Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [14:12] + read-write + + + L2_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input. + [11:8] + read-write + + + L1_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input. + [7:4] + read-write + + + L0_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input. + [3:0] + read-write + + + + + TMDS_WDATA + 0x000001c4 + Write-only access to the TMDS colour data register. + 0x00000000 + + + TMDS_WDATA + [31:0] + write-only + + + + + TMDS_PEEK_SINGLE + 0x000001c8 + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). + + The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. + 0x00000000 + + + TMDS_PEEK_SINGLE + [31:0] + read-only + modify + + + + + TMDS_POP_SINGLE + 0x000001cc + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. + + The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. + 0x00000000 + + + TMDS_POP_SINGLE + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L0 + 0x000001d0 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L0 + 0x000001d4 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L1 + 0x000001d8 + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L1 + 0x000001dc + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L2 + 0x000001e0 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L2 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L2 + 0x000001e4 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L2 + [31:0] + read-only + modify + + + + + + + SIO_NS + 0xd0020000 + + + BOOTRAM + Additional registers mapped adjacent to the bootram, for use by the bootrom. + 0x400e0000 + + 0 + 2092 + registers + + + + WRITE_ONCE0 + 0x00000800 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x00000000 + + + WRITE_ONCE0 + [31:0] + read-write + + + + + WRITE_ONCE1 + 0x00000804 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x00000000 + + + WRITE_ONCE1 + [31:0] + read-write + + + + + BOOTLOCK_STAT + 0x00000808 + Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. + 0x000000ff + + + BOOTLOCK_STAT + [7:0] + read-write + + + + + BOOTLOCK0 + 0x0000080c + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK0 + [31:0] + read-write + + + + + BOOTLOCK1 + 0x00000810 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK1 + [31:0] + read-write + + + + + BOOTLOCK2 + 0x00000814 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK2 + [31:0] + read-write + + + + + BOOTLOCK3 + 0x00000818 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK3 + [31:0] + read-write + + + + + BOOTLOCK4 + 0x0000081c + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK4 + [31:0] + read-write + + + + + BOOTLOCK5 + 0x00000820 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK5 + [31:0] + read-write + + + + + BOOTLOCK6 + 0x00000824 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK6 + [31:0] + read-write + + + + + BOOTLOCK7 + 0x00000828 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK7 + [31:0] + read-write + + + + + + + CORESIGHT_TRACE + Coresight block - RP specific registers + 0x50700000 + + 0 + 8 + registers + + + + CTRL_STATUS + 0x00000000 + Control and status register + 0x00000001 + + + TRACE_CAPTURE_FIFO_OVERFLOW + This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit. + [1:1] + read-write + + + TRACE_CAPTURE_FIFO_FLUSH + Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. + + Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. + + Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU. + [0:0] + read-write + + + + + TRACE_CAPTURE_FIFO + 0x00000004 + FIFO for trace data captured from the TPIU + 0x00000000 + + + RDATA + Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. + + Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: + + * TPIU TRACECTL output is low (normal trace data) + + * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) + + These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices + + The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock. + [31:0] + read-only + modify + + + + + + + USB + USB FS/LS controller device registers + 0x50110000 + + 0 + 280 + registers + + + USBCTRL_IRQ + 14 + + + + ADDR_ENDP + 0x00000000 + Device address and endpoint control + 0x00000000 + + + ENDPOINT + Device endpoint to send data to. Only valid for HOST mode. + [19:16] + read-write + + + ADDRESS + In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. + [6:0] + read-write + + + + + ADDR_ENDP1 + 0x00000004 + Interrupt endpoint 1. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP2 + 0x00000008 + Interrupt endpoint 2. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP3 + 0x0000000c + Interrupt endpoint 3. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP4 + 0x00000010 + Interrupt endpoint 4. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP5 + 0x00000014 + Interrupt endpoint 5. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP6 + 0x00000018 + Interrupt endpoint 6. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP7 + 0x0000001c + Interrupt endpoint 7. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP8 + 0x00000020 + Interrupt endpoint 8. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP9 + 0x00000024 + Interrupt endpoint 9. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP10 + 0x00000028 + Interrupt endpoint 10. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP11 + 0x0000002c + Interrupt endpoint 11. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP12 + 0x00000030 + Interrupt endpoint 12. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP13 + 0x00000034 + Interrupt endpoint 13. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP14 + 0x00000038 + Interrupt endpoint 14. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP15 + 0x0000003c + Interrupt endpoint 15. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + MAIN_CTRL + 0x00000040 + Main control register + 0x00000004 + + + SIM_TIMING + Reduced timings for simulation + [31:31] + read-write + + + PHY_ISO + Isolates USB phy after controller power-up + Remove isolation once software has configured the controller + Not isolated = 0, Isolated = 1 + [2:2] + read-write + + + HOST_NDEVICE + Device mode = 0, Host mode = 1 + [1:1] + read-write + + + CONTROLLER_EN + Enable controller + [0:0] + read-write + + + + + SOF_WR + 0x00000044 + Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + 0x00000000 + + + COUNT + [10:0] + write-only + + + + + SOF_RD + 0x00000048 + Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + 0x00000000 + + + COUNT + [10:0] + read-only + + + + + SIE_CTRL + 0x0000004c + SIE control register + 0x00008000 + + + EP0_INT_STALL + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + [31:31] + read-write + + + EP0_DOUBLE_BUF + Device: EP0 single buffered = 0, double buffered = 1 + [30:30] + read-write + + + EP0_INT_1BUF + Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + [29:29] + read-write + + + EP0_INT_2BUF + Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + [28:28] + read-write + + + EP0_INT_NAK + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + [27:27] + read-write + + + DIRECT_EN + Direct bus drive enable + [26:26] + read-write + + + DIRECT_DP + Direct control of DP + [25:25] + read-write + + + DIRECT_DM + Direct control of DM + [24:24] + read-write + + + EP0_STOP_ON_SHORT_PACKET + Device: Stop EP0 on a short packet. + [19:19] + read-write + + + TRANSCEIVER_PD + Power down bus transceiver + [18:18] + read-write + + + RPU_OPT + Device: Pull-up strength (0=1K2, 1=2k3) + [17:17] + read-write + + + PULLUP_EN + Device: Enable pull up resistor + [16:16] + read-write + + + PULLDOWN_EN + Host: Enable pull down resistors + [15:15] + read-write + + + RESET_BUS + Host: Reset bus + [13:13] + write-only + + + RESUME + Device: Remote wakeup. Device can initiate its own resume after suspend. + [12:12] + write-only + + + VBUS_EN + Host: Enable VBUS + [11:11] + read-write + + + KEEP_ALIVE_EN + Host: Enable keep alive packet (for low speed bus) + [10:10] + read-write + + + SOF_EN + Host: Enable SOF generation (for full speed bus) + [9:9] + read-write + + + SOF_SYNC + Host: Delay packet(s) until after SOF + [8:8] + read-write + + + PREAMBLE_EN + Host: Preable enable for LS device on FS hub + [6:6] + read-write + + + STOP_TRANS + Host: Stop transaction + [4:4] + write-only + + + RECEIVE_DATA + Host: Receive transaction (IN to host) + [3:3] + read-write + + + SEND_DATA + Host: Send transaction (OUT from host) + [2:2] + read-write + + + SEND_SETUP + Host: Send Setup packet + [1:1] + read-write + + + START_TRANS + Host: Start transaction + [0:0] + write-only + + + + + SIE_STATUS + 0x00000050 + SIE status register + 0x00000000 + + + DATA_SEQ_ERROR + Data Sequence Error. + + The device can raise a sequence error in the following conditions: + + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM + + The host can raise a data sequence error in the following conditions: + + * An IN packet from the device has the wrong data PID + [31:31] + read-write + oneToClear + + + ACK_REC + ACK received. Raised by both host and device. + [30:30] + read-write + oneToClear + + + STALL_REC + Host: STALL received + [29:29] + read-write + oneToClear + + + NAK_REC + Host: NAK received + [28:28] + read-write + oneToClear + + + RX_TIMEOUT + RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. + [27:27] + read-write + oneToClear + + + RX_OVERFLOW + RX overflow is raised by the Serial RX engine if the incoming data is too fast. + [26:26] + read-write + oneToClear + + + BIT_STUFF_ERROR + Bit Stuff Error. Raised by the Serial RX engine. + [25:25] + read-write + oneToClear + + + CRC_ERROR + CRC Error. Raised by the Serial RX engine. + [24:24] + read-write + oneToClear + + + ENDPOINT_ERROR + An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error. + [23:23] + read-write + oneToClear + + + BUS_RESET + Device: bus reset received + [19:19] + read-write + oneToClear + + + TRANS_COMPLETE + Transaction complete. + + Raised by device if: + + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register + + Raised by host if: + + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set + [18:18] + read-write + oneToClear + + + SETUP_REC + Device: Setup packet received + [17:17] + read-write + oneToClear + + + CONNECTED + Device: connected + [16:16] + read-only + + + RX_SHORT_PACKET + Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early. + [12:12] + read-write + oneToClear + + + RESUME + Host: Device has initiated a remote resume. Device: host has initiated a resume. + [11:11] + read-write + oneToClear + + + VBUS_OVER_CURR + VBUS over current detected + [10:10] + read-only + + + SPEED + Host: device speed. Disconnected = 00, LS = 01, FS = 10 + [9:8] + read-only + + + SUSPENDED + Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled. + [4:4] + read-write + oneToClear + + + LINE_STATE + USB bus line state + [3:2] + read-only + + + VBUS_DETECTED + Device: VBUS Detected + [0:0] + read-only + + + + + INT_EP_CTRL + 0x00000054 + interrupt endpoint control register + 0x00000000 + + + INT_EP_ACTIVE + Host: Enable interrupt endpoint 1 -> 15 + [15:1] + read-write + + + + + BUFF_STATUS + 0x00000058 + Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + BUFF_CPU_SHOULD_HANDLE + 0x0000005c + Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + 0x00000000 + + + EP15_OUT + [31:31] + read-only + + + EP15_IN + [30:30] + read-only + + + EP14_OUT + [29:29] + read-only + + + EP14_IN + [28:28] + read-only + + + EP13_OUT + [27:27] + read-only + + + EP13_IN + [26:26] + read-only + + + EP12_OUT + [25:25] + read-only + + + EP12_IN + [24:24] + read-only + + + EP11_OUT + [23:23] + read-only + + + EP11_IN + [22:22] + read-only + + + EP10_OUT + [21:21] + read-only + + + EP10_IN + [20:20] + read-only + + + EP9_OUT + [19:19] + read-only + + + EP9_IN + [18:18] + read-only + + + EP8_OUT + [17:17] + read-only + + + EP8_IN + [16:16] + read-only + + + EP7_OUT + [15:15] + read-only + + + EP7_IN + [14:14] + read-only + + + EP6_OUT + [13:13] + read-only + + + EP6_IN + [12:12] + read-only + + + EP5_OUT + [11:11] + read-only + + + EP5_IN + [10:10] + read-only + + + EP4_OUT + [9:9] + read-only + + + EP4_IN + [8:8] + read-only + + + EP3_OUT + [7:7] + read-only + + + EP3_IN + [6:6] + read-only + + + EP2_OUT + [5:5] + read-only + + + EP2_IN + [4:4] + read-only + + + EP1_OUT + [3:3] + read-only + + + EP1_IN + [2:2] + read-only + + + EP0_OUT + [1:1] + read-only + + + EP0_IN + [0:0] + read-only + + + + + EP_ABORT + 0x00000060 + Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + + + EP15_IN + [30:30] + read-write + + + EP14_OUT + [29:29] + read-write + + + EP14_IN + [28:28] + read-write + + + EP13_OUT + [27:27] + read-write + + + EP13_IN + [26:26] + read-write + + + EP12_OUT + [25:25] + read-write + + + EP12_IN + [24:24] + read-write + + + EP11_OUT + [23:23] + read-write + + + EP11_IN + [22:22] + read-write + + + EP10_OUT + [21:21] + read-write + + + EP10_IN + [20:20] + read-write + + + EP9_OUT + [19:19] + read-write + + + EP9_IN + [18:18] + read-write + + + EP8_OUT + [17:17] + read-write + + + EP8_IN + [16:16] + read-write + + + EP7_OUT + [15:15] + read-write + + + EP7_IN + [14:14] + read-write + + + EP6_OUT + [13:13] + read-write + + + EP6_IN + [12:12] + read-write + + + EP5_OUT + [11:11] + read-write + + + EP5_IN + [10:10] + read-write + + + EP4_OUT + [9:9] + read-write + + + EP4_IN + [8:8] + read-write + + + EP3_OUT + [7:7] + read-write + + + EP3_IN + [6:6] + read-write + + + EP2_OUT + [5:5] + read-write + + + EP2_IN + [4:4] + read-write + + + EP1_OUT + [3:3] + read-write + + + EP1_IN + [2:2] + read-write + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + EP_ABORT_DONE + 0x00000064 + Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + EP_STALL_ARM + 0x00000068 + Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + 0x00000000 + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + NAK_POLL + 0x0000006c + Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + 0x00100010 + + + RETRY_COUNT_HI + Bits 9:6 of nak_retry count + [31:28] + read-only + + + EPX_STOPPED_ON_NAK + EPX polling has stopped because a nak was received + [27:27] + read-write + oneToClear + + + STOP_EPX_ON_NAK + Stop polling epx when a nak is received + [26:26] + read-write + + + DELAY_FS + NAK polling interval for a full speed device + [25:16] + read-write + + + RETRY_COUNT_LO + Bits 5:0 of nak_retry_count + [15:10] + read-only + + + DELAY_LS + NAK polling interval for a low speed device + [9:0] + read-write + + + + + EP_STATUS_STALL_NAK + 0x00000070 + Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + USB_MUXING + 0x00000074 + Where to connect the USB controller. Should be to_phy by default. + 0x00000001 + + + SWAP_DPDM + Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. + This is done at a low level so overrides all other controls. + [31:31] + read-write + + + USBPHY_AS_GPIO + Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller. + [4:4] + read-write + + + SOFTCON + [3:3] + read-write + + + TO_DIGITAL_PAD + [2:2] + read-write + + + TO_EXTPHY + [1:1] + read-write + + + TO_PHY + [0:0] + read-write + + + + + USB_PWR + 0x00000078 + Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + 0x00000000 + + + OVERCURR_DETECT_EN + [5:5] + read-write + + + OVERCURR_DETECT + [4:4] + read-write + + + VBUS_DETECT_OVERRIDE_EN + [3:3] + read-write + + + VBUS_DETECT + [2:2] + read-write + + + VBUS_EN_OVERRIDE_EN + [1:1] + read-write + + + VBUS_EN + [0:0] + read-write + + + + + USBPHY_DIRECT + 0x0000007c + This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + 0x00000000 + + + RX_DM_OVERRIDE + Override rx_dm value into controller + [25:25] + read-write + + + RX_DP_OVERRIDE + Override rx_dp value into controller + [24:24] + read-write + + + RX_DD_OVERRIDE + Override rx_dd value into controller + [23:23] + read-write + + + DM_OVV + DM over voltage + [22:22] + read-only + + + DP_OVV + DP over voltage + [21:21] + read-only + + + DM_OVCN + DM overcurrent + [20:20] + read-only + + + DP_OVCN + DP overcurrent + [19:19] + read-only + + + RX_DM + DPM pin state + [18:18] + read-only + + + RX_DP + DPP pin state + [17:17] + read-only + + + RX_DD + Differential RX + [16:16] + read-only + + + TX_DIFFMODE + TX_DIFFMODE=0: Single ended mode + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) + [15:15] + read-write + + + TX_FSSLEW + TX_FSSLEW=0: Low speed slew rate + TX_FSSLEW=1: Full speed slew rate + [14:14] + read-write + + + TX_PD + TX power down override (if override enable is set). 1 = powered down. + [13:13] + read-write + + + RX_PD + RX power down override (if override enable is set). 1 = powered down. + [12:12] + read-write + + + TX_DM + Output data. TX_DIFFMODE=1, Ignored + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + [11:11] + read-write + + + TX_DP + Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + [10:10] + read-write + + + TX_DM_OE + Output enable. If TX_DIFFMODE=1, Ignored. + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + [9:9] + read-write + + + TX_DP_OE + Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + [8:8] + read-write + + + DM_PULLDN_EN + DM pull down enable + [6:6] + read-write + + + DM_PULLUP_EN + DM pull up enable + [5:5] + read-write + + + DM_PULLUP_HISEL + Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [4:4] + read-write + + + DP_PULLDN_EN + DP pull down enable + [2:2] + read-write + + + DP_PULLUP_EN + DP pull up enable + [1:1] + read-write + + + DP_PULLUP_HISEL + Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [0:0] + read-write + + + + + USBPHY_DIRECT_OVERRIDE + 0x00000080 + Override enable for each control in usbphy_direct + 0x00000000 + + + RX_DM_OVERRIDE_EN + [18:18] + read-write + + + RX_DP_OVERRIDE_EN + [17:17] + read-write + + + RX_DD_OVERRIDE_EN + [16:16] + read-write + + + TX_DIFFMODE_OVERRIDE_EN + [15:15] + read-write + + + DM_PULLUP_OVERRIDE_EN + [12:12] + read-write + + + TX_FSSLEW_OVERRIDE_EN + [11:11] + read-write + + + TX_PD_OVERRIDE_EN + [10:10] + read-write + + + RX_PD_OVERRIDE_EN + [9:9] + read-write + + + TX_DM_OVERRIDE_EN + [8:8] + read-write + + + TX_DP_OVERRIDE_EN + [7:7] + read-write + + + TX_DM_OE_OVERRIDE_EN + [6:6] + read-write + + + TX_DP_OE_OVERRIDE_EN + [5:5] + read-write + + + DM_PULLDN_EN_OVERRIDE_EN + [4:4] + read-write + + + DP_PULLDN_EN_OVERRIDE_EN + [3:3] + read-write + + + DP_PULLUP_EN_OVERRIDE_EN + [2:2] + read-write + + + DM_PULLUP_HISEL_OVERRIDE_EN + [1:1] + read-write + + + DP_PULLUP_HISEL_OVERRIDE_EN + [0:0] + read-write + + + + + USBPHY_TRIM + 0x00000084 + Used to adjust trim values of USB phy pull down resistors. + 0x00001f1f + + + DM_PULLDN_TRIM + Value to drive to USB PHY + DM pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [12:8] + read-write + + + DP_PULLDN_TRIM + Value to drive to USB PHY + DP pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [4:0] + read-write + + + + + LINESTATE_TUNING + 0x00000088 + Used for debug only. + 0x000000f8 + + + SPARE_FIX + [11:8] + read-write + + + DEV_LS_WAKE_FIX + Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer + [7:7] + read-write + + + DEV_RX_ERR_QUIESCE + Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet. + [6:6] + read-write + + + SIE_RX_CHATTER_SE0_FIX + RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as + 8 consecutive idle bits. + [5:5] + read-write + + + SIE_RX_BITSTUFF_FIX + RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to + avoid a hang during certain packet phases. + [4:4] + read-write + + + DEV_BUFF_CONTROL_DOUBLE_READ_FIX + Device - the controller FSM performs two reads of the buffer status memory address to + avoid sampling metastable data. An enabled buffer is only used if both reads match. + [3:3] + read-write + + + MULTI_HUB_FIX + Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays. + [2:2] + read-write + + + LINESTATE_DELAY + Device/Host - add an extra 1-bit debounce of linestate sampling. + [1:1] + read-write + + + RCV_DELAY + Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs. + [0:0] + read-write + + + + + INTR + 0x0000008c + Raw Interrupts + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + INTE + 0x00000090 + Interrupt Enable + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTF + 0x00000094 + Interrupt Force + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTS + 0x00000098 + Interrupt status after masking & forcing + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + SOF_TIMESTAMP_RAW + 0x00000100 + Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. + 0x00000000 + + + SOF_TIMESTAMP_RAW + [20:0] + read-only + + + + + SOF_TIMESTAMP_LAST + 0x00000104 + Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. + 0x00000000 + + + SOF_TIMESTAMP_LAST + [20:0] + read-only + + + + + SM_STATE + 0x00000108 + 0x00000000 + + + RX_DASM + [11:8] + read-only + + + BC_STATE + [7:5] + read-only + + + STATE + [4:0] + read-only + + + + + EP_TX_ERROR + 0x0000010c + TX error count for each endpoint. Write to each field to reset the counter to 0. + 0x00000000 + + + EP15 + [31:30] + read-write + oneToClear + + + EP14 + [29:28] + read-write + oneToClear + + + EP13 + [27:26] + read-write + oneToClear + + + EP12 + [25:24] + read-write + oneToClear + + + EP11 + [23:22] + read-write + oneToClear + + + EP10 + [21:20] + read-write + oneToClear + + + EP9 + [19:18] + read-write + oneToClear + + + EP8 + [17:16] + read-write + oneToClear + + + EP7 + [15:14] + read-write + oneToClear + + + EP6 + [13:12] + read-write + oneToClear + + + EP5 + [11:10] + read-write + oneToClear + + + EP4 + [9:8] + read-write + oneToClear + + + EP3 + [7:6] + read-write + oneToClear + + + EP2 + [5:4] + read-write + oneToClear + + + EP1 + [3:2] + read-write + oneToClear + + + EP0 + [1:0] + read-write + oneToClear + + + + + EP_RX_ERROR + 0x00000110 + RX error count for each endpoint. Write to each field to reset the counter to 0. + 0x00000000 + + + EP15_SEQ + [31:31] + read-write + oneToClear + + + EP15_TRANSACTION + [30:30] + read-write + oneToClear + + + EP14_SEQ + [29:29] + read-write + oneToClear + + + EP14_TRANSACTION + [28:28] + read-write + oneToClear + + + EP13_SEQ + [27:27] + read-write + oneToClear + + + EP13_TRANSACTION + [26:26] + read-write + oneToClear + + + EP12_SEQ + [25:25] + read-write + oneToClear + + + EP12_TRANSACTION + [24:24] + read-write + oneToClear + + + EP11_SEQ + [23:23] + read-write + oneToClear + + + EP11_TRANSACTION + [22:22] + read-write + oneToClear + + + EP10_SEQ + [21:21] + read-write + oneToClear + + + EP10_TRANSACTION + [20:20] + read-write + oneToClear + + + EP9_SEQ + [19:19] + read-write + oneToClear + + + EP9_TRANSACTION + [18:18] + read-write + oneToClear + + + EP8_SEQ + [17:17] + read-write + oneToClear + + + EP8_TRANSACTION + [16:16] + read-write + oneToClear + + + EP7_SEQ + [15:15] + read-write + oneToClear + + + EP7_TRANSACTION + [14:14] + read-write + oneToClear + + + EP6_SEQ + [13:13] + read-write + oneToClear + + + EP6_TRANSACTION + [12:12] + read-write + oneToClear + + + EP5_SEQ + [11:11] + read-write + oneToClear + + + EP5_TRANSACTION + [10:10] + read-write + oneToClear + + + EP4_SEQ + [9:9] + read-write + oneToClear + + + EP4_TRANSACTION + [8:8] + read-write + oneToClear + + + EP3_SEQ + [7:7] + read-write + oneToClear + + + EP3_TRANSACTION + [6:6] + read-write + oneToClear + + + EP2_SEQ + [5:5] + read-write + oneToClear + + + EP2_TRANSACTION + [4:4] + read-write + oneToClear + + + EP1_SEQ + [3:3] + read-write + oneToClear + + + EP1_TRANSACTION + [2:2] + read-write + oneToClear + + + EP0_SEQ + [1:1] + read-write + oneToClear + + + EP0_TRANSACTION + [0:0] + read-write + oneToClear + + + + + DEV_SM_WATCHDOG + 0x00000114 + Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. + Set limit while enable is low and then set the enable. + 0x00000000 + + + FIRED + [20:20] + read-write + oneToClear + + + RESET + Set to 1 to forcibly reset the device state machine on watchdog expiry + [19:19] + read-write + + + ENABLE + [18:18] + read-write + + + LIMIT + [17:0] + read-write + + + + + + + TRNG + ARM TrustZone RNG register block + 0x400f0000 + + 0 + 492 + registers + + + TRNG_IRQ + 39 + + + + RNG_IMR + 0x00000100 + Interrupt masking. + 0x0000000f + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [3:3] + read-write + + + CRNGT_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [2:2] + read-write + + + AUTOCORR_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [1:1] + read-write + + + EHR_VALID_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [0:0] + read-write + + + + + RNG_ISR + 0x00000104 + RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE. + [3:3] + read-only + + + CRNGT_ERR + 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal. + [2:2] + read-only + + + AUTOCORR_ERR + 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset. + [1:1] + read-only + + + EHR_VALID + 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read. + [0:0] + read-only + + + + + RNG_ICR + 0x00000108 + Interrupt/status bit clear Register. + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [3:3] + read-write + + + CRNGT_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [2:2] + read-write + + + AUTOCORR_ERR + Cannot be cleared by SW! Only RNG reset clears this bit. + [1:1] + read-write + + + EHR_VALID + Write 1'b1 - clear corresponding bit in RNG_ISR. + [0:0] + read-write + + + + + TRNG_CONFIG + 0x0000010c + Selecting the inverter-chain length. + 0x00000000 + + + RESERVED + RESERVED + [31:2] + read-only + + + RND_SRC_SEL + Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source). + [1:0] + read-write + + + + + TRNG_VALID + 0x00000110 + 192 bit collection indication. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + EHR_VALID + 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register. + [0:0] + read-only + + + + + EHR_DATA0 + 0x00000114 + RNG collected bits. + 0x00000000 + + + EHR_DATA0 + Bits [31:0] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA1 + 0x00000118 + RNG collected bits. + 0x00000000 + + + EHR_DATA1 + Bits [63:32] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA2 + 0x0000011c + RNG collected bits. + 0x00000000 + + + EHR_DATA2 + Bits [95:64] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA3 + 0x00000120 + RNG collected bits. + 0x00000000 + + + EHR_DATA3 + Bits [127:96] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA4 + 0x00000124 + RNG collected bits. + 0x00000000 + + + EHR_DATA4 + Bits [159:128] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA5 + 0x00000128 + RNG collected bits. + 0x00000000 + + + EHR_DATA5 + Bits [191:160] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + RND_SOURCE_ENABLE + 0x0000012c + Enable signal for the random source. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RND_SRC_EN + * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled + [0:0] + read-write + + + + + SAMPLE_CNT1 + 0x00000130 + Counts clocks between sampling of random bit. + 0x0000ffff + + + SAMPLE_CNTR1 + Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen + [31:0] + read-write + + + + + AUTOCORR_STATISTIC + 0x00000134 + Statistic about Autocorrelation test activations. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [21:14] + read-write + + + AUTOCORR_TRYS + Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [13:0] + read-write + + + + + TRNG_DEBUG_CONTROL + 0x00000138 + Debug register. + 0x00000000 + + + AUTO_CORRELATE_BYPASS + When set, the autocorrelation test in the TRNG module is bypassed. + [3:3] + read-write + + + TRNG_CRNGT_BYPASS + When set, the CRNGT test in the RNG is bypassed. + [2:2] + read-write + + + VNC_BYPASS + When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test). + [1:1] + read-write + + + RESERVED + N/A + [0:0] + read-only + + + + + TRNG_SW_RESET + 0x00000140 + Generate internal SW reset within the RNG block. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_SW_RESET + Writing 1'b1 to this register causes an internal RNG reset. + [0:0] + read-write + + + + + RNG_DEBUG_EN_INPUT + 0x000001b4 + Enable the RNG debug mode + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RNG_DEBUG_EN + * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled + [0:0] + read-write + + + + + TRNG_BUSY + 0x000001b8 + RNG Busy indication. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_BUSY + Reflects rng_busy status. + [0:0] + read-only + + + + + RST_BITS_COUNTER + 0x000001bc + Reset the counter of collected bits in the RNG. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RST_BITS_COUNTER + Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place. + [0:0] + read-write + + + + + RNG_VERSION + 0x000001c0 + Displays the version settings of the TRNG. + 0x00000000 + + + RESERVED + RESERVED + [31:8] + read-only + + + RNG_USE_5_SBOXES + * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES + [7:7] + read-only + + + RESEEDING_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [6:6] + read-only + + + KAT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [5:5] + read-only + + + PRNG_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [4:4] + read-only + + + TRNG_TESTS_BYPASS_EN + * 1'b1 - Exists. *1'b0 - Does not exist + [3:3] + read-only + + + AUTOCORR_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [2:2] + read-only + + + CRNGT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [1:1] + read-only + + + EHR_WIDTH_192 + * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR + [0:0] + read-only + + + + + RNG_BIST_CNTR_0 + 0x000001e0 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_1 + 0x000001e4 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_2 + 0x000001e8 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + + + GLITCH_DETECTOR + Glitch detector controls + 0x40158000 + + 0 + 24 + registers + + + + ARM + 0x00000000 + Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. + + Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. + + This register is Secure read/write only. + 0x00005bad + + + ARM + [15:0] + read-write + + + no + 23469 + Do not force the glitch detectors to be armed + + + yes + 0 + Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) + + + + + + + DISARM + 0x00000004 + 0x00000000 + + + DISARM + Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. + + This register is Secure read/write only. + [15:0] + read-write + + + no + 0 + Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) + + + yes + 56495 + Disarm the glitch detectors + + + + + + + SENSITIVITY + 0x00000008 + Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. + + This register is Secure read/write only. + 0x00000000 + + + DEFAULT + [31:24] + read-write + + + yes + 0 + Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) + + + no + 222 + Do not use the default sensitivity configured in OTP. Instead use the value from this register. + + + + + DET3_INV + Must be the inverse of DET3, else the default value is used. + [15:14] + read-write + + + DET2_INV + Must be the inverse of DET2, else the default value is used. + [13:12] + read-write + + + DET1_INV + Must be the inverse of DET1, else the default value is used. + [11:10] + read-write + + + DET0_INV + Must be the inverse of DET0, else the default value is used. + [9:8] + read-write + + + DET3 + Set sensitivity for detector 3. Higher values are more sensitive. + [7:6] + read-write + + + DET2 + Set sensitivity for detector 2. Higher values are more sensitive. + [5:4] + read-write + + + DET1 + Set sensitivity for detector 1. Higher values are more sensitive. + [3:2] + read-write + + + DET0 + Set sensitivity for detector 0. Higher values are more sensitive. + [1:0] + read-write + + + + + LOCK + 0x0000000c + 0x00000000 + + + LOCK + Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only. + [7:0] + read-write + + + + + TRIG_STATUS + 0x00000010 + Set when a detector output triggers. Write-1-clear. + + (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) + + This register is Secure read/write only. + 0x00000000 + + + DET3 + [3:3] + read-write + oneToClear + + + DET2 + [2:2] + read-write + oneToClear + + + DET1 + [1:1] + read-write + oneToClear + + + DET0 + [0:0] + read-write + oneToClear + + + + + TRIG_FORCE + 0x00000014 + Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. + + If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. + + This register is Secure read/write only. + 0x00000000 + + + TRIG_FORCE + [3:0] + write-only + + + + + + + OTP + SNPS OTP control IF (SBPI and RPi wrapper control) + 0x40120000 + + 0 + 372 + registers + + + OTP_IRQ + 38 + + + + SW_LOCK0 + 0x00000000 + Software lock register for page 0. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK1 + 0x00000004 + Software lock register for page 1. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK2 + 0x00000008 + Software lock register for page 2. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK3 + 0x0000000c + Software lock register for page 3. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK4 + 0x00000010 + Software lock register for page 4. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK5 + 0x00000014 + Software lock register for page 5. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK6 + 0x00000018 + Software lock register for page 6. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK7 + 0x0000001c + Software lock register for page 7. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK8 + 0x00000020 + Software lock register for page 8. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK9 + 0x00000024 + Software lock register for page 9. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK10 + 0x00000028 + Software lock register for page 10. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK11 + 0x0000002c + Software lock register for page 11. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK12 + 0x00000030 + Software lock register for page 12. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK13 + 0x00000034 + Software lock register for page 13. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK14 + 0x00000038 + Software lock register for page 14. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK15 + 0x0000003c + Software lock register for page 15. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK16 + 0x00000040 + Software lock register for page 16. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK17 + 0x00000044 + Software lock register for page 17. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK18 + 0x00000048 + Software lock register for page 18. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK19 + 0x0000004c + Software lock register for page 19. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK20 + 0x00000050 + Software lock register for page 20. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK21 + 0x00000054 + Software lock register for page 21. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK22 + 0x00000058 + Software lock register for page 22. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK23 + 0x0000005c + Software lock register for page 23. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK24 + 0x00000060 + Software lock register for page 24. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK25 + 0x00000064 + Software lock register for page 25. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK26 + 0x00000068 + Software lock register for page 26. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK27 + 0x0000006c + Software lock register for page 27. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK28 + 0x00000070 + Software lock register for page 28. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK29 + 0x00000074 + Software lock register for page 29. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK30 + 0x00000078 + Software lock register for page 30. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK31 + 0x0000007c + Software lock register for page 31. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK32 + 0x00000080 + Software lock register for page 32. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK33 + 0x00000084 + Software lock register for page 33. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK34 + 0x00000088 + Software lock register for page 34. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK35 + 0x0000008c + Software lock register for page 35. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK36 + 0x00000090 + Software lock register for page 36. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK37 + 0x00000094 + Software lock register for page 37. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK38 + 0x00000098 + Software lock register for page 38. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK39 + 0x0000009c + Software lock register for page 39. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK40 + 0x000000a0 + Software lock register for page 40. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK41 + 0x000000a4 + Software lock register for page 41. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK42 + 0x000000a8 + Software lock register for page 42. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK43 + 0x000000ac + Software lock register for page 43. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK44 + 0x000000b0 + Software lock register for page 44. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK45 + 0x000000b4 + Software lock register for page 45. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK46 + 0x000000b8 + Software lock register for page 46. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK47 + 0x000000bc + Software lock register for page 47. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK48 + 0x000000c0 + Software lock register for page 48. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK49 + 0x000000c4 + Software lock register for page 49. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK50 + 0x000000c8 + Software lock register for page 50. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK51 + 0x000000cc + Software lock register for page 51. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK52 + 0x000000d0 + Software lock register for page 52. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK53 + 0x000000d4 + Software lock register for page 53. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK54 + 0x000000d8 + Software lock register for page 54. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK55 + 0x000000dc + Software lock register for page 55. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK56 + 0x000000e0 + Software lock register for page 56. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK57 + 0x000000e4 + Software lock register for page 57. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK58 + 0x000000e8 + Software lock register for page 58. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK59 + 0x000000ec + Software lock register for page 59. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK60 + 0x000000f0 + Software lock register for page 60. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK61 + 0x000000f4 + Software lock register for page 61. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK62 + 0x000000f8 + Software lock register for page 62. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK63 + 0x000000fc + Software lock register for page 63. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SBPI_INSTR + 0x00000100 + Dispatch instructions to the SBPI interface, used for programming the OTP fuses. + 0x00000000 + + + EXEC + Execute instruction + [30:30] + write-only + + + IS_WR + Payload type is write + [29:29] + read-write + + + HAS_PAYLOAD + Instruction has payload (data to be written or to be read) + [28:28] + read-write + + + PAYLOAD_SIZE_M1 + Instruction payload size in bytes minus 1 + [27:24] + read-write + + + TARGET + Instruction target, it can be PMC (0x3a) or DAP (0x02) + [23:16] + read-write + + + CMD + [15:8] + read-write + + + SHORT_WDATA + wdata to be used only when payload_size_m1=0 + [7:0] + read-write + + + + + SBPI_WDATA_0 + 0x00000104 + SBPI write payload bytes 3..0 + 0x00000000 + + + SBPI_WDATA_0 + [31:0] + read-write + + + + + SBPI_WDATA_1 + 0x00000108 + SBPI write payload bytes 7..4 + 0x00000000 + + + SBPI_WDATA_1 + [31:0] + read-write + + + + + SBPI_WDATA_2 + 0x0000010c + SBPI write payload bytes 11..8 + 0x00000000 + + + SBPI_WDATA_2 + [31:0] + read-write + + + + + SBPI_WDATA_3 + 0x00000110 + SBPI write payload bytes 15..12 + 0x00000000 + + + SBPI_WDATA_3 + [31:0] + read-write + + + + + SBPI_RDATA_0 + 0x00000114 + Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_0 + [31:0] + read-only + modify + + + + + SBPI_RDATA_1 + 0x00000118 + Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_1 + [31:0] + read-only + modify + + + + + SBPI_RDATA_2 + 0x0000011c + Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_2 + [31:0] + read-only + modify + + + + + SBPI_RDATA_3 + 0x00000120 + Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_3 + [31:0] + read-only + modify + + + + + SBPI_STATUS + 0x00000124 + 0x00000000 + + + MISO + SBPI MISO (master in - slave out): response from SBPI + [23:16] + read-only + + + FLAG + SBPI flag + [12:12] + read-only + + + INSTR_MISS + Last instruction missed (dropped), as the previous has not finished running + [8:8] + read-write + oneToClear + + + INSTR_DONE + Last instruction done + [4:4] + read-write + oneToClear + + + RDATA_VLD + Read command has returned data + [0:0] + read-write + oneToClear + + + + + USR + 0x00000128 + Controls for APB data read interface (USER interface) + 0x00000001 + + + PD + Power-down; 1 disables current reference. Must be 0 to read data from the OTP. + [4:4] + read-write + + + DCTRL + 1 enables USER interface; 0 disables USER interface (enables SBPI). + + This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted. + [0:0] + read-write + + + + + DBG + 0x0000012c + Debug for OTP power-on state machine + 0x00000000 + + + CUSTOMER_RMA_FLAG + The chip is in RMA mode + [12:12] + read-only + + + PSM_STATE + Monitor the PSM FSM's state + [7:4] + read-only + + + ROSC_UP + Ring oscillator is up and running + [3:3] + read-only + + + ROSC_UP_SEEN + Ring oscillator was seen up and running + [2:2] + read-write + oneToClear + + + BOOT_DONE + PSM boot done status flag + [1:1] + read-only + + + PSM_DONE + PSM done status flag + [0:0] + read-only + + + + + BIST + 0x00000134 + During BIST, count address locations that have at least one leaky bit + 0x0fff0000 + + + CNT_FAIL + Flag if the count of address locations with at least one leaky bit exceeds cnt_max + [30:30] + read-only + + + CNT_CLR + Clear counter before use + [29:29] + write-only + + + CNT_ENA + Enable the counter before the BIST function is initiated + [28:28] + read-write + + + CNT_MAX + The cnt_fail flag will be set if the number of leaky locations exceeds this number + [27:16] + read-write + + + CNT + Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option. + [12:0] + read-only + + + + + CRT_KEY_W0 + 0x00000138 + Word 0 (bits 31..0) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W0 + [31:0] + write-only + + + + + CRT_KEY_W1 + 0x0000013c + Word 1 (bits 63..32) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W1 + [31:0] + write-only + + + + + CRT_KEY_W2 + 0x00000140 + Word 2 (bits 95..64) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W2 + [31:0] + write-only + + + + + CRT_KEY_W3 + 0x00000144 + Word 3 (bits 127..96) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W3 + [31:0] + write-only + + + + + CRITICAL + 0x00000148 + Quickly check values of critical flags read during boot up + 0x00000000 + + + RISCV_DISABLE + [17:17] + read-only + + + ARM_DISABLE + [16:16] + read-only + + + GLITCH_DETECTOR_SENS + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + [4:4] + read-only + + + DEFAULT_ARCHSEL + [3:3] + read-only + + + DEBUG_DISABLE + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + [1:1] + read-only + + + SECURE_BOOT_ENABLE + [0:0] + read-only + + + + + KEY_VALID + 0x0000014c + Which keys were valid (enrolled) at boot time + 0x00000000 + + + KEY_VALID + [7:0] + read-only + + + + + DEBUGEN + 0x00000150 + Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. + + Specifically: + + - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. + + - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. + + - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. + 0x00000000 + + + MISC + Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. + + These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [8:8] + read-write + + + PROC1_SECURE + Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). + + Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + [3:3] + read-write + + + PROC1 + Enable core 1's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [2:2] + read-write + + + PROC0_SECURE + Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). + + Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [1:1] + read-write + + + PROC0 + Enable core 0's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [0:0] + read-write + + + + + DEBUGEN_LOCK + 0x00000154 + Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. + 0x00000000 + + + MISC + Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set. + [8:8] + read-write + + + PROC1_SECURE + Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set. + [3:3] + read-write + + + PROC1 + Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set. + [2:2] + read-write + + + PROC0_SECURE + Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set. + [1:1] + read-write + + + PROC0 + Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set. + [0:0] + read-write + + + + + ARCHSEL + 0x00000158 + Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. + + This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). + + Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. + + Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. + 0x00000000 + + + CORE1 + Select architecture for core 1. + [1:1] + read-write + + + arm + 0 + Switch core 1 to Arm (Cortex-M33) + + + riscv + 1 + Switch core 1 to RISC-V (Hazard3) + + + + + CORE0 + Select architecture for core 0. + [0:0] + read-write + + + arm + 0 + Switch core 0 to Arm (Cortex-M33) + + + riscv + 1 + Switch core 0 to RISC-V (Hazard3) + + + + + + + ARCHSEL_STATUS + 0x0000015c + Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. + 0x00000000 + + + CORE1 + Current architecture for core 0. Updated on processor warm reset. + [1:1] + read-only + + + arm + 0 + Core 1 is currently Arm (Cortex-M33) + + + riscv + 1 + Core 1 is currently RISC-V (Hazard3) + + + + + CORE0 + Current architecture for core 0. Updated on processor warm reset. + [0:0] + read-only + + + arm + 0 + Core 0 is currently Arm (Cortex-M33) + + + riscv + 1 + Core 0 is currently RISC-V (Hazard3) + + + + + + + BOOTDIS + 0x00000160 + Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the power manager BOOTDIS register. + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset. + [1:1] + read-write + + + NOW + When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + INTR + 0x00000164 + Raw Interrupts + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + oneToClear + + + APB_RD_SEC_FAIL + [3:3] + read-write + oneToClear + + + APB_DCTRL_FAIL + [2:2] + read-write + oneToClear + + + SBPI_WR_FAIL + [1:1] + read-write + oneToClear + + + SBPI_FLAG_N + [0:0] + read-only + + + + + INTE + 0x00000168 + Interrupt Enable + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTF + 0x0000016c + Interrupt Force + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTS + 0x00000170 + Interrupt status after masking & forcing + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-only + + + APB_RD_SEC_FAIL + [3:3] + read-only + + + APB_DCTRL_FAIL + [2:2] + read-only + + + SBPI_WR_FAIL + [1:1] + read-only + + + SBPI_FLAG_N + [0:0] + read-only + + + + + + + OTP_DATA + Predefined OTP data layout for RP2350 + 0x40130000 + + 0 + 7920 + registers + + + + CHIPID0 + 0x0000 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 16 + 0x0000 + + + CHIPID0 + [15:0] + read-only + + + + + CHIPID1 + 0x0002 + Bits 31:16 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID1 + [15:0] + read-only + + + + + CHIPID2 + 0x0004 + Bits 47:32 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID2 + [15:0] + read-only + + + + + CHIPID3 + 0x0006 + Bits 63:48 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID3 + [15:0] + read-only + + + + + RANDID0 + 0x0008 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 16 + 0x0000 + + + RANDID0 + [15:0] + read-only + + + + + RANDID1 + 0x000a + Bits 31:16 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID1 + [15:0] + read-only + + + + + RANDID2 + 0x000c + Bits 47:32 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID2 + [15:0] + read-only + + + + + RANDID3 + 0x000e + Bits 63:48 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID3 + [15:0] + read-only + + + + + RANDID4 + 0x0010 + Bits 79:64 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID4 + [15:0] + read-only + + + + + RANDID5 + 0x0012 + Bits 95:80 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID5 + [15:0] + read-only + + + + + RANDID6 + 0x0014 + Bits 111:96 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID6 + [15:0] + read-only + + + + + RANDID7 + 0x0016 + Bits 127:112 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID7 + [15:0] + read-only + + + + + ROSC_CALIB + 0x0020 + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 16 + 0x0000 + + + ROSC_CALIB + [15:0] + read-only + + + + + LPOSC_CALIB + 0x0022 + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 16 + 0x0000 + + + LPOSC_CALIB + [15:0] + read-only + + + + + NUM_GPIOS + 0x0030 + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 16 + 0x0000 + + + NUM_GPIOS + [7:0] + read-only + + + + + INFO_CRC0 + 0x006c + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 16 + 0x0000 + + + INFO_CRC0 + [15:0] + read-only + + + + + INFO_CRC1 + 0x006e + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 16 + 0x0000 + + + INFO_CRC1 + [15:0] + read-only + + + + + FLASH_DEVINFO + 0x00a8 + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 16 + 0x0000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [15:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + 0x00aa + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 16 + 0x0000 + + + FLASH_PARTITION_SLOT_SIZE + [15:0] + read-only + + + + + BOOTSEL_LED_CFG + 0x00ac + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 16 + 0x0000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [8:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + 0x00ae + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 16 + 0x0000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [15:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + 0x00b0 + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 16 + 0x0000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [15:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + 0x00b8 + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 16 + 0x0000 + + + USB_WHITE_LABEL_ADDR + [15:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + 0x00bc + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 16 + 0x0000 + + + OTPBOOT_SRC + [15:0] + read-only + + + + + OTPBOOT_LEN + 0x00be + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 16 + 0x0000 + + + OTPBOOT_LEN + [15:0] + read-only + + + + + OTPBOOT_DST0 + 0x00c0 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 16 + 0x0000 + + + OTPBOOT_DST0 + [15:0] + read-only + + + + + OTPBOOT_DST1 + 0x00c2 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 16 + 0x0000 + + + OTPBOOT_DST1 + [15:0] + read-only + + + + + BOOTKEY0_0 + 0x0100 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_0 + [15:0] + read-only + + + + + BOOTKEY0_1 + 0x0102 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_1 + [15:0] + read-only + + + + + BOOTKEY0_2 + 0x0104 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_2 + [15:0] + read-only + + + + + BOOTKEY0_3 + 0x0106 + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_3 + [15:0] + read-only + + + + + BOOTKEY0_4 + 0x0108 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_4 + [15:0] + read-only + + + + + BOOTKEY0_5 + 0x010a + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_5 + [15:0] + read-only + + + + + BOOTKEY0_6 + 0x010c + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_6 + [15:0] + read-only + + + + + BOOTKEY0_7 + 0x010e + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_7 + [15:0] + read-only + + + + + BOOTKEY0_8 + 0x0110 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_8 + [15:0] + read-only + + + + + BOOTKEY0_9 + 0x0112 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_9 + [15:0] + read-only + + + + + BOOTKEY0_10 + 0x0114 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_10 + [15:0] + read-only + + + + + BOOTKEY0_11 + 0x0116 + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_11 + [15:0] + read-only + + + + + BOOTKEY0_12 + 0x0118 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_12 + [15:0] + read-only + + + + + BOOTKEY0_13 + 0x011a + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_13 + [15:0] + read-only + + + + + BOOTKEY0_14 + 0x011c + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_14 + [15:0] + read-only + + + + + BOOTKEY0_15 + 0x011e + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_15 + [15:0] + read-only + + + + + BOOTKEY1_0 + 0x0120 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_0 + [15:0] + read-only + + + + + BOOTKEY1_1 + 0x0122 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_1 + [15:0] + read-only + + + + + BOOTKEY1_2 + 0x0124 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_2 + [15:0] + read-only + + + + + BOOTKEY1_3 + 0x0126 + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_3 + [15:0] + read-only + + + + + BOOTKEY1_4 + 0x0128 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_4 + [15:0] + read-only + + + + + BOOTKEY1_5 + 0x012a + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_5 + [15:0] + read-only + + + + + BOOTKEY1_6 + 0x012c + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_6 + [15:0] + read-only + + + + + BOOTKEY1_7 + 0x012e + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_7 + [15:0] + read-only + + + + + BOOTKEY1_8 + 0x0130 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_8 + [15:0] + read-only + + + + + BOOTKEY1_9 + 0x0132 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_9 + [15:0] + read-only + + + + + BOOTKEY1_10 + 0x0134 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_10 + [15:0] + read-only + + + + + BOOTKEY1_11 + 0x0136 + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_11 + [15:0] + read-only + + + + + BOOTKEY1_12 + 0x0138 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_12 + [15:0] + read-only + + + + + BOOTKEY1_13 + 0x013a + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_13 + [15:0] + read-only + + + + + BOOTKEY1_14 + 0x013c + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_14 + [15:0] + read-only + + + + + BOOTKEY1_15 + 0x013e + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_15 + [15:0] + read-only + + + + + BOOTKEY2_0 + 0x0140 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_0 + [15:0] + read-only + + + + + BOOTKEY2_1 + 0x0142 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_1 + [15:0] + read-only + + + + + BOOTKEY2_2 + 0x0144 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_2 + [15:0] + read-only + + + + + BOOTKEY2_3 + 0x0146 + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_3 + [15:0] + read-only + + + + + BOOTKEY2_4 + 0x0148 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_4 + [15:0] + read-only + + + + + BOOTKEY2_5 + 0x014a + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_5 + [15:0] + read-only + + + + + BOOTKEY2_6 + 0x014c + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_6 + [15:0] + read-only + + + + + BOOTKEY2_7 + 0x014e + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_7 + [15:0] + read-only + + + + + BOOTKEY2_8 + 0x0150 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_8 + [15:0] + read-only + + + + + BOOTKEY2_9 + 0x0152 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_9 + [15:0] + read-only + + + + + BOOTKEY2_10 + 0x0154 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_10 + [15:0] + read-only + + + + + BOOTKEY2_11 + 0x0156 + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_11 + [15:0] + read-only + + + + + BOOTKEY2_12 + 0x0158 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_12 + [15:0] + read-only + + + + + BOOTKEY2_13 + 0x015a + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_13 + [15:0] + read-only + + + + + BOOTKEY2_14 + 0x015c + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_14 + [15:0] + read-only + + + + + BOOTKEY2_15 + 0x015e + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_15 + [15:0] + read-only + + + + + BOOTKEY3_0 + 0x0160 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_0 + [15:0] + read-only + + + + + BOOTKEY3_1 + 0x0162 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_1 + [15:0] + read-only + + + + + BOOTKEY3_2 + 0x0164 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_2 + [15:0] + read-only + + + + + BOOTKEY3_3 + 0x0166 + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_3 + [15:0] + read-only + + + + + BOOTKEY3_4 + 0x0168 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_4 + [15:0] + read-only + + + + + BOOTKEY3_5 + 0x016a + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_5 + [15:0] + read-only + + + + + BOOTKEY3_6 + 0x016c + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_6 + [15:0] + read-only + + + + + BOOTKEY3_7 + 0x016e + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_7 + [15:0] + read-only + + + + + BOOTKEY3_8 + 0x0170 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_8 + [15:0] + read-only + + + + + BOOTKEY3_9 + 0x0172 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_9 + [15:0] + read-only + + + + + BOOTKEY3_10 + 0x0174 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_10 + [15:0] + read-only + + + + + BOOTKEY3_11 + 0x0176 + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_11 + [15:0] + read-only + + + + + BOOTKEY3_12 + 0x0178 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_12 + [15:0] + read-only + + + + + BOOTKEY3_13 + 0x017a + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_13 + [15:0] + read-only + + + + + BOOTKEY3_14 + 0x017c + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_14 + [15:0] + read-only + + + + + BOOTKEY3_15 + 0x017e + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_15 + [15:0] + read-only + + + + + KEY1_0 + 0x1e90 + Bits 15:0 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_0 + [15:0] + read-only + + + + + KEY1_1 + 0x1e92 + Bits 31:16 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_1 + [15:0] + read-only + + + + + KEY1_2 + 0x1e94 + Bits 47:32 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_2 + [15:0] + read-only + + + + + KEY1_3 + 0x1e96 + Bits 63:48 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_3 + [15:0] + read-only + + + + + KEY1_4 + 0x1e98 + Bits 79:64 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_4 + [15:0] + read-only + + + + + KEY1_5 + 0x1e9a + Bits 95:80 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_5 + [15:0] + read-only + + + + + KEY1_6 + 0x1e9c + Bits 111:96 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_6 + [15:0] + read-only + + + + + KEY1_7 + 0x1e9e + Bits 127:112 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_7 + [15:0] + read-only + + + + + KEY2_0 + 0x1ea0 + Bits 15:0 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_0 + [15:0] + read-only + + + + + KEY2_1 + 0x1ea2 + Bits 31:16 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_1 + [15:0] + read-only + + + + + KEY2_2 + 0x1ea4 + Bits 47:32 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_2 + [15:0] + read-only + + + + + KEY2_3 + 0x1ea6 + Bits 63:48 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_3 + [15:0] + read-only + + + + + KEY2_4 + 0x1ea8 + Bits 79:64 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_4 + [15:0] + read-only + + + + + KEY2_5 + 0x1eaa + Bits 95:80 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_5 + [15:0] + read-only + + + + + KEY2_6 + 0x1eac + Bits 111:96 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_6 + [15:0] + read-only + + + + + KEY2_7 + 0x1eae + Bits 127:112 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_7 + [15:0] + read-only + + + + + KEY3_0 + 0x1eb0 + Bits 15:0 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_0 + [15:0] + read-only + + + + + KEY3_1 + 0x1eb2 + Bits 31:16 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_1 + [15:0] + read-only + + + + + KEY3_2 + 0x1eb4 + Bits 47:32 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_2 + [15:0] + read-only + + + + + KEY3_3 + 0x1eb6 + Bits 63:48 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_3 + [15:0] + read-only + + + + + KEY3_4 + 0x1eb8 + Bits 79:64 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_4 + [15:0] + read-only + + + + + KEY3_5 + 0x1eba + Bits 95:80 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_5 + [15:0] + read-only + + + + + KEY3_6 + 0x1ebc + Bits 111:96 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_6 + [15:0] + read-only + + + + + KEY3_7 + 0x1ebe + Bits 127:112 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_7 + [15:0] + read-only + + + + + KEY4_0 + 0x1ec0 + Bits 15:0 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_0 + [15:0] + read-only + + + + + KEY4_1 + 0x1ec2 + Bits 31:16 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_1 + [15:0] + read-only + + + + + KEY4_2 + 0x1ec4 + Bits 47:32 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_2 + [15:0] + read-only + + + + + KEY4_3 + 0x1ec6 + Bits 63:48 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_3 + [15:0] + read-only + + + + + KEY4_4 + 0x1ec8 + Bits 79:64 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_4 + [15:0] + read-only + + + + + KEY4_5 + 0x1eca + Bits 95:80 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_5 + [15:0] + read-only + + + + + KEY4_6 + 0x1ecc + Bits 111:96 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_6 + [15:0] + read-only + + + + + KEY4_7 + 0x1ece + Bits 127:112 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_7 + [15:0] + read-only + + + + + KEY5_0 + 0x1ed0 + Bits 15:0 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_0 + [15:0] + read-only + + + + + KEY5_1 + 0x1ed2 + Bits 31:16 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_1 + [15:0] + read-only + + + + + KEY5_2 + 0x1ed4 + Bits 47:32 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_2 + [15:0] + read-only + + + + + KEY5_3 + 0x1ed6 + Bits 63:48 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_3 + [15:0] + read-only + + + + + KEY5_4 + 0x1ed8 + Bits 79:64 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_4 + [15:0] + read-only + + + + + KEY5_5 + 0x1eda + Bits 95:80 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_5 + [15:0] + read-only + + + + + KEY5_6 + 0x1edc + Bits 111:96 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_6 + [15:0] + read-only + + + + + KEY5_7 + 0x1ede + Bits 127:112 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_7 + [15:0] + read-only + + + + + KEY6_0 + 0x1ee0 + Bits 15:0 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_0 + [15:0] + read-only + + + + + KEY6_1 + 0x1ee2 + Bits 31:16 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_1 + [15:0] + read-only + + + + + KEY6_2 + 0x1ee4 + Bits 47:32 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_2 + [15:0] + read-only + + + + + KEY6_3 + 0x1ee6 + Bits 63:48 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_3 + [15:0] + read-only + + + + + KEY6_4 + 0x1ee8 + Bits 79:64 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_4 + [15:0] + read-only + + + + + KEY6_5 + 0x1eea + Bits 95:80 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_5 + [15:0] + read-only + + + + + KEY6_6 + 0x1eec + Bits 111:96 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_6 + [15:0] + read-only + + + + + KEY6_7 + 0x1eee + Bits 127:112 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_7 + [15:0] + read-only + + + + + + + OTP_DATA_RAW + Predefined OTP data layout for RP2350 + 0x40134000 + + 0 + 16384 + registers + + + + CHIPID0 + 0x00000000 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 0x00000000 + + + CHIPID0 + [15:0] + read-only + + + + + CHIPID1 + 0x00000004 + Bits 31:16 of public device ID (ECC) + 0x00000000 + + + CHIPID1 + [15:0] + read-only + + + + + CHIPID2 + 0x00000008 + Bits 47:32 of public device ID (ECC) + 0x00000000 + + + CHIPID2 + [15:0] + read-only + + + + + CHIPID3 + 0x0000000c + Bits 63:48 of public device ID (ECC) + 0x00000000 + + + CHIPID3 + [15:0] + read-only + + + + + RANDID0 + 0x00000010 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 0x00000000 + + + RANDID0 + [15:0] + read-only + + + + + RANDID1 + 0x00000014 + Bits 31:16 of private per-device random number (ECC) + 0x00000000 + + + RANDID1 + [15:0] + read-only + + + + + RANDID2 + 0x00000018 + Bits 47:32 of private per-device random number (ECC) + 0x00000000 + + + RANDID2 + [15:0] + read-only + + + + + RANDID3 + 0x0000001c + Bits 63:48 of private per-device random number (ECC) + 0x00000000 + + + RANDID3 + [15:0] + read-only + + + + + RANDID4 + 0x00000020 + Bits 79:64 of private per-device random number (ECC) + 0x00000000 + + + RANDID4 + [15:0] + read-only + + + + + RANDID5 + 0x00000024 + Bits 95:80 of private per-device random number (ECC) + 0x00000000 + + + RANDID5 + [15:0] + read-only + + + + + RANDID6 + 0x00000028 + Bits 111:96 of private per-device random number (ECC) + 0x00000000 + + + RANDID6 + [15:0] + read-only + + + + + RANDID7 + 0x0000002c + Bits 127:112 of private per-device random number (ECC) + 0x00000000 + + + RANDID7 + [15:0] + read-only + + + + + ROSC_CALIB + 0x00000040 + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 0x00000000 + + + ROSC_CALIB + [15:0] + read-only + + + + + LPOSC_CALIB + 0x00000044 + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 0x00000000 + + + LPOSC_CALIB + [15:0] + read-only + + + + + NUM_GPIOS + 0x00000060 + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 0x00000000 + + + NUM_GPIOS + [7:0] + read-only + + + + + INFO_CRC0 + 0x000000d8 + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 0x00000000 + + + INFO_CRC0 + [15:0] + read-only + + + + + INFO_CRC1 + 0x000000dc + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 0x00000000 + + + INFO_CRC1 + [15:0] + read-only + + + + + CRIT0 + 0x000000e0 + Page 0 critical boot flags (RBIT-8) + 0x00000000 + + + RISCV_DISABLE + Permanently disable RISC-V processors (Hazard3) + [1:1] + read-only + + + ARM_DISABLE + Permanently disable ARM processors (Cortex-M33) + [0:0] + read-only + + + + + CRIT0_R1 + 0x000000e4 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R1 + [23:0] + read-only + + + + + CRIT0_R2 + 0x000000e8 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R2 + [23:0] + read-only + + + + + CRIT0_R3 + 0x000000ec + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R3 + [23:0] + read-only + + + + + CRIT0_R4 + 0x000000f0 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R4 + [23:0] + read-only + + + + + CRIT0_R5 + 0x000000f4 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R5 + [23:0] + read-only + + + + + CRIT0_R6 + 0x000000f8 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R6 + [23:0] + read-only + + + + + CRIT0_R7 + 0x000000fc + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R7 + [23:0] + read-only + + + + + CRIT1 + 0x00000100 + Page 1 critical boot flags (RBIT-8) + 0x00000000 + + + GLITCH_DETECTOR_SENS + Increase the sensitivity of the glitch detectors from their default. + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + Arm the glitch detectors to reset the system if an abnormal clock/power event is observed. + [4:4] + read-only + + + BOOT_ARCH + Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. + [3:3] + read-only + + + DEBUG_DISABLE + Disable all debug access + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + Disable Secure debug access + [1:1] + read-only + + + SECURE_BOOT_ENABLE + Enable boot signature enforcement, and permanently disable the RISC-V cores. + [0:0] + read-only + + + + + CRIT1_R1 + 0x00000104 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R1 + [23:0] + read-only + + + + + CRIT1_R2 + 0x00000108 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R2 + [23:0] + read-only + + + + + CRIT1_R3 + 0x0000010c + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R3 + [23:0] + read-only + + + + + CRIT1_R4 + 0x00000110 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R4 + [23:0] + read-only + + + + + CRIT1_R5 + 0x00000114 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R5 + [23:0] + read-only + + + + + CRIT1_R6 + 0x00000118 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R6 + [23:0] + read-only + + + + + CRIT1_R7 + 0x0000011c + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R7 + [23:0] + read-only + + + + + BOOT_FLAGS0 + 0x00000120 + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 0x00000000 + + + DISABLE_SRAM_WINDOW_BOOT + [21:21] + read-only + + + DISABLE_XIP_ACCESS_ON_SRAM_ENTRY + Disable all access to XIP after entering an SRAM binary. + + Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table. + [20:20] + read-only + + + DISABLE_BOOTSEL_UART_BOOT + [19:19] + read-only + + + DISABLE_BOOTSEL_USB_PICOBOOT_IFC + [18:18] + read-only + + + DISABLE_BOOTSEL_USB_MSD_IFC + [17:17] + read-only + + + DISABLE_WATCHDOG_SCRATCH + [16:16] + read-only + + + DISABLE_POWER_SCRATCH + [15:15] + read-only + + + ENABLE_OTP_BOOT + Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. + + The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. + + Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window. + [14:14] + read-only + + + DISABLE_OTP_BOOT + Takes precedence over ENABLE_OTP_BOOT. + [13:13] + read-only + + + DISABLE_FLASH_BOOT + [12:12] + read-only + + + ROLLBACK_REQUIRED + Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted. + [11:11] + read-only + + + HASHED_PARTITION_TABLE + Require a partition table to be hashed (if not signed) + [10:10] + read-only + + + SECURE_PARTITION_TABLE + Require a partition table to be signed + [9:9] + read-only + + + DISABLE_AUTO_SWITCH_ARCH + Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled + [8:8] + read-only + + + SINGLE_FLASH_BINARY + Restrict flash boot path to use of a single binary at the start of flash + [7:7] + read-only + + + OVERRIDE_FLASH_PARTITION_SLOT_SIZE + Override the limit for default flash metadata scanning. + + The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit + [6:6] + read-only + + + FLASH_DEVINFO_ENABLE + Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices. + [5:5] + read-only + + + FAST_SIGCHECK_ROSC_DIV + Enable quartering of ROSC divisor during signature check, to reduce secure boot time + [4:4] + read-only + + + FLASH_IO_VOLTAGE_1V8 + If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. + + If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V) + [3:3] + read-only + + + ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG + Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. + + Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. + + If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz. + [2:2] + read-only + + + ENABLE_BOOTSEL_LED + Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid + [1:1] + read-only + + + DISABLE_BOOTSEL_EXEC2 + [0:0] + read-only + + + + + BOOT_FLAGS0_R1 + 0x00000124 + Redundant copy of BOOT_FLAGS0 + 0x00000000 + + + BOOT_FLAGS0_R1 + [23:0] + read-only + + + + + BOOT_FLAGS0_R2 + 0x00000128 + Redundant copy of BOOT_FLAGS0 + 0x00000000 + + + BOOT_FLAGS0_R2 + [23:0] + read-only + + + + + BOOT_FLAGS1 + 0x0000012c + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 0x00000000 + + + DOUBLE_TAP + Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. + + This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART. + [19:19] + read-only + + + DOUBLE_TAP_DELAY + Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. + + For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. + + 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value. + [18:16] + read-only + + + KEY_INVALID + Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time. + [11:8] + read-only + + + KEY_VALID + Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. + + Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. + + Do not enable secure boot without first installing a valid key. This will render your device unbootable. + [3:0] + read-only + + + + + BOOT_FLAGS1_R1 + 0x00000130 + Redundant copy of BOOT_FLAGS1 + 0x00000000 + + + BOOT_FLAGS1_R1 + [23:0] + read-only + + + + + BOOT_FLAGS1_R2 + 0x00000134 + Redundant copy of BOOT_FLAGS1 + 0x00000000 + + + BOOT_FLAGS1_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0 + 0x00000138 + Default boot version thermometer counter, bits 23:0 (RBIT-3) + 0x00000000 + + + DEFAULT_BOOT_VERSION0 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R1 + 0x0000013c + Redundant copy of DEFAULT_BOOT_VERSION0 + 0x00000000 + + + DEFAULT_BOOT_VERSION0_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R2 + 0x00000140 + Redundant copy of DEFAULT_BOOT_VERSION0 + 0x00000000 + + + DEFAULT_BOOT_VERSION0_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1 + 0x00000144 + Default boot version thermometer counter, bits 47:24 (RBIT-3) + 0x00000000 + + + DEFAULT_BOOT_VERSION1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R1 + 0x00000148 + Redundant copy of DEFAULT_BOOT_VERSION1 + 0x00000000 + + + DEFAULT_BOOT_VERSION1_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R2 + 0x0000014c + Redundant copy of DEFAULT_BOOT_VERSION1 + 0x00000000 + + + DEFAULT_BOOT_VERSION1_R2 + [23:0] + read-only + + + + + FLASH_DEVINFO + 0x00000150 + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 0x00000000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [15:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + 0x00000154 + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 0x00000000 + + + FLASH_PARTITION_SLOT_SIZE + [15:0] + read-only + + + + + BOOTSEL_LED_CFG + 0x00000158 + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 0x00000000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [8:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + 0x0000015c + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 0x00000000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [15:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + 0x00000160 + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 0x00000000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [15:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_BOOT_FLAGS + 0x00000164 + USB boot specific feature flags (RBIT-3) + 0x00000000 + + + DP_DM_SWAP + Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental). + [23:23] + read-only + + + WHITE_LABEL_ADDR_VALID + valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15) + [22:22] + read-only + + + WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID + valid flag for the USB_WHITE_LABEL_ADDR field + [15:15] + read-only + + + WL_INFO_UF2_TXT_MODEL_STRDEF_VALID + valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14) + [14:14] + read-only + + + WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13) + [13:13] + read-only + + + WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12) + [12:12] + read-only + + + WL_SCSI_INQUIRY_VERSION_STRDEF_VALID + valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11) + [11:11] + read-only + + + WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID + valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10) + [10:10] + read-only + + + WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID + valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9) + [9:9] + read-only + + + WL_VOLUME_LABEL_STRDEF_VALID + valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8) + [8:8] + read-only + + + WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID + valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7) + [7:7] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID + valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6) + [6:6] + read-only + + + WL_USB_DEVICE_PRODUCT_STRDEF_VALID + valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5) + [5:5] + read-only + + + WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID + valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4) + [4:4] + read-only + + + WL_USB_DEVICE_LANG_ID_VALUE_VALID + valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3) + [3:3] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID + valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2) + [2:2] + read-only + + + WL_USB_DEVICE_PID_VALUE_VALID + valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1) + [1:1] + read-only + + + WL_USB_DEVICE_VID_VALUE_VALID + valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0) + [0:0] + read-only + + + + + USB_BOOT_FLAGS_R1 + 0x00000168 + Redundant copy of USB_BOOT_FLAGS + 0x00000000 + + + USB_BOOT_FLAGS_R1 + [23:0] + read-only + + + + + USB_BOOT_FLAGS_R2 + 0x0000016c + Redundant copy of USB_BOOT_FLAGS + 0x00000000 + + + USB_BOOT_FLAGS_R2 + [23:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + 0x00000170 + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 0x00000000 + + + USB_WHITE_LABEL_ADDR + [15:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + 0x00000178 + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 0x00000000 + + + OTPBOOT_SRC + [15:0] + read-only + + + + + OTPBOOT_LEN + 0x0000017c + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 0x00000000 + + + OTPBOOT_LEN + [15:0] + read-only + + + + + OTPBOOT_DST0 + 0x00000180 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0x00000000 + + + OTPBOOT_DST0 + [15:0] + read-only + + + + + OTPBOOT_DST1 + 0x00000184 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0x00000000 + + + OTPBOOT_DST1 + [15:0] + read-only + + + + + BOOTKEY0_0 + 0x00000200 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_0 + [15:0] + read-only + + + + + BOOTKEY0_1 + 0x00000204 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_1 + [15:0] + read-only + + + + + BOOTKEY0_2 + 0x00000208 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_2 + [15:0] + read-only + + + + + BOOTKEY0_3 + 0x0000020c + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_3 + [15:0] + read-only + + + + + BOOTKEY0_4 + 0x00000210 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_4 + [15:0] + read-only + + + + + BOOTKEY0_5 + 0x00000214 + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_5 + [15:0] + read-only + + + + + BOOTKEY0_6 + 0x00000218 + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_6 + [15:0] + read-only + + + + + BOOTKEY0_7 + 0x0000021c + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_7 + [15:0] + read-only + + + + + BOOTKEY0_8 + 0x00000220 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_8 + [15:0] + read-only + + + + + BOOTKEY0_9 + 0x00000224 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_9 + [15:0] + read-only + + + + + BOOTKEY0_10 + 0x00000228 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_10 + [15:0] + read-only + + + + + BOOTKEY0_11 + 0x0000022c + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_11 + [15:0] + read-only + + + + + BOOTKEY0_12 + 0x00000230 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_12 + [15:0] + read-only + + + + + BOOTKEY0_13 + 0x00000234 + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_13 + [15:0] + read-only + + + + + BOOTKEY0_14 + 0x00000238 + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_14 + [15:0] + read-only + + + + + BOOTKEY0_15 + 0x0000023c + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_15 + [15:0] + read-only + + + + + BOOTKEY1_0 + 0x00000240 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_0 + [15:0] + read-only + + + + + BOOTKEY1_1 + 0x00000244 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_1 + [15:0] + read-only + + + + + BOOTKEY1_2 + 0x00000248 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_2 + [15:0] + read-only + + + + + BOOTKEY1_3 + 0x0000024c + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_3 + [15:0] + read-only + + + + + BOOTKEY1_4 + 0x00000250 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_4 + [15:0] + read-only + + + + + BOOTKEY1_5 + 0x00000254 + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_5 + [15:0] + read-only + + + + + BOOTKEY1_6 + 0x00000258 + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_6 + [15:0] + read-only + + + + + BOOTKEY1_7 + 0x0000025c + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_7 + [15:0] + read-only + + + + + BOOTKEY1_8 + 0x00000260 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_8 + [15:0] + read-only + + + + + BOOTKEY1_9 + 0x00000264 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_9 + [15:0] + read-only + + + + + BOOTKEY1_10 + 0x00000268 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_10 + [15:0] + read-only + + + + + BOOTKEY1_11 + 0x0000026c + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_11 + [15:0] + read-only + + + + + BOOTKEY1_12 + 0x00000270 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_12 + [15:0] + read-only + + + + + BOOTKEY1_13 + 0x00000274 + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_13 + [15:0] + read-only + + + + + BOOTKEY1_14 + 0x00000278 + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_14 + [15:0] + read-only + + + + + BOOTKEY1_15 + 0x0000027c + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_15 + [15:0] + read-only + + + + + BOOTKEY2_0 + 0x00000280 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_0 + [15:0] + read-only + + + + + BOOTKEY2_1 + 0x00000284 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_1 + [15:0] + read-only + + + + + BOOTKEY2_2 + 0x00000288 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_2 + [15:0] + read-only + + + + + BOOTKEY2_3 + 0x0000028c + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_3 + [15:0] + read-only + + + + + BOOTKEY2_4 + 0x00000290 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_4 + [15:0] + read-only + + + + + BOOTKEY2_5 + 0x00000294 + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_5 + [15:0] + read-only + + + + + BOOTKEY2_6 + 0x00000298 + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_6 + [15:0] + read-only + + + + + BOOTKEY2_7 + 0x0000029c + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_7 + [15:0] + read-only + + + + + BOOTKEY2_8 + 0x000002a0 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_8 + [15:0] + read-only + + + + + BOOTKEY2_9 + 0x000002a4 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_9 + [15:0] + read-only + + + + + BOOTKEY2_10 + 0x000002a8 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_10 + [15:0] + read-only + + + + + BOOTKEY2_11 + 0x000002ac + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_11 + [15:0] + read-only + + + + + BOOTKEY2_12 + 0x000002b0 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_12 + [15:0] + read-only + + + + + BOOTKEY2_13 + 0x000002b4 + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_13 + [15:0] + read-only + + + + + BOOTKEY2_14 + 0x000002b8 + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_14 + [15:0] + read-only + + + + + BOOTKEY2_15 + 0x000002bc + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_15 + [15:0] + read-only + + + + + BOOTKEY3_0 + 0x000002c0 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_0 + [15:0] + read-only + + + + + BOOTKEY3_1 + 0x000002c4 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_1 + [15:0] + read-only + + + + + BOOTKEY3_2 + 0x000002c8 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_2 + [15:0] + read-only + + + + + BOOTKEY3_3 + 0x000002cc + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_3 + [15:0] + read-only + + + + + BOOTKEY3_4 + 0x000002d0 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_4 + [15:0] + read-only + + + + + BOOTKEY3_5 + 0x000002d4 + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_5 + [15:0] + read-only + + + + + BOOTKEY3_6 + 0x000002d8 + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_6 + [15:0] + read-only + + + + + BOOTKEY3_7 + 0x000002dc + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_7 + [15:0] + read-only + + + + + BOOTKEY3_8 + 0x000002e0 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_8 + [15:0] + read-only + + + + + BOOTKEY3_9 + 0x000002e4 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_9 + [15:0] + read-only + + + + + BOOTKEY3_10 + 0x000002e8 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_10 + [15:0] + read-only + + + + + BOOTKEY3_11 + 0x000002ec + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_11 + [15:0] + read-only + + + + + BOOTKEY3_12 + 0x000002f0 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_12 + [15:0] + read-only + + + + + BOOTKEY3_13 + 0x000002f4 + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_13 + [15:0] + read-only + + + + + BOOTKEY3_14 + 0x000002f8 + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_14 + [15:0] + read-only + + + + + BOOTKEY3_15 + 0x000002fc + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_15 + [15:0] + read-only + + + + + KEY1_0 + 0x00003d20 + Bits 15:0 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_0 + [15:0] + read-only + + + + + KEY1_1 + 0x00003d24 + Bits 31:16 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_1 + [15:0] + read-only + + + + + KEY1_2 + 0x00003d28 + Bits 47:32 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_2 + [15:0] + read-only + + + + + KEY1_3 + 0x00003d2c + Bits 63:48 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_3 + [15:0] + read-only + + + + + KEY1_4 + 0x00003d30 + Bits 79:64 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_4 + [15:0] + read-only + + + + + KEY1_5 + 0x00003d34 + Bits 95:80 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_5 + [15:0] + read-only + + + + + KEY1_6 + 0x00003d38 + Bits 111:96 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_6 + [15:0] + read-only + + + + + KEY1_7 + 0x00003d3c + Bits 127:112 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_7 + [15:0] + read-only + + + + + KEY2_0 + 0x00003d40 + Bits 15:0 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_0 + [15:0] + read-only + + + + + KEY2_1 + 0x00003d44 + Bits 31:16 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_1 + [15:0] + read-only + + + + + KEY2_2 + 0x00003d48 + Bits 47:32 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_2 + [15:0] + read-only + + + + + KEY2_3 + 0x00003d4c + Bits 63:48 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_3 + [15:0] + read-only + + + + + KEY2_4 + 0x00003d50 + Bits 79:64 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_4 + [15:0] + read-only + + + + + KEY2_5 + 0x00003d54 + Bits 95:80 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_5 + [15:0] + read-only + + + + + KEY2_6 + 0x00003d58 + Bits 111:96 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_6 + [15:0] + read-only + + + + + KEY2_7 + 0x00003d5c + Bits 127:112 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_7 + [15:0] + read-only + + + + + KEY3_0 + 0x00003d60 + Bits 15:0 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_0 + [15:0] + read-only + + + + + KEY3_1 + 0x00003d64 + Bits 31:16 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_1 + [15:0] + read-only + + + + + KEY3_2 + 0x00003d68 + Bits 47:32 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_2 + [15:0] + read-only + + + + + KEY3_3 + 0x00003d6c + Bits 63:48 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_3 + [15:0] + read-only + + + + + KEY3_4 + 0x00003d70 + Bits 79:64 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_4 + [15:0] + read-only + + + + + KEY3_5 + 0x00003d74 + Bits 95:80 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_5 + [15:0] + read-only + + + + + KEY3_6 + 0x00003d78 + Bits 111:96 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_6 + [15:0] + read-only + + + + + KEY3_7 + 0x00003d7c + Bits 127:112 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_7 + [15:0] + read-only + + + + + KEY4_0 + 0x00003d80 + Bits 15:0 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_0 + [15:0] + read-only + + + + + KEY4_1 + 0x00003d84 + Bits 31:16 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_1 + [15:0] + read-only + + + + + KEY4_2 + 0x00003d88 + Bits 47:32 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_2 + [15:0] + read-only + + + + + KEY4_3 + 0x00003d8c + Bits 63:48 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_3 + [15:0] + read-only + + + + + KEY4_4 + 0x00003d90 + Bits 79:64 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_4 + [15:0] + read-only + + + + + KEY4_5 + 0x00003d94 + Bits 95:80 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_5 + [15:0] + read-only + + + + + KEY4_6 + 0x00003d98 + Bits 111:96 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_6 + [15:0] + read-only + + + + + KEY4_7 + 0x00003d9c + Bits 127:112 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_7 + [15:0] + read-only + + + + + KEY5_0 + 0x00003da0 + Bits 15:0 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_0 + [15:0] + read-only + + + + + KEY5_1 + 0x00003da4 + Bits 31:16 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_1 + [15:0] + read-only + + + + + KEY5_2 + 0x00003da8 + Bits 47:32 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_2 + [15:0] + read-only + + + + + KEY5_3 + 0x00003dac + Bits 63:48 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_3 + [15:0] + read-only + + + + + KEY5_4 + 0x00003db0 + Bits 79:64 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_4 + [15:0] + read-only + + + + + KEY5_5 + 0x00003db4 + Bits 95:80 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_5 + [15:0] + read-only + + + + + KEY5_6 + 0x00003db8 + Bits 111:96 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_6 + [15:0] + read-only + + + + + KEY5_7 + 0x00003dbc + Bits 127:112 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_7 + [15:0] + read-only + + + + + KEY6_0 + 0x00003dc0 + Bits 15:0 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_0 + [15:0] + read-only + + + + + KEY6_1 + 0x00003dc4 + Bits 31:16 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_1 + [15:0] + read-only + + + + + KEY6_2 + 0x00003dc8 + Bits 47:32 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_2 + [15:0] + read-only + + + + + KEY6_3 + 0x00003dcc + Bits 63:48 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_3 + [15:0] + read-only + + + + + KEY6_4 + 0x00003dd0 + Bits 79:64 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_4 + [15:0] + read-only + + + + + KEY6_5 + 0x00003dd4 + Bits 95:80 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_5 + [15:0] + read-only + + + + + KEY6_6 + 0x00003dd8 + Bits 111:96 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_6 + [15:0] + read-only + + + + + KEY6_7 + 0x00003ddc + Bits 127:112 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_7 + [15:0] + read-only + + + + + KEY1_VALID + 0x00003de4 + Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY2_VALID + 0x00003de8 + Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY3_VALID + 0x00003dec + Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY4_VALID + 0x00003df0 + Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY5_VALID + 0x00003df4 + Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY6_VALID + 0x00003df8 + Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + PAGE0_LOCK0 + 0x00003e00 + Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE0_LOCK1 + 0x00003e04 + Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE1_LOCK0 + 0x00003e08 + Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE1_LOCK1 + 0x00003e0c + Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE2_LOCK0 + 0x00003e10 + Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE2_LOCK1 + 0x00003e14 + Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE3_LOCK0 + 0x00003e18 + Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE3_LOCK1 + 0x00003e1c + Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE4_LOCK0 + 0x00003e20 + Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE4_LOCK1 + 0x00003e24 + Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE5_LOCK0 + 0x00003e28 + Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE5_LOCK1 + 0x00003e2c + Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE6_LOCK0 + 0x00003e30 + Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE6_LOCK1 + 0x00003e34 + Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE7_LOCK0 + 0x00003e38 + Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE7_LOCK1 + 0x00003e3c + Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE8_LOCK0 + 0x00003e40 + Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE8_LOCK1 + 0x00003e44 + Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE9_LOCK0 + 0x00003e48 + Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE9_LOCK1 + 0x00003e4c + Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE10_LOCK0 + 0x00003e50 + Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE10_LOCK1 + 0x00003e54 + Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE11_LOCK0 + 0x00003e58 + Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE11_LOCK1 + 0x00003e5c + Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE12_LOCK0 + 0x00003e60 + Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE12_LOCK1 + 0x00003e64 + Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE13_LOCK0 + 0x00003e68 + Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE13_LOCK1 + 0x00003e6c + Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE14_LOCK0 + 0x00003e70 + Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE14_LOCK1 + 0x00003e74 + Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE15_LOCK0 + 0x00003e78 + Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE15_LOCK1 + 0x00003e7c + Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE16_LOCK0 + 0x00003e80 + Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE16_LOCK1 + 0x00003e84 + Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE17_LOCK0 + 0x00003e88 + Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE17_LOCK1 + 0x00003e8c + Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE18_LOCK0 + 0x00003e90 + Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE18_LOCK1 + 0x00003e94 + Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE19_LOCK0 + 0x00003e98 + Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE19_LOCK1 + 0x00003e9c + Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE20_LOCK0 + 0x00003ea0 + Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE20_LOCK1 + 0x00003ea4 + Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE21_LOCK0 + 0x00003ea8 + Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE21_LOCK1 + 0x00003eac + Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE22_LOCK0 + 0x00003eb0 + Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE22_LOCK1 + 0x00003eb4 + Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE23_LOCK0 + 0x00003eb8 + Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE23_LOCK1 + 0x00003ebc + Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE24_LOCK0 + 0x00003ec0 + Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE24_LOCK1 + 0x00003ec4 + Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE25_LOCK0 + 0x00003ec8 + Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE25_LOCK1 + 0x00003ecc + Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE26_LOCK0 + 0x00003ed0 + Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE26_LOCK1 + 0x00003ed4 + Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE27_LOCK0 + 0x00003ed8 + Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE27_LOCK1 + 0x00003edc + Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE28_LOCK0 + 0x00003ee0 + Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE28_LOCK1 + 0x00003ee4 + Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE29_LOCK0 + 0x00003ee8 + Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE29_LOCK1 + 0x00003eec + Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE30_LOCK0 + 0x00003ef0 + Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE30_LOCK1 + 0x00003ef4 + Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE31_LOCK0 + 0x00003ef8 + Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE31_LOCK1 + 0x00003efc + Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE32_LOCK0 + 0x00003f00 + Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE32_LOCK1 + 0x00003f04 + Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE33_LOCK0 + 0x00003f08 + Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE33_LOCK1 + 0x00003f0c + Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE34_LOCK0 + 0x00003f10 + Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE34_LOCK1 + 0x00003f14 + Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE35_LOCK0 + 0x00003f18 + Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE35_LOCK1 + 0x00003f1c + Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE36_LOCK0 + 0x00003f20 + Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE36_LOCK1 + 0x00003f24 + Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE37_LOCK0 + 0x00003f28 + Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE37_LOCK1 + 0x00003f2c + Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE38_LOCK0 + 0x00003f30 + Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE38_LOCK1 + 0x00003f34 + Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE39_LOCK0 + 0x00003f38 + Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE39_LOCK1 + 0x00003f3c + Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE40_LOCK0 + 0x00003f40 + Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE40_LOCK1 + 0x00003f44 + Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE41_LOCK0 + 0x00003f48 + Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE41_LOCK1 + 0x00003f4c + Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE42_LOCK0 + 0x00003f50 + Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE42_LOCK1 + 0x00003f54 + Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE43_LOCK0 + 0x00003f58 + Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE43_LOCK1 + 0x00003f5c + Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE44_LOCK0 + 0x00003f60 + Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE44_LOCK1 + 0x00003f64 + Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE45_LOCK0 + 0x00003f68 + Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE45_LOCK1 + 0x00003f6c + Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE46_LOCK0 + 0x00003f70 + Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE46_LOCK1 + 0x00003f74 + Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE47_LOCK0 + 0x00003f78 + Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE47_LOCK1 + 0x00003f7c + Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE48_LOCK0 + 0x00003f80 + Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE48_LOCK1 + 0x00003f84 + Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE49_LOCK0 + 0x00003f88 + Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE49_LOCK1 + 0x00003f8c + Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE50_LOCK0 + 0x00003f90 + Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE50_LOCK1 + 0x00003f94 + Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE51_LOCK0 + 0x00003f98 + Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE51_LOCK1 + 0x00003f9c + Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE52_LOCK0 + 0x00003fa0 + Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE52_LOCK1 + 0x00003fa4 + Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE53_LOCK0 + 0x00003fa8 + Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE53_LOCK1 + 0x00003fac + Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE54_LOCK0 + 0x00003fb0 + Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE54_LOCK1 + 0x00003fb4 + Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE55_LOCK0 + 0x00003fb8 + Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE55_LOCK1 + 0x00003fbc + Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE56_LOCK0 + 0x00003fc0 + Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE56_LOCK1 + 0x00003fc4 + Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE57_LOCK0 + 0x00003fc8 + Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE57_LOCK1 + 0x00003fcc + Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE58_LOCK0 + 0x00003fd0 + Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE58_LOCK1 + 0x00003fd4 + Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE59_LOCK0 + 0x00003fd8 + Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE59_LOCK1 + 0x00003fdc + Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE60_LOCK0 + 0x00003fe0 + Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE60_LOCK1 + 0x00003fe4 + Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE61_LOCK0 + 0x00003fe8 + Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE61_LOCK1 + 0x00003fec + Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE62_LOCK0 + 0x00003ff0 + Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE62_LOCK1 + 0x00003ff4 + Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE63_LOCK0 + 0x00003ff8 + Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + RMA + Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible. + [7:7] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE63_LOCK1 + 0x00003ffc + Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + + + TBMAN + For managing simulation testbenches + 0x40160000 + + 0 + 4 + registers + + + + PLATFORM + 0x00000000 + Indicates the type of platform in use + 0x00000001 + + + HDLSIM + Indicates the platform is a simulation + [2:2] + read-only + + + FPGA + Indicates the platform is an FPGA + [1:1] + read-only + + + ASIC + Indicates the platform is an ASIC + [0:0] + read-only + + + + + + + USB_DPRAM + DPRAM layout for USB device. + 0x50100000 + + 0 + 256 + registers + + + + SETUP_PACKET_LOW + 0x00000000 + Bytes 0-3 of the SETUP packet from the host. + 0x00000000 + + + WVALUE + [31:16] + read-write + + + BREQUEST + [15:8] + read-write + + + BMREQUESTTYPE + [7:0] + read-write + + + + + SETUP_PACKET_HIGH + 0x00000004 + Bytes 4-7 of the setup packet from the host. + 0x00000000 + + + WLENGTH + [31:16] + read-write + + + WINDEX + [15:0] + read-write + + + + + EP1_IN_CONTROL + 0x00000008 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP1_OUT_CONTROL + 0x0000000c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_IN_CONTROL + 0x00000010 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_OUT_CONTROL + 0x00000014 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_IN_CONTROL + 0x00000018 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_OUT_CONTROL + 0x0000001c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_IN_CONTROL + 0x00000020 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_OUT_CONTROL + 0x00000024 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_IN_CONTROL + 0x00000028 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_OUT_CONTROL + 0x0000002c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_IN_CONTROL + 0x00000030 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_OUT_CONTROL + 0x00000034 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_IN_CONTROL + 0x00000038 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_OUT_CONTROL + 0x0000003c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_IN_CONTROL + 0x00000040 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_OUT_CONTROL + 0x00000044 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_IN_CONTROL + 0x00000048 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_OUT_CONTROL + 0x0000004c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_IN_CONTROL + 0x00000050 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_OUT_CONTROL + 0x00000054 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_IN_CONTROL + 0x00000058 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_OUT_CONTROL + 0x0000005c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_IN_CONTROL + 0x00000060 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_OUT_CONTROL + 0x00000064 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_IN_CONTROL + 0x00000068 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_OUT_CONTROL + 0x0000006c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_IN_CONTROL + 0x00000070 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_OUT_CONTROL + 0x00000074 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_IN_CONTROL + 0x00000078 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_OUT_CONTROL + 0x0000007c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP0_IN_BUFFER_CONTROL + 0x00000080 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP0_OUT_BUFFER_CONTROL + 0x00000084 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP1_IN_BUFFER_CONTROL + 0x00000088 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP1_OUT_BUFFER_CONTROL + 0x0000008c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP2_IN_BUFFER_CONTROL + 0x00000090 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP2_OUT_BUFFER_CONTROL + 0x00000094 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP3_IN_BUFFER_CONTROL + 0x00000098 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP3_OUT_BUFFER_CONTROL + 0x0000009c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP4_IN_BUFFER_CONTROL + 0x000000a0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP4_OUT_BUFFER_CONTROL + 0x000000a4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP5_IN_BUFFER_CONTROL + 0x000000a8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP5_OUT_BUFFER_CONTROL + 0x000000ac + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP6_IN_BUFFER_CONTROL + 0x000000b0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP6_OUT_BUFFER_CONTROL + 0x000000b4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP7_IN_BUFFER_CONTROL + 0x000000b8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP7_OUT_BUFFER_CONTROL + 0x000000bc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP8_IN_BUFFER_CONTROL + 0x000000c0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP8_OUT_BUFFER_CONTROL + 0x000000c4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP9_IN_BUFFER_CONTROL + 0x000000c8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP9_OUT_BUFFER_CONTROL + 0x000000cc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP10_IN_BUFFER_CONTROL + 0x000000d0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP10_OUT_BUFFER_CONTROL + 0x000000d4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP11_IN_BUFFER_CONTROL + 0x000000d8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP11_OUT_BUFFER_CONTROL + 0x000000dc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP12_IN_BUFFER_CONTROL + 0x000000e0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP12_OUT_BUFFER_CONTROL + 0x000000e4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP13_IN_BUFFER_CONTROL + 0x000000e8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP13_OUT_BUFFER_CONTROL + 0x000000ec + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP14_IN_BUFFER_CONTROL + 0x000000f0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP14_OUT_BUFFER_CONTROL + 0x000000f4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP15_IN_BUFFER_CONTROL + 0x000000f8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP15_OUT_BUFFER_CONTROL + 0x000000fc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + + + diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.c b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.c new file mode 100644 index 000000000..cb2e72467 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.c @@ -0,0 +1,68 @@ +/****************************************************************************************** + Filename : SysTickTimer.c + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : System timer driver implementation + +******************************************************************************************/ + +#include "SysTickTimer.h" + +//========================================================================================= +// Functions +//========================================================================================= + +//----------------------------------------------------------------------------- +/// \brief +/// +/// \descr +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------- +void SysTickTimer_Init(void) +{ + pSTK_CTRL->u32Register = 0; + pSTK_VAL->u32Register = 0; + pSTK_CTRL->bits.u1CLOCKSRC = SYS_TICK_CLKSRC_PROCESSOR_CLOCK; + pSTK_CTRL->bits.u1TICKINT = SYS_TICK_ENABLE_INT; +} + +//----------------------------------------------------------------------------- +/// \brief +/// +/// \descr +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------- +void SysTickTimer_Start(uint32 timeout) +{ + pSTK_LOAD->u32Register = timeout; + pSTK_CTRL->bits.u1ENABLE = SYS_TICK_ENABLE_TIMER; +} + +//----------------------------------------------------------------------------- +/// \brief +/// +/// \descr +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------- +void SysTickTimer_Stop(void) +{ + pSTK_CTRL->bits.u1ENABLE = 0U; +} \ No newline at end of file diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.h new file mode 100644 index 000000000..eeb5c6ba2 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.h @@ -0,0 +1,107 @@ +/****************************************************************************************** + Filename : SysTickTimer.h + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : System timer driver header file + +******************************************************************************************/ + +#ifndef __SYSTICK_TIMER_H__ +#define __SYSTICK_TIMER_H__ + +#include "Platform_Types.h" + +//========================================================================================= +// Types definition +//========================================================================================= +typedef union +{ + struct + { + uint32 u1ENABLE:1; + uint32 u1TICKINT:1; + uint32 u1CLOCKSRC:1; + uint32 :13; + uint32 u1COUNTFLAG:1; + uint32 :15; + }bits; + + uint32 u32Register; + +}stStkCtrl; + +typedef union +{ + struct + { + uint32 u24RELOAD:24; + uint32 :8; + }bits; + + uint32 u32Register; + +}stStkLoad; + +typedef union +{ + struct + { + uint32 u24CURRENT:24; + uint32 :8; + }bits; + + uint32 u32Register; + +}stStkVal; + +typedef union +{ + struct + { + uint32 u24TENMS:24; + uint32 :6; + uint32 u1SKEW:1; + uint32 u1NOREF:1; + }bits; + + uint32 u32Register; + +}stStkCalib; + +//========================================================================================= +// Definitions +//========================================================================================= +#define SYS_TICK_BASE_REG (0xE000E010UL) + +#define pSTK_CTRL ((volatile stStkCtrl* const) (SYS_TICK_BASE_REG + 0x00)) +#define pSTK_LOAD ((volatile stStkLoad* const) (SYS_TICK_BASE_REG + 0x04)) +#define pSTK_VAL ((volatile stStkVal* const) (SYS_TICK_BASE_REG + 0x08)) +#define pSTK_CALIB ((volatile stStkCalib* const)(SYS_TICK_BASE_REG + 0x0C)) + +#define CPU_FREQ_MHZ 133U +#define SYS_TICK_MS(x) ((uint32)(CPU_FREQ_MHZ * x * 1000UL) - 1UL) +#define SYS_TICK_US(x) ((uint32)(CPU_FREQ_MHZ * x) - 1UL) + +#define SYS_TICK_CLKSRC_PROCESSOR_CLOCK 1U +#define SYS_TICK_CLKSRC_EXTERNAL_REFERENCE_CLOCK 0U +#define SYS_TICK_ENABLE_INT 1U +#define SYS_TICK_ENABLE_TIMER 1U + +//========================================================================================= +// Prototypes +//========================================================================================= +void SysTickTimer_Init(void); +void SysTickTimer_Start(uint32 timeout); +void SysTickTimer_Stop(void); + + +#endif /*__SYSTICK_TIMER_H__*/ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.c b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.c new file mode 100644 index 000000000..cf80376ec --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.c @@ -0,0 +1,1019 @@ +/****************************************************************************************** + Filename : USB.c + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : USB low level device driver implementation + +******************************************************************************************/ + +//============================================================================= +// Includes +//============================================================================= +#include "RP2350.h" +#include "USB.h" +#include "usb_hwreg.h" +#include "usb_types.h" +#include + +//============================================================================= +// Globals (Debug purpose only) +//============================================================================= +#define ENABLE_DEBUG_USB 0 +#define ENABLE_DEBUG_HLT 0 + +#if ENABLE_DEBUG_USB + #define __DEBUG_USB__ +#endif + +#if ENABLE_DEBUG_USB && ENABLE_DEBUG_HLT + #define __DEBUG_HALT__ +#endif + +#ifdef __DEBUG_USB__ +volatile uint64 _EP0_[100] = {0}; +volatile uint32 _EP0_index = 0; + +volatile uint64 _EP0_SpecificReq[100] = {0}; +volatile uint32 _EP0_SpecificReq_index = 0; + +volatile uint32 BusResetCounter = 0; + +volatile uint32 UsbReceived_EP0_OUT_count = 0; +volatile uint32 UsbReceived_EP0_IN_count = 0; + +volatile uint32 UsbReceived_EP1_IN_count = 0; +volatile uint32 UsbReceived_EP1_OUT_count = 0; + +volatile uint32 UsbReceived_EP2_IN_count = 0; +volatile uint32 UsbReceived_EP2_OUT_count = 0; + +volatile uint32 UsbReceived_EP3_IN_count = 0; +volatile uint32 UsbReceived_EP3_OUT_count = 0; + +volatile uint32 UsbNotSupportedRequestCount = 0; + +volatile uint32 boHaltBeforeEnableUsb = 1; +#endif +//============================================================================= +// Local types +//============================================================================= +typedef void (*pStandardRequestHandler)(const tUsbSetupPacket* const pUsbSetupPacket); + +//============================================================================= +// Static functions +//============================================================================= +static void UsbDriver_HandleSetupPacket (const tUsbSetupPacket* const pUsbSetupPacket); +static boolean UsbDriver_SendDataToHost (uint8 endpoint, uint8 pid, uint8* buffer, uint8 size); +static boolean UsbDriver_ConfigureEpOutBuf (uint8 endpoint, uint8 pid, uint8 size); +static boolean UsbDriver_SendStallToHost (uint8 endpoint, uint8 pid); +static boolean UsbDriver_ConfigureEndpoint (uint8 endpoint, uint8 direction, uint8 type); +static void UsbDriver_Req_get_status (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_clear_feature (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_set_feature (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_set_address (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_get_descriptor (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_set_descriptor (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_get_configuration (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_set_configuration (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_get_interface (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_set_interface (const tUsbSetupPacket* const pUsbSetupPacket); +static void UsbDriver_Req_synch_frame (const tUsbSetupPacket* const pUsbSetupPacket); + +//============================================================================= +// Globals +//============================================================================= +static volatile uint32 UsbDeviceAddress = 0; +static volatile uint8 EPx_dataPid[16] = {DATA0_PID}; + +static const pStandardRequestHandler + StandardRequestHandlerLockupTable[13] = { + UsbDriver_Req_get_status, + UsbDriver_Req_clear_feature, + NULL, + UsbDriver_Req_set_feature, + NULL, + UsbDriver_Req_set_address, + UsbDriver_Req_get_descriptor, + UsbDriver_Req_set_descriptor, + UsbDriver_Req_get_configuration, + UsbDriver_Req_set_configuration, + UsbDriver_Req_get_interface, + UsbDriver_Req_set_interface, + UsbDriver_Req_synch_frame + }; + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +void USBCTRL_IRQ(void) +{ + /* handle SETUP packets */ + if(USBCTRL_REGS->INTS.bit.SETUP_REQ) + { + /* clear the interrupt */ + USBCTRL_REGS->SIE_STATUS.bit.SETUP_REC = 1u; + + /* get the SETUP packet data */ + const tUsbSetupPacket* const UsbSetupPacket = (const tUsbSetupPacket* const)USBCTRL_DPRAM_BASE; + + /* call the appropriate SETUP packet handler */ + UsbDriver_HandleSetupPacket(UsbSetupPacket); + +#ifdef __DEBUG_USB__ + //save the data + _EP0_[_EP0_index++] = *(volatile uint64*)(USBCTRL_DPRAM_BASE); +#endif + } + + /* handle bus reset */ + if(USBCTRL_REGS->INTS.bit.BUS_RESET) + { + /* clear the bus reset interrupt flag */ + USBCTRL_REGS->SIE_STATUS.bit.BUS_RESET = 1; + USBCTRL_REGS->ADDR_ENDP.bit.ADDRESS = 0; + UsbDeviceAddress = 0; +#ifdef __DEBUG_USB__ + BusResetCounter++; +#endif + } + + /* handle OUT and IN packets */ + if(USBCTRL_REGS->INTS.bit.BUFF_STATUS) + { + /***************************************************************************/ + /* endpoint 0 */ + /***************************************************************************/ + if(USBCTRL_REGS->BUFF_STATUS.bit.EP0_OUT) + { +#ifdef __DEBUG_USB__ + UsbReceived_EP0_OUT_count++; +#endif + /* clear the EP0_OUT buffer status */ + USBCTRL_REGS->BUFF_STATUS.bit.EP0_OUT = 1; + + /* configure the expected OUT packet */ + UsbDriver_ConfigureEpOutBuf(EP0, DATA1_PID, 64); + } + + if(USBCTRL_REGS->BUFF_STATUS.bit.EP0_IN) + { + /* this bit indicate that the DATA is received by the HOST and we received ACK from HOST, the EP0_IN buffer is empty + (USBCTRL_DPRAM->EP0_IN_BUFFER_CONTROL.bit.FULL_0 is cleared to indicate that data has been sent). + */ +#ifdef __DEBUG_USB__ + UsbReceived_EP0_IN_count++; +#endif + /* clear the EP0_IN buffer status */ + USBCTRL_REGS->BUFF_STATUS.bit.EP0_IN = 1; + + if(UsbDeviceAddress != 0) + { + /* setup device address */ + USBCTRL_REGS->ADDR_ENDP.reg |= (uint32)(UsbDeviceAddress & 0x7Ful); + } + + /* configure the expected OUT packet */ + UsbDriver_ConfigureEpOutBuf(EP0, DATA1_PID, 64); + } + + /***************************************************************************/ + /* endpoint 1 */ + /***************************************************************************/ + if(USBCTRL_REGS->BUFF_STATUS.bit.EP1_OUT) + { +#ifdef __DEBUG_USB__ + UsbReceived_EP1_OUT_count++; +#endif + /* clear the EP1_OUT buffer status */ + USBCTRL_REGS->BUFF_STATUS.bit.EP1_OUT = 1; + + /* TODO: copy the received data and call the handler */ + + EPx_dataPid[EP1] ^= 1u; + UsbDriver_ConfigureEpOutBuf(EP1, EPx_dataPid[EP1], 64u); + } + if(USBCTRL_REGS->BUFF_STATUS.bit.EP1_IN) + { +#ifdef __DEBUG_USB__ + UsbReceived_EP1_IN_count++; +#endif + /* clear the EP1_IN buffer status */ + USBCTRL_REGS->BUFF_STATUS.bit.EP1_IN = 1; + + /* TODO: notify the handler */ + + /* update the EP1_OUT buffer config with the new expect data pid */ + EPx_dataPid[EP1] ^= 1u; + UsbDriver_ConfigureEpOutBuf(EP1, EPx_dataPid[EP1], 64u); + } + /***************************************************************************/ + /* endpoint 2 */ + /***************************************************************************/ + if(USBCTRL_REGS->BUFF_STATUS.bit.EP2_OUT) + { +#ifdef __DEBUG_USB__ + UsbReceived_EP2_OUT_count++; +#endif + /* clear the EP2_OUT buffer status */ + USBCTRL_REGS->BUFF_STATUS.bit.EP2_OUT = 1; + + /* TODO: copy the received data and call the handler */ + + EPx_dataPid[EP2] ^= 1u; + UsbDriver_ConfigureEpOutBuf(EP2, EPx_dataPid[EP2], 64u); + } + if(USBCTRL_REGS->BUFF_STATUS.bit.EP2_IN) + { +#ifdef __DEBUG_USB__ + UsbReceived_EP2_IN_count++; +#endif + /* clear the EP2_IN buffer status */ + USBCTRL_REGS->BUFF_STATUS.bit.EP2_IN = 1; + + /* TODO: notify the handler */ + + /* update the EP2_OUT buffer config with the new expect data pid */ + EPx_dataPid[EP2] ^= 1u; + UsbDriver_ConfigureEpOutBuf(EP2, EPx_dataPid[EP2], 64u); + } + /***************************************************************************/ + /* endpoint 3 */ + /***************************************************************************/ + if(USBCTRL_REGS->BUFF_STATUS.bit.EP3_OUT) + { +#ifdef __DEBUG_USB__ + UsbReceived_EP3_OUT_count++; +#endif + /* clear the EP3_OUT buffer status */ + USBCTRL_REGS->BUFF_STATUS.bit.EP3_OUT = 1; + + /* TODO: copy the received data and call the handler */ + + EPx_dataPid[EP3] ^= 1u; + UsbDriver_ConfigureEpOutBuf(EP3, EPx_dataPid[EP3], 64u); + } + if(USBCTRL_REGS->BUFF_STATUS.bit.EP3_IN) + { +#ifdef __DEBUG_USB__ + UsbReceived_EP3_IN_count++; +#endif + /* clear the EP3_IN buffer status */ + USBCTRL_REGS->BUFF_STATUS.bit.EP3_IN = 1; + + /* TODO: notify the handler */ + + /* update the EP3_OUT buffer config with the new expect data pid */ + EPx_dataPid[EP3] ^= 1u; + UsbDriver_ConfigureEpOutBuf(EP3, EPx_dataPid[EP3], 64u); + } + } + + /* handle EP's NAK and STALL notification */ + if(USBCTRL_REGS->INTS.bit.EP_STALL_NAK) + { + if(USBCTRL_REGS->EP_STATUS_STALL_NAK.bit.EP1_IN) + { + /* NAK token was sent by the device controller as response for IN token from host. + this means that the host is requesting a DATA packet on EP1_IN + */ + /* clear the EP1_IN NAK interrupt flag */ + USBCTRL_REGS->EP_STATUS_STALL_NAK.bit.EP1_IN = 1u; + + /* send back the last received data from the host (echo test) */ + uint8* const pBuffer_EP1 = (uint8*)((uint32)(USBCTRL_DPRAM_BASE + 0x100u + (EP1 * 0x80u))); + UsbDriver_SendDataToHost(EP1, EPx_dataPid[EP1], pBuffer_EP1, 4u); + } + + if(USBCTRL_REGS->EP_STATUS_STALL_NAK.bit.EP2_IN) + { + /* NAK token was sent by the device controller as response for IN token from host. + this means that the host is requesting a DATA packet on EP2_IN + */ + /* clear the EP2_IN NAK interrupt flag */ + USBCTRL_REGS->EP_STATUS_STALL_NAK.bit.EP2_IN = 1u; + } + + if(USBCTRL_REGS->EP_STATUS_STALL_NAK.bit.EP3_IN) + { + /* NAK token was sent by the device controller as response for IN token from host. + this means that the host is requesting a DATA packet on EP3_IN + */ + /* clear the EP3_IN NAK interrupt flag */ + USBCTRL_REGS->EP_STATUS_STALL_NAK.bit.EP3_IN = 1u; + } + } +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +void UsbInit(void) +{ + //release the reset of PLL_USB + RESETS->RESET.bit.pll_usb = 0u; + while(RESETS->RESET_DONE.bit.pll_usb != 1); + + //configure the PLL_USB + PLL_USB->CS.bit.REFDIV = 1u; + PLL_USB->FBDIV_INT.bit.FBDIV_INT = 40U; + PLL_USB->PRIM.bit.POSTDIV1 = 5U; + PLL_USB->PRIM.bit.POSTDIV2 = 2U; + + PLL_USB->PWR.bit.PD = 0u; + PLL_USB->PWR.bit.VCOPD = 0u; + + while(PLL_USB->CS.bit.LOCK != 1u); + + PLL_USB->PWR.bit.POSTDIVPD = 0u; + + // switch the system clock to use the PLL + CLOCKS->CLK_SYS_CTRL.bit.AUXSRC = CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_pll_sys; + CLOCKS->CLK_SYS_CTRL.bit.SRC = CLOCKS_CLK_SYS_CTRL_SRC_clksrc_clk_sys_aux; + + //switch on the USB clock + CLOCKS->CLK_USB_CTRL.bit.AUXSRC = CLOCKS_CLK_USB_CTRL_AUXSRC_clksrc_pll_usb; + CLOCKS->CLK_USB_CTRL.bit.ENABLE = 1u; + + // switch off the ROSC clock + + //release reset of usb + RESETS->RESET.bit.usbctrl = 0u; + while(RESETS->RESET_DONE.bit.usbctrl != 1); + + //clear the DPRAM + for(uint32 i=0; i < 4096U; i = i+8) + { + *(volatile uint64*)(USBCTRL_DPRAM_BASE + i) = 0; + } + + //enable USB + USBCTRL_REGS->USB_MUXING.bit.TO_PHY = 1u; + USBCTRL_REGS->USB_MUXING.bit.SOFTCON = 0u; + USBCTRL_REGS->MAIN_CTRL.bit.HOST_NDEVICE = 0u; + + USBCTRL_REGS->USB_PWR.bit.VBUS_DETECT = 1u; + USBCTRL_REGS->USB_PWR.bit.VBUS_DETECT_OVERRIDE_EN = 1u; + + USBCTRL_REGS->MAIN_CTRL.bit.CONTROLLER_EN = 1u; + + USBCTRL_REGS->SIE_CTRL.bit.EP0_INT_1BUF = 1u; + + //enable usb interrupt + USBCTRL_REGS->INTE.bit.BUFF_STATUS = 1u; // note: this interrupt is needed to detect OUT and IN requests send by the host. + USBCTRL_REGS->INTE.bit.BUS_RESET = 1u; // note: this interrupt is needed to detect a reset state on the USB bus. + USBCTRL_REGS->INTE.bit.SETUP_REQ = 1u; // note: this interrupt is needed to notify the CPU about a received SETUP packet. + USBCTRL_REGS->INTE.bit.EP_STALL_NAK = 1u; // note: this interrupt is needed to notify the CPU about a sent/received NAK/STALL packet. + + //enable NVIC + NVIC_EnableIRQ(USBCTRL_IRQ_IRQn); + __enable_irq(); + + /* enable endpoint 1 */ + UsbDriver_ConfigureEndpoint(EP1, EP_DIR_IN, 2u); + UsbDriver_ConfigureEndpoint(EP1, EP_DIR_OUT, 2u); + UsbDriver_ConfigureEpOutBuf(EP1, EPx_dataPid[EP1], 64u); + + /* enable endpoint 2 */ + UsbDriver_ConfigureEndpoint(EP2, EP_DIR_IN, 2u); + UsbDriver_ConfigureEndpoint(EP2, EP_DIR_OUT, 2u); + UsbDriver_ConfigureEpOutBuf(EP2, EPx_dataPid[EP2], 64u); + + /* enable endpoint 3 */ + UsbDriver_ConfigureEndpoint(EP3, EP_DIR_IN, 3u); + +#ifdef __DEBUG_HALT__ + while(boHaltBeforeEnableUsb); +#endif + + /* enable the USB controller */ + USBCTRL_REGS->SIE_CTRL.bit.PULLUP_EN = 1u; + +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static boolean UsbDriver_ConfigureEndpoint(uint8 endpoint, uint8 direction, uint8 type) +{ + boolean status = FALSE; + + if(endpoint > 0u && endpoint < 16u) + { + if(EP_DIR_IN == direction) + { + volatile EPx_CONTROL* epx_in_control = (volatile EPx_CONTROL*)(USBCTRL_DPRAM_BASE + (EPx_IN_CONTROL_OFFSET * endpoint)); + epx_in_control->reg = 0; + epx_in_control->bit.INTERRUPT_PER_BUFF = 1u; + epx_in_control->bit.INTERRUPT_ON_NAK = 1u; + epx_in_control->bit.INTERRUPT_ON_STALL = 1u; + epx_in_control->bit.ENDPOINT_TYPE = type & 0x03u; + epx_in_control->bit.BUFFER_ADDRESS = (uint16)(0x100u + (endpoint * 0x80u)); + epx_in_control->bit.ENABLE = 1u; + } + else if(EP_DIR_OUT == direction) + { + volatile EPx_CONTROL* epx_out_control = (volatile EPx_CONTROL*)(USBCTRL_DPRAM_BASE + EPx_OUT_CONTROL_OFFSET + ((endpoint)* 8ul)); + epx_out_control->reg = 0u; + epx_out_control->bit.INTERRUPT_PER_BUFF = 1u; + epx_out_control->bit.ENDPOINT_TYPE = type & 0x03u; + epx_out_control->bit.BUFFER_ADDRESS = (uint16)(0x100u + (endpoint * 0x80u)); + epx_out_control->bit.ENABLE = 1u; + } + else + { + /* wrong endpoint direction */ + return(status); + } + status = TRUE; + } + + return(status); +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static boolean UsbDriver_SendDataToHost(uint8 endpoint, uint8 pid, uint8* buffer, uint8 size) +{ + boolean status = FALSE; + + EPx_BUFFER_CONTROL* epx_in_buffer_control = (EPx_BUFFER_CONTROL*)(USBCTRL_DPRAM_BASE + EPx_IN_BUFFER_CONTROL_OFFSET + (endpoint * 8ul)); + + if((size < 65u) && (endpoint < 16u) && (pid < 2u)) + { + if(buffer != NULL) + { + for(uint8 i = 0; i < size; i++) + { + ((volatile uint8*)(USBCTRL_DPRAM_BASE + 0x100ul + (endpoint * 0x80ul)))[i] = buffer[i]; + } + } + + epx_in_buffer_control->reg = 0; + epx_in_buffer_control->bit.LENGTH_0 = size; + epx_in_buffer_control->bit.AVAILABLE_0 = 1u; + epx_in_buffer_control->bit.PID_0 = (pid == 0 ? 0 : 1); + epx_in_buffer_control->bit.FULL_0 = 1u; + + status = TRUE; + } + + return(status); +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static boolean UsbDriver_SendStallToHost(uint8 endpoint, uint8 pid) +{ + boolean status = FALSE; + + EPx_BUFFER_CONTROL* epx_in_buffer_control = (EPx_BUFFER_CONTROL*)(USBCTRL_DPRAM_BASE + EPx_IN_BUFFER_CONTROL_OFFSET + (endpoint * 8ul)); + + if((endpoint < 16u) && (pid < 2u)) + { + epx_in_buffer_control->reg = 0; + epx_in_buffer_control->bit.LENGTH_0 = 0; + epx_in_buffer_control->bit.AVAILABLE_0 = 1u; + epx_in_buffer_control->bit.PID_0 = (pid == 0 ? 0 : 1); + epx_in_buffer_control->bit.STALL = 1u; + + if(endpoint == EP0) + { + USBCTRL_REGS->EP_STALL_ARM.bit.EP0_IN = 1u; + } + epx_in_buffer_control->bit.FULL_0 = 1u; + + status = TRUE; + } + + return(status); +} +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static boolean UsbDriver_ConfigureEpOutBuf(uint8 endpoint, uint8 pid, uint8 size) +{ + boolean status = FALSE; + + EPx_BUFFER_CONTROL* epx_out_buffer_control = (EPx_BUFFER_CONTROL*)(USBCTRL_DPRAM_BASE + EPx_OUT_BUFFER_CONTROL_OFFSET + (endpoint * 8ul)); + + if((size < 65u) && (endpoint < 16u) && (pid < 2u)) + { + /* configure the expected OUT packet */ + epx_out_buffer_control->reg = 0; + epx_out_buffer_control->bit.LENGTH_0 = size; + epx_out_buffer_control->bit.AVAILABLE_0 = 1u; + epx_out_buffer_control->bit.PID_0 = (pid == 0 ? 0 : 1); + epx_out_buffer_control->bit.FULL_0 = 0u; + status = TRUE; + } + + return(status); +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_HandleSetupPacket(const tUsbSetupPacket* const pUsbSetupPacket) +{ + const uint8 Request = pUsbSetupPacket->bRequest; + const tbmRequestType* const bmRequestType = (tbmRequestType*)(pUsbSetupPacket); + + if((bmRequestType->Type == USB_REQ_TYPE_STANDARD) && (Request < 13u) && (StandardRequestHandlerLockupTable[Request] != NULL)) + { + /* call the appropriate handler */ + StandardRequestHandlerLockupTable[Request](pUsbSetupPacket); + } + else if(bmRequestType->Type == USB_REQ_TYPE_CLASS) + { + /* class specific requests */ + if(bmRequestType->TransferDirection == USB_REQ_DIR_DEVICE_TO_HOST) + { + /* IN token is expected from the host, handle the specific request immediatly to the upper layer */ + if(Request == 0x21u) + { + /* GET_LINE_CODING */ + uint8 LineCodingFormat[7] = { 0x80, + 0x25, + 0, + 0, + 0, + 0, + 8 + }; + UsbDriver_SendDataToHost(EP0, DATA1_PID, (uint8*)LineCodingFormat, 7u); + } + } + else + { + /* OUT token is expected from the host, handle the specific request to upper layer after receiving the data on EP0 */ + if(Request == 0x20u) + { + /* SET_LINE_CODING */ + UsbDriver_SendDataToHost(EP0, DATA1_PID, NULL, 0); + } + else if(Request == 0x22u) + { + /* SET_CONTROL_LINE_STATE */ + UsbDriver_SendDataToHost(EP0, DATA1_PID, NULL, 0); + } + else + { + } + } +#ifdef __DEBUG_USB__ + _EP0_SpecificReq[_EP0_SpecificReq_index++] = *(volatile uint64*)pUsbSetupPacket; +#endif + } + else + { + for(;;); + } +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_get_status(const tUsbSetupPacket* const pUsbSetupPacket) +{ + (void)pUsbSetupPacket; +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_clear_feature(const tUsbSetupPacket* const pUsbSetupPacket) +{ + (void)pUsbSetupPacket; +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_set_feature(const tUsbSetupPacket* const pUsbSetupPacket) +{ + (void)pUsbSetupPacket; +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_set_address(const tUsbSetupPacket* const pUsbSetupPacket) +{ + UsbDeviceAddress = pUsbSetupPacket->wValue; + UsbDriver_SendDataToHost(EP0, DATA1_PID, NULL, 0); +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_get_descriptor(const tUsbSetupPacket* const pUsbSetupPacket) +{ + const uint8 DescriptorType = (uint8)(pUsbSetupPacket->wValue >> 8); + + if(USB_DESCRIPTOR_TYPE_DEVICE == DescriptorType) + { + /* send the device descriptor */ + const unsigned char device_dsc[0x12] = { + 0x12, // bLength + 0x01, // bDescriptorType (Device) + 0x10, 0x01, // bcdUSB (1.1) + 0xEF, // bDeviceClass (Miscellaneous Device Class) + 0x02, // bDeviceSubClass (Common Class) + 0x01, // bDeviceProtocol (Interface Association Descriptor) + 0x40, // bMaxPacketSize0 (64 bytes) + 0x8a, 0x2e, // idVendor + 0x0a, 0x00, // idProduct + 0x01, 0x00, // bcdDevice (Device Version 0.01) + 0x01, // iManufacturer (String Index 1) + 0x02, // iProduct (String Index 2) + 0x03, // iSerialNumber (String Index 3) + 0x01 // bNumConfigurations (1 configuration) + }; + UsbDriver_SendDataToHost(EP0, DATA1_PID, (uint8*)device_dsc, sizeof(device_dsc)); + } + else if(USB_DESCRIPTOR_TYPE_CONFIGURATION == DescriptorType) + { + /* send configuration descriptor */ + static const uint8 configuration_dsc[] = { + /* Configuration Descriptor */ + 0x09, // bLength: Configuration Descriptor size + 0x02, // bDescriptorType: Configuration + 98, 0x00, // wTotalLength: The number of bytes in the configuration descriptor and all of its subordinate descriptors + 0x03, // bNumInterfaces: 3 interfaces (1 for vendor custom class, 1 for CDC Control and 1 for CDC Data) + 0x01, // bConfigurationValue: this Configuration index + 0x00, // iConfiguration: Index of string descriptor describing the configuration + 0x80, // bmAttributes: Self-powered + 250, // bMaxPower: 500 mA + + // Interface Descriptor (vendor custom class) + 0x09, // bLength - Descriptor size in bytes (09h) + 0x04, // bDescriptorType - The constant Interface (04h) + 0, // bInterfaceNumber - Interface number 0 + 0, // bAlternateSetting - A number that identifies a descriptor with alternate settings for this bInterfaceNumber. + 2, // bNumEndpoint - Number of endpoints supported not counting endpoint zero + 0xff, // bInterfaceClass - Class code + 0xff, // bInterfaceSubclass - Subclass code + 0xff, // bInterfaceProtocol - Protocol code + 0, // iInterface - Interface string index + + // Endpoint Descriptor (IN) + 0x07, // bLength - Descriptor size in bytes (07h) + 0x05, // bDescriptorType - The constant Endpoint (05h) + EP_DIR_IN | EP1, // bEndpointAddress - Endpoint number and direction + 0x02, // bmAttributes - Transfer type and supplementary information + 0x40,0x00, // wMaxPacketSize - Maximum packet size supported + 255, // bInterval - Service interval or NAK rate + + // Endpoint Descriptor (OUT) + 0x07, // bLength - Descriptor size in bytes (07h) + 0x05, // bDescriptorType - The constant Endpoint (05h) + EP_DIR_OUT | EP1, // bEndpointAddress - Endpoint number and direction + 0x02, // bmAttributes - Transfer type and supplementary information + 0x40,0x00, // wMaxPacketSize - Maximum packet size supported + 255, // bInterval - Service interval or NAK rate + + /* Interface Association Descriptor (IAD) for CDC/ACM */ + 0x08, // bLength: Interface Descriptor size + 0x0B, // bDescriptorType: IAD + 0x01, // bFirstInterface: First interface number (1) + 0x02, // bInterfaceCount: Number of interfaces for this function (2) + 0x02, // bFunctionClass: Communication Interface Class (CDC) + 0x02, // bFunctionSubClass: Abstract Control Model (ACM) + 0x00, // bFunctionProtocol: ???? + 0x00, // iFunction: Index of string descriptor describing this function + + /* Interface Descriptor (CDC Control) */ + 0x09, // bLength: Interface Descriptor size + 0x04, // bDescriptorType: Interface + 1, // bInterfaceNumber: Interface number 1 + 0x00, // bAlternateSetting: Alternate setting + 0x01, // bNumEndpoints: One endpoint (CDC Control) + 0x02, // bInterfaceClass: CDC + 0x02, // bInterfaceSubClass: Abstract Control Model + 0x00, // bInterfaceProtocol: V.25ter (AT commands) + 0x00, // iInterface: Index of string descriptor describing this interface + + /* CDC Header Functional Descriptor */ + 0x05, // bLength: CDC header Descriptor size + 0x24, // bDescriptorType: CS_INTERFACE + 0x00, // bDescriptorSubType: Header + 0x20, 0x01, // bcdCDC: CDC specification release number + + /* CDC Call Management Functional Descriptor */ + 0x05, // bLength: CDC Call Management Descriptor size + 0x24, // bDescriptorType: CS_INTERFACE + 0x01, // bDescriptorSubType: Call Management + 0x00, // bmCapabilities: Device does not handle call management itself + 0x02, // bDataInterface: Interface number of Data Class interface + + /* CDC Abstract Control Management Functional Descriptor */ + 0x04, // bLength: CDC Abstract Control Management Descriptor size + 0x24, // bDescriptorType: CS_INTERFACE + 0x02, // bDescriptorSubType: Abstract Control Management + 0x02, // bmCapabilities: Device supports the request combination of Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State + + /* CDC Union Functional Descriptor */ + 0x05, // bLength: CDC Union Descriptor size + 0x24, // bDescriptorType: CS_INTERFACE + 0x06, // bDescriptorSubType: Union + 0x01, // bControlInterface: Interface number of the Control interface + 0x02, // bSubordinateInterface0: Interface number of the subordinate interface + + /* Endpoint Descriptor (CDC Control IN) */ + 0x07, // bLength: Endpoint Descriptor size + 0x05, // bDescriptorType: Endpoint + EP_DIR_IN | EP3, // bEndpointAddress: CDC Control endpoint address (IN) + 0x03, // bmAttributes: Interrupt + 0x08, 0x00, // wMaxPacketSize: CDC Control packet size (8 bytes) + 0x10, // bInterval: Polling interval (16ms) + + /* Interface Descriptor (CDC Data) */ + 0x09, // bLength: Interface Descriptor size + 0x04, // bDescriptorType: Interface + 2, // bInterfaceNumber: Interface number 2 + 0x00, // bAlternateSetting: Alternate setting + 0x02, // bNumEndpoints: Two endpoints (CDC Data) + 0x0A, // bInterfaceClass: CDC Data + 0x00, // bInterfaceSubClass + 0x00, // bInterfaceProtocol + 0x00, // iInterface: Index of string descriptor describing this interface + + /* Endpoint Descriptor (CDC Data IN) */ + 0x07, // bLength: Endpoint Descriptor size + 0x05, // bDescriptorType: Endpoint + EP_DIR_IN | EP2, // bEndpointAddress: CDC Data IN endpoint address + 0x02, // bmAttributes: Bulk + 0x40, 0x00, // wMaxPacketSize: CDC Data packet size (64 bytes) + 0x00, // bInterval: Never NAK + + /* Endpoint Descriptor (CDC Data OUT) */ + 0x07, // bLength: Endpoint Descriptor size + 0x05, // bDescriptorType: Endpoint + EP_DIR_OUT | EP2, // bEndpointAddress: CDC Data OUT endpoint address + 0x02, // bmAttributes: Bulk + 0x40, 0x00, // wMaxPacketSize: CDC Data packet size (64 bytes) + 0x00 // bInterval: Never NAK + }; + + + /* check the configuration size requested by the host + note: we must send exactly the requested size otherwise the host will abort the enumeration process */ + const uint8 size = (((uint8)(pUsbSetupPacket->wLength) > sizeof(configuration_dsc)) && (sizeof(configuration_dsc) < 65u)) ? sizeof(configuration_dsc) : (uint8)(pUsbSetupPacket->wLength); + + const uint8 number_of_64_packet_size = sizeof(configuration_dsc) / 64u; + const uint8 remaining_config_data_size = sizeof(configuration_dsc) % 64u; + + EPx_BUFFER_CONTROL* epx_in_buffer_control = (EPx_BUFFER_CONTROL*)(USBCTRL_DPRAM_BASE + EPx_IN_BUFFER_CONTROL_OFFSET + (EP0 * 8ul)); + + if(size > 64u) + { + uint8 data_pid = DATA1_PID; + + for(uint32 i=0; i < number_of_64_packet_size; i++) + { + UsbDriver_SendDataToHost(EP0, data_pid, (uint8*)((uint32)configuration_dsc + i*64u), (uint8)64); + + data_pid ^= 1u; + + /* wait till the buffer got transmitterd */ + while(epx_in_buffer_control->bit.FULL_0); + } + + /* send the remaining data */ + UsbDriver_SendDataToHost(EP0, data_pid, (uint8*)((uint32)configuration_dsc + number_of_64_packet_size*64u), (uint8)remaining_config_data_size); + + } + else + { + /* only one packet of 64-byte max */ + /* send the configuration to the host */ + UsbDriver_SendDataToHost(EP0, DATA1_PID, (uint8*)configuration_dsc, (uint8)size); + } + } + else if(USB_DESCRIPTOR_TYPE_HID_REPORT == DescriptorType) + { + const uint8 hid_rpt_desc[] = + { + 0x06, 0x00, 0xFF, // Usage Page = 0xFF00 (Vendor Defined Page 1) + 0x09, 0x01, // Usage (Vendor Usage 1) + 0xA1, 0x01, // Collection (Application) + // Input report + 0x19, 0x01, // Usage Minimum + 0x29, 0x40, // Usage Maximum + 0x15, 0x00, // Logical Minimum (data bytes in the report may have minimum value = 0x00) + 0x26, 0xFF, 0x00, // Logical Maximum (data bytes in the report may have maximum value = 0x00FF = unsigned 255) + 0x75, 0x08, // Report Size: 8-bit field size + 0x95, 64, // Report Count + 0x81, 0x02, // Input (Data, Array, Abs) + // Output report + 0x19, 0x01, // Usage Minimum + 0x29, 0x40, // Usage Maximum + 0x75, 0x08, // Report Size: 8-bit field size + 0x95, 64, // Report Count + 0x91, 0x02, // Output (Data, Array, Abs) + 0xC0 // End Collection + }; + + UsbDriver_SendDataToHost(EP0, DATA1_PID, (uint8*)hid_rpt_desc, sizeof(hid_rpt_desc)); + + } + else if(USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER == DescriptorType) + { + /* As DEVICE_QUALIFIER is used only for high speed we will not support it on RP2350 (has only a full speed device controller) */ + UsbDriver_SendStallToHost(EP0, DATA1_PID); + } + else if(USB_DESCRIPTOR_TYPE_STRING == DescriptorType) + { + const tUsbStringDescriptor UsbStringDescriptor = {4, 0x03, {0x0409}}; + const tUsbSubsequentStringDescriptor UsbSubsequentStringDescriptor_0 = {30, 0x03, {'C','H','A','L','A','N','D','I',' ','A','M','I','N','E'}}; /* Manufacturer string descriptor */ + const tUsbSubsequentStringDescriptor UsbSubsequentStringDescriptor_1 = {36, 0x03, {'C','H','A','L','A','N','D','I',' ','D','E','B','U','G','G','E','R'}}; /* Product string descriptor */ + const tUsbSubsequentStringDescriptor UsbSubsequentStringDescriptor_2 = {10, 0x03, {'2','0','2','3'}}; /* SerialNumber */ + + const uint8 StrIdx = (uint8)pUsbSetupPacket->wValue; + + if(StrIdx == 0u) + { + UsbDriver_SendDataToHost(EP0, DATA1_PID, (uint8*)&UsbStringDescriptor,UsbStringDescriptor.bLength); + } + else if(StrIdx == 1u) + { + UsbDriver_SendDataToHost(EP0, DATA1_PID, (uint8*)&UsbSubsequentStringDescriptor_0, UsbSubsequentStringDescriptor_0.bLength); + } + else if(StrIdx == 2u) + { + UsbDriver_SendDataToHost(EP0, DATA1_PID, (uint8*)&UsbSubsequentStringDescriptor_1, UsbSubsequentStringDescriptor_1.bLength); + } + else if(StrIdx == 3u) + { + UsbDriver_SendDataToHost(EP0, DATA1_PID, (uint8*)&UsbSubsequentStringDescriptor_2, UsbSubsequentStringDescriptor_2.bLength); + } + else + { + UsbDriver_SendStallToHost(EP0, DATA1_PID); + } + } + else + { + + } +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_set_descriptor(const tUsbSetupPacket* const pUsbSetupPacket) +{ + (void)pUsbSetupPacket; +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_get_configuration(const tUsbSetupPacket* const pUsbSetupPacket) +{ + /* as we have only one configuration just send one to the host */ + (void)pUsbSetupPacket; + const uint8 config = 1; + UsbDriver_SendDataToHost(EP0, DATA1_PID, (uint8*)&config, 1); +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_set_configuration(const tUsbSetupPacket* const pUsbSetupPacket) +{ + /* as we have only one configuration just send ACK to the host */ + (void)pUsbSetupPacket; + UsbDriver_SendDataToHost(EP0, DATA1_PID, NULL, 0); +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_get_interface(const tUsbSetupPacket* const pUsbSetupPacket) +{ + (void)pUsbSetupPacket; +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_set_interface(const tUsbSetupPacket* const pUsbSetupPacket) +{ + (void)pUsbSetupPacket; +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +static void UsbDriver_Req_synch_frame(const tUsbSetupPacket* const pUsbSetupPacket) +{ + (void)pUsbSetupPacket; +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +void UsbDriver_SendSerialMsg(uint8* msg) +{ + UsbDriver_SendDataToHost(EP2, EPx_dataPid[EP2], (uint8*)msg, (uint8)strlen((const char*)msg)); +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +boolean UsbDriver_IsDeviceConnected(void) +{ + return(USBCTRL_REGS->SIE_STATUS.bit.CONNECTED == 1u ? TRUE : FALSE); +} diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.h new file mode 100644 index 000000000..1781337c9 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/USB.h @@ -0,0 +1,257 @@ +/****************************************************************************************** + Filename : USB.h + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : USB low level device driver header file + +******************************************************************************************/ + +#ifndef __USB_H__ +#define __USB_H__ + +#include "Platform_Types.h" +#include "usb_types.h" + +void USBCTRL_IRQ(void); +void UsbInit(void); +void UsbDriver_SendSerialMsg(uint8* msg); +boolean UsbDriver_IsDeviceConnected(void); + +/* endpoints IDs */ +#define EP0 0u +#define EP1 1u +#define EP2 2u +#define EP3 3u +#define EP4 4u +#define EP5 5u +#define EP6 6u +#define EP7 7u +#define EP8 8u +#define EP9 9u +#define EP10 10u +#define EP11 11u +#define EP12 12u +#define EP13 13u +#define EP14 14u +#define EP15 15u + +/* endpoints direction */ +#define EP_DIR_IN 0x80 +#define EP_DIR_OUT 0x00 + +/* Data PIDs */ +#define DATA0_PID 0u +#define DATA1_PID 1u + +/* SETUP Packet - Standard requests */ +#define USB_REQ_GET_STATUS 0u +#define USB_REQ_CLEAR_FEATURE 1u +#define USB_REQ_SET_FEATURE 3u +#define USB_REQ_SET_ADDRESS 5u +#define USB_REQ_GET_DESCRIPTOR 6u +#define USB_REQ_SET_DESCRIPTOR 7u +#define USB_REQ_GET_CONFIGURATION 8u +#define USB_REQ_SET_CONFIGURATION 9u +#define USB_REQ_GET_INTERFACE 10u +#define USB_REQ_SET_INTERFACE 11u +#define USB_REQ_SYNCH_FRAME 12u + +#define USB_REQ_DIR_DEVICE_TO_HOST 1u +#define USB_REQ_DIR_HOST_TO_DEVICE 0u + +#define USB_REQ_TYPE_STANDARD 0u +#define USB_REQ_TYPE_CLASS 1u +#define USB_REQ_TYPE_VENDOR 2u +#define USB_REQ_TYPE_RESERVED 3u + +#define USB_REQ_RECIPIENT_DEVICE 0u +#define USB_REQ_RECIPIENT_INTERFACE 1u +#define USB_REQ_RECIPIENT_ENDPOINT 2u + +/* Descriptor Types */ +#define USB_DESCRIPTOR_TYPE_DEVICE 1u +#define USB_DESCRIPTOR_TYPE_CONFIGURATION 2u +#define USB_DESCRIPTOR_TYPE_STRING 3u +#define USB_DESCRIPTOR_TYPE_INTERFACE 4u +#define USB_DESCRIPTOR_TYPE_ENDPOINT 5u +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 6u +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION 7u +#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER 8u +#define USB_DESCRIPTOR_TYPE_HID_REPORT 0x22u + + +/* USB device type */ +typedef struct +{ + uint32_t DeviceAddress; + tUsbDeviceDescriptor UsbDeviceDescriptor; + tUsbEndpointDescriptor UsbEndpointDescriptor; /* this must be a pointer to a pool of endpoints (maybe a linked list) */ + tUsbConfigurationDescriptor UsbConfigurationDescriptor; + uint8_t desc[]; +}__attribute__((packed)) UsbDeviceDriverContainer_t; + +#if 0 +static UsbDeviceDriverContainer_t UsbDeviceDriverContainer = { + /* DeviceAddress */ + 0, + /* UsbDeviceDescriptor */ + { + 0x12, // bLength + 0x01, // bDescriptorType (Device) + 0x10, 0x01, // bcdUSB (1.1) + 0xEF, // bDeviceClass (Miscellaneous Device Class) + 0x02, // bDeviceSubClass (Common Class) + 0x01, // bDeviceProtocol (Interface Association Descriptor) + 0x40, // bMaxPacketSize0 (64 bytes) + 0x8a, 0x2e, // idVendor + 0x0a, 0x00, // idProduct + 0x01, 0x00, // bcdDevice (Device Version 0.01) + 0x01, // iManufacturer (String Index 1) + 0x02, // iProduct (String Index 2) + 0x03, // iSerialNumber (String Index 3) + 0x01 // bNumConfigurations (1 configuration) + }, + /* UsbEndpointDescriptor */ + { + 0 + }, + /* UsbConfigurationDescriptor */ + { + /* Configuration Descriptor */ + 0x09, // bLength: Configuration Descriptor size + 0x02, // bDescriptorType: Configuration + 98, 0x00, // wTotalLength: The number of bytes in the configuration descriptor and all of its subordinate descriptors + 0x03, // bNumInterfaces: 3 interfaces (1 for vendor custom class, 1 for CDC Control and 1 for CDC Data) + 0x01, // bConfigurationValue: this Configuration index + 0x00, // iConfiguration: Index of string descriptor describing the configuration + 0x80, // bmAttributes: Self-powered + 250 // bMaxPower: 500 mA + }, + { + // Interface Descriptor (vendor custom class) + 0x09, // bLength - Descriptor size in bytes (09h) + 0x04, // bDescriptorType - The constant Interface (04h) + 0, // bInterfaceNumber - Interface number 0 + 0, // bAlternateSetting - A number that identifies a descriptor with alternate settings for this bInterfaceNumber. + 2, // bNumEndpoint - Number of endpoints supported not counting endpoint zero + 0xff, // bInterfaceClass - Class code + 0xff, // bInterfaceSubclass - Subclass code + 0xff, // bInterfaceProtocol - Protocol code + 0, // iInterface - Interface string index + + // Endpoint Descriptor (IN) + 0x07, // bLength - Descriptor size in bytes (07h) + 0x05, // bDescriptorType - The constant Endpoint (05h) + EP_DIR_IN | EP1, // bEndpointAddress - Endpoint number and direction + 0x02, // bmAttributes - Transfer type and supplementary information + 0x40,0x00, // wMaxPacketSize - Maximum packet size supported + 255, // bInterval - Service interval or NAK rate + + // Endpoint Descriptor (OUT) + 0x07, // bLength - Descriptor size in bytes (07h) + 0x05, // bDescriptorType - The constant Endpoint (05h) + EP_DIR_OUT | EP1, // bEndpointAddress - Endpoint number and direction + 0x02, // bmAttributes - Transfer type and supplementary information + 0x40,0x00, // wMaxPacketSize - Maximum packet size supported + 255, // bInterval - Service interval or NAK rate + + /* Interface Association Descriptor (IAD) for CDC/ACM */ + 0x08, // bLength: Interface Descriptor size + 0x0B, // bDescriptorType: IAD + 0x01, // bFirstInterface: First interface number (1) + 0x02, // bInterfaceCount: Number of interfaces for this function (2) + 0x02, // bFunctionClass: Communication Interface Class (CDC) + 0x02, // bFunctionSubClass: Abstract Control Model (ACM) + 0x00, // bFunctionProtocol: ???? + 0x00, // iFunction: Index of string descriptor describing this function + + /* Interface Descriptor (CDC Control) */ + 0x09, // bLength: Interface Descriptor size + 0x04, // bDescriptorType: Interface + 1, // bInterfaceNumber: Interface number 1 + 0x00, // bAlternateSetting: Alternate setting + 0x01, // bNumEndpoints: One endpoint (CDC Control) + 0x02, // bInterfaceClass: CDC + 0x02, // bInterfaceSubClass: Abstract Control Model + 0x00, // bInterfaceProtocol: V.25ter (AT commands) + 0x00, // iInterface: Index of string descriptor describing this interface + + /* CDC Header Functional Descriptor */ + 0x05, // bLength: CDC header Descriptor size + 0x24, // bDescriptorType: CS_INTERFACE + 0x00, // bDescriptorSubType: Header + 0x20, 0x01, // bcdCDC: CDC specification release number + + /* CDC Call Management Functional Descriptor */ + 0x05, // bLength: CDC Call Management Descriptor size + 0x24, // bDescriptorType: CS_INTERFACE + 0x01, // bDescriptorSubType: Call Management + 0x00, // bmCapabilities: Device does not handle call management itself + 0x01, // bDataInterface: Interface number of Data Class interface + + /* CDC Abstract Control Management Functional Descriptor */ + 0x04, // bLength: CDC Abstract Control Management Descriptor size + 0x24, // bDescriptorType: CS_INTERFACE + 0x02, // bDescriptorSubType: Abstract Control Management + 0x02, // bmCapabilities: Device supports the request combination of Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State + + /* CDC Union Functional Descriptor */ + 0x05, // bLength: CDC Union Descriptor size + 0x24, // bDescriptorType: CS_INTERFACE + 0x06, // bDescriptorSubType: Union + 0x01, // bControlInterface: Interface number of the Control interface + 0x02, // bSubordinateInterface0: Interface number of the subordinate interface + + /* Endpoint Descriptor (CDC Control IN) */ + 0x07, // bLength: Endpoint Descriptor size + 0x05, // bDescriptorType: Endpoint + EP_DIR_IN | EP3, // bEndpointAddress: CDC Control endpoint address (IN) + 0x03, // bmAttributes: Interrupt + 0x08, 0x00, // wMaxPacketSize: CDC Control packet size (8 bytes) + 0x10, // bInterval: Polling interval (16ms) + + /* Interface Descriptor (CDC Data) */ + 0x09, // bLength: Interface Descriptor size + 0x04, // bDescriptorType: Interface + 2, // bInterfaceNumber: Interface number 2 + 0x00, // bAlternateSetting: Alternate setting + 0x02, // bNumEndpoints: Two endpoints (CDC Data) + 0x0A, // bInterfaceClass: CDC Data + 0x00, // bInterfaceSubClass + 0x00, // bInterfaceProtocol + 0x00, // iInterface: Index of string descriptor describing this interface + + /* Endpoint Descriptor (CDC Data IN) */ + 0x07, // bLength: Endpoint Descriptor size + 0x05, // bDescriptorType: Endpoint + EP_DIR_IN | EP2, // bEndpointAddress: CDC Data IN endpoint address + 0x02, // bmAttributes: Bulk + 0x40, 0x00, // wMaxPacketSize: CDC Data packet size (64 bytes) + 0x00, // bInterval: Never NAK + + /* Endpoint Descriptor (CDC Data OUT) */ + 0x07, // bLength: Endpoint Descriptor size + 0x05, // bDescriptorType: Endpoint + EP_DIR_OUT | EP2, // bEndpointAddress: CDC Data OUT endpoint address + 0x02, // bmAttributes: Bulk + 0x40, 0x00, // wMaxPacketSize: CDC Data packet size (64 bytes) + 0x00 // bInterval: Never NAK + } + }; + + + +#endif + + + +#endif diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/usb_hwreg.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/usb_hwreg.h new file mode 100644 index 000000000..72565fa41 --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/usb_hwreg.h @@ -0,0 +1,87 @@ + +#ifndef __USB_HWREG_H__ +#define __USB_HWREG_H__ + +#include + +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + + +typedef union { + __IOM uint32_t reg; /*!< (@ 0x00000080) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } bit; +} EPx_BUFFER_CONTROL; + +typedef union { + __IOM uint32_t reg; /*!< (@ 0x00000008) EP1_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } bit; +} EPx_CONTROL; + +#ifndef USBCTRL_DPRAM_BASE +#define USBCTRL_DPRAM_BASE 0x50100000UL +#endif + +#ifndef USBCTRL_REGS_BASE +#define USBCTRL_REGS_BASE 0x50110000UL +#endif + +#define EPx_IN_CONTROL_OFFSET 0x08 +#define EPx_OUT_CONTROL_OFFSET 0x04 + +#define EPx_IN_BUFFER_CONTROL_OFFSET 0x80 +#define EPx_OUT_BUFFER_CONTROL_OFFSET 0x84 + +#endif /*__USB_HWREG_H__*/ diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/usb_types.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/usb_types.h new file mode 100644 index 000000000..b5d93e9ff --- /dev/null +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/USB/usb_types.h @@ -0,0 +1,133 @@ + +#ifndef __USB_TYPES_H__ +#define __USB_TYPES_H__ + +#include "Platform_Types.h" + +//------------------------------------------------------------------------------------------------------------------ +// Setup Packet +//------------------------------------------------------------------------------------------------------------------ +typedef struct +{ + uint8 bmRequestType; + uint8 bRequest; + uint16 wValue; + uint16 wIndex; + uint16 wLength; +}tUsbSetupPacket; + +typedef struct +{ + uint8 Recipient:5u; + uint8 Type:2u; + uint8 TransferDirection:1u; +}tbmRequestType; + +//------------------------------------------------------------------------------------------------------------------ +// Device Descriptor +//------------------------------------------------------------------------------------------------------------------ +typedef struct +{ + uint8 bLength; //Size of the Descriptor in Bytes (18 bytes) + uint8 bDescriptorType; //Constant Device Descriptor (0x01) + uint8 bcdUSB_L; //USB Specification Number (LSB byte) which device complies too. + uint8 bcdUSB_H; //USB Specification Number (MSB byte) which device complies too. + uint8 bDeviceClass; //Class Code (Assigned by USB Org) If equal to Zero, each interface specifies it’s own class code If equal to 0xFF, the class code is vendor specified. Otherwise field is valid Class Code. + uint8 bDeviceSubClass; //SubClass Subclass Code (Assigned by USB Org) + uint8 bDeviceProtocol; //Protocol Protocol Code (Assigned by USB Org) + uint8 bMaxPacketSize; //Number Maximum Packet Size for Zero Endpoint. Valid Sizes are 8, 16, 32, 64 + uint8 idVendor_L; //Vendor ID (LSB byte) (Assigned by USB Org) + uint8 idVendor_H; //Vendor ID (MSB byte) (Assigned by USB Org) + uint8 idProduct_L; //Product ID (LSB byte) (Assigned by Manufacturer) + uint8 idProduct_H; //Product ID (MSB byte) (Assigned by Manufacturer) + uint8 bcdDevice_L; //Device Release Number (LSB byte) + uint8 bcdDevice_H; //Device Release Number (MSB byte) + uint8 iManufacturer; //Index of Manufacturer String Descriptor + uint8 iProduct; //Index of Product String Descriptor + uint8 iSerialNumber; //Index of Serial Number String Descriptor + uint8 bNumConfigurations; //Number of Possible Configurations +}tUsbDeviceDescriptor; + +//------------------------------------------------------------------------------------------------------------------ +// Configuration Descriptor +//------------------------------------------------------------------------------------------------------------------ +typedef struct +{ + uint8 bLength; //Size of Descriptor in Bytes + uint8 bDescriptorType; //Configuration Descriptor (0x02) + uint8 wTotalLength_L; //Total length in bytes of data returned (LSB byte) + uint8 wTotalLength_H; //Total length in bytes of data returned (MSB byte) + uint8 bNumInterfaces; //Number of Interfaces + uint8 bConfigurationValue; //Value to use as an argument to select this configuration + uint8 iConfiguration; //Index of String Descriptor describing this configuration + uint8 bmAttributes; //D7 Reserved, set to 1. (USB 1.0 Bus Powered) D6 Self Powered, D5 Remote Wakeup, D4..0 Reserved, set to 0. + uint8 bMaxPower; //Maximum Power Consumption in 2mA units +}tUsbConfigurationDescriptor; + +//------------------------------------------------------------------------------------------------------------------ +// Interface Descriptor +//------------------------------------------------------------------------------------------------------------------ +typedef struct +{ + uint8 bLength; //Size of Descriptor in Bytes (9 Bytes) + uint8 bDescriptorType; //Interface Descriptor (0x04) + uint8 bInterfaceNumber; //Number of Interface + uint8 bAlternateSetting; //Value used to select alternative setting + uint8 bNumEndpoints; //Number of Endpoints used for this interface + uint8 bInterfaceClass; //Class Code (Assigned by USB Org) + uint8 bInterfaceSubClass; //Subclass Code (Assigned by USB Org) + uint8 bInterfaceProtocol; //Protocol Code (Assigned by USB Org) + uint8 iInterface; //Index of String Descriptor Describing this interface +}tUsbInterfaceDescriptor; + +//------------------------------------------------------------------------------------------------------------------ +// Endpoint Descriptor +//------------------------------------------------------------------------------------------------------------------ +typedef struct +{ + uint8 bLength; //Size of Descriptor in Bytes (7 bytes) + uint8 bDescriptorType; //Endpoint Descriptor (0x05) + uint8 bEndpointAddress; //Endpoint AddressBits 0..3b Endpoint Number.Bits 4..6b Reserved. Set to Zero Bits 7 Direction 0 = Out, 1 = In (Ignored for Control Endpoints) + uint8 bmAttributes; //Bits 0..1 Transfer Type + //00 = Control + //01 = Isochronous + //10 = Bulk + //11 = Interrupt + //Bits 2..7 are reserved. If Isochronous endpoint, + //Bits 3..2 = Synchronisation Type (Iso Mode) + //00 = No Synchonisation + //01 = Asynchronous + //10 = Adaptive + //11 = Synchronous + //Bits 5..4 = Usage Type (Iso Mode) + //00 = Data Endpoint + //01 = Feedback Endpoint + //10 = Explicit Feedback Data Endpoint + //11 = Reserved + uint8 wMaxPacketSize_L; //Maximum Packet Size this endpoint is capable of sending or receiving (LSB byte) + uint8 wMaxPacketSize_H; //Maximum Packet Size this endpoint is capable of sending or receiving (MSB byte) + uint8 bInterval; //Interval for polling endpoint data transfers. Value in frame counts. Ignored for Bulk & Control Endpoints. Isochronous must equal 1 and field may range from 1 to 255 for interrupt endpoints. +}tUsbEndpointDescriptor; + +//------------------------------------------------------------------------------------------------------------------ +// String Descriptors +//------------------------------------------------------------------------------------------------------------------ +#define USB_NUMBER_OF_SUPPORTED_LANGUAGE 1U +#define USB_MAX_STRING_LENGTH 50U + +typedef struct +{ + uint8 bLength; //Size of Descriptor in Bytes + uint8 bDescriptorType; //String Descriptor (0x03) + uint16 wLANGID[USB_NUMBER_OF_SUPPORTED_LANGUAGE]; //Supported Language Code (e.g. 0x0409 English - United States) +}tUsbStringDescriptor; + + +typedef struct +{ + uint8 bLength; //Size of Descriptor in Bytes + uint8 bDescriptorType; //String Descriptor (0x03) + uint16 bString[USB_MAX_STRING_LENGTH]; //Unicode Encoded String +}tUsbSubsequentStringDescriptor; + +#endif diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index d5cc5ba92..c8dca8b6d 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -874,6 +874,11 @@ + + + + + @@ -979,6 +984,9 @@ + + + @@ -1039,6 +1047,9 @@ + + + diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index f23a43116..12aa11b39 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -241,9 +241,6 @@ {1f84b105-783c-488a-923c-b9963ec66cc9} - - {f9d8c7a7-3b11-4c4f-b19a-b247dae7e8df} - {2a5b0873-804c-44a8-87f1-c1a223a094b9} @@ -256,6 +253,24 @@ {7d7e50db-5e14-4ecb-be6f-de57de5d7389} + + {f9d8c7a7-3b11-4c4f-b19a-b247dae7e8df} + + + {6e60b74b-286f-4cd0-a99e-75ae6bb76af8} + + + {66796a1a-dbfb-41d7-b5fa-0226f8a52cde} + + + {8c5a07af-8670-4a05-ad94-771c344e97e8} + + + {7fd0772a-f2d2-4eb4-832f-f32f0bc0cae9} + + + {451ca947-56ce-46cf-a4e8-036c75f8b86a} + @@ -591,6 +606,21 @@ micros\stm32l432\make + + micros\rpi_pico2_rp2350\Startup\Core\ARM + + + micros\rpi_pico2_rp2350\Startup\Core\ARM + + + micros\rpi_pico2_rp2350\make + + + micros\rpi_pico2_rp2350\make + + + micros\rpi_pico2_rp2350\make + @@ -863,10 +893,24 @@ micros\stm32l432\startup + + micros\rpi_pico2_rp2350\Startup + + + micros\rpi_pico2_rp2350\Startup\Core\ARM + + + micros\rpi_pico2_rp2350\Startup\Core\ARM + micros\bcm2835_raspi_b\startup\SD_CARD\PiZero + + + micros\rpi_pico2_rp2350\Startup\Core\ARM + + \ No newline at end of file diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/IntVect.c b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/IntVect.c new file mode 100644 index 000000000..8500b4d9a --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/IntVect.c @@ -0,0 +1,229 @@ +/****************************************************************************************** + Filename : IntVect.c + + Core : ARM Cortex-M33 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 29.08.2024 + + Description : Interrupt vector tables for RP2350 + +******************************************************************************************/ + +//============================================================================= +// Types definition +//============================================================================= +typedef void (*InterruptHandler)(void); + +void UndefinedHandler(void); +void UndefinedHandler(void) { for(;;); } + +//============================================================================= +// Functions prototype +//============================================================================= +void Startup_Init(void); +void main_Core1 (void) __attribute__((weak, alias("UndefinedHandler"))); +void __CORE0_STACK_TOP(void); +void __CORE1_STACK_TOP(void); + +/* Default interrupts handler */ +void NMI(void) __attribute__((weak, alias("UndefinedHandler"))); +void HardFault(void) __attribute__((weak, alias("UndefinedHandler"))); +void SVCall(void) __attribute__((weak, alias("UndefinedHandler"))); +void PendSV(void) __attribute__((weak, alias("UndefinedHandler"))); +void SysTickTimer(void) __attribute__((weak, alias("UndefinedHandler"))); +void TIMER0_IRQ_0_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void TIMER0_IRQ_1_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void TIMER0_IRQ_2_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void TIMER0_IRQ_3_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void TIMER1_IRQ_0_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void TIMER1_IRQ_1_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void TIMER1_IRQ_2_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void TIMER1_IRQ_3_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PWM_IRQ_WRAP_0_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PWM_IRQ_WRAP_1_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void DMA_IRQ_0_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void DMA_IRQ_1_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void DMA_IRQ_2_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void DMA_IRQ_3_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void USBCTRL_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PIO0_IRQ_0_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PIO0_IRQ_1_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PIO1_IRQ_0_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PIO1_IRQ_1_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PIO2_IRQ_0_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PIO2_IRQ_1_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void IO_IRQ_BANK0_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void IO_IRQ_BANK0_NS_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void IO_IRQ_QSPI_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void IO_IRQ_QSPI_NS_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void SIO_IRQ_FIFO_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void SIO_IRQ_BELL_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void SIO_IRQ_FIFO_NS_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void SIO_IRQ_BELL_NS_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void SIO_IRQ_MTIMECMP_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void CLOCKS_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void SPI0_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void SPI1_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void UART0_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void UART1_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void ADC_IRQ_FIFO_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void I2C0_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void I2C1_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void OTP_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void TRNG_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PLL_SYS_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void PLL_USB_IRQ_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void POWMAN_IRQ_POW_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); +void POWMAN_IRQ_TIMER_IRQn(void) __attribute__((weak, alias("UndefinedHandler"))); + +//============================================================================= +// Interrupt vector table Core0 +//============================================================================= +const InterruptHandler __attribute__((section(".intvect_c0"), aligned(128))) __INTVECT_Core0[] = +{ + (InterruptHandler)&__CORE0_STACK_TOP, + (InterruptHandler)&Startup_Init, + (InterruptHandler)&NMI, + (InterruptHandler)&HardFault, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)&SVCall, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)&PendSV, + (InterruptHandler)&SysTickTimer, + (InterruptHandler)&TIMER0_IRQ_0_IRQn, + (InterruptHandler)&TIMER0_IRQ_1_IRQn, + (InterruptHandler)&TIMER0_IRQ_2_IRQn, + (InterruptHandler)&TIMER0_IRQ_3_IRQn, + (InterruptHandler)&TIMER1_IRQ_0_IRQn, + (InterruptHandler)&TIMER1_IRQ_1_IRQn, + (InterruptHandler)&TIMER1_IRQ_2_IRQn, + (InterruptHandler)&TIMER1_IRQ_3_IRQn, + (InterruptHandler)&PWM_IRQ_WRAP_0_IRQn, + (InterruptHandler)&PWM_IRQ_WRAP_1_IRQn, + (InterruptHandler)&DMA_IRQ_0_IRQn, + (InterruptHandler)&DMA_IRQ_1_IRQn, + (InterruptHandler)&DMA_IRQ_2_IRQn, + (InterruptHandler)&DMA_IRQ_3_IRQn, + (InterruptHandler)&USBCTRL_IRQ_IRQn, + (InterruptHandler)&PIO0_IRQ_0_IRQn, + (InterruptHandler)&PIO0_IRQ_1_IRQn, + (InterruptHandler)&PIO1_IRQ_0_IRQn, + (InterruptHandler)&PIO1_IRQ_1_IRQn, + (InterruptHandler)&PIO2_IRQ_0_IRQn, + (InterruptHandler)&PIO2_IRQ_1_IRQn, + (InterruptHandler)&IO_IRQ_BANK0_IRQn, + (InterruptHandler)&IO_IRQ_BANK0_NS_IRQn, + (InterruptHandler)&IO_IRQ_QSPI_IRQn, + (InterruptHandler)&IO_IRQ_QSPI_NS_IRQn, + (InterruptHandler)&SIO_IRQ_FIFO_IRQn, + (InterruptHandler)&SIO_IRQ_BELL_IRQn, + (InterruptHandler)&SIO_IRQ_FIFO_NS_IRQn, + (InterruptHandler)&SIO_IRQ_BELL_NS_IRQn, + (InterruptHandler)&SIO_IRQ_MTIMECMP_IRQn, + (InterruptHandler)&CLOCKS_IRQ_IRQn, + (InterruptHandler)&SPI0_IRQ_IRQn, + (InterruptHandler)&SPI1_IRQ_IRQn, + (InterruptHandler)&UART0_IRQ_IRQn, + (InterruptHandler)&UART1_IRQ_IRQn, + (InterruptHandler)&ADC_IRQ_FIFO_IRQn, + (InterruptHandler)&I2C0_IRQ_IRQn, + (InterruptHandler)&I2C1_IRQ_IRQn, + (InterruptHandler)&OTP_IRQ_IRQn, + (InterruptHandler)&TRNG_IRQ_IRQn, + (InterruptHandler)&PLL_SYS_IRQ_IRQn, + (InterruptHandler)&PLL_USB_IRQ_IRQn, + (InterruptHandler)&POWMAN_IRQ_POW_IRQn, + (InterruptHandler)&POWMAN_IRQ_TIMER_IRQn, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0 + }; + +//============================================================================= +// Interrupt vector table Core1 +//============================================================================= +const InterruptHandler __attribute__((section(".intvect_c1"), aligned(128))) __INTVECT_Core1[] = +{ + (InterruptHandler)&__CORE1_STACK_TOP, + (InterruptHandler)&main_Core1, + (InterruptHandler)&NMI, + (InterruptHandler)&HardFault, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)&SVCall, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)&PendSV, + (InterruptHandler)&SysTickTimer, + (InterruptHandler)&TIMER0_IRQ_0_IRQn, + (InterruptHandler)&TIMER0_IRQ_1_IRQn, + (InterruptHandler)&TIMER0_IRQ_2_IRQn, + (InterruptHandler)&TIMER0_IRQ_3_IRQn, + (InterruptHandler)&TIMER1_IRQ_0_IRQn, + (InterruptHandler)&TIMER1_IRQ_1_IRQn, + (InterruptHandler)&TIMER1_IRQ_2_IRQn, + (InterruptHandler)&TIMER1_IRQ_3_IRQn, + (InterruptHandler)&PWM_IRQ_WRAP_0_IRQn, + (InterruptHandler)&PWM_IRQ_WRAP_1_IRQn, + (InterruptHandler)&DMA_IRQ_0_IRQn, + (InterruptHandler)&DMA_IRQ_1_IRQn, + (InterruptHandler)&DMA_IRQ_2_IRQn, + (InterruptHandler)&DMA_IRQ_3_IRQn, + (InterruptHandler)&USBCTRL_IRQ_IRQn, + (InterruptHandler)&PIO0_IRQ_0_IRQn, + (InterruptHandler)&PIO0_IRQ_1_IRQn, + (InterruptHandler)&PIO1_IRQ_0_IRQn, + (InterruptHandler)&PIO1_IRQ_1_IRQn, + (InterruptHandler)&PIO2_IRQ_0_IRQn, + (InterruptHandler)&PIO2_IRQ_1_IRQn, + (InterruptHandler)&IO_IRQ_BANK0_IRQn, + (InterruptHandler)&IO_IRQ_BANK0_NS_IRQn, + (InterruptHandler)&IO_IRQ_QSPI_IRQn, + (InterruptHandler)&IO_IRQ_QSPI_NS_IRQn, + (InterruptHandler)&SIO_IRQ_FIFO_IRQn, + (InterruptHandler)&SIO_IRQ_BELL_IRQn, + (InterruptHandler)&SIO_IRQ_FIFO_NS_IRQn, + (InterruptHandler)&SIO_IRQ_BELL_NS_IRQn, + (InterruptHandler)&SIO_IRQ_MTIMECMP_IRQn, + (InterruptHandler)&CLOCKS_IRQ_IRQn, + (InterruptHandler)&SPI0_IRQ_IRQn, + (InterruptHandler)&SPI1_IRQ_IRQn, + (InterruptHandler)&UART0_IRQ_IRQn, + (InterruptHandler)&UART1_IRQ_IRQn, + (InterruptHandler)&ADC_IRQ_FIFO_IRQn, + (InterruptHandler)&I2C0_IRQ_IRQn, + (InterruptHandler)&I2C1_IRQ_IRQn, + (InterruptHandler)&OTP_IRQ_IRQn, + (InterruptHandler)&TRNG_IRQ_IRQn, + (InterruptHandler)&PLL_SYS_IRQ_IRQn, + (InterruptHandler)&PLL_USB_IRQ_IRQn, + (InterruptHandler)&POWMAN_IRQ_POW_IRQn, + (InterruptHandler)&POWMAN_IRQ_TIMER_IRQn, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0, + (InterruptHandler)0 +}; diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/boot.s b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/boot.s new file mode 100644 index 000000000..e69de29bb diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h new file mode 100644 index 000000000..5873a0796 --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h @@ -0,0 +1,26 @@ +/****************************************************************************************** + Filename : core_arch.h + + Core : ARM Cortex-M33 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 29.08.2024 + + Description : ARM macros for Raspberry Pi Pico 2 + +******************************************************************************************/ + +#ifndef __CORE_ARCH_H__ +#define __CORE_ARCH_H__ + + + +#define CORE_ARCH_SEND_EVENT_INST() __asm("SEV") + + +#endif //__CORE_ARCH_H__ diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/image_definition_block.c b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/image_definition_block.c new file mode 100644 index 000000000..44f36c70f --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/image_definition_block.c @@ -0,0 +1,27 @@ +/****************************************************************************************** + Filename : image_definition_block.c + + Core : ARM Cortex-M33 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 29.08.2024 + + Description : Image definition block for Raspberry Pi Pico 2 + +******************************************************************************************/ + +#include "stdint.h" + +const uint32_t __attribute__((section(".image_start_block"), aligned(4))) image_definition_Block[] = +{ + 0xffffded3, + 0x10210142, + 0x000001ff, + 0x00000000, + 0xab123579 +}; diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/util.s b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/util.s new file mode 100644 index 000000000..2fba0b503 --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/util.s @@ -0,0 +1,34 @@ +// *************************************************************************************** +// Filename : util.s +// +// Author : Chalandi Amine +// +// Owner : Chalandi Amine +// +// Date : 04.09.2024 +// +// Description : low-level utility functions +// +// *************************************************************************************** + +.file "util.s" + +.syntax unified + +.cpu cortex-m33 + + +.thumb_func +.section ".text", "ax" +.align 8 +.globl BlockingDelay +.type BlockingDelay, % function + + +BlockingDelay: + subs r0, r0, #1 + bne BlockingDelay + bx lr + +.size BlockingDelay, .-BlockingDelay + diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Startup.c b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Startup.c new file mode 100644 index 000000000..437a6226f --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Startup.c @@ -0,0 +1,205 @@ +// *************************************************************************************** +// Filename : Startup.c +// +// Author : Chalandi Amine +// +// Owner : Chalandi Amine +// +// Date : 04.09.2024 +// +// Description : C/C++ Runtime Setup (Crt0) +// +// *************************************************************************************** + +//========================================================================================= +// types definitions +//========================================================================================= +typedef struct +{ + unsigned long sourceAddr; /* Source Address (section in ROM memory) */ + unsigned long targetAddr; /* Target Address (section in RAM memory) */ + unsigned long size; /* length of section (bytes) */ +} runtimeCopyTable_t; + +typedef struct +{ + unsigned long Addr; /* source Address (section in RAM memory) */ + unsigned long size; /* length of section (bytes) */ +} runtimeClearTable_t; + +//========================================================================================= +// linker variables +//========================================================================================= +extern const runtimeCopyTable_t __RUNTIME_COPY_TABLE[]; +extern const runtimeClearTable_t __RUNTIME_CLEAR_TABLE[]; +extern unsigned long __CPPCTOR_LIST__[]; + +//========================================================================================= +// defines +//========================================================================================= +#define __STARTUP_RUNTIME_COPYTABLE (runtimeCopyTable_t*)(&__RUNTIME_COPY_TABLE[0]) +#define __STARTUP_RUNTIME_CLEARTABLE (runtimeClearTable_t*)(&__RUNTIME_CLEAR_TABLE[0]) +#define __STARTUP_RUNTIME_CTORS (unsigned long*)(&__CPPCTOR_LIST__[0]) + +//========================================================================================= +// function prototype +//========================================================================================= +void Startup_Init(void) __attribute__((used)); +static void Startup_InitRam(void); +static void Startup_InitCtors(void); +static void Startup_RunApplication(void); +static void Startup_Unexpected_Exit(void); +static void Startup_InitSystemClock(void); +static void Startup_InitCore(void); +//========================================================================================= +// extern function prototype +//========================================================================================= +int main(void) __attribute__((weak)); +void RP2350_ClockInit(void) __attribute__((weak)); +void RP2350_InitCore(void) __attribute__((weak)); + +//========================================================================================= +// macros +//========================================================================================= +#define ENABLE_IRQ() __asm("CPSIE i") +#define DISABLE_IRQ() __asm("CPSID i") + +//----------------------------------------------------------------------------------------- +/// \brief Startup_Init function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +void Startup_Init(void) +{ + /* Initialize the CPU Core */ + Startup_InitCore(); + + /* Configure the system clock */ + Startup_InitSystemClock(); + + /* Initialize the RAM memory */ + Startup_InitRam(); + + /* Initialize the non-local C++ objects */ + Startup_InitCtors(); + + /* Start the application */ + Startup_RunApplication(); +} + + +//----------------------------------------------------------------------------------------- +/// \brief Startup_InitRam function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_InitRam(void) +{ + unsigned long ClearTableIdx = 0; + unsigned long CopyTableIdx = 0; + + /* Clear Table */ + + while((__STARTUP_RUNTIME_CLEARTABLE)[ClearTableIdx].Addr != (unsigned long)-1 && (__STARTUP_RUNTIME_CLEARTABLE)[ClearTableIdx].size != (unsigned long)-1) + { + for(unsigned int cpt = 0; cpt < (__STARTUP_RUNTIME_CLEARTABLE)[ClearTableIdx].size; cpt++) + { + *(volatile unsigned char*)((unsigned long)((__STARTUP_RUNTIME_CLEARTABLE)[ClearTableIdx].Addr) + cpt) = 0; + } + + ClearTableIdx++; + } + + /* Copy Table */ + + while((__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].sourceAddr != (unsigned long)-1 && + (__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].targetAddr != (unsigned long)-1 && + (__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].size != (unsigned long)-1 + ) + { + for(unsigned int cpt = 0; cpt < (__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].size; cpt++) + { + *(volatile unsigned char*)((unsigned long)((__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].targetAddr) + cpt) = + *(volatile unsigned char*)((unsigned long)((__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].sourceAddr) + cpt); + } + + CopyTableIdx++; + } +} + +//----------------------------------------------------------------------------------------- +/// \brief Startup_InitCtors function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_InitCtors(void) +{ + unsigned long CtorIdx = 0U; + + while((__STARTUP_RUNTIME_CTORS)[CtorIdx] != ((unsigned long)-1)) + { + ((void (*)(void))((__STARTUP_RUNTIME_CTORS)[CtorIdx++]))(); + } +} + +//----------------------------------------------------------------------------------------- +/// \brief Startup_RunApplication function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_RunApplication(void) +{ + /* Check the weak function */ + if((unsigned int) main != 0) + { + /* Call the main function */ + (void)main(); + } + + /* Catch unexpected exit from main or if main does not exist */ + Startup_Unexpected_Exit(); +} + +//----------------------------------------------------------------------------------------- +/// \brief Startup_Unexpected_Exit function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_Unexpected_Exit(void) +{ + for(;;); +} + +//----------------------------------------------------------------------------------------- +/// \brief Startup_InitSystemClock function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_InitSystemClock(void) +{ + RP2350_ClockInit(); +} + +//----------------------------------------------------------------------------------------- +/// \brief Startup_InitCore function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +void Startup_InitCore(void) +{ + RP2350_InitCore(); +} diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld new file mode 100644 index 000000000..7240ae485 --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld @@ -0,0 +1,144 @@ +/* + Copyright Christopher Kormanyos 2024. + Distributed under the Boost Software License, + Version 1.0. (See accompanying file LICENSE_1_0.txt + or copy at http://www.boost.org/LICENSE_1_0.txt) +*/ + +/* Linker script for STM32F1xx ARM(R) Cortex(TM)-M3 MCU */ + +INPUT(libc.a libm.a libgcc.a) + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +MEMORY +{ + SBL(rx) : ORIGIN = 0x10000000, LENGTH = 0x200 + VEC(rx) : ORIGIN = 0x10000200, LENGTH = 0x200 + ROM(rx) : ORIGIN = 0x10000400, LENGTH = 2M - 0x400 + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 264K - 4K - 4K +} + +SECTIONS +{ + /* Pico Secondary bootloader */ + .SBL : + { + . = ALIGN(4); + PROVIDE(__SBL_BASE_ADDRESS = .); + *(.SBL) + KEEP(*(.SBL)) + } > SBL + + /* Interrupt vector table */ + .intvect : + { + . = ALIGN(4); + PROVIDE(__INTVECT_BASE_ADDRESS = .); + *(.intvect_c0) + *(.intvect_c1) + KEEP(*(.intvect_c0)) + KEEP(*(.intvect_c1)) + } > VEC + + /* startup */ + .startup : + { + *(.startup) + . = ALIGN(0x10); + KEEP(*(.startup)) + } > ROM = 0x5555 + + /* Program code (text), read-only data and static ctors */ + .text : + { + _ctors_begin = .; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array*)) + _ctors_end = .; + *(.progmem*) + . = ALIGN(4); + *(.text) + . = ALIGN(4); + *(.text*) + . = ALIGN(4); + *(.rodata) + . = ALIGN(4); + *(.rodata*) + . = ALIGN(4); + *(.glue_7) + . = ALIGN(4); + *(.glue_7t) + . = ALIGN(4); + } > ROM + + .ARM.extab : + { + . = ALIGN(4); + *(.ARM.extab) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + . = ALIGN(4); + } > ROM + + .exidx : + { + . = ALIGN(4); + PROVIDE(__exidx_start = .); + *(.ARM.exidx*) + . = ALIGN(4); + PROVIDE(__exidx_end = .); + } > ROM + + .ARM.attributes : + { + *(.ARM.attributes) + } > ROM + + . = 0x20000000; + . = ALIGN(4); + + /* The ROM-to-RAM initialized data section */ + .data : + { + _data_begin = .; + *(.data) + . = ALIGN(4); + KEEP (*(.data)) + *(.data*) + . = ALIGN(4); + KEEP (*(.data*)) + _data_end = .; + } > RAM AT > ROM + + /* The uninitialized (zero-cleared) data section */ + .bss : + { + _bss_begin = .; + *(.bss) + . = ALIGN(4); + KEEP (*(.bss)) + *(.bss*) + . = ALIGN(4); + KEEP (*(.bss*)) + _bss_end = .; + } > RAM + + PROVIDE(end = .); + PROVIDE(_fini = .); + + _rom_data_begin = LOADADDR(.data); + + /* stack definitions */ + + . = 0x20041FF8; + . = ALIGN(8); + + PROVIDE(__CORE0_STACK_TOP = .) ; + + . = 0x20040FF8; + . = ALIGN(8); + + PROVIDE(__CORE1_STACK_TOP = .) ; +} diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk new file mode 100644 index 000000000..b7e6c25e5 --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk @@ -0,0 +1,18 @@ +# +# Copyright Christopher Kormanyos 2024. +# Distributed under the Boost Software License, +# Version 1.0. (See accompanying file LICENSE_1_0.txt +# or copy at http://www.boost.org/LICENSE_1_0.txt) +# + +# ------------------------------------------------------------------------------ +# File list of the stm32f1xx files in the project +# ------------------------------------------------------------------------------ + +FILES_TGT = $(PATH_APP)/mcal/$(TGT)/mcal_cpu_rp2040 \ + $(PATH_APP)/mcal/mcal_gcc_cxx_completion \ + $(PATH_TGT)/startup/crt0 \ + $(PATH_TGT)/startup/crt0_init_ram \ + $(PATH_TGT)/startup/crt1 \ + $(PATH_TGT)/startup/int_vect \ + $(PATH_TGT)/startup/secondary_boot diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk new file mode 100644 index 000000000..46b755fe2 --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk @@ -0,0 +1,53 @@ +# Copyright Christopher Kormanyos 2024. +# Distributed under the Boost Software License, +# Version 1.0. (See accompanying file LICENSE_1_0.txt +# or copy at http://www.boost.org/LICENSE_1_0.txt) +# + +# ------------------------------------------------------------------------------ +# compiler flags for the target architecture +# ------------------------------------------------------------------------------ + +GCC_VERSION = 13.2.1 +GCC_TARGET = arm-none-eabi +GCC_PREFIX = arm-none-eabi + +TGT_SUFFIX = elf + +TGT_ALLFLAGS = -O2 \ + -mlittle-endian \ + -mlong-calls \ + -mcpu=cortex-m0plus \ + -mthumb \ + -mabi=aapcs \ + -finline-functions \ + -finline-limit=64 \ + -ffast-math + +TGT_CFLAGS = -std=c11 \ + -Wunsuffixed-float-constants \ + $(TGT_ALLFLAGS) + +TGT_CXXFLAGS = -std=c++14 \ + -Wno-psabi \ + $(TGT_ALLFLAGS) + +TGT_INCLUDES = -isystem $(PATH_APP)/util/STL + +TGT_AFLAGS = + +TGT_LDFLAGS = -nostdlib \ + -nostartfiles \ + -Wl,--gc-sections \ + -Wl,-Map,$(APP).map \ + -T $(LINKER_DEFINITION_FILE) + +ifeq ($(TYP_OS),WIN) +IMG_SUFFIX := uf2 +IMAGE_FILE := $(APP).$(IMG_SUFFIX) +ELF2UF2 := $(PATH_TOOLS)/rpi_pico/elf2uf2.exe +ELF2UF2 := $(subst /,\,$(PATH_TOOLS)/rpi_pico/elf2uf2.exe) +RULE_SPECIAL_MAKE_IMAGE_FILE := $(ELF2UF2) $(subst /,\,$(APP).$(TGT_SUFFIX)) $(subst /,\,$(IMAGE_FILE)) +else +RULE_SPECIAL_MAKE_IMAGE_FILE := +endif diff --git a/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040.ld b/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040.ld index aad2ec16b..7240ae485 100644 --- a/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040.ld +++ b/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040.ld @@ -1,5 +1,5 @@ /* - Copyright Christopher Kormanyos 2007 - 2024. + Copyright Christopher Kormanyos 2024. Distributed under the Boost Software License, Version 1.0. (See accompanying file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt) @@ -25,7 +25,7 @@ SECTIONS /* Pico Secondary bootloader */ .SBL : { - . = ALIGN(4); + . = ALIGN(4); PROVIDE(__SBL_BASE_ADDRESS = .); *(.SBL) KEEP(*(.SBL)) @@ -135,10 +135,10 @@ SECTIONS . = 0x20041FF8; . = ALIGN(8); - PROVIDE(__CORE0_STACK_TOP = .) ; + PROVIDE(__CORE0_STACK_TOP = .) ; . = 0x20040FF8; . = ALIGN(8); - PROVIDE(__CORE1_STACK_TOP = .) ; + PROVIDE(__CORE1_STACK_TOP = .) ; } diff --git a/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040_files.gmk b/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040_files.gmk index fb811ae26..b7e6c25e5 100644 --- a/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040_files.gmk +++ b/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040_files.gmk @@ -1,5 +1,5 @@ # -# Copyright Christopher Kormanyos 2007 - 2024. +# Copyright Christopher Kormanyos 2024. # Distributed under the Boost Software License, # Version 1.0. (See accompanying file LICENSE_1_0.txt # or copy at http://www.boost.org/LICENSE_1_0.txt) diff --git a/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040_flags.gmk b/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040_flags.gmk index b7d995b70..46b755fe2 100644 --- a/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040_flags.gmk +++ b/ref_app/target/micros/rpi_pico_rp2040/make/rpi_pico_rp2040_flags.gmk @@ -1,4 +1,4 @@ -# Copyright Christopher Kormanyos 2007 - 2024. +# Copyright Christopher Kormanyos 2024. # Distributed under the Boost Software License, # Version 1.0. (See accompanying file LICENSE_1_0.txt # or copy at http://www.boost.org/LICENSE_1_0.txt) @@ -47,7 +47,7 @@ IMG_SUFFIX := uf2 IMAGE_FILE := $(APP).$(IMG_SUFFIX) ELF2UF2 := $(PATH_TOOLS)/rpi_pico/elf2uf2.exe ELF2UF2 := $(subst /,\,$(PATH_TOOLS)/rpi_pico/elf2uf2.exe) -RULE_SPECIAL_MAKE_IMAGE_FILE := $(ELF2UF2) -v $(subst /,\,$(APP).$(TGT_SUFFIX)) $(subst /,\,$(IMAGE_FILE)) +RULE_SPECIAL_MAKE_IMAGE_FILE := $(ELF2UF2) $(subst /,\,$(APP).$(TGT_SUFFIX)) $(subst /,\,$(IMAGE_FILE)) else RULE_SPECIAL_MAKE_IMAGE_FILE := endif diff --git a/ref_app/target/micros/rpi_pico_rp2040/startup/secondary_boot.cpp b/ref_app/target/micros/rpi_pico_rp2040/startup/secondary_boot.cpp index 9ddbcd2bf..ba615d259 100644 --- a/ref_app/target/micros/rpi_pico_rp2040/startup/secondary_boot.cpp +++ b/ref_app/target/micros/rpi_pico_rp2040/startup/secondary_boot.cpp @@ -28,10 +28,10 @@ #include extern "C" -const volatile std::uint8_t __SBL[static_cast(UINT16_C(512))] __attribute__((section(".SBL"))); +const volatile std::uint8_t __SBL[static_cast(UINT16_C(0x200))] __attribute__((section(".SBL"), aligned(0x100))); extern "C" -const volatile std::uint8_t __SBL[static_cast(UINT16_C(512))] = +const volatile std::uint8_t __SBL[static_cast(UINT16_C(0x200))] = { 0x00, 0xB5, 0x2F, 0x4B, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60, 0xD8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2B, 0x4B, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61, From e173d7d2dbeb38a61993f31094be0f87851dd914 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Tue, 10 Sep 2024 20:46:00 +0200 Subject: [PATCH 2/7] Builds chalandi rp2350 but not yet run --- ref_app/ref_app.sln | 4 + .../src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c | 4 +- ref_app/target.vcxproj | 77 +++++-- ref_app/target.vcxproj.filters | 12 + .../micros/rpi_pico2_rp2350/Appli/main.c | 182 +++++++++++++++ .../rpi_pico2_rp2350/Std/Platform_Types.h | 42 ++++ .../rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld | 212 +++++++++--------- .../make/rpi_pico2_rp2350_files.gmk | 18 +- .../make/rpi_pico2_rp2350_flags.gmk | 21 +- 9 files changed, 426 insertions(+), 146 deletions(-) create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Std/Platform_Types.h diff --git a/ref_app/ref_app.sln b/ref_app/ref_app.sln index ff2143804..8d31cfca6 100644 --- a/ref_app/ref_app.sln +++ b/ref_app/ref_app.sln @@ -56,6 +56,7 @@ Global target riscvfe310|x64 = target riscvfe310|x64 target rl78|x64 = target rl78|x64 target rpi_pico_rp2040|x64 = target rpi_pico_rp2040|x64 + target rpi_pico2_rp2350|x64 = target rpi_pico2_rp2350|x64 target rx63n|x64 = target rx63n|x64 target stm32f100|x64 = target stm32f100|x64 target stm32f407|x64 = target stm32f407|x64 @@ -86,6 +87,7 @@ Global {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target riscvfe310|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target rl78|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target rpi_pico_rp2040|x64.ActiveCfg = Release|x64 + {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target rpi_pico2_rp2350|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target rx63n|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target stm32f100|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target stm32f407|x64.ActiveCfg = Release|x64 @@ -122,6 +124,8 @@ Global {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target rl78|x64.Build.0 = target rl78|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target rpi_pico_rp2040|x64.ActiveCfg = target rpi_pico_rp2040|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target rpi_pico_rp2040|x64.Build.0 = target rpi_pico_rp2040|x64 + {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target rpi_pico2_rp2350|x64.ActiveCfg = target rpi_pico2_rp2350|x64 + {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target rpi_pico2_rp2350|x64.Build.0 = target rpi_pico2_rp2350|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target rx63n|x64.ActiveCfg = target rx63n|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target rx63n|x64.Build.0 = target rx63n|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target stm32f100|x64.ActiveCfg = target stm32f100|x64 diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c index 9f6d3d785..4b1c0eef7 100644 --- a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c @@ -18,8 +18,8 @@ //============================================================================= // Includes //============================================================================= -#include "Cpu.h" -#include "core_arch.h" +#include +#include //============================================================================= // Globals diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index c8dca8b6d..96ebf2c5d 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -1,6 +1,10 @@  + + target rpi_pico2_rp2350 + x64 + target stm32l432 x64 @@ -140,109 +144,115 @@ Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 Makefile Unicode true - v142 + v143 + + + Makefile + Unicode + true + v143 Makefile @@ -254,27 +264,27 @@ Makefile - v142 + v143 Makefile - v142 + v143 Makefile - v142 + v143 Makefile - v142 + v143 Makefile - v142 + v143 Makefile - v142 + v143 Makefile @@ -359,6 +369,9 @@ + + + <_ProjectFileVersion>10.0.30319.1 @@ -386,6 +399,7 @@ target\build\build.bat am335x target\build\build.bat bcm2835_raspi_b target\build\build.bat rpi_pico_rp2040 + target\build\build.bat rpi_pico2_rp2350 Build\Build.bat AVR rebuild Build\Build.bat AVR rebuild Build\Build.bat AVR rebuild @@ -411,6 +425,7 @@ target\build\build.bat am335x rebuild target\build\build.bat bcm2835_raspi_b rebuild target\build\build.bat rpi_pico_rp2040 rebuild + target\build\build.bat rpi_pico2_rp2350 rebuild Target\Build\Build.bat avr clean_all Target\Build\Build.bat atmega4809 clean_all Target\Build\Build.bat atmega2560 clean_all @@ -436,6 +451,7 @@ target\build\build.bat am335x clean_all target\build\build.bat bcm2835_raspi_b clean_all target\build\build.bat rpi_pico_rp2040 clean_all + target\build\build.bat rpi_pico2_rp2350 clean_all $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex @@ -460,6 +476,7 @@ $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex + $(SolutionDir)bin\ref_app.hex $(NMakePreprocessorDefinitions) $(NMakePreprocessorDefinitions) $(NMakePreprocessorDefinitions) @@ -484,6 +501,7 @@ + $(ProjectDir)/Cpp; $(ProjectDir)/Cpp/Hal/AVR;$(NMakeIncludeSearchPath) $(ProjectDir)/Cpp; $(ProjectDir)/Cpp/Hal/AVR;$(NMakeIncludeSearchPath) $(ProjectDir)/Cpp; $(ProjectDir)/Cpp/Hal/AVR;$(NMakeIncludeSearchPath) @@ -508,6 +526,7 @@ $(SolutionDir)/src;$(SolutionDir)/src/mcal/am335x $(SolutionDir)/src;$(SolutionDir)/src/mcal/bcm2835_raspi_b $(SolutionDir)/src;$(SolutionDir)/src/mcal/rpi_pico_rp2040;$(IncludePath) + $(SolutionDir)/src;$(SolutionDir)/src/mcal/rpi_pico_rp2040;$(IncludePath) $(NMakeForcedIncludes) $(NMakeForcedIncludes) $(NMakeForcedIncludes) @@ -532,6 +551,7 @@ + $(NMakeAssemblySearchPath) $(NMakeAssemblySearchPath) $(NMakeAssemblySearchPath) @@ -556,6 +576,7 @@ + $(NMakeForcedUsingAssemblies) $(NMakeForcedUsingAssemblies) $(NMakeForcedUsingAssemblies) @@ -580,6 +601,7 @@ + Build\Build.bat R8C Build\Build.bat R8C Build\Build.bat R8C rebuild @@ -821,6 +843,11 @@ $(SolutionDir)tmp\log\ref_app.log + + + $(SolutionDir)tmp\log\ref_app.log + + $(SolutionDir)..\Bin\App.log @@ -984,6 +1011,7 @@ + @@ -1049,6 +1077,7 @@ + diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index 12aa11b39..3e60a3b3f 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -271,6 +271,12 @@ {451ca947-56ce-46cf-a4e8-036c75f8b86a} + + {8f7c20e8-9cec-4cf8-b3b5-48ce200d6733} + + + {6be8f2e8-8491-442a-9308-13667c843931} + @@ -902,6 +908,9 @@ micros\rpi_pico2_rp2350\Startup\Core\ARM + + micros\rpi_pico2_rp2350\Appli + @@ -912,5 +921,8 @@ micros\rpi_pico2_rp2350\Startup\Core\ARM + + micros\rpi_pico2_rp2350\Std + \ No newline at end of file diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c b/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c new file mode 100644 index 000000000..709832d3b --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c @@ -0,0 +1,182 @@ +/****************************************************************************************** + Filename : main.c + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : Application main function + +******************************************************************************************/ + +//============================================================================= +// Includes +//============================================================================= +#include "Platform_Types.h" +#include "Cpu.h" +#include "Gpio.h" +#include "SysTickTimer.h" + +//============================================================================= +// Macros +//============================================================================= + +//============================================================================= +// Prototypes +//============================================================================= +void main_Core0(void); +void main_Core1(void); +void BlockingDelay(uint32 delay); + +//============================================================================= +// Globals +//============================================================================= +#ifdef DEBUG + volatile boolean boHaltCore0 = TRUE; + volatile boolean boHaltCore1 = TRUE; +#endif + +//----------------------------------------------------------------------------------------- +/// \brief main function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +int main(void) +{ + /* Run the main function of the core 0, it will start the core 1 */ + main_Core0(); + + /* Synchronize with core 1 */ + RP2350_MulticoreSync((uint32_t)HW_PER_SIO->CPUID.reg); + + /* endless loop on the core 0 */ + for(;;); + + /* never reached */ + return(0); +} + +//----------------------------------------------------------------------------------------- +/// \brief main_Core0 function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +void main_Core0(void) +{ +#ifdef DEBUG + while(boHaltCore0); +#endif + +#ifdef CORE_FAMILY_ARM + /* Disable interrupts on core 0 */ + __asm volatile("CPSID i"); +#endif + + /* Output disable on pin 25 */ + LED_GREEN_CFG(); + + + /* Start the Core 1 and turn on the led to be sure that we passed successfully the core 1 initiaization */ + if(TRUE == RP2350_StartCore1()) + { + LED_GREEN_ON(); + } + else + { + /* Loop forever in case of error */ + while(1) + { + __asm volatile("NOP"); + } + } + +} + +//----------------------------------------------------------------------------------------- +/// \brief main_Core1 function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- + volatile uint64_t* pMTIMECMP = (volatile uint64_t*)&(HW_PER_SIO->MTIMECMP.reg); + volatile uint64_t* pMTIME = (volatile uint64_t*)&(HW_PER_SIO->MTIME.reg); + +void main_Core1(void) +{ +#ifdef DEBUG + while(boHaltCore1); +#endif + + /* Note: Core 1 is started with interrupt enabled by the BootRom */ + + /* Clear the stiky bits of the FIFO_ST on core 1 */ + HW_PER_SIO->FIFO_ST.reg = 0xFFu; + +#ifdef CORE_FAMILY_ARM + __asm volatile("DSB"); + + /* Clear all pending interrupts on core 1 */ + NVIC->ICPR[0] = (uint32)-1; + +#endif + + /* Synchronize with core 0 */ + RP2350_MulticoreSync((uint32_t)HW_PER_SIO->CPUID.reg); + + +#ifdef CORE_FAMILY_RISC_V + + /* configure the machine timer for 1Hz interrupt window */ + #include "riscv.h" + + /* enable machine timer interrupt */ + riscv_set_csr(RVCSR_MIE_OFFSET, 0x80ul); + + /* enable global interrupt */ + riscv_set_csr(RVCSR_MSTATUS_OFFSET, 0x08ul); + + /* configure machine timer to use 150 MHz */ + HW_PER_SIO->MTIME_CTRL.bit.FULLSPEED = 1; + + /* set next timeout (machine timer is enabled by default) */ + *pMTIMECMP = *pMTIME + 150000000ul; //1s + +#endif + + while(1) + { +#ifdef CORE_FAMILY_ARM + #define DELAY 15000000 + LED_GREEN_TOGGLE(); +#else + #define DELAY 10000000 +#endif + + BlockingDelay(DELAY); + } +} + + +#ifdef CORE_FAMILY_RISC_V +__attribute__((interrupt)) void Isr_MachineTimerInterrupt(void); + +void Isr_MachineTimerInterrupt(void) +{ + *pMTIMECMP = *pMTIME + 150000000ul; + + LED_GREEN_TOGGLE(); +} + +#endif + diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Std/Platform_Types.h b/ref_app/target/micros/rpi_pico2_rp2350/Std/Platform_Types.h new file mode 100644 index 000000000..c5524b9cc --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/Std/Platform_Types.h @@ -0,0 +1,42 @@ +/****************************************************************************************** + Filename : Platform_Types.h + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : Platform types header file + +******************************************************************************************/ + +#ifndef __PLATFORM_TYPES_H__ +#define __PLATFORM_TYPES_H__ + +typedef unsigned char uint8; +typedef signed char sint8; +typedef unsigned short uint16; +typedef signed short sint16; +typedef unsigned long uint32; +typedef signed long sint32; +typedef unsigned long long uint64; +typedef signed long long sint64; + +typedef void (*pFunc)(void); + +typedef enum +{ + FALSE = 0, + TRUE +}boolean; + +#define NULL (void*)0 + +#define NULL_PTR (void*)0 + +#endif diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld index 7240ae485..fb346f89f 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld @@ -1,144 +1,140 @@ -/* - Copyright Christopher Kormanyos 2024. - Distributed under the Boost Software License, - Version 1.0. (See accompanying file LICENSE_1_0.txt - or copy at http://www.boost.org/LICENSE_1_0.txt) -*/ - -/* Linker script for STM32F1xx ARM(R) Cortex(TM)-M3 MCU */ - -INPUT(libc.a libm.a libgcc.a) - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) +/****************************************************************************************** + Filename : Memory_Map.ld + + Core : ARM Cortex-M33 / RISC-V Hazard3 + + MCU : RP2350 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 04.09.2024 + + Description : Linker description file for Raspberry Pi Pico 2 + +******************************************************************************************/ + +/****************************************************************************************** + ELF Entrypoint +******************************************************************************************/ +ENTRY(Startup_Init) + +/****************************************************************************************** + Globals +******************************************************************************************/ +__STACK_SIZE_CORE0 = 2K; +__STACK_SIZE_CORE1 = 2K; + +/****************************************************************************************** + Memory configuration +******************************************************************************************/ MEMORY { - SBL(rx) : ORIGIN = 0x10000000, LENGTH = 0x200 - VEC(rx) : ORIGIN = 0x10000200, LENGTH = 0x200 - ROM(rx) : ORIGIN = 0x10000400, LENGTH = 2M - 0x400 - RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 264K - 4K - 4K + FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 32M + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512K } +/****************************************************************************************** + Sections definition +******************************************************************************************/ SECTIONS { - /* Pico Secondary bootloader */ - .SBL : + /* Program code */ + .program : ALIGN(4) { - . = ALIGN(4); - PROVIDE(__SBL_BASE_ADDRESS = .); - *(.SBL) - KEEP(*(.SBL)) - } > SBL - - /* Interrupt vector table */ - .intvect : - { - . = ALIGN(4); + PROVIDE(__CODE_BASE_ADDRESS = .); PROVIDE(__INTVECT_BASE_ADDRESS = .); + *(.riscv_intvect) + KEEP(*(.riscv_intvect)) *(.intvect_c0) *(.intvect_c1) KEEP(*(.intvect_c0)) KEEP(*(.intvect_c1)) - } > VEC - - /* startup */ - .startup : - { - *(.startup) - . = ALIGN(0x10); - KEEP(*(.startup)) - } > ROM = 0x5555 + PROVIDE(__IMAGE_DEF_BLOCK_START_ADDRESS = .); + KEEP(*(.image_start_block)) + *(.text) + *(.text.*) + } > FLASH - /* Program code (text), read-only data and static ctors */ - .text : + /* Read-only data (.rodata) */ + .rodata : ALIGN(4) { - _ctors_begin = .; - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array*)) - _ctors_end = .; - *(.progmem*) - . = ALIGN(4); - *(.text) - . = ALIGN(4); - *(.text*) - . = ALIGN(4); + PROVIDE(__RODATA_BASE_ADDRESS = .); *(.rodata) - . = ALIGN(4); - *(.rodata*) - . = ALIGN(4); - *(.glue_7) - . = ALIGN(4); - *(.glue_7t) - . = ALIGN(4); - } > ROM + } > FLASH - .ARM.extab : + /* Section for constructors */ + .ctors : ALIGN(4) { + PROVIDE(__CPPCTOR_LIST__ = .); + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + LONG(-1) ; + PROVIDE(__CPPCTOR_END__ = .); . = ALIGN(4); - *(.ARM.extab) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - . = ALIGN(4); - } > ROM + } > FLASH + - .exidx : + /* Section for destructors */ + .dtors : ALIGN(4) { + PROVIDE(__CPPDTOR_LIST__ = .); + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + LONG(-1) ; + PROVIDE(__CPPDTOR_END__ = .); + . = ALIGN(4); + } > FLASH + + /* Runtime clear table */ + .clear_sec : ALIGN(4) + { + PROVIDE(__RUNTIME_CLEAR_TABLE = .) ; + LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); + LONG(-1); LONG(-1); . = ALIGN(4); - PROVIDE(__exidx_start = .); - *(.ARM.exidx*) - . = ALIGN(4); - PROVIDE(__exidx_end = .); - } > ROM + } > FLASH - .ARM.attributes : + /* Runtime copy table */ + .copy_sec : ALIGN(4) { - *(.ARM.attributes) - } > ROM - - . = 0x20000000; - . = ALIGN(4); + PROVIDE(__RUNTIME_COPY_TABLE = .) ; + LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); + LONG(-1); LONG(-1); LONG(-1); + . = ALIGN(4); + } > FLASH /* The ROM-to-RAM initialized data section */ - .data : + .data : ALIGN(4) { - _data_begin = .; + PROVIDE(__DATA_BASE_ADDRESS = .); *(.data) - . = ALIGN(4); - KEEP (*(.data)) - *(.data*) - . = ALIGN(4); - KEEP (*(.data*)) - _data_end = .; - } > RAM AT > ROM + } > RAM AT>FLASH - /* The uninitialized (zero-cleared) data section */ - .bss : + /* The uninitialized (zero-cleared) bss section */ + .bss : ALIGN(4) { - _bss_begin = .; + PROVIDE(__BSS_BASE_ADDRESS = .); *(.bss) - . = ALIGN(4); - KEEP (*(.bss)) - *(.bss*) - . = ALIGN(4); - KEEP (*(.bss*)) - _bss_end = .; } > RAM - PROVIDE(end = .); - PROVIDE(_fini = .); - - _rom_data_begin = LOADADDR(.data); - - /* stack definitions */ - - . = 0x20041FF8; - . = ALIGN(8); - - PROVIDE(__CORE0_STACK_TOP = .) ; + /* stack definition */ + .stack_core0 : + { + . = ALIGN(MAX(__STACK_SIZE_CORE0 , .), 8); + PROVIDE(__CORE0_STACK_TOP = .) ; + } > RAM - . = 0x20040FF8; - . = ALIGN(8); + .stack_core1 : + { + . = ALIGN(MAX(__STACK_SIZE_CORE1 , .), 8); + PROVIDE(__CORE1_STACK_TOP = .) ; + } > RAM - PROVIDE(__CORE1_STACK_TOP = .) ; } diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk index b7e6c25e5..fe8e06bf6 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk @@ -9,10 +9,14 @@ # File list of the stm32f1xx files in the project # ------------------------------------------------------------------------------ -FILES_TGT = $(PATH_APP)/mcal/$(TGT)/mcal_cpu_rp2040 \ - $(PATH_APP)/mcal/mcal_gcc_cxx_completion \ - $(PATH_TGT)/startup/crt0 \ - $(PATH_TGT)/startup/crt0_init_ram \ - $(PATH_TGT)/startup/crt1 \ - $(PATH_TGT)/startup/int_vect \ - $(PATH_TGT)/startup/secondary_boot +FILES_CPP := + +FILES_TGT = $(PATH_APP)/mcal/$(TGT)/Mcal/Clock/Clock \ + $(PATH_APP)/mcal/$(TGT)/Mcal/Cpu/Cpu \ + $(PATH_APP)/mcal/$(TGT)/Mcal/SysTickTimer/SysTickTimer \ + $(PATH_TGT)/Appli/main \ + $(PATH_TGT)/Startup/Core/ARM/boot \ + $(PATH_TGT)/Startup/Core/ARM/image_definition_block \ + $(PATH_TGT)/Startup/Core/ARM/IntVect \ + $(PATH_TGT)/Startup/Core/ARM/util \ + $(PATH_TGT)/Startup/Startup diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk index 46b755fe2..814ecd01f 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk @@ -17,22 +17,33 @@ TGT_SUFFIX = elf TGT_ALLFLAGS = -O2 \ -mlittle-endian \ -mlong-calls \ - -mcpu=cortex-m0plus \ + -mcpu=cortex-m33 \ + -march=armv8-m.main+fp+dsp \ + -mfloat-abi=softfp \ -mthumb \ -mabi=aapcs \ -finline-functions \ - -finline-limit=64 \ - -ffast-math + -finline-limit=64 TGT_CFLAGS = -std=c11 \ -Wunsuffixed-float-constants \ - $(TGT_ALLFLAGS) + $(TGT_ALLFLAGS) \ + -DCORE_FAMILY_ARM TGT_CXXFLAGS = -std=c++14 \ -Wno-psabi \ $(TGT_ALLFLAGS) -TGT_INCLUDES = -isystem $(PATH_APP)/util/STL +TGT_INCLUDES = -I$(PATH_TGT)/Startup/Core/ARM \ + -I$(PATH_APP)/mcal/$(TGT)/Mcal/Clock \ + -I$(PATH_APP)/mcal/$(TGT)/Mcal/Cmsis \ + -I$(PATH_APP)/mcal/$(TGT)/Mcal/Cmsis/m-profile \ + -I$(PATH_APP)/mcal/$(TGT)/Mcal/Cpu \ + -I$(PATH_APP)/mcal/$(TGT)/Mcal/Gpio \ + -I$(PATH_APP)/mcal/$(TGT)/Mcal/SysTickTimer \ + -I$(PATH_APP)/mcal/$(TGT)/Mcal \ + -I$(PATH_TGT)/Std \ + -isystem $(PATH_APP)/util/STL TGT_AFLAGS = From 8dadb909b5f73888b02539c6556215fe6579d96c Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Tue, 10 Sep 2024 21:11:49 +0200 Subject: [PATCH 3/7] Blinky 1/2Hz build run OK but problem at O2 --- .../micros/rpi_pico2_rp2350/Appli/main.c | 23 ++++++++++++------- .../make/rpi_pico2_rp2350_flags.gmk | 8 +++---- 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c b/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c index 709832d3b..126a5c1a6 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c +++ b/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c @@ -109,8 +109,18 @@ void main_Core0(void) /// /// \return void //----------------------------------------------------------------------------------------- - volatile uint64_t* pMTIMECMP = (volatile uint64_t*)&(HW_PER_SIO->MTIMECMP.reg); - volatile uint64_t* pMTIME = (volatile uint64_t*)&(HW_PER_SIO->MTIME.reg); + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wcast-align" +#endif + +volatile uint64_t* pMTIMECMP = (volatile uint64_t*)&(HW_PER_SIO->MTIMECMP.reg); +volatile uint64_t* pMTIME = (volatile uint64_t*)&(HW_PER_SIO->MTIME.reg); + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif void main_Core1(void) { @@ -156,14 +166,11 @@ void main_Core1(void) while(1) { -#ifdef CORE_FAMILY_ARM - #define DELAY 15000000 LED_GREEN_TOGGLE(); -#else - #define DELAY 10000000 -#endif - BlockingDelay(DELAY); + BlockingDelay(10000000); + BlockingDelay(10000000); + BlockingDelay(10000000); } } diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk index 814ecd01f..e7adb1e64 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk @@ -14,7 +14,7 @@ GCC_PREFIX = arm-none-eabi TGT_SUFFIX = elf -TGT_ALLFLAGS = -O2 \ +TGT_ALLFLAGS = -O0 \ -mlittle-endian \ -mlong-calls \ -mcpu=cortex-m33 \ @@ -56,9 +56,9 @@ TGT_LDFLAGS = -nostdlib \ ifeq ($(TYP_OS),WIN) IMG_SUFFIX := uf2 IMAGE_FILE := $(APP).$(IMG_SUFFIX) -ELF2UF2 := $(PATH_TOOLS)/rpi_pico/elf2uf2.exe -ELF2UF2 := $(subst /,\,$(PATH_TOOLS)/rpi_pico/elf2uf2.exe) -RULE_SPECIAL_MAKE_IMAGE_FILE := $(ELF2UF2) $(subst /,\,$(APP).$(TGT_SUFFIX)) $(subst /,\,$(IMAGE_FILE)) +ELF2UF2 := $(PATH_TOOLS)/rpi_pico2/picotool/picotool.exe +ELF2UF2 := $(subst /,\,$(PATH_TOOLS)/rpi_pico2/picotool/picotool.exe) +RULE_SPECIAL_MAKE_IMAGE_FILE := $(ELF2UF2) uf2 convert --quiet $(subst /,\,$(APP).$(TGT_SUFFIX)) $(subst /,\,$(IMAGE_FILE)) --family rp2350-arm-s --abs-block else RULE_SPECIAL_MAKE_IMAGE_FILE := endif From 4274d34c898860b5e7184758bb05a5636a5e4945 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Thu, 12 Sep 2024 07:12:45 +0200 Subject: [PATCH 4/7] Get rp2350 booting with lots still TODO --- .../src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c | 23 +++++++- .../Mcal/SysTickTimer/SysTickTimer.c | 14 +++++ .../Mcal/SysTickTimer/SysTickTimer.h | 4 +- ref_app/target.vcxproj | 1 + ref_app/target.vcxproj.filters | 3 + ref_app/target/app/make/app_make.gmk | 6 +- ref_app/target/app/make/app_rules.gmk | 8 --- .../micros/rpi_pico2_rp2350/Appli/main.c | 47 +++++++++++---- .../Startup/Core/ARM/IntVect.c | 6 +- .../Startup/Core/ARM/core_1_run.cpp | 30 ++++++++++ .../Startup/Core/ARM/core_arch.h | 5 ++ .../Startup/Core/ARM/image_definition_block.c | 14 ++--- .../rpi_pico2_rp2350/Startup/Core/ARM/util.s | 57 +++++++++++++++++++ .../micros/rpi_pico2_rp2350/Startup/Startup.c | 2 +- .../make/rpi_pico2_rp2350_files.gmk | 1 + .../make/rpi_pico2_rp2350_flags.gmk | 39 +++++++------ 16 files changed, 204 insertions(+), 56 deletions(-) create mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_1_run.cpp diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c index 4b1c0eef7..a27799db8 100644 --- a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/Cpu/Cpu.c @@ -18,12 +18,15 @@ //============================================================================= // Includes //============================================================================= -#include -#include +#include "Cpu.h" +#include "core_arch.h" + +#include //============================================================================= // Globals //============================================================================= +static uint32 u32MulticoreLock = 0; static volatile uint32 u32MulticoreSync = 0; @@ -36,8 +39,14 @@ static volatile uint32 u32MulticoreSync = 0; //----------------------------------------------------------------------------------------- void RP2350_MulticoreSync(uint32 CpuId) { + /* aquire the multicore lock */ + arch_spin_lock(&u32MulticoreLock); + u32MulticoreSync |= (1UL << CpuId); + /* release the multicore lock */ + arch_spin_unlock(&u32MulticoreLock); + while(u32MulticoreSync != MULTICORE_SYNC_MASK); } @@ -72,8 +81,15 @@ void RP2350_InitCore(void) while((HW_PER_RESETS->RESET_DONE.bit.IO_BANK0 == 0U) || (HW_PER_RESETS->RESET_DONE.bit.PADS_BANK0 == 0U)); +#ifdef CORE_FAMILY_ARM + /*Setting EXTEXCLALL allows external exclusive operations to be used in a configuration with no MPU. + This is because the default memory map does not include any shareable Normal memory.*/ + SCnSCB->ACTLR |= (1ul<<29); +#endif } +extern bool core_1_run_flag_get(void); + //----------------------------------------------------------------------------------------- /// \brief RP2350_StartCore1 function /// @@ -150,6 +166,7 @@ boolean RP2350_StartCore1(void) /* Clear the stiky bits of the FIFO_ST on core 0 */ HW_PER_SIO->FIFO_ST.reg = 0xFFu; + while(!core_1_run_flag_get()) { ; } + return(TRUE); } - diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.c b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.c index cb2e72467..72848f0f0 100644 --- a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.c +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.c @@ -53,6 +53,20 @@ void SysTickTimer_Start(uint32 timeout) pSTK_CTRL->bits.u1ENABLE = SYS_TICK_ENABLE_TIMER; } +//----------------------------------------------------------------------------- +/// \brief +/// +/// \descr +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------- +void SysTickTimer_Reload(uint32 timeout) +{ + pSTK_LOAD->u32Register = timeout; +} + //----------------------------------------------------------------------------- /// \brief /// diff --git a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.h b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.h index eeb5c6ba2..fca437feb 100644 --- a/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.h +++ b/ref_app/src/mcal/rpi_pico2_rp2350/Mcal/SysTickTimer/SysTickTimer.h @@ -87,7 +87,7 @@ typedef union #define pSTK_VAL ((volatile stStkVal* const) (SYS_TICK_BASE_REG + 0x08)) #define pSTK_CALIB ((volatile stStkCalib* const)(SYS_TICK_BASE_REG + 0x0C)) -#define CPU_FREQ_MHZ 133U +#define CPU_FREQ_MHZ 150U #define SYS_TICK_MS(x) ((uint32)(CPU_FREQ_MHZ * x * 1000UL) - 1UL) #define SYS_TICK_US(x) ((uint32)(CPU_FREQ_MHZ * x) - 1UL) @@ -102,6 +102,6 @@ typedef union void SysTickTimer_Init(void); void SysTickTimer_Start(uint32 timeout); void SysTickTimer_Stop(void); - +void SysTickTimer_Reload(uint32 timeout); #endif /*__SYSTICK_TIMER_H__*/ diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index 96ebf2c5d..af3ff9a23 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -1012,6 +1012,7 @@ + diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index 3e60a3b3f..9e7cbff66 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -911,6 +911,9 @@ micros\rpi_pico2_rp2350\Appli + + micros\rpi_pico2_rp2350\Startup\Core\ARM + diff --git a/ref_app/target/app/make/app_make.gmk b/ref_app/target/app/make/app_make.gmk index 1c59e7920..52afc4195 100644 --- a/ref_app/target/app/make/app_make.gmk +++ b/ref_app/target/app/make/app_make.gmk @@ -265,9 +265,7 @@ GCCFLAGS = -g \ $(WARN_FLAGS) \ -Wno-comment \ -gdwarf-2 \ - -fno-exceptions \ - -ffunction-sections \ - -fdata-sections + -fno-exceptions CFLAGS = $(GCCFLAGS) \ $(TGT_CFLAGS) \ @@ -283,7 +281,7 @@ CXXFLAGS = $(GCCFLAGS) \ -Wzero-as-null-pointer-constant AFLAGS = $(GCCFLAGS) \ - $(TGT_CFLAGS) \ + $(TGT_CXXFLAGS) \ $(TGT_AFLAGS) \ -x assembler diff --git a/ref_app/target/app/make/app_rules.gmk b/ref_app/target/app/make/app_rules.gmk index d76505a1f..83391bf31 100644 --- a/ref_app/target/app/make/app_rules.gmk +++ b/ref_app/target/app/make/app_rules.gmk @@ -39,9 +39,6 @@ $(PATH_OBJ)/%.o : %.cpp # ...and be sure to include the path in the dependency file. @-$(CC) $(CXXFLAGS) $(C_INCLUDES) $(DEP_FLAGS) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err @-$(SED) -e 's|:\([0-9]*\):\([0-9]*\):|(\1,\2) :|' $(PATH_ERR)/$(basename $(@F)).err -ifneq ($(findstr risc,$(GCC_TARGET)),) - @-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst -endif # ------------------------------------------------------------------------------ # Rule to compile C++ source file (*.cc) to object file (*.o). @@ -57,9 +54,6 @@ $(PATH_OBJ)/%.o : %.cc # ...and be sure to include the path in the dependency file. @-$(CC) $(CXXFLAGS) $(C_INCLUDES) $(DEP_FLAGS) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err @-$(SED) -e 's|.h:\([0-9]*\),|.h(\1) :|' -e 's|.hpp:\([0-9]*\),|.hpp(\1) :|' -e 's|.cc:\([0-9]*\),|.cc(\1) :|' $(PATH_ERR)/$(basename $(@F)).err -ifneq ($(findstr risc,$(GCC_TARGET)),) - @-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst -endif # ------------------------------------------------------------------------------ # Rule to compile C source file (*.c) to object file (*.o). @@ -75,7 +69,6 @@ $(PATH_OBJ)/%.o : %.c # ...and be sure to include the path in the dependency file. @-$(CC) $(CFLAGS) $(C_INCLUDES) $(DEP_FLAGS) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err @-$(SED) -e 's|.h:\([0-9]*\),|.h(\1) :|' -e 's|.c:\([0-9]*\),|.c(\1) :|' $(PATH_ERR)/$(basename $(@F)).err - @-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst # ------------------------------------------------------------------------------ @@ -90,4 +83,3 @@ $(PATH_OBJ)/%.o : %.s # ...and create an assembly listing using objdump @-$(CC) $(AFLAGS) $(C_INCLUDES) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err @-$(SED) -e 's|:\([0-9]*\):|(\1) :|' $(PATH_ERR)/$(basename $(@F)).err - @-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c b/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c index 126a5c1a6..a132d02ae 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c +++ b/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c @@ -23,6 +23,8 @@ #include "Gpio.h" #include "SysTickTimer.h" +#include + //============================================================================= // Macros //============================================================================= @@ -109,7 +111,6 @@ void main_Core0(void) /// /// \return void //----------------------------------------------------------------------------------------- - #if defined(__GNUC__) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-align" @@ -122,12 +123,16 @@ volatile uint64_t* pMTIME = (volatile uint64_t*)&(HW_PER_SIO->MTIME.reg); #pragma GCC diagnostic pop #endif +extern void core_1_run_flag_set(bool); + void main_Core1(void) { #ifdef DEBUG while(boHaltCore1); #endif + core_1_run_flag_set(true); + /* Note: Core 1 is started with interrupt enabled by the BootRom */ /* Clear the stiky bits of the FIFO_ST on core 1 */ @@ -162,28 +167,46 @@ void main_Core1(void) /* set next timeout (machine timer is enabled by default) */ *pMTIMECMP = *pMTIME + 150000000ul; //1s +#else + + /* configure ARM systick timer */ + SysTickTimer_Init(); + SysTickTimer_Start(SYS_TICK_MS(100)); + #endif while(1) { - LED_GREEN_TOGGLE(); - - BlockingDelay(10000000); - BlockingDelay(10000000); - BlockingDelay(10000000); + __asm("nop"); } } #ifdef CORE_FAMILY_RISC_V -__attribute__((interrupt)) void Isr_MachineTimerInterrupt(void); - -void Isr_MachineTimerInterrupt(void) -{ + __attribute__((interrupt)) void Isr_MachineTimerInterrupt(void); + + void Isr_MachineTimerInterrupt(void) + { *pMTIMECMP = *pMTIME + 150000000ul; + + LED_GREEN_TOGGLE(); + } - LED_GREEN_TOGGLE(); -} +#else + + void SysTickTimer(void); + + void SysTickTimer(void) + { + static uint32_t cpt = 0; + SysTickTimer_Reload(SYS_TICK_MS(100)); + + if(++cpt >= 10ul) + { + LED_GREEN_TOGGLE(); + cpt = 0; + } + } #endif diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/IntVect.c b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/IntVect.c index 8500b4d9a..1f1ecea68 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/IntVect.c +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/IntVect.c @@ -26,7 +26,7 @@ void UndefinedHandler(void) { for(;;); } //============================================================================= // Functions prototype //============================================================================= -void Startup_Init(void); +void Startup_Init(void) __attribute__((used)); void main_Core1 (void) __attribute__((weak, alias("UndefinedHandler"))); void __CORE0_STACK_TOP(void); void __CORE1_STACK_TOP(void); @@ -85,7 +85,7 @@ void POWMAN_IRQ_TIMER_IRQn(void) __attribute__((weak, alias("UndefinedHandler")) //============================================================================= // Interrupt vector table Core0 //============================================================================= -const InterruptHandler __attribute__((section(".intvect_c0"), aligned(128))) __INTVECT_Core0[] = +const InterruptHandler __attribute__((section(".intvect_c0"), used, aligned(128))) __INTVECT_Core0[] = { (InterruptHandler)&__CORE0_STACK_TOP, (InterruptHandler)&Startup_Init, @@ -158,7 +158,7 @@ const InterruptHandler __attribute__((section(".intvect_c0"), aligned(128))) __I //============================================================================= // Interrupt vector table Core1 //============================================================================= -const InterruptHandler __attribute__((section(".intvect_c1"), aligned(128))) __INTVECT_Core1[] = +const InterruptHandler __attribute__((section(".intvect_c1"), used, aligned(128))) __INTVECT_Core1[] = { (InterruptHandler)&__CORE1_STACK_TOP, (InterruptHandler)&main_Core1, diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_1_run.cpp b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_1_run.cpp new file mode 100644 index 000000000..5cd4ee408 --- /dev/null +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_1_run.cpp @@ -0,0 +1,30 @@ + +namespace local +{ + auto core_1_run_flag() -> bool&; + + auto core_1_run_flag() -> bool& + { + static bool run_flag { false }; + + return run_flag; + } +} + +extern "C" +{ + auto core_1_run_flag_set(bool setting) -> void; + auto core_1_run_flag_get(void) -> bool; + + auto core_1_run_flag_set(bool setting) -> void + { + local::core_1_run_flag() = setting; + } + + auto core_1_run_flag_get(void) -> bool + { + const bool result { local::core_1_run_flag() }; + + return result; + } +} diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h index 5873a0796..592617e80 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h @@ -21,6 +21,11 @@ #define CORE_ARCH_SEND_EVENT_INST() __asm("SEV") +#define CORE_ARCH_DISABLE_INTERRUPTS() __asm("CPSID i") +#define CORE_ARCH_ENABLE_INTERRUPTS() __asm("CPSIE i") +void arch_spin_lock(uint32* lock); +void arch_spin_unlock(uint32* lock); + #endif //__CORE_ARCH_H__ diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/image_definition_block.c b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/image_definition_block.c index 44f36c70f..054a21313 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/image_definition_block.c +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/image_definition_block.c @@ -15,13 +15,13 @@ ******************************************************************************************/ -#include "stdint.h" +#include -const uint32_t __attribute__((section(".image_start_block"), aligned(4))) image_definition_Block[] = +const uint32_t __attribute__((section(".image_start_block"), used, aligned(4))) image_definition_Block[] = { - 0xffffded3, - 0x10210142, - 0x000001ff, - 0x00000000, - 0xab123579 + UINT32_C(0xFFFFDED3), + UINT32_C(0x10210142), + UINT32_C(0x000001FF), + UINT32_C(0x00000000), + UINT32_C(0xAB123579) }; diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/util.s b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/util.s index 2fba0b503..f840de27e 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/util.s +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/util.s @@ -17,7 +17,13 @@ .cpu cortex-m33 +/******************************************************************************************* + \brief + \param + + \return +********************************************************************************************/ .thumb_func .section ".text", "ax" .align 8 @@ -32,3 +38,54 @@ BlockingDelay: .size BlockingDelay, .-BlockingDelay +/******************************************************************************************* + \brief + + \param + + \return +********************************************************************************************/ +.thumb_func +.section ".text", "ax" +.align 8 +.globl arch_spin_lock +.type arch_spin_lock, % function + + +arch_spin_lock: + mov r1, #1 // Set r1 to 1 (lock acquired) +.L_loop: + ldaex r2, [r0] // Load exclusive value + cmp r2, #0 // Check if lock is free + bne .L_loop // Retry if not free + strex r2, r1, [r0] // Try to acquire the lock + cmp r2, #0 // Check if successful + bne .L_loop // Retry if not + dmb // Ensure memory ordering after acquiring the lock + bx lr // Return if successful + + +.size arch_spin_lock, .-arch_spin_lock + +/******************************************************************************************* + \brief + + \param + + \return +********************************************************************************************/ +.thumb_func +.section ".text", "ax" +.align 8 +.globl arch_spin_unlock +.type arch_spin_unlock, % function + + +arch_spin_unlock: + dmb // Ensure memory operations before unlocking + mov r1, #0 // Clear the lock + stl r1, [r0] // Store with release semantics + bx lr // Return + + +.size arch_spin_unlock, .-arch_spin_unlock diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Startup.c b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Startup.c index 437a6226f..78212065f 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Startup.c +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Startup.c @@ -54,7 +54,7 @@ static void Startup_InitCore(void); //========================================================================================= // extern function prototype //========================================================================================= -int main(void) __attribute__((weak)); +int main(void); void RP2350_ClockInit(void) __attribute__((weak)); void RP2350_InitCore(void) __attribute__((weak)); diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk index fe8e06bf6..8395ced39 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk @@ -16,6 +16,7 @@ FILES_TGT = $(PATH_APP)/mcal/$(TGT)/Mcal/Clock/Clock \ $(PATH_APP)/mcal/$(TGT)/Mcal/SysTickTimer/SysTickTimer \ $(PATH_TGT)/Appli/main \ $(PATH_TGT)/Startup/Core/ARM/boot \ + $(PATH_TGT)/Startup/Core/ARM/core_1_run \ $(PATH_TGT)/Startup/Core/ARM/image_definition_block \ $(PATH_TGT)/Startup/Core/ARM/IntVect \ $(PATH_TGT)/Startup/Core/ARM/util \ diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk index e7adb1e64..67ed8f694 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_flags.gmk @@ -8,50 +8,57 @@ # compiler flags for the target architecture # ------------------------------------------------------------------------------ -GCC_VERSION = 13.2.1 +GCC_VERSION = 13.3.1 GCC_TARGET = arm-none-eabi GCC_PREFIX = arm-none-eabi TGT_SUFFIX = elf -TGT_ALLFLAGS = -O0 \ - -mlittle-endian \ - -mlong-calls \ +TGT_ALLFLAGS = -O2 \ -mcpu=cortex-m33 \ - -march=armv8-m.main+fp+dsp \ - -mfloat-abi=softfp \ -mthumb \ + -march=armv8-m.main+fp+dsp \ -mabi=aapcs \ - -finline-functions \ - -finline-limit=64 + -mfloat-abi=softfp \ + -DCORE_FAMILY_ARM \ + -MD \ + -fomit-frame-pointer \ + -Wa,-adhln=$(PATH_LST)/$(basename $(@F)).lst TGT_CFLAGS = -std=c11 \ -Wunsuffixed-float-constants \ $(TGT_ALLFLAGS) \ - -DCORE_FAMILY_ARM + -DCORE_FAMILY_ARM \ + -Wa,-adhln=$(PATH_LST)/$(basename $(@F)).lst TGT_CXXFLAGS = -std=c++14 \ -Wno-psabi \ - $(TGT_ALLFLAGS) + $(TGT_ALLFLAGS) \ + -Wa,-adhln=$(PATH_LST)/$(basename $(@F)).lst TGT_INCLUDES = -I$(PATH_TGT)/Startup/Core/ARM \ -I$(PATH_APP)/mcal/$(TGT)/Mcal/Clock \ - -I$(PATH_APP)/mcal/$(TGT)/Mcal/Cmsis \ -I$(PATH_APP)/mcal/$(TGT)/Mcal/Cmsis/m-profile \ + -I$(PATH_APP)/mcal/$(TGT)/Mcal/Cmsis \ -I$(PATH_APP)/mcal/$(TGT)/Mcal/Cpu \ -I$(PATH_APP)/mcal/$(TGT)/Mcal/Gpio \ -I$(PATH_APP)/mcal/$(TGT)/Mcal/SysTickTimer \ -I$(PATH_APP)/mcal/$(TGT)/Mcal \ - -I$(PATH_TGT)/Std \ - -isystem $(PATH_APP)/util/STL + -I$(PATH_TGT)/Std -TGT_AFLAGS = +TGT_AFLAGS = $(TGT_ALLFLAGS) TGT_LDFLAGS = -nostdlib \ -nostartfiles \ - -Wl,--gc-sections \ + $(TGT_ALLFLAGS) \ + -e Startup_Init \ + -Wl,--no-warn-rwx-segments \ + -Wl,-z,max-page-size=4096 \ -Wl,-Map,$(APP).map \ - -T $(LINKER_DEFINITION_FILE) + -T $(LINKER_DEFINITION_FILE) \ + --specs=nano.specs \ + --specs=nosys.specs + ifeq ($(TYP_OS),WIN) IMG_SUFFIX := uf2 From b5573e63c7147fa098aa0548109473c31c825470 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Fri, 13 Sep 2024 07:46:23 +0200 Subject: [PATCH 5/7] Restore some build attribs also it boots --- ref_app/target/app/make/app_make.gmk | 3 ++- ref_app/target/app/make/app_rules.gmk | 8 ++++++++ .../micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h | 2 +- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/ref_app/target/app/make/app_make.gmk b/ref_app/target/app/make/app_make.gmk index 52afc4195..d3101eb7a 100644 --- a/ref_app/target/app/make/app_make.gmk +++ b/ref_app/target/app/make/app_make.gmk @@ -265,7 +265,8 @@ GCCFLAGS = -g \ $(WARN_FLAGS) \ -Wno-comment \ -gdwarf-2 \ - -fno-exceptions + -fno-exceptions \ + -ffunction-sections CFLAGS = $(GCCFLAGS) \ $(TGT_CFLAGS) \ diff --git a/ref_app/target/app/make/app_rules.gmk b/ref_app/target/app/make/app_rules.gmk index 83391bf31..d76505a1f 100644 --- a/ref_app/target/app/make/app_rules.gmk +++ b/ref_app/target/app/make/app_rules.gmk @@ -39,6 +39,9 @@ $(PATH_OBJ)/%.o : %.cpp # ...and be sure to include the path in the dependency file. @-$(CC) $(CXXFLAGS) $(C_INCLUDES) $(DEP_FLAGS) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err @-$(SED) -e 's|:\([0-9]*\):\([0-9]*\):|(\1,\2) :|' $(PATH_ERR)/$(basename $(@F)).err +ifneq ($(findstr risc,$(GCC_TARGET)),) + @-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst +endif # ------------------------------------------------------------------------------ # Rule to compile C++ source file (*.cc) to object file (*.o). @@ -54,6 +57,9 @@ $(PATH_OBJ)/%.o : %.cc # ...and be sure to include the path in the dependency file. @-$(CC) $(CXXFLAGS) $(C_INCLUDES) $(DEP_FLAGS) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err @-$(SED) -e 's|.h:\([0-9]*\),|.h(\1) :|' -e 's|.hpp:\([0-9]*\),|.hpp(\1) :|' -e 's|.cc:\([0-9]*\),|.cc(\1) :|' $(PATH_ERR)/$(basename $(@F)).err +ifneq ($(findstr risc,$(GCC_TARGET)),) + @-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst +endif # ------------------------------------------------------------------------------ # Rule to compile C source file (*.c) to object file (*.o). @@ -69,6 +75,7 @@ $(PATH_OBJ)/%.o : %.c # ...and be sure to include the path in the dependency file. @-$(CC) $(CFLAGS) $(C_INCLUDES) $(DEP_FLAGS) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err @-$(SED) -e 's|.h:\([0-9]*\),|.h(\1) :|' -e 's|.c:\([0-9]*\),|.c(\1) :|' $(PATH_ERR)/$(basename $(@F)).err + @-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst # ------------------------------------------------------------------------------ @@ -83,3 +90,4 @@ $(PATH_OBJ)/%.o : %.s # ...and create an assembly listing using objdump @-$(CC) $(AFLAGS) $(C_INCLUDES) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err @-$(SED) -e 's|:\([0-9]*\):|(\1) :|' $(PATH_ERR)/$(basename $(@F)).err + @-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h index 592617e80..583baafd1 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h @@ -25,7 +25,7 @@ #define CORE_ARCH_ENABLE_INTERRUPTS() __asm("CPSIE i") -void arch_spin_lock(uint32* lock); +void arch_spin_lock (uint32* lock); void arch_spin_unlock(uint32* lock); #endif //__CORE_ARCH_H__ From 3cf3a75739b504f7f3b8fcc6737f2dd7d410d52f Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Fri, 13 Sep 2024 19:48:19 +0200 Subject: [PATCH 6/7] Update regarding chalandi improvements --- ref_app/ref_app.vcxproj | 16 ---------------- ref_app/ref_app.vcxproj.filters | 15 --------------- ref_app/target.vcxproj | 1 - ref_app/target.vcxproj.filters | 3 --- ref_app/target/app/make/app_make.gmk | 1 + .../target/micros/rpi_pico2_rp2350/Appli/main.c | 5 +++++ .../rpi_pico2_rp2350/Startup/Core/ARM/boot.s | 0 .../rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld | 4 +++- .../make/rpi_pico2_rp2350_files.gmk | 1 - 9 files changed, 9 insertions(+), 37 deletions(-) delete mode 100644 ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/boot.s diff --git a/ref_app/ref_app.vcxproj b/ref_app/ref_app.vcxproj index 1037a7adc..0794ea605 100644 --- a/ref_app/ref_app.vcxproj +++ b/ref_app/ref_app.vcxproj @@ -584,10 +584,6 @@ true true - - true - true - true true @@ -1971,18 +1967,6 @@ true true - - true - true - - - true - true - - - true - true - true true diff --git a/ref_app/ref_app.vcxproj.filters b/ref_app/ref_app.vcxproj.filters index ca4c97ed3..bb2d6dee1 100644 --- a/ref_app/ref_app.vcxproj.filters +++ b/ref_app/ref_app.vcxproj.filters @@ -248,9 +248,6 @@ {5e0acfbd-219f-4b10-a237-ea58c3677e31} - - {2ba6be78-d4c7-4100-ae31-1b1e8ac645a5} - @@ -1153,9 +1150,6 @@ src\mcal\rpi_pico2_rp2350\Mcal\SysTickTimer - - src\mcal\rpi_pico2_rp2350\Mcal\USB - @@ -2709,15 +2703,6 @@ src\mcal\rpi_pico2_rp2350\Mcal\SysTickTimer - - src\mcal\rpi_pico2_rp2350\Mcal\USB - - - src\mcal\rpi_pico2_rp2350\Mcal\USB - - - src\mcal\rpi_pico2_rp2350\Mcal\USB - diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index af3ff9a23..52f1efbe6 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -904,7 +904,6 @@ - diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index 9e7cbff66..ad1c601d0 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -615,9 +615,6 @@ micros\rpi_pico2_rp2350\Startup\Core\ARM - - micros\rpi_pico2_rp2350\Startup\Core\ARM - micros\rpi_pico2_rp2350\make diff --git a/ref_app/target/app/make/app_make.gmk b/ref_app/target/app/make/app_make.gmk index d3101eb7a..2809a9131 100644 --- a/ref_app/target/app/make/app_make.gmk +++ b/ref_app/target/app/make/app_make.gmk @@ -266,6 +266,7 @@ GCCFLAGS = -g \ -Wno-comment \ -gdwarf-2 \ -fno-exceptions \ + -fdata-sections \ -ffunction-sections CFLAGS = $(GCCFLAGS) \ diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c b/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c index a132d02ae..5eacd801f 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c +++ b/ref_app/target/micros/rpi_pico2_rp2350/Appli/main.c @@ -139,6 +139,11 @@ void main_Core1(void) HW_PER_SIO->FIFO_ST.reg = 0xFFu; #ifdef CORE_FAMILY_ARM + + /*Setting EXTEXCLALL allows external exclusive operations to be used in a configuration with no MPU. + This is because the default memory map does not include any shareable Normal memory.*/ + SCnSCB->ACTLR |= (1ul<<29); + __asm volatile("DSB"); /* Clear all pending interrupts on core 1 */ diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/boot.s b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/boot.s deleted file mode 100644 index e69de29bb..000000000 diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld index fb346f89f..d1598b86b 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350.ld @@ -55,7 +55,7 @@ SECTIONS PROVIDE(__IMAGE_DEF_BLOCK_START_ADDRESS = .); KEEP(*(.image_start_block)) *(.text) - *(.text.*) + *(.text*) } > FLASH /* Read-only data (.rodata) */ @@ -115,6 +115,7 @@ SECTIONS { PROVIDE(__DATA_BASE_ADDRESS = .); *(.data) + *(.data*) } > RAM AT>FLASH /* The uninitialized (zero-cleared) bss section */ @@ -122,6 +123,7 @@ SECTIONS { PROVIDE(__BSS_BASE_ADDRESS = .); *(.bss) + *(.bss*) } > RAM /* stack definition */ diff --git a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk index 8395ced39..47a33fdf2 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk +++ b/ref_app/target/micros/rpi_pico2_rp2350/make/rpi_pico2_rp2350_files.gmk @@ -15,7 +15,6 @@ FILES_TGT = $(PATH_APP)/mcal/$(TGT)/Mcal/Clock/Clock \ $(PATH_APP)/mcal/$(TGT)/Mcal/Cpu/Cpu \ $(PATH_APP)/mcal/$(TGT)/Mcal/SysTickTimer/SysTickTimer \ $(PATH_TGT)/Appli/main \ - $(PATH_TGT)/Startup/Core/ARM/boot \ $(PATH_TGT)/Startup/Core/ARM/core_1_run \ $(PATH_TGT)/Startup/Core/ARM/image_definition_block \ $(PATH_TGT)/Startup/Core/ARM/IntVect \ From ed42e4e91d52420a1bad1348c1a5a396e0e1ae13 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Fri, 13 Sep 2024 19:51:34 +0200 Subject: [PATCH 7/7] Improve syntax --- .../micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h index 583baafd1..fbdfda840 100644 --- a/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h +++ b/ref_app/target/micros/rpi_pico2_rp2350/Startup/Core/ARM/core_arch.h @@ -18,13 +18,10 @@ #ifndef __CORE_ARCH_H__ #define __CORE_ARCH_H__ - - #define CORE_ARCH_SEND_EVENT_INST() __asm("SEV") #define CORE_ARCH_DISABLE_INTERRUPTS() __asm("CPSID i") #define CORE_ARCH_ENABLE_INTERRUPTS() __asm("CPSIE i") - void arch_spin_lock (uint32* lock); void arch_spin_unlock(uint32* lock);