From 230824dec6964cea510f1b943a70de0a9536d7e4 Mon Sep 17 00:00:00 2001 From: Lukasz Dalek Date: Tue, 13 Apr 2021 13:14:06 +0200 Subject: [PATCH] forbid-implicit-declarations: Apply clang formatting Signed-off-by: Lukasz Dalek --- .../forbid_implicit_declarations_rule.cc | 90 ++-- .../forbid_implicit_declarations_rule_test.cc | 432 ++++++++++-------- 2 files changed, 287 insertions(+), 235 deletions(-) diff --git a/verilog/analysis/checkers/forbid_implicit_declarations_rule.cc b/verilog/analysis/checkers/forbid_implicit_declarations_rule.cc index e1ae41600..f301ca43a 100644 --- a/verilog/analysis/checkers/forbid_implicit_declarations_rule.cc +++ b/verilog/analysis/checkers/forbid_implicit_declarations_rule.cc @@ -25,9 +25,9 @@ #include "common/text/symbol.h" #include "common/text/syntax_tree_context.h" #include "common/text/tree_context_visitor.h" +#include "verilog/CST/identifier.h" #include "verilog/analysis/descriptions.h" #include "verilog/analysis/lint_rule_registry.h" -#include "verilog/CST/identifier.h" #include "verilog/analysis/symbol_table.h" namespace verilog { @@ -49,20 +49,23 @@ const char ForbidImplicitDeclarationsRule::kTopic[] = "implicit-declarations"; const char ForbidImplicitDeclarationsRule::kMessage[] = "Nets must be declared explicitly."; -std::string ForbidImplicitDeclarationsRule::GetDescription(DescriptionType description_type) { - return absl::StrCat("Checks that there are no occurrences of " - "implicitly declared nets."); +std::string ForbidImplicitDeclarationsRule::GetDescription( + DescriptionType description_type) { + return absl::StrCat( + "Checks that there are no occurrences of " + "implicitly declared nets."); } -void ForbidImplicitDeclarationsRule::Lint(const verible::TextStructureView& text_structure, - absl::string_view filename) { +void ForbidImplicitDeclarationsRule::Lint( + const verible::TextStructureView& text_structure, + absl::string_view filename) { SymbolTable symbol_table(nullptr); ParsedVerilogSourceFile* src = new ParsedVerilogSourceFile("internal", &text_structure); // Already parsed, calling to ensure that VerilogSourceFile internals are in // correct state - const auto status =src->Parse(); + const auto status = src->Parse(); CHECK_EQ(status.ok(), true); auto diagnostics = BuildSymbolTable(*src, &symbol_table); @@ -73,42 +76,43 @@ void ForbidImplicitDeclarationsRule::Lint(const verible::TextStructureView& text // during symbol table building stage auto& violations = this->violations_; - symbol_table.Root().ApplyPreOrder( - [&violations, &text_structure](const SymbolTableNode& node) { - for (const auto& itr : node.Value().local_references_to_bind) { - ABSL_DIE_IF_NULL(itr.LastLeaf())->ApplyPreOrder( - [&violations, &text_structure](const ReferenceComponent& node) { - // Skip unresolved symbols (implicit declarations are pre-resolved) - if (node.resolved_symbol == nullptr) { - return; - } - - const auto& resolved_symbol_node = - *ABSL_DIE_IF_NULL(node.resolved_symbol); - const auto& resolved_symbol = - resolved_symbol_node.Value(); - const auto& resolved_symbol_identifier = - *ABSL_DIE_IF_NULL(resolved_symbol_node.Key()); - - // Skip pre-resolved symbols that have explicit declarations - if (resolved_symbol.declared_type.implicit == false) { - return; - } - - // Only report reference that caused implicit declarations - if (node.identifier.begin() == resolved_symbol_identifier.begin()) { - const auto offset = std::distance(text_structure.Contents().begin(), - node.identifier.begin()); - CHECK_GE(offset, 0); - auto range = text_structure.TokenRangeSpanningOffsets(offset, offset); - auto token = range.begin(); - CHECK(token != text_structure.TokenStream().end()); - const auto& token_info = *token; - violations.insert(LintViolation(token_info, kMessage)); - } - }); - } - }); + symbol_table.Root().ApplyPreOrder([&violations, &text_structure]( + const SymbolTableNode& node) { + for (const auto& itr : node.Value().local_references_to_bind) { + ABSL_DIE_IF_NULL(itr.LastLeaf()) + ->ApplyPreOrder([&violations, + &text_structure](const ReferenceComponent& node) { + // Skip unresolved symbols (implicit declarations are pre-resolved) + if (node.resolved_symbol == nullptr) { + return; + } + + const auto& resolved_symbol_node = + *ABSL_DIE_IF_NULL(node.resolved_symbol); + const auto& resolved_symbol = resolved_symbol_node.Value(); + const auto& resolved_symbol_identifier = + *ABSL_DIE_IF_NULL(resolved_symbol_node.Key()); + + // Skip pre-resolved symbols that have explicit declarations + if (resolved_symbol.declared_type.implicit == false) { + return; + } + + // Only report reference that caused implicit declarations + if (node.identifier.begin() == resolved_symbol_identifier.begin()) { + const auto offset = std::distance( + text_structure.Contents().begin(), node.identifier.begin()); + CHECK_GE(offset, 0); + auto range = + text_structure.TokenRangeSpanningOffsets(offset, offset); + auto token = range.begin(); + CHECK(token != text_structure.TokenStream().end()); + const auto& token_info = *token; + violations.insert(LintViolation(token_info, kMessage)); + } + }); + } + }); } LintRuleStatus ForbidImplicitDeclarationsRule::Report() const { diff --git a/verilog/analysis/checkers/forbid_implicit_declarations_rule_test.cc b/verilog/analysis/checkers/forbid_implicit_declarations_rule_test.cc index f4a5513c6..c58565d84 100644 --- a/verilog/analysis/checkers/forbid_implicit_declarations_rule_test.cc +++ b/verilog/analysis/checkers/forbid_implicit_declarations_rule_test.cc @@ -16,10 +16,10 @@ #include -#include "gtest/gtest.h" #include "common/analysis/linter_test_utils.h" #include "common/analysis/text_structure_linter_test_utils.h" #include "common/text/symbol.h" +#include "gtest/gtest.h" #include "verilog/CST/verilog_nonterminals.h" #include "verilog/CST/verilog_treebuilder_utils.h" #include "verilog/analysis/verilog_analyzer.h" @@ -33,197 +33,245 @@ using verible::RunLintTestCases; TEST(ForbidImplicitDeclarationsRule, FunctionFailures) { auto kToken = SymbolIdentifier; - const std::initializer_list ForbidImplicitDeclarationsTestCases = { - {""}, - {"module m;\nendmodule\n"}, - {"module m;\nassign ", {kToken, "a1"}, " = 1'b0;\nendmodule"}, - {"module m;\n" - " wire a1;\n" - " assign a1 = 1'b0;\n" - "endmodule"}, - {"module m;\n" - " assign ", {kToken, "a1"}, " = 1'b1;\n" - " module foo;\n" - " endmodule\n" - "endmodule"}, - {"module m;\n" - " module foo;\n" - " endmodule\n" - " assign ", {kToken, "a1"}, " = 1'b1;\n" - "endmodule"}, - {"module m;\n" - " wire a1;\n" - " module foo;\n" - " assign a1 = 1'b0;\n" - " endmodule;\n" - "endmodule"}, - - // declaration and assignement separated by module block - {"module m;\n" - " wire a1;\n" - " module foo;\n" - " endmodule;\n" - " assign a1 = 1'b0;\n" - "endmodule"}, - {"module m;\n" - " wire a1;\n" - " module foo;\n" - " assign a1 = 1'b0;\n" - " endmodule\n" - " assign a1 = 1'b0;\n" - "endmodule"}, - - // overlapping net - {"module m;\n" - " wire a1;\n" - " module foo;\n" - " wire a1;\n" - " assign a1 = 1'b0;\n" - " endmodule\n" - " assign a1 = 1'b0;\n" - "endmodule"}, - - // multiple declarations - {"module m;\n" - " wire a0, a1;\n" - " assign a0 = 1'b0;\n" - " assign a1 = 1'b1;\n" - "endmodule"}, - {"module m;\n" - " wire a0, a2;\n" - " assign a0 = 1'b0;\n" - " assign ", {kToken, "a1"}, " = 1'b1;\n" - "endmodule"}, - - // multiple net assignments - {"module m;\n" - " assign ", {kToken, "a"}, " = b, ", {kToken, "c"}, " = d;\n" - "endmodule"}, - - // concatenated - {"module m;\n" - " assign {", {kToken, "a"}, "} = 1'b0;\n" - "endmodule"}, - {"module m;\n" - " assign {", {kToken, "a"}, ",", {kToken, "b"}, "} = 2'b01;\n" - "endmodule"}, - {"module m;\n" - " assign {", {kToken, "a"}, ",", {kToken, "b"}, ",", {kToken, "c"}, "} = 3'b010;\n" - "endmodule"}, - {"module m;\n" - " wire b;\n" - " assign {", {kToken, "a"}, ", b,", {kToken, "c"}, "} = 3'b010;\n" - "endmodule"}, - - // out-of-scope - {"module m;\n" - " module foo;\n" - " wire a1;\n" - " endmodule\n" - " assign ", {kToken, "a1"}, " = 1'b1;\n" - "endmodule"}, - {"module m;\n" - " module foo;\n" - " wire a1;\n" - " assign a1 = 1'b0;\n" - " endmodule\n" - " assign ", {kToken, "a1"}, " = 1'b1;\n" - "endmodule"}, - {"module m;\n" - " wire a1;\n" - " module foo;\n" - " assign a1 = 1'b0;\n" - " endmodule\n" - " assign a1 = 1'b1;\n" - "endmodule"}, - - // multi-level module blocks - {"module m1;\n" - " wire x1;\n" - " module m2;\n" - " wire x2;\n" - " module m3;\n" - " wire x3;\n" - " module m4;\n" - " wire x4;\n" - " assign x4 = 1'b0;\n" - " assign x3 = 1'b0;\n" - " assign x2 = 1'b0;\n" - " assign x1 = 1'b0;\n" - " endmodule\n" - " assign ", {kToken, "x4"}, " = 1'b0;\n" - " assign x3 = 1'b1;\n" - " assign x2 = 1'b0;\n" - " assign x1 = 1'b0;\n" - " endmodule\n" - " assign ", {kToken, "x4"}, " = 1'b0;\n" - " assign ", {kToken, "x3"}, " = 1'b0;\n" - " assign x2 = 1'b0;\n" - " assign x1 = 1'b0;\n" - " endmodule\n" - " assign ", {kToken, "x4"}, " = 1'b0;\n" - " assign ", {kToken, "x3"}, " = 1'b0;\n" - " assign ", {kToken, "x2"}, " = 1'b0;\n" - " assign x1 = 1'b1;\n" - "endmodule"}, - - // generate block, TODO: multi-level - {"module m;\ngenerate\nendgenerate\nendmodule"}, - {"module m;\n" - " wire a1;\n" - " assign a1 = 1'b1;\n" - " generate\n" - " endgenerate\n" - " assign a1 = 1'b0;\n" - "endmodule"}, - {"module m;\n" - " generate\n" - " wire a1;\n" - " assign a1 = 1'b1;\n" - " endgenerate\n" - "endmodule"}, - {"module m;\n" - " generate\n" - " assign ", {kToken, "a1"}, " = 1'b1;\n" - " endgenerate\n" - "endmodule"}, - {"module m;\n" - " generate\n" - " wire a1;\n" - " assign a1 = 1'b1;\n" - " endgenerate\n" - " assign a1 = 1'b1;\n" - "endmodule"}, - {"module m;\n" - " wire a1;\n" - " assign a1 = 1'b1;\n" - " generate\n" - " assign a1 = 1'b1;\n" - " endgenerate\n" - " assign a1 = 1'b0;\n" - "endmodule"}, - {"module m;\n" - " wire a1;\n" - " generate\n" - " wire a2\n" - " assign a1 = 1'b1;\n" - " endgenerate\n" - " assign ", {kToken, "a2"}, " = 1'b0;\n" - "endmodule"}, - {"module m;\n" - " wire a1;\n" - " generate\n" - " wire a2;\n" - " assign a1 = 1'b1;\n" - " assign a2 = a1;\n" - " endgenerate\n" - " assign a2 = 1'b0;\n" - " assign a1 = a2;\n" - "endmodule"}, - - // TODO: nets declared inside terminal/port connection list - // TODO: assignments/connections inside loop and conditional generate constructs - }; + const std::initializer_list + ForbidImplicitDeclarationsTestCases = { + {""}, + {"module m;\nendmodule\n"}, + {"module m;\nassign ", {kToken, "a1"}, " = 1'b0;\nendmodule"}, + {"module m;\n" + " wire a1;\n" + " assign a1 = 1'b0;\n" + "endmodule"}, + {"module m;\n" + " assign ", + {kToken, "a1"}, + " = 1'b1;\n" + " module foo;\n" + " endmodule\n" + "endmodule"}, + {"module m;\n" + " module foo;\n" + " endmodule\n" + " assign ", + {kToken, "a1"}, + " = 1'b1;\n" + "endmodule"}, + {"module m;\n" + " wire a1;\n" + " module foo;\n" + " assign a1 = 1'b0;\n" + " endmodule;\n" + "endmodule"}, + + // declaration and assignement separated by module block + {"module m;\n" + " wire a1;\n" + " module foo;\n" + " endmodule;\n" + " assign a1 = 1'b0;\n" + "endmodule"}, + {"module m;\n" + " wire a1;\n" + " module foo;\n" + " assign a1 = 1'b0;\n" + " endmodule\n" + " assign a1 = 1'b0;\n" + "endmodule"}, + + // overlapping net + {"module m;\n" + " wire a1;\n" + " module foo;\n" + " wire a1;\n" + " assign a1 = 1'b0;\n" + " endmodule\n" + " assign a1 = 1'b0;\n" + "endmodule"}, + + // multiple declarations + {"module m;\n" + " wire a0, a1;\n" + " assign a0 = 1'b0;\n" + " assign a1 = 1'b1;\n" + "endmodule"}, + {"module m;\n" + " wire a0, a2;\n" + " assign a0 = 1'b0;\n" + " assign ", + {kToken, "a1"}, + " = 1'b1;\n" + "endmodule"}, + + // multiple net assignments + {"module m;\n" + " assign ", + {kToken, "a"}, + " = b, ", + {kToken, "c"}, + " = d;\n" + "endmodule"}, + + // concatenated + {"module m;\n" + " assign {", + {kToken, "a"}, + "} = 1'b0;\n" + "endmodule"}, + {"module m;\n" + " assign {", + {kToken, "a"}, + ",", + {kToken, "b"}, + "} = 2'b01;\n" + "endmodule"}, + {"module m;\n" + " assign {", + {kToken, "a"}, + ",", + {kToken, "b"}, + ",", + {kToken, "c"}, + "} = 3'b010;\n" + "endmodule"}, + {"module m;\n" + " wire b;\n" + " assign {", + {kToken, "a"}, + ", b,", + {kToken, "c"}, + "} = 3'b010;\n" + "endmodule"}, + + // out-of-scope + {"module m;\n" + " module foo;\n" + " wire a1;\n" + " endmodule\n" + " assign ", + {kToken, "a1"}, + " = 1'b1;\n" + "endmodule"}, + {"module m;\n" + " module foo;\n" + " wire a1;\n" + " assign a1 = 1'b0;\n" + " endmodule\n" + " assign ", + {kToken, "a1"}, + " = 1'b1;\n" + "endmodule"}, + {"module m;\n" + " wire a1;\n" + " module foo;\n" + " assign a1 = 1'b0;\n" + " endmodule\n" + " assign a1 = 1'b1;\n" + "endmodule"}, + + // multi-level module blocks + {"module m1;\n" + " wire x1;\n" + " module m2;\n" + " wire x2;\n" + " module m3;\n" + " wire x3;\n" + " module m4;\n" + " wire x4;\n" + " assign x4 = 1'b0;\n" + " assign x3 = 1'b0;\n" + " assign x2 = 1'b0;\n" + " assign x1 = 1'b0;\n" + " endmodule\n" + " assign ", + {kToken, "x4"}, + " = 1'b0;\n" + " assign x3 = 1'b1;\n" + " assign x2 = 1'b0;\n" + " assign x1 = 1'b0;\n" + " endmodule\n" + " assign ", + {kToken, "x4"}, + " = 1'b0;\n" + " assign ", + {kToken, "x3"}, + " = 1'b0;\n" + " assign x2 = 1'b0;\n" + " assign x1 = 1'b0;\n" + " endmodule\n" + " assign ", + {kToken, "x4"}, + " = 1'b0;\n" + " assign ", + {kToken, "x3"}, + " = 1'b0;\n" + " assign ", + {kToken, "x2"}, + " = 1'b0;\n" + " assign x1 = 1'b1;\n" + "endmodule"}, + + // generate block, TODO: multi-level + {"module m;\ngenerate\nendgenerate\nendmodule"}, + {"module m;\n" + " wire a1;\n" + " assign a1 = 1'b1;\n" + " generate\n" + " endgenerate\n" + " assign a1 = 1'b0;\n" + "endmodule"}, + {"module m;\n" + " generate\n" + " wire a1;\n" + " assign a1 = 1'b1;\n" + " endgenerate\n" + "endmodule"}, + {"module m;\n" + " generate\n" + " assign ", + {kToken, "a1"}, + " = 1'b1;\n" + " endgenerate\n" + "endmodule"}, + {"module m;\n" + " generate\n" + " wire a1;\n" + " assign a1 = 1'b1;\n" + " endgenerate\n" + " assign a1 = 1'b1;\n" + "endmodule"}, + {"module m;\n" + " wire a1;\n" + " assign a1 = 1'b1;\n" + " generate\n" + " assign a1 = 1'b1;\n" + " endgenerate\n" + " assign a1 = 1'b0;\n" + "endmodule"}, + {"module m;\n" + " wire a1;\n" + " generate\n" + " wire a2\n" + " assign a1 = 1'b1;\n" + " endgenerate\n" + " assign ", + {kToken, "a2"}, + " = 1'b0;\n" + "endmodule"}, + {"module m;\n" + " wire a1;\n" + " generate\n" + " wire a2;\n" + " assign a1 = 1'b1;\n" + " assign a2 = a1;\n" + " endgenerate\n" + " assign a2 = 1'b0;\n" + " assign a1 = a2;\n" + "endmodule"}, + + // TODO: nets declared inside terminal/port connection list + // TODO: assignments/connections inside loop and conditional generate + // constructs + }; RunLintTestCases( ForbidImplicitDeclarationsTestCases);