From 4c7c91c40aededf29d8b0a7c91bbcaf37051503d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 28 Oct 2024 10:58:56 -0700 Subject: [PATCH] vsets should trap when mstatus.VS is off --- src/main/scala/rocket/RocketCore.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index db3a48846e2..20f9cf534ed 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -382,7 +382,8 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') || id_ctrl.amo && !csr.io.status.isa('a'-'a') || id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) || - (id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) || + id_set_vconfig && csr.io.decode(0).vector_illegal || + id_ctrl.vec && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) || id_ctrl.dp && !csr.io.status.isa('d'-'a') || ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') || id_raddr2_illegal && id_ctrl.rxs2 ||