From 794c5b1b14b3534a336661c9bfed0077832aa921 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Tue, 30 Jul 2024 03:38:05 +0800 Subject: [PATCH] bug fix to io.out.bits.store --- src/main/scala/tile/FPU.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala index d2369639364..1affeb48769 100644 --- a/src/main/scala/tile/FPU.scala +++ b/src/main/scala/tile/FPU.scala @@ -477,7 +477,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetime val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) - io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1))): Seq[UInt])(tag) + io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U