From 71a1b6f4f3c22e005a383a3ec065965cc593c593 Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Sat, 7 Oct 2023 15:06:09 +0800 Subject: [PATCH 01/18] Fix the missing flow argument in TileLink/ToAXI4 (#3505) `flow` must be explicitly passed to `Queue.irrevocable` to avoid mismatching the arguments. --- src/main/scala/tilelink/ToAXI4.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tilelink/ToAXI4.scala b/src/main/scala/tilelink/ToAXI4.scala index 2c8ab84bb31..5aa6426f84a 100644 --- a/src/main/scala/tilelink/ToAXI4.scala +++ b/src/main/scala/tilelink/ToAXI4.scala @@ -145,8 +145,8 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String val depth = if (combinational) 1 else 2 val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params))) val out_w = Wire(chiselTypeOf(out.w)) - out.w :<>= Queue.irrevocable(out_w, entries=depth, combinational) - val queue_arw = Queue.irrevocable(out_arw, entries=depth, combinational) + out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational) + val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational) // Fan out the ARW channel to AR and AW out.ar.bits := queue_arw.bits From bb7415576471ca5082b7210546a675228dc585e9 Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Sat, 7 Oct 2023 23:07:23 +0800 Subject: [PATCH 02/18] Fix the missing DontCare in TileLink Edges/Delayer (#3504) * add DontCare for user/echo bits in Channel A/C/D * add DontCare for messages without any data payload --- src/main/scala/tilelink/Delayer.scala | 6 ++ src/main/scala/tilelink/Edges.scala | 86 ++++++++++++++++++--------- 2 files changed, 63 insertions(+), 29 deletions(-) diff --git a/src/main/scala/tilelink/Delayer.scala b/src/main/scala/tilelink/Delayer.scala index eb70bc5e4d5..58d08e4bc48 100644 --- a/src/main/scala/tilelink/Delayer.scala +++ b/src/main/scala/tilelink/Delayer.scala @@ -30,6 +30,8 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule anoise.size := LFSRNoiseMaker(anoise.params.sizeBits) anoise.source := LFSRNoiseMaker(anoise.params.sourceBits) anoise.address := LFSRNoiseMaker(anoise.params.addressBits) + anoise.user := DontCare + anoise.echo := DontCare anoise.mask := LFSRNoiseMaker(anoise.params.dataBits/8) anoise.data := LFSRNoiseMaker(anoise.params.dataBits) anoise.corrupt := LFSRNoiseMaker(1) @@ -50,6 +52,8 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule cnoise.size := LFSRNoiseMaker(cnoise.params.sizeBits) cnoise.source := LFSRNoiseMaker(cnoise.params.sourceBits) cnoise.address := LFSRNoiseMaker(cnoise.params.addressBits) + cnoise.user := DontCare + cnoise.echo := DontCare cnoise.data := LFSRNoiseMaker(cnoise.params.dataBits) cnoise.corrupt := LFSRNoiseMaker(1)(0) @@ -60,6 +64,8 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule dnoise.source := LFSRNoiseMaker(dnoise.params.sourceBits) dnoise.sink := LFSRNoiseMaker(dnoise.params.sinkBits) dnoise.denied := LFSRNoiseMaker(1)(0) + dnoise.user := DontCare + dnoise.echo := DontCare dnoise.data := LFSRNoiseMaker(dnoise.params.dataBits) dnoise.corrupt := LFSRNoiseMaker(1)(0) diff --git a/src/main/scala/tilelink/Edges.scala b/src/main/scala/tilelink/Edges.scala index 2c555c03ac2..ce34cbb98a0 100644 --- a/src/main/scala/tilelink/Edges.scala +++ b/src/main/scala/tilelink/Edges.scala @@ -345,14 +345,15 @@ class TLEdgeOut( require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) - a :#= DontCare a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress + a.user := DontCare + a.echo := DontCare a.mask := mask(toAddress, lgSize) - a.data := 0.U + a.data := DontCare a.corrupt := false.B (legal, a) } @@ -366,8 +367,10 @@ class TLEdgeOut( a.size := lgSize a.source := fromSource a.address := toAddress + a.user := DontCare + a.echo := DontCare a.mask := mask(toAddress, lgSize) - a.data := 0.U + a.data := DontCare a.corrupt := false.B (legal, a) } @@ -376,13 +379,14 @@ class TLEdgeOut( require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) - c :#= DontCare c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress - c.data := 0.U + c.user := DontCare + c.echo := DontCare + c.data := DontCare c.corrupt := false.B (legal, c) } @@ -391,12 +395,13 @@ class TLEdgeOut( require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) - c :#= DontCare c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress + c.user := DontCare + c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) @@ -410,13 +415,14 @@ class TLEdgeOut( def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) - c :#= DontCare c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress - c.data := 0.U + c.user := DontCare + c.echo := DontCare + c.data := DontCare c.corrupt := false.B c } @@ -426,12 +432,13 @@ class TLEdgeOut( def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) - c :#= DontCare c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress + c.user := DontCare + c.echo := DontCare c.data := data c.corrupt := corrupt c @@ -452,14 +459,15 @@ class TLEdgeOut( require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) - a :#= DontCare a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress + a.user := DontCare + a.echo := DontCare a.mask := mask(toAddress, lgSize) - a.data := 0.U + a.data := DontCare a.corrupt := false.B (legal, a) } @@ -471,12 +479,13 @@ class TLEdgeOut( require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) - a :#= DontCare a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress + a.user := DontCare + a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt @@ -490,12 +499,13 @@ class TLEdgeOut( require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) - a :#= DontCare a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress + a.user := DontCare + a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt @@ -506,12 +516,13 @@ class TLEdgeOut( require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) - a :#= DontCare a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress + a.user := DontCare + a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt @@ -522,12 +533,13 @@ class TLEdgeOut( require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) - a :#= DontCare a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress + a.user := DontCare + a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt @@ -538,14 +550,15 @@ class TLEdgeOut( require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) - a :#= DontCare a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress + a.user := DontCare + a.echo := DontCare a.mask := mask(toAddress, lgSize) - a.data := 0.U + a.data := DontCare a.corrupt := false.B (legal, a) } @@ -553,13 +566,14 @@ class TLEdgeOut( def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) - c :#= DontCare c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress - c.data := 0.U + c.user := DontCare + c.echo := DontCare + c.data := DontCare c.corrupt := false.B c } @@ -569,12 +583,13 @@ class TLEdgeOut( def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) - c :#= DontCare c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress + c.user := DontCare + c.echo := DontCare c.data := data c.corrupt := corrupt c @@ -583,13 +598,14 @@ class TLEdgeOut( def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) - c :#= DontCare c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress - c.data := 0.U + c.user := DontCare + c.echo := DontCare + c.data := DontCare c.corrupt := false.B c } @@ -620,7 +636,7 @@ class TLEdgeIn( b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) - b.data := 0.U + b.data := DontCare b.corrupt := false.B (legal, b) } @@ -634,7 +650,9 @@ class TLEdgeIn( d.source := toSource d.sink := fromSink d.denied := denied - d.data := 0.U + d.user := DontCare + d.echo := DontCare + d.data := DontCare d.corrupt := false.B d } @@ -648,6 +666,8 @@ class TLEdgeIn( d.source := toSource d.sink := fromSink d.denied := denied + d.user := DontCare + d.echo := DontCare d.data := data d.corrupt := corrupt d @@ -662,7 +682,9 @@ class TLEdgeIn( d.source := toSource d.sink := 0.U d.denied := denied - d.data := 0.U + d.user := DontCare + d.echo := DontCare + d.data := DontCare d.corrupt := false.B d } @@ -678,7 +700,7 @@ class TLEdgeIn( b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) - b.data := 0.U + b.data := DontCare b.corrupt := false.B (legal, b) } @@ -759,7 +781,7 @@ class TLEdgeIn( b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) - b.data := 0.U + b.data := DontCare b.corrupt := false.B (legal, b) } @@ -775,7 +797,9 @@ class TLEdgeIn( d.source := toSource d.sink := 0.U d.denied := denied - d.data := 0.U + d.user := DontCare + d.echo := DontCare + d.data := DontCare d.corrupt := false.B d } @@ -791,6 +815,8 @@ class TLEdgeIn( d.source := toSource d.sink := 0.U d.denied := denied + d.user := DontCare + d.echo := DontCare d.data := data d.corrupt := corrupt d @@ -807,7 +833,9 @@ class TLEdgeIn( d.source := toSource d.sink := 0.U d.denied := denied - d.data := 0.U + d.user := DontCare + d.echo := DontCare + d.data := DontCare d.corrupt := false.B d } From 4fed21e5fb15aab34a79c9854fa0cdd5a7b53db2 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Wed, 11 Oct 2023 09:34:06 +0800 Subject: [PATCH 03/18] Bump flake dependencies (#3506) * bump flake * remove legacy firtool option --- build.sc | 1 - flake.lock | 30 ++++++++++++++++++++++++------ flake.nix | 3 ++- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/build.sc b/build.sc index bfd9eb3e0e9..2cf8c7f02c0 100644 --- a/build.sc +++ b/build.sc @@ -141,7 +141,6 @@ trait Emulator extends Cross.Module2[String, String] { os.proc("firtool", generator.chirrtl().path, s"--annotation-file=${generator.chiselAnno().path}", - "-disable-infer-rw", "--disable-annotation-unknown", "-dedup", "-O=debug", diff --git a/flake.lock b/flake.lock index b0128cb6f91..e0cf2cdc548 100644 --- a/flake.lock +++ b/flake.lock @@ -1,12 +1,15 @@ { "nodes": { "flake-utils": { + "inputs": { + "systems": "systems" + }, "locked": { - "lastModified": 1676283394, - "narHash": "sha256-XX2f9c3iySLCw54rJ/CZs+ZK6IQy7GXNY4nSOyu2QG4=", + "lastModified": 1694529238, + "narHash": "sha256-zsNZZGTGnMOf9YpHKJqMSsa0dXbfmxeoJ7xHlrt+xmY=", "owner": "numtide", "repo": "flake-utils", - "rev": "3db36a8b464d0c4532ba1c7dda728f4576d6d073", + "rev": "ff7b65b44d01cf9ba6a71320833626af21126384", "type": "github" }, "original": { @@ -17,11 +20,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1676300157, - "narHash": "sha256-1HjRzfp6LOLfcj/HJHdVKWAkX9QRAouoh6AjzJiIerU=", + "lastModified": 1696019113, + "narHash": "sha256-X3+DKYWJm93DRSdC5M6K5hLqzSya9BjibtBsuARoPco=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "545c7a31e5dedea4a6d372712a18e00ce097d462", + "rev": "f5892ddac112a1e9b3612c39af1b72987ee5783a", "type": "github" }, "original": { @@ -36,6 +39,21 @@ "flake-utils": "flake-utils", "nixpkgs": "nixpkgs" } + }, + "systems": { + "locked": { + "lastModified": 1681028828, + "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=", + "owner": "nix-systems", + "repo": "default", + "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e", + "type": "github" + }, + "original": { + "owner": "nix-systems", + "repo": "default", + "type": "github" + } } }, "root": "root", diff --git a/flake.nix b/flake.nix index d9a19fcf541..28d32e91fb4 100644 --- a/flake.nix +++ b/flake.nix @@ -20,7 +20,8 @@ mill dtc verilator cmake ninja - python3 python3Packages.bootstrapped-pip + python3 + python3Packages.pip pkgsCross.riscv64-embedded.buildPackages.gcc pkgsCross.riscv64-embedded.buildPackages.gdb openocd From 2a190d2f1187c92f0a4f58ba9b8dc24feeafa746 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Tue, 17 Oct 2023 19:32:48 +0800 Subject: [PATCH 04/18] Add documentation to DCache about datapath of meta/data arbiter (#3510) --- src/main/scala/rocket/DCache.scala | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 308392acad1..f8b291c64c3 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -115,6 +115,17 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) + + /** Metadata Arbiter: + * 0: Tag update on reset + * 1: Tag update on ECC error + * 2: Tag update on hit + * 3: Tag update on refill + * 4: Tag update on release + * 5: Tag update on flush + * 6: Tag update on probe + * 7: Tag update on CPU request + */ val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( @@ -126,6 +137,12 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { // data val data = Module(new DCacheDataArray) + /** Data Arbiter + * 0: data from pending store buffer + * 1: data from TL-D refill + * 2: release to TL-A + * 3: hit path to CPU + */ val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits From b47fdf9b2781f2d0ca7b413674abe797ee745323 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 1 Nov 2023 09:36:04 -0700 Subject: [PATCH 05/18] Fix RoCCCSRIO bidir --- src/main/scala/tile/RocketTile.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 2527e135e1d..930d803e392 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -185,7 +185,7 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer) core.io.rocc.resp <> respArb.get.io.out core.io.rocc.busy <> (cmdRouter.get.io.busy || outer.roccs.map(_.module.io.busy).reduce(_ || _)) core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ || _) - (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 := t._1 } + (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 <> t._1 } } else { // tie off core.io.rocc.cmd.ready := false.B From 8907e63b92e67bde53eb159ce6730806a5427b04 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Fri, 3 Nov 2023 01:37:03 +0800 Subject: [PATCH 06/18] Remove Chisel 3.6 support (#3515) --- build.sc | 1 - 1 file changed, 1 deletion(-) diff --git a/build.sc b/build.sc index 2cf8c7f02c0..4442891b0e7 100644 --- a/build.sc +++ b/build.sc @@ -10,7 +10,6 @@ object v { val scala = "2.13.10" // the first version in this Map is the mainly supported version which will be used to run tests val chiselCrossVersions = Map( - "3.6.0" -> (ivy"edu.berkeley.cs::chisel3:3.6.0", ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0"), "5.0.0" -> (ivy"org.chipsalliance::chisel:5.0.0", ivy"org.chipsalliance:::chisel-plugin:5.0.0"), ) val mainargs = ivy"com.lihaoyi::mainargs:0.5.0" From b2b78fd645de215783fc14d2af9e62c5d8b4c751 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 3 Nov 2023 12:02:27 -0700 Subject: [PATCH 07/18] Add DelayQueue variations --- src/main/scala/util/DelayQueue.scala | 61 ++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 src/main/scala/util/DelayQueue.scala diff --git a/src/main/scala/util/DelayQueue.scala b/src/main/scala/util/DelayQueue.scala new file mode 100644 index 00000000000..831d70e3207 --- /dev/null +++ b/src/main/scala/util/DelayQueue.scala @@ -0,0 +1,61 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.util + +import chisel3._ +import chisel3.util._ + +class DelayQueue[T <: Data](gen: T, entries: Int) extends Module { + val io = IO(new Bundle { + val enq = Flipped(DecoupledIO(gen)) + val deq = DecoupledIO(gen) + val timer = Input(UInt()) + val delay = Input(UInt()) + }) + + val q = Module(new Queue(new Bundle { + val data = gen + val time = UInt(io.timer.getWidth.W) + }, entries, flow=true)) + + val delay_r = RegInit(0.U(io.delay.getWidth.W)) + when (delay_r =/= io.delay) { + delay_r := io.delay + assert(q.io.count == 0, "Undefined behavior when delay is changed while queue has elements.") + } + + q.io.enq.bits.data := io.enq.bits + q.io.enq.bits.time := io.timer + q.io.enq.valid := io.enq.fire + io.enq.ready := q.io.enq.ready + + io.deq.bits := q.io.deq.bits.data + io.deq.valid := q.io.deq.valid && ((io.timer - q.io.deq.bits.time) >= delay_r) + q.io.deq.ready := io.deq.fire +} + +object DelayQueue { + def apply[T <: Data](source: DecoupledIO[T], timer: UInt, delay: UInt, depth: Int): DecoupledIO[T] = { + val delayQueue = Module(new DelayQueue(chiselTypeOf(source.bits), depth)) + delayQueue.io.enq <> source + delayQueue.io.timer := timer + delayQueue.io.delay := delay + delayQueue.io.deq + } + + def apply[T <: Data](source: DecoupledIO[T], timerWidth: Int, delay: UInt, depth: Int): DecoupledIO[T] = { + val timer = RegInit(0.U(timerWidth.W)) + timer := timer + 1.U + apply(source, timer, delay, depth) + } + + def apply[T <: Data](source: DecoupledIO[T], delay: Int): DecoupledIO[T] = { + val mDelay = delay.max(1) + apply(source, (1 + log2Ceil(mDelay)), delay.U, mDelay) + } + + def apply[T <: Data](source: DecoupledIO[T], delay: UInt, maxDelay: Int = 4096): DecoupledIO[T] = { + val mDelay = maxDelay.max(1) + apply(source, (1 + log2Ceil(mDelay)), delay, mDelay) + } +} From 4dc63059a2459e70cd21cdf5c563d85c45956c1a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 6 Nov 2023 17:48:43 -0800 Subject: [PATCH 08/18] Add docstrings --- src/main/scala/util/DelayQueue.scala | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/src/main/scala/util/DelayQueue.scala b/src/main/scala/util/DelayQueue.scala index 831d70e3207..cdfa2f50743 100644 --- a/src/main/scala/util/DelayQueue.scala +++ b/src/main/scala/util/DelayQueue.scala @@ -5,6 +5,16 @@ package freechips.rocketchip.util import chisel3._ import chisel3.util._ +/** A queue that delays elements by a certain cycle count. + * + * @param gen queue element type + * @param entries queue size + * + * @param enq enqueue + * @param deq dequeue + * @param timer cycle count timer + * @param entries cycle delay + */ class DelayQueue[T <: Data](gen: T, entries: Int) extends Module { val io = IO(new Bundle { val enq = Flipped(DecoupledIO(gen)) @@ -35,6 +45,13 @@ class DelayQueue[T <: Data](gen: T, entries: Int) extends Module { } object DelayQueue { + /** Helper to connect a delay queue. + * + * @param source decoupled queue input + * @param timer cycle count timer + * @param delay cycle delay + * @param depth queue size + */ def apply[T <: Data](source: DecoupledIO[T], timer: UInt, delay: UInt, depth: Int): DecoupledIO[T] = { val delayQueue = Module(new DelayQueue(chiselTypeOf(source.bits), depth)) delayQueue.io.enq <> source @@ -43,17 +60,35 @@ object DelayQueue { delayQueue.io.deq } + /** Helper to connect a delay queue and instantiate a timer to keep track of cycle count. + * + * @param source decoupled queue input + * @param timerWidth width of cycle count timer + * @param delay cycle delay + * @param depth queue size + */ def apply[T <: Data](source: DecoupledIO[T], timerWidth: Int, delay: UInt, depth: Int): DecoupledIO[T] = { val timer = RegInit(0.U(timerWidth.W)) timer := timer + 1.U apply(source, timer, delay, depth) } + /** Helper to connect a delay queue that delays elements by a statically defined cycle count. + * + * @param source decoupled queue input + * @param delay static cycle delay + */ def apply[T <: Data](source: DecoupledIO[T], delay: Int): DecoupledIO[T] = { val mDelay = delay.max(1) apply(source, (1 + log2Ceil(mDelay)), delay.U, mDelay) } + /** Helper to connect a delay queue that delays elements by a dynamically set cycle count. + * + * @param source decoupled queue input + * @param delay cycle delay + * @param maxDelay maximum cycle delay + */ def apply[T <: Data](source: DecoupledIO[T], delay: UInt, maxDelay: Int = 4096): DecoupledIO[T] = { val mDelay = maxDelay.max(1) apply(source, (1 + log2Ceil(mDelay)), delay, mDelay) From 5087e53235000f20922656498912742420bf4e48 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Tue, 14 Nov 2023 09:49:44 +0800 Subject: [PATCH 09/18] Fix r_pte update condition when S2 PTE cache hit (#3525) (#3526) Co-authored-by: Sihao Liu --- src/main/scala/rocket/PTW.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala index 876dfe478e2..f0338807d3d 100644 --- a/src/main/scala/rocket/PTW.scala +++ b/src/main/scala/rocket/PTW.scala @@ -677,8 +677,10 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()( r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error, l2_pte, + // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp + Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem - Mux(state === s_req && !stage2_pte_cache_hit && pte_cache_hit, makePTE(pte_cache_data, l2_pte), + Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte @@ -687,7 +689,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()( Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), - r_pte))))))) + r_pte)))))))) when (l2_hit && !l2_error) { assert(state === s_req || state === s_wait1) From 180e4bc0c55215d2b433fcd6a9ce810abf9daff2 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Wed, 15 Nov 2023 14:27:49 +0800 Subject: [PATCH 10/18] add sonatype snapshots repo for test chisel releases (#3527) --- build.sc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/build.sc b/build.sc index 4442891b0e7..f139ab528d5 100644 --- a/build.sc +++ b/build.sc @@ -15,6 +15,9 @@ object v { val mainargs = ivy"com.lihaoyi::mainargs:0.5.0" val json4sJackson = ivy"org.json4s::json4s-jackson:4.0.5" val scalaReflect = ivy"org.scala-lang:scala-reflect:${scala}" + val sonatypesSnapshots = Seq( + MavenRepository("https://s01.oss.sonatype.org/content/repositories/snapshots") + ) } object macros extends Macros @@ -47,6 +50,8 @@ trait Hardfloat def chiselIvy = Some(v.chiselCrossVersions(crossValue)._1) def chiselPluginIvy = Some(v.chiselCrossVersions(crossValue)._2) + + def repositoriesTask = T.task(super.repositoriesTask() ++ v.sonatypesSnapshots) } object cde extends CDE @@ -89,6 +94,8 @@ trait RocketChip def mainargsIvy = v.mainargs def json4sJacksonIvy = v.json4sJackson + + def repositoriesTask = T.task(super.repositoriesTask() ++ v.sonatypesSnapshots) } trait RocketChipPublishModule From 1101d212fc7f72509628dcf587efb6d29a46d43f Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sun, 24 Sep 2023 22:44:03 +0800 Subject: [PATCH 11/18] remove torture --- .gitmodules | 3 --- torture | 1 - 2 files changed, 4 deletions(-) delete mode 160000 torture diff --git a/.gitmodules b/.gitmodules index 77819d7f768..59885c0c39d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,6 @@ [submodule "hardfloat"] path = hardfloat url = https://github.com/ucb-bar/berkeley-hardfloat.git -[submodule "torture"] - path = torture - url = https://github.com/ucb-bar/riscv-torture.git [submodule "cde"] path = cde url = https://github.com/chipsalliance/cde.git diff --git a/torture b/torture deleted file mode 160000 index 99d8b2b441e..00000000000 --- a/torture +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 99d8b2b441ecaa18b852505bb7718ee04e2753f5 From b0a3b663916c9f9e4f60ca77a519c2abdc272e48 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sun, 24 Sep 2023 22:48:15 +0800 Subject: [PATCH 12/18] move cde and hardfloat to dependencies folder --- .gitmodules | 8 ++++---- build.sc | 12 ++++++------ cde => dependencies/cde | 0 hardfloat => dependencies/hardfloat | 0 4 files changed, 10 insertions(+), 10 deletions(-) rename cde => dependencies/cde (100%) rename hardfloat => dependencies/hardfloat (100%) diff --git a/.gitmodules b/.gitmodules index 59885c0c39d..b2c07ea2978 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,6 @@ -[submodule "hardfloat"] - path = hardfloat +[submodule "dependencies/hardfloat"] + path = dependencies/hardfloat url = https://github.com/ucb-bar/berkeley-hardfloat.git -[submodule "cde"] - path = cde +[submodule "dependencies/cde"] + path = dependencies/cde url = https://github.com/chipsalliance/cde.git diff --git a/build.sc b/build.sc index f139ab528d5..d583e56769a 100644 --- a/build.sc +++ b/build.sc @@ -2,8 +2,8 @@ import mill._ import mill.scalalib._ import mill.scalalib.publish._ import coursier.maven.MavenRepository -import $file.hardfloat.common -import $file.cde.common +import $file.dependencies.hardfloat.common +import $file.dependencies.cde.common import $file.common object v { @@ -35,13 +35,13 @@ trait Macros object hardfloat extends mill.define.Cross[Hardfloat](v.chiselCrossVersions.keys.toSeq) trait Hardfloat - extends millbuild.hardfloat.common.HardfloatModule + extends millbuild.dependencies.hardfloat.common.HardfloatModule with RocketChipPublishModule with Cross.Module[String] { def scalaVersion: T[String] = T(v.scala) - override def millSourcePath = os.pwd / "hardfloat" / "hardfloat" + override def millSourcePath = os.pwd / "dependencies" / "hardfloat" / "hardfloat" def chiselModule = None @@ -57,13 +57,13 @@ trait Hardfloat object cde extends CDE trait CDE - extends millbuild.cde.common.CDEModule + extends millbuild.dependencies.cde.common.CDEModule with RocketChipPublishModule with ScalaModule { def scalaVersion: T[String] = T(v.scala) - override def millSourcePath = os.pwd / "cde" / "cde" + override def millSourcePath = os.pwd / "dependencies" / "cde" / "cde" } object rocketchip extends Cross[RocketChip](v.chiselCrossVersions.keys.toSeq) diff --git a/cde b/dependencies/cde similarity index 100% rename from cde rename to dependencies/cde diff --git a/hardfloat b/dependencies/hardfloat similarity index 100% rename from hardfloat rename to dependencies/hardfloat From 7b0195575c18d9e7fc06b50ab8b09645b26029bd Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Mon, 2 Oct 2023 08:39:56 +0800 Subject: [PATCH 13/18] add support to build chisel from source --- .gitmodules | 3 +++ build.sc | 31 ++++++++++++++++++++++--------- dependencies/chisel | 1 + 3 files changed, 26 insertions(+), 9 deletions(-) create mode 160000 dependencies/chisel diff --git a/.gitmodules b/.gitmodules index b2c07ea2978..fa1f58748ff 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,3 +4,6 @@ [submodule "dependencies/cde"] path = dependencies/cde url = https://github.com/chipsalliance/cde.git +[submodule "dependencies/chisel"] + path = dependencies/chisel + url = https://github.com/chipsalliance/chisel.git diff --git a/build.sc b/build.sc index d583e56769a..3336121e20e 100644 --- a/build.sc +++ b/build.sc @@ -4,13 +4,16 @@ import mill.scalalib.publish._ import coursier.maven.MavenRepository import $file.dependencies.hardfloat.common import $file.dependencies.cde.common +import $file.dependencies.chisel.build import $file.common object v { - val scala = "2.13.10" + val scala = "2.13.12" // the first version in this Map is the mainly supported version which will be used to run tests val chiselCrossVersions = Map( "5.0.0" -> (ivy"org.chipsalliance::chisel:5.0.0", ivy"org.chipsalliance:::chisel-plugin:5.0.0"), + // build from project from source + "source" -> (ivy"org.chipsalliance::chisel:99", ivy"org.chipsalliance:::chisel-plugin:99"), ) val mainargs = ivy"com.lihaoyi::mainargs:0.5.0" val json4sJackson = ivy"org.json4s::json4s-jackson:4.0.5" @@ -20,6 +23,16 @@ object v { ) } +// Build form source only for dev +object chisel extends Chisel + +trait Chisel + extends millbuild.dependencies.chisel.build.Chisel { + def crossValue = v.scala + override def millSourcePath = os.pwd / "dependencies" / "chisel" + def scalaVersion = T(v.scala) +} + object macros extends Macros trait Macros @@ -43,13 +56,13 @@ trait Hardfloat override def millSourcePath = os.pwd / "dependencies" / "hardfloat" / "hardfloat" - def chiselModule = None + def chiselModule = Option.when(crossValue == "source")(chisel) - def chiselPluginJar = None + def chiselPluginJar = T(Option.when(crossValue == "source")(chisel.pluginModule.jar())) - def chiselIvy = Some(v.chiselCrossVersions(crossValue)._1) + def chiselIvy = Option.when(crossValue != "source")(v.chiselCrossVersions(crossValue)._1) - def chiselPluginIvy = Some(v.chiselCrossVersions(crossValue)._2) + def chiselPluginIvy = Option.when(crossValue != "source")(v.chiselCrossVersions(crossValue)._2) def repositoriesTask = T.task(super.repositoriesTask() ++ v.sonatypesSnapshots) } @@ -77,13 +90,13 @@ trait RocketChip override def millSourcePath = super.millSourcePath / os.up - def chiselModule = None + def chiselModule = Option.when(crossValue == "source")(chisel) - def chiselPluginJar = None + def chiselPluginJar = T(Option.when(crossValue == "source")(chisel.pluginModule.jar())) - def chiselIvy = Some(v.chiselCrossVersions(crossValue)._1) + def chiselIvy = Option.when(crossValue != "source")(v.chiselCrossVersions(crossValue)._1) - def chiselPluginIvy = Some(v.chiselCrossVersions(crossValue)._2) + def chiselPluginIvy = Option.when(crossValue != "source")(v.chiselCrossVersions(crossValue)._2) def macrosModule = macros diff --git a/dependencies/chisel b/dependencies/chisel new file mode 160000 index 00000000000..e3bcc90db37 --- /dev/null +++ b/dependencies/chisel @@ -0,0 +1 @@ +Subproject commit e3bcc90db37f1aec9f8048813f4f0666098d9bee From 1751e0cb4f136ce607844c5fcdc602b46ede257f Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Thu, 16 Nov 2023 14:58:50 +0800 Subject: [PATCH 14/18] Bump to Chisel 5.1 --- build.sc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sc b/build.sc index 3336121e20e..f417177e4a7 100644 --- a/build.sc +++ b/build.sc @@ -11,7 +11,7 @@ object v { val scala = "2.13.12" // the first version in this Map is the mainly supported version which will be used to run tests val chiselCrossVersions = Map( - "5.0.0" -> (ivy"org.chipsalliance::chisel:5.0.0", ivy"org.chipsalliance:::chisel-plugin:5.0.0"), + "5.1.0" -> (ivy"org.chipsalliance::chisel:5.1.0", ivy"org.chipsalliance:::chisel-plugin:5.1.0"), // build from project from source "source" -> (ivy"org.chipsalliance::chisel:99", ivy"org.chipsalliance:::chisel-plugin:99"), ) From 218ae0aac0e9044cc5105158eda62e9638764f4a Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Fri, 17 Nov 2023 00:13:27 +0800 Subject: [PATCH 15/18] Remove Scalar Crypto and BitManip --- .github/workflows/mill-ci.yml | 2 +- build.sc | 7 +- scripts/arch-test/emulator/riscof_emulator.py | 24 - scripts/arch-test/spike/riscof_spike.py | 24 - src/main/scala/rocket/ABLU.scala | 365 -------- src/main/scala/rocket/ALU.scala | 72 +- src/main/scala/rocket/BitManipCrypto.scala | 59 -- src/main/scala/rocket/CSR.scala | 2 - src/main/scala/rocket/CryptoNIST.scala | 261 ------ src/main/scala/rocket/CryptoSM.scala | 56 -- src/main/scala/rocket/IDecode.scala | 803 ++++++------------ src/main/scala/rocket/RocketCore.scala | 57 +- src/main/scala/subsystem/Configs.scala | 32 - src/main/scala/system/Configs.scala | 3 - src/main/scala/tile/BaseTile.scala | 5 - src/main/scala/tile/Core.scala | 9 - src/main/scala/util/BarrelShifter.scala | 94 -- src/main/scala/util/SBox.scala | 344 -------- 18 files changed, 269 insertions(+), 1950 deletions(-) delete mode 100644 src/main/scala/rocket/ABLU.scala delete mode 100644 src/main/scala/rocket/CryptoSM.scala delete mode 100644 src/main/scala/util/SBox.scala diff --git a/.github/workflows/mill-ci.yml b/.github/workflows/mill-ci.yml index 5ffecd16589..0d03a2eb5ae 100644 --- a/.github/workflows/mill-ci.yml +++ b/.github/workflows/mill-ci.yml @@ -72,7 +72,7 @@ jobs: if: ${{ false }} # disable for now, I prefer adding firesim-based simulation framework in the future. strategy: matrix: - config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei", "BitManipCryptoConfig,64,RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh", "BitManipCrypto32Config,32,RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"] + config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei"] steps: - uses: actions/checkout@v2 with: diff --git a/build.sc b/build.sc index f417177e4a7..b19e7a8927d 100644 --- a/build.sc +++ b/build.sc @@ -203,7 +203,7 @@ trait Emulator extends Cross.Module2[String, String] { "debug_rob.cc", "emulator.cc", "remote_bitbang.cc", - ).map(c => PathRef(csrcDir().path / c)) + ).map(c => PathRef(csrcDir().path / c)) } def CMakeListsString = T { @@ -313,8 +313,6 @@ object emulator extends Cross[Emulator]( // ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"), ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"), - ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig"), - ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config"), ) object `runnable-riscv-test` extends mill.Cross[RiscvTest]( @@ -402,9 +400,6 @@ object `runnable-arch-test` extends mill.Cross[ArchTest]( // For CI within reasonable time ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultConfig", "64", "RV64IMACZicsr_Zifencei"), ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "32", "RV32IMACZicsr_Zifencei"), - - ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig", "64", "RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"), - ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config", "32", "RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"), ) object `runnable-jtag-dtm-test` extends mill.Cross[JTAGDTMTest]( diff --git a/scripts/arch-test/emulator/riscof_emulator.py b/scripts/arch-test/emulator/riscof_emulator.py index 82658c725a5..d0ea02253a1 100644 --- a/scripts/arch-test/emulator/riscof_emulator.py +++ b/scripts/arch-test/emulator/riscof_emulator.py @@ -111,30 +111,6 @@ def build(self, isa_yaml, platform_yaml): self.isa += '_Zicsr' if "Zifencei" in ispec["ISA"]: self.isa += '_Zifencei' - if "Zba" in ispec["ISA"]: - self.isa += '_Zba' - if "Zbb" in ispec["ISA"]: - self.isa += '_Zbb' - if "Zbc" in ispec["ISA"]: - self.isa += '_Zbc' - if "Zbkb" in ispec["ISA"]: - self.isa += '_Zbkb' - if "Zbkc" in ispec["ISA"]: - self.isa += '_Zbkc' - if "Zbkx" in ispec["ISA"]: - self.isa += '_Zbkx' - if "Zbs" in ispec["ISA"]: - self.isa += '_Zbs' - if "Zknd" in ispec["ISA"]: - self.isa += '_Zknd' - if "Zkne" in ispec["ISA"]: - self.isa += '_Zkne' - if "Zknh" in ispec["ISA"]: - self.isa += '_Zknh' - if "Zksed" in ispec["ISA"]: - self.isa += '_Zksed' - if "Zksh" in ispec["ISA"]: - self.isa += '_Zksh' #TODO: The following assumes you are using the riscv-gcc toolchain. If # not please change appropriately diff --git a/scripts/arch-test/spike/riscof_spike.py b/scripts/arch-test/spike/riscof_spike.py index 1186c5cb5e8..5bb68dd0281 100644 --- a/scripts/arch-test/spike/riscof_spike.py +++ b/scripts/arch-test/spike/riscof_spike.py @@ -111,30 +111,6 @@ def build(self, isa_yaml, platform_yaml): self.isa += '_Zicsr' if "Zifencei" in ispec["ISA"]: self.isa += '_Zifencei' - if "Zba" in ispec["ISA"]: - self.isa += '_Zba' - if "Zbb" in ispec["ISA"]: - self.isa += '_Zbb' - if "Zbc" in ispec["ISA"]: - self.isa += '_Zbc' - if "Zbkb" in ispec["ISA"]: - self.isa += '_Zbkb' - if "Zbkc" in ispec["ISA"]: - self.isa += '_Zbkc' - if "Zbkx" in ispec["ISA"]: - self.isa += '_Zbkx' - if "Zbs" in ispec["ISA"]: - self.isa += '_Zbs' - if "Zknd" in ispec["ISA"]: - self.isa += '_Zknd' - if "Zkne" in ispec["ISA"]: - self.isa += '_Zkne' - if "Zknh" in ispec["ISA"]: - self.isa += '_Zknh' - if "Zksed" in ispec["ISA"]: - self.isa += '_Zksed' - if "Zksh" in ispec["ISA"]: - self.isa += '_Zksh' #TODO: The following assumes you are using the riscv-gcc toolchain. If # not please change appropriately diff --git a/src/main/scala/rocket/ABLU.scala b/src/main/scala/rocket/ABLU.scala deleted file mode 100644 index d6dcef1cdc8..00000000000 --- a/src/main/scala/rocket/ABLU.scala +++ /dev/null @@ -1,365 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package freechips.rocketchip.rocket - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile.CoreModule - -// These are for the ABLU unit, which uses an alternate function encoding -class ABLUFN extends ALUFN -{ - override val SZ_ALU_FN = 39 - override def FN_X = BitPat("b??_???_????_????_????__????__??_????_????_????_????") - override def FN_ADD = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_0001".U(SZ_ALU_FN.W) - override def FN_SL = "b00_000_0000_1100_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W) - override def FN_SEQ = "b00_100_0000_0000_0000__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W) - override def FN_SNE = "b00_110_0000_0000_0000__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W) - override def FN_XOR = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_1000".U(SZ_ALU_FN.W) - override def FN_SR = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W) - override def FN_OR = "b00_000_0000_0000_0000__0001__00_0000_0000_0001_0000".U(SZ_ALU_FN.W) - override def FN_AND = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_0100".U(SZ_ALU_FN.W) - override def FN_SUB = "b00_000_0000_0000_0011__0001__00_0000_0000_0000_0001".U(SZ_ALU_FN.W) - override def FN_SRA = "b00_000_0000_0001_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W) - override def FN_SLT = "b00_000_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W) - override def FN_SGE = "b00_010_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W) - override def FN_SLTU = "b00_001_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W) - override def FN_SGEU = "b00_011_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W) - - // from Zb - // Zba: UW is encoded here becuase it is DW_64 - override def FN_ADDUW = "b00_000_0000_0000_1000__0001__00_0000_0000_0000_0001".U(SZ_ALU_FN.W) - override def FN_SLLIUW = "b00_000_0000_1100_1000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W) - override def FN_SH1ADD = "b00_000_0000_0000_0000__0010__00_0000_0000_0000_0001".U(SZ_ALU_FN.W) - override def FN_SH1ADDUW = "b00_000_0000_0000_1000__0010__00_0000_0000_0000_0001".U(SZ_ALU_FN.W) - override def FN_SH2ADD = "b00_000_0000_0000_0000__0100__00_0000_0000_0000_0001".U(SZ_ALU_FN.W) - override def FN_SH2ADDUW = "b00_000_0000_0000_1000__0100__00_0000_0000_0000_0001".U(SZ_ALU_FN.W) - override def FN_SH3ADD = "b00_000_0000_0000_0000__1000__00_0000_0000_0000_0001".U(SZ_ALU_FN.W) - override def FN_SH3ADDUW = "b00_000_0000_0000_1000__1000__00_0000_0000_0000_0001".U(SZ_ALU_FN.W) - // Zbb - override def FN_ROR = "b00_000_0000_0010_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W) - override def FN_ROL = "b00_000_0000_1110_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W) - override def FN_ANDN = "b00_000_0000_0000_0010__0001__00_0000_0000_0000_0100".U(SZ_ALU_FN.W) - override def FN_ORN = "b00_000_0000_0000_0010__0001__00_0000_0000_0001_0000".U(SZ_ALU_FN.W) - override def FN_XNOR = "b00_000_0000_0000_0010__0001__00_0000_0000_0000_1000".U(SZ_ALU_FN.W) - override def FN_REV8 = "b00_000_0000_0000_0000__0001__00_0001_0000_0000_0000".U(SZ_ALU_FN.W) - override def FN_ORCB = "b10_000_0000_0000_0000__0001__00_0010_0000_0000_0000".U(SZ_ALU_FN.W) - override def FN_SEXTB = "b00_000_0000_0000_0000__0001__00_0000_1000_0000_0000".U(SZ_ALU_FN.W) - override def FN_SEXTH = "b01_000_0000_0000_0000__0001__00_0000_0100_0000_0000".U(SZ_ALU_FN.W) - override def FN_ZEXTH = "b00_000_0000_0000_0000__0001__00_0000_0100_0000_0000".U(SZ_ALU_FN.W) - override def FN_MAX = "b00_000_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W) - override def FN_MAXU = "b00_001_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W) - override def FN_MIN = "b00_010_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W) - override def FN_MINU = "b00_011_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W) - override def FN_CPOP = "b00_000_0000_0000_0000__0001__00_0000_0001_0000_0000".U(SZ_ALU_FN.W) - override def FN_CLZ = "b00_000_1101_1110_0000__0001__00_0000_0010_0000_0000".U(SZ_ALU_FN.W) - override def FN_CTZ = "b00_000_1101_0000_0000__0001__00_0000_0010_0000_0000".U(SZ_ALU_FN.W) - // Zbs - override def FN_BCLR = "b00_000_1110_1000_0100__0001__00_0000_0000_0000_0100".U(SZ_ALU_FN.W) - override def FN_BEXT = "b00_000_1000_1000_0100__0001__00_0000_0000_0010_0000".U(SZ_ALU_FN.W) - override def FN_BINV = "b00_000_1000_1000_0100__0001__00_0000_0000_0000_1000".U(SZ_ALU_FN.W) - override def FN_BSET = "b00_000_1000_1000_0100__0001__00_0000_0000_0001_0000".U(SZ_ALU_FN.W) - // Zbk - override def FN_BREV8 = "b00_000_0000_0000_0000__0001__00_0010_0000_0000_0000".U(SZ_ALU_FN.W) - override def FN_PACK = "b00_000_0000_0000_0000__0001__00_0100_0000_0000_0000".U(SZ_ALU_FN.W) - override def FN_PACKH = "b00_000_0000_0000_0000__0001__00_1000_0000_0000_0000".U(SZ_ALU_FN.W) - override def FN_ZIP = "b00_000_0000_0000_0000__0001__01_0000_0000_0000_0000".U(SZ_ALU_FN.W) - override def FN_UNZIP = "b00_000_0000_0000_0000__0001__10_0000_0000_0000_0000".U(SZ_ALU_FN.W) - def SZ_ZBK_FN = 5 - override def FN_CLMUL = "b00001".U(SZ_ZBK_FN.W) // These use the BitManipCrypto FU, not ABLU - override def FN_CLMULR = "b00010".U(SZ_ZBK_FN.W) - override def FN_CLMULH = "b00100".U(SZ_ZBK_FN.W) - override def FN_XPERM8 = "b01000".U(SZ_ZBK_FN.W) - override def FN_XPERM4 = "b10000".U(SZ_ZBK_FN.W) - // Zkn: These use the CryptoNIST unit - def SZ_ZKN_FN = 17 - override def FN_AES_DS = "b0010__0001__0_0000_0001".U(SZ_ZKN_FN.W) - override def FN_AES_DSM = "b0000__0010__0_0000_0001".U(SZ_ZKN_FN.W) - override def FN_AES_ES = "b0011__0001__0_0000_0001".U(SZ_ZKN_FN.W) - override def FN_AES_ESM = "b0001__0010__0_0000_0001".U(SZ_ZKN_FN.W) - override def FN_AES_IM = "b1000__0010__0_0000_0001".U(SZ_ZKN_FN.W) - override def FN_AES_KS1 = "b0101__0100__0_0000_0001".U(SZ_ZKN_FN.W) - override def FN_AES_KS2 = "b0000__1000__0_0000_0001".U(SZ_ZKN_FN.W) - override def FN_SHA256_SIG0 = "b0000__0001__0_0000_0010".U(SZ_ZKN_FN.W) - override def FN_SHA256_SIG1 = "b0000__0001__0_0000_0100".U(SZ_ZKN_FN.W) - override def FN_SHA256_SUM0 = "b0000__0001__0_0000_1000".U(SZ_ZKN_FN.W) - override def FN_SHA256_SUM1 = "b0000__0001__0_0001_0000".U(SZ_ZKN_FN.W) - override def FN_SHA512_SIG0 = "b0000__0001__0_0010_0000".U(SZ_ZKN_FN.W) - override def FN_SHA512_SIG1 = "b0000__0001__0_0100_0000".U(SZ_ZKN_FN.W) - override def FN_SHA512_SUM0 = "b0000__0001__0_1000_0000".U(SZ_ZKN_FN.W) - override def FN_SHA512_SUM1 = "b0000__0001__1_0000_0000".U(SZ_ZKN_FN.W) - // Zks: Thses use the CryptoSM unit - def SZ_ZKS_FN = 4 - override def FN_SM4ED = "b01_01".U(SZ_ZKS_FN.W) - override def FN_SM4KS = "b00_01".U(SZ_ZKS_FN.W) - override def FN_SM3P0 = "b10_10".U(SZ_ZKS_FN.W) - override def FN_SM3P1 = "b00_10".U(SZ_ZKS_FN.W) - - - override def FN_DIV = FN_XOR - override def FN_DIVU = FN_SR - override def FN_REM = FN_OR - override def FN_REMU = FN_AND - - override def FN_MUL = FN_ADD - override def FN_MULH = FN_SL - override def FN_MULHSU = FN_SEQ - override def FN_MULHU = FN_SNE - - // not implemented functions for this fn - override def isMulFN(fn: UInt, cmp: UInt) = ??? - override def isCmp(cmd: UInt) = ??? - override def cmpUnsigned(cmd: UInt) = ??? - override def cmpInverted(cmd: UInt) = ??? - override def cmpEq(cmd: UInt) = ??? - - override def isSub(cmd: UInt) = cmd(22) - def isIn2Inv(cmd: UInt) = cmd(23) - def isZBS(cmd: UInt) = cmd(24) - def isUW(cmd: UInt) = cmd(25) - def isSRA(cmd: UInt) = cmd(26) - def isRotate(cmd: UInt) = cmd(27) - def isLeft(cmd: UInt) = cmd(28) - def isLeftZBS(cmd: UInt) = cmd(29) - def isCZ(cmd: UInt) = cmd(30) - def isBCLR(cmd: UInt) = cmd(31) - def isCZBCLR(cmd: UInt) = cmd(32) - def isCZZBS(cmd: UInt) = cmd(33) - def isUnsigned(cmd: UInt) = cmd(34) - def isInverted(cmd: UInt) = cmd(35) - def isSEQSNE(cmd: UInt) = cmd(36) - def isSEXT(cmd: UInt) = cmd(37) - def isORC(cmd: UInt) = cmd(38) - def shxadd1H(cmd: UInt) = cmd(21,18) - def out1H(cmd: UInt) = cmd(17,0) - // Zbk - def isClmul(cmd: UInt) = cmd(0) - def zbkOut1H(cmd: UInt) = cmd(4,0) - // Zkn - def isEnc(cmd: UInt) = cmd(13) - def isNotMix(cmd: UInt) = cmd(14) - override def isKs1(cmd: UInt) = cmd(15) - def isIm(cmd: UInt) = cmd(16) - def aes1H(cmd: UInt) = cmd(12,9) - def zknOut1H(cmd: UInt) = cmd(8,0) - // Zks - def isEd(cmd: UInt) = cmd(2) - def isP0(cmd: UInt) = cmd(3) - def zksOut1H(cmd: UInt) = cmd(1,0) -} - -object ABLUFN { - def apply() = new ABLUFN -} - -class ABLU(implicit p: Parameters) extends AbstractALU(new ABLUFN)(p) { - val isSub = aluFn.isSub(io.fn) - val isIn2Inv = aluFn.isIn2Inv(io.fn) - val isZBS = aluFn.isZBS(io.fn) - val isUW = aluFn.isUW(io.fn) - val isSRA = aluFn.isSRA(io.fn) - val isRotate = aluFn.isRotate(io.fn) - val isLeft = aluFn.isLeft(io.fn) - val isLeftZBS = aluFn.isLeftZBS(io.fn) - val isCZ = aluFn.isCZ(io.fn) - val isBCLR = aluFn.isBCLR(io.fn) - val isCZBCLR = aluFn.isCZBCLR(io.fn) - val isCZZBS = aluFn.isCZZBS(io.fn) - val isUnsigned = aluFn.isUnsigned(io.fn) - val isInverted = aluFn.isInverted(io.fn) - val isSEQSNE = aluFn.isSEQSNE(io.fn) - val isSEXT = aluFn.isSEXT(io.fn) - val isORC = aluFn.isORC(io.fn) - val shxadd1H = aluFn.shxadd1H(io.fn) - val out1H = aluFn.out1H(io.fn) - - // process input - // used by SUB, ANDN, ORN, XNOR - val in2_inv = Mux(isIn2Inv, ~io.in2, io.in2) - val shamt = - if (xLen == 32) io.in2(4,0) - else { - require(xLen == 64) - Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0)) - } - val in1_ext = - if (xLen == 32) io.in1 - else { - require(xLen == 64) - val in1_hi_orig = io.in1(63,32) - // note that CLZW uses rotate - val in1_hi_rotate = io.in1(31,0) - // note that sext fills 0 for ADDW/SUBW, but it works - val in1_hi_sext = Fill(32, isSRA & io.in1(31)) // 31 to 63 then to 64 in shout_r - val in1_hi_zext = Fill(32, 0.U) - val in1_hi = Mux(io.dw === DW_64, - Mux(isUW, in1_hi_zext, in1_hi_orig), - Mux(isRotate, in1_hi_rotate, in1_hi_sext)) - Cat(in1_hi, io.in1(31,0)) - } - // one arm: SL, ROL, SLLIUW, CLZ - // another arm: SR, SRA, ROR, CTZ, ADD, SUB, ZBS - // note that CLZW is not included here - // in1 capable of right hand operation - // isLeft - val in1_r = Mux(isLeft, Reverse(in1_ext), in1_ext) - - // shifter - val shin = Mux(isZBS, - if (xLen == 32) (BigInt(1) << 31).U(32.W) - else { - require(xLen == 64) - (BigInt(1) << 63).U(64.W) - }, in1_r) - // TODO: Merge shift and rotate (manual barrel or upstream to Chisel) - val shout_r = (Cat(isSRA & shin(xLen-1), shin).asSInt >> shamt)(xLen-1,0) - val roout_r = shin.rotateRight(shamt)(xLen-1,0) - val shro_r = Mux(isRotate, roout_r, shout_r) - // one arm: SL, ROL, SLLIUW, ZBS - // another arm: SR, SRA, ROR - val shro = Mux(isLeftZBS, Reverse(shro_r), shro_r) - - // adder - val adder_in1 = - Mux1H(shxadd1H, Seq( - if (xLen == 32) in1_r - else { - require(xLen == 64) - // for CLZW/CTZW - Mux(io.dw === DW_64, in1_r, Cat(Fill(32, 1.U(1.W)), in1_r(31,0))) - }, - (in1_ext << 1)(xLen-1,0), - (in1_ext << 2)(xLen-1,0), - (in1_ext << 3)(xLen-1,0))) - // out = in1 - 1 when isCLZ/isCTZ - // note that when isCZ, isSub is 0 as ~0 = ~1+1 = -1 - val adder_in2 = Mux(isCZ, - ~0.U(xLen.W), in2_inv) - // adder_out = adder_in1 + adder_in2 + isSub - val adder_out = (Cat(adder_in1, 1.U(1.W)) + Cat(adder_in2, isSub))(xLen,1) - io.adder_out := adder_out - - // logic - // AND, OR, XOR - // ANDN, ORN, XNOR - // BCLR, BEXT, BINV, BSET - val out_inv = Mux(isCZBCLR, ~Mux(isBCLR, shro, adder_out), shro) - val logic_in2 = Mux(isCZZBS, out_inv, in2_inv) - // also BINV - val xor = adder_in1 ^ logic_in2 - // also BCLR - val and = adder_in1 & logic_in2 - // also BSET - val or = adder_in1 | logic_in2 - val bext = and.orR - - // SLT, SLTU - // BEQ, BNE, BLT, BGE - // MAX, MIN - val slt = - Mux(io.in1(xLen-1) === io.in2(xLen-1), adder_out(xLen-1), - Mux(isUnsigned, io.in2(xLen-1), io.in1(xLen-1))) - val cmp = isInverted ^ Mux(isSEQSNE, ~(xor.orR), slt) - io.cmp_out := cmp - // MAX, MAXU, MIN, MINU - val max_min = Mux(cmp, io.in2, io.in1) - - // counter - // CLZ, CPOP, CTZ - val cpop = PopCount( - if (xLen == 32) io.in1 - else { - require(xLen == 64) - Mux(io.dw === DW_64, io.in1, Cat(Fill(32, 0.U(1.W)), io.in1(31,0))) - }) - // ctz_in = ~adder_out & adder_in1 // all zero or one hot - val ctz_in = and - val ctz_out = Cat(~ctz_in.orR, VecInit((0 to log2Ceil(xLen)-1).map( - x => { - val bits = ctz_in.asBools.zipWithIndex - VecInit( - bits - filter { case (_, i) => i % (1 << (x + 1)) >= (1 << x) } - map { case (b, _) => b } - ).asUInt.orR - } - ).toSeq).asUInt) - - // ZEXT/SEXT - val exth = Cat(Fill(xLen-16, Mux(isSEXT, io.in1(15), 0.U)), io.in1(15,0)) - val extb = Cat(Fill(xLen-8, io.in1(7)), io.in1(7,0)) - - // REV/ORC - def asBytes(in: UInt): Vec[UInt] = VecInit(in.asBools.grouped(8).map(VecInit(_).asUInt).toSeq) - val in1_bytes = asBytes(io.in1) - val rev8 = VecInit(in1_bytes.reverse.toSeq).asUInt - val orc_brev8 = VecInit(in1_bytes.map(x => { - val orc = Mux(x.orR, 0xFF.U(8.W), 0.U(8.W)) - // BREV8 only in Zbk - if (usingBitManipCrypto) - Mux(isORC, orc, Reverse(x)) - else orc - }).toSeq).asUInt - - // pack - def sext(in: UInt): UInt = { - val in_hi_32 = Fill(32, in(31)) - Cat(in_hi_32, in) - } - val pack = if (usingBitManipCrypto) { - if (xLen == 32) Cat(io.in2(xLen/2-1,0), io.in1(xLen/2-1,0)) - else { - require(xLen == 64) - Mux(io.dw === DW_64, - Cat(io.in2(xLen/2-1,0), io.in1(xLen/2-1,0)), - sext(Cat(io.in2(xLen/4-1,0), io.in1(xLen/4-1,0)))) - } - } else 0.U - val packh = if (usingBitManipCrypto) Cat(0.U((xLen-16).W), io.in2(7,0), io.in1(7,0)) else 0.U - - // zip - val zip = if (xLen == 32 && usingBitManipCrypto) { - val lo = io.in1(15,0).asBools - val hi = io.in1(31,16).asBools - VecInit(lo.zip(hi).map { case (l, h) => VecInit(Seq(l, h)).asUInt }).asUInt - } else 0.U - val unzip = if (xLen == 32 && usingBitManipCrypto) { - val bits = io.in1.asBools.zipWithIndex - val lo = VecInit(bits filter { case (_, i) => i % 2 == 0 } map { case (b, _) => b }).asUInt - val hi = VecInit(bits filter { case (_, i) => i % 2 != 0 } map { case (b, _) => b }).asUInt - Cat(hi, lo) - } else 0.U - - val out = Mux1H(out1H, Seq( - adder_out, - shro, - and, - xor, - // - or, - bext, - cmp, - max_min, - // - cpop, - ctz_out, - exth, - extb, - // - rev8, - orc_brev8, - pack, - packh, - // - zip, - unzip)) - - val out_w = - if (xLen == 32) out - else { - require(xLen == 64) - Mux(io.dw === DW_64, out, Cat(Fill(32, out(31)), out(31,0))) - } - io.out := out_w -} diff --git a/src/main/scala/rocket/ALU.scala b/src/main/scala/rocket/ALU.scala index 68e7db4a98f..20c2bdffeb3 100644 --- a/src/main/scala/rocket/ALU.scala +++ b/src/main/scala/rocket/ALU.scala @@ -28,73 +28,6 @@ class ALUFN { def FN_SLTU = 14.U def FN_SGEU = 15.U - // The Base ALU does not support any Zb FNs - // from Zb - // Zba: UW is encoded here becuase it is DW_64 - def FN_ADDUW : UInt = ??? - def FN_SLLIUW : UInt = ??? - def FN_SH1ADD : UInt = ??? - def FN_SH1ADDUW : UInt = ??? - def FN_SH2ADD : UInt = ??? - def FN_SH2ADDUW : UInt = ??? - def FN_SH3ADD : UInt = ??? - def FN_SH3ADDUW : UInt = ??? - // Zbb - def FN_ROR : UInt = ??? - def FN_ROL : UInt = ??? - def FN_ANDN : UInt = ??? - def FN_ORN : UInt = ??? - def FN_XNOR : UInt = ??? - def FN_REV8 : UInt = ??? - def FN_ORCB : UInt = ??? - def FN_SEXTB : UInt = ??? - def FN_SEXTH : UInt = ??? - def FN_ZEXTH : UInt = ??? - def FN_MAX : UInt = ??? - def FN_MAXU : UInt = ??? - def FN_MIN : UInt = ??? - def FN_MINU : UInt = ??? - def FN_CPOP : UInt = ??? - def FN_CLZ : UInt = ??? - def FN_CTZ : UInt = ??? - // Zbs - def FN_BCLR : UInt = ??? - def FN_BEXT : UInt = ??? - def FN_BINV : UInt = ??? - def FN_BSET : UInt = ??? - // Zbk - def FN_BREV8 : UInt = ??? - def FN_PACK : UInt = ??? - def FN_PACKH : UInt = ??? - def FN_ZIP : UInt = ??? - def FN_UNZIP : UInt = ??? - def FN_CLMUL : UInt = ??? - def FN_CLMULR : UInt = ??? - def FN_CLMULH : UInt = ??? - def FN_XPERM8 : UInt = ??? - def FN_XPERM4 : UInt = ??? - // Zkn - def FN_AES_DS : UInt = ??? - def FN_AES_DSM : UInt = ??? - def FN_AES_ES : UInt = ??? - def FN_AES_ESM : UInt = ??? - def FN_AES_IM : UInt = ??? - def FN_AES_KS1 : UInt = ??? - def FN_AES_KS2 : UInt = ??? - def FN_SHA256_SIG0 : UInt = ??? - def FN_SHA256_SIG1 : UInt = ??? - def FN_SHA256_SUM0 : UInt = ??? - def FN_SHA256_SUM1 : UInt = ??? - def FN_SHA512_SIG0 : UInt = ??? - def FN_SHA512_SIG1 : UInt = ??? - def FN_SHA512_SUM0 : UInt = ??? - def FN_SHA512_SUM1 : UInt = ??? - //Zks - def FN_SM4ED : UInt = ??? - def FN_SM4KS : UInt = ??? - def FN_SM3P0 : UInt = ??? - def FN_SM3P1 : UInt = ??? - // Mul/div reuse some integer FNs def FN_DIV = FN_XOR def FN_DIVU = FN_SR @@ -112,9 +45,6 @@ class ALUFN { def cmpUnsigned(cmd: UInt) = cmd(1) def cmpInverted(cmd: UInt) = cmd(0) def cmpEq(cmd: UInt) = !cmd(3) - - // Only CryptoNIST uses this - def isKs1(cmd: UInt): Bool = ??? } object ALUFN { @@ -175,7 +105,7 @@ class ALU(implicit p: Parameters) extends AbstractALU(new ALUFN)(p) { val shift_logic = (aluFn.isCmp (io.fn) && slt) | logic | shout val shift_logic_cond = cond_out match { case Some(co) => shift_logic | co - case _ => shift_logic + case _ => shift_logic } val out = Mux(io.fn === aluFn.FN_ADD || io.fn === aluFn.FN_SUB, io.adder_out, shift_logic_cond) diff --git a/src/main/scala/rocket/BitManipCrypto.scala b/src/main/scala/rocket/BitManipCrypto.scala index c09768b82e6..e69de29bb2d 100644 --- a/src/main/scala/rocket/BitManipCrypto.scala +++ b/src/main/scala/rocket/BitManipCrypto.scala @@ -1,59 +0,0 @@ -// See LICENSE.SiFive for license details. - -package freechips.rocketchip.rocket - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters - - -class BitManipCryptoInterface(xLen: Int) extends Bundle { - val fn = Input(UInt(ABLUFN().SZ_ZBK_FN.W)) - val dw = Input(Bool()) - val rs1 = Input(UInt(xLen.W)) - val rs2 = Input(UInt(xLen.W)) - val rd = Output(UInt(xLen.W)) -} - -class BitManipCrypto(xLen: Int)(implicit val p: Parameters) extends Module with HasRocketCoreParameters { - val fn = ABLUFN() - val io = IO(new BitManipCryptoInterface(xLen)) - - val isClmul = fn.isClmul(io.fn) - val out1H = fn.zbkOut1H(io.fn) - - // helper - def asBytes(in: UInt): Vec[UInt] = VecInit(in.asBools.grouped(8).map(VecInit(_).asUInt).toSeq) - def asNibbles(in: UInt): Vec[UInt] = VecInit(in.asBools.grouped(4).map(VecInit(_).asUInt).toSeq) - - // xperm - val rs1_bytes = asBytes(io.rs1) - val rs2_bytes = asBytes(io.rs2) - val rs1_nibbles = asNibbles(io.rs1) - val rs2_nibbles = asNibbles(io.rs2) - // only instantiate clmul when usingBitManip && !usingBitManipCrypto - val xperm8 = if (usingBitManipCrypto) VecInit(rs2_bytes.map( - x => Mux(x(7,log2Ceil(xLen/8)).orR, 0.U(8.W), rs1_bytes(x)) // return 0 when x overflow - ).toSeq).asUInt else 0.U - val xperm4 = if (usingBitManipCrypto) VecInit(rs2_nibbles.map( - x => if (xLen == 32) Mux(x(3,log2Ceil(xLen/4)).orR, 0.U(4.W), rs1_nibbles(x)) // return 0 when x overflow - else { - require(xLen == 64) - rs1_nibbles(x) - } - ).toSeq).asUInt else 0.U - - // clmul - val clmul_rs1 = Mux(isClmul, io.rs1, Reverse(io.rs1)) - val clmul_rs2 = Mux(isClmul, io.rs2, Reverse(io.rs2)) - val clmul = clmul_rs2.asBools.zipWithIndex.map({ - case (b, i) => Mux(b, clmul_rs1 << i, 0.U) - }).reduce(_ ^ _)(xLen-1,0) - val clmulr = Reverse(clmul) - val clmulh = Cat(0.U(1.W), clmulr(xLen-1,1)) - - // according to FN_xxx above - io.rd := Mux1H(out1H, Seq( - clmul, clmulr, clmulh, - xperm8, xperm4)) -} diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index e8cd587efde..737f18673c4 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -628,8 +628,6 @@ class CSRFile( (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (usingVector) "V" else "") + - // The current spec does not define what sub-extensions constitute the 'B' misa bit - // (if (usingBitManip) "B" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + diff --git a/src/main/scala/rocket/CryptoNIST.scala b/src/main/scala/rocket/CryptoNIST.scala index ad59a860c17..e69de29bb2d 100644 --- a/src/main/scala/rocket/CryptoNIST.scala +++ b/src/main/scala/rocket/CryptoNIST.scala @@ -1,261 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package freechips.rocketchip.rocket - -import chisel3._ -import chisel3.util._ -import freechips.rocketchip.util._ - -class CryptoNISTInterface(xLen: Int) extends Bundle { - val fn = Input(UInt(ABLUFN().SZ_ZKN_FN.W)) - val hl = Input(Bool()) - val bs = Input(UInt(2.W)) - val rs1 = Input(UInt(xLen.W)) - val rs2 = Input(UInt(xLen.W)) - val rd = Output(UInt(xLen.W)) -} - -object AES { - val rcon: Seq[Int] = Seq( - 0x01, 0x02, 0x04, 0x08, - 0x10, 0x20, 0x40, 0x80, - 0x1b, 0x36, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 - ) -} - -class AESSBox extends Module { - val io = IO(new Bundle { - val isEnc = Input(Bool()) - val in = Input(UInt(8.W)) - val out = Output(UInt(8.W)) - }) - - val enc = SBoxAESEncIn(io.in) - val dec = SBoxAESDecIn(io.in) - val mid = SBoxMid(Mux(io.isEnc, enc, dec)) - io.out := Mux(io.isEnc, SBoxAESEncOut(mid), SBoxAESDecOut(mid)) -} - -class GFMul(y: Int) extends Module { - val io = IO(new Bundle { - val in = Input(UInt(8.W)) - val out = Output(UInt(8.W)) - }) - - // x*f(x) = 2*in in GF - def xt(in: UInt): UInt = (in << 1)(7,0) ^ Mux(in(7), 0x1b.U(8.W), 0x00.U(8.W)) - // 4*in in GF - def xt2(in: UInt): UInt = xt(xt(in)) - // 8*in in GF - def xt3(in: UInt): UInt = xt(xt2(in)) - - require(y != 0) - io.out := VecInit( - (if ((y & 0x1) != 0) Seq( (io.in)) else Nil) ++ - (if ((y & 0x2) != 0) Seq( xt(io.in)) else Nil) ++ - (if ((y & 0x4) != 0) Seq(xt2(io.in)) else Nil) ++ - (if ((y & 0x8) != 0) Seq(xt3(io.in)) else Nil) - ).reduce(_ ^ _) -} - -class ShiftRows(enc: Boolean) extends Module { - val io = IO(new Bundle { - val in1 = Input(UInt(64.W)) - val in2 = Input(UInt(64.W)) - val out = Output(UInt(64.W)) - }) - - val stride = if (enc) 5 else 13 - val indexes = Seq.tabulate(4)(x => (x * stride) % 16) ++ - Seq.tabulate(4)(x => (x * stride + 4) % 16) - - def asBytes(in: UInt): Vec[UInt] = VecInit(in.asBools.grouped(8).map(VecInit(_).asUInt).toSeq) - val bytes = asBytes(io.in1) ++ asBytes(io.in2) - - io.out := VecInit(indexes.map(bytes(_)).toSeq).asUInt -} - -class MixColumn8(enc: Boolean) extends Module { - val io = IO(new Bundle { - val in = Input(UInt(8.W)) - val out = Output(UInt(32.W)) - }) - - def m(x: UInt, y: Int): UInt = { - val m = Module(new GFMul(y)) - m.io.in := x - m.io.out - } - - val out = if (enc) Cat(m(io.in, 3), io.in, io.in, m(io.in, 2)) - else Cat(m(io.in, 0xb), m(io.in, 0xd), m(io.in, 9), m(io.in, 0xe)) - io.out := out -} - -class MixColumn32(enc: Boolean) extends Module { - val io = IO(new Bundle { - val in = Input(UInt(32.W)) - val out = Output(UInt(32.W)) - }) - - def asBytes(in: UInt): Vec[UInt] = VecInit(in.asBools.grouped(8).map(VecInit(_).asUInt).toSeq) - io.out := asBytes(io.in).zipWithIndex.map({ - case (b, i) => { - val m = Module(new MixColumn8(enc)) - m.io.in := b - m.io.out.rotateLeft(i * 8) - } - }).reduce(_ ^ _) -} - -class MixColumn64(enc: Boolean) extends Module { - val io = IO(new Bundle { - val in = Input(UInt(64.W)) - val out = Output(UInt(64.W)) - }) - - io.out := VecInit(io.in.asBools.grouped(32).map(VecInit(_).asUInt).map({ - x => { - val m = Module(new MixColumn32(enc)) - m.io.in := x - m.io.out - } - }).toSeq).asUInt -} - -class CryptoNIST(xLen:Int) extends Module { - val fn = ABLUFN() - val io = IO(new CryptoNISTInterface(xLen)) - - val isEnc = fn.isEnc(io.fn) - val isNotMix = fn.isNotMix(io.fn) - val isKs1 = fn.isKs1(io.fn) - val isIm = fn.isIm(io.fn) - val aes1H = fn.aes1H(io.fn) - val out1H = fn.zknOut1H(io.fn) - - // helper - def asBytes(in: UInt): Vec[UInt] = VecInit(in.asBools.grouped(8).map(VecInit(_).asUInt).toSeq) - - // aes - val aes = if (xLen == 32) { - val si = asBytes(io.rs2)(io.bs) - val so = { - val m = Module(new AESSBox) - m.io.in := si - m.io.isEnc := isEnc - m.io.out - } - val mixed_so = Mux(isNotMix, Cat(0.U(24.W), so), { - val mc_enc = Module(new MixColumn8(true)) - val mc_dec = Module(new MixColumn8(false)) - mc_enc.io.in := so - mc_dec.io.in := so - Mux(isEnc, mc_enc.io.out, mc_dec.io.out) - }) - // Vec rightRotate = UInt rotateLeft as Vec is big endian while UInt is little endian - // FIXME: use chisel3.stdlib.BarrelShifter after chisel3 3.6.0 - io.rs1 ^ BarrelShifter.rightRotate(asBytes(mixed_so), io.bs).asUInt - } else { - require(xLen == 64) - // var name from rvk spec enc/dec - val sr = { - val sr_enc = Module(new ShiftRows(true)) - val sr_dec = Module(new ShiftRows(false)) - sr_enc.io.in1 := io.rs1 - sr_enc.io.in2 := io.rs2 - sr_dec.io.in1 := io.rs1 - sr_dec.io.in2 := io.rs2 - Mux(isEnc, sr_enc.io.out, sr_dec.io.out) - } - // var name from rvk spec ks1 - val rnum = io.rs2(3,0) - val tmp1 = io.rs1(63,32) - val tmp2 = Mux(rnum === 0xA.U, tmp1, tmp1.rotateRight(8)) - // reuse 8 Sbox here - val si = Mux(isKs1, Cat(0.U(32.W), tmp2), sr) - val so = VecInit(asBytes(si).map(x => { - val m = Module(new AESSBox) - m.io.in := x - m.io.isEnc := isEnc - m.io.out - }).toSeq).asUInt - val mixed = { - val mc_in = Mux(isIm, io.rs1, so) - val mc_enc = Module(new MixColumn64(true)) - val mc_dec = Module(new MixColumn64(false)) - mc_enc.io.in := mc_in - mc_dec.io.in := mc_in - // for isIm, it is also dec - Mux(isEnc, mc_enc.io.out, mc_dec.io.out) - } - // var name from rvk spec ks1 - val rc = VecInit(AES.rcon.map(_.U(8.W)).toSeq)(rnum) - val tmp4 = so(31,0) ^ rc - val ks1 = Cat(tmp4, tmp4) - // var name from rvk spec ks2 - val w0 = tmp1 ^ io.rs2(31,0) - val w1 = w0 ^ io.rs2(63,32) - val ks2 = Cat(w1, w0) - Mux1H(aes1H, Seq(so, mixed, ks1, ks2)) - } - - // sha - def sext(in: UInt): UInt = if (xLen == 32) in - else { - require(xLen == 64) - val in_hi_32 = Fill(32, in(31)) - Cat(in_hi_32, in) - } - val inb = io.rs1(31,0) - val sha256sig0 = sext(inb.rotateRight(7) ^ inb.rotateRight(18) ^ (inb >> 3)) - val sha256sig1 = sext(inb.rotateRight(17) ^ inb.rotateRight(19) ^ (inb >> 10)) - val sha256sum0 = sext(inb.rotateRight(2) ^ inb.rotateRight(13) ^ inb.rotateRight(22)) - val sha256sum1 = sext(inb.rotateRight(6) ^ inb.rotateRight(11) ^ inb.rotateRight(25)) - - val sha512sig0 = if (xLen == 32) { - val sha512sig0_rs1 = (io.rs1 >> 1 ) ^ (io.rs1 >> 7) ^ (io.rs1 >> 8) - val sha512sig0_rs2h = (io.rs2 << 31) ^ (io.rs2 << 24) - val sha512sig0_rs2l = sha512sig0_rs2h ^ (io.rs2 << 25) - sha512sig0_rs1 ^ Mux(io.hl, sha512sig0_rs2h, sha512sig0_rs2l) - } else { - require(xLen == 64) - io.rs1.rotateRight(1) ^ io.rs1.rotateRight(8) ^ io.rs1 >> 7 - } - - val sha512sig1 = if (xLen == 32) { - val sha512sig1_rs1 = (io.rs1 << 3 ) ^ (io.rs1 >> 6) ^ (io.rs1 >> 19) - val sha512sig1_rs2h = (io.rs2 >> 29) ^ (io.rs2 << 13) - val sha512sig1_rs2l = sha512sig1_rs2h ^ (io.rs2 << 26) - sha512sig1_rs1 ^ Mux(io.hl, sha512sig1_rs2h, sha512sig1_rs2l) - } else { - require(xLen == 64) - io.rs1.rotateRight(19) ^ io.rs1.rotateRight(61) ^ io.rs1 >> 6 - } - - val sha512sum0 = if (xLen == 32) { - val sha512sum0_rs1 = (io.rs1 << 25) ^ (io.rs1 << 30) ^ (io.rs1 >> 28) - val sha512sum0_rs2 = (io.rs2 >> 7) ^ (io.rs2 >> 2) ^ (io.rs2 << 4) - sha512sum0_rs1 ^ sha512sum0_rs2 - } else { - require(xLen == 64) - io.rs1.rotateRight(28) ^ io.rs1.rotateRight(34) ^ io.rs1.rotateRight(39) - } - - val sha512sum1 = if (xLen == 32) { - val sha512sum1_rs1 = (io.rs1 << 23) ^ (io.rs1 >> 14) ^ (io.rs1 >> 18) - val sha512sum1_rs2 = (io.rs2 >> 9) ^ (io.rs2 << 18) ^ (io.rs2 << 14) - sha512sum1_rs1 ^ sha512sum1_rs2 - } else { - require(xLen == 64) - io.rs1.rotateRight(14) ^ io.rs1.rotateRight(18) ^ io.rs1.rotateRight(41) - } - - io.rd := Mux1H(out1H, Seq( - aes, - sha256sig0, sha256sig1, - sha256sum0, sha256sum1, - sha512sig0, sha512sig1, - sha512sum0, sha512sum1)) -} diff --git a/src/main/scala/rocket/CryptoSM.scala b/src/main/scala/rocket/CryptoSM.scala deleted file mode 100644 index 5092e164445..00000000000 --- a/src/main/scala/rocket/CryptoSM.scala +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package freechips.rocketchip.rocket - -import chisel3._ -import chisel3.util._ -import freechips.rocketchip.util._ - -class CryptoSMInterface(xLen: Int) extends Bundle { - val fn = Input(UInt(ABLUFN().SZ_ZKS_FN.W)) - val bs = Input(UInt(2.W)) - val rs1 = Input(UInt(xLen.W)) - val rs2 = Input(UInt(xLen.W)) - val rd = Output(UInt(xLen.W)) -} - -class CryptoSM(xLen:Int) extends Module { - val fn = ABLUFN() - val io = IO(new CryptoSMInterface(xLen)) - - val isEd = fn.isEd(io.fn) - val isP0 = fn.isP0(io.fn) - val out1H = fn.zksOut1H(io.fn) - - // helper - def sext(in: UInt): UInt = if (xLen == 32) in - else { - require(xLen == 64) - val in_hi_32 = Fill(32, in(31)) - Cat(in_hi_32, in) - } - def asBytes(in: UInt): Vec[UInt] = VecInit(in.asBools.grouped(8).map(VecInit(_).asUInt).toSeq) - - // sm4 - // dynamic selection should be merged into aes rv32 logic! - val si = asBytes(io.rs2(31,0))(io.bs) - // this can also be merged into AESSbox for rv32 - val so = SBoxSM4Out(SBoxMid(SBoxSM4In(si))) - val x = Cat(0.U(24.W), so) - val y = Mux(isEd, - x ^ (x << 8) ^ (x << 2) ^ (x << 18) ^ ((x & 0x3F.U) << 26) ^ ((x & 0xC0.U) << 10), - x ^ ((x & 0x7.U) << 29) ^ ((x & 0xFE.U) << 7) ^ ((x & 0x1.U) << 23) ^ ((x & 0xF8.U) << 13))(31,0) - // dynamic rotate should be merged into aes rv32 logic! - // Vec rightRotate = UInt rotateLeft as Vec is big endian while UInt is little endian - // FIXME: use chisel3.stdlib.BarrelShifter after chisel3 3.6.0 - val z = BarrelShifter.rightRotate(asBytes(y), io.bs).asUInt - val sm4 = sext(z ^ io.rs1(31,0)) - - // sm3 - val r1 = io.rs1(31,0) - val sm3 = sext(Mux(isP0, - r1 ^ r1.rotateLeft(9) ^ r1.rotateLeft(17), - r1 ^ r1.rotateLeft(15) ^ r1.rotateLeft(23))) - - io.rd := Mux1H(out1H, Seq(sm4, sm3)) -} diff --git a/src/main/scala/rocket/IDecode.scala b/src/main/scala/rocket/IDecode.scala index 50db5dda926..86ee7eef58a 100644 --- a/src/main/scala/rocket/IDecode.scala +++ b/src/main/scala/rocket/IDecode.scala @@ -25,9 +25,6 @@ class IntCtrlSigs(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends Bu val jalr = Bool() val rxs2 = Bool() val rxs1 = Bool() - val zbk = Bool() - val zkn = Bool() - val zks = Bool() val sel_alu2 = Bits(A2_X.getWidth.W) val sel_alu1 = Bits(A1_X.getWidth.W) val sel_imm = Bits(IMM_X.getWidth.W) @@ -49,19 +46,19 @@ class IntCtrlSigs(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends Bu val dp = Bool() def default: List[BitPat] = - // jal renf1 fence.i - // val | jalr | renf2 | - // | fp_val| | renx2 | | renf3 | - // | | rocc| | | renx1 s_alu1 mem_val | | | wfd | - // | | | br| | | | s_alu2 | imm dw alu | mem_cmd | | | | mul | - // | | | | | | | | zbk | | | | | | | | | | | | div | fence - // | | | | | | | | | zkn | | | | | | | | | | | | | wxd | | amo - // | | | | | | | | | | zks | | | | | | | | | | | | | | | | | dp - List(N,X,X,X,X,X,X,X,X,X,X, A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, X,X,X,X,X,X,X,CSR.X,X,X,X,X) + // jal renf1 fence.i + // val | jalr | renf2 | + // | fp_val| | renx2 | | renf3 | + // | | rocc| | | renx1 s_alu1 mem_val | | | wfd | + // | | | br| | | | s_alu2 | imm dw alu | mem_cmd | | | | mul | + // | | | | | | | | | | | | | | | | | | | | div | fence + // | | | | | | | | | | | | | | | | | | | | | wxd | | amo + // | | | | | | | | | | | | | | | | | | | | | | | | | dp + List(N,X,X,X,X,X,X,X, A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, X,X,X,X,X,X,X,CSR.X,X,X,X,X) def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = DecodeLogic(inst, default, table) - val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, zbk, zkn, zks, sel_alu2, + val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2, sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, rfs1, rfs2, rfs3, wfd, mul, div, wxd, csr, fence_i, fence, amo, dp) sigs zip decoder map {case(s,d) => s := d} @@ -72,62 +69,62 @@ class IntCtrlSigs(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends Bu class IDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - BNE-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SNE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - BEQ-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SEQ, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - BLT-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - BLTU-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - BGE-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - BGEU-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGEU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - - JAL-> List(Y,N,N,N,Y,N,N,N,N,N,N,A2_SIZE,A1_PC, IMM_UJ,DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - JALR-> List(Y,N,N,N,N,Y,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - AUIPC-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - - LB-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - LH-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - LW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - LBU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - LHU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SB-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - SH-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - SW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - - LUI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - ADDI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SLTI -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SLTIU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - ANDI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - ORI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - XORI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - ADD-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SUB-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SLT-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SLTU-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - AND-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - OR-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - XOR-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SLL-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SRL-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SRA-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - - FENCE-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,Y,N,N), - - ECALL-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - EBREAK-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - MRET-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - WFI-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - CSRRW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N), - CSRRS-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N), - CSRRC-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N), - CSRRWI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N), - CSRRSI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N), - CSRRCI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N)) + BNE-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SNE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BEQ-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SEQ, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BLT-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BLTU-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BGE-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BGEU-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGEU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + + JAL-> List(Y,N,N,N,Y,N,N,N,A2_SIZE,A1_PC, IMM_UJ,DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + JALR-> List(Y,N,N,N,N,Y,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + AUIPC-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + + LB-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + LH-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + LW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + LBU-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + LHU-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SB-> List(Y,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + SH-> List(Y,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + SW-> List(Y,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + + LUI-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + ADDI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLTI -> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLTIU-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + ANDI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + ORI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + XORI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + ADD-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SUB-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLT-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLTU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + AND-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + OR-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + XOR-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLL-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRL-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRA-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + + FENCE-> List(Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,Y,N,N), + + ECALL-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + EBREAK-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + MRET-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + WFI-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + CSRRW-> List(Y,N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N), + CSRRS-> List(Y,N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N), + CSRRC-> List(Y,N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N), + CSRRWI-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N), + CSRRSI-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N), + CSRRCI-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N)) } class CeaseDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - CEASE-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) + CEASE-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) } @@ -136,14 +133,14 @@ class FenceIDecode(flushDCache: Boolean, aluFn: ALUFN = ALUFN())(implicit val p: private val (v, cmd) = if (flushDCache) (Y, BitPat(M_FLUSH_ALL)) else (N, M_X) val table: Array[(BitPat, List[BitPat])] = Array( - FENCE_I-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, v,cmd, N,N,N,N,N,N,N,CSR.N,Y,Y,N,N)) + FENCE_I-> List(Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, v,cmd, N,N,N,N,N,N,N,CSR.N,Y,Y,N,N)) } class ConditionalZeroDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - CZERO_EQZ-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_CZEQZ, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CZERO_NEZ-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_CZNEZ, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) + CZERO_EQZ-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_CZEQZ, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CZERO_NEZ-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_CZNEZ, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) } class CFlushDecode(supportsFlushLine: Boolean, aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants @@ -152,94 +149,94 @@ class CFlushDecode(supportsFlushLine: Boolean, aluFn: ALUFN = ALUFN())(implicit val table: Array[(BitPat, List[BitPat])] = Array( zapRs1(CFLUSH_D_L1)-> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_FLUSH_ALL,N,N,N,N,N,N,N,CSR.I,N,N,N,N), + List(Y,N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_FLUSH_ALL,N,N,N,N,N,N,N,CSR.I,N,N,N,N), zapRs1(CDISCARD_D_L1)-> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_FLUSH_ALL,N,N,N,N,N,N,N,CSR.I,N,N,N,N)) + List(Y,N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_FLUSH_ALL,N,N,N,N,N,N,N,CSR.I,N,N,N,N)) } class SVMDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - SFENCE_VMA->List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_SFENCE, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) + SFENCE_VMA->List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_SFENCE, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) } class SDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - SRET-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) + SRET-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) } class HypervisorDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - HFENCE_VVMA->List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_HFENCEV, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - HFENCE_GVMA->List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_HFENCEG, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + HFENCE_VVMA->List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_HFENCEV, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + HFENCE_GVMA->List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_HFENCEG, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - HLV_B -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), - HLV_BU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), - HLV_H -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), - HLV_HU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), - HLVX_HU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_HLVX, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), - HLV_W-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), - HLVX_WU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_HLVX, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), + HLV_B -> List(Y,N,N,N,N,N,N,Y,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), + HLV_BU-> List(Y,N,N,N,N,N,N,Y,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), + HLV_H -> List(Y,N,N,N,N,N,N,Y,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), + HLV_HU-> List(Y,N,N,N,N,N,N,Y,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), + HLVX_HU-> List(Y,N,N,N,N,N,N,Y,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_HLVX, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), + HLV_W-> List(Y,N,N,N,N,N,N,Y,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), + HLVX_WU-> List(Y,N,N,N,N,N,N,Y,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_HLVX, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), - HSV_B-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO, A1_RS1, IMM_I, DW_XPR, aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - HSV_H-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO, A1_RS1, IMM_I, DW_XPR, aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - HSV_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO, A1_RS1, IMM_I, DW_XPR, aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) + HSV_B-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO, A1_RS1, IMM_I, DW_XPR, aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + HSV_H-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO, A1_RS1, IMM_I, DW_XPR, aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + HSV_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO, A1_RS1, IMM_I, DW_XPR, aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) } class DebugDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - DRET-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) + DRET-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) } class NMIDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - MNRET-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) + MNRET-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) } class I32Decode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( Instructions32.SLLI-> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), Instructions32.SRLI-> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), Instructions32.SRAI-> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) + List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) } class I64Decode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - LD-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - LWU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SD-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - - SLLI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SRLI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SRAI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - - ADDIW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_32,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SLLIW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_32,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SRLIW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_32,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SRAIW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_32,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - ADDW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SUBW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SLLW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SRLW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SRAW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) + LD-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + LWU-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SD-> List(Y,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + + SLLI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRLI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRAI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + + ADDIW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLLIW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRLIW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRAIW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + ADDW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SUBW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLLW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRLW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRAW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) } class Hypervisor64Decode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - HLV_D-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), - HSV_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO, A1_RS1, IMM_I, DW_XPR, aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - HLV_WU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N)) + HLV_D-> List(Y,N,N,N,N,N,N,Y,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N), + HSV_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO, A1_RS1, IMM_I, DW_XPR, aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + HLV_WU-> List(Y,N,N,N,N,N,N,Y,A2_ZERO, A1_RS1, IMM_X, DW_XPR, aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.I,N,N,N,N)) } class MDecode(pipelinedMul: Boolean, aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants @@ -247,15 +244,15 @@ class MDecode(pipelinedMul: Boolean, aluFn: ALUFN = ALUFN())(implicit val p: Par val M = if (pipelinedMul) Y else N val D = if (pipelinedMul) N else Y val table: Array[(BitPat, List[BitPat])] = Array( - MUL-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_MUL, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), - MULH-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_MULH, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), - MULHU-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_MULHU, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), - MULHSU-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_MULHSU,N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), - - DIV-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_DIV, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), - DIVU-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_DIVU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), - REM-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_REM, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), - REMU-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_REMU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N)) + MUL-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_MUL, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), + MULH-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_MULH, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), + MULHU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_MULHU, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), + MULHSU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_MULHSU,N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), + + DIV-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_DIV, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), + DIVU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_DIVU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), + REM-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_REM, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), + REMU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_REMU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N)) } class M64Decode(pipelinedMul: Boolean, aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants @@ -263,478 +260,204 @@ class M64Decode(pipelinedMul: Boolean, aluFn: ALUFN = ALUFN())(implicit val p: P val M = if (pipelinedMul) Y else N val D = if (pipelinedMul) N else Y val table: Array[(BitPat, List[BitPat])] = Array( - MULW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_MUL, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), + MULW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_MUL, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N), - DIVW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_DIV, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), - DIVUW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_DIVU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), - REMW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_REM, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), - REMUW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_REMU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N)) + DIVW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_DIV, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), + DIVUW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_DIVU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), + REMW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_REM, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N), + REMUW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, aluFn.FN_REMU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N)) } class ADecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - AMOADD_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_ADD, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOXOR_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_XOR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOSWAP_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_SWAP, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOAND_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_AND, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOOR_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_OR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOMIN_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MIN, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOMINU_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MINU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOMAX_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MAX, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOMAXU_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MAXU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - - LR_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XLR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - SC_W-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XSC, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N)) + AMOADD_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_ADD, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOXOR_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_XOR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOSWAP_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_SWAP, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOAND_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_AND, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOOR_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_OR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOMIN_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MIN, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOMINU_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MINU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOMAX_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MAX, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOMAXU_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MAXU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + + LR_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XLR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + SC_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XSC, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N)) } class A64Decode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - AMOADD_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_ADD, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOSWAP_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_SWAP, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOXOR_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_XOR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOAND_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_AND, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOOR_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_OR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOMIN_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MIN, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOMINU_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MINU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOMAX_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MAX, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - AMOMAXU_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MAXU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - - LR_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XLR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), - SC_D-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XSC, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N)) + AMOADD_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_ADD, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOSWAP_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_SWAP, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOXOR_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_XOR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOAND_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_AND, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOOR_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_OR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOMIN_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MIN, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOMINU_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MINU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOMAX_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MAX, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + AMOMAXU_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XA_MAXU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + + LR_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XLR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N), + SC_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, Y,M_XSC, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N)) } class HDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - FCVT_S_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FCVT_H_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FSGNJ_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FSGNJX_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FSGNJN_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FMIN_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FMAX_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FADD_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FSUB_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FMUL_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FMADD_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), - FMSUB_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), - FNMADD_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), - FNMSUB_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), - FCLASS_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FMV_X_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FCVT_W_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FCVT_WU_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FEQ_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), - FLT_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), - FLE_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), - FMV_H_X-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FCVT_H_W-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FCVT_H_WU-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FLH-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FSH-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,N), - FDIV_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FSQRT_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N)) + FCVT_S_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FCVT_H_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FSGNJ_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FSGNJX_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FSGNJN_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FMIN_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FMAX_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FADD_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FSUB_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FMUL_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FMADD_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), + FMSUB_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), + FNMADD_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), + FNMSUB_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), + FCLASS_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FMV_X_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FCVT_W_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FCVT_WU_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FEQ_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), + FLT_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), + FLE_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), + FMV_H_X-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FCVT_H_W-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FCVT_H_WU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FLH-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FSH-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,N), + FDIV_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FSQRT_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N)) } class FDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - FSGNJ_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FSGNJX_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FSGNJN_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FMIN_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FMAX_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FADD_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FSUB_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FMUL_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FMADD_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), - FMSUB_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), - FNMADD_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), - FNMSUB_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), - FCLASS_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FMV_X_W-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FCVT_W_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FCVT_WU_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FEQ_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), - FLT_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), - FLE_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), - FMV_W_X-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FCVT_S_W-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FCVT_S_WU-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FLW-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FSW-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,N), - FDIV_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), - FSQRT_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N)) + FSGNJ_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FSGNJX_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FSGNJN_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FMIN_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FMAX_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FADD_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FSUB_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FMUL_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FMADD_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), + FMSUB_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), + FNMADD_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), + FNMSUB_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N), + FCLASS_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FMV_X_W-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FCVT_W_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FCVT_WU_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FEQ_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), + FLT_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), + FLE_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N), + FMV_W_X-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FCVT_S_W-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FCVT_S_WU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FLW-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FSW-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,N), + FDIV_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N), + FSQRT_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N)) } class DDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - FCVT_S_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y), - FCVT_D_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y), - FSGNJ_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), - FSGNJX_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), - FSGNJN_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), - FMIN_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), - FMAX_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), - FADD_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), - FSUB_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), - FMUL_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), - FMADD_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y), - FMSUB_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y), - FNMADD_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y), - FNMSUB_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y), - FCLASS_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), - FCVT_W_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), - FCVT_WU_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), - FEQ_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y), - FLT_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y), - FLE_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y), - FCVT_D_W-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), - FCVT_D_WU-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), - FLD-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), - FSD-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,Y), - FDIV_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), - FSQRT_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y)) + FCVT_S_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y), + FCVT_D_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y), + FSGNJ_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), + FSGNJX_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), + FSGNJN_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), + FMIN_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), + FMAX_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), + FADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), + FSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), + FMUL_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), + FMADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y), + FMSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y), + FNMADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y), + FNMSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y), + FCLASS_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), + FCVT_W_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), + FCVT_WU_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), + FEQ_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y), + FLT_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y), + FLE_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y), + FCVT_D_W-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), + FCVT_D_WU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), + FLD-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), + FSD-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,Y), + FDIV_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y), + FSQRT_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y)) } class HDDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - FCVT_D_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y), - FCVT_H_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y)) + FCVT_D_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y), + FCVT_H_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y)) } class H64Decode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - FCVT_L_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FCVT_LU_H-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FCVT_H_L-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FCVT_H_LU-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N)) + FCVT_L_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FCVT_LU_H-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FCVT_H_L-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FCVT_H_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N)) } class F64Decode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - FCVT_L_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FCVT_LU_S-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), - FCVT_S_L-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), - FCVT_S_LU-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N)) + FCVT_L_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FCVT_LU_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N), + FCVT_S_L-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N), + FCVT_S_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N)) } class D64Decode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - FMV_X_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), - FCVT_L_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), - FCVT_LU_D-> List(Y,Y,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), - FMV_D_X-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), - FCVT_D_L-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), - FCVT_D_LU-> List(Y,Y,N,N,N,N,N,Y,N,N,N,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y)) -} - -trait UsesABLUFN { - val aluFn = ABLUFN() -} - -class ZBADecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - SH1ADD -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR, aluFn.FN_SH1ADD,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SH2ADD -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR, aluFn.FN_SH2ADD,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SH3ADD -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR, aluFn.FN_SH3ADD,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBA64Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - ADD_UW -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_64,aluFn.FN_ADDUW ,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SLLI_UW -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_64,aluFn.FN_SLLIUW ,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SH1ADD_UW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_64,aluFn.FN_SH1ADDUW,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SH2ADD_UW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_64,aluFn.FN_SH2ADDUW,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SH3ADD_UW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_64,aluFn.FN_SH3ADDUW,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -// In both Zbb and Zbkb -class ZBBNDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - ANDN -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ANDN, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - ORN -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ORN , N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - XNOR -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_XNOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -// In both Zbb and Zbkb -class ZBBRDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - ROR -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ROR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - ROL -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ROL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBBR32Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - Instructions32.RORI -> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_ROR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBBR64Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - RORI -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_ROR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - RORW -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_32, aluFn.FN_ROR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - ROLW -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_32, aluFn.FN_ROL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - RORIW -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_32, aluFn.FN_ROR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -// Only in Zbb -class ZBBCDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - CLZ -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_CLZ , N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CTZ -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_CTZ , N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CPOP -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_CPOP, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBBC64Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - CLZW -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_32,aluFn.FN_CLZ , N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CTZW -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_32,aluFn.FN_CTZ , N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CPOPW -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_32,aluFn.FN_CPOP, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -// Only in Zbb -class ZBBMDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - MAX -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_MAX , N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - MAXU -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_MAXU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - MIN -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_MIN , N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - MINU -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_MINU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -// Only in Zbb -class ZBBSEDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - SEXT_H -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_SEXTH, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SEXT_B -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_SEXTB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBBZE64Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - ZEXT_H -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ZEXTH, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBBZE32Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - Instructions32.ZEXT_H -> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ZEXTH, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBBORCBDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - ORC_B -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ORCB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -// In both Zbb and Zbkb -class ZBBREV864Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - REV8 -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_REV8, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -// In both Zbb and Zbkb -class ZBBREV832Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - Instructions32.REV8-> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X,A1_RS1, IMM_X, DW_XPR,aluFn.FN_REV8, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -// Only in Zbkb -class ZBKBDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - PACK -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_PACK, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - PACKH -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_PACKH, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - BREV8 -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X ,A1_RS1, IMM_X, DW_XPR,aluFn.FN_BREV8, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBKB64Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - PACKW -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_32, aluFn.FN_PACK, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBKB32Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - Instructions32.ZIP -> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_ZIP, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.UNZIP -> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_UNZIP, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -// also in Zbkc but Zbkc does not have CLMULR -class ZBCDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - CLMUL -> List(Y,N,N,N,N,N,Y,Y,Y,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_CLMUL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CLMULH -> List(Y,N,N,N,N,N,Y,Y,Y,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_CLMULH, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBCRDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - CLMULR -> List(Y,N,N,N,N,N,Y,Y,Y,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_CLMULR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBKXDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - XPERM8 -> List(Y,N,N,N,N,N,Y,Y,Y,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_XPERM8, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - XPERM4 -> List(Y,N,N,N,N,N,Y,Y,Y,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_XPERM4, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBSDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - BCLR -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_BCLR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - BEXT -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_BEXT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - BINV -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_BINV, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - BSET -> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_BSET, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBS32Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - Instructions32.BCLRI -> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_BCLR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.BEXTI -> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_BEXT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.BINVI -> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_BINV, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.BSETI -> - List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_BSET, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZBS64Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - BCLRI -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_BCLR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - BEXTI -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_BEXT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - BINVI -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_BINV, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - BSETI -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_BSET, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZKND32Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - Instructions32.AES32DSI -> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_DS, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.AES32DSMI-> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_DSM,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} -class ZKND64Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - AES64DS -> List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_DS, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - AES64DSM -> List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_DSM,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - AES64IM -> List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_IM, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - AES64KS1I ->List(Y,N,N,N,N,N,N,Y,N,Y,N,A2_IMM,A1_RS1, IMM_I, DW_XPR,aluFn.FN_AES_KS1,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - AES64KS2 -> List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_KS2,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} -class ZKNE32Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - Instructions32.AES32ESI -> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_ES, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.AES32ESMI -> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_ESM,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} -class ZKNE64Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - AES64ES -> List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_ES, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - AES64ESM -> List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_XPR,aluFn.FN_AES_ESM,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZKNHDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - SHA256SIG0->List(Y,N,N,N,N,N,N,Y,N,Y,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA256_SIG0,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SHA256SIG1->List(Y,N,N,N,N,N,N,Y,N,Y,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA256_SIG1,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SHA256SUM0->List(Y,N,N,N,N,N,N,Y,N,Y,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA256_SUM0,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SHA256SUM1->List(Y,N,N,N,N,N,N,Y,N,Y,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA256_SUM1,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} -class ZKNH32Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - Instructions32.SHA512SIG0L -> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SIG0,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.SHA512SIG1L -> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SIG1,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.SHA512SIG0H -> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SIG0,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.SHA512SIG1H -> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SIG1,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.SHA512SUM0R -> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SUM0,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - Instructions32.SHA512SUM1R -> - List(Y,N,N,N,N,N,Y,Y,N,Y,N,A2_RS2,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SUM1,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} -class ZKNH64Decode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - SHA512SIG0->List(Y,N,N,N,N,N,N,Y,N,Y,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SIG0,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SHA512SIG1->List(Y,N,N,N,N,N,N,Y,N,Y,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SIG1,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SHA512SUM0->List(Y,N,N,N,N,N,N,Y,N,Y,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SUM0,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SHA512SUM1->List(Y,N,N,N,N,N,N,Y,N,Y,N,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SHA512_SUM1,N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) -} - -class ZKSDecode(implicit val p: Parameters) extends DecodeConstants with UsesABLUFN -{ - val table: Array[(BitPat, List[BitPat])] = Array( - SM4ED -> List(Y,N,N,N,N,N,Y,Y,N,N,Y,A2_RS2,A1_RS1, IMM_X, DW_X, aluFn.FN_SM4ED, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SM4KS -> List(Y,N,N,N,N,N,Y,Y,N,N,Y,A2_RS2,A1_RS1, IMM_X, DW_X, aluFn.FN_SM4KS, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SM3P0 -> List(Y,N,N,N,N,N,N,Y,N,N,Y,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SM3P0, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - SM3P1 -> List(Y,N,N,N,N,N,N,Y,N,N,Y,A2_X ,A1_RS1, IMM_X, DW_X, aluFn.FN_SM3P1, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) + FMV_X_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), + FCVT_L_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), + FCVT_LU_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y), + FMV_D_X-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), + FCVT_D_L-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y), + FCVT_D_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y)) } class RoCCDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - CUSTOM0-> List(Y,N,Y,N,N,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM0_RS1-> List(Y,N,Y,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM0_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM0_RD-> List(Y,N,Y,N,N,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM0_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM0_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM1-> List(Y,N,Y,N,N,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM1_RS1-> List(Y,N,Y,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM1_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM1_RD-> List(Y,N,Y,N,N,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM1_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM1_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM2-> List(Y,N,Y,N,N,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM2_RS1-> List(Y,N,Y,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM2_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM2_RD-> List(Y,N,Y,N,N,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM2_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM2_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM3-> List(Y,N,Y,N,N,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM3_RS1-> List(Y,N,Y,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM3_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), - CUSTOM3_RD-> List(Y,N,Y,N,N,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM3_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - CUSTOM3_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) + CUSTOM0-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM0_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM0_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM0_RD-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM0_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM0_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM1-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM1_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM1_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM1_RD-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM1_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM1_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM2-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM2_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM2_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM2_RD-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM2_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM2_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM3-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM3_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM3_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,N,CSR.N,N,N,N,N), + CUSTOM3_RD-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM3_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + CUSTOM3_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X,N,N,N,N,N,N,Y,CSR.N,N,N,N,N)) } diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index 34f16d273c3..65f8c73234a 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -23,10 +23,6 @@ case class RocketCoreParams( useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, - useBitManip: Boolean = false, - useBitManipCrypto: Boolean = false, - useCryptoNIST: Boolean = false, - useCryptoSM: Boolean = false, useConditionalZero: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, @@ -79,12 +75,10 @@ trait HasRocketCoreParameters extends HasCoreParameters { val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this - val usingABLU = usingBitManip || usingBitManipCrypto - val aluFn = if (usingABLU) new ABLUFN else new ALUFN + val aluFn = new ALUFN require(!fastLoadByte || fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") - require(!(usingABLU && usingConditionalZero), "Zicond is not yet implemented in ABLU") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { @@ -189,14 +183,6 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) (if (fLen >= 64) new DDecode(aluFn) +: (xLen > 32).option(new D64Decode(aluFn)).toSeq else Nil) ++: (if (minFLen == 16) new HDecode(aluFn) +: (xLen > 32).option(new H64Decode(aluFn)).toSeq ++: (fLen >= 64).option(new HDDecode(aluFn)).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode(aluFn))) ++: - (if (usingBitManip) new ZBADecode +: (xLen == 64).option(new ZBA64Decode).toSeq ++: new ZBBMDecode +: new ZBBORCBDecode +: new ZBCRDecode +: new ZBSDecode +: (xLen == 32).option(new ZBS32Decode).toSeq ++: (xLen == 64).option(new ZBS64Decode).toSeq ++: new ZBBSEDecode +: new ZBBCDecode +: (xLen == 64).option(new ZBBC64Decode).toSeq else Nil) ++: - (if (usingBitManip && !usingBitManipCrypto) (xLen == 32).option(new ZBBZE32Decode).toSeq ++: (xLen == 64).option(new ZBBZE64Decode).toSeq else Nil) ++: - (if (usingBitManip || usingBitManipCrypto) new ZBBNDecode +: new ZBCDecode +: new ZBBRDecode +: (xLen == 32).option(new ZBBR32Decode).toSeq ++: (xLen == 64).option(new ZBBR64Decode).toSeq ++: (xLen == 32).option(new ZBBREV832Decode).toSeq ++: (xLen == 64).option(new ZBBREV864Decode).toSeq else Nil) ++: - (if (usingBitManipCrypto) new ZBKXDecode +: new ZBKBDecode +: (xLen == 32).option(new ZBKB32Decode).toSeq ++: (xLen == 64).option(new ZBKB64Decode).toSeq else Nil) ++: - (if (usingCryptoNIST) (xLen == 32).option(new ZKND32Decode).toSeq ++: (xLen == 64).option(new ZKND64Decode).toSeq else Nil) ++: - (if (usingCryptoNIST) (xLen == 32).option(new ZKNE32Decode).toSeq ++: (xLen == 64).option(new ZKNE64Decode).toSeq else Nil) ++: - (if (usingCryptoNIST) new ZKNHDecode +: (xLen == 32).option(new ZKNH32Decode).toSeq ++: (xLen == 64).option(new ZKNH64Decode).toSeq else Nil) ++: - (usingCryptoSM.option(new ZKSDecode)) ++: (if (xLen == 32) new I32Decode(aluFn) else new I64Decode(aluFn)) +: (usingVM.option(new SVMDecode(aluFn))) ++: (usingSupervisor.option(new SDecode(aluFn))) ++: @@ -312,7 +298,6 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) - val id_illegal_rnum = if (usingCryptoNIST) (id_ctrl.zkn && aluFn.isKs1(id_ctrl.alu_fn) && id_inst(0)(23,20) > 0xA.U(4.W)) else false.B val id_illegal_insn = !id_ctrl.legal || (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') || id_ctrl.amo && !csr.io.status.isa('a'-'a') || @@ -324,8 +309,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) id_waddr_illegal && id_ctrl.wxd || id_ctrl.rocc && csr.io.decode(0).rocc_illegal || id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) || - !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) || - id_illegal_rnum + !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) || (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) @@ -409,7 +393,6 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S))) val alu = Module(aluFn match { - case _: ABLUFN => new ABLU case _: ALUFN => new ALU }) alu.io.dw := ex_ctrl.alu_dw @@ -417,34 +400,6 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt - val ex_zbk_wdata = if (!usingBitManipCrypto && !usingBitManip) 0.U else { - val zbk = Module(new BitManipCrypto(xLen)) - zbk.io.fn := ex_ctrl.alu_fn - zbk.io.dw := ex_ctrl.alu_dw - zbk.io.rs1 := ex_op1.asUInt - zbk.io.rs2 := ex_op2.asUInt - zbk.io.rd - } - - val ex_zkn_wdata = if (!usingCryptoNIST) 0.U else { - val zkn = Module(new CryptoNIST(xLen)) - zkn.io.fn := ex_ctrl.alu_fn - zkn.io.hl := ex_reg_inst(27) - zkn.io.bs := ex_reg_inst(31,30) - zkn.io.rs1 := ex_op1.asUInt - zkn.io.rs2 := ex_op2.asUInt - zkn.io.rd - } - - val ex_zks_wdata = if (!usingCryptoSM) 0.U else { - val zks = Module(new CryptoSM(xLen)) - zks.io.fn := ex_ctrl.alu_fn - zks.io.bs := ex_reg_inst(31,30) - zks.io.rs1 := ex_op1.asUInt - zks.io.rs2 := ex_op2.asUInt - zks.io.rd - } - // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen, aluFn = aluFn)) div.io.req.valid := ex_reg_valid && ex_ctrl.div @@ -591,13 +546,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H - mem_reg_wdata := Mux1H(Seq( - ex_ctrl.zbk -> ex_zbk_wdata, - ex_ctrl.zkn -> ex_zkn_wdata, - ex_ctrl.zks -> ex_zks_wdata, - (!ex_ctrl.zbk && !ex_ctrl.zkn && !ex_ctrl.zks) - -> alu.io.out, - )) + mem_reg_wdata := alu.io.out mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) { diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala index 7b4a8368ac1..a9dbf4307bb 100644 --- a/src/main/scala/subsystem/Configs.scala +++ b/src/main/scala/subsystem/Configs.scala @@ -408,38 +408,6 @@ class WithFPUWithoutDivSqrt extends Config((site, here, up) => { } }) -class WithBitManip extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(useBitManip = true))) - case t => t - } -}) - -class WithBitManipCrypto extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(useBitManipCrypto = true))) - case t => t - } -}) - -class WithCryptoNIST extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(useCryptoNIST = true))) - case t => t - } -}) - -class WithCryptoSM extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(useCryptoSM = true))) - case t => t - } -}) - class WithRocketDebugROB(enable: Boolean = true) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala index bb418b9ec9d..9fb7debde82 100644 --- a/src/main/scala/system/Configs.scala +++ b/src/main/scala/system/Configs.scala @@ -27,9 +27,6 @@ class DefaultSmallConfig extends Config(new WithNSmallCores(1) ++ new WithCohere class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig) class DefaultFP16Config extends Config(new WithFP16 ++ new DefaultConfig) -class BitManipCryptoConfig extends Config(new WithBitManip ++ new WithCryptoNIST ++ new WithCryptoSM ++ new DefaultConfig) -class BitManipCrypto32Config extends Config(new WithBitManip ++ new WithCryptoNIST ++ new WithCryptoSM ++ new DefaultRV32Config) - class HypervisorConfig extends Config(new WithHypervisor ++ new DefaultConfig) class DualBankConfig extends Config(new WithNBanks(2) ++ new DefaultConfig) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index df20aa0aa23..4182752d77c 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -113,11 +113,6 @@ trait HasNonDiplomaticTileParameters { Option.when(tileParams.core.useConditionalZero)(Seq("zicond")) ++ Some(Seq("zicsr", "zifencei", "zihpm")) ++ Option.when(tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen >= 16 && tileParams.core.fpu.get.minFLen <= 16)(Seq("zfh")) ++ - Option.when(tileParams.core.useBitManip)(Seq("zba", "zbb", "zbc")) ++ - Option.when(tileParams.core.hasBitManipCrypto)(Seq("zbkb", "zbkc", "zbkx")) ++ - Option.when(tileParams.core.useBitManip)(Seq("zbs")) ++ - Option.when(tileParams.core.useCryptoNIST)(Seq("zknd", "zkne", "zknh")) ++ - Option.when(tileParams.core.useCryptoSM)(Seq("zksed", "zksh")) ++ tileParams.core.customIsaExt.map(Seq(_)) ).flatten val multiLetterString = multiLetterExt.mkString("_") diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala index bb4d7abf6ae..f6981892dca 100644 --- a/src/main/scala/tile/Core.scala +++ b/src/main/scala/tile/Core.scala @@ -22,11 +22,7 @@ trait CoreParams { val useAtomics: Boolean val useAtomicsOnlyForIO: Boolean val useCompressed: Boolean - val useBitManip: Boolean - val useBitManipCrypto: Boolean val useVector: Boolean = false - val useCryptoNIST: Boolean - val useCryptoSM: Boolean val useRVE: Boolean val useConditionalZero: Boolean val mulDiv: Option[MulDivParams] @@ -59,7 +55,6 @@ trait CoreParams { def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs def hasSupervisorMode: Boolean = useSupervisor || useVM - def hasBitManipCrypto: Boolean = useBitManipCrypto || useCryptoNIST || useCryptoSM def instBytes: Int = instBits / 8 def fetchBytes: Int = fetchWidth * instBytes def lrscCycles: Int @@ -85,11 +80,7 @@ trait HasCoreParameters extends HasTileParameters { val usingAtomicsOnlyForIO = coreParams.useAtomicsOnlyForIO val usingAtomicsInCache = usingAtomics && !usingAtomicsOnlyForIO val usingCompressed = coreParams.useCompressed - val usingBitManip = coreParams.useBitManip - val usingBitManipCrypto = coreParams.hasBitManipCrypto val usingVector = coreParams.useVector - val usingCryptoNIST = coreParams.useCryptoNIST - val usingCryptoSM = coreParams.useCryptoSM val usingNMI = coreParams.useNMI val usingConditionalZero = coreParams.useConditionalZero diff --git a/src/main/scala/util/BarrelShifter.scala b/src/main/scala/util/BarrelShifter.scala index cd6e439d692..e69de29bb2d 100644 --- a/src/main/scala/util/BarrelShifter.scala +++ b/src/main/scala/util/BarrelShifter.scala @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -// FIXME: use chisel3.stdlib.BarrelShifter after chisel3 3.6.0 -package freechips.rocketchip.util - -import chisel3._ -import chisel3.util.{Mux1H, UIntToOH} - -/** A Barrel Shifter implementation for Vec type. - * - * @param inputs input signal to be shifted, should be a [[Vec]] type. - * @param shiftInput input signal to indicate the shift number, encoded in UInt. - * @param shiftGranularity how many bits will be resolved in each layer. - * For a smaller `shiftGranularity`, latency will be high, but area is smaller. - * For a large `shiftGranularity`, latency will be low, but area is higher. - * - * @example {{{ - * val input = 0xAABBCCDD.U(32.W) - * val bytes = VecInit(input.asBools.grouped(8).map(VecInit(_).asUInt).toSeq) - * val shamt = 1.U(2.W) - * val output = BarrelShifter.leftRotate(bytes, shamt).asUInt // big endian - * // output = 0xDDAABBCC.U(32.W) - * // The depth of Mux is 2, whereas originally - * // the depth of Mux is log(32) = 5 - * val output = BarrelShifter.leftRotate(bytes, shamt, 2).asUInt // depth is 1 now - * }}} - */ -object BarrelShifter { - private trait ShiftType - - private object LeftShift extends ShiftType - - private object RightShift extends ShiftType - - private object LeftRotate extends ShiftType - - private object RightRotate extends ShiftType - - private def apply[T <: Data]( - inputs: Vec[T], - shiftInput: UInt, - shiftType: ShiftType, - shiftGranularity: Int = 1 - ): Vec[T] = { - require(shiftGranularity > 0) - val elementType: T = chiselTypeOf(inputs.head) - shiftInput.asBools - .grouped(shiftGranularity) - .map(VecInit(_).asUInt) - .zipWithIndex - .foldLeft(inputs) { - case (prev, (shiftBits, layer)) => - Mux1H( - UIntToOH(shiftBits), - Seq.tabulate(1 << shiftBits.getWidth)(i => { - // For each layer of barrel shifter, it needs to - // Mux between shift 0 and i * 2^(depthOfLayer*granularity) - // - // e.g, when depth = 2 and granu = 1, the first layer Mux between 0 and 1 - // while the second layer Mux between 0 and 2, thus Vec.shift(UInt(2.W)) - // - // e.g, when depth = 2 and granu = 2, the first layer Mux between 0, 1, 2 and 3 - // while the second layer Mux between 0, 4, 8, and 12, thus achieving Vec.shift(UInt(4.W)) - // - // Also, shift no more than inputs length since prev.drop will not warn about overflow - // this is for Vec with length not the exponential of 2, e.g. 13 - val layerShift: Int = (i * (1 << (layer * shiftGranularity))).min(prev.length) - VecInit(shiftType match { - case LeftRotate => - prev.drop(layerShift) ++ prev.take(layerShift) - case LeftShift => - prev.drop(layerShift) ++ Seq.fill(layerShift)(0.U.asTypeOf(elementType)) - case RightRotate => - prev.takeRight(layerShift) ++ prev.dropRight(layerShift) - case RightShift => - Seq.fill(layerShift)(0.U.asTypeOf(elementType)) ++ prev.dropRight(layerShift) - }) - }) - ) - } - } - - def leftShift[T <: Data](inputs: Vec[T], shift: UInt, layerSize: Int = 1): Vec[T] = - apply(inputs, shift, LeftShift, layerSize) - - def rightShift[T <: Data](inputs: Vec[T], shift: UInt, layerSize: Int = 1): Vec[T] = - apply(inputs, shift, RightShift, layerSize) - - def leftRotate[T <: Data](inputs: Vec[T], shift: UInt, layerSize: Int = 1): Vec[T] = - apply(inputs, shift, LeftRotate, layerSize) - - def rightRotate[T <: Data](inputs: Vec[T], shift: UInt, layerSize: Int = 1): Vec[T] = - apply(inputs, shift, RightRotate, layerSize) -} diff --git a/src/main/scala/util/SBox.scala b/src/main/scala/util/SBox.scala deleted file mode 100644 index 210e7ab6185..00000000000 --- a/src/main/scala/util/SBox.scala +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// -// This is translated from https://github.com/riscv/riscv-crypto -// -// 2020-01-29 Markku-Juhani O. Saarinen -// Copyright (c) 2020, PQShield Ltd. All rights reserved. -// Converted to Chisel in 2022 - -/* - [BoPe12] Boyar J., Peralta R. "A Small Depth-16 Circuit for the AES - S-Box." Proc.SEC 2012. IFIP AICT 376. Springer, pp. 287-298 (2012) - DOI: https://doi.org/10.1007/978-3-642-30436-1_24 - Preprint: https://eprint.iacr.org/2011/332.pdf - - [Ny93] Nyberg K., "Differentially Uniform Mappings for Cryptography", - Proc. EUROCRYPT '93, LNCS 765, Springer, pp. 55-64 (1993) - DOI: https://doi.org/10.1007/3-540-48285-7_6 -*/ - -package freechips.rocketchip.util - -import chisel3._ - -// top (inner) linear layer for AES -object SBoxAESEncIn { - def apply(x: UInt): UInt = { - val t = Wire(Vec(6, Bool())) - val y = Wire(Vec(21, Bool())) - t( 0) := x( 3) ^ x( 1) - t( 1) := x( 6) ^ x( 5) - t( 2) := x( 6) ^ x( 2) - t( 3) := x( 5) ^ x( 2) - t( 4) := x( 4) ^ x( 0) - t( 5) := x( 1) ^ x( 0) - y( 0) := x( 0) - y( 1) := x( 7) ^ x( 4) - y( 2) := x( 7) ^ x( 2) - y( 3) := x( 7) ^ x( 1) - y( 4) := x( 4) ^ x( 2) - y( 5) := y( 1) ^ t( 0) - y( 6) := x( 0) ^ y( 5) - y( 7) := x( 0) ^ t( 1) - y( 8) := y( 5) ^ t( 1) - y( 9) := y( 3) ^ y( 4) - y(10) := y( 5) ^ t( 2) - y(11) := t( 0) ^ t( 2) - y(12) := t( 0) ^ t( 3) - y(13) := y( 7) ^ y(12) - y(14) := t( 1) ^ t( 4) - y(15) := y( 1) ^ y(14) - y(16) := t( 1) ^ t( 5) - y(17) := y( 2) ^ y(16) - y(18) := y( 2) ^ y( 8) - y(19) := y(15) ^ y(13) - y(20) := y( 1) ^ t( 3) - y.asUInt - } -} - -// top (inner) linear layer for AES^-1 -object SBoxAESDecIn { - def apply(x: UInt): UInt = { - val t = Wire(Vec(5, Bool())) - val y = Wire(Vec(21, Bool())) - t( 0) := x( 1) ^ x( 0) - t( 1) := x( 6) ^ x( 1) - t( 2) := x( 5) ^ ~x( 2) - t( 3) := x( 2) ^ ~x( 1) - t( 4) := x( 5) ^ ~x( 3) - y( 0) := x( 7) ^ t( 2) - y( 1) := x( 4) ^ x( 3) - y( 2) := x( 7) ^ ~x( 6) - y( 3) := y( 1) ^ t( 0) - y( 4) := x( 3) ^ y( 6) - y( 5) := y(16) ^ t( 2) - y( 6) := x( 6) ^ ~y(17) - y( 7) := x( 0) ^ ~y( 1) - y( 8) := y( 2) ^ y(18) - y( 9) := y( 2) ^ t( 0) - y(10) := y( 8) ^ t( 3) - y(11) := y( 8) ^ y(20) - y(12) := t( 1) ^ t( 4) - y(13) := x( 5) ^ ~y(14) - y(14) := y(16) ^ t( 0) - y(15) := y(18) ^ t( 1) - y(16) := x( 6) ^ ~x( 4) - y(17) := x( 7) ^ x( 4) - y(18) := x( 3) ^ ~x( 0) - y(19) := x( 5) ^ ~y( 1) - y(20) := y( 1) ^ t( 3) - y.asUInt - } -} - -// top (inner) linear layer for SM4 -object SBoxSM4In { - def apply(x: UInt): UInt = { - val t = Wire(Vec(7, Bool())) - val y = Wire(Vec(21, Bool())) - t( 0) := x(3) ^ x( 4) - t( 1) := x(2) ^ x( 7) - t( 2) := x(7) ^ y(18) - t( 3) := x(1) ^ t( 1) - t( 4) := x(6) ^ x( 7) - t( 5) := x(0) ^ y(18) - t( 6) := x(3) ^ x( 6) - y( 0) := x(5) ^ ~y(10) - y( 1) := t(0) ^ t( 3) - y( 2) := x(0) ^ t( 0) - y( 3) := x(3) ^ y( 4) - y( 4) := x(0) ^ t( 3) - y( 5) := x(5) ^ t( 5) - y( 6) := x(0) ^ ~x( 1) - y( 7) := t(0) ^ ~y(10) - y( 8) := t(0) ^ t( 5) - y( 9) := x(3) - y(10) := x(1) ^ y(18) - y(11) := t(0) ^ t( 4) - y(12) := x(5) ^ t( 4) - y(13) := x(5) ^ ~y( 1) - y(14) := x(4) ^ ~t( 2) - y(15) := x(1) ^ ~t( 6) - y(16) := x(0) ^ ~t( 2) - y(17) := t(0) ^ ~t( 2) - y(18) := x(2) ^ x( 6) - y(19) := x(5) ^ ~y(14) - y(20) := x(0) ^ t( 1) - y.asUInt - } -} - -// The shared non-linear middle part for AES, AES^-1, and SM4. -object SBoxMid { - def apply(x: UInt): UInt = { - val t = Wire(Vec(46, Bool())) - val y = Wire(Vec(18, Bool())) - t( 0) := x( 3) ^ x(12) - t( 1) := x( 9) & x( 5) - t( 2) := x(17) & x( 6) - t( 3) := x(10) ^ t( 1) - t( 4) := x(14) & x( 0) - t( 5) := t( 4) ^ t( 1) - t( 6) := x( 3) & x(12) - t( 7) := x(16) & x( 7) - t( 8) := t( 0) ^ t( 6) - t( 9) := x(15) & x(13) - t(10) := t( 9) ^ t( 6) - t(11) := x( 1) & x(11) - t(12) := x( 4) & x(20) - t(13) := t(12) ^ t(11) - t(14) := x( 2) & x( 8) - t(15) := t(14) ^ t(11) - t(16) := t( 3) ^ t( 2) - t(17) := t( 5) ^ x(18) - t(18) := t( 8) ^ t( 7) - t(19) := t(10) ^ t(15) - t(20) := t(16) ^ t(13) - t(21) := t(17) ^ t(15) - t(22) := t(18) ^ t(13) - t(23) := t(19) ^ x(19) - t(24) := t(22) ^ t(23) - t(25) := t(22) & t(20) - t(26) := t(21) ^ t(25) - t(27) := t(20) ^ t(21) - t(28) := t(23) ^ t(25) - t(29) := t(28) & t(27) - t(30) := t(26) & t(24) - t(31) := t(20) & t(23) - t(32) := t(27) & t(31) - t(33) := t(27) ^ t(25) - t(34) := t(21) & t(22) - t(35) := t(24) & t(34) - t(36) := t(24) ^ t(25) - t(37) := t(21) ^ t(29) - t(38) := t(32) ^ t(33) - t(39) := t(23) ^ t(30) - t(40) := t(35) ^ t(36) - t(41) := t(38) ^ t(40) - t(42) := t(37) ^ t(39) - t(43) := t(37) ^ t(38) - t(44) := t(39) ^ t(40) - t(45) := t(42) ^ t(41) - y( 0) := t(38) & x( 7) - y( 1) := t(37) & x(13) - y( 2) := t(42) & x(11) - y( 3) := t(45) & x(20) - y( 4) := t(41) & x( 8) - y( 5) := t(44) & x( 9) - y( 6) := t(40) & x(17) - y( 7) := t(39) & x(14) - y( 8) := t(43) & x( 3) - y( 9) := t(38) & x(16) - y(10) := t(37) & x(15) - y(11) := t(42) & x( 1) - y(12) := t(45) & x( 4) - y(13) := t(41) & x( 2) - y(14) := t(44) & x( 5) - y(15) := t(40) & x( 6) - y(16) := t(39) & x( 0) - y(17) := t(43) & x(12) - y.asUInt - } -} - -// bottom (outer) linear layer for AES -object SBoxAESEncOut { - def apply(x: UInt): UInt = { - val t = Wire(Vec(30, Bool())) - val y = Wire(Vec(8, Bool())) - t( 0) := x(11) ^ x(12) - t( 1) := x( 0) ^ x( 6) - t( 2) := x(14) ^ x(16) - t( 3) := x(15) ^ x( 5) - t( 4) := x( 4) ^ x( 8) - t( 5) := x(17) ^ x(11) - t( 6) := x(12) ^ t( 5) - t( 7) := x(14) ^ t( 3) - t( 8) := x( 1) ^ x( 9) - t( 9) := x( 2) ^ x( 3) - t(10) := x( 3) ^ t( 4) - t(11) := x(10) ^ t( 2) - t(12) := x(16) ^ x( 1) - t(13) := x( 0) ^ t( 0) - t(14) := x( 2) ^ x(11) - t(15) := x( 5) ^ t( 1) - t(16) := x( 6) ^ t( 0) - t(17) := x( 7) ^ t( 1) - t(18) := x( 8) ^ t( 8) - t(19) := x(13) ^ t( 4) - t(20) := t( 0) ^ t( 1) - t(21) := t( 1) ^ t( 7) - t(22) := t( 3) ^ t(12) - t(23) := t(18) ^ t( 2) - t(24) := t(15) ^ t( 9) - t(25) := t( 6) ^ t(10) - t(26) := t( 7) ^ t( 9) - t(27) := t( 8) ^ t(10) - t(28) := t(11) ^ t(14) - t(29) := t(11) ^ t(17) - y( 0) := t( 6) ^ ~t(23) - y( 1) := t(13) ^ ~t(27) - y( 2) := t(25) ^ t(29) - y( 3) := t(20) ^ t(22) - y( 4) := t( 6) ^ t(21) - y( 5) := t(19) ^ ~t(28) - y( 6) := t(16) ^ ~t(26) - y( 7) := t( 6) ^ t(24) - y.asUInt - } -} - -// bottom (outer) linear layer for AES^-1 -object SBoxAESDecOut { - def apply(x: UInt): UInt = { - val t = Wire(Vec(30, Bool())) - val y = Wire(Vec(8, Bool())) - t( 0) := x( 2) ^ x(11) - t( 1) := x( 8) ^ x( 9) - t( 2) := x( 4) ^ x(12) - t( 3) := x(15) ^ x( 0) - t( 4) := x(16) ^ x( 6) - t( 5) := x(14) ^ x( 1) - t( 6) := x(17) ^ x(10) - t( 7) := t( 0) ^ t( 1) - t( 8) := x( 0) ^ x( 3) - t( 9) := x( 5) ^ x(13) - t(10) := x( 7) ^ t( 4) - t(11) := t( 0) ^ t( 3) - t(12) := x(14) ^ x(16) - t(13) := x(17) ^ x( 1) - t(14) := x(17) ^ x(12) - t(15) := x( 4) ^ x( 9) - t(16) := x( 7) ^ x(11) - t(17) := x( 8) ^ t( 2) - t(18) := x(13) ^ t( 5) - t(19) := t( 2) ^ t( 3) - t(20) := t( 4) ^ t( 6) - t(21) := 0.U - t(22) := t( 2) ^ t( 7) - t(23) := t( 7) ^ t( 8) - t(24) := t( 5) ^ t( 7) - t(25) := t( 6) ^ t(10) - t(26) := t( 9) ^ t(11) - t(27) := t(10) ^ t(18) - t(28) := t(11) ^ t(25) - t(29) := t(15) ^ t(20) - y( 0) := t( 9) ^ t(16) - y( 1) := t(14) ^ t(23) - y( 2) := t(19) ^ t(24) - y( 3) := t(23) ^ t(27) - y( 4) := t(12) ^ t(22) - y( 5) := t(17) ^ t(28) - y( 6) := t(26) ^ t(29) - y( 7) := t(13) ^ t(22) - y.asUInt - } -} - -// bottom (outer) linear layer for SM4 -object SBoxSM4Out { - def apply(x: UInt): UInt = { - val t = Wire(Vec(30, Bool())) - val y = Wire(Vec(8, Bool())) - t( 0) := x( 4) ^ x( 7) - t( 1) := x(13) ^ x(15) - t( 2) := x( 2) ^ x(16) - t( 3) := x( 6) ^ t( 0) - t( 4) := x(12) ^ t( 1) - t( 5) := x( 9) ^ x(10) - t( 6) := x(11) ^ t( 2) - t( 7) := x( 1) ^ t( 4) - t( 8) := x( 0) ^ x(17) - t( 9) := x( 3) ^ x(17) - t(10) := x( 8) ^ t( 3) - t(11) := t( 2) ^ t( 5) - t(12) := x(14) ^ t( 6) - t(13) := t( 7) ^ t( 9) - t(14) := x( 0) ^ x( 6) - t(15) := x( 7) ^ x(16) - t(16) := x( 5) ^ x(13) - t(17) := x( 3) ^ x(15) - t(18) := x(10) ^ x(12) - t(19) := x( 9) ^ t( 1) - t(20) := x( 4) ^ t( 4) - t(21) := x(14) ^ t( 3) - t(22) := x(16) ^ t( 5) - t(23) := t( 7) ^ t(14) - t(24) := t( 8) ^ t(11) - t(25) := t( 0) ^ t(12) - t(26) := t(17) ^ t( 3) - t(27) := t(18) ^ t(10) - t(28) := t(19) ^ t( 6) - t(29) := t( 8) ^ t(10) - y( 0) := t(11) ^ ~t(13) - y( 1) := t(15) ^ ~t(23) - y( 2) := t(20) ^ t(24) - y( 3) := t(16) ^ t(25) - y( 4) := t(26) ^ ~t(22) - y( 5) := t(21) ^ t(13) - y( 6) := t(27) ^ ~t(12) - y( 7) := t(28) ^ ~t(29) - y.asUInt - } -} From df66c19e873fbc74214082f512a1cbb7a15087e7 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Fri, 24 Nov 2023 01:32:54 +0800 Subject: [PATCH 16/18] remove vMemDataBits check --- src/main/scala/tile/Core.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala index f6981892dca..259560f8b1e 100644 --- a/src/main/scala/tile/Core.scala +++ b/src/main/scala/tile/Core.scala @@ -113,7 +113,6 @@ trait HasCoreParameters extends HasTileParameters { if (usingVector) { require(isPow2(vLen), s"vLen ($vLen) must be a power of 2") require(eLen >= 32 && vLen % eLen == 0, s"eLen must divide vLen ($vLen) and be no less than 32") - require(vMemDataBits >= eLen && vLen % vMemDataBits == 0, s"vMemDataBits ($vMemDataBits) must divide vLen ($vLen) and be no less than eLen ($eLen)") } lazy val hartIdLen: Int = p(MaxHartIdBits) From 74dd9b19d0bc911670f8e7a50178bd946c3200cf Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Fri, 24 Nov 2023 01:41:12 +0800 Subject: [PATCH 17/18] remove vector on dcache port --- src/main/scala/tile/BaseTile.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 4182752d77c..1fb447317b8 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -93,7 +93,7 @@ trait HasNonDiplomaticTileParameters { // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors - def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + tileParams.core.useVector.toInt + def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size // TODO merge with isaString in CSR.scala def isaDTS: String = { From 5bef59a8cfafdadf43b75eb59714a9134d9b53ff Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sat, 25 Nov 2023 16:47:25 +0800 Subject: [PATCH 18/18] add vectorUseDCache parameter --- src/main/scala/tile/BaseTile.scala | 2 +- src/main/scala/tile/Core.scala | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 1fb447317b8..448050a0d50 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -93,7 +93,7 @@ trait HasNonDiplomaticTileParameters { // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors - def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt // TODO merge with isaString in CSR.scala def isaDTS: String = { diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala index 259560f8b1e..8c9018da50a 100644 --- a/src/main/scala/tile/Core.scala +++ b/src/main/scala/tile/Core.scala @@ -23,6 +23,7 @@ trait CoreParams { val useAtomicsOnlyForIO: Boolean val useCompressed: Boolean val useVector: Boolean = false + val vectorUseDCache: Boolean = false val useRVE: Boolean val useConditionalZero: Boolean val mulDiv: Option[MulDivParams]