From 54ff5559f592372fb393cacade267a8f026bcd29 Mon Sep 17 00:00:00 2001
From: Sungkeun Kim <sk84.kim@samsung.com>
Date: Thu, 18 Jul 2024 10:53:23 +0900
Subject: [PATCH]  Add IO Connections for Custom User Field in TL Channels
 within Xbar  DontCare should come first before waiveAll so that matching
 userfield  bewteen bundles can be connected  Please refer to the issue page
 below.  https://github.com/ucb-bar/chipyard/issues/1888

---
 src/main/scala/tilelink/Xbar.scala | 32 ++++--------------------------
 1 file changed, 4 insertions(+), 28 deletions(-)

diff --git a/src/main/scala/tilelink/Xbar.scala b/src/main/scala/tilelink/Xbar.scala
index e6c16d94484..09a5ff15476 100644
--- a/src/main/scala/tilelink/Xbar.scala
+++ b/src/main/scala/tilelink/Xbar.scala
@@ -157,14 +157,8 @@ object TLXbar
       val r = inputIdRanges(i)
 
       if (connectAIO(i).exists(x=>x)) {
-        in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
         in(i).a.bits.user := DontCare
-        // If there are user defined bundles in both sides, connect them.
-        io_in(i).a.bits.user.keydata.foreach { case (io_in_key, io_in_bundle) =>
-          in(i).a.bits.user.lift(io_in_key).foreach { in_bundle =>
-            in_bundle <> io_in_bundle
-          }
-        }
+        in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
         in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
       } else {
         in(i).a := DontCare
@@ -184,14 +178,8 @@ object TLXbar
       }
 
       if (connectCIO(i).exists(x=>x)) {
-        in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
         in(i).c.bits.user := DontCare
-        // If there are user defined bundles in both sides, connect them.
-        io_in(i).c.bits.user.keydata.foreach { case (io_in_key, io_in_bundle) =>
-          in(i).c.bits.user.lift(io_in_key).foreach { in_bundle =>
-            in_bundle <> io_in_bundle
-          }
-        }
+        in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
         in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
       } else {
         in(i).c := DontCare
@@ -226,14 +214,8 @@ object TLXbar
       val r = outputIdRanges(o)
 
       if (connectAOI(o).exists(x=>x)) {
-        io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
         out(o).a.bits.user := DontCare
-        // If there are user defined bundles in both sides, connect them.
-        out(o).a.bits.user.keydata.foreach { case (out_key, out_bundle) =>
-          io_out(o).a.bits.user.lift(out_key).foreach { io_out_bundle =>
-            io_out_bundle <> out_bundle
-          }
-        }
+        io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
       } else {
         out(o).a := DontCare
         io_out(o).a := DontCare
@@ -251,14 +233,8 @@ object TLXbar
       }
 
       if (connectCOI(o).exists(x=>x)) {
-        io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
         out(o).c.bits.user := DontCare
-        // If there are user defined bundles in both sides, connect them.
-        out(o).c.bits.user.keydata.foreach { case (out_key, out_bundle) =>
-          io_out(o).c.bits.user.lift(out_key).foreach { io_out_bundle =>
-            io_out_bundle <> out_bundle
-          }
-        }
+        io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
       } else {
         out(o).c  := DontCare
         io_out(o).c  := DontCare