diff --git a/src/main/scala/devices/tilelink/PhysicalFilter.scala b/src/main/scala/devices/tilelink/PhysicalFilter.scala
index 24570d19e99..c56bfeb4bc3 100644
--- a/src/main/scala/devices/tilelink/PhysicalFilter.scala
+++ b/src/main/scala/devices/tilelink/PhysicalFilter.scala
@@ -240,7 +240,7 @@ class PhysicalFilter(params: PhysicalFilterParams)(implicit p: Parameters) exten
 
       // Frame an appropriate deny message
       val denyValid = RegInit(false.B)
-      val deny = Reg(in.d.bits)
+      val deny = Reg(chiselTypeOf(in.d.bits))
       val d_opcode = TLMessages.adResponse(in.a.bits.opcode)
       val d_grant = edgeIn.manager.anySupportAcquireB.B && deny.opcode === TLMessages.Grant
       when (in.a.valid && !allow && deny_ready && a_first) {
@@ -262,7 +262,7 @@ class PhysicalFilter(params: PhysicalFilterParams)(implicit p: Parameters) exten
         }
       }
 
-      val out_d = Wire(in.d.bits)
+      val out_d = Wire(chiselTypeOf(in.d.bits))
       out_d := out.d.bits
 
       // Deny can have unconditional priority, because the only out.d message possible is
diff --git a/src/main/scala/tilelink/Xbar.scala b/src/main/scala/tilelink/Xbar.scala
index 3ef0047bb12..4d6c9ef7b63 100644
--- a/src/main/scala/tilelink/Xbar.scala
+++ b/src/main/scala/tilelink/Xbar.scala
@@ -161,8 +161,8 @@ object TLXbar
       val r = inputIdRanges(i)
 
       if (connectAIO(i).exists(x=>x)) {
-        in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
         in(i).a.bits.user := DontCare
+        in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
         in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
       } else {
         in(i).a := DontCare
@@ -182,8 +182,8 @@ object TLXbar
       }
 
       if (connectCIO(i).exists(x=>x)) {
-        in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
         in(i).c.bits.user := DontCare
+        in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
         in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
       } else {
         in(i).c := DontCare
@@ -218,8 +218,8 @@ object TLXbar
       val r = outputIdRanges(o)
 
       if (connectAOI(o).exists(x=>x)) {
-        io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
         out(o).a.bits.user := DontCare
+        io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
       } else {
         out(o).a := DontCare
         io_out(o).a := DontCare
@@ -237,8 +237,8 @@ object TLXbar
       }
 
       if (connectCOI(o).exists(x=>x)) {
-        io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
         out(o).c.bits.user := DontCare
+        io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
       } else {
         out(o).c  := DontCare
         io_out(o).c  := DontCare