diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
index ee3cec6f751..1dddf253c02 100644
--- a/src/main/scala/rocket/RocketCore.scala
+++ b/src/main/scala/rocket/RocketCore.scala
@@ -919,7 +919,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
 
       DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata)
     } else { // synthesizable ROB (no FPRs)
-      require(!usingVector)
+      require(!usingVector, "Synthesizable ROB does not support vector implementations")
       val csr_trace_with_wdata = WireInit(csr.io.trace(0))
       csr_trace_with_wdata.wdata.get := rf_wdata