diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
index 605a5fd12b3..6ddfada6540 100644
--- a/src/main/scala/rocket/RocketCore.scala
+++ b/src/main/scala/rocket/RocketCore.scala
@@ -70,6 +70,7 @@ case class RocketCoreParams(
   override def vLen = vector.map(_.vLen).getOrElse(0)
   override def eLen = vector.map(_.eLen).getOrElse(0)
   override def vfLen = vector.map(_.vfLen).getOrElse(0)
+  override def vfh = vector.map(_.vfh).getOrElse(false)
   override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0)
   override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction
   override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32)
diff --git a/src/main/scala/rocket/VectorUnit.scala b/src/main/scala/rocket/VectorUnit.scala
index db476e25e9b..870d99c25a6 100644
--- a/src/main/scala/rocket/VectorUnit.scala
+++ b/src/main/scala/rocket/VectorUnit.scala
@@ -12,6 +12,7 @@ case class RocketCoreVectorParams(
   vLen: Int,
   eLen: Int,
   vfLen: Int,
+  vfh: Boolean,
   vMemDataBits: Int,
   decoder: Parameters => RocketVectorDecoder,
   useDCache: Boolean,
diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala
index 4e0c5d3b49d..00cfb9306b6 100644
--- a/src/main/scala/tile/BaseTile.scala
+++ b/src/main/scala/tile/BaseTile.scala
@@ -115,6 +115,8 @@ trait HasNonDiplomaticTileParameters {
       }
       Seq(s"zve${tileParams.core.eLen}$c")
     }
+    val zvfh = Option.when(tileParams.core.useVector && tileParams.core.vfh) { Seq("zvfh") }
+
     val multiLetterExt = (
       // rdcycle[h], rdinstret[h] is implemented
       // rdtime[h] is not implemented, and could be provided by software emulation
@@ -123,8 +125,7 @@ trait HasNonDiplomaticTileParameters {
       Option.when(tileParams.core.useConditionalZero)(Seq("zicond")) ++
       Some(Seq("zicsr", "zifencei", "zihpm")) ++
       Option.when(tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen >= 16 && tileParams.core.fpu.get.minFLen <= 16)(Seq("zfh")) ++
-      zvl ++
-      zve ++
+      zvl ++ zve ++ zvfh ++
       tileParams.core.customIsaExt.map(Seq(_))
     ).flatten
     val multiLetterString = multiLetterExt.mkString("_")
diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
index 603eba21523..67981a387a7 100644
--- a/src/main/scala/tile/Core.scala
+++ b/src/main/scala/tile/Core.scala
@@ -68,6 +68,7 @@ trait CoreParams {
   def vLen: Int = 0
   def eLen: Int = 0
   def vfLen: Int = 0
+  def vfh: Boolean = false
   def hasV: Boolean = vLen >= 128 && eLen >= 64 && vfLen >= 64
   def vMemDataBits: Int = 0
 }
@@ -119,6 +120,7 @@ trait HasCoreParameters extends HasTileParameters {
     require(eLen >= 32 && vLen % eLen == 0, s"eLen must divide vLen ($vLen) and be no less than 32")
     require(eLen == 32 || eLen == 64)
     require(vfLen <= eLen)
+    require(!coreParams.vfh || (vfLen >= 32 && coreParams.minFLen <= 16))
   }
 
   if (coreParams.useVM) {
diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
index 58dd4917646..1affeb48769 100644
--- a/src/main/scala/tile/FPU.scala
+++ b/src/main/scala/tile/FPU.scala
@@ -472,23 +472,23 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetime
   dcmp.io.signaling := !in.rm(1)
 
   val tag = in.typeTagOut
-  val store = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen,   ieee(in.in1)(15, 0).sextTo(minXLen))
-                                   else              Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
+  val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen,   ieee(in.in1)(15, 0).sextTo(minXLen))
+                                        else              Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
 
-  val toint = WireDefault(store)
+  val toint = WireDefault(toint_ieee)
   val intType = WireDefault(in.fmt(0))
-  io.out.bits.store := store
+  io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
   io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
   io.out.bits.exc := 0.U
 
   when (in.rm(0)) {
     val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
-    toint := classify_out | (store >> minXLen << minXLen)
+    toint := classify_out | (toint_ieee >> minXLen << minXLen)
     intType := false.B
   }
 
   when (in.wflags) { // feq/flt/fle, fcvt
-    toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (store >> minXLen << minXLen)
+    toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
     io.out.bits.exc := dcmp.io.exceptionFlags
     intType := false.B