From 0306b3a4aaa5a33ba17733fa37009b01c3ea3831 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sun, 25 Feb 2024 17:56:42 +0800 Subject: [PATCH] purge xbus to migrate to location API --- src/main/scala/devices/tilelink/CLINT.scala | 2 +- .../groundtest/GroundTestSubsystem.scala | 4 +- src/main/scala/subsystem/BaseSubsystem.scala | 13 ++---- src/main/scala/subsystem/Ports.scala | 40 +++++++++---------- 4 files changed, 26 insertions(+), 33 deletions(-) diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala index d83bde22899..b85e08b4e01 100644 --- a/src/main/scala/devices/tilelink/CLINT.scala +++ b/src/main/scala/devices/tilelink/CLINT.scala @@ -105,7 +105,7 @@ trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) val clintDomainWrapper = tlbus.generateSynchronousDomain.suggestName("clint_domain") - val clint = clintDomainWrapper { LazyModule(new CLINT(params, cbus.beatBytes)) } + val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlBusWrapperLocationMap.lift(CBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus) := _ } } val clintTick = clintDomainWrapper { InModuleBody { val tick = IO(Input(Bool())) diff --git a/src/main/scala/groundtest/GroundTestSubsystem.scala b/src/main/scala/groundtest/GroundTestSubsystem.scala index 379ed58aaca..f45b3bb92a8 100644 --- a/src/main/scala/groundtest/GroundTestSubsystem.scala +++ b/src/main/scala/groundtest/GroundTestSubsystem.scala @@ -21,8 +21,8 @@ class GroundTestSubsystem(implicit p: Parameters) with HasTileInputConstants with CanHaveMasterAXI4MemPort { - val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), beatBytes=pbus.beatBytes)) - pbus.coupleTo("TestRAM") { testram.node := TLFragmenter(pbus) := _ } + val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), beatBytes=tlBusWrapperLocationMap.get(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).beatBytes)) + tlBusWrapperLocationMap.lift(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).coupleTo("TestRAM") { testram.node := TLFragmenter(tlBusWrapperLocationMap.lift(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))))) := _ } // No cores to monitor def coreMonitorBundles = Nil diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala index f2c8ebbf333..52435295eec 100644 --- a/src/main/scala/subsystem/BaseSubsystem.scala +++ b/src/main/scala/subsystem/BaseSubsystem.scala @@ -90,18 +90,11 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem) val busContextName = "subsystem" - val sbus = tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))) - tlBusWrapperLocationMap.lift(SBUS).map { _.clockGroupNode := allClockGroupsNode } + tlBusWrapperLocationMap.get(p(TLManagerViewpointLocated(location))).map { _.clockGroupNode := allClockGroupsNode } // TODO: Preserve legacy implicit-clock behavior for IBUS for now. If binding // a PLIC to the CBUS, ensure it is synchronously coupled to the SBUS. - ibus.clockNode := sbus.fixedClockNode - - // TODO deprecate these public members to see where users are manually hardcoding a particular bus that might actually not exist in a certain dynamic topology - val pbus = tlBusWrapperLocationMap.lift(PBUS).getOrElse(sbus) - val fbus = tlBusWrapperLocationMap.lift(FBUS).getOrElse(sbus) - val mbus = tlBusWrapperLocationMap.lift(MBUS).getOrElse(sbus) - val cbus = tlBusWrapperLocationMap.lift(CBUS).getOrElse(sbus) + ibus.clockNode := tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).fixedClockNode // Collect information for use in DTS ResourceBinding { @@ -141,7 +134,7 @@ abstract class BaseSubsystemModuleImp[+L <: BaseSubsystem](_outer: L) extends Ba Annotated.addressMapping(this, mapping) println("Generated Address Map") - mapping.map(entry => println(entry.toString((outer.sbus.busView.bundle.addressBits-1)/4 + 1))) + mapping.foreach(entry => println(entry.toString((outer.tlBusWrapperLocationMap(p(TLManagerViewpointLocated(outer.location))).busView.bundle.addressBits-1)/4 + 1))) println("") ElaborationArtefacts.add("memmap.json", s"""{"mapping":[${mapping.map(_.toJSON).mkString(",")}]}""") diff --git a/src/main/scala/subsystem/Ports.scala b/src/main/scala/subsystem/Ports.scala index 89fc25376fd..10cf2b9d460 100644 --- a/src/main/scala/subsystem/Ports.scala +++ b/src/main/scala/subsystem/Ports.scala @@ -40,7 +40,7 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem => val memAXI4Node = AXI4SlaveNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) => Seq.tabulate(nMemoryChannels) { channel => val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) - val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) + val filter = AddressSet(channel * tlBusWrapperLocationMap.lift(MBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).blockBytes, ~((nMemoryChannels-1) * tlBusWrapperLocationMap.lift(MBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).blockBytes)) AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( @@ -48,22 +48,22 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem => resources = device.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, - supportsWrite = TransferSizes(1, mbus.blockBytes), - supportsRead = TransferSizes(1, mbus.blockBytes), + supportsWrite = TransferSizes(1, tlBusWrapperLocationMap.lift(MBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).blockBytes), + supportsRead = TransferSizes(1, tlBusWrapperLocationMap.lift(MBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).blockBytes), interleavedId = Some(0))), // slave does not interleave read responses beatBytes = memPortParams.beatBytes) } }).toList.flatten) for (i <- 0 until memAXI4Node.portParams.size) { - val mem_bypass_xbar = mbus { TLXbar() } + val mem_bypass_xbar = tlBusWrapperLocationMap.lift(MBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))) { TLXbar() } // Create an incoherent alias for the AXI4 memory memPortParamsOpt.foreach(memPortParams => { memPortParams.incohBase.foreach(incohBase => { val cohRegion = AddressSet(0, incohBase-1) val incohRegion = AddressSet(incohBase, incohBase-1) - val replicator = sbus { + val replicator = tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))) { val replicator = LazyModule(new RegionReplicator(ReplicatedRegion(cohRegion, cohRegion.widen(incohBase)))) val prefixSource = BundleBridgeSource[UInt](() => UInt(1.W)) replicator.prefix := prefixSource @@ -71,9 +71,9 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem => InModuleBody { prefixSource.bundle := 0.U(1.W) } replicator } - sbus.coupleTo(s"memory_controller_bypass_port_named_$portName") { - (mbus.crossIn(mem_bypass_xbar)(ValName("bus_xing"))(p(SbusToMbusXTypeKey)) - := TLWidthWidget(sbus.beatBytes) + tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).coupleTo(s"memory_controller_bypass_port_named_$portName") { + (tlBusWrapperLocationMap.lift(MBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).crossIn(mem_bypass_xbar)(ValName("bus_xing"))(p(SbusToMbusXTypeKey)) + := TLWidthWidget(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).beatBytes) := replicator.node := TLFilter(TLFilter.mSubtract(cohRegion)) := TLFilter(TLFilter.mResourceRemover) @@ -83,12 +83,12 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem => }) }) - mbus.coupleTo(s"memory_controller_port_named_$portName") { + tlBusWrapperLocationMap.lift(MBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).coupleTo(s"memory_controller_port_named_$portName") { (memAXI4Node := AXI4UserYanker() := AXI4IdIndexer(idBits) := TLToAXI4() - := TLWidthWidget(mbus.beatBytes) + := TLWidthWidget(tlBusWrapperLocationMap.lift(MBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).beatBytes) := mem_bypass_xbar := _ ) @@ -116,14 +116,14 @@ trait CanHaveMasterAXI4MMIOPort { this: BaseSubsystem => beatBytes = params.beatBytes)).toSeq) mmioPortParamsOpt.map { params => - sbus.coupleTo(s"port_named_$portName") { + tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).coupleTo(s"port_named_$portName") { (mmioAXI4Node := AXI4Buffer() := AXI4UserYanker() - := AXI4Deinterleaver(sbus.blockBytes) + := AXI4Deinterleaver(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).blockBytes) := AXI4IdIndexer(params.idBits) := TLToAXI4() - := TLWidthWidget(sbus.beatBytes) + := TLWidthWidget(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).beatBytes) := _) } } @@ -145,7 +145,7 @@ trait CanHaveSlaveAXI4Port { this: BaseSubsystem => id = IdRange(0, 1 << params.idBits))))).toSeq) slavePortParamsOpt.map { params => - fbus.coupleFrom(s"port_named_$portName") { + tlBusWrapperLocationMap.get(FBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).coupleFrom(s"port_named_$portName") { ( _ := TLBuffer(BufferParams.default) := TLFIFOFixer(TLFIFOFixer.all) @@ -174,17 +174,17 @@ trait CanHaveMasterTLMMIOPort { this: BaseSubsystem => address = AddressSet.misaligned(params.base, params.size), resources = device.ranges, executable = params.executable, - supportsGet = TransferSizes(1, sbus.blockBytes), - supportsPutFull = TransferSizes(1, sbus.blockBytes), - supportsPutPartial = TransferSizes(1, sbus.blockBytes))), + supportsGet = TransferSizes(1, tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).blockBytes), + supportsPutFull = TransferSizes(1, tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).blockBytes), + supportsPutPartial = TransferSizes(1, tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).blockBytes))), beatBytes = params.beatBytes)).toSeq) mmioPortParamsOpt.map { params => - sbus.coupleTo(s"port_named_$portName") { + tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).coupleTo(s"port_named_$portName") { (mmioTLNode := TLBuffer() := TLSourceShrinker(1 << params.idBits) - := TLWidthWidget(sbus.beatBytes) + := TLWidthWidget(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).beatBytes) := _ ) } } @@ -210,7 +210,7 @@ trait CanHaveSlaveTLPort { this: BaseSubsystem => sourceId = IdRange(0, 1 << params.idBits))))).toSeq) slavePortParamsOpt.map { params => - sbus.coupleFrom(s"port_named_$portName") { + tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).coupleFrom(s"port_named_$portName") { ( _ := TLSourceShrinker(1 << params.sourceBits) := TLWidthWidget(params.beatBytes)